xref: /openbmc/linux/drivers/gpu/drm/bridge/tc358768.c (revision 2755e375)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  *  Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com
4  *  Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
5  */
6 
7 #include <linux/clk.h>
8 #include <linux/device.h>
9 #include <linux/gpio/consumer.h>
10 #include <linux/i2c.h>
11 #include <linux/kernel.h>
12 #include <linux/media-bus-format.h>
13 #include <linux/minmax.h>
14 #include <linux/module.h>
15 #include <linux/regmap.h>
16 #include <linux/regulator/consumer.h>
17 #include <linux/slab.h>
18 #include <linux/units.h>
19 
20 #include <drm/drm_atomic_helper.h>
21 #include <drm/drm_drv.h>
22 #include <drm/drm_mipi_dsi.h>
23 #include <drm/drm_of.h>
24 #include <drm/drm_panel.h>
25 #include <video/mipi_display.h>
26 #include <video/videomode.h>
27 
28 /* Global (16-bit addressable) */
29 #define TC358768_CHIPID			0x0000
30 #define TC358768_SYSCTL			0x0002
31 #define TC358768_CONFCTL		0x0004
32 #define TC358768_VSDLY			0x0006
33 #define TC358768_DATAFMT		0x0008
34 #define TC358768_GPIOEN			0x000E
35 #define TC358768_GPIODIR		0x0010
36 #define TC358768_GPIOIN			0x0012
37 #define TC358768_GPIOOUT		0x0014
38 #define TC358768_PLLCTL0		0x0016
39 #define TC358768_PLLCTL1		0x0018
40 #define TC358768_CMDBYTE		0x0022
41 #define TC358768_PP_MISC		0x0032
42 #define TC358768_DSITX_DT		0x0050
43 #define TC358768_FIFOSTATUS		0x00F8
44 
45 /* Debug (16-bit addressable) */
46 #define TC358768_VBUFCTRL		0x00E0
47 #define TC358768_DBG_WIDTH		0x00E2
48 #define TC358768_DBG_VBLANK		0x00E4
49 #define TC358768_DBG_DATA		0x00E8
50 
51 /* TX PHY (32-bit addressable) */
52 #define TC358768_CLW_DPHYCONTTX		0x0100
53 #define TC358768_D0W_DPHYCONTTX		0x0104
54 #define TC358768_D1W_DPHYCONTTX		0x0108
55 #define TC358768_D2W_DPHYCONTTX		0x010C
56 #define TC358768_D3W_DPHYCONTTX		0x0110
57 #define TC358768_CLW_CNTRL		0x0140
58 #define TC358768_D0W_CNTRL		0x0144
59 #define TC358768_D1W_CNTRL		0x0148
60 #define TC358768_D2W_CNTRL		0x014C
61 #define TC358768_D3W_CNTRL		0x0150
62 
63 /* TX PPI (32-bit addressable) */
64 #define TC358768_STARTCNTRL		0x0204
65 #define TC358768_DSITXSTATUS		0x0208
66 #define TC358768_LINEINITCNT		0x0210
67 #define TC358768_LPTXTIMECNT		0x0214
68 #define TC358768_TCLK_HEADERCNT		0x0218
69 #define TC358768_TCLK_TRAILCNT		0x021C
70 #define TC358768_THS_HEADERCNT		0x0220
71 #define TC358768_TWAKEUP		0x0224
72 #define TC358768_TCLK_POSTCNT		0x0228
73 #define TC358768_THS_TRAILCNT		0x022C
74 #define TC358768_HSTXVREGCNT		0x0230
75 #define TC358768_HSTXVREGEN		0x0234
76 #define TC358768_TXOPTIONCNTRL		0x0238
77 #define TC358768_BTACNTRL1		0x023C
78 
79 /* TX CTRL (32-bit addressable) */
80 #define TC358768_DSI_CONTROL		0x040C
81 #define TC358768_DSI_STATUS		0x0410
82 #define TC358768_DSI_INT		0x0414
83 #define TC358768_DSI_INT_ENA		0x0418
84 #define TC358768_DSICMD_RDFIFO		0x0430
85 #define TC358768_DSI_ACKERR		0x0434
86 #define TC358768_DSI_ACKERR_INTENA	0x0438
87 #define TC358768_DSI_ACKERR_HALT	0x043c
88 #define TC358768_DSI_RXERR		0x0440
89 #define TC358768_DSI_RXERR_INTENA	0x0444
90 #define TC358768_DSI_RXERR_HALT		0x0448
91 #define TC358768_DSI_ERR		0x044C
92 #define TC358768_DSI_ERR_INTENA		0x0450
93 #define TC358768_DSI_ERR_HALT		0x0454
94 #define TC358768_DSI_CONFW		0x0500
95 #define TC358768_DSI_LPCMD		0x0500
96 #define TC358768_DSI_RESET		0x0504
97 #define TC358768_DSI_INT_CLR		0x050C
98 #define TC358768_DSI_START		0x0518
99 
100 /* DSITX CTRL (16-bit addressable) */
101 #define TC358768_DSICMD_TX		0x0600
102 #define TC358768_DSICMD_TYPE		0x0602
103 #define TC358768_DSICMD_WC		0x0604
104 #define TC358768_DSICMD_WD0		0x0610
105 #define TC358768_DSICMD_WD1		0x0612
106 #define TC358768_DSICMD_WD2		0x0614
107 #define TC358768_DSICMD_WD3		0x0616
108 #define TC358768_DSI_EVENT		0x0620
109 #define TC358768_DSI_VSW		0x0622
110 #define TC358768_DSI_VBPR		0x0624
111 #define TC358768_DSI_VACT		0x0626
112 #define TC358768_DSI_HSW		0x0628
113 #define TC358768_DSI_HBPR		0x062A
114 #define TC358768_DSI_HACT		0x062C
115 
116 /* TC358768_DSI_CONTROL (0x040C) register */
117 #define TC358768_DSI_CONTROL_DIS_MODE	BIT(15)
118 #define TC358768_DSI_CONTROL_TXMD	BIT(7)
119 #define TC358768_DSI_CONTROL_HSCKMD	BIT(5)
120 #define TC358768_DSI_CONTROL_EOTDIS	BIT(0)
121 
122 /* TC358768_DSI_CONFW (0x0500) register */
123 #define TC358768_DSI_CONFW_MODE_SET	(5 << 29)
124 #define TC358768_DSI_CONFW_MODE_CLR	(6 << 29)
125 #define TC358768_DSI_CONFW_ADDR_DSI_CONTROL	(0x3 << 24)
126 
127 static const char * const tc358768_supplies[] = {
128 	"vddc", "vddmipi", "vddio"
129 };
130 
131 struct tc358768_dsi_output {
132 	struct mipi_dsi_device *dev;
133 	struct drm_panel *panel;
134 	struct drm_bridge *bridge;
135 };
136 
137 struct tc358768_priv {
138 	struct device *dev;
139 	struct regmap *regmap;
140 	struct gpio_desc *reset_gpio;
141 	struct regulator_bulk_data supplies[ARRAY_SIZE(tc358768_supplies)];
142 	struct clk *refclk;
143 	int enabled;
144 	int error;
145 
146 	struct mipi_dsi_host dsi_host;
147 	struct drm_bridge bridge;
148 	struct tc358768_dsi_output output;
149 
150 	u32 pd_lines; /* number of Parallel Port Input Data Lines */
151 	u32 dsi_lanes; /* number of DSI Lanes */
152 	u32 dsi_bpp; /* number of Bits Per Pixel over DSI */
153 
154 	/* Parameters for PLL programming */
155 	u32 fbd;	/* PLL feedback divider */
156 	u32 prd;	/* PLL input divider */
157 	u32 frs;	/* PLL Freqency range for HSCK (post divider) */
158 
159 	u32 dsiclk;	/* pll_clk / 2 */
160 };
161 
dsi_host_to_tc358768(struct mipi_dsi_host * host)162 static inline struct tc358768_priv *dsi_host_to_tc358768(struct mipi_dsi_host
163 							 *host)
164 {
165 	return container_of(host, struct tc358768_priv, dsi_host);
166 }
167 
bridge_to_tc358768(struct drm_bridge * bridge)168 static inline struct tc358768_priv *bridge_to_tc358768(struct drm_bridge
169 						       *bridge)
170 {
171 	return container_of(bridge, struct tc358768_priv, bridge);
172 }
173 
tc358768_clear_error(struct tc358768_priv * priv)174 static int tc358768_clear_error(struct tc358768_priv *priv)
175 {
176 	int ret = priv->error;
177 
178 	priv->error = 0;
179 	return ret;
180 }
181 
tc358768_write(struct tc358768_priv * priv,u32 reg,u32 val)182 static void tc358768_write(struct tc358768_priv *priv, u32 reg, u32 val)
183 {
184 	/* work around https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */
185 	int tmpval = val;
186 	size_t count = 2;
187 
188 	if (priv->error)
189 		return;
190 
191 	/* 16-bit register? */
192 	if (reg < 0x100 || reg >= 0x600)
193 		count = 1;
194 
195 	priv->error = regmap_bulk_write(priv->regmap, reg, &tmpval, count);
196 }
197 
tc358768_read(struct tc358768_priv * priv,u32 reg,u32 * val)198 static void tc358768_read(struct tc358768_priv *priv, u32 reg, u32 *val)
199 {
200 	size_t count = 2;
201 
202 	if (priv->error)
203 		return;
204 
205 	/* 16-bit register? */
206 	if (reg < 0x100 || reg >= 0x600) {
207 		*val = 0;
208 		count = 1;
209 	}
210 
211 	priv->error = regmap_bulk_read(priv->regmap, reg, val, count);
212 }
213 
tc358768_update_bits(struct tc358768_priv * priv,u32 reg,u32 mask,u32 val)214 static void tc358768_update_bits(struct tc358768_priv *priv, u32 reg, u32 mask,
215 				 u32 val)
216 {
217 	u32 tmp, orig;
218 
219 	tc358768_read(priv, reg, &orig);
220 
221 	if (priv->error)
222 		return;
223 
224 	tmp = orig & ~mask;
225 	tmp |= val & mask;
226 	if (tmp != orig)
227 		tc358768_write(priv, reg, tmp);
228 }
229 
tc358768_sw_reset(struct tc358768_priv * priv)230 static int tc358768_sw_reset(struct tc358768_priv *priv)
231 {
232 	/* Assert Reset */
233 	tc358768_write(priv, TC358768_SYSCTL, 1);
234 	/* Release Reset, Exit Sleep */
235 	tc358768_write(priv, TC358768_SYSCTL, 0);
236 
237 	return tc358768_clear_error(priv);
238 }
239 
tc358768_hw_enable(struct tc358768_priv * priv)240 static void tc358768_hw_enable(struct tc358768_priv *priv)
241 {
242 	int ret;
243 
244 	if (priv->enabled)
245 		return;
246 
247 	ret = clk_prepare_enable(priv->refclk);
248 	if (ret < 0)
249 		dev_err(priv->dev, "error enabling refclk (%d)\n", ret);
250 
251 	ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies);
252 	if (ret < 0)
253 		dev_err(priv->dev, "error enabling regulators (%d)\n", ret);
254 
255 	if (priv->reset_gpio)
256 		usleep_range(200, 300);
257 
258 	/*
259 	 * The RESX is active low (GPIO_ACTIVE_LOW).
260 	 * DEASSERT (value = 0) the reset_gpio to enable the chip
261 	 */
262 	gpiod_set_value_cansleep(priv->reset_gpio, 0);
263 
264 	/* wait for encoder clocks to stabilize */
265 	usleep_range(1000, 2000);
266 
267 	priv->enabled = true;
268 }
269 
tc358768_hw_disable(struct tc358768_priv * priv)270 static void tc358768_hw_disable(struct tc358768_priv *priv)
271 {
272 	int ret;
273 
274 	if (!priv->enabled)
275 		return;
276 
277 	/*
278 	 * The RESX is active low (GPIO_ACTIVE_LOW).
279 	 * ASSERT (value = 1) the reset_gpio to disable the chip
280 	 */
281 	gpiod_set_value_cansleep(priv->reset_gpio, 1);
282 
283 	ret = regulator_bulk_disable(ARRAY_SIZE(priv->supplies),
284 				     priv->supplies);
285 	if (ret < 0)
286 		dev_err(priv->dev, "error disabling regulators (%d)\n", ret);
287 
288 	clk_disable_unprepare(priv->refclk);
289 
290 	priv->enabled = false;
291 }
292 
tc358768_pll_to_pclk(struct tc358768_priv * priv,u32 pll_clk)293 static u32 tc358768_pll_to_pclk(struct tc358768_priv *priv, u32 pll_clk)
294 {
295 	return (u32)div_u64((u64)pll_clk * priv->dsi_lanes, priv->dsi_bpp);
296 }
297 
tc358768_pclk_to_pll(struct tc358768_priv * priv,u32 pclk)298 static u32 tc358768_pclk_to_pll(struct tc358768_priv *priv, u32 pclk)
299 {
300 	return (u32)div_u64((u64)pclk * priv->dsi_bpp, priv->dsi_lanes);
301 }
302 
tc358768_calc_pll(struct tc358768_priv * priv,const struct drm_display_mode * mode,bool verify_only)303 static int tc358768_calc_pll(struct tc358768_priv *priv,
304 			     const struct drm_display_mode *mode,
305 			     bool verify_only)
306 {
307 	static const u32 frs_limits[] = {
308 		1000000000,
309 		500000000,
310 		250000000,
311 		125000000,
312 		62500000
313 	};
314 	unsigned long refclk;
315 	u32 prd, target_pll, i, max_pll, min_pll;
316 	u32 frs, best_diff, best_pll, best_prd, best_fbd;
317 
318 	target_pll = tc358768_pclk_to_pll(priv, mode->clock * 1000);
319 
320 	/* pll_clk = RefClk * [(FBD + 1)/ (PRD + 1)] * [1 / (2^FRS)] */
321 
322 	for (i = 0; i < ARRAY_SIZE(frs_limits); i++)
323 		if (target_pll >= frs_limits[i])
324 			break;
325 
326 	if (i == ARRAY_SIZE(frs_limits) || i == 0)
327 		return -EINVAL;
328 
329 	frs = i - 1;
330 	max_pll = frs_limits[i - 1];
331 	min_pll = frs_limits[i];
332 
333 	refclk = clk_get_rate(priv->refclk);
334 
335 	best_diff = UINT_MAX;
336 	best_pll = 0;
337 	best_prd = 0;
338 	best_fbd = 0;
339 
340 	for (prd = 0; prd < 16; ++prd) {
341 		u32 divisor = (prd + 1) * (1 << frs);
342 		u32 fbd;
343 
344 		for (fbd = 0; fbd < 512; ++fbd) {
345 			u32 pll, diff, pll_in;
346 
347 			pll = (u32)div_u64((u64)refclk * (fbd + 1), divisor);
348 
349 			if (pll >= max_pll || pll < min_pll)
350 				continue;
351 
352 			pll_in = (u32)div_u64((u64)refclk, prd + 1);
353 			if (pll_in < 4000000)
354 				continue;
355 
356 			diff = max(pll, target_pll) - min(pll, target_pll);
357 
358 			if (diff < best_diff) {
359 				best_diff = diff;
360 				best_pll = pll;
361 				best_prd = prd;
362 				best_fbd = fbd;
363 
364 				if (best_diff == 0)
365 					goto found;
366 			}
367 		}
368 	}
369 
370 	if (best_diff == UINT_MAX) {
371 		dev_err(priv->dev, "could not find suitable PLL setup\n");
372 		return -EINVAL;
373 	}
374 
375 found:
376 	if (verify_only)
377 		return 0;
378 
379 	priv->fbd = best_fbd;
380 	priv->prd = best_prd;
381 	priv->frs = frs;
382 	priv->dsiclk = best_pll / 2;
383 
384 	return 0;
385 }
386 
tc358768_dsi_host_attach(struct mipi_dsi_host * host,struct mipi_dsi_device * dev)387 static int tc358768_dsi_host_attach(struct mipi_dsi_host *host,
388 				    struct mipi_dsi_device *dev)
389 {
390 	struct tc358768_priv *priv = dsi_host_to_tc358768(host);
391 	struct drm_bridge *bridge;
392 	struct drm_panel *panel;
393 	struct device_node *ep;
394 	int ret;
395 
396 	if (dev->lanes > 4) {
397 		dev_err(priv->dev, "unsupported number of data lanes(%u)\n",
398 			dev->lanes);
399 		return -EINVAL;
400 	}
401 
402 	/*
403 	 * tc358768 supports both Video and Pulse mode, but the driver only
404 	 * implements Video (event) mode currently
405 	 */
406 	if (!(dev->mode_flags & MIPI_DSI_MODE_VIDEO)) {
407 		dev_err(priv->dev, "Only MIPI_DSI_MODE_VIDEO is supported\n");
408 		return -ENOTSUPP;
409 	}
410 
411 	/*
412 	 * tc358768 supports RGB888, RGB666, RGB666_PACKED and RGB565, but only
413 	 * RGB888 is verified.
414 	 */
415 	if (dev->format != MIPI_DSI_FMT_RGB888) {
416 		dev_warn(priv->dev, "Only MIPI_DSI_FMT_RGB888 tested!\n");
417 		return -ENOTSUPP;
418 	}
419 
420 	ret = drm_of_find_panel_or_bridge(host->dev->of_node, 1, 0, &panel,
421 					  &bridge);
422 	if (ret)
423 		return ret;
424 
425 	if (panel) {
426 		bridge = drm_panel_bridge_add_typed(panel,
427 						    DRM_MODE_CONNECTOR_DSI);
428 		if (IS_ERR(bridge))
429 			return PTR_ERR(bridge);
430 	}
431 
432 	priv->output.dev = dev;
433 	priv->output.bridge = bridge;
434 	priv->output.panel = panel;
435 
436 	priv->dsi_lanes = dev->lanes;
437 	priv->dsi_bpp = mipi_dsi_pixel_format_to_bpp(dev->format);
438 
439 	/* get input ep (port0/endpoint0) */
440 	ret = -EINVAL;
441 	ep = of_graph_get_endpoint_by_regs(host->dev->of_node, 0, 0);
442 	if (ep) {
443 		ret = of_property_read_u32(ep, "data-lines", &priv->pd_lines);
444 
445 		of_node_put(ep);
446 	}
447 
448 	if (ret)
449 		priv->pd_lines = priv->dsi_bpp;
450 
451 	drm_bridge_add(&priv->bridge);
452 
453 	return 0;
454 }
455 
tc358768_dsi_host_detach(struct mipi_dsi_host * host,struct mipi_dsi_device * dev)456 static int tc358768_dsi_host_detach(struct mipi_dsi_host *host,
457 				    struct mipi_dsi_device *dev)
458 {
459 	struct tc358768_priv *priv = dsi_host_to_tc358768(host);
460 
461 	drm_bridge_remove(&priv->bridge);
462 	if (priv->output.panel)
463 		drm_panel_bridge_remove(priv->output.bridge);
464 
465 	return 0;
466 }
467 
tc358768_dsi_host_transfer(struct mipi_dsi_host * host,const struct mipi_dsi_msg * msg)468 static ssize_t tc358768_dsi_host_transfer(struct mipi_dsi_host *host,
469 					  const struct mipi_dsi_msg *msg)
470 {
471 	struct tc358768_priv *priv = dsi_host_to_tc358768(host);
472 	struct mipi_dsi_packet packet;
473 	int ret;
474 
475 	if (!priv->enabled) {
476 		dev_err(priv->dev, "Bridge is not enabled\n");
477 		return -ENODEV;
478 	}
479 
480 	if (msg->rx_len) {
481 		dev_warn(priv->dev, "MIPI rx is not supported\n");
482 		return -ENOTSUPP;
483 	}
484 
485 	if (msg->tx_len > 8) {
486 		dev_warn(priv->dev, "Maximum 8 byte MIPI tx is supported\n");
487 		return -ENOTSUPP;
488 	}
489 
490 	ret = mipi_dsi_create_packet(&packet, msg);
491 	if (ret)
492 		return ret;
493 
494 	if (mipi_dsi_packet_format_is_short(msg->type)) {
495 		tc358768_write(priv, TC358768_DSICMD_TYPE,
496 			       (0x10 << 8) | (packet.header[0] & 0x3f));
497 		tc358768_write(priv, TC358768_DSICMD_WC, 0);
498 		tc358768_write(priv, TC358768_DSICMD_WD0,
499 			       (packet.header[2] << 8) | packet.header[1]);
500 	} else {
501 		int i;
502 
503 		tc358768_write(priv, TC358768_DSICMD_TYPE,
504 			       (0x40 << 8) | (packet.header[0] & 0x3f));
505 		tc358768_write(priv, TC358768_DSICMD_WC, packet.payload_length);
506 		for (i = 0; i < packet.payload_length; i += 2) {
507 			u16 val = packet.payload[i];
508 
509 			if (i + 1 < packet.payload_length)
510 				val |= packet.payload[i + 1] << 8;
511 
512 			tc358768_write(priv, TC358768_DSICMD_WD0 + i, val);
513 		}
514 	}
515 
516 	/* start transfer */
517 	tc358768_write(priv, TC358768_DSICMD_TX, 1);
518 
519 	ret = tc358768_clear_error(priv);
520 	if (ret)
521 		dev_warn(priv->dev, "Software disable failed: %d\n", ret);
522 	else
523 		ret = packet.size;
524 
525 	return ret;
526 }
527 
528 static const struct mipi_dsi_host_ops tc358768_dsi_host_ops = {
529 	.attach = tc358768_dsi_host_attach,
530 	.detach = tc358768_dsi_host_detach,
531 	.transfer = tc358768_dsi_host_transfer,
532 };
533 
tc358768_bridge_attach(struct drm_bridge * bridge,enum drm_bridge_attach_flags flags)534 static int tc358768_bridge_attach(struct drm_bridge *bridge,
535 				  enum drm_bridge_attach_flags flags)
536 {
537 	struct tc358768_priv *priv = bridge_to_tc358768(bridge);
538 
539 	if (!drm_core_check_feature(bridge->dev, DRIVER_ATOMIC)) {
540 		dev_err(priv->dev, "needs atomic updates support\n");
541 		return -ENOTSUPP;
542 	}
543 
544 	return drm_bridge_attach(bridge->encoder, priv->output.bridge, bridge,
545 				 flags);
546 }
547 
548 static enum drm_mode_status
tc358768_bridge_mode_valid(struct drm_bridge * bridge,const struct drm_display_info * info,const struct drm_display_mode * mode)549 tc358768_bridge_mode_valid(struct drm_bridge *bridge,
550 			   const struct drm_display_info *info,
551 			   const struct drm_display_mode *mode)
552 {
553 	struct tc358768_priv *priv = bridge_to_tc358768(bridge);
554 
555 	if (tc358768_calc_pll(priv, mode, true))
556 		return MODE_CLOCK_RANGE;
557 
558 	return MODE_OK;
559 }
560 
tc358768_bridge_disable(struct drm_bridge * bridge)561 static void tc358768_bridge_disable(struct drm_bridge *bridge)
562 {
563 	struct tc358768_priv *priv = bridge_to_tc358768(bridge);
564 	int ret;
565 
566 	/* set FrmStop */
567 	tc358768_update_bits(priv, TC358768_PP_MISC, BIT(15), BIT(15));
568 
569 	/* wait at least for one frame */
570 	msleep(50);
571 
572 	/* clear PP_en */
573 	tc358768_update_bits(priv, TC358768_CONFCTL, BIT(6), 0);
574 
575 	/* set RstPtr */
576 	tc358768_update_bits(priv, TC358768_PP_MISC, BIT(14), BIT(14));
577 
578 	ret = tc358768_clear_error(priv);
579 	if (ret)
580 		dev_warn(priv->dev, "Software disable failed: %d\n", ret);
581 }
582 
tc358768_bridge_post_disable(struct drm_bridge * bridge)583 static void tc358768_bridge_post_disable(struct drm_bridge *bridge)
584 {
585 	struct tc358768_priv *priv = bridge_to_tc358768(bridge);
586 
587 	tc358768_hw_disable(priv);
588 }
589 
tc358768_setup_pll(struct tc358768_priv * priv,const struct drm_display_mode * mode)590 static int tc358768_setup_pll(struct tc358768_priv *priv,
591 			      const struct drm_display_mode *mode)
592 {
593 	u32 fbd, prd, frs;
594 	int ret;
595 
596 	ret = tc358768_calc_pll(priv, mode, false);
597 	if (ret) {
598 		dev_err(priv->dev, "PLL calculation failed: %d\n", ret);
599 		return ret;
600 	}
601 
602 	fbd = priv->fbd;
603 	prd = priv->prd;
604 	frs = priv->frs;
605 
606 	dev_dbg(priv->dev, "PLL: refclk %lu, fbd %u, prd %u, frs %u\n",
607 		clk_get_rate(priv->refclk), fbd, prd, frs);
608 	dev_dbg(priv->dev, "PLL: pll_clk: %u, DSIClk %u, HSByteClk %u\n",
609 		priv->dsiclk * 2, priv->dsiclk, priv->dsiclk / 4);
610 	dev_dbg(priv->dev, "PLL: pclk %u (panel: %u)\n",
611 		tc358768_pll_to_pclk(priv, priv->dsiclk * 2),
612 		mode->clock * 1000);
613 
614 	/* PRD[15:12] FBD[8:0] */
615 	tc358768_write(priv, TC358768_PLLCTL0, (prd << 12) | fbd);
616 
617 	/* FRS[11:10] LBWS[9:8] CKEN[4] RESETB[1] EN[0] */
618 	tc358768_write(priv, TC358768_PLLCTL1,
619 		       (frs << 10) | (0x2 << 8) | BIT(1) | BIT(0));
620 
621 	/* wait for lock */
622 	usleep_range(1000, 2000);
623 
624 	/* FRS[11:10] LBWS[9:8] CKEN[4] PLL_CKEN[4] RESETB[1] EN[0] */
625 	tc358768_write(priv, TC358768_PLLCTL1,
626 		       (frs << 10) | (0x2 << 8) | BIT(4) | BIT(1) | BIT(0));
627 
628 	return tc358768_clear_error(priv);
629 }
630 
tc358768_ns_to_cnt(u32 ns,u32 period_ps)631 static u32 tc358768_ns_to_cnt(u32 ns, u32 period_ps)
632 {
633 	return DIV_ROUND_UP(ns * 1000, period_ps);
634 }
635 
tc358768_ps_to_ns(u32 ps)636 static u32 tc358768_ps_to_ns(u32 ps)
637 {
638 	return ps / 1000;
639 }
640 
tc358768_bridge_pre_enable(struct drm_bridge * bridge)641 static void tc358768_bridge_pre_enable(struct drm_bridge *bridge)
642 {
643 	struct tc358768_priv *priv = bridge_to_tc358768(bridge);
644 	struct mipi_dsi_device *dsi_dev = priv->output.dev;
645 	unsigned long mode_flags = dsi_dev->mode_flags;
646 	u32 val, val2, lptxcnt, hact, data_type;
647 	s32 raw_val;
648 	const struct drm_display_mode *mode;
649 	u32 hsbyteclk_ps, dsiclk_ps, ui_ps;
650 	u32 dsiclk, hsbyteclk, video_start;
651 	const u32 internal_delay = 40;
652 	int ret, i;
653 	struct videomode vm;
654 	struct device *dev = priv->dev;
655 
656 	if (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) {
657 		dev_warn_once(dev, "Non-continuous mode unimplemented, falling back to continuous\n");
658 		mode_flags &= ~MIPI_DSI_CLOCK_NON_CONTINUOUS;
659 	}
660 
661 	tc358768_hw_enable(priv);
662 
663 	ret = tc358768_sw_reset(priv);
664 	if (ret) {
665 		dev_err(dev, "Software reset failed: %d\n", ret);
666 		tc358768_hw_disable(priv);
667 		return;
668 	}
669 
670 	mode = &bridge->encoder->crtc->state->adjusted_mode;
671 	ret = tc358768_setup_pll(priv, mode);
672 	if (ret) {
673 		dev_err(dev, "PLL setup failed: %d\n", ret);
674 		tc358768_hw_disable(priv);
675 		return;
676 	}
677 
678 	drm_display_mode_to_videomode(mode, &vm);
679 
680 	dsiclk = priv->dsiclk;
681 	hsbyteclk = dsiclk / 4;
682 
683 	/* Data Format Control Register */
684 	val = BIT(2) | BIT(1) | BIT(0); /* rdswap_en | dsitx_en | txdt_en */
685 	switch (dsi_dev->format) {
686 	case MIPI_DSI_FMT_RGB888:
687 		val |= (0x3 << 4);
688 		hact = vm.hactive * 3;
689 		video_start = (vm.hsync_len + vm.hback_porch) * 3;
690 		data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24;
691 		break;
692 	case MIPI_DSI_FMT_RGB666:
693 		val |= (0x4 << 4);
694 		hact = vm.hactive * 3;
695 		video_start = (vm.hsync_len + vm.hback_porch) * 3;
696 		data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18;
697 		break;
698 
699 	case MIPI_DSI_FMT_RGB666_PACKED:
700 		val |= (0x4 << 4) | BIT(3);
701 		hact = vm.hactive * 18 / 8;
702 		video_start = (vm.hsync_len + vm.hback_porch) * 18 / 8;
703 		data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
704 		break;
705 
706 	case MIPI_DSI_FMT_RGB565:
707 		val |= (0x5 << 4);
708 		hact = vm.hactive * 2;
709 		video_start = (vm.hsync_len + vm.hback_porch) * 2;
710 		data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16;
711 		break;
712 	default:
713 		dev_err(dev, "Invalid data format (%u)\n",
714 			dsi_dev->format);
715 		tc358768_hw_disable(priv);
716 		return;
717 	}
718 
719 	/* VSDly[9:0] */
720 	video_start = max(video_start, internal_delay + 1) - internal_delay;
721 	tc358768_write(priv, TC358768_VSDLY, video_start);
722 
723 	tc358768_write(priv, TC358768_DATAFMT, val);
724 	tc358768_write(priv, TC358768_DSITX_DT, data_type);
725 
726 	/* Enable D-PHY (HiZ->LP11) */
727 	tc358768_write(priv, TC358768_CLW_CNTRL, 0x0000);
728 	/* Enable lanes */
729 	for (i = 0; i < dsi_dev->lanes; i++)
730 		tc358768_write(priv, TC358768_D0W_CNTRL + i * 4, 0x0000);
731 
732 	/* DSI Timings */
733 	hsbyteclk_ps = (u32)div_u64(PICO, hsbyteclk);
734 	dsiclk_ps = (u32)div_u64(PICO, dsiclk);
735 	ui_ps = dsiclk_ps / 2;
736 	dev_dbg(dev, "dsiclk: %u ps, ui %u ps, hsbyteclk %u ps\n", dsiclk_ps,
737 		ui_ps, hsbyteclk_ps);
738 
739 	/* LP11 > 100us for D-PHY Rx Init */
740 	val = tc358768_ns_to_cnt(100 * 1000, hsbyteclk_ps) - 1;
741 	dev_dbg(dev, "LINEINITCNT: %u\n", val);
742 	tc358768_write(priv, TC358768_LINEINITCNT, val);
743 
744 	/* LPTimeCnt > 50ns */
745 	val = tc358768_ns_to_cnt(50, hsbyteclk_ps) - 1;
746 	lptxcnt = val;
747 	dev_dbg(dev, "LPTXTIMECNT: %u\n", val);
748 	tc358768_write(priv, TC358768_LPTXTIMECNT, val);
749 
750 	/* 38ns < TCLK_PREPARE < 95ns */
751 	val = tc358768_ns_to_cnt(65, hsbyteclk_ps) - 1;
752 	dev_dbg(dev, "TCLK_PREPARECNT %u\n", val);
753 	/* TCLK_PREPARE + TCLK_ZERO > 300ns */
754 	val2 = tc358768_ns_to_cnt(300 - tc358768_ps_to_ns(2 * ui_ps),
755 				  hsbyteclk_ps) - 2;
756 	dev_dbg(dev, "TCLK_ZEROCNT %u\n", val2);
757 	val |= val2 << 8;
758 	tc358768_write(priv, TC358768_TCLK_HEADERCNT, val);
759 
760 	/* TCLK_TRAIL > 60ns AND TEOT <= 105 ns + 12*UI */
761 	raw_val = tc358768_ns_to_cnt(60 + tc358768_ps_to_ns(2 * ui_ps), hsbyteclk_ps) - 5;
762 	val = clamp(raw_val, 0, 127);
763 	dev_dbg(dev, "TCLK_TRAILCNT: %u\n", val);
764 	tc358768_write(priv, TC358768_TCLK_TRAILCNT, val);
765 
766 	/* 40ns + 4*UI < THS_PREPARE < 85ns + 6*UI */
767 	val = 50 + tc358768_ps_to_ns(4 * ui_ps);
768 	val = tc358768_ns_to_cnt(val, hsbyteclk_ps) - 1;
769 	dev_dbg(dev, "THS_PREPARECNT %u\n", val);
770 	/* THS_PREPARE + THS_ZERO > 145ns + 10*UI */
771 	raw_val = tc358768_ns_to_cnt(145 - tc358768_ps_to_ns(3 * ui_ps), hsbyteclk_ps) - 10;
772 	val2 = clamp(raw_val, 0, 127);
773 	dev_dbg(dev, "THS_ZEROCNT %u\n", val2);
774 	val |= val2 << 8;
775 	tc358768_write(priv, TC358768_THS_HEADERCNT, val);
776 
777 	/* TWAKEUP > 1ms in lptxcnt steps */
778 	val = tc358768_ns_to_cnt(1020000, hsbyteclk_ps);
779 	val = val / (lptxcnt + 1) - 1;
780 	dev_dbg(dev, "TWAKEUP: %u\n", val);
781 	tc358768_write(priv, TC358768_TWAKEUP, val);
782 
783 	/* TCLK_POSTCNT > 60ns + 52*UI */
784 	val = tc358768_ns_to_cnt(60 + tc358768_ps_to_ns(52 * ui_ps),
785 				 hsbyteclk_ps) - 3;
786 	dev_dbg(dev, "TCLK_POSTCNT: %u\n", val);
787 	tc358768_write(priv, TC358768_TCLK_POSTCNT, val);
788 
789 	/* max(60ns + 4*UI, 8*UI) < THS_TRAILCNT < 105ns + 12*UI */
790 	raw_val = tc358768_ns_to_cnt(60 + tc358768_ps_to_ns(18 * ui_ps),
791 				     hsbyteclk_ps) - 4;
792 	val = clamp(raw_val, 0, 15);
793 	dev_dbg(dev, "THS_TRAILCNT: %u\n", val);
794 	tc358768_write(priv, TC358768_THS_TRAILCNT, val);
795 
796 	val = BIT(0);
797 	for (i = 0; i < dsi_dev->lanes; i++)
798 		val |= BIT(i + 1);
799 	tc358768_write(priv, TC358768_HSTXVREGEN, val);
800 
801 	tc358768_write(priv, TC358768_TXOPTIONCNTRL,
802 		       (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) ? 0 : BIT(0));
803 
804 	/* TXTAGOCNT[26:16] RXTASURECNT[10:0] */
805 	val = tc358768_ps_to_ns((lptxcnt + 1) * hsbyteclk_ps * 4);
806 	val = tc358768_ns_to_cnt(val, hsbyteclk_ps) / 4 - 1;
807 	dev_dbg(dev, "TXTAGOCNT: %u\n", val);
808 	val2 = tc358768_ns_to_cnt(tc358768_ps_to_ns((lptxcnt + 1) * hsbyteclk_ps),
809 				  hsbyteclk_ps) - 2;
810 	dev_dbg(dev, "RXTASURECNT: %u\n", val2);
811 	val = val << 16 | val2;
812 	tc358768_write(priv, TC358768_BTACNTRL1, val);
813 
814 	/* START[0] */
815 	tc358768_write(priv, TC358768_STARTCNTRL, 1);
816 
817 	if (dsi_dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
818 		/* Set pulse mode */
819 		tc358768_write(priv, TC358768_DSI_EVENT, 0);
820 
821 		/* vact */
822 		tc358768_write(priv, TC358768_DSI_VACT, vm.vactive);
823 
824 		/* vsw */
825 		tc358768_write(priv, TC358768_DSI_VSW, vm.vsync_len);
826 
827 		/* vbp */
828 		tc358768_write(priv, TC358768_DSI_VBPR, vm.vback_porch);
829 
830 		/* hsw * byteclk * ndl / pclk */
831 		val = (u32)div_u64(vm.hsync_len *
832 				   (u64)hsbyteclk * priv->dsi_lanes,
833 				   vm.pixelclock);
834 		tc358768_write(priv, TC358768_DSI_HSW, val);
835 
836 		/* hbp * byteclk * ndl / pclk */
837 		val = (u32)div_u64(vm.hback_porch *
838 				   (u64)hsbyteclk * priv->dsi_lanes,
839 				   vm.pixelclock);
840 		tc358768_write(priv, TC358768_DSI_HBPR, val);
841 	} else {
842 		/* Set event mode */
843 		tc358768_write(priv, TC358768_DSI_EVENT, 1);
844 
845 		/* vact */
846 		tc358768_write(priv, TC358768_DSI_VACT, vm.vactive);
847 
848 		/* vsw (+ vbp) */
849 		tc358768_write(priv, TC358768_DSI_VSW,
850 			       vm.vsync_len + vm.vback_porch);
851 
852 		/* vbp (not used in event mode) */
853 		tc358768_write(priv, TC358768_DSI_VBPR, 0);
854 
855 		/* (hsw + hbp) * byteclk * ndl / pclk */
856 		val = (u32)div_u64((vm.hsync_len + vm.hback_porch) *
857 				   (u64)hsbyteclk * priv->dsi_lanes,
858 				   vm.pixelclock);
859 		tc358768_write(priv, TC358768_DSI_HSW, val);
860 
861 		/* hbp (not used in event mode) */
862 		tc358768_write(priv, TC358768_DSI_HBPR, 0);
863 	}
864 
865 	/* hact (bytes) */
866 	tc358768_write(priv, TC358768_DSI_HACT, hact);
867 
868 	/* VSYNC polarity */
869 	tc358768_update_bits(priv, TC358768_CONFCTL, BIT(5),
870 			     (mode->flags & DRM_MODE_FLAG_PVSYNC) ? BIT(5) : 0);
871 
872 	/* HSYNC polarity */
873 	tc358768_update_bits(priv, TC358768_PP_MISC, BIT(0),
874 			     (mode->flags & DRM_MODE_FLAG_PHSYNC) ? BIT(0) : 0);
875 
876 	/* Start DSI Tx */
877 	tc358768_write(priv, TC358768_DSI_START, 0x1);
878 
879 	/* Configure DSI_Control register */
880 	val = TC358768_DSI_CONFW_MODE_CLR | TC358768_DSI_CONFW_ADDR_DSI_CONTROL;
881 	val |= TC358768_DSI_CONTROL_TXMD | TC358768_DSI_CONTROL_HSCKMD |
882 	       0x3 << 1 | TC358768_DSI_CONTROL_EOTDIS;
883 	tc358768_write(priv, TC358768_DSI_CONFW, val);
884 
885 	val = TC358768_DSI_CONFW_MODE_SET | TC358768_DSI_CONFW_ADDR_DSI_CONTROL;
886 	val |= (dsi_dev->lanes - 1) << 1;
887 
888 	val |= TC358768_DSI_CONTROL_TXMD;
889 
890 	if (!(mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
891 		val |= TC358768_DSI_CONTROL_HSCKMD;
892 
893 	if (dsi_dev->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET)
894 		val |= TC358768_DSI_CONTROL_EOTDIS;
895 
896 	tc358768_write(priv, TC358768_DSI_CONFW, val);
897 
898 	val = TC358768_DSI_CONFW_MODE_CLR | TC358768_DSI_CONFW_ADDR_DSI_CONTROL;
899 	val |= TC358768_DSI_CONTROL_DIS_MODE; /* DSI mode */
900 	tc358768_write(priv, TC358768_DSI_CONFW, val);
901 
902 	ret = tc358768_clear_error(priv);
903 	if (ret) {
904 		dev_err(dev, "Bridge pre_enable failed: %d\n", ret);
905 		tc358768_bridge_disable(bridge);
906 		tc358768_bridge_post_disable(bridge);
907 	}
908 }
909 
tc358768_bridge_enable(struct drm_bridge * bridge)910 static void tc358768_bridge_enable(struct drm_bridge *bridge)
911 {
912 	struct tc358768_priv *priv = bridge_to_tc358768(bridge);
913 	int ret;
914 
915 	if (!priv->enabled) {
916 		dev_err(priv->dev, "Bridge is not enabled\n");
917 		return;
918 	}
919 
920 	/* clear FrmStop and RstPtr */
921 	tc358768_update_bits(priv, TC358768_PP_MISC, 0x3 << 14, 0);
922 
923 	/* set PP_en */
924 	tc358768_update_bits(priv, TC358768_CONFCTL, BIT(6), BIT(6));
925 
926 	ret = tc358768_clear_error(priv);
927 	if (ret) {
928 		dev_err(priv->dev, "Bridge enable failed: %d\n", ret);
929 		tc358768_bridge_disable(bridge);
930 		tc358768_bridge_post_disable(bridge);
931 	}
932 }
933 
934 #define MAX_INPUT_SEL_FORMATS	1
935 
936 static u32 *
tc358768_atomic_get_input_bus_fmts(struct drm_bridge * bridge,struct drm_bridge_state * bridge_state,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state,u32 output_fmt,unsigned int * num_input_fmts)937 tc358768_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
938 				   struct drm_bridge_state *bridge_state,
939 				   struct drm_crtc_state *crtc_state,
940 				   struct drm_connector_state *conn_state,
941 				   u32 output_fmt,
942 				   unsigned int *num_input_fmts)
943 {
944 	struct tc358768_priv *priv = bridge_to_tc358768(bridge);
945 	u32 *input_fmts;
946 
947 	*num_input_fmts = 0;
948 
949 	input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
950 			     GFP_KERNEL);
951 	if (!input_fmts)
952 		return NULL;
953 
954 	switch (priv->pd_lines) {
955 	case 16:
956 		input_fmts[0] = MEDIA_BUS_FMT_RGB565_1X16;
957 		break;
958 	case 18:
959 		input_fmts[0] = MEDIA_BUS_FMT_RGB666_1X18;
960 		break;
961 	default:
962 	case 24:
963 		input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
964 		break;
965 	}
966 
967 	*num_input_fmts = MAX_INPUT_SEL_FORMATS;
968 
969 	return input_fmts;
970 }
971 
972 static const struct drm_bridge_funcs tc358768_bridge_funcs = {
973 	.attach = tc358768_bridge_attach,
974 	.mode_valid = tc358768_bridge_mode_valid,
975 	.pre_enable = tc358768_bridge_pre_enable,
976 	.enable = tc358768_bridge_enable,
977 	.disable = tc358768_bridge_disable,
978 	.post_disable = tc358768_bridge_post_disable,
979 
980 	.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
981 	.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
982 	.atomic_reset = drm_atomic_helper_bridge_reset,
983 	.atomic_get_input_bus_fmts = tc358768_atomic_get_input_bus_fmts,
984 };
985 
986 static const struct drm_bridge_timings default_tc358768_timings = {
987 	.input_bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE
988 		 | DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE
989 		 | DRM_BUS_FLAG_DE_HIGH,
990 };
991 
tc358768_is_reserved_reg(unsigned int reg)992 static bool tc358768_is_reserved_reg(unsigned int reg)
993 {
994 	switch (reg) {
995 	case 0x114 ... 0x13f:
996 	case 0x200:
997 	case 0x20c:
998 	case 0x400 ... 0x408:
999 	case 0x41c ... 0x42f:
1000 		return true;
1001 	default:
1002 		return false;
1003 	}
1004 }
1005 
tc358768_writeable_reg(struct device * dev,unsigned int reg)1006 static bool tc358768_writeable_reg(struct device *dev, unsigned int reg)
1007 {
1008 	if (tc358768_is_reserved_reg(reg))
1009 		return false;
1010 
1011 	switch (reg) {
1012 	case TC358768_CHIPID:
1013 	case TC358768_FIFOSTATUS:
1014 	case TC358768_DSITXSTATUS ... (TC358768_DSITXSTATUS + 2):
1015 	case TC358768_DSI_CONTROL ... (TC358768_DSI_INT_ENA + 2):
1016 	case TC358768_DSICMD_RDFIFO ... (TC358768_DSI_ERR_HALT + 2):
1017 		return false;
1018 	default:
1019 		return true;
1020 	}
1021 }
1022 
tc358768_readable_reg(struct device * dev,unsigned int reg)1023 static bool tc358768_readable_reg(struct device *dev, unsigned int reg)
1024 {
1025 	if (tc358768_is_reserved_reg(reg))
1026 		return false;
1027 
1028 	switch (reg) {
1029 	case TC358768_STARTCNTRL:
1030 	case TC358768_DSI_CONFW ... (TC358768_DSI_CONFW + 2):
1031 	case TC358768_DSI_INT_CLR ... (TC358768_DSI_INT_CLR + 2):
1032 	case TC358768_DSI_START ... (TC358768_DSI_START + 2):
1033 	case TC358768_DBG_DATA:
1034 		return false;
1035 	default:
1036 		return true;
1037 	}
1038 }
1039 
1040 static const struct regmap_config tc358768_regmap_config = {
1041 	.name = "tc358768",
1042 	.reg_bits = 16,
1043 	.val_bits = 16,
1044 	.max_register = TC358768_DSI_HACT,
1045 	.cache_type = REGCACHE_NONE,
1046 	.writeable_reg = tc358768_writeable_reg,
1047 	.readable_reg = tc358768_readable_reg,
1048 	.reg_format_endian = REGMAP_ENDIAN_BIG,
1049 	.val_format_endian = REGMAP_ENDIAN_BIG,
1050 };
1051 
1052 static const struct i2c_device_id tc358768_i2c_ids[] = {
1053 	{ "tc358768", 0 },
1054 	{ "tc358778", 0 },
1055 	{ }
1056 };
1057 MODULE_DEVICE_TABLE(i2c, tc358768_i2c_ids);
1058 
1059 static const struct of_device_id tc358768_of_ids[] = {
1060 	{ .compatible = "toshiba,tc358768", },
1061 	{ .compatible = "toshiba,tc358778", },
1062 	{ }
1063 };
1064 MODULE_DEVICE_TABLE(of, tc358768_of_ids);
1065 
tc358768_get_regulators(struct tc358768_priv * priv)1066 static int tc358768_get_regulators(struct tc358768_priv *priv)
1067 {
1068 	int i, ret;
1069 
1070 	for (i = 0; i < ARRAY_SIZE(priv->supplies); ++i)
1071 		priv->supplies[i].supply = tc358768_supplies[i];
1072 
1073 	ret = devm_regulator_bulk_get(priv->dev, ARRAY_SIZE(priv->supplies),
1074 				      priv->supplies);
1075 	if (ret < 0)
1076 		dev_err(priv->dev, "failed to get regulators: %d\n", ret);
1077 
1078 	return ret;
1079 }
1080 
tc358768_i2c_probe(struct i2c_client * client)1081 static int tc358768_i2c_probe(struct i2c_client *client)
1082 {
1083 	struct tc358768_priv *priv;
1084 	struct device *dev = &client->dev;
1085 	struct device_node *np = dev->of_node;
1086 	int ret;
1087 
1088 	if (!np)
1089 		return -ENODEV;
1090 
1091 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1092 	if (!priv)
1093 		return -ENOMEM;
1094 
1095 	dev_set_drvdata(dev, priv);
1096 	priv->dev = dev;
1097 
1098 	ret = tc358768_get_regulators(priv);
1099 	if (ret)
1100 		return ret;
1101 
1102 	priv->refclk = devm_clk_get(dev, "refclk");
1103 	if (IS_ERR(priv->refclk))
1104 		return PTR_ERR(priv->refclk);
1105 
1106 	/*
1107 	 * RESX is low active, to disable tc358768 initially (keep in reset)
1108 	 * the gpio line must be LOW. This is the ASSERTED state of
1109 	 * GPIO_ACTIVE_LOW (GPIOD_OUT_HIGH == ASSERTED).
1110 	 */
1111 	priv->reset_gpio  = devm_gpiod_get_optional(dev, "reset",
1112 						    GPIOD_OUT_HIGH);
1113 	if (IS_ERR(priv->reset_gpio))
1114 		return PTR_ERR(priv->reset_gpio);
1115 
1116 	priv->regmap = devm_regmap_init_i2c(client, &tc358768_regmap_config);
1117 	if (IS_ERR(priv->regmap)) {
1118 		dev_err(dev, "Failed to init regmap\n");
1119 		return PTR_ERR(priv->regmap);
1120 	}
1121 
1122 	priv->dsi_host.dev = dev;
1123 	priv->dsi_host.ops = &tc358768_dsi_host_ops;
1124 
1125 	priv->bridge.funcs = &tc358768_bridge_funcs;
1126 	priv->bridge.timings = &default_tc358768_timings;
1127 	priv->bridge.of_node = np;
1128 
1129 	i2c_set_clientdata(client, priv);
1130 
1131 	return mipi_dsi_host_register(&priv->dsi_host);
1132 }
1133 
tc358768_i2c_remove(struct i2c_client * client)1134 static void tc358768_i2c_remove(struct i2c_client *client)
1135 {
1136 	struct tc358768_priv *priv = i2c_get_clientdata(client);
1137 
1138 	mipi_dsi_host_unregister(&priv->dsi_host);
1139 }
1140 
1141 static struct i2c_driver tc358768_driver = {
1142 	.driver = {
1143 		.name = "tc358768",
1144 		.of_match_table = tc358768_of_ids,
1145 	},
1146 	.id_table = tc358768_i2c_ids,
1147 	.probe = tc358768_i2c_probe,
1148 	.remove	= tc358768_i2c_remove,
1149 };
1150 module_i2c_driver(tc358768_driver);
1151 
1152 MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>");
1153 MODULE_DESCRIPTION("TC358768AXBG/TC358778XBG DSI bridge");
1154 MODULE_LICENSE("GPL v2");
1155