xref: /openbmc/qemu/target/sh4/cpu.h (revision 7d95db5e)
1 /*
2  *  SH4 emulation
3  *
4  *  Copyright (c) 2005 Samuel Tardieu
5  *
6  * This library is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU Lesser General Public
8  * License as published by the Free Software Foundation; either
9  * version 2.1 of the License, or (at your option) any later version.
10  *
11  * This library is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14  * Lesser General Public License for more details.
15  *
16  * You should have received a copy of the GNU Lesser General Public
17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #ifndef SH4_CPU_H
21 #define SH4_CPU_H
22 
23 #include "cpu-qom.h"
24 #include "exec/cpu-defs.h"
25 #include "qemu/cpu-float.h"
26 
27 /* CPU Subtypes */
28 #define SH_CPU_SH7750  (1 << 0)
29 #define SH_CPU_SH7750S (1 << 1)
30 #define SH_CPU_SH7750R (1 << 2)
31 #define SH_CPU_SH7751  (1 << 3)
32 #define SH_CPU_SH7751R (1 << 4)
33 #define SH_CPU_SH7785  (1 << 5)
34 #define SH_CPU_SH7750_ALL (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7750R)
35 #define SH_CPU_SH7751_ALL (SH_CPU_SH7751 | SH_CPU_SH7751R)
36 
37 #define SR_MD 30
38 #define SR_RB 29
39 #define SR_BL 28
40 #define SR_FD 15
41 #define SR_M  9
42 #define SR_Q  8
43 #define SR_I3 7
44 #define SR_I2 6
45 #define SR_I1 5
46 #define SR_I0 4
47 #define SR_S  1
48 #define SR_T  0
49 
50 #define FPSCR_MASK             (0x003fffff)
51 #define FPSCR_FR               (1 << 21)
52 #define FPSCR_SZ               (1 << 20)
53 #define FPSCR_PR               (1 << 19)
54 #define FPSCR_DN               (1 << 18)
55 #define FPSCR_CAUSE_MASK       (0x3f << 12)
56 #define FPSCR_CAUSE_SHIFT      (12)
57 #define FPSCR_CAUSE_E          (1 << 17)
58 #define FPSCR_CAUSE_V          (1 << 16)
59 #define FPSCR_CAUSE_Z          (1 << 15)
60 #define FPSCR_CAUSE_O          (1 << 14)
61 #define FPSCR_CAUSE_U          (1 << 13)
62 #define FPSCR_CAUSE_I          (1 << 12)
63 #define FPSCR_ENABLE_MASK      (0x1f << 7)
64 #define FPSCR_ENABLE_SHIFT     (7)
65 #define FPSCR_ENABLE_V         (1 << 11)
66 #define FPSCR_ENABLE_Z         (1 << 10)
67 #define FPSCR_ENABLE_O         (1 << 9)
68 #define FPSCR_ENABLE_U         (1 << 8)
69 #define FPSCR_ENABLE_I         (1 << 7)
70 #define FPSCR_FLAG_MASK        (0x1f << 2)
71 #define FPSCR_FLAG_SHIFT       (2)
72 #define FPSCR_FLAG_V           (1 << 6)
73 #define FPSCR_FLAG_Z           (1 << 5)
74 #define FPSCR_FLAG_O           (1 << 4)
75 #define FPSCR_FLAG_U           (1 << 3)
76 #define FPSCR_FLAG_I           (1 << 2)
77 #define FPSCR_RM_MASK          (0x03 << 0)
78 #define FPSCR_RM_NEAREST       (0 << 0)
79 #define FPSCR_RM_ZERO          (1 << 0)
80 
81 #define TB_FLAG_DELAY_SLOT       (1 << 0)
82 #define TB_FLAG_DELAY_SLOT_COND  (1 << 1)
83 #define TB_FLAG_DELAY_SLOT_RTE   (1 << 2)
84 #define TB_FLAG_PENDING_MOVCA    (1 << 3)
85 #define TB_FLAG_GUSA_SHIFT       4                      /* [11:4] */
86 #define TB_FLAG_GUSA_EXCLUSIVE   (1 << 12)
87 #define TB_FLAG_UNALIGN          (1 << 13)
88 #define TB_FLAG_SR_FD            (1 << SR_FD)           /* 15 */
89 #define TB_FLAG_FPSCR_PR         FPSCR_PR               /* 19 */
90 #define TB_FLAG_FPSCR_SZ         FPSCR_SZ               /* 20 */
91 #define TB_FLAG_FPSCR_FR         FPSCR_FR               /* 21 */
92 #define TB_FLAG_SR_RB            (1 << SR_RB)           /* 29 */
93 #define TB_FLAG_SR_MD            (1 << SR_MD)           /* 30 */
94 
95 #define TB_FLAG_DELAY_SLOT_MASK  (TB_FLAG_DELAY_SLOT |       \
96                                   TB_FLAG_DELAY_SLOT_COND |  \
97                                   TB_FLAG_DELAY_SLOT_RTE)
98 #define TB_FLAG_GUSA_MASK        ((0xff << TB_FLAG_GUSA_SHIFT) | \
99                                   TB_FLAG_GUSA_EXCLUSIVE)
100 #define TB_FLAG_FPSCR_MASK       (TB_FLAG_FPSCR_PR | \
101                                   TB_FLAG_FPSCR_SZ | \
102                                   TB_FLAG_FPSCR_FR)
103 #define TB_FLAG_SR_MASK          (TB_FLAG_SR_FD | \
104                                   TB_FLAG_SR_RB | \
105                                   TB_FLAG_SR_MD)
106 #define TB_FLAG_ENVFLAGS_MASK    (TB_FLAG_DELAY_SLOT_MASK | \
107                                   TB_FLAG_GUSA_MASK)
108 
109 typedef struct tlb_t {
110     uint32_t vpn;        /* virtual page number */
111     uint32_t ppn;        /* physical page number */
112     uint32_t size;       /* mapped page size in bytes */
113     uint8_t asid;        /* address space identifier */
114     uint8_t v:1;         /* validity */
115     uint8_t sz:2;        /* page size */
116     uint8_t sh:1;        /* share status */
117     uint8_t c:1;         /* cacheability */
118     uint8_t pr:2;        /* protection key */
119     uint8_t d:1;         /* dirty */
120     uint8_t wt:1;        /* write through */
121     uint8_t sa:3;        /* space attribute (PCMCIA) */
122     uint8_t tc:1;        /* timing control */
123 } tlb_t;
124 
125 #define UTLB_SIZE 64
126 #define ITLB_SIZE 4
127 
128 #define TARGET_INSN_START_EXTRA_WORDS 1
129 
130 enum sh_features {
131     SH_FEATURE_SH4A = 1,
132     SH_FEATURE_BCR3_AND_BCR4 = 2,
133 };
134 
135 typedef struct memory_content {
136     uint32_t address;
137     uint32_t value;
138     struct memory_content *next;
139 } memory_content;
140 
141 typedef struct CPUArchState {
142     uint32_t flags;             /* general execution flags */
143     uint32_t gregs[24];         /* general registers */
144     float32 fregs[32];          /* floating point registers */
145     uint32_t sr;                /* status register (with T split out) */
146     uint32_t sr_m;              /* M bit of status register */
147     uint32_t sr_q;              /* Q bit of status register */
148     uint32_t sr_t;              /* T bit of status register */
149     uint32_t ssr;               /* saved status register */
150     uint32_t spc;               /* saved program counter */
151     uint32_t gbr;               /* global base register */
152     uint32_t vbr;               /* vector base register */
153     uint32_t sgr;               /* saved global register 15 */
154     uint32_t dbr;               /* debug base register */
155     uint32_t pc;                /* program counter */
156     uint32_t delayed_pc;        /* target of delayed branch */
157     uint32_t delayed_cond;      /* condition of delayed branch */
158     uint32_t pr;                /* procedure register */
159     uint32_t fpscr;             /* floating point status/control register */
160     uint32_t fpul;              /* floating point communication register */
161 
162     /* multiply and accumulate: high, low and combined. */
163     union {
164         uint64_t mac;
165         struct {
166 #if HOST_BIG_ENDIAN
167             uint32_t mach, macl;
168 #else
169             uint32_t macl, mach;
170 #endif
171         };
172     };
173 
174     /* float point status register */
175     float_status fp_status;
176 
177     /* Those belong to the specific unit (SH7750) but are handled here */
178     uint32_t mmucr;             /* MMU control register */
179     uint32_t pteh;              /* page table entry high register */
180     uint32_t ptel;              /* page table entry low register */
181     uint32_t ptea;              /* page table entry assistance register */
182     uint32_t ttb;               /* translation table base register */
183     uint32_t tea;               /* TLB exception address register */
184     uint32_t tra;               /* TRAPA exception register */
185     uint32_t expevt;            /* exception event register */
186     uint32_t intevt;            /* interrupt event register */
187 
188     tlb_t itlb[ITLB_SIZE];      /* instruction translation table */
189     tlb_t utlb[UTLB_SIZE];      /* unified translation table */
190 
191     /* LDST = LOCK_ADDR != -1.  */
192     uint32_t lock_addr;
193     uint32_t lock_value;
194 
195     /* Fields up to this point are cleared by a CPU reset */
196     struct {} end_reset_fields;
197 
198     /* Fields from here on are preserved over CPU reset. */
199     int id;                     /* CPU model */
200 
201     /* The features that we should emulate. See sh_features above.  */
202     uint32_t features;
203 
204     void *intc_handle;
205     int in_sleep;               /* SR_BL ignored during sleep */
206     memory_content *movcal_backup;
207     memory_content **movcal_backup_tail;
208 } CPUSH4State;
209 
210 /**
211  * SuperHCPU:
212  * @env: #CPUSH4State
213  *
214  * A SuperH CPU.
215  */
216 struct ArchCPU {
217     CPUState parent_obj;
218 
219     CPUSH4State env;
220 };
221 
222 /**
223  * SuperHCPUClass:
224  * @parent_realize: The parent class' realize handler.
225  * @parent_phases: The parent class' reset phase handlers.
226  * @pvr: Processor Version Register
227  * @prr: Processor Revision Register
228  * @cvr: Cache Version Register
229  *
230  * A SuperH CPU model.
231  */
232 struct SuperHCPUClass {
233     CPUClass parent_class;
234 
235     DeviceRealize parent_realize;
236     ResettablePhases parent_phases;
237 
238     uint32_t pvr;
239     uint32_t prr;
240     uint32_t cvr;
241 };
242 
243 void superh_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
244 int superh_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
245 int superh_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
246 G_NORETURN void superh_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
247                                                MMUAccessType access_type, int mmu_idx,
248                                                uintptr_t retaddr);
249 
250 void sh4_translate_init(void);
251 
252 #if !defined(CONFIG_USER_ONLY)
253 hwaddr superh_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
254 bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
255                          MMUAccessType access_type, int mmu_idx,
256                          bool probe, uintptr_t retaddr);
257 void superh_cpu_do_interrupt(CPUState *cpu);
258 bool superh_cpu_exec_interrupt(CPUState *cpu, int int_req);
259 void cpu_sh4_invalidate_tlb(CPUSH4State *s);
260 uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s,
261                                        hwaddr addr);
262 void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, hwaddr addr,
263                                     uint32_t mem_value);
264 uint32_t cpu_sh4_read_mmaped_itlb_data(CPUSH4State *s,
265                                        hwaddr addr);
266 void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, hwaddr addr,
267                                     uint32_t mem_value);
268 uint32_t cpu_sh4_read_mmaped_utlb_addr(CPUSH4State *s,
269                                        hwaddr addr);
270 void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr,
271                                     uint32_t mem_value);
272 uint32_t cpu_sh4_read_mmaped_utlb_data(CPUSH4State *s,
273                                        hwaddr addr);
274 void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr,
275                                     uint32_t mem_value);
276 #endif
277 
278 int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr);
279 
280 void cpu_load_tlb(CPUSH4State * env);
281 
282 #define CPU_RESOLVING_TYPE TYPE_SUPERH_CPU
283 
284 /* MMU modes definitions */
285 #define MMU_USER_IDX 1
286 
287 #include "exec/cpu-all.h"
288 
289 /* MMU control register */
290 #define MMUCR    0x1F000010
291 #define MMUCR_AT (1<<0)
292 #define MMUCR_TI (1<<2)
293 #define MMUCR_SV (1<<8)
294 #define MMUCR_URC_BITS (6)
295 #define MMUCR_URC_OFFSET (10)
296 #define MMUCR_URC_SIZE (1 << MMUCR_URC_BITS)
297 #define MMUCR_URC_MASK (((MMUCR_URC_SIZE) - 1) << MMUCR_URC_OFFSET)
cpu_mmucr_urc(uint32_t mmucr)298 static inline int cpu_mmucr_urc (uint32_t mmucr)
299 {
300     return ((mmucr & MMUCR_URC_MASK) >> MMUCR_URC_OFFSET);
301 }
302 
303 /* PTEH : Page Translation Entry High register */
304 #define PTEH_ASID_BITS (8)
305 #define PTEH_ASID_SIZE (1 << PTEH_ASID_BITS)
306 #define PTEH_ASID_MASK (PTEH_ASID_SIZE - 1)
307 #define cpu_pteh_asid(pteh) ((pteh) & PTEH_ASID_MASK)
308 #define PTEH_VPN_BITS (22)
309 #define PTEH_VPN_OFFSET (10)
310 #define PTEH_VPN_SIZE (1 << PTEH_VPN_BITS)
311 #define PTEH_VPN_MASK (((PTEH_VPN_SIZE) - 1) << PTEH_VPN_OFFSET)
cpu_pteh_vpn(uint32_t pteh)312 static inline int cpu_pteh_vpn (uint32_t pteh)
313 {
314     return ((pteh & PTEH_VPN_MASK) >> PTEH_VPN_OFFSET);
315 }
316 
317 /* PTEL : Page Translation Entry Low register */
318 #define PTEL_V        (1 << 8)
319 #define cpu_ptel_v(ptel) (((ptel) & PTEL_V) >> 8)
320 #define PTEL_C        (1 << 3)
321 #define cpu_ptel_c(ptel) (((ptel) & PTEL_C) >> 3)
322 #define PTEL_D        (1 << 2)
323 #define cpu_ptel_d(ptel) (((ptel) & PTEL_D) >> 2)
324 #define PTEL_SH       (1 << 1)
325 #define cpu_ptel_sh(ptel)(((ptel) & PTEL_SH) >> 1)
326 #define PTEL_WT       (1 << 0)
327 #define cpu_ptel_wt(ptel) ((ptel) & PTEL_WT)
328 
329 #define PTEL_SZ_HIGH_OFFSET  (7)
330 #define PTEL_SZ_HIGH  (1 << PTEL_SZ_HIGH_OFFSET)
331 #define PTEL_SZ_LOW_OFFSET   (4)
332 #define PTEL_SZ_LOW   (1 << PTEL_SZ_LOW_OFFSET)
cpu_ptel_sz(uint32_t ptel)333 static inline int cpu_ptel_sz (uint32_t ptel)
334 {
335     int sz;
336     sz = (ptel & PTEL_SZ_HIGH) >> PTEL_SZ_HIGH_OFFSET;
337     sz <<= 1;
338     sz |= (ptel & PTEL_SZ_LOW) >> PTEL_SZ_LOW_OFFSET;
339     return sz;
340 }
341 
342 #define PTEL_PPN_BITS (19)
343 #define PTEL_PPN_OFFSET (10)
344 #define PTEL_PPN_SIZE (1 << PTEL_PPN_BITS)
345 #define PTEL_PPN_MASK (((PTEL_PPN_SIZE) - 1) << PTEL_PPN_OFFSET)
cpu_ptel_ppn(uint32_t ptel)346 static inline int cpu_ptel_ppn (uint32_t ptel)
347 {
348     return ((ptel & PTEL_PPN_MASK) >> PTEL_PPN_OFFSET);
349 }
350 
351 #define PTEL_PR_BITS   (2)
352 #define PTEL_PR_OFFSET (5)
353 #define PTEL_PR_SIZE (1 << PTEL_PR_BITS)
354 #define PTEL_PR_MASK (((PTEL_PR_SIZE) - 1) << PTEL_PR_OFFSET)
cpu_ptel_pr(uint32_t ptel)355 static inline int cpu_ptel_pr (uint32_t ptel)
356 {
357     return ((ptel & PTEL_PR_MASK) >> PTEL_PR_OFFSET);
358 }
359 
360 /* PTEA : Page Translation Entry Assistance register */
361 #define PTEA_SA_BITS (3)
362 #define PTEA_SA_SIZE (1 << PTEA_SA_BITS)
363 #define PTEA_SA_MASK (PTEA_SA_SIZE - 1)
364 #define cpu_ptea_sa(ptea) ((ptea) & PTEA_SA_MASK)
365 #define PTEA_TC        (1 << 3)
366 #define cpu_ptea_tc(ptea) (((ptea) & PTEA_TC) >> 3)
367 
cpu_read_sr(CPUSH4State * env)368 static inline target_ulong cpu_read_sr(CPUSH4State *env)
369 {
370     return env->sr | (env->sr_m << SR_M) |
371                      (env->sr_q << SR_Q) |
372                      (env->sr_t << SR_T);
373 }
374 
cpu_write_sr(CPUSH4State * env,target_ulong sr)375 static inline void cpu_write_sr(CPUSH4State *env, target_ulong sr)
376 {
377     env->sr_m = (sr >> SR_M) & 1;
378     env->sr_q = (sr >> SR_Q) & 1;
379     env->sr_t = (sr >> SR_T) & 1;
380     env->sr = sr & ~((1u << SR_M) | (1u << SR_Q) | (1u << SR_T));
381 }
382 
cpu_get_tb_cpu_state(CPUSH4State * env,vaddr * pc,uint64_t * cs_base,uint32_t * flags)383 static inline void cpu_get_tb_cpu_state(CPUSH4State *env, vaddr *pc,
384                                         uint64_t *cs_base, uint32_t *flags)
385 {
386     *pc = env->pc;
387     /* For a gUSA region, notice the end of the region.  */
388     *cs_base = env->flags & TB_FLAG_GUSA_MASK ? env->gregs[0] : 0;
389     *flags = env->flags
390             | (env->fpscr & TB_FLAG_FPSCR_MASK)
391             | (env->sr & TB_FLAG_SR_MASK)
392             | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 3 */
393 #ifdef CONFIG_USER_ONLY
394     *flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus;
395 #endif
396 }
397 
398 #endif /* SH4_CPU_H */
399