1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * LoongArch translation routines. 4 * 5 * Copyright (c) 2021 Loongson Technology Corporation Limited 6 */ 7 8 #ifndef TARGET_LOONGARCH_TRANSLATE_H 9 #define TARGET_LOONGARCH_TRANSLATE_H 10 11 #include "exec/translator.h" 12 13 #define TRANS(NAME, AVAIL, FUNC, ...) \ 14 static bool trans_##NAME(DisasContext *ctx, arg_##NAME * a) \ 15 { return avail_##AVAIL(ctx) && FUNC(ctx, a, __VA_ARGS__); } 16 17 #define TRANS64(NAME, AVAIL, FUNC, ...) \ 18 static bool trans_##NAME(DisasContext *ctx, arg_##NAME * a) \ 19 { return avail_64(ctx) && avail_##AVAIL(ctx) && FUNC(ctx, a, __VA_ARGS__); } 20 21 #define avail_ALL(C) true 22 #define avail_64(C) (FIELD_EX32((C)->cpucfg1, CPUCFG1, ARCH) == \ 23 CPUCFG1_ARCH_LA64) 24 #define avail_FP(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, FP)) 25 #define avail_FP_SP(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, FP_SP)) 26 #define avail_FP_DP(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, FP_DP)) 27 #define avail_LSPW(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LSPW)) 28 #define avail_LAM(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LAM)) 29 #define avail_LSX(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LSX)) 30 #define avail_LASX(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LASX)) 31 #define avail_IOCSR(C) (FIELD_EX32((C)->cpucfg1, CPUCFG1, IOCSR)) 32 #define avail_CRC(C) (FIELD_EX32((C)->cpucfg1, CPUCFG1, CRC)) 33 34 /* 35 * If an operation is being performed on less than TARGET_LONG_BITS, 36 * it may require the inputs to be sign- or zero-extended; which will 37 * depend on the exact operation being performed. 38 */ 39 typedef enum { 40 EXT_NONE, 41 EXT_SIGN, 42 EXT_ZERO, 43 } DisasExtend; 44 45 typedef struct DisasContext { 46 DisasContextBase base; 47 target_ulong page_start; 48 uint32_t opcode; 49 uint16_t mem_idx; 50 uint16_t plv; 51 int vl; /* Vector length */ 52 TCGv zero; 53 bool la64; /* LoongArch64 mode */ 54 bool va32; /* 32-bit virtual address */ 55 uint32_t cpucfg1; 56 uint32_t cpucfg2; 57 } DisasContext; 58 59 void generate_exception(DisasContext *ctx, int excp); 60 61 extern TCGv cpu_gpr[32], cpu_pc; 62 extern TCGv_i32 cpu_fscr0; 63 extern TCGv_i64 cpu_fpr[32]; 64 65 #endif 66