1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2017 NXP
4  * Copyright 2015 Freescale Semiconductor
5  */
6 
7 #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_
8 #define _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_
9 
10 #ifndef __ASSEMBLY__
11 #include <linux/types.h>
12 #ifdef CONFIG_FSL_LSCH2
13 #include <asm/arch/immap_lsch2.h>
14 #endif
15 #ifdef CONFIG_FSL_LSCH3
16 #include <asm/arch/immap_lsch3.h>
17 #endif
18 #endif
19 
20 #ifdef CONFIG_SYS_FSL_CCSR_GUR_LE
21 #define gur_in32(a)       in_le32(a)
22 #define gur_out32(a, v)   out_le32(a, v)
23 #elif defined(CONFIG_SYS_FSL_CCSR_GUR_BE)
24 #define gur_in32(a)       in_be32(a)
25 #define gur_out32(a, v)   out_be32(a, v)
26 #endif
27 
28 #ifdef CONFIG_SYS_FSL_CCSR_SCFG_LE
29 #define scfg_in32(a)       in_le32(a)
30 #define scfg_out32(a, v)   out_le32(a, v)
31 #define scfg_clrbits32(addr, clear) clrbits_le32(addr, clear)
32 #define scfg_clrsetbits32(addr, clear, set) clrsetbits_le32(addr, clear, set)
33 #elif defined(CONFIG_SYS_FSL_CCSR_SCFG_BE)
34 #define scfg_in32(a)       in_be32(a)
35 #define scfg_out32(a, v)   out_be32(a, v)
36 #define scfg_clrbits32(addr, clear) clrbits_be32(addr, clear)
37 #define scfg_clrsetbits32(addr, clear, set) clrsetbits_be32(addr, clear, set)
38 #endif
39 
40 #ifdef CONFIG_SYS_FSL_PEX_LUT_LE
41 #define pex_lut_in32(a)       in_le32(a)
42 #define pex_lut_out32(a, v)   out_le32(a, v)
43 #elif defined(CONFIG_SYS_FSL_PEX_LUT_BE)
44 #define pex_lut_in32(a)       in_be32(a)
45 #define pex_lut_out32(a, v)   out_be32(a, v)
46 #endif
47 #ifndef __ASSEMBLY__
48 struct cpu_type {
49 	char name[15];
50 	u32 soc_ver;
51 	u32 num_cores;
52 };
53 
54 #define CPU_TYPE_ENTRY(n, v, nc) \
55 	{ .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
56 
57 #ifdef CONFIG_TFABOOT
58 #define SMC_DRAM_BANK_INFO (0xC200FF12)
59 #define SIP_SVC_RCW	0xC200FF18
60 
61 phys_size_t tfa_get_dram_size(void);
62 
63 enum boot_src {
64 	BOOT_SOURCE_RESERVED = 0,
65 	BOOT_SOURCE_IFC_NOR,
66 	BOOT_SOURCE_IFC_NAND,
67 	BOOT_SOURCE_QSPI_NOR,
68 	BOOT_SOURCE_QSPI_NAND,
69 	BOOT_SOURCE_XSPI_NOR,
70 	BOOT_SOURCE_XSPI_NAND,
71 	BOOT_SOURCE_SD_MMC,
72 	BOOT_SOURCE_SD_MMC2,
73 	BOOT_SOURCE_I2C1_EXTENDED,
74 };
75 
76 enum boot_src get_boot_src(void);
77 #endif
78 #endif
79 #define SVR_WO_E		0xFFFFFE
80 #define SVR_LS1012A		0x870400
81 #define SVR_LS1043A		0x879200
82 #define SVR_LS1023A		0x879208
83 /* LS1043A/LS1023A 23x23 package silicon has different value of VAR_PER */
84 #define SVR_LS1043A_P23		0x879202
85 #define SVR_LS1023A_P23		0x87920A
86 #define SVR_LS1046A		0x870700
87 #define SVR_LS1026A		0x870708
88 #define SVR_LS1048A		0x870320
89 #define SVR_LS1084A		0x870302
90 #define SVR_LS1088A		0x870300
91 #define SVR_LS1044A		0x870322
92 #define SVR_LS2045A		0x870120
93 #define SVR_LS2080A		0x870110
94 #define SVR_LS2085A		0x870100
95 #define SVR_LS2040A		0x870130
96 #define SVR_LS2088A		0x870900
97 #define SVR_LS2084A		0x870910
98 #define SVR_LS2048A		0x870920
99 #define SVR_LS2044A		0x870930
100 #define SVR_LS2081A		0x870918
101 #define SVR_LS2041A		0x870914
102 #define SVR_LX2160A		0x873601
103 #define SVR_LX2120A		0x873621
104 #define SVR_LX2080A		0x873603
105 
106 #define SVR_MAJ(svr)		(((svr) >> 4) & 0xf)
107 #define SVR_MIN(svr)		(((svr) >> 0) & 0xf)
108 #define SVR_REV(svr)		(((svr) >> 0) & 0xff)
109 #define SVR_SOC_VER(svr)	(((svr) >> 8) & SVR_WO_E)
110 #define IS_E_PROCESSOR(svr)	(!((svr >> 8) & 0x1))
111 #ifdef CONFIG_ARCH_LX2160A
112 #define IS_C_PROCESSOR(svr)	(!((svr >> 12) & 0x1))
113 #endif
114 #define IS_SVR_REV(svr, maj, min) \
115 		((SVR_MAJ(svr) == (maj)) && (SVR_MIN(svr) == (min)))
116 #define SVR_DEV(svr)		((svr) >> 8)
117 #define IS_SVR_DEV(svr, dev)	(((svr) >> 16) == (dev))
118 
119 #ifndef __ASSEMBLY__
120 #ifdef CONFIG_FSL_LSCH3
121 void fsl_lsch3_early_init_f(void);
122 int get_core_volt_from_fuse(void);
123 #elif defined(CONFIG_FSL_LSCH2)
124 void fsl_lsch2_early_init_f(void);
125 int setup_chip_volt(void);
126 /* Setup core vdd in unit mV */
127 int board_setup_core_volt(u32 vdd);
128 #ifdef CONFIG_FSL_PFE
129 void init_pfe_scfg_dcfg_regs(void);
130 #endif
131 #endif
132 #ifdef CONFIG_QSPI_AHB_INIT
133 int qspi_ahb_init(void);
134 #endif
135 
136 void cpu_name(char *name);
137 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
138 void erratum_a009635(void);
139 #endif
140 
141 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
142 void erratum_a010315(void);
143 #endif
144 
145 bool soc_has_dp_ddr(void);
146 bool soc_has_aiop(void);
147 #endif
148 
149 #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */
150