1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * R8A66597 HCD (Host Controller Driver) for u-boot
4 *
5 * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
6 */
7
8 #ifndef __R8A66597_H__
9 #define __R8A66597_H__
10
11 #define SYSCFG0 0x00
12 #define SYSCFG1 0x02
13 #define SYSSTS0 0x04
14 #define SYSSTS1 0x06
15 #define DVSTCTR0 0x08
16 #define DVSTCTR1 0x0A
17 #define TESTMODE 0x0C
18 #define PINCFG 0x0E
19 #define DMA0CFG 0x10
20 #define DMA1CFG 0x12
21 #define CFIFO 0x14
22 #define D0FIFO 0x18
23 #define D1FIFO 0x1C
24 #define CFIFOSEL 0x20
25 #define CFIFOCTR 0x22
26 #define CFIFOSIE 0x24
27 #define D0FIFOSEL 0x28
28 #define D0FIFOCTR 0x2A
29 #define D1FIFOSEL 0x2C
30 #define D1FIFOCTR 0x2E
31 #define INTENB0 0x30
32 #define INTENB1 0x32
33 #define INTENB2 0x34
34 #define BRDYENB 0x36
35 #define NRDYENB 0x38
36 #define BEMPENB 0x3A
37 #define SOFCFG 0x3C
38 #define INTSTS0 0x40
39 #define INTSTS1 0x42
40 #define INTSTS2 0x44
41 #define BRDYSTS 0x46
42 #define NRDYSTS 0x48
43 #define BEMPSTS 0x4A
44 #define FRMNUM 0x4C
45 #define UFRMNUM 0x4E
46 #define USBADDR 0x50
47 #define USBREQ 0x54
48 #define USBVAL 0x56
49 #define USBINDX 0x58
50 #define USBLENG 0x5A
51 #define DCPCFG 0x5C
52 #define DCPMAXP 0x5E
53 #define DCPCTR 0x60
54 #define PIPESEL 0x64
55 #define PIPECFG 0x68
56 #define PIPEBUF 0x6A
57 #define PIPEMAXP 0x6C
58 #define PIPEPERI 0x6E
59 #define PIPE1CTR 0x70
60 #define PIPE2CTR 0x72
61 #define PIPE3CTR 0x74
62 #define PIPE4CTR 0x76
63 #define PIPE5CTR 0x78
64 #define PIPE6CTR 0x7A
65 #define PIPE7CTR 0x7C
66 #define PIPE8CTR 0x7E
67 #define PIPE9CTR 0x80
68 #define PIPE1TRE 0x90
69 #define PIPE1TRN 0x92
70 #define PIPE2TRE 0x94
71 #define PIPE2TRN 0x96
72 #define PIPE3TRE 0x98
73 #define PIPE3TRN 0x9A
74 #define PIPE4TRE 0x9C
75 #define PIPE4TRN 0x9E
76 #define PIPE5TRE 0xA0
77 #define PIPE5TRN 0xA2
78 #define DEVADD0 0xD0
79 #define DEVADD1 0xD2
80 #define DEVADD2 0xD4
81 #define DEVADD3 0xD6
82 #define DEVADD4 0xD8
83 #define DEVADD5 0xDA
84 #define DEVADD6 0xDC
85 #define DEVADD7 0xDE
86 #define DEVADD8 0xE0
87 #define DEVADD9 0xE2
88 #define DEVADDA 0xE4
89 #define SUSPMODE0 0x102 /* RZ/A only */
90
91 /* System Configuration Control Register */
92 #if !defined(CONFIG_RZA_USB)
93 #define XTAL 0xC000 /* b15-14: Crystal selection */
94 #define XTAL48 0x8000 /* 48MHz */
95 #define XTAL24 0x4000 /* 24MHz */
96 #define XTAL12 0x0000 /* 12MHz */
97 #define XCKE 0x2000 /* b13: External clock enable */
98 #define PLLC 0x0800 /* b11: PLL control */
99 #define SCKE 0x0400 /* b10: USB clock enable */
100 #define PCSDIS 0x0200 /* b9: not CS wakeup */
101 #define LPSME 0x0100 /* b8: Low power sleep mode */
102 #endif
103 #define HSE 0x0080 /* b7: Hi-speed enable */
104 #define DCFM 0x0040 /* b6: Controller function select */
105 #define DRPD 0x0020 /* b5: D+/- pull down control */
106 #define DPRPU 0x0010 /* b4: D+ pull up control */
107 #if defined(CONFIG_RZA_USB)
108 #define XTAL 0x0004 /* b2: Crystal selection */
109 #define XTAL12 0x0004 /* 12MHz */
110 #define XTAL48 0x0000 /* 48MHz */
111 #define UPLLE 0x0002 /* b1: internal PLL control */
112 #endif
113 #define USBE 0x0001 /* b0: USB module operation enable */
114
115 /* System Configuration Status Register */
116 #define OVCBIT 0x8000 /* b15-14: Over-current bit */
117 #define OVCMON 0xC000 /* b15-14: Over-current monitor */
118 #define SOFEA 0x0020 /* b5: SOF monitor */
119 #define IDMON 0x0004 /* b3: ID-pin monitor */
120 #define LNST 0x0003 /* b1-0: D+, D- line status */
121 #define SE1 0x0003 /* SE1 */
122 #define FS_KSTS 0x0002 /* Full-Speed K State */
123 #define FS_JSTS 0x0001 /* Full-Speed J State */
124 #define LS_JSTS 0x0002 /* Low-Speed J State */
125 #define LS_KSTS 0x0001 /* Low-Speed K State */
126 #define SE0 0x0000 /* SE0 */
127
128 /* Device State Control Register */
129 #define EXTLP0 0x0400 /* b10: External port */
130 #define VBOUT 0x0200 /* b9: VBUS output */
131 #define WKUP 0x0100 /* b8: Remote wakeup */
132 #define RWUPE 0x0080 /* b7: Remote wakeup sense */
133 #define USBRST 0x0040 /* b6: USB reset enable */
134 #define RESUME 0x0020 /* b5: Resume enable */
135 #define UACT 0x0010 /* b4: USB bus enable */
136 #define RHST 0x0007 /* b1-0: Reset handshake status */
137 #define HSPROC 0x0004 /* HS handshake is processing */
138 #define HSMODE 0x0003 /* Hi-Speed mode */
139 #define FSMODE 0x0002 /* Full-Speed mode */
140 #define LSMODE 0x0001 /* Low-Speed mode */
141 #define UNDECID 0x0000 /* Undecided */
142
143 /* Test Mode Register */
144 #define UTST 0x000F /* b3-0: Test select */
145 #define H_TST_PACKET 0x000C /* HOST TEST Packet */
146 #define H_TST_SE0_NAK 0x000B /* HOST TEST SE0 NAK */
147 #define H_TST_K 0x000A /* HOST TEST K */
148 #define H_TST_J 0x0009 /* HOST TEST J */
149 #define H_TST_NORMAL 0x0000 /* HOST Normal Mode */
150 #define P_TST_PACKET 0x0004 /* PERI TEST Packet */
151 #define P_TST_SE0_NAK 0x0003 /* PERI TEST SE0 NAK */
152 #define P_TST_K 0x0002 /* PERI TEST K */
153 #define P_TST_J 0x0001 /* PERI TEST J */
154 #define P_TST_NORMAL 0x0000 /* PERI Normal Mode */
155
156 /* Data Pin Configuration Register */
157 #define LDRV 0x8000 /* b15: Drive Current Adjust */
158 #define VIF1 0x0000 /* VIF = 1.8V */
159 #define VIF3 0x8000 /* VIF = 3.3V */
160 #define INTA 0x0001 /* b1: USB INT-pin active */
161
162 /* DMAx Pin Configuration Register */
163 #define DREQA 0x4000 /* b14: Dreq active select */
164 #define BURST 0x2000 /* b13: Burst mode */
165 #define DACKA 0x0400 /* b10: Dack active select */
166 #define DFORM 0x0380 /* b9-7: DMA mode select */
167 #define CPU_ADR_RD_WR 0x0000 /* Address + RD/WR mode (CPU bus) */
168 #define CPU_DACK_RD_WR 0x0100 /* DACK + RD/WR mode (CPU bus) */
169 #define CPU_DACK_ONLY 0x0180 /* DACK only mode (CPU bus) */
170 #define SPLIT_DACK_ONLY 0x0200 /* DACK only mode (SPLIT bus) */
171 #define DENDA 0x0040 /* b6: Dend active select */
172 #define PKTM 0x0020 /* b5: Packet mode */
173 #define DENDE 0x0010 /* b4: Dend enable */
174 #define OBUS 0x0004 /* b2: OUTbus mode */
175
176 /* CFIFO/DxFIFO Port Select Register */
177 #define RCNT 0x8000 /* b15: Read count mode */
178 #define REW 0x4000 /* b14: Buffer rewind */
179 #define DCLRM 0x2000 /* b13: DMA buffer clear mode */
180 #define DREQE 0x1000 /* b12: DREQ output enable */
181 #if defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
182 #define MBW 0x0800
183 #else
184 #if !defined(CONFIG_RZA_USB)
185 #define MBW 0x0400 /* b10: Maximum bit width for FIFO access */
186 #else
187 #define MBW 0x0800 /* b10: Maximum bit width for FIFO access */
188 #endif
189 #endif
190 #define MBW_8 0x0000 /* 8bit */
191 #define MBW_16 0x0400 /* 16bit */
192 #define MBW_32 0x0800 /* 32bit */
193 #define BIGEND 0x0100 /* b8: Big endian mode */
194 #define BYTE_LITTLE 0x0000 /* little dendian */
195 #define BYTE_BIG 0x0100 /* big endifan */
196 #define ISEL 0x0020 /* b5: DCP FIFO port direction select */
197 #define CURPIPE 0x000F /* b2-0: PIPE select */
198
199 /* CFIFO/DxFIFO Port Control Register */
200 #define BVAL 0x8000 /* b15: Buffer valid flag */
201 #define BCLR 0x4000 /* b14: Buffer clear */
202 #define FRDY 0x2000 /* b13: FIFO ready */
203 #define DTLN 0x0FFF /* b11-0: FIFO received data length */
204
205 /* Interrupt Enable Register 0 */
206 #define VBSE 0x8000 /* b15: VBUS interrupt */
207 #define RSME 0x4000 /* b14: Resume interrupt */
208 #define SOFE 0x2000 /* b13: Frame update interrupt */
209 #define DVSE 0x1000 /* b12: Device state transition interrupt */
210 #define CTRE 0x0800 /* b11: Control transfer stage transition interrupt */
211 #define BEMPE 0x0400 /* b10: Buffer empty interrupt */
212 #define NRDYE 0x0200 /* b9: Buffer not ready interrupt */
213 #define BRDYE 0x0100 /* b8: Buffer ready interrupt */
214
215 /* Interrupt Enable Register 1 */
216 #define OVRCRE 0x8000 /* b15: Over-current interrupt */
217 #define BCHGE 0x4000 /* b14: USB us chenge interrupt */
218 #define DTCHE 0x1000 /* b12: Detach sense interrupt */
219 #define ATTCHE 0x0800 /* b11: Attach sense interrupt */
220 #define EOFERRE 0x0040 /* b6: EOF error interrupt */
221 #define SIGNE 0x0020 /* b5: SETUP IGNORE interrupt */
222 #define SACKE 0x0010 /* b4: SETUP ACK interrupt */
223
224 /* BRDY Interrupt Enable/Status Register */
225 #define BRDY9 0x0200 /* b9: PIPE9 */
226 #define BRDY8 0x0100 /* b8: PIPE8 */
227 #define BRDY7 0x0080 /* b7: PIPE7 */
228 #define BRDY6 0x0040 /* b6: PIPE6 */
229 #define BRDY5 0x0020 /* b5: PIPE5 */
230 #define BRDY4 0x0010 /* b4: PIPE4 */
231 #define BRDY3 0x0008 /* b3: PIPE3 */
232 #define BRDY2 0x0004 /* b2: PIPE2 */
233 #define BRDY1 0x0002 /* b1: PIPE1 */
234 #define BRDY0 0x0001 /* b1: PIPE0 */
235
236 /* NRDY Interrupt Enable/Status Register */
237 #define NRDY9 0x0200 /* b9: PIPE9 */
238 #define NRDY8 0x0100 /* b8: PIPE8 */
239 #define NRDY7 0x0080 /* b7: PIPE7 */
240 #define NRDY6 0x0040 /* b6: PIPE6 */
241 #define NRDY5 0x0020 /* b5: PIPE5 */
242 #define NRDY4 0x0010 /* b4: PIPE4 */
243 #define NRDY3 0x0008 /* b3: PIPE3 */
244 #define NRDY2 0x0004 /* b2: PIPE2 */
245 #define NRDY1 0x0002 /* b1: PIPE1 */
246 #define NRDY0 0x0001 /* b1: PIPE0 */
247
248 /* BEMP Interrupt Enable/Status Register */
249 #define BEMP9 0x0200 /* b9: PIPE9 */
250 #define BEMP8 0x0100 /* b8: PIPE8 */
251 #define BEMP7 0x0080 /* b7: PIPE7 */
252 #define BEMP6 0x0040 /* b6: PIPE6 */
253 #define BEMP5 0x0020 /* b5: PIPE5 */
254 #define BEMP4 0x0010 /* b4: PIPE4 */
255 #define BEMP3 0x0008 /* b3: PIPE3 */
256 #define BEMP2 0x0004 /* b2: PIPE2 */
257 #define BEMP1 0x0002 /* b1: PIPE1 */
258 #define BEMP0 0x0001 /* b0: PIPE0 */
259
260 /* SOF Pin Configuration Register */
261 #define TRNENSEL 0x0100 /* b8: Select transaction enable period */
262 #define BRDYM 0x0040 /* b6: BRDY clear timing */
263 #define INTL 0x0020 /* b5: Interrupt sense select */
264 #define EDGESTS 0x0010 /* b4: */
265 #define SOFMODE 0x000C /* b3-2: SOF pin select */
266 #define SOF_125US 0x0008 /* SOF OUT 125us Frame Signal */
267 #define SOF_1MS 0x0004 /* SOF OUT 1ms Frame Signal */
268 #define SOF_DISABLE 0x0000 /* SOF OUT Disable */
269
270 /* Interrupt Status Register 0 */
271 #define VBINT 0x8000 /* b15: VBUS interrupt */
272 #define RESM 0x4000 /* b14: Resume interrupt */
273 #define SOFR 0x2000 /* b13: SOF frame update interrupt */
274 #define DVST 0x1000 /* b12: Device state transition interrupt */
275 #define CTRT 0x0800 /* b11: Control transfer stage transition interrupt */
276 #define BEMP 0x0400 /* b10: Buffer empty interrupt */
277 #define NRDY 0x0200 /* b9: Buffer not ready interrupt */
278 #define BRDY 0x0100 /* b8: Buffer ready interrupt */
279 #define VBSTS 0x0080 /* b7: VBUS input port */
280 #define DVSQ 0x0070 /* b6-4: Device state */
281 #define DS_SPD_CNFG 0x0070 /* Suspend Configured */
282 #define DS_SPD_ADDR 0x0060 /* Suspend Address */
283 #define DS_SPD_DFLT 0x0050 /* Suspend Default */
284 #define DS_SPD_POWR 0x0040 /* Suspend Powered */
285 #define DS_SUSP 0x0040 /* Suspend */
286 #define DS_CNFG 0x0030 /* Configured */
287 #define DS_ADDS 0x0020 /* Address */
288 #define DS_DFLT 0x0010 /* Default */
289 #define DS_POWR 0x0000 /* Powered */
290 #define DVSQS 0x0030 /* b5-4: Device state */
291 #define VALID 0x0008 /* b3: Setup packet detected flag */
292 #define CTSQ 0x0007 /* b2-0: Control transfer stage */
293 #define CS_SQER 0x0006 /* Sequence error */
294 #define CS_WRND 0x0005 /* Control write nodata status stage */
295 #define CS_WRSS 0x0004 /* Control write status stage */
296 #define CS_WRDS 0x0003 /* Control write data stage */
297 #define CS_RDSS 0x0002 /* Control read status stage */
298 #define CS_RDDS 0x0001 /* Control read data stage */
299 #define CS_IDST 0x0000 /* Idle or setup stage */
300
301 /* Interrupt Status Register 1 */
302 #define OVRCR 0x8000 /* b15: Over-current interrupt */
303 #define BCHG 0x4000 /* b14: USB bus chenge interrupt */
304 #define DTCH 0x1000 /* b12: Detach sense interrupt */
305 #define ATTCH 0x0800 /* b11: Attach sense interrupt */
306 #define EOFERR 0x0040 /* b6: EOF-error interrupt */
307 #define SIGN 0x0020 /* b5: Setup ignore interrupt */
308 #define SACK 0x0010 /* b4: Setup acknowledge interrupt */
309
310 /* Frame Number Register */
311 #define OVRN 0x8000 /* b15: Overrun error */
312 #define CRCE 0x4000 /* b14: Received data error */
313 #define FRNM 0x07FF /* b10-0: Frame number */
314
315 /* Micro Frame Number Register */
316 #define UFRNM 0x0007 /* b2-0: Micro frame number */
317
318 /* Default Control Pipe Maxpacket Size Register */
319 /* Pipe Maxpacket Size Register */
320 #define DEVSEL 0xF000 /* b15-14: Device address select */
321 #define MAXP 0x007F /* b6-0: Maxpacket size of default control pipe */
322
323 /* Default Control Pipe Control Register */
324 #define BSTS 0x8000 /* b15: Buffer status */
325 #define SUREQ 0x4000 /* b14: Send USB request */
326 #define CSCLR 0x2000 /* b13: complete-split status clear */
327 #define CSSTS 0x1000 /* b12: complete-split status */
328 #define SUREQCLR 0x0800 /* b11: stop setup request */
329 #define SQCLR 0x0100 /* b8: Sequence toggle bit clear */
330 #define SQSET 0x0080 /* b7: Sequence toggle bit set */
331 #define SQMON 0x0040 /* b6: Sequence toggle bit monitor */
332 #define PBUSY 0x0020 /* b5: pipe busy */
333 #define PINGE 0x0010 /* b4: ping enable */
334 #define CCPL 0x0004 /* b2: Enable control transfer complete */
335 #define PID 0x0003 /* b1-0: Response PID */
336 #define PID_STALL11 0x0003 /* STALL */
337 #define PID_STALL 0x0002 /* STALL */
338 #define PID_BUF 0x0001 /* BUF */
339 #define PID_NAK 0x0000 /* NAK */
340
341 /* Pipe Window Select Register */
342 #define PIPENM 0x0007 /* b2-0: Pipe select */
343
344 /* Pipe Configuration Register */
345 #define R8A66597_TYP 0xC000 /* b15-14: Transfer type */
346 #define R8A66597_ISO 0xC000 /* Isochronous */
347 #define R8A66597_INT 0x8000 /* Interrupt */
348 #define R8A66597_BULK 0x4000 /* Bulk */
349 #define R8A66597_BFRE 0x0400 /* b10: Buffer ready interrupt mode select */
350 #define R8A66597_DBLB 0x0200 /* b9: Double buffer mode select */
351 #define R8A66597_CNTMD 0x0100 /* b8: Continuous transfer mode select */
352 #define R8A66597_SHTNAK 0x0080 /* b7: Transfer end NAK */
353 #define R8A66597_DIR 0x0010 /* b4: Transfer direction select */
354 #define R8A66597_EPNUM 0x000F /* b3-0: Eendpoint number select */
355
356 /* Pipe Buffer Configuration Register */
357 #define BUFSIZE 0x7C00 /* b14-10: Pipe buffer size */
358 #define BUFNMB 0x007F /* b6-0: Pipe buffer number */
359 #define PIPE0BUF 256
360 #define PIPExBUF 64
361
362 /* Pipe Maxpacket Size Register */
363 #define MXPS 0x07FF /* b10-0: Maxpacket size */
364
365 /* Pipe Cycle Configuration Register */
366 #define IFIS 0x1000 /* b12: Isochronous in-buffer flush mode select */
367 #define IITV 0x0007 /* b2-0: Isochronous interval */
368
369 /* Pipex Control Register */
370 #define BSTS 0x8000 /* b15: Buffer status */
371 #define INBUFM 0x4000 /* b14: IN buffer monitor (Only for PIPE1 to 5) */
372 #define CSCLR 0x2000 /* b13: complete-split status clear */
373 #define CSSTS 0x1000 /* b12: complete-split status */
374 #define ATREPM 0x0400 /* b10: Auto repeat mode */
375 #define ACLRM 0x0200 /* b9: Out buffer auto clear mode */
376 #define SQCLR 0x0100 /* b8: Sequence toggle bit clear */
377 #define SQSET 0x0080 /* b7: Sequence toggle bit set */
378 #define SQMON 0x0040 /* b6: Sequence toggle bit monitor */
379 #define PBUSY 0x0020 /* b5: pipe busy */
380 #define PID 0x0003 /* b1-0: Response PID */
381
382 /* PIPExTRE */
383 #define TRENB 0x0200 /* b9: Transaction counter enable */
384 #define TRCLR 0x0100 /* b8: Transaction counter clear */
385
386 /* PIPExTRN */
387 #define TRNCNT 0xFFFF /* b15-0: Transaction counter */
388
389 /* DEVADDx */
390 #define UPPHUB 0x7800
391 #define HUBPORT 0x0700
392 #define USBSPD 0x00C0
393 #define RTPORT 0x0001
394
395 /* Suspend Mode Register */
396 #define SUSPM 0x4000 /* b14: Suspend */
397
398 #define R8A66597_MAX_NUM_PIPE 10
399 #define R8A66597_BUF_BSIZE 8
400 #define R8A66597_MAX_DEVICE 10
401 #if defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
402 #define R8A66597_MAX_ROOT_HUB 1
403 #else
404 #define R8A66597_MAX_ROOT_HUB 2
405 #endif
406 #define R8A66597_MAX_SAMPLING 5
407 #define R8A66597_RH_POLL_TIME 10
408
409 #define BULK_IN_PIPENUM 3
410 #define BULK_IN_BUFNUM 8
411
412 #define BULK_OUT_PIPENUM 4
413 #define BULK_OUT_BUFNUM 40
414
415 #define check_bulk_or_isoc(pipenum) ((pipenum >= 1 && pipenum <= 5))
416 #define check_interrupt(pipenum) ((pipenum >= 6 && pipenum <= 9))
417 #define make_devsel(addr) (addr << 12)
418
419 struct r8a66597 {
420 unsigned long reg;
421 unsigned short pipe_config; /* bit field */
422 unsigned short port_status;
423 unsigned short port_change;
424 u16 speed; /* HSMODE or FSMODE or LSMODE */
425 unsigned char rh_devnum;
426 };
427
r8a66597_read(struct r8a66597 * r8a66597,unsigned long offset)428 static inline u16 r8a66597_read(struct r8a66597 *r8a66597, unsigned long offset)
429 {
430 return inw(r8a66597->reg + offset);
431 }
432
r8a66597_read_fifo(struct r8a66597 * r8a66597,unsigned long offset,void * buf,int len)433 static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
434 unsigned long offset, void *buf,
435 int len)
436 {
437 int i;
438 #if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) || defined(CONFIG_RZA_USB)
439 unsigned long fifoaddr = r8a66597->reg + offset;
440 unsigned long count;
441 unsigned long *p = buf;
442
443 count = len / 4;
444 for (i = 0; i < count; i++)
445 p[i] = inl(r8a66597->reg + offset);
446
447 if (len & 0x00000003) {
448 unsigned long tmp = inl(fifoaddr);
449 memcpy((unsigned char *)buf + count * 4, &tmp, len & 0x03);
450 }
451 #else
452 unsigned short *p = buf;
453
454 len = (len + 1) / 2;
455 for (i = 0; i < len; i++)
456 p[i] = inw(r8a66597->reg + offset);
457 #endif
458 }
459
r8a66597_write(struct r8a66597 * r8a66597,u16 val,unsigned long offset)460 static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val,
461 unsigned long offset)
462 {
463 outw(val, r8a66597->reg + offset);
464 }
465
r8a66597_write_fifo(struct r8a66597 * r8a66597,unsigned long offset,void * buf,int len)466 static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
467 unsigned long offset, void *buf,
468 int len)
469 {
470 int i;
471 unsigned long fifoaddr = r8a66597->reg + offset;
472 #if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) || defined(CONFIG_RZA_USB)
473 unsigned long count;
474 unsigned char *pb;
475 unsigned long *p = buf;
476
477 count = len / 4;
478 for (i = 0; i < count; i++)
479 outl(p[i], fifoaddr);
480
481 if (len & 0x00000003) {
482 pb = (unsigned char *)buf + count * 4;
483 for (i = 0; i < (len & 0x00000003); i++) {
484 if (r8a66597_read(r8a66597, CFIFOSEL) & BIGEND)
485 outb(pb[i], fifoaddr + i);
486 else
487 outb(pb[i], fifoaddr + 3 - i);
488 }
489 }
490 #else
491 int odd = len & 0x0001;
492 unsigned short *p = buf;
493
494 len = len / 2;
495 for (i = 0; i < len; i++)
496 outw(p[i], fifoaddr);
497
498 if (odd) {
499 unsigned char *pb = (unsigned char *)(buf + len);
500 outb(*pb, fifoaddr);
501 }
502 #endif
503 }
504
r8a66597_mdfy(struct r8a66597 * r8a66597,u16 val,u16 pat,unsigned long offset)505 static inline void r8a66597_mdfy(struct r8a66597 *r8a66597,
506 u16 val, u16 pat, unsigned long offset)
507 {
508 u16 tmp;
509 tmp = r8a66597_read(r8a66597, offset);
510 tmp = tmp & (~pat);
511 tmp = tmp | val;
512 r8a66597_write(r8a66597, tmp, offset);
513 }
514
515 #define r8a66597_bclr(r8a66597, val, offset) \
516 r8a66597_mdfy(r8a66597, 0, val, offset)
517 #define r8a66597_bset(r8a66597, val, offset) \
518 r8a66597_mdfy(r8a66597, val, 0, offset)
519
get_syscfg_reg(int port)520 static inline unsigned long get_syscfg_reg(int port)
521 {
522 return port == 0 ? SYSCFG0 : SYSCFG1;
523 }
524
get_syssts_reg(int port)525 static inline unsigned long get_syssts_reg(int port)
526 {
527 return port == 0 ? SYSSTS0 : SYSSTS1;
528 }
529
get_dvstctr_reg(int port)530 static inline unsigned long get_dvstctr_reg(int port)
531 {
532 return port == 0 ? DVSTCTR0 : DVSTCTR1;
533 }
534
get_dmacfg_reg(int port)535 static inline unsigned long get_dmacfg_reg(int port)
536 {
537 return port == 0 ? DMA0CFG : DMA1CFG;
538 }
539
get_intenb_reg(int port)540 static inline unsigned long get_intenb_reg(int port)
541 {
542 return port == 0 ? INTENB1 : INTENB2;
543 }
544
get_intsts_reg(int port)545 static inline unsigned long get_intsts_reg(int port)
546 {
547 return port == 0 ? INTSTS1 : INTSTS2;
548 }
549
get_rh_usb_speed(struct r8a66597 * r8a66597,int port)550 static inline u16 get_rh_usb_speed(struct r8a66597 *r8a66597, int port)
551 {
552 unsigned long dvstctr_reg = get_dvstctr_reg(port);
553
554 return r8a66597_read(r8a66597, dvstctr_reg) & RHST;
555 }
556
r8a66597_port_power(struct r8a66597 * r8a66597,int port,int power)557 static inline void r8a66597_port_power(struct r8a66597 *r8a66597, int port,
558 int power)
559 {
560 unsigned long dvstctr_reg = get_dvstctr_reg(port);
561
562 if (power)
563 r8a66597_bset(r8a66597, VBOUT, dvstctr_reg);
564 else
565 r8a66597_bclr(r8a66597, VBOUT, dvstctr_reg);
566 }
567
568 #define get_pipectr_addr(pipenum) (PIPE1CTR + (pipenum - 1) * 2)
569 #define get_pipetre_addr(pipenum) (PIPE1TRE + (pipenum - 1) * 4)
570 #define get_pipetrn_addr(pipenum) (PIPE1TRN + (pipenum - 1) * 4)
571 #define get_devadd_addr(address) (DEVADD0 + address * 2)
572
573
574 /* USB HUB CONSTANTS (not OHCI-specific; see hub.h, based on usb_ohci.h) */
575
576 /* destination of request */
577 #define RH_INTERFACE 0x01
578 #define RH_ENDPOINT 0x02
579 #define RH_OTHER 0x03
580
581 #define RH_CLASS 0x20
582 #define RH_VENDOR 0x40
583
584 /* Requests: bRequest << 8 | bmRequestType */
585 #define RH_GET_STATUS 0x0080
586 #define RH_CLEAR_FEATURE 0x0100
587 #define RH_SET_FEATURE 0x0300
588 #define RH_SET_ADDRESS 0x0500
589 #define RH_GET_DESCRIPTOR 0x0680
590 #define RH_SET_DESCRIPTOR 0x0700
591 #define RH_GET_CONFIGURATION 0x0880
592 #define RH_SET_CONFIGURATION 0x0900
593 #define RH_GET_STATE 0x0280
594 #define RH_GET_INTERFACE 0x0A80
595 #define RH_SET_INTERFACE 0x0B00
596 #define RH_SYNC_FRAME 0x0C80
597 /* Our Vendor Specific Request */
598 #define RH_SET_EP 0x2000
599
600 /* Hub port features */
601 #define RH_PORT_CONNECTION 0x00
602 #define RH_PORT_ENABLE 0x01
603 #define RH_PORT_SUSPEND 0x02
604 #define RH_PORT_OVER_CURRENT 0x03
605 #define RH_PORT_RESET 0x04
606 #define RH_PORT_POWER 0x08
607 #define RH_PORT_LOW_SPEED 0x09
608
609 #define RH_C_PORT_CONNECTION 0x10
610 #define RH_C_PORT_ENABLE 0x11
611 #define RH_C_PORT_SUSPEND 0x12
612 #define RH_C_PORT_OVER_CURRENT 0x13
613 #define RH_C_PORT_RESET 0x14
614
615 /* Hub features */
616 #define RH_C_HUB_LOCAL_POWER 0x00
617 #define RH_C_HUB_OVER_CURRENT 0x01
618
619 #define RH_DEVICE_REMOTE_WAKEUP 0x00
620 #define RH_ENDPOINT_STALL 0x01
621
622 #define RH_ACK 0x01
623 #define RH_REQ_ERR -1
624 #define RH_NACK 0x00
625
626 /* OHCI ROOT HUB REGISTER MASKS */
627
628 /* roothub.portstatus [i] bits */
629 #define RH_PS_CCS 0x00000001 /* current connect status */
630 #define RH_PS_PES 0x00000002 /* port enable status*/
631 #define RH_PS_PSS 0x00000004 /* port suspend status */
632 #define RH_PS_POCI 0x00000008 /* port over current indicator */
633 #define RH_PS_PRS 0x00000010 /* port reset status */
634 #define RH_PS_PPS 0x00000100 /* port power status */
635 #define RH_PS_LSDA 0x00000200 /* low speed device attached */
636 #define RH_PS_CSC 0x00010000 /* connect status change */
637 #define RH_PS_PESC 0x00020000 /* port enable status change */
638 #define RH_PS_PSSC 0x00040000 /* port suspend status change */
639 #define RH_PS_OCIC 0x00080000 /* over current indicator change */
640 #define RH_PS_PRSC 0x00100000 /* port reset status change */
641
642 /* roothub.status bits */
643 #define RH_HS_LPS 0x00000001 /* local power status */
644 #define RH_HS_OCI 0x00000002 /* over current indicator */
645 #define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */
646 #define RH_HS_LPSC 0x00010000 /* local power status change */
647 #define RH_HS_OCIC 0x00020000 /* over current indicator change */
648 #define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */
649
650 /* roothub.b masks */
651 #define RH_B_DR 0x0000ffff /* device removable flags */
652 #define RH_B_PPCM 0xffff0000 /* port power control mask */
653
654 /* roothub.a masks */
655 #define RH_A_NDP (0xff << 0) /* number of downstream ports */
656 #define RH_A_PSM (1 << 8) /* power switching mode */
657 #define RH_A_NPS (1 << 9) /* no power switching */
658 #define RH_A_DT (1 << 10) /* device type (mbz) */
659 #define RH_A_OCPM (1 << 11) /* over current protection mode */
660 #define RH_A_NOCP (1 << 12) /* no over current protection */
661 #define RH_A_POTPGT (0xff << 24) /* power on to power good time */
662
663 #endif /* __R8A66597_H__ */
664