xref: /openbmc/linux/drivers/ata/pata_ns87415.c (revision 3fc2febb)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  *    pata_ns87415.c - NS87415 (and PARISC SUPERIO 87560) PATA
4  *
5  *	(C) 2005 Red Hat <alan@lxorguk.ukuu.org.uk>
6  *
7  *    This is a fairly generic MWDMA controller. It has some limitations
8  *    as it requires timing reloads on PIO/DMA transitions but it is otherwise
9  *    fairly well designed.
10  *
11  *    This driver assumes the firmware has left the chip in a valid ST506
12  *    compliant state, either legacy IRQ 14/15 or native INTA shared. You
13  *    may need to add platform code if your system fails to do this.
14  *
15  *    The same cell appears in the 87560 controller used by some PARISC
16  *    systems. This has its own special mountain of errata.
17  *
18  *    TODO:
19  *	Get someone to test on SPARC
20  *	Implement lazy pio/dma switching for better performance
21  *	8bit shared timing.
22  *	See if we need to kill the FIFO for ATAPI
23  */
24 
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28 #include <linux/blkdev.h>
29 #include <linux/delay.h>
30 #include <linux/device.h>
31 #include <scsi/scsi_host.h>
32 #include <linux/libata.h>
33 #include <linux/ata.h>
34 
35 #define DRV_NAME	"pata_ns87415"
36 #define DRV_VERSION	"0.0.1"
37 
38 /**
39  *	ns87415_set_mode - Initialize host controller mode timings
40  *	@ap: Port whose timings we are configuring
41  *	@adev: Device whose timings we are configuring
42  *	@mode: Mode to set
43  *
44  *	Program the mode registers for this controller, channel and
45  *	device. Because the chip is quite an old design we have to do this
46  *	for PIO/DMA switches.
47  *
48  *	LOCKING:
49  *	None (inherited from caller).
50  */
51 
ns87415_set_mode(struct ata_port * ap,struct ata_device * adev,u8 mode)52 static void ns87415_set_mode(struct ata_port *ap, struct ata_device *adev, u8 mode)
53 {
54 	struct pci_dev *dev	= to_pci_dev(ap->host->dev);
55 	int unit		= 2 * ap->port_no + adev->devno;
56 	int timing		= 0x44 + 2 * unit;
57 	unsigned long T		= 1000000000 / 33333;	/* PCI clocks */
58 	struct ata_timing t;
59 	u16 clocking;
60 	u8 iordy;
61 	u8 status;
62 
63 	/* Timing register format is 17 - low nybble read timing with
64 	   the high nybble being 16 - x for recovery time in PCI clocks */
65 
66 	ata_timing_compute(adev, adev->pio_mode, &t, T, 0);
67 
68 	clocking = 17 - clamp_val(t.active, 2, 17);
69 	clocking |= (16 - clamp_val(t.recover, 1, 16)) << 4;
70  	/* Use the same timing for read and write bytes */
71 	clocking |= (clocking << 8);
72 	pci_write_config_word(dev, timing, clocking);
73 
74 	/* Set the IORDY enable versus DMA enable on or off properly */
75 	pci_read_config_byte(dev, 0x42, &iordy);
76 	iordy &= ~(1 << (4 + unit));
77 	if (mode >= XFER_MW_DMA_0 || !ata_pio_need_iordy(adev))
78 		iordy |= (1 << (4 + unit));
79 
80 	/* Paranoia: We shouldn't ever get here with busy write buffers
81 	   but if so wait */
82 
83 	pci_read_config_byte(dev, 0x43, &status);
84 	while (status & 0x03) {
85 		udelay(1);
86 		pci_read_config_byte(dev, 0x43, &status);
87 	}
88 	/* Flip the IORDY/DMA bits now we are sure the write buffers are
89 	   clear */
90 	pci_write_config_byte(dev, 0x42, iordy);
91 
92 	/* TODO: Set byte 54 command timing to the best 8bit
93 	   mode shared by all four devices */
94 }
95 
96 /**
97  *	ns87415_set_piomode - Initialize host controller PATA PIO timings
98  *	@ap: Port whose timings we are configuring
99  *	@adev: Device to program
100  *
101  *	Set PIO mode for device, in host controller PCI config space.
102  *
103  *	LOCKING:
104  *	None (inherited from caller).
105  */
106 
ns87415_set_piomode(struct ata_port * ap,struct ata_device * adev)107 static void ns87415_set_piomode(struct ata_port *ap, struct ata_device *adev)
108 {
109 	ns87415_set_mode(ap, adev, adev->pio_mode);
110 }
111 
112 /**
113  *	ns87415_bmdma_setup		-	Set up DMA
114  *	@qc: Command block
115  *
116  *	Set up for bus mastering DMA. We have to do this ourselves
117  *	rather than use the helper due to a chip erratum
118  */
119 
ns87415_bmdma_setup(struct ata_queued_cmd * qc)120 static void ns87415_bmdma_setup(struct ata_queued_cmd *qc)
121 {
122 	struct ata_port *ap = qc->ap;
123 	unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
124 	u8 dmactl;
125 
126 	/* load PRD table addr. */
127 	mb();	/* make sure PRD table writes are visible to controller */
128 	iowrite32(ap->bmdma_prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
129 
130 	/* specify data direction, triple-check start bit is clear */
131 	dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
132 	dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
133 	/* Due to an erratum we need to write these bits to the wrong
134 	   place - which does save us an I/O bizarrely */
135 	dmactl |= ATA_DMA_INTR | ATA_DMA_ERR;
136 	if (!rw)
137 		dmactl |= ATA_DMA_WR;
138 	iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
139 	/* issue r/w command */
140 	ap->ops->sff_exec_command(ap, &qc->tf);
141 }
142 
143 /**
144  *	ns87415_bmdma_start		-	Begin DMA transfer
145  *	@qc: Command block
146  *
147  *	Switch the timings for the chip and set up for a DMA transfer
148  *	before the DMA burst begins.
149  *
150  *	FIXME: We should do lazy switching on bmdma_start versus
151  *	ata_pio_data_xfer for better performance.
152  */
153 
ns87415_bmdma_start(struct ata_queued_cmd * qc)154 static void ns87415_bmdma_start(struct ata_queued_cmd *qc)
155 {
156 	ns87415_set_mode(qc->ap, qc->dev, qc->dev->dma_mode);
157 	ata_bmdma_start(qc);
158 }
159 
160 /**
161  *	ns87415_bmdma_stop		-	End DMA transfer
162  *	@qc: Command block
163  *
164  *	End DMA mode and switch the controller back into PIO mode
165  */
166 
ns87415_bmdma_stop(struct ata_queued_cmd * qc)167 static void ns87415_bmdma_stop(struct ata_queued_cmd *qc)
168 {
169 	ata_bmdma_stop(qc);
170 	ns87415_set_mode(qc->ap, qc->dev, qc->dev->pio_mode);
171 }
172 
173 /**
174  *	ns87415_irq_clear		-	Clear interrupt
175  *	@ap: Channel to clear
176  *
177  *	Erratum: Due to a chip bug registers 02 and 0A bit 1 and 2 (the
178  *	error bits) are reset by writing to register 00 or 08.
179  */
180 
ns87415_irq_clear(struct ata_port * ap)181 static void ns87415_irq_clear(struct ata_port *ap)
182 {
183 	void __iomem *mmio = ap->ioaddr.bmdma_addr;
184 
185 	if (!mmio)
186 		return;
187 	iowrite8((ioread8(mmio + ATA_DMA_CMD) | ATA_DMA_INTR | ATA_DMA_ERR),
188 			mmio + ATA_DMA_CMD);
189 }
190 
191 /**
192  *	ns87415_check_atapi_dma		-	ATAPI DMA filter
193  *	@qc: Command block
194  *
195  *	Disable ATAPI DMA (for now). We may be able to do DMA if we
196  *	kill the prefetching. This isn't clear.
197  */
198 
ns87415_check_atapi_dma(struct ata_queued_cmd * qc)199 static int ns87415_check_atapi_dma(struct ata_queued_cmd *qc)
200 {
201 	return -EOPNOTSUPP;
202 }
203 
204 #if defined(CONFIG_SUPERIO)
205 
206 /* SUPERIO 87560 is a PoS chip that NatSem denies exists.
207  * Unfortunately, it's built-in on all Astro-based PA-RISC workstations
208  * which use the integrated NS87514 cell for CD-ROM support.
209  * i.e we have to support for CD-ROM installs.
210  * See drivers/parisc/superio.c for more gory details.
211  *
212  * Workarounds taken from drivers/ide/pci/ns87415.c
213  */
214 
215 #include <asm/superio.h>
216 
217 #define SUPERIO_IDE_MAX_RETRIES 25
218 
219 /**
220  *	ns87560_read_buggy	-	workaround buggy Super I/O chip
221  *	@port: Port to read
222  *
223  *	Work around chipset problems in the 87560 SuperIO chip
224  */
225 
ns87560_read_buggy(void __iomem * port)226 static u8 ns87560_read_buggy(void __iomem *port)
227 {
228 	u8 tmp;
229 	int retries = SUPERIO_IDE_MAX_RETRIES;
230 	do {
231 		tmp = ioread8(port);
232 		if (tmp != 0)
233 			return tmp;
234 		udelay(50);
235 	} while(retries-- > 0);
236 	return tmp;
237 }
238 
239 /**
240  *	ns87560_check_status
241  *	@ap: channel to check
242  *
243  *	Return the status of the channel working around the
244  *	87560 flaws.
245  */
246 
ns87560_check_status(struct ata_port * ap)247 static u8 ns87560_check_status(struct ata_port *ap)
248 {
249 	return ns87560_read_buggy(ap->ioaddr.status_addr);
250 }
251 
252 /**
253  *	ns87560_tf_read - input device's ATA taskfile shadow registers
254  *	@ap: Port from which input is read
255  *	@tf: ATA taskfile register set for storing input
256  *
257  *	Reads ATA taskfile registers for currently-selected device
258  *	into @tf. Work around the 87560 bugs.
259  *
260  *	LOCKING:
261  *	Inherited from caller.
262  */
ns87560_tf_read(struct ata_port * ap,struct ata_taskfile * tf)263 static void ns87560_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
264 {
265 	struct ata_ioports *ioaddr = &ap->ioaddr;
266 
267 	tf->status = ns87560_check_status(ap);
268 	tf->error = ioread8(ioaddr->error_addr);
269 	tf->nsect = ioread8(ioaddr->nsect_addr);
270 	tf->lbal = ioread8(ioaddr->lbal_addr);
271 	tf->lbam = ioread8(ioaddr->lbam_addr);
272 	tf->lbah = ioread8(ioaddr->lbah_addr);
273 	tf->device = ns87560_read_buggy(ioaddr->device_addr);
274 
275 	if (tf->flags & ATA_TFLAG_LBA48) {
276 		iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
277 		tf->hob_feature = ioread8(ioaddr->error_addr);
278 		tf->hob_nsect = ioread8(ioaddr->nsect_addr);
279 		tf->hob_lbal = ioread8(ioaddr->lbal_addr);
280 		tf->hob_lbam = ioread8(ioaddr->lbam_addr);
281 		tf->hob_lbah = ioread8(ioaddr->lbah_addr);
282 		iowrite8(tf->ctl, ioaddr->ctl_addr);
283 		ap->last_ctl = tf->ctl;
284 	}
285 }
286 
287 /**
288  *	ns87560_bmdma_status
289  *	@ap: channel to check
290  *
291  *	Return the DMA status of the channel working around the
292  *	87560 flaws.
293  */
294 
ns87560_bmdma_status(struct ata_port * ap)295 static u8 ns87560_bmdma_status(struct ata_port *ap)
296 {
297 	return ns87560_read_buggy(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
298 }
299 #endif		/* 87560 SuperIO Support */
300 
301 static struct ata_port_operations ns87415_pata_ops = {
302 	.inherits		= &ata_bmdma_port_ops,
303 
304 	.check_atapi_dma	= ns87415_check_atapi_dma,
305 	.bmdma_setup		= ns87415_bmdma_setup,
306 	.bmdma_start		= ns87415_bmdma_start,
307 	.bmdma_stop		= ns87415_bmdma_stop,
308 	.sff_irq_clear		= ns87415_irq_clear,
309 
310 	.cable_detect		= ata_cable_40wire,
311 	.set_piomode		= ns87415_set_piomode,
312 };
313 
314 #if defined(CONFIG_SUPERIO)
315 static struct ata_port_operations ns87560_pata_ops = {
316 	.inherits		= &ns87415_pata_ops,
317 	.sff_tf_read		= ns87560_tf_read,
318 	.sff_check_status	= ns87560_check_status,
319 	.bmdma_status		= ns87560_bmdma_status,
320 };
321 #endif
322 
323 static const struct scsi_host_template ns87415_sht = {
324 	ATA_BMDMA_SHT(DRV_NAME),
325 };
326 
ns87415_fixup(struct pci_dev * pdev)327 static void ns87415_fixup(struct pci_dev *pdev)
328 {
329 	/* Select 512 byte sectors */
330 	pci_write_config_byte(pdev, 0x55, 0xEE);
331 	/* Select PIO0 8bit clocking */
332 	pci_write_config_byte(pdev, 0x54, 0xB7);
333 }
334 
335 /**
336  *	ns87415_init_one - Register 87415 ATA PCI device with kernel services
337  *	@pdev: PCI device to register
338  *	@ent: Entry in ns87415_pci_tbl matching with @pdev
339  *
340  *	Called from kernel PCI layer.  We probe for combined mode (sigh),
341  *	and then hand over control to libata, for it to do the rest.
342  *
343  *	LOCKING:
344  *	Inherited from PCI layer (may sleep).
345  *
346  *	RETURNS:
347  *	Zero on success, or -ERRNO value.
348  */
349 
ns87415_init_one(struct pci_dev * pdev,const struct pci_device_id * ent)350 static int ns87415_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
351 {
352 	static const struct ata_port_info info = {
353 		.flags		= ATA_FLAG_SLAVE_POSS,
354 		.pio_mask	= ATA_PIO4,
355 		.mwdma_mask	= ATA_MWDMA2,
356 		.port_ops	= &ns87415_pata_ops,
357 	};
358 	const struct ata_port_info *ppi[] = { &info, NULL };
359 	int rc;
360 #if defined(CONFIG_SUPERIO)
361 	static const struct ata_port_info info87560 = {
362 		.flags		= ATA_FLAG_SLAVE_POSS,
363 		.pio_mask	= ATA_PIO4,
364 		.mwdma_mask	= ATA_MWDMA2,
365 		.port_ops	= &ns87560_pata_ops,
366 	};
367 
368 	if (PCI_SLOT(pdev->devfn) == 0x0E)
369 		ppi[0] = &info87560;
370 #endif
371 	ata_print_version_once(&pdev->dev, DRV_VERSION);
372 
373 	rc = pcim_enable_device(pdev);
374 	if (rc)
375 		return rc;
376 
377 	ns87415_fixup(pdev);
378 
379 	return ata_pci_bmdma_init_one(pdev, ppi, &ns87415_sht, NULL, 0);
380 }
381 
382 static const struct pci_device_id ns87415_pci_tbl[] = {
383 	{ PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_87415), },
384 
385 	{ }	/* terminate list */
386 };
387 
388 #ifdef CONFIG_PM_SLEEP
ns87415_reinit_one(struct pci_dev * pdev)389 static int ns87415_reinit_one(struct pci_dev *pdev)
390 {
391 	struct ata_host *host = pci_get_drvdata(pdev);
392 	int rc;
393 
394 	rc = ata_pci_device_do_resume(pdev);
395 	if (rc)
396 		return rc;
397 
398 	ns87415_fixup(pdev);
399 
400 	ata_host_resume(host);
401 	return 0;
402 }
403 #endif
404 
405 static struct pci_driver ns87415_pci_driver = {
406 	.name			= DRV_NAME,
407 	.id_table		= ns87415_pci_tbl,
408 	.probe			= ns87415_init_one,
409 	.remove			= ata_pci_remove_one,
410 #ifdef CONFIG_PM_SLEEP
411 	.suspend		= ata_pci_device_suspend,
412 	.resume			= ns87415_reinit_one,
413 #endif
414 };
415 
416 module_pci_driver(ns87415_pci_driver);
417 
418 MODULE_AUTHOR("Alan Cox");
419 MODULE_DESCRIPTION("ATA low-level driver for NS87415 controllers");
420 MODULE_LICENSE("GPL");
421 MODULE_DEVICE_TABLE(pci, ns87415_pci_tbl);
422 MODULE_VERSION(DRV_VERSION);
423