1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2021-2022 Bootlin 4 * Author: Paul Kocialkowski <paul.kocialkowski@bootlin.com> 5 */ 6 7 #ifndef _SUN6I_ISP_REG_H_ 8 #define _SUN6I_ISP_REG_H_ 9 10 #include <linux/kernel.h> 11 12 #define SUN6I_ISP_ADDR_VALUE(a) ((a) >> 2) 13 14 /* Frontend */ 15 16 #define SUN6I_ISP_SRC_MODE_DRAM 0 17 #define SUN6I_ISP_SRC_MODE_CSI(n) (1 + (n)) 18 19 #define SUN6I_ISP_FE_CFG_REG 0x0 20 #define SUN6I_ISP_FE_CFG_EN BIT(0) 21 #define SUN6I_ISP_FE_CFG_SRC0_MODE(v) (((v) << 8) & GENMASK(9, 8)) 22 #define SUN6I_ISP_FE_CFG_SRC1_MODE(v) (((v) << 16) & GENMASK(17, 16)) 23 24 #define SUN6I_ISP_FE_CTRL_REG 0x4 25 #define SUN6I_ISP_FE_CTRL_SCAP_EN BIT(0) 26 #define SUN6I_ISP_FE_CTRL_VCAP_EN BIT(1) 27 #define SUN6I_ISP_FE_CTRL_PARA_READY BIT(2) 28 #define SUN6I_ISP_FE_CTRL_LUT_UPDATE BIT(3) 29 #define SUN6I_ISP_FE_CTRL_LENS_UPDATE BIT(4) 30 #define SUN6I_ISP_FE_CTRL_GAMMA_UPDATE BIT(5) 31 #define SUN6I_ISP_FE_CTRL_DRC_UPDATE BIT(6) 32 #define SUN6I_ISP_FE_CTRL_DISC_UPDATE BIT(7) 33 #define SUN6I_ISP_FE_CTRL_OUTPUT_SPEED_CTRL(v) (((v) << 16) & GENMASK(17, 16)) 34 #define SUN6I_ISP_FE_CTRL_VCAP_READ_START BIT(31) 35 36 #define SUN6I_ISP_FE_INT_EN_REG 0x8 37 #define SUN6I_ISP_FE_INT_EN_FINISH BIT(0) 38 #define SUN6I_ISP_FE_INT_EN_START BIT(1) 39 #define SUN6I_ISP_FE_INT_EN_PARA_SAVE BIT(2) 40 #define SUN6I_ISP_FE_INT_EN_PARA_LOAD BIT(3) 41 #define SUN6I_ISP_FE_INT_EN_SRC0_FIFO BIT(4) 42 #define SUN6I_ISP_FE_INT_EN_SRC1_FIFO BIT(5) 43 #define SUN6I_ISP_FE_INT_EN_ROT_FINISH BIT(6) 44 #define SUN6I_ISP_FE_INT_EN_LINE_NUM_START BIT(7) 45 46 #define SUN6I_ISP_FE_INT_STA_REG 0xc 47 #define SUN6I_ISP_FE_INT_STA_CLEAR 0xff 48 #define SUN6I_ISP_FE_INT_STA_FINISH BIT(0) 49 #define SUN6I_ISP_FE_INT_STA_START BIT(1) 50 #define SUN6I_ISP_FE_INT_STA_PARA_SAVE BIT(2) 51 #define SUN6I_ISP_FE_INT_STA_PARA_LOAD BIT(3) 52 #define SUN6I_ISP_FE_INT_STA_SRC0_FIFO BIT(4) 53 #define SUN6I_ISP_FE_INT_STA_SRC1_FIFO BIT(5) 54 #define SUN6I_ISP_FE_INT_STA_ROT_FINISH BIT(6) 55 #define SUN6I_ISP_FE_INT_STA_LINE_NUM_START BIT(7) 56 57 /* Only since sun9i-a80-isp. */ 58 #define SUN6I_ISP_FE_INT_LINE_NUM_REG 0x18 59 #define SUN6I_ISP_FE_ROT_OF_CFG_REG 0x1c 60 61 /* Buffers/tables */ 62 63 #define SUN6I_ISP_REG_LOAD_ADDR_REG 0x20 64 #define SUN6I_ISP_REG_SAVE_ADDR_REG 0x24 65 66 #define SUN6I_ISP_LUT_TABLE_ADDR_REG 0x28 67 #define SUN6I_ISP_DRC_TABLE_ADDR_REG 0x2c 68 #define SUN6I_ISP_STATS_ADDR_REG 0x30 69 70 /* SRAM */ 71 72 #define SUN6I_ISP_SRAM_RW_OFFSET_REG 0x38 73 #define SUN6I_ISP_SRAM_RW_DATA_REG 0x3c 74 75 /* Global */ 76 77 #define SUN6I_ISP_MODULE_EN_REG 0x40 78 #define SUN6I_ISP_MODULE_EN_AE BIT(0) 79 #define SUN6I_ISP_MODULE_EN_OBC BIT(1) 80 #define SUN6I_ISP_MODULE_EN_DPC_LUT BIT(2) 81 #define SUN6I_ISP_MODULE_EN_DPC_OTF BIT(3) 82 #define SUN6I_ISP_MODULE_EN_BDNF BIT(4) 83 #define SUN6I_ISP_MODULE_EN_AWB BIT(6) 84 #define SUN6I_ISP_MODULE_EN_WB BIT(7) 85 #define SUN6I_ISP_MODULE_EN_LSC BIT(8) 86 #define SUN6I_ISP_MODULE_EN_BGC BIT(9) 87 #define SUN6I_ISP_MODULE_EN_SAP BIT(10) 88 #define SUN6I_ISP_MODULE_EN_AF BIT(11) 89 #define SUN6I_ISP_MODULE_EN_RGB2RGB BIT(12) 90 #define SUN6I_ISP_MODULE_EN_RGB_DRC BIT(13) 91 #define SUN6I_ISP_MODULE_EN_TDNF BIT(15) 92 #define SUN6I_ISP_MODULE_EN_AFS BIT(16) 93 #define SUN6I_ISP_MODULE_EN_HIST BIT(17) 94 #define SUN6I_ISP_MODULE_EN_YUV_GAIN_OFFSET BIT(18) 95 #define SUN6I_ISP_MODULE_EN_YUV_DRC BIT(19) 96 #define SUN6I_ISP_MODULE_EN_TG BIT(20) 97 #define SUN6I_ISP_MODULE_EN_ROT BIT(21) 98 #define SUN6I_ISP_MODULE_EN_CONTRAST BIT(22) 99 #define SUN6I_ISP_MODULE_EN_SATU BIT(24) 100 #define SUN6I_ISP_MODULE_EN_SRC1 BIT(30) 101 #define SUN6I_ISP_MODULE_EN_SRC0 BIT(31) 102 103 #define SUN6I_ISP_MODE_REG 0x44 104 #define SUN6I_ISP_MODE_INPUT_FMT(v) ((v) & GENMASK(2, 0)) 105 #define SUN6I_ISP_MODE_INPUT_YUV_SEQ(v) (((v) << 3) & GENMASK(4, 3)) 106 #define SUN6I_ISP_MODE_OTF_DPC(v) (((v) << 16) & BIT(16)) 107 #define SUN6I_ISP_MODE_SHARP(v) (((v) << 17) & BIT(17)) 108 #define SUN6I_ISP_MODE_HIST(v) (((v) << 20) & GENMASK(21, 20)) 109 110 #define SUN6I_ISP_INPUT_FMT_YUV420 0 111 #define SUN6I_ISP_INPUT_FMT_YUV422 1 112 #define SUN6I_ISP_INPUT_FMT_RAW_BGGR 4 113 #define SUN6I_ISP_INPUT_FMT_RAW_RGGB 5 114 #define SUN6I_ISP_INPUT_FMT_RAW_GBRG 6 115 #define SUN6I_ISP_INPUT_FMT_RAW_GRBG 7 116 117 #define SUN6I_ISP_INPUT_YUV_SEQ_YUYV 0 118 #define SUN6I_ISP_INPUT_YUV_SEQ_YVYU 1 119 #define SUN6I_ISP_INPUT_YUV_SEQ_UYVY 2 120 #define SUN6I_ISP_INPUT_YUV_SEQ_VYUY 3 121 122 #define SUN6I_ISP_IN_CFG_REG 0x48 123 #define SUN6I_ISP_IN_CFG_STRIDE_DIV16(v) ((v) & GENMASK(10, 0)) 124 125 #define SUN6I_ISP_IN_LUMA_RGB_ADDR0_REG 0x4c 126 #define SUN6I_ISP_IN_CHROMA_ADDR0_REG 0x50 127 #define SUN6I_ISP_IN_LUMA_RGB_ADDR1_REG 0x54 128 #define SUN6I_ISP_IN_CHROMA_ADDR1_REG 0x58 129 130 /* AE */ 131 132 #define SUN6I_ISP_AE_CFG_REG 0x60 133 #define SUN6I_ISP_AE_CFG_LOW_BRI_TH(v) ((v) & GENMASK(11, 0)) 134 #define SUN6I_ISP_AE_CFG_HORZ_NUM(v) (((v) << 12) & GENMASK(15, 12)) 135 #define SUN6I_ISP_AE_CFG_HIGH_BRI_TH(v) (((v) << 16) & GENMASK(27, 16)) 136 #define SUN6I_ISP_AE_CFG_VERT_NUM(v) (((v) << 28) & GENMASK(31, 28)) 137 138 #define SUN6I_ISP_AE_SIZE_REG 0x64 139 #define SUN6I_ISP_AE_SIZE_WIDTH(v) ((v) & GENMASK(10, 0)) 140 #define SUN6I_ISP_AE_SIZE_HEIGHT(v) (((v) << 16) & GENMASK(26, 16)) 141 142 #define SUN6I_ISP_AE_POS_REG 0x68 143 #define SUN6I_ISP_AE_POS_HORZ_START(v) ((v) & GENMASK(10, 0)) 144 #define SUN6I_ISP_AE_POS_VERT_START(v) (((v) << 16) & GENMASK(26, 16)) 145 146 /* OB */ 147 148 #define SUN6I_ISP_OB_SIZE_REG 0x78 149 #define SUN6I_ISP_OB_SIZE_WIDTH(v) ((v) & GENMASK(13, 0)) 150 #define SUN6I_ISP_OB_SIZE_HEIGHT(v) (((v) << 16) & GENMASK(29, 16)) 151 152 #define SUN6I_ISP_OB_VALID_REG 0x7c 153 #define SUN6I_ISP_OB_VALID_WIDTH(v) ((v) & GENMASK(12, 0)) 154 #define SUN6I_ISP_OB_VALID_HEIGHT(v) (((v) << 16) & GENMASK(28, 16)) 155 156 #define SUN6I_ISP_OB_SRC0_VALID_START_REG 0x80 157 #define SUN6I_ISP_OB_SRC0_VALID_START_HORZ(v) ((v) & GENMASK(11, 0)) 158 #define SUN6I_ISP_OB_SRC0_VALID_START_VERT(v) (((v) << 16) & GENMASK(27, 16)) 159 160 #define SUN6I_ISP_OB_SRC1_VALID_START_REG 0x84 161 #define SUN6I_ISP_OB_SRC1_VALID_START_HORZ(v) ((v) & GENMASK(11, 0)) 162 #define SUN6I_ISP_OB_SRC1_VALID_START_VERT(v) (((v) << 16) & GENMASK(27, 16)) 163 164 #define SUN6I_ISP_OB_SPRITE_REG 0x88 165 #define SUN6I_ISP_OB_SPRITE_WIDTH(v) ((v) & GENMASK(12, 0)) 166 #define SUN6I_ISP_OB_SPRITE_HEIGHT(v) (((v) << 16) & GENMASK(28, 16)) 167 168 #define SUN6I_ISP_OB_SPRITE_START_REG 0x8c 169 #define SUN6I_ISP_OB_SPRITE_START_HORZ(v) ((v) & GENMASK(11, 0)) 170 #define SUN6I_ISP_OB_SPRITE_START_VERT(v) (((v) << 16) & GENMASK(27, 16)) 171 172 #define SUN6I_ISP_OB_CFG_REG 0x90 173 #define SUN6I_ISP_OB_HORZ_POS_REG 0x94 174 #define SUN6I_ISP_OB_VERT_PARA_REG 0x98 175 #define SUN6I_ISP_OB_OFFSET_FIXED_REG 0x9c 176 177 /* BDNF */ 178 179 #define SUN6I_ISP_BDNF_CFG_REG 0xcc 180 #define SUN6I_ISP_BDNF_CFG_IN_DIS_MIN(v) ((v) & GENMASK(7, 0)) 181 #define SUN6I_ISP_BDNF_CFG_IN_DIS_MAX(v) (((v) << 16) & GENMASK(23, 16)) 182 183 #define SUN6I_ISP_BDNF_COEF_RB_REG 0xd0 184 #define SUN6I_ISP_BDNF_COEF_RB(i, v) (((v) << (4 * (i))) & \ 185 GENMASK(4 * (i) + 3, 4 * (i))) 186 187 #define SUN6I_ISP_BDNF_COEF_G_REG 0xd4 188 #define SUN6I_ISP_BDNF_COEF_G(i, v) (((v) << (4 * (i))) & \ 189 GENMASK(4 * (i) + 3, 4 * (i))) 190 191 /* Bayer */ 192 193 #define SUN6I_ISP_BAYER_OFFSET0_REG 0xe0 194 #define SUN6I_ISP_BAYER_OFFSET0_R(v) ((v) & GENMASK(12, 0)) 195 #define SUN6I_ISP_BAYER_OFFSET0_GR(v) (((v) << 16) & GENMASK(28, 16)) 196 197 #define SUN6I_ISP_BAYER_OFFSET1_REG 0xe4 198 #define SUN6I_ISP_BAYER_OFFSET1_GB(v) ((v) & GENMASK(12, 0)) 199 #define SUN6I_ISP_BAYER_OFFSET1_B(v) (((v) << 16) & GENMASK(28, 16)) 200 201 #define SUN6I_ISP_BAYER_GAIN0_REG 0xe8 202 #define SUN6I_ISP_BAYER_GAIN0_R(v) ((v) & GENMASK(11, 0)) 203 #define SUN6I_ISP_BAYER_GAIN0_GR(v) (((v) << 16) & GENMASK(27, 16)) 204 205 #define SUN6I_ISP_BAYER_GAIN1_REG 0xec 206 #define SUN6I_ISP_BAYER_GAIN1_GB(v) ((v) & GENMASK(11, 0)) 207 #define SUN6I_ISP_BAYER_GAIN1_B(v) (((v) << 16) & GENMASK(27, 16)) 208 209 /* WB */ 210 211 #define SUN6I_ISP_WB_GAIN0_REG 0x140 212 #define SUN6I_ISP_WB_GAIN0_R(v) ((v) & GENMASK(11, 0)) 213 #define SUN6I_ISP_WB_GAIN0_GR(v) (((v) << 16) & GENMASK(27, 16)) 214 215 #define SUN6I_ISP_WB_GAIN1_REG 0x144 216 #define SUN6I_ISP_WB_GAIN1_GB(v) ((v) & GENMASK(11, 0)) 217 #define SUN6I_ISP_WB_GAIN1_B(v) (((v) << 16) & GENMASK(27, 16)) 218 219 #define SUN6I_ISP_WB_CFG_REG 0x148 220 #define SUN6I_ISP_WB_CFG_CLIP(v) ((v) & GENMASK(11, 0)) 221 222 /* Global */ 223 224 #define SUN6I_ISP_MCH_SIZE_CFG_REG 0x1e0 225 #define SUN6I_ISP_MCH_SIZE_CFG_WIDTH(v) ((v) & GENMASK(12, 0)) 226 #define SUN6I_ISP_MCH_SIZE_CFG_HEIGHT(v) (((v) << 16) & GENMASK(28, 16)) 227 228 #define SUN6I_ISP_MCH_SCALE_CFG_REG 0x1e4 229 #define SUN6I_ISP_MCH_SCALE_CFG_X_RATIO(v) ((v) & GENMASK(11, 0)) 230 #define SUN6I_ISP_MCH_SCALE_CFG_Y_RATIO(v) (((v) << 16) & GENMASK(27, 16)) 231 #define SUN6I_ISP_MCH_SCALE_CFG_WEIGHT_SHIFT(v) (((v) << 28) & GENMASK(31, 28)) 232 233 #define SUN6I_ISP_SCH_SIZE_CFG_REG 0x1e8 234 #define SUN6I_ISP_SCH_SIZE_CFG_WIDTH(v) ((v) & GENMASK(12, 0)) 235 #define SUN6I_ISP_SCH_SIZE_CFG_HEIGHT(v) (((v) << 16) & GENMASK(28, 16)) 236 237 #define SUN6I_ISP_SCH_SCALE_CFG_REG 0x1ec 238 #define SUN6I_ISP_SCH_SCALE_CFG_X_RATIO(v) ((v) & GENMASK(11, 0)) 239 #define SUN6I_ISP_SCH_SCALE_CFG_Y_RATIO(v) (((v) << 16) & GENMASK(27, 16)) 240 #define SUN6I_ISP_SCH_SCALE_CFG_WEIGHT_SHIFT(v) (((v) << 28) & GENMASK(31, 28)) 241 242 #define SUN6I_ISP_MCH_CFG_REG 0x1f0 243 #define SUN6I_ISP_MCH_CFG_EN BIT(0) 244 #define SUN6I_ISP_MCH_CFG_SCALE_EN BIT(1) 245 #define SUN6I_ISP_MCH_CFG_OUTPUT_FMT(v) (((v) << 2) & GENMASK(4, 2)) 246 #define SUN6I_ISP_MCH_CFG_MIRROR_EN BIT(5) 247 #define SUN6I_ISP_MCH_CFG_FLIP_EN BIT(6) 248 #define SUN6I_ISP_MCH_CFG_STRIDE_Y_DIV4(v) (((v) << 8) & GENMASK(18, 8)) 249 #define SUN6I_ISP_MCH_CFG_STRIDE_UV_DIV4(v) (((v) << 20) & GENMASK(30, 20)) 250 251 #define SUN6I_ISP_OUTPUT_FMT_YUV420SP 0 252 #define SUN6I_ISP_OUTPUT_FMT_YUV422SP 1 253 #define SUN6I_ISP_OUTPUT_FMT_YVU420SP 2 254 #define SUN6I_ISP_OUTPUT_FMT_YVU422SP 3 255 #define SUN6I_ISP_OUTPUT_FMT_YUV420P 4 256 #define SUN6I_ISP_OUTPUT_FMT_YUV422P 5 257 #define SUN6I_ISP_OUTPUT_FMT_YVU420P 6 258 #define SUN6I_ISP_OUTPUT_FMT_YVU422P 7 259 260 #define SUN6I_ISP_SCH_CFG_REG 0x1f4 261 262 #define SUN6I_ISP_MCH_Y_ADDR0_REG 0x1f8 263 #define SUN6I_ISP_MCH_U_ADDR0_REG 0x1fc 264 #define SUN6I_ISP_MCH_V_ADDR0_REG 0x200 265 #define SUN6I_ISP_MCH_Y_ADDR1_REG 0x204 266 #define SUN6I_ISP_MCH_U_ADDR1_REG 0x208 267 #define SUN6I_ISP_MCH_V_ADDR1_REG 0x20c 268 #define SUN6I_ISP_SCH_Y_ADDR0_REG 0x210 269 #define SUN6I_ISP_SCH_U_ADDR0_REG 0x214 270 #define SUN6I_ISP_SCH_V_ADDR0_REG 0x218 271 #define SUN6I_ISP_SCH_Y_ADDR1_REG 0x21c 272 #define SUN6I_ISP_SCH_U_ADDR1_REG 0x220 273 #define SUN6I_ISP_SCH_V_ADDR1_REG 0x224 274 275 #endif 276