1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * ALSA SoC SPDIF Audio Layer
4 *
5 * Copyright 2015 Andrea Venturi <be17068@iperbole.bo.it>
6 * Copyright 2015 Marcus Cooper <codekipper@gmail.com>
7 *
8 * Based on the Allwinner SDK driver, released under the GPL.
9 */
10
11 #include <linux/clk.h>
12 #include <linux/delay.h>
13 #include <linux/device.h>
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/regmap.h>
17 #include <linux/of_address.h>
18 #include <linux/of_device.h>
19 #include <linux/ioport.h>
20 #include <linux/module.h>
21 #include <linux/platform_device.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/reset.h>
24 #include <linux/spinlock.h>
25 #include <sound/asoundef.h>
26 #include <sound/dmaengine_pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/soc.h>
29
30 #define SUN4I_SPDIF_CTL (0x00)
31 #define SUN4I_SPDIF_CTL_MCLKDIV(v) ((v) << 4) /* v even */
32 #define SUN4I_SPDIF_CTL_MCLKOUTEN BIT(2)
33 #define SUN4I_SPDIF_CTL_GEN BIT(1)
34 #define SUN4I_SPDIF_CTL_RESET BIT(0)
35
36 #define SUN4I_SPDIF_TXCFG (0x04)
37 #define SUN4I_SPDIF_TXCFG_SINGLEMOD BIT(31)
38 #define SUN4I_SPDIF_TXCFG_ASS BIT(17)
39 #define SUN4I_SPDIF_TXCFG_NONAUDIO BIT(16)
40 #define SUN4I_SPDIF_TXCFG_TXRATIO(v) ((v) << 4)
41 #define SUN4I_SPDIF_TXCFG_TXRATIO_MASK GENMASK(8, 4)
42 #define SUN4I_SPDIF_TXCFG_FMTRVD GENMASK(3, 2)
43 #define SUN4I_SPDIF_TXCFG_FMT16BIT (0 << 2)
44 #define SUN4I_SPDIF_TXCFG_FMT20BIT (1 << 2)
45 #define SUN4I_SPDIF_TXCFG_FMT24BIT (2 << 2)
46 #define SUN4I_SPDIF_TXCFG_CHSTMODE BIT(1)
47 #define SUN4I_SPDIF_TXCFG_TXEN BIT(0)
48
49 #define SUN4I_SPDIF_RXCFG (0x08)
50 #define SUN4I_SPDIF_RXCFG_LOCKFLAG BIT(4)
51 #define SUN4I_SPDIF_RXCFG_CHSTSRC BIT(3)
52 #define SUN4I_SPDIF_RXCFG_CHSTCP BIT(1)
53 #define SUN4I_SPDIF_RXCFG_RXEN BIT(0)
54
55 #define SUN4I_SPDIF_TXFIFO (0x0C)
56
57 #define SUN4I_SPDIF_RXFIFO (0x10)
58
59 #define SUN4I_SPDIF_FCTL (0x14)
60 #define SUN4I_SPDIF_FCTL_FIFOSRC BIT(31)
61 #define SUN4I_SPDIF_FCTL_FTX BIT(17)
62 #define SUN4I_SPDIF_FCTL_FRX BIT(16)
63 #define SUN4I_SPDIF_FCTL_TXTL(v) ((v) << 8)
64 #define SUN4I_SPDIF_FCTL_TXTL_MASK GENMASK(12, 8)
65 #define SUN4I_SPDIF_FCTL_RXTL(v) ((v) << 3)
66 #define SUN4I_SPDIF_FCTL_RXTL_MASK GENMASK(7, 3)
67 #define SUN4I_SPDIF_FCTL_TXIM BIT(2)
68 #define SUN4I_SPDIF_FCTL_RXOM(v) ((v) << 0)
69 #define SUN4I_SPDIF_FCTL_RXOM_MASK GENMASK(1, 0)
70
71 #define SUN50I_H6_SPDIF_FCTL (0x14)
72 #define SUN50I_H6_SPDIF_FCTL_HUB_EN BIT(31)
73 #define SUN50I_H6_SPDIF_FCTL_FTX BIT(30)
74 #define SUN50I_H6_SPDIF_FCTL_FRX BIT(29)
75 #define SUN50I_H6_SPDIF_FCTL_TXTL(v) ((v) << 12)
76 #define SUN50I_H6_SPDIF_FCTL_TXTL_MASK GENMASK(19, 12)
77 #define SUN50I_H6_SPDIF_FCTL_RXTL(v) ((v) << 4)
78 #define SUN50I_H6_SPDIF_FCTL_RXTL_MASK GENMASK(10, 4)
79 #define SUN50I_H6_SPDIF_FCTL_TXIM BIT(2)
80 #define SUN50I_H6_SPDIF_FCTL_RXOM(v) ((v) << 0)
81 #define SUN50I_H6_SPDIF_FCTL_RXOM_MASK GENMASK(1, 0)
82
83 #define SUN4I_SPDIF_FSTA (0x18)
84 #define SUN4I_SPDIF_FSTA_TXE BIT(14)
85 #define SUN4I_SPDIF_FSTA_TXECNTSHT (8)
86 #define SUN4I_SPDIF_FSTA_RXA BIT(6)
87 #define SUN4I_SPDIF_FSTA_RXACNTSHT (0)
88
89 #define SUN4I_SPDIF_INT (0x1C)
90 #define SUN4I_SPDIF_INT_RXLOCKEN BIT(18)
91 #define SUN4I_SPDIF_INT_RXUNLOCKEN BIT(17)
92 #define SUN4I_SPDIF_INT_RXPARERREN BIT(16)
93 #define SUN4I_SPDIF_INT_TXDRQEN BIT(7)
94 #define SUN4I_SPDIF_INT_TXUIEN BIT(6)
95 #define SUN4I_SPDIF_INT_TXOIEN BIT(5)
96 #define SUN4I_SPDIF_INT_TXEIEN BIT(4)
97 #define SUN4I_SPDIF_INT_RXDRQEN BIT(2)
98 #define SUN4I_SPDIF_INT_RXOIEN BIT(1)
99 #define SUN4I_SPDIF_INT_RXAIEN BIT(0)
100
101 #define SUN4I_SPDIF_ISTA (0x20)
102 #define SUN4I_SPDIF_ISTA_RXLOCKSTA BIT(18)
103 #define SUN4I_SPDIF_ISTA_RXUNLOCKSTA BIT(17)
104 #define SUN4I_SPDIF_ISTA_RXPARERRSTA BIT(16)
105 #define SUN4I_SPDIF_ISTA_TXUSTA BIT(6)
106 #define SUN4I_SPDIF_ISTA_TXOSTA BIT(5)
107 #define SUN4I_SPDIF_ISTA_TXESTA BIT(4)
108 #define SUN4I_SPDIF_ISTA_RXOSTA BIT(1)
109 #define SUN4I_SPDIF_ISTA_RXASTA BIT(0)
110
111 #define SUN8I_SPDIF_TXFIFO (0x20)
112
113 #define SUN4I_SPDIF_TXCNT (0x24)
114
115 #define SUN4I_SPDIF_RXCNT (0x28)
116
117 #define SUN4I_SPDIF_TXCHSTA0 (0x2C)
118 #define SUN4I_SPDIF_TXCHSTA0_CLK(v) ((v) << 28)
119 #define SUN4I_SPDIF_TXCHSTA0_SAMFREQ(v) ((v) << 24)
120 #define SUN4I_SPDIF_TXCHSTA0_SAMFREQ_MASK GENMASK(27, 24)
121 #define SUN4I_SPDIF_TXCHSTA0_CHNUM(v) ((v) << 20)
122 #define SUN4I_SPDIF_TXCHSTA0_CHNUM_MASK GENMASK(23, 20)
123 #define SUN4I_SPDIF_TXCHSTA0_SRCNUM(v) ((v) << 16)
124 #define SUN4I_SPDIF_TXCHSTA0_CATACOD(v) ((v) << 8)
125 #define SUN4I_SPDIF_TXCHSTA0_MODE(v) ((v) << 6)
126 #define SUN4I_SPDIF_TXCHSTA0_EMPHASIS(v) ((v) << 3)
127 #define SUN4I_SPDIF_TXCHSTA0_CP BIT(2)
128 #define SUN4I_SPDIF_TXCHSTA0_AUDIO BIT(1)
129 #define SUN4I_SPDIF_TXCHSTA0_PRO BIT(0)
130
131 #define SUN4I_SPDIF_TXCHSTA1 (0x30)
132 #define SUN4I_SPDIF_TXCHSTA1_CGMSA(v) ((v) << 8)
133 #define SUN4I_SPDIF_TXCHSTA1_ORISAMFREQ(v) ((v) << 4)
134 #define SUN4I_SPDIF_TXCHSTA1_ORISAMFREQ_MASK GENMASK(7, 4)
135 #define SUN4I_SPDIF_TXCHSTA1_SAMWORDLEN(v) ((v) << 1)
136 #define SUN4I_SPDIF_TXCHSTA1_MAXWORDLEN BIT(0)
137
138 #define SUN4I_SPDIF_RXCHSTA0 (0x34)
139 #define SUN4I_SPDIF_RXCHSTA0_CLK(v) ((v) << 28)
140 #define SUN4I_SPDIF_RXCHSTA0_SAMFREQ(v) ((v) << 24)
141 #define SUN4I_SPDIF_RXCHSTA0_CHNUM(v) ((v) << 20)
142 #define SUN4I_SPDIF_RXCHSTA0_SRCNUM(v) ((v) << 16)
143 #define SUN4I_SPDIF_RXCHSTA0_CATACOD(v) ((v) << 8)
144 #define SUN4I_SPDIF_RXCHSTA0_MODE(v) ((v) << 6)
145 #define SUN4I_SPDIF_RXCHSTA0_EMPHASIS(v) ((v) << 3)
146 #define SUN4I_SPDIF_RXCHSTA0_CP BIT(2)
147 #define SUN4I_SPDIF_RXCHSTA0_AUDIO BIT(1)
148 #define SUN4I_SPDIF_RXCHSTA0_PRO BIT(0)
149
150 #define SUN4I_SPDIF_RXCHSTA1 (0x38)
151 #define SUN4I_SPDIF_RXCHSTA1_CGMSA(v) ((v) << 8)
152 #define SUN4I_SPDIF_RXCHSTA1_ORISAMFREQ(v) ((v) << 4)
153 #define SUN4I_SPDIF_RXCHSTA1_SAMWORDLEN(v) ((v) << 1)
154 #define SUN4I_SPDIF_RXCHSTA1_MAXWORDLEN BIT(0)
155
156 /* Defines for Sampling Frequency */
157 #define SUN4I_SPDIF_SAMFREQ_44_1KHZ 0x0
158 #define SUN4I_SPDIF_SAMFREQ_NOT_INDICATED 0x1
159 #define SUN4I_SPDIF_SAMFREQ_48KHZ 0x2
160 #define SUN4I_SPDIF_SAMFREQ_32KHZ 0x3
161 #define SUN4I_SPDIF_SAMFREQ_22_05KHZ 0x4
162 #define SUN4I_SPDIF_SAMFREQ_24KHZ 0x6
163 #define SUN4I_SPDIF_SAMFREQ_88_2KHZ 0x8
164 #define SUN4I_SPDIF_SAMFREQ_76_8KHZ 0x9
165 #define SUN4I_SPDIF_SAMFREQ_96KHZ 0xa
166 #define SUN4I_SPDIF_SAMFREQ_176_4KHZ 0xc
167 #define SUN4I_SPDIF_SAMFREQ_192KHZ 0xe
168
169 /**
170 * struct sun4i_spdif_quirks - Differences between SoC variants.
171 *
172 * @reg_dac_txdata: TX FIFO offset for DMA config.
173 * @has_reset: SoC needs reset deasserted.
174 * @val_fctl_ftx: TX FIFO flush bitmask.
175 */
176 struct sun4i_spdif_quirks {
177 unsigned int reg_dac_txdata;
178 bool has_reset;
179 unsigned int val_fctl_ftx;
180 unsigned int mclk_multiplier;
181 };
182
183 struct sun4i_spdif_dev {
184 struct platform_device *pdev;
185 struct clk *spdif_clk;
186 struct clk *apb_clk;
187 struct reset_control *rst;
188 struct snd_soc_dai_driver cpu_dai_drv;
189 struct regmap *regmap;
190 struct snd_dmaengine_dai_dma_data dma_params_tx;
191 const struct sun4i_spdif_quirks *quirks;
192 spinlock_t lock;
193 };
194
sun4i_spdif_configure(struct sun4i_spdif_dev * host)195 static void sun4i_spdif_configure(struct sun4i_spdif_dev *host)
196 {
197 const struct sun4i_spdif_quirks *quirks = host->quirks;
198
199 /* soft reset SPDIF */
200 regmap_write(host->regmap, SUN4I_SPDIF_CTL, SUN4I_SPDIF_CTL_RESET);
201
202 /* flush TX FIFO */
203 regmap_update_bits(host->regmap, SUN4I_SPDIF_FCTL,
204 quirks->val_fctl_ftx, quirks->val_fctl_ftx);
205
206 /* clear TX counter */
207 regmap_write(host->regmap, SUN4I_SPDIF_TXCNT, 0);
208 }
209
sun4i_snd_txctrl_on(struct snd_pcm_substream * substream,struct sun4i_spdif_dev * host)210 static void sun4i_snd_txctrl_on(struct snd_pcm_substream *substream,
211 struct sun4i_spdif_dev *host)
212 {
213 if (substream->runtime->channels == 1)
214 regmap_update_bits(host->regmap, SUN4I_SPDIF_TXCFG,
215 SUN4I_SPDIF_TXCFG_SINGLEMOD,
216 SUN4I_SPDIF_TXCFG_SINGLEMOD);
217
218 /* SPDIF TX ENABLE */
219 regmap_update_bits(host->regmap, SUN4I_SPDIF_TXCFG,
220 SUN4I_SPDIF_TXCFG_TXEN, SUN4I_SPDIF_TXCFG_TXEN);
221
222 /* DRQ ENABLE */
223 regmap_update_bits(host->regmap, SUN4I_SPDIF_INT,
224 SUN4I_SPDIF_INT_TXDRQEN, SUN4I_SPDIF_INT_TXDRQEN);
225
226 /* Global enable */
227 regmap_update_bits(host->regmap, SUN4I_SPDIF_CTL,
228 SUN4I_SPDIF_CTL_GEN, SUN4I_SPDIF_CTL_GEN);
229 }
230
sun4i_snd_txctrl_off(struct snd_pcm_substream * substream,struct sun4i_spdif_dev * host)231 static void sun4i_snd_txctrl_off(struct snd_pcm_substream *substream,
232 struct sun4i_spdif_dev *host)
233 {
234 /* SPDIF TX DISABLE */
235 regmap_update_bits(host->regmap, SUN4I_SPDIF_TXCFG,
236 SUN4I_SPDIF_TXCFG_TXEN, 0);
237
238 /* DRQ DISABLE */
239 regmap_update_bits(host->regmap, SUN4I_SPDIF_INT,
240 SUN4I_SPDIF_INT_TXDRQEN, 0);
241
242 /* Global disable */
243 regmap_update_bits(host->regmap, SUN4I_SPDIF_CTL,
244 SUN4I_SPDIF_CTL_GEN, 0);
245 }
246
sun4i_spdif_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * cpu_dai)247 static int sun4i_spdif_startup(struct snd_pcm_substream *substream,
248 struct snd_soc_dai *cpu_dai)
249 {
250 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
251 struct sun4i_spdif_dev *host = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
252
253 if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
254 return -EINVAL;
255
256 sun4i_spdif_configure(host);
257
258 return 0;
259 }
260
sun4i_spdif_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * cpu_dai)261 static int sun4i_spdif_hw_params(struct snd_pcm_substream *substream,
262 struct snd_pcm_hw_params *params,
263 struct snd_soc_dai *cpu_dai)
264 {
265 int ret = 0;
266 int fmt;
267 unsigned long rate = params_rate(params);
268 u32 mclk_div = 0;
269 unsigned int mclk = 0;
270 u32 reg_val;
271 struct sun4i_spdif_dev *host = snd_soc_dai_get_drvdata(cpu_dai);
272 struct platform_device *pdev = host->pdev;
273
274 /* Add the PCM and raw data select interface */
275 switch (params_channels(params)) {
276 case 1: /* PCM mode */
277 case 2:
278 fmt = 0;
279 break;
280 case 4: /* raw data mode */
281 fmt = SUN4I_SPDIF_TXCFG_NONAUDIO;
282 break;
283 default:
284 return -EINVAL;
285 }
286
287 switch (params_format(params)) {
288 case SNDRV_PCM_FORMAT_S16_LE:
289 fmt |= SUN4I_SPDIF_TXCFG_FMT16BIT;
290 break;
291 case SNDRV_PCM_FORMAT_S20_3LE:
292 fmt |= SUN4I_SPDIF_TXCFG_FMT20BIT;
293 break;
294 case SNDRV_PCM_FORMAT_S24_LE:
295 fmt |= SUN4I_SPDIF_TXCFG_FMT24BIT;
296 break;
297 default:
298 return -EINVAL;
299 }
300
301 switch (rate) {
302 case 22050:
303 case 44100:
304 case 88200:
305 case 176400:
306 mclk = 22579200;
307 break;
308 case 24000:
309 case 32000:
310 case 48000:
311 case 96000:
312 case 192000:
313 mclk = 24576000;
314 break;
315 default:
316 return -EINVAL;
317 }
318 mclk *= host->quirks->mclk_multiplier;
319
320 ret = clk_set_rate(host->spdif_clk, mclk);
321 if (ret < 0) {
322 dev_err(&pdev->dev,
323 "Setting SPDIF clock rate for %d Hz failed!\n", mclk);
324 return ret;
325 }
326
327 regmap_update_bits(host->regmap, SUN4I_SPDIF_FCTL,
328 SUN4I_SPDIF_FCTL_TXIM, SUN4I_SPDIF_FCTL_TXIM);
329
330 switch (rate) {
331 case 22050:
332 case 24000:
333 mclk_div = 8;
334 break;
335 case 32000:
336 mclk_div = 6;
337 break;
338 case 44100:
339 case 48000:
340 mclk_div = 4;
341 break;
342 case 88200:
343 case 96000:
344 mclk_div = 2;
345 break;
346 case 176400:
347 case 192000:
348 mclk_div = 1;
349 break;
350 default:
351 return -EINVAL;
352 }
353 mclk_div *= host->quirks->mclk_multiplier;
354
355 reg_val = 0;
356 reg_val |= SUN4I_SPDIF_TXCFG_ASS;
357 reg_val |= fmt; /* set non audio and bit depth */
358 reg_val |= SUN4I_SPDIF_TXCFG_CHSTMODE;
359 reg_val |= SUN4I_SPDIF_TXCFG_TXRATIO(mclk_div - 1);
360 regmap_write(host->regmap, SUN4I_SPDIF_TXCFG, reg_val);
361
362 return 0;
363 }
364
sun4i_spdif_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)365 static int sun4i_spdif_trigger(struct snd_pcm_substream *substream, int cmd,
366 struct snd_soc_dai *dai)
367 {
368 int ret = 0;
369 struct sun4i_spdif_dev *host = snd_soc_dai_get_drvdata(dai);
370
371 if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
372 return -EINVAL;
373
374 switch (cmd) {
375 case SNDRV_PCM_TRIGGER_START:
376 case SNDRV_PCM_TRIGGER_RESUME:
377 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
378 sun4i_snd_txctrl_on(substream, host);
379 break;
380
381 case SNDRV_PCM_TRIGGER_STOP:
382 case SNDRV_PCM_TRIGGER_SUSPEND:
383 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
384 sun4i_snd_txctrl_off(substream, host);
385 break;
386
387 default:
388 ret = -EINVAL;
389 break;
390 }
391 return ret;
392 }
393
sun4i_spdif_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)394 static int sun4i_spdif_info(struct snd_kcontrol *kcontrol,
395 struct snd_ctl_elem_info *uinfo)
396 {
397 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
398 uinfo->count = 1;
399
400 return 0;
401 }
402
sun4i_spdif_get_status_mask(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)403 static int sun4i_spdif_get_status_mask(struct snd_kcontrol *kcontrol,
404 struct snd_ctl_elem_value *ucontrol)
405 {
406 u8 *status = ucontrol->value.iec958.status;
407
408 status[0] = 0xff;
409 status[1] = 0xff;
410 status[2] = 0xff;
411 status[3] = 0xff;
412 status[4] = 0xff;
413 status[5] = 0x03;
414
415 return 0;
416 }
417
sun4i_spdif_get_status(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)418 static int sun4i_spdif_get_status(struct snd_kcontrol *kcontrol,
419 struct snd_ctl_elem_value *ucontrol)
420 {
421 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
422 struct sun4i_spdif_dev *host = snd_soc_dai_get_drvdata(cpu_dai);
423 u8 *status = ucontrol->value.iec958.status;
424 unsigned long flags;
425 unsigned int reg;
426
427 spin_lock_irqsave(&host->lock, flags);
428
429 regmap_read(host->regmap, SUN4I_SPDIF_TXCHSTA0, ®);
430
431 status[0] = reg & 0xff;
432 status[1] = (reg >> 8) & 0xff;
433 status[2] = (reg >> 16) & 0xff;
434 status[3] = (reg >> 24) & 0xff;
435
436 regmap_read(host->regmap, SUN4I_SPDIF_TXCHSTA1, ®);
437
438 status[4] = reg & 0xff;
439 status[5] = (reg >> 8) & 0x3;
440
441 spin_unlock_irqrestore(&host->lock, flags);
442
443 return 0;
444 }
445
sun4i_spdif_set_status(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)446 static int sun4i_spdif_set_status(struct snd_kcontrol *kcontrol,
447 struct snd_ctl_elem_value *ucontrol)
448 {
449 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
450 struct sun4i_spdif_dev *host = snd_soc_dai_get_drvdata(cpu_dai);
451 u8 *status = ucontrol->value.iec958.status;
452 unsigned long flags;
453 unsigned int reg;
454 bool chg0, chg1;
455
456 spin_lock_irqsave(&host->lock, flags);
457
458 reg = (u32)status[3] << 24;
459 reg |= (u32)status[2] << 16;
460 reg |= (u32)status[1] << 8;
461 reg |= (u32)status[0];
462
463 regmap_update_bits_check(host->regmap, SUN4I_SPDIF_TXCHSTA0,
464 GENMASK(31,0), reg, &chg0);
465
466 reg = (u32)status[5] << 8;
467 reg |= (u32)status[4];
468
469 regmap_update_bits_check(host->regmap, SUN4I_SPDIF_TXCHSTA1,
470 GENMASK(9,0), reg, &chg1);
471
472 reg = SUN4I_SPDIF_TXCFG_CHSTMODE;
473 if (status[0] & IEC958_AES0_NONAUDIO)
474 reg |= SUN4I_SPDIF_TXCFG_NONAUDIO;
475
476 regmap_update_bits(host->regmap, SUN4I_SPDIF_TXCFG,
477 SUN4I_SPDIF_TXCFG_CHSTMODE |
478 SUN4I_SPDIF_TXCFG_NONAUDIO, reg);
479
480 spin_unlock_irqrestore(&host->lock, flags);
481
482 return chg0 || chg1;
483 }
484
485 static struct snd_kcontrol_new sun4i_spdif_controls[] = {
486 {
487 .access = SNDRV_CTL_ELEM_ACCESS_READ,
488 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
489 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, MASK),
490 .info = sun4i_spdif_info,
491 .get = sun4i_spdif_get_status_mask
492 },
493 {
494 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
495 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
496 .info = sun4i_spdif_info,
497 .get = sun4i_spdif_get_status,
498 .put = sun4i_spdif_set_status
499 }
500 };
501
sun4i_spdif_soc_dai_probe(struct snd_soc_dai * dai)502 static int sun4i_spdif_soc_dai_probe(struct snd_soc_dai *dai)
503 {
504 struct sun4i_spdif_dev *host = snd_soc_dai_get_drvdata(dai);
505
506 snd_soc_dai_init_dma_data(dai, &host->dma_params_tx, NULL);
507 snd_soc_add_dai_controls(dai, sun4i_spdif_controls,
508 ARRAY_SIZE(sun4i_spdif_controls));
509
510 return 0;
511 }
512
513 static const struct snd_soc_dai_ops sun4i_spdif_dai_ops = {
514 .probe = sun4i_spdif_soc_dai_probe,
515 .startup = sun4i_spdif_startup,
516 .trigger = sun4i_spdif_trigger,
517 .hw_params = sun4i_spdif_hw_params,
518 };
519
520 static const struct regmap_config sun4i_spdif_regmap_config = {
521 .reg_bits = 32,
522 .reg_stride = 4,
523 .val_bits = 32,
524 .max_register = SUN4I_SPDIF_RXCHSTA1,
525 };
526
527 #define SUN4I_RATES SNDRV_PCM_RATE_8000_192000
528
529 #define SUN4I_FORMATS (SNDRV_PCM_FORMAT_S16_LE | \
530 SNDRV_PCM_FORMAT_S20_3LE | \
531 SNDRV_PCM_FORMAT_S24_LE)
532
533 static struct snd_soc_dai_driver sun4i_spdif_dai = {
534 .playback = {
535 .channels_min = 1,
536 .channels_max = 2,
537 .rates = SUN4I_RATES,
538 .formats = SUN4I_FORMATS,
539 },
540 .ops = &sun4i_spdif_dai_ops,
541 .name = "spdif",
542 };
543
544 static const struct sun4i_spdif_quirks sun4i_a10_spdif_quirks = {
545 .reg_dac_txdata = SUN4I_SPDIF_TXFIFO,
546 .val_fctl_ftx = SUN4I_SPDIF_FCTL_FTX,
547 .mclk_multiplier = 1,
548 };
549
550 static const struct sun4i_spdif_quirks sun6i_a31_spdif_quirks = {
551 .reg_dac_txdata = SUN4I_SPDIF_TXFIFO,
552 .val_fctl_ftx = SUN4I_SPDIF_FCTL_FTX,
553 .has_reset = true,
554 .mclk_multiplier = 1,
555 };
556
557 static const struct sun4i_spdif_quirks sun8i_h3_spdif_quirks = {
558 .reg_dac_txdata = SUN8I_SPDIF_TXFIFO,
559 .val_fctl_ftx = SUN4I_SPDIF_FCTL_FTX,
560 .has_reset = true,
561 .mclk_multiplier = 4,
562 };
563
564 static const struct sun4i_spdif_quirks sun50i_h6_spdif_quirks = {
565 .reg_dac_txdata = SUN8I_SPDIF_TXFIFO,
566 .val_fctl_ftx = SUN50I_H6_SPDIF_FCTL_FTX,
567 .has_reset = true,
568 .mclk_multiplier = 1,
569 };
570
571 static const struct of_device_id sun4i_spdif_of_match[] = {
572 {
573 .compatible = "allwinner,sun4i-a10-spdif",
574 .data = &sun4i_a10_spdif_quirks,
575 },
576 {
577 .compatible = "allwinner,sun6i-a31-spdif",
578 .data = &sun6i_a31_spdif_quirks,
579 },
580 {
581 .compatible = "allwinner,sun8i-h3-spdif",
582 .data = &sun8i_h3_spdif_quirks,
583 },
584 {
585 .compatible = "allwinner,sun50i-h6-spdif",
586 .data = &sun50i_h6_spdif_quirks,
587 },
588 {
589 .compatible = "allwinner,sun50i-h616-spdif",
590 /* Essentially the same as the H6, but without RX */
591 .data = &sun50i_h6_spdif_quirks,
592 },
593 { /* sentinel */ }
594 };
595 MODULE_DEVICE_TABLE(of, sun4i_spdif_of_match);
596
597 static const struct snd_soc_component_driver sun4i_spdif_component = {
598 .name = "sun4i-spdif",
599 .legacy_dai_naming = 1,
600 };
601
sun4i_spdif_runtime_suspend(struct device * dev)602 static int sun4i_spdif_runtime_suspend(struct device *dev)
603 {
604 struct sun4i_spdif_dev *host = dev_get_drvdata(dev);
605
606 clk_disable_unprepare(host->spdif_clk);
607 clk_disable_unprepare(host->apb_clk);
608
609 return 0;
610 }
611
sun4i_spdif_runtime_resume(struct device * dev)612 static int sun4i_spdif_runtime_resume(struct device *dev)
613 {
614 struct sun4i_spdif_dev *host = dev_get_drvdata(dev);
615 int ret;
616
617 ret = clk_prepare_enable(host->spdif_clk);
618 if (ret)
619 return ret;
620 ret = clk_prepare_enable(host->apb_clk);
621 if (ret)
622 clk_disable_unprepare(host->spdif_clk);
623
624 return ret;
625 }
626
sun4i_spdif_probe(struct platform_device * pdev)627 static int sun4i_spdif_probe(struct platform_device *pdev)
628 {
629 struct sun4i_spdif_dev *host;
630 struct resource *res;
631 const struct sun4i_spdif_quirks *quirks;
632 int ret;
633 void __iomem *base;
634
635 dev_dbg(&pdev->dev, "Entered %s\n", __func__);
636
637 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
638 if (!host)
639 return -ENOMEM;
640
641 host->pdev = pdev;
642 spin_lock_init(&host->lock);
643
644 /* Initialize this copy of the CPU DAI driver structure */
645 memcpy(&host->cpu_dai_drv, &sun4i_spdif_dai, sizeof(sun4i_spdif_dai));
646 host->cpu_dai_drv.name = dev_name(&pdev->dev);
647
648 /* Get the addresses */
649 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
650 if (IS_ERR(base))
651 return PTR_ERR(base);
652
653 quirks = of_device_get_match_data(&pdev->dev);
654 if (quirks == NULL) {
655 dev_err(&pdev->dev, "Failed to determine the quirks to use\n");
656 return -ENODEV;
657 }
658 host->quirks = quirks;
659
660 host->regmap = devm_regmap_init_mmio(&pdev->dev, base,
661 &sun4i_spdif_regmap_config);
662
663 /* Clocks */
664 host->apb_clk = devm_clk_get(&pdev->dev, "apb");
665 if (IS_ERR(host->apb_clk)) {
666 dev_err(&pdev->dev, "failed to get a apb clock.\n");
667 return PTR_ERR(host->apb_clk);
668 }
669
670 host->spdif_clk = devm_clk_get(&pdev->dev, "spdif");
671 if (IS_ERR(host->spdif_clk)) {
672 dev_err(&pdev->dev, "failed to get a spdif clock.\n");
673 return PTR_ERR(host->spdif_clk);
674 }
675
676 host->dma_params_tx.addr = res->start + quirks->reg_dac_txdata;
677 host->dma_params_tx.maxburst = 8;
678 host->dma_params_tx.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
679
680 platform_set_drvdata(pdev, host);
681
682 if (quirks->has_reset) {
683 host->rst = devm_reset_control_get_optional_exclusive(&pdev->dev,
684 NULL);
685 if (PTR_ERR(host->rst) == -EPROBE_DEFER) {
686 ret = -EPROBE_DEFER;
687 dev_err(&pdev->dev, "Failed to get reset: %d\n", ret);
688 return ret;
689 }
690 if (!IS_ERR(host->rst))
691 reset_control_deassert(host->rst);
692 }
693
694 ret = devm_snd_soc_register_component(&pdev->dev,
695 &sun4i_spdif_component, &sun4i_spdif_dai, 1);
696 if (ret)
697 return ret;
698
699 pm_runtime_enable(&pdev->dev);
700 if (!pm_runtime_enabled(&pdev->dev)) {
701 ret = sun4i_spdif_runtime_resume(&pdev->dev);
702 if (ret)
703 goto err_unregister;
704 }
705
706 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
707 if (ret)
708 goto err_suspend;
709 return 0;
710 err_suspend:
711 if (!pm_runtime_status_suspended(&pdev->dev))
712 sun4i_spdif_runtime_suspend(&pdev->dev);
713 err_unregister:
714 pm_runtime_disable(&pdev->dev);
715 return ret;
716 }
717
sun4i_spdif_remove(struct platform_device * pdev)718 static void sun4i_spdif_remove(struct platform_device *pdev)
719 {
720 pm_runtime_disable(&pdev->dev);
721 if (!pm_runtime_status_suspended(&pdev->dev))
722 sun4i_spdif_runtime_suspend(&pdev->dev);
723 }
724
725 static const struct dev_pm_ops sun4i_spdif_pm = {
726 SET_RUNTIME_PM_OPS(sun4i_spdif_runtime_suspend,
727 sun4i_spdif_runtime_resume, NULL)
728 };
729
730 static struct platform_driver sun4i_spdif_driver = {
731 .driver = {
732 .name = "sun4i-spdif",
733 .of_match_table = sun4i_spdif_of_match,
734 .pm = &sun4i_spdif_pm,
735 },
736 .probe = sun4i_spdif_probe,
737 .remove_new = sun4i_spdif_remove,
738 };
739
740 module_platform_driver(sun4i_spdif_driver);
741
742 MODULE_AUTHOR("Marcus Cooper <codekipper@gmail.com>");
743 MODULE_AUTHOR("Andrea Venturi <be17068@iperbole.bo.it>");
744 MODULE_DESCRIPTION("Allwinner sun4i SPDIF SoC Interface");
745 MODULE_LICENSE("GPL");
746 MODULE_ALIAS("platform:sun4i-spdif");
747