1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (C) 2015 Andrea Venturi
4 * Andrea Venturi <be17068@iperbole.bo.it>
5 *
6 * Copyright (C) 2016 Maxime Ripard
7 * Maxime Ripard <maxime.ripard@free-electrons.com>
8 */
9
10 #include <linux/clk.h>
11 #include <linux/dmaengine.h>
12 #include <linux/module.h>
13 #include <linux/of_device.h>
14 #include <linux/platform_device.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/regmap.h>
17 #include <linux/reset.h>
18
19 #include <sound/dmaengine_pcm.h>
20 #include <sound/pcm_params.h>
21 #include <sound/soc.h>
22 #include <sound/soc-dai.h>
23
24 #define SUN4I_I2S_CTRL_REG 0x00
25 #define SUN4I_I2S_CTRL_SDO_EN_MASK GENMASK(11, 8)
26 #define SUN4I_I2S_CTRL_SDO_EN(sdo) BIT(8 + (sdo))
27 #define SUN4I_I2S_CTRL_MODE_MASK BIT(5)
28 #define SUN4I_I2S_CTRL_MODE_SLAVE (1 << 5)
29 #define SUN4I_I2S_CTRL_MODE_MASTER (0 << 5)
30 #define SUN4I_I2S_CTRL_TX_EN BIT(2)
31 #define SUN4I_I2S_CTRL_RX_EN BIT(1)
32 #define SUN4I_I2S_CTRL_GL_EN BIT(0)
33
34 #define SUN4I_I2S_FMT0_REG 0x04
35 #define SUN4I_I2S_FMT0_LRCLK_POLARITY_MASK BIT(7)
36 #define SUN4I_I2S_FMT0_LRCLK_POLARITY_INVERTED (1 << 7)
37 #define SUN4I_I2S_FMT0_LRCLK_POLARITY_NORMAL (0 << 7)
38 #define SUN4I_I2S_FMT0_BCLK_POLARITY_MASK BIT(6)
39 #define SUN4I_I2S_FMT0_BCLK_POLARITY_INVERTED (1 << 6)
40 #define SUN4I_I2S_FMT0_BCLK_POLARITY_NORMAL (0 << 6)
41 #define SUN4I_I2S_FMT0_SR_MASK GENMASK(5, 4)
42 #define SUN4I_I2S_FMT0_SR(sr) ((sr) << 4)
43 #define SUN4I_I2S_FMT0_WSS_MASK GENMASK(3, 2)
44 #define SUN4I_I2S_FMT0_WSS(wss) ((wss) << 2)
45 #define SUN4I_I2S_FMT0_FMT_MASK GENMASK(1, 0)
46 #define SUN4I_I2S_FMT0_FMT_RIGHT_J (2 << 0)
47 #define SUN4I_I2S_FMT0_FMT_LEFT_J (1 << 0)
48 #define SUN4I_I2S_FMT0_FMT_I2S (0 << 0)
49
50 #define SUN4I_I2S_FMT1_REG 0x08
51 #define SUN4I_I2S_FMT1_REG_SEXT_MASK BIT(8)
52 #define SUN4I_I2S_FMT1_REG_SEXT(sext) ((sext) << 8)
53
54 #define SUN4I_I2S_FIFO_TX_REG 0x0c
55 #define SUN4I_I2S_FIFO_RX_REG 0x10
56
57 #define SUN4I_I2S_FIFO_CTRL_REG 0x14
58 #define SUN4I_I2S_FIFO_CTRL_FLUSH_TX BIT(25)
59 #define SUN4I_I2S_FIFO_CTRL_FLUSH_RX BIT(24)
60 #define SUN4I_I2S_FIFO_CTRL_TX_MODE_MASK BIT(2)
61 #define SUN4I_I2S_FIFO_CTRL_TX_MODE(mode) ((mode) << 2)
62 #define SUN4I_I2S_FIFO_CTRL_RX_MODE_MASK GENMASK(1, 0)
63 #define SUN4I_I2S_FIFO_CTRL_RX_MODE(mode) (mode)
64
65 #define SUN4I_I2S_FIFO_STA_REG 0x18
66
67 #define SUN4I_I2S_DMA_INT_CTRL_REG 0x1c
68 #define SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN BIT(7)
69 #define SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN BIT(3)
70
71 #define SUN4I_I2S_INT_STA_REG 0x20
72
73 #define SUN4I_I2S_CLK_DIV_REG 0x24
74 #define SUN4I_I2S_CLK_DIV_MCLK_EN BIT(7)
75 #define SUN4I_I2S_CLK_DIV_BCLK_MASK GENMASK(6, 4)
76 #define SUN4I_I2S_CLK_DIV_BCLK(bclk) ((bclk) << 4)
77 #define SUN4I_I2S_CLK_DIV_MCLK_MASK GENMASK(3, 0)
78 #define SUN4I_I2S_CLK_DIV_MCLK(mclk) ((mclk) << 0)
79
80 #define SUN4I_I2S_TX_CNT_REG 0x28
81 #define SUN4I_I2S_RX_CNT_REG 0x2c
82
83 #define SUN4I_I2S_TX_CHAN_SEL_REG 0x30
84 #define SUN4I_I2S_CHAN_SEL_MASK GENMASK(2, 0)
85 #define SUN4I_I2S_CHAN_SEL(num_chan) (((num_chan) - 1) << 0)
86
87 #define SUN4I_I2S_TX_CHAN_MAP_REG 0x34
88 #define SUN4I_I2S_TX_CHAN_MAP(chan, sample) ((sample) << (chan << 2))
89
90 #define SUN4I_I2S_RX_CHAN_SEL_REG 0x38
91 #define SUN4I_I2S_RX_CHAN_MAP_REG 0x3c
92
93 /* Defines required for sun8i-h3 support */
94 #define SUN8I_I2S_CTRL_BCLK_OUT BIT(18)
95 #define SUN8I_I2S_CTRL_LRCK_OUT BIT(17)
96
97 #define SUN8I_I2S_CTRL_MODE_MASK GENMASK(5, 4)
98 #define SUN8I_I2S_CTRL_MODE_RIGHT (2 << 4)
99 #define SUN8I_I2S_CTRL_MODE_LEFT (1 << 4)
100 #define SUN8I_I2S_CTRL_MODE_PCM (0 << 4)
101
102 #define SUN8I_I2S_FMT0_LRCLK_POLARITY_MASK BIT(19)
103 #define SUN8I_I2S_FMT0_LRCLK_POLARITY_START_HIGH (1 << 19)
104 #define SUN8I_I2S_FMT0_LRCLK_POLARITY_START_LOW (0 << 19)
105 #define SUN8I_I2S_FMT0_LRCK_PERIOD_MASK GENMASK(17, 8)
106 #define SUN8I_I2S_FMT0_LRCK_PERIOD(period) ((period - 1) << 8)
107 #define SUN8I_I2S_FMT0_BCLK_POLARITY_MASK BIT(7)
108 #define SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED (1 << 7)
109 #define SUN8I_I2S_FMT0_BCLK_POLARITY_NORMAL (0 << 7)
110
111 #define SUN8I_I2S_FMT1_REG_SEXT_MASK GENMASK(5, 4)
112 #define SUN8I_I2S_FMT1_REG_SEXT(sext) ((sext) << 4)
113
114 #define SUN8I_I2S_INT_STA_REG 0x0c
115 #define SUN8I_I2S_FIFO_TX_REG 0x20
116
117 #define SUN8I_I2S_CHAN_CFG_REG 0x30
118 #define SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK GENMASK(7, 4)
119 #define SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(chan) ((chan - 1) << 4)
120 #define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK GENMASK(3, 0)
121 #define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(chan) (chan - 1)
122
123 #define SUN8I_I2S_TX_CHAN_MAP_REG 0x44
124 #define SUN8I_I2S_TX_CHAN_SEL_REG 0x34
125 #define SUN8I_I2S_TX_CHAN_OFFSET_MASK GENMASK(13, 12)
126 #define SUN8I_I2S_TX_CHAN_OFFSET(offset) (offset << 12)
127 #define SUN8I_I2S_TX_CHAN_EN_MASK GENMASK(11, 4)
128 #define SUN8I_I2S_TX_CHAN_EN(num_chan) (((1 << num_chan) - 1) << 4)
129
130 #define SUN8I_I2S_RX_CHAN_SEL_REG 0x54
131 #define SUN8I_I2S_RX_CHAN_MAP_REG 0x58
132
133 /* Defines required for sun50i-h6 support */
134 #define SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET_MASK GENMASK(21, 20)
135 #define SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET(offset) ((offset) << 20)
136 #define SUN50I_H6_I2S_TX_CHAN_SEL_MASK GENMASK(19, 16)
137 #define SUN50I_H6_I2S_TX_CHAN_SEL(chan) ((chan - 1) << 16)
138 #define SUN50I_H6_I2S_TX_CHAN_EN_MASK GENMASK(15, 0)
139 #define SUN50I_H6_I2S_TX_CHAN_EN(num_chan) (((1 << num_chan) - 1))
140
141 #define SUN50I_H6_I2S_TX_CHAN_SEL_REG(pin) (0x34 + 4 * (pin))
142 #define SUN50I_H6_I2S_TX_CHAN_MAP0_REG(pin) (0x44 + 8 * (pin))
143 #define SUN50I_H6_I2S_TX_CHAN_MAP1_REG(pin) (0x48 + 8 * (pin))
144
145 #define SUN50I_H6_I2S_RX_CHAN_SEL_REG 0x64
146 #define SUN50I_H6_I2S_RX_CHAN_MAP0_REG 0x68
147 #define SUN50I_H6_I2S_RX_CHAN_MAP1_REG 0x6C
148
149 #define SUN50I_R329_I2S_RX_CHAN_MAP0_REG 0x68
150 #define SUN50I_R329_I2S_RX_CHAN_MAP1_REG 0x6c
151 #define SUN50I_R329_I2S_RX_CHAN_MAP2_REG 0x70
152 #define SUN50I_R329_I2S_RX_CHAN_MAP3_REG 0x74
153
154 struct sun4i_i2s;
155
156 /**
157 * struct sun4i_i2s_quirks - Differences between SoC variants.
158 * @has_reset: SoC needs reset deasserted.
159 * @reg_offset_txdata: offset of the tx fifo.
160 * @sun4i_i2s_regmap: regmap config to use.
161 * @field_clkdiv_mclk_en: regmap field to enable mclk output.
162 * @field_fmt_wss: regmap field to set word select size.
163 * @field_fmt_sr: regmap field to set sample resolution.
164 * @num_din_pins: input pins
165 * @num_dout_pins: output pins (currently set but unused)
166 * @bclk_dividers: bit clock dividers array
167 * @num_bclk_dividers: number of bit clock dividers
168 * @mclk_dividers: mclk dividers array
169 * @num_mclk_dividers: number of mclk dividers
170 * @get_bclk_parent_rate: callback to get bclk parent rate
171 * @get_sr: callback to get sample resolution
172 * @get_wss: callback to get word select size
173 * @set_chan_cfg: callback to set channel configuration
174 * @set_fmt: callback to set format
175 */
176 struct sun4i_i2s_quirks {
177 bool has_reset;
178 unsigned int reg_offset_txdata; /* TX FIFO */
179 const struct regmap_config *sun4i_i2s_regmap;
180
181 /* Register fields for i2s */
182 struct reg_field field_clkdiv_mclk_en;
183 struct reg_field field_fmt_wss;
184 struct reg_field field_fmt_sr;
185
186 unsigned int num_din_pins;
187 unsigned int num_dout_pins;
188
189 const struct sun4i_i2s_clk_div *bclk_dividers;
190 unsigned int num_bclk_dividers;
191 const struct sun4i_i2s_clk_div *mclk_dividers;
192 unsigned int num_mclk_dividers;
193
194 unsigned long (*get_bclk_parent_rate)(const struct sun4i_i2s *i2s);
195 int (*get_sr)(unsigned int width);
196 int (*get_wss)(unsigned int width);
197
198 /*
199 * In the set_chan_cfg() function pointer:
200 * @slots: channels per frame + padding slots, regardless of format
201 * @slot_width: bits per sample + padding bits, regardless of format
202 */
203 int (*set_chan_cfg)(const struct sun4i_i2s *i2s,
204 unsigned int channels, unsigned int slots,
205 unsigned int slot_width);
206 int (*set_fmt)(const struct sun4i_i2s *i2s, unsigned int fmt);
207 };
208
209 struct sun4i_i2s {
210 struct clk *bus_clk;
211 struct clk *mod_clk;
212 struct regmap *regmap;
213 struct reset_control *rst;
214
215 unsigned int format;
216 unsigned int mclk_freq;
217 unsigned int slots;
218 unsigned int slot_width;
219
220 struct snd_dmaengine_dai_dma_data capture_dma_data;
221 struct snd_dmaengine_dai_dma_data playback_dma_data;
222
223 /* Register fields for i2s */
224 struct regmap_field *field_clkdiv_mclk_en;
225 struct regmap_field *field_fmt_wss;
226 struct regmap_field *field_fmt_sr;
227
228 const struct sun4i_i2s_quirks *variant;
229 };
230
231 struct sun4i_i2s_clk_div {
232 u8 div;
233 u8 val;
234 };
235
236 static const struct sun4i_i2s_clk_div sun4i_i2s_bclk_div[] = {
237 { .div = 2, .val = 0 },
238 { .div = 4, .val = 1 },
239 { .div = 6, .val = 2 },
240 { .div = 8, .val = 3 },
241 { .div = 12, .val = 4 },
242 { .div = 16, .val = 5 },
243 /* TODO - extend divide ratio supported by newer SoCs */
244 };
245
246 static const struct sun4i_i2s_clk_div sun4i_i2s_mclk_div[] = {
247 { .div = 1, .val = 0 },
248 { .div = 2, .val = 1 },
249 { .div = 4, .val = 2 },
250 { .div = 6, .val = 3 },
251 { .div = 8, .val = 4 },
252 { .div = 12, .val = 5 },
253 { .div = 16, .val = 6 },
254 { .div = 24, .val = 7 },
255 /* TODO - extend divide ratio supported by newer SoCs */
256 };
257
258 static const struct sun4i_i2s_clk_div sun8i_i2s_clk_div[] = {
259 { .div = 1, .val = 1 },
260 { .div = 2, .val = 2 },
261 { .div = 4, .val = 3 },
262 { .div = 6, .val = 4 },
263 { .div = 8, .val = 5 },
264 { .div = 12, .val = 6 },
265 { .div = 16, .val = 7 },
266 { .div = 24, .val = 8 },
267 { .div = 32, .val = 9 },
268 { .div = 48, .val = 10 },
269 { .div = 64, .val = 11 },
270 { .div = 96, .val = 12 },
271 { .div = 128, .val = 13 },
272 { .div = 176, .val = 14 },
273 { .div = 192, .val = 15 },
274 };
275
sun4i_i2s_get_bclk_parent_rate(const struct sun4i_i2s * i2s)276 static unsigned long sun4i_i2s_get_bclk_parent_rate(const struct sun4i_i2s *i2s)
277 {
278 return i2s->mclk_freq;
279 }
280
sun8i_i2s_get_bclk_parent_rate(const struct sun4i_i2s * i2s)281 static unsigned long sun8i_i2s_get_bclk_parent_rate(const struct sun4i_i2s *i2s)
282 {
283 return clk_get_rate(i2s->mod_clk);
284 }
285
sun4i_i2s_get_bclk_div(struct sun4i_i2s * i2s,unsigned long parent_rate,unsigned int sampling_rate,unsigned int channels,unsigned int word_size)286 static int sun4i_i2s_get_bclk_div(struct sun4i_i2s *i2s,
287 unsigned long parent_rate,
288 unsigned int sampling_rate,
289 unsigned int channels,
290 unsigned int word_size)
291 {
292 const struct sun4i_i2s_clk_div *dividers = i2s->variant->bclk_dividers;
293 int div = parent_rate / sampling_rate / word_size / channels;
294 int i;
295
296 for (i = 0; i < i2s->variant->num_bclk_dividers; i++) {
297 const struct sun4i_i2s_clk_div *bdiv = ÷rs[i];
298
299 if (bdiv->div == div)
300 return bdiv->val;
301 }
302
303 return -EINVAL;
304 }
305
sun4i_i2s_get_mclk_div(struct sun4i_i2s * i2s,unsigned long parent_rate,unsigned long mclk_rate)306 static int sun4i_i2s_get_mclk_div(struct sun4i_i2s *i2s,
307 unsigned long parent_rate,
308 unsigned long mclk_rate)
309 {
310 const struct sun4i_i2s_clk_div *dividers = i2s->variant->mclk_dividers;
311 int div = parent_rate / mclk_rate;
312 int i;
313
314 for (i = 0; i < i2s->variant->num_mclk_dividers; i++) {
315 const struct sun4i_i2s_clk_div *mdiv = ÷rs[i];
316
317 if (mdiv->div == div)
318 return mdiv->val;
319 }
320
321 return -EINVAL;
322 }
323
324 static int sun4i_i2s_oversample_rates[] = { 128, 192, 256, 384, 512, 768 };
sun4i_i2s_oversample_is_valid(unsigned int oversample)325 static bool sun4i_i2s_oversample_is_valid(unsigned int oversample)
326 {
327 int i;
328
329 for (i = 0; i < ARRAY_SIZE(sun4i_i2s_oversample_rates); i++)
330 if (sun4i_i2s_oversample_rates[i] == oversample)
331 return true;
332
333 return false;
334 }
335
sun4i_i2s_set_clk_rate(struct snd_soc_dai * dai,unsigned int rate,unsigned int slots,unsigned int slot_width)336 static int sun4i_i2s_set_clk_rate(struct snd_soc_dai *dai,
337 unsigned int rate,
338 unsigned int slots,
339 unsigned int slot_width)
340 {
341 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
342 unsigned int oversample_rate, clk_rate, bclk_parent_rate;
343 int bclk_div, mclk_div;
344 int ret;
345
346 switch (rate) {
347 case 176400:
348 case 88200:
349 case 44100:
350 case 22050:
351 case 11025:
352 clk_rate = 22579200;
353 break;
354
355 case 192000:
356 case 128000:
357 case 96000:
358 case 64000:
359 case 48000:
360 case 32000:
361 case 24000:
362 case 16000:
363 case 12000:
364 case 8000:
365 clk_rate = 24576000;
366 break;
367
368 default:
369 dev_err(dai->dev, "Unsupported sample rate: %u\n", rate);
370 return -EINVAL;
371 }
372
373 ret = clk_set_rate(i2s->mod_clk, clk_rate);
374 if (ret)
375 return ret;
376
377 oversample_rate = i2s->mclk_freq / rate;
378 if (!sun4i_i2s_oversample_is_valid(oversample_rate)) {
379 dev_err(dai->dev, "Unsupported oversample rate: %d\n",
380 oversample_rate);
381 return -EINVAL;
382 }
383
384 bclk_parent_rate = i2s->variant->get_bclk_parent_rate(i2s);
385 bclk_div = sun4i_i2s_get_bclk_div(i2s, bclk_parent_rate,
386 rate, slots, slot_width);
387 if (bclk_div < 0) {
388 dev_err(dai->dev, "Unsupported BCLK divider: %d\n", bclk_div);
389 return -EINVAL;
390 }
391
392 mclk_div = sun4i_i2s_get_mclk_div(i2s, clk_rate, i2s->mclk_freq);
393 if (mclk_div < 0) {
394 dev_err(dai->dev, "Unsupported MCLK divider: %d\n", mclk_div);
395 return -EINVAL;
396 }
397
398 regmap_write(i2s->regmap, SUN4I_I2S_CLK_DIV_REG,
399 SUN4I_I2S_CLK_DIV_BCLK(bclk_div) |
400 SUN4I_I2S_CLK_DIV_MCLK(mclk_div));
401
402 regmap_field_write(i2s->field_clkdiv_mclk_en, 1);
403
404 return 0;
405 }
406
sun4i_i2s_get_sr(unsigned int width)407 static int sun4i_i2s_get_sr(unsigned int width)
408 {
409 switch (width) {
410 case 16:
411 return 0;
412 case 20:
413 return 1;
414 case 24:
415 return 2;
416 }
417
418 return -EINVAL;
419 }
420
sun4i_i2s_get_wss(unsigned int width)421 static int sun4i_i2s_get_wss(unsigned int width)
422 {
423 switch (width) {
424 case 16:
425 return 0;
426 case 20:
427 return 1;
428 case 24:
429 return 2;
430 case 32:
431 return 3;
432 }
433
434 return -EINVAL;
435 }
436
sun8i_i2s_get_sr_wss(unsigned int width)437 static int sun8i_i2s_get_sr_wss(unsigned int width)
438 {
439 switch (width) {
440 case 8:
441 return 1;
442 case 12:
443 return 2;
444 case 16:
445 return 3;
446 case 20:
447 return 4;
448 case 24:
449 return 5;
450 case 28:
451 return 6;
452 case 32:
453 return 7;
454 }
455
456 return -EINVAL;
457 }
458
sun4i_i2s_set_chan_cfg(const struct sun4i_i2s * i2s,unsigned int channels,unsigned int slots,unsigned int slot_width)459 static int sun4i_i2s_set_chan_cfg(const struct sun4i_i2s *i2s,
460 unsigned int channels, unsigned int slots,
461 unsigned int slot_width)
462 {
463 /* Map the channels for playback and capture */
464 regmap_write(i2s->regmap, SUN4I_I2S_TX_CHAN_MAP_REG, 0x76543210);
465 regmap_write(i2s->regmap, SUN4I_I2S_RX_CHAN_MAP_REG, 0x00003210);
466
467 /* Configure the channels */
468 regmap_update_bits(i2s->regmap, SUN4I_I2S_TX_CHAN_SEL_REG,
469 SUN4I_I2S_CHAN_SEL_MASK,
470 SUN4I_I2S_CHAN_SEL(channels));
471 regmap_update_bits(i2s->regmap, SUN4I_I2S_RX_CHAN_SEL_REG,
472 SUN4I_I2S_CHAN_SEL_MASK,
473 SUN4I_I2S_CHAN_SEL(channels));
474
475 return 0;
476 }
477
sun8i_i2s_set_chan_cfg(const struct sun4i_i2s * i2s,unsigned int channels,unsigned int slots,unsigned int slot_width)478 static int sun8i_i2s_set_chan_cfg(const struct sun4i_i2s *i2s,
479 unsigned int channels, unsigned int slots,
480 unsigned int slot_width)
481 {
482 unsigned int lrck_period;
483
484 /* Map the channels for playback and capture */
485 regmap_write(i2s->regmap, SUN8I_I2S_TX_CHAN_MAP_REG, 0x76543210);
486 regmap_write(i2s->regmap, SUN8I_I2S_RX_CHAN_MAP_REG, 0x76543210);
487
488 /* Configure the channels */
489 regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG,
490 SUN4I_I2S_CHAN_SEL_MASK,
491 SUN4I_I2S_CHAN_SEL(channels));
492 regmap_update_bits(i2s->regmap, SUN8I_I2S_RX_CHAN_SEL_REG,
493 SUN4I_I2S_CHAN_SEL_MASK,
494 SUN4I_I2S_CHAN_SEL(channels));
495
496 regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG,
497 SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK,
498 SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(channels));
499 regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG,
500 SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK,
501 SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(channels));
502
503 switch (i2s->format & SND_SOC_DAIFMT_FORMAT_MASK) {
504 case SND_SOC_DAIFMT_DSP_A:
505 case SND_SOC_DAIFMT_DSP_B:
506 lrck_period = slot_width * slots;
507 break;
508
509 case SND_SOC_DAIFMT_LEFT_J:
510 case SND_SOC_DAIFMT_RIGHT_J:
511 case SND_SOC_DAIFMT_I2S:
512 lrck_period = slot_width;
513 break;
514
515 default:
516 return -EINVAL;
517 }
518
519 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG,
520 SUN8I_I2S_FMT0_LRCK_PERIOD_MASK,
521 SUN8I_I2S_FMT0_LRCK_PERIOD(lrck_period));
522
523 regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG,
524 SUN8I_I2S_TX_CHAN_EN_MASK,
525 SUN8I_I2S_TX_CHAN_EN(channels));
526
527 return 0;
528 }
529
sun50i_h6_i2s_set_chan_cfg(const struct sun4i_i2s * i2s,unsigned int channels,unsigned int slots,unsigned int slot_width)530 static int sun50i_h6_i2s_set_chan_cfg(const struct sun4i_i2s *i2s,
531 unsigned int channels, unsigned int slots,
532 unsigned int slot_width)
533 {
534 unsigned int lrck_period;
535
536 /* Map the channels for playback and capture */
537 regmap_write(i2s->regmap, SUN50I_H6_I2S_TX_CHAN_MAP0_REG(0), 0xFEDCBA98);
538 regmap_write(i2s->regmap, SUN50I_H6_I2S_TX_CHAN_MAP1_REG(0), 0x76543210);
539 if (i2s->variant->num_din_pins > 1) {
540 regmap_write(i2s->regmap, SUN50I_R329_I2S_RX_CHAN_MAP0_REG, 0x0F0E0D0C);
541 regmap_write(i2s->regmap, SUN50I_R329_I2S_RX_CHAN_MAP1_REG, 0x0B0A0908);
542 regmap_write(i2s->regmap, SUN50I_R329_I2S_RX_CHAN_MAP2_REG, 0x07060504);
543 regmap_write(i2s->regmap, SUN50I_R329_I2S_RX_CHAN_MAP3_REG, 0x03020100);
544 } else {
545 regmap_write(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_MAP0_REG, 0xFEDCBA98);
546 regmap_write(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_MAP1_REG, 0x76543210);
547 }
548
549 /* Configure the channels */
550 regmap_update_bits(i2s->regmap, SUN50I_H6_I2S_TX_CHAN_SEL_REG(0),
551 SUN50I_H6_I2S_TX_CHAN_SEL_MASK,
552 SUN50I_H6_I2S_TX_CHAN_SEL(channels));
553 regmap_update_bits(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_SEL_REG,
554 SUN50I_H6_I2S_TX_CHAN_SEL_MASK,
555 SUN50I_H6_I2S_TX_CHAN_SEL(channels));
556
557 regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG,
558 SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK,
559 SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(channels));
560 regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG,
561 SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK,
562 SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(channels));
563
564 switch (i2s->format & SND_SOC_DAIFMT_FORMAT_MASK) {
565 case SND_SOC_DAIFMT_DSP_A:
566 case SND_SOC_DAIFMT_DSP_B:
567 lrck_period = slot_width * slots;
568 break;
569
570 case SND_SOC_DAIFMT_LEFT_J:
571 case SND_SOC_DAIFMT_RIGHT_J:
572 case SND_SOC_DAIFMT_I2S:
573 lrck_period = slot_width;
574 break;
575
576 default:
577 return -EINVAL;
578 }
579
580 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG,
581 SUN8I_I2S_FMT0_LRCK_PERIOD_MASK,
582 SUN8I_I2S_FMT0_LRCK_PERIOD(lrck_period));
583
584 regmap_update_bits(i2s->regmap, SUN50I_H6_I2S_TX_CHAN_SEL_REG(0),
585 SUN50I_H6_I2S_TX_CHAN_EN_MASK,
586 SUN50I_H6_I2S_TX_CHAN_EN(channels));
587
588 return 0;
589 }
590
sun4i_i2s_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)591 static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream,
592 struct snd_pcm_hw_params *params,
593 struct snd_soc_dai *dai)
594 {
595 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
596 unsigned int word_size = params_width(params);
597 unsigned int slot_width = params_physical_width(params);
598 unsigned int channels = params_channels(params);
599
600 unsigned int slots = channels;
601
602 int ret, sr, wss;
603 u32 width;
604
605 if (i2s->slots)
606 slots = i2s->slots;
607
608 if (i2s->slot_width)
609 slot_width = i2s->slot_width;
610
611 ret = i2s->variant->set_chan_cfg(i2s, channels, slots, slot_width);
612 if (ret < 0) {
613 dev_err(dai->dev, "Invalid channel configuration\n");
614 return ret;
615 }
616
617 /* Set significant bits in our FIFOs */
618 regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG,
619 SUN4I_I2S_FIFO_CTRL_TX_MODE_MASK |
620 SUN4I_I2S_FIFO_CTRL_RX_MODE_MASK,
621 SUN4I_I2S_FIFO_CTRL_TX_MODE(1) |
622 SUN4I_I2S_FIFO_CTRL_RX_MODE(1));
623
624 switch (params_physical_width(params)) {
625 case 16:
626 width = DMA_SLAVE_BUSWIDTH_2_BYTES;
627 break;
628 case 32:
629 width = DMA_SLAVE_BUSWIDTH_4_BYTES;
630 break;
631 default:
632 dev_err(dai->dev, "Unsupported physical sample width: %d\n",
633 params_physical_width(params));
634 return -EINVAL;
635 }
636 i2s->playback_dma_data.addr_width = width;
637
638 sr = i2s->variant->get_sr(word_size);
639 if (sr < 0)
640 return -EINVAL;
641
642 wss = i2s->variant->get_wss(slot_width);
643 if (wss < 0)
644 return -EINVAL;
645
646 regmap_field_write(i2s->field_fmt_wss, wss);
647 regmap_field_write(i2s->field_fmt_sr, sr);
648
649 return sun4i_i2s_set_clk_rate(dai, params_rate(params),
650 slots, slot_width);
651 }
652
sun4i_i2s_set_soc_fmt(const struct sun4i_i2s * i2s,unsigned int fmt)653 static int sun4i_i2s_set_soc_fmt(const struct sun4i_i2s *i2s,
654 unsigned int fmt)
655 {
656 u32 val;
657
658 /* DAI clock polarity */
659 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
660 case SND_SOC_DAIFMT_IB_IF:
661 /* Invert both clocks */
662 val = SUN4I_I2S_FMT0_BCLK_POLARITY_INVERTED |
663 SUN4I_I2S_FMT0_LRCLK_POLARITY_INVERTED;
664 break;
665 case SND_SOC_DAIFMT_IB_NF:
666 /* Invert bit clock */
667 val = SUN4I_I2S_FMT0_BCLK_POLARITY_INVERTED;
668 break;
669 case SND_SOC_DAIFMT_NB_IF:
670 /* Invert frame clock */
671 val = SUN4I_I2S_FMT0_LRCLK_POLARITY_INVERTED;
672 break;
673 case SND_SOC_DAIFMT_NB_NF:
674 val = 0;
675 break;
676 default:
677 return -EINVAL;
678 }
679
680 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG,
681 SUN4I_I2S_FMT0_LRCLK_POLARITY_MASK |
682 SUN4I_I2S_FMT0_BCLK_POLARITY_MASK,
683 val);
684
685 /* DAI Mode */
686 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
687 case SND_SOC_DAIFMT_I2S:
688 val = SUN4I_I2S_FMT0_FMT_I2S;
689 break;
690
691 case SND_SOC_DAIFMT_LEFT_J:
692 val = SUN4I_I2S_FMT0_FMT_LEFT_J;
693 break;
694
695 case SND_SOC_DAIFMT_RIGHT_J:
696 val = SUN4I_I2S_FMT0_FMT_RIGHT_J;
697 break;
698
699 default:
700 return -EINVAL;
701 }
702
703 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG,
704 SUN4I_I2S_FMT0_FMT_MASK, val);
705
706 /* DAI clock master masks */
707 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
708 case SND_SOC_DAIFMT_BP_FP:
709 /* BCLK and LRCLK master */
710 val = SUN4I_I2S_CTRL_MODE_MASTER;
711 break;
712
713 case SND_SOC_DAIFMT_BC_FC:
714 /* BCLK and LRCLK slave */
715 val = SUN4I_I2S_CTRL_MODE_SLAVE;
716 break;
717
718 default:
719 return -EINVAL;
720 }
721 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
722 SUN4I_I2S_CTRL_MODE_MASK, val);
723
724 return 0;
725 }
726
sun8i_i2s_set_soc_fmt(const struct sun4i_i2s * i2s,unsigned int fmt)727 static int sun8i_i2s_set_soc_fmt(const struct sun4i_i2s *i2s,
728 unsigned int fmt)
729 {
730 u32 mode, lrclk_pol, bclk_pol, val;
731 u8 offset;
732
733 /* DAI Mode */
734 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
735 case SND_SOC_DAIFMT_DSP_A:
736 lrclk_pol = SUN8I_I2S_FMT0_LRCLK_POLARITY_START_HIGH;
737 mode = SUN8I_I2S_CTRL_MODE_PCM;
738 offset = 1;
739 break;
740
741 case SND_SOC_DAIFMT_DSP_B:
742 lrclk_pol = SUN8I_I2S_FMT0_LRCLK_POLARITY_START_HIGH;
743 mode = SUN8I_I2S_CTRL_MODE_PCM;
744 offset = 0;
745 break;
746
747 case SND_SOC_DAIFMT_I2S:
748 lrclk_pol = SUN8I_I2S_FMT0_LRCLK_POLARITY_START_LOW;
749 mode = SUN8I_I2S_CTRL_MODE_LEFT;
750 offset = 1;
751 break;
752
753 case SND_SOC_DAIFMT_LEFT_J:
754 lrclk_pol = SUN8I_I2S_FMT0_LRCLK_POLARITY_START_HIGH;
755 mode = SUN8I_I2S_CTRL_MODE_LEFT;
756 offset = 0;
757 break;
758
759 case SND_SOC_DAIFMT_RIGHT_J:
760 lrclk_pol = SUN8I_I2S_FMT0_LRCLK_POLARITY_START_HIGH;
761 mode = SUN8I_I2S_CTRL_MODE_RIGHT;
762 offset = 0;
763 break;
764
765 default:
766 return -EINVAL;
767 }
768
769 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
770 SUN8I_I2S_CTRL_MODE_MASK, mode);
771 regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG,
772 SUN8I_I2S_TX_CHAN_OFFSET_MASK,
773 SUN8I_I2S_TX_CHAN_OFFSET(offset));
774 regmap_update_bits(i2s->regmap, SUN8I_I2S_RX_CHAN_SEL_REG,
775 SUN8I_I2S_TX_CHAN_OFFSET_MASK,
776 SUN8I_I2S_TX_CHAN_OFFSET(offset));
777
778 /* DAI clock polarity */
779 bclk_pol = SUN8I_I2S_FMT0_BCLK_POLARITY_NORMAL;
780
781 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
782 case SND_SOC_DAIFMT_IB_IF:
783 /* Invert both clocks */
784 lrclk_pol ^= SUN8I_I2S_FMT0_LRCLK_POLARITY_MASK;
785 bclk_pol = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED;
786 break;
787 case SND_SOC_DAIFMT_IB_NF:
788 /* Invert bit clock */
789 bclk_pol = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED;
790 break;
791 case SND_SOC_DAIFMT_NB_IF:
792 /* Invert frame clock */
793 lrclk_pol ^= SUN8I_I2S_FMT0_LRCLK_POLARITY_MASK;
794 break;
795 case SND_SOC_DAIFMT_NB_NF:
796 /* No inversion */
797 break;
798 default:
799 return -EINVAL;
800 }
801
802 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG,
803 SUN8I_I2S_FMT0_LRCLK_POLARITY_MASK |
804 SUN8I_I2S_FMT0_BCLK_POLARITY_MASK,
805 lrclk_pol | bclk_pol);
806
807 /* DAI clock master masks */
808 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
809 case SND_SOC_DAIFMT_BP_FP:
810 /* BCLK and LRCLK master */
811 val = SUN8I_I2S_CTRL_BCLK_OUT | SUN8I_I2S_CTRL_LRCK_OUT;
812 break;
813
814 case SND_SOC_DAIFMT_BC_FC:
815 /* BCLK and LRCLK slave */
816 val = 0;
817 break;
818
819 default:
820 return -EINVAL;
821 }
822
823 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
824 SUN8I_I2S_CTRL_BCLK_OUT | SUN8I_I2S_CTRL_LRCK_OUT,
825 val);
826
827 /* Set sign extension to pad out LSB with 0 */
828 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT1_REG,
829 SUN8I_I2S_FMT1_REG_SEXT_MASK,
830 SUN8I_I2S_FMT1_REG_SEXT(0));
831
832 return 0;
833 }
834
sun50i_h6_i2s_set_soc_fmt(const struct sun4i_i2s * i2s,unsigned int fmt)835 static int sun50i_h6_i2s_set_soc_fmt(const struct sun4i_i2s *i2s,
836 unsigned int fmt)
837 {
838 u32 mode, lrclk_pol, bclk_pol, val;
839 u8 offset;
840
841 /* DAI Mode */
842 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
843 case SND_SOC_DAIFMT_DSP_A:
844 lrclk_pol = SUN8I_I2S_FMT0_LRCLK_POLARITY_START_HIGH;
845 mode = SUN8I_I2S_CTRL_MODE_PCM;
846 offset = 1;
847 break;
848
849 case SND_SOC_DAIFMT_DSP_B:
850 lrclk_pol = SUN8I_I2S_FMT0_LRCLK_POLARITY_START_HIGH;
851 mode = SUN8I_I2S_CTRL_MODE_PCM;
852 offset = 0;
853 break;
854
855 case SND_SOC_DAIFMT_I2S:
856 lrclk_pol = SUN8I_I2S_FMT0_LRCLK_POLARITY_START_LOW;
857 mode = SUN8I_I2S_CTRL_MODE_LEFT;
858 offset = 1;
859 break;
860
861 case SND_SOC_DAIFMT_LEFT_J:
862 lrclk_pol = SUN8I_I2S_FMT0_LRCLK_POLARITY_START_HIGH;
863 mode = SUN8I_I2S_CTRL_MODE_LEFT;
864 offset = 0;
865 break;
866
867 case SND_SOC_DAIFMT_RIGHT_J:
868 lrclk_pol = SUN8I_I2S_FMT0_LRCLK_POLARITY_START_HIGH;
869 mode = SUN8I_I2S_CTRL_MODE_RIGHT;
870 offset = 0;
871 break;
872
873 default:
874 return -EINVAL;
875 }
876
877 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
878 SUN8I_I2S_CTRL_MODE_MASK, mode);
879 regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG,
880 SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET_MASK,
881 SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET(offset));
882 regmap_update_bits(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_SEL_REG,
883 SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET_MASK,
884 SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET(offset));
885
886 /* DAI clock polarity */
887 bclk_pol = SUN8I_I2S_FMT0_BCLK_POLARITY_NORMAL;
888
889 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
890 case SND_SOC_DAIFMT_IB_IF:
891 /* Invert both clocks */
892 lrclk_pol ^= SUN8I_I2S_FMT0_LRCLK_POLARITY_MASK;
893 bclk_pol = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED;
894 break;
895 case SND_SOC_DAIFMT_IB_NF:
896 /* Invert bit clock */
897 bclk_pol = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED;
898 break;
899 case SND_SOC_DAIFMT_NB_IF:
900 /* Invert frame clock */
901 lrclk_pol ^= SUN8I_I2S_FMT0_LRCLK_POLARITY_MASK;
902 break;
903 case SND_SOC_DAIFMT_NB_NF:
904 /* No inversion */
905 break;
906 default:
907 return -EINVAL;
908 }
909
910 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG,
911 SUN8I_I2S_FMT0_LRCLK_POLARITY_MASK |
912 SUN8I_I2S_FMT0_BCLK_POLARITY_MASK,
913 lrclk_pol | bclk_pol);
914
915
916 /* DAI clock master masks */
917 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
918 case SND_SOC_DAIFMT_BP_FP:
919 /* BCLK and LRCLK master */
920 val = SUN8I_I2S_CTRL_BCLK_OUT | SUN8I_I2S_CTRL_LRCK_OUT;
921 break;
922
923 case SND_SOC_DAIFMT_BC_FC:
924 /* BCLK and LRCLK slave */
925 val = 0;
926 break;
927
928 default:
929 return -EINVAL;
930 }
931
932 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
933 SUN8I_I2S_CTRL_BCLK_OUT | SUN8I_I2S_CTRL_LRCK_OUT,
934 val);
935
936 /* Set sign extension to pad out LSB with 0 */
937 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT1_REG,
938 SUN8I_I2S_FMT1_REG_SEXT_MASK,
939 SUN8I_I2S_FMT1_REG_SEXT(0));
940
941 return 0;
942 }
943
sun4i_i2s_set_fmt(struct snd_soc_dai * dai,unsigned int fmt)944 static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
945 {
946 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
947 int ret;
948
949 ret = i2s->variant->set_fmt(i2s, fmt);
950 if (ret) {
951 dev_err(dai->dev, "Unsupported format configuration\n");
952 return ret;
953 }
954
955 i2s->format = fmt;
956
957 return 0;
958 }
959
sun4i_i2s_start_capture(struct sun4i_i2s * i2s)960 static void sun4i_i2s_start_capture(struct sun4i_i2s *i2s)
961 {
962 /* Flush RX FIFO */
963 regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG,
964 SUN4I_I2S_FIFO_CTRL_FLUSH_RX,
965 SUN4I_I2S_FIFO_CTRL_FLUSH_RX);
966
967 /* Clear RX counter */
968 regmap_write(i2s->regmap, SUN4I_I2S_RX_CNT_REG, 0);
969
970 /* Enable RX Block */
971 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
972 SUN4I_I2S_CTRL_RX_EN,
973 SUN4I_I2S_CTRL_RX_EN);
974
975 /* Enable RX DRQ */
976 regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG,
977 SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN,
978 SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN);
979 }
980
sun4i_i2s_start_playback(struct sun4i_i2s * i2s)981 static void sun4i_i2s_start_playback(struct sun4i_i2s *i2s)
982 {
983 /* Flush TX FIFO */
984 regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG,
985 SUN4I_I2S_FIFO_CTRL_FLUSH_TX,
986 SUN4I_I2S_FIFO_CTRL_FLUSH_TX);
987
988 /* Clear TX counter */
989 regmap_write(i2s->regmap, SUN4I_I2S_TX_CNT_REG, 0);
990
991 /* Enable TX Block */
992 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
993 SUN4I_I2S_CTRL_TX_EN,
994 SUN4I_I2S_CTRL_TX_EN);
995
996 /* Enable TX DRQ */
997 regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG,
998 SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN,
999 SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN);
1000 }
1001
sun4i_i2s_stop_capture(struct sun4i_i2s * i2s)1002 static void sun4i_i2s_stop_capture(struct sun4i_i2s *i2s)
1003 {
1004 /* Disable RX Block */
1005 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
1006 SUN4I_I2S_CTRL_RX_EN,
1007 0);
1008
1009 /* Disable RX DRQ */
1010 regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG,
1011 SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN,
1012 0);
1013 }
1014
sun4i_i2s_stop_playback(struct sun4i_i2s * i2s)1015 static void sun4i_i2s_stop_playback(struct sun4i_i2s *i2s)
1016 {
1017 /* Disable TX Block */
1018 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
1019 SUN4I_I2S_CTRL_TX_EN,
1020 0);
1021
1022 /* Disable TX DRQ */
1023 regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG,
1024 SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN,
1025 0);
1026 }
1027
sun4i_i2s_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)1028 static int sun4i_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
1029 struct snd_soc_dai *dai)
1030 {
1031 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
1032
1033 switch (cmd) {
1034 case SNDRV_PCM_TRIGGER_START:
1035 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1036 case SNDRV_PCM_TRIGGER_RESUME:
1037 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1038 sun4i_i2s_start_playback(i2s);
1039 else
1040 sun4i_i2s_start_capture(i2s);
1041 break;
1042
1043 case SNDRV_PCM_TRIGGER_STOP:
1044 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1045 case SNDRV_PCM_TRIGGER_SUSPEND:
1046 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1047 sun4i_i2s_stop_playback(i2s);
1048 else
1049 sun4i_i2s_stop_capture(i2s);
1050 break;
1051
1052 default:
1053 return -EINVAL;
1054 }
1055
1056 return 0;
1057 }
1058
sun4i_i2s_set_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)1059 static int sun4i_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id,
1060 unsigned int freq, int dir)
1061 {
1062 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
1063
1064 if (clk_id != 0)
1065 return -EINVAL;
1066
1067 i2s->mclk_freq = freq;
1068
1069 return 0;
1070 }
1071
sun4i_i2s_set_tdm_slot(struct snd_soc_dai * dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int slot_width)1072 static int sun4i_i2s_set_tdm_slot(struct snd_soc_dai *dai,
1073 unsigned int tx_mask, unsigned int rx_mask,
1074 int slots, int slot_width)
1075 {
1076 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
1077
1078 if (slots > 8)
1079 return -EINVAL;
1080
1081 i2s->slots = slots;
1082 i2s->slot_width = slot_width;
1083
1084 return 0;
1085 }
1086
sun4i_i2s_dai_probe(struct snd_soc_dai * dai)1087 static int sun4i_i2s_dai_probe(struct snd_soc_dai *dai)
1088 {
1089 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
1090
1091 snd_soc_dai_init_dma_data(dai,
1092 &i2s->playback_dma_data,
1093 &i2s->capture_dma_data);
1094
1095 return 0;
1096 }
1097
1098 static const struct snd_soc_dai_ops sun4i_i2s_dai_ops = {
1099 .probe = sun4i_i2s_dai_probe,
1100 .hw_params = sun4i_i2s_hw_params,
1101 .set_fmt = sun4i_i2s_set_fmt,
1102 .set_sysclk = sun4i_i2s_set_sysclk,
1103 .set_tdm_slot = sun4i_i2s_set_tdm_slot,
1104 .trigger = sun4i_i2s_trigger,
1105 };
1106
1107 #define SUN4I_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
1108 SNDRV_PCM_FMTBIT_S20_LE | \
1109 SNDRV_PCM_FMTBIT_S24_LE)
1110
1111 static struct snd_soc_dai_driver sun4i_i2s_dai = {
1112 .capture = {
1113 .stream_name = "Capture",
1114 .channels_min = 1,
1115 .channels_max = 8,
1116 .rates = SNDRV_PCM_RATE_8000_192000,
1117 .formats = SUN4I_FORMATS,
1118 },
1119 .playback = {
1120 .stream_name = "Playback",
1121 .channels_min = 1,
1122 .channels_max = 8,
1123 .rates = SNDRV_PCM_RATE_8000_192000,
1124 .formats = SUN4I_FORMATS,
1125 },
1126 .ops = &sun4i_i2s_dai_ops,
1127 .symmetric_rate = 1,
1128 };
1129
1130 static const struct snd_soc_component_driver sun4i_i2s_component = {
1131 .name = "sun4i-dai",
1132 .legacy_dai_naming = 1,
1133 };
1134
sun4i_i2s_rd_reg(struct device * dev,unsigned int reg)1135 static bool sun4i_i2s_rd_reg(struct device *dev, unsigned int reg)
1136 {
1137 switch (reg) {
1138 case SUN4I_I2S_FIFO_TX_REG:
1139 return false;
1140
1141 default:
1142 return true;
1143 }
1144 }
1145
sun4i_i2s_wr_reg(struct device * dev,unsigned int reg)1146 static bool sun4i_i2s_wr_reg(struct device *dev, unsigned int reg)
1147 {
1148 switch (reg) {
1149 case SUN4I_I2S_FIFO_RX_REG:
1150 case SUN4I_I2S_FIFO_STA_REG:
1151 return false;
1152
1153 default:
1154 return true;
1155 }
1156 }
1157
sun4i_i2s_volatile_reg(struct device * dev,unsigned int reg)1158 static bool sun4i_i2s_volatile_reg(struct device *dev, unsigned int reg)
1159 {
1160 switch (reg) {
1161 case SUN4I_I2S_FIFO_RX_REG:
1162 case SUN4I_I2S_INT_STA_REG:
1163 case SUN4I_I2S_RX_CNT_REG:
1164 case SUN4I_I2S_TX_CNT_REG:
1165 return true;
1166
1167 default:
1168 return false;
1169 }
1170 }
1171
sun8i_i2s_rd_reg(struct device * dev,unsigned int reg)1172 static bool sun8i_i2s_rd_reg(struct device *dev, unsigned int reg)
1173 {
1174 switch (reg) {
1175 case SUN8I_I2S_FIFO_TX_REG:
1176 return false;
1177
1178 default:
1179 return true;
1180 }
1181 }
1182
sun8i_i2s_volatile_reg(struct device * dev,unsigned int reg)1183 static bool sun8i_i2s_volatile_reg(struct device *dev, unsigned int reg)
1184 {
1185 switch (reg) {
1186 case SUN4I_I2S_FIFO_CTRL_REG:
1187 case SUN4I_I2S_FIFO_RX_REG:
1188 case SUN4I_I2S_FIFO_STA_REG:
1189 case SUN4I_I2S_RX_CNT_REG:
1190 case SUN4I_I2S_TX_CNT_REG:
1191 case SUN8I_I2S_FIFO_TX_REG:
1192 case SUN8I_I2S_INT_STA_REG:
1193 return true;
1194
1195 default:
1196 return false;
1197 }
1198 }
1199
1200 static const struct reg_default sun4i_i2s_reg_defaults[] = {
1201 { SUN4I_I2S_CTRL_REG, 0x00000000 },
1202 { SUN4I_I2S_FMT0_REG, 0x0000000c },
1203 { SUN4I_I2S_FMT1_REG, 0x00004020 },
1204 { SUN4I_I2S_FIFO_CTRL_REG, 0x000400f0 },
1205 { SUN4I_I2S_DMA_INT_CTRL_REG, 0x00000000 },
1206 { SUN4I_I2S_CLK_DIV_REG, 0x00000000 },
1207 { SUN4I_I2S_TX_CHAN_SEL_REG, 0x00000001 },
1208 { SUN4I_I2S_TX_CHAN_MAP_REG, 0x76543210 },
1209 { SUN4I_I2S_RX_CHAN_SEL_REG, 0x00000001 },
1210 { SUN4I_I2S_RX_CHAN_MAP_REG, 0x00003210 },
1211 };
1212
1213 static const struct reg_default sun8i_i2s_reg_defaults[] = {
1214 { SUN4I_I2S_CTRL_REG, 0x00060000 },
1215 { SUN4I_I2S_FMT0_REG, 0x00000033 },
1216 { SUN4I_I2S_FMT1_REG, 0x00000030 },
1217 { SUN4I_I2S_FIFO_CTRL_REG, 0x000400f0 },
1218 { SUN4I_I2S_DMA_INT_CTRL_REG, 0x00000000 },
1219 { SUN4I_I2S_CLK_DIV_REG, 0x00000000 },
1220 { SUN8I_I2S_CHAN_CFG_REG, 0x00000000 },
1221 { SUN8I_I2S_TX_CHAN_SEL_REG, 0x00000000 },
1222 { SUN8I_I2S_TX_CHAN_MAP_REG, 0x00000000 },
1223 { SUN8I_I2S_RX_CHAN_SEL_REG, 0x00000000 },
1224 { SUN8I_I2S_RX_CHAN_MAP_REG, 0x00000000 },
1225 };
1226
1227 static const struct reg_default sun50i_h6_i2s_reg_defaults[] = {
1228 { SUN4I_I2S_CTRL_REG, 0x00060000 },
1229 { SUN4I_I2S_FMT0_REG, 0x00000033 },
1230 { SUN4I_I2S_FMT1_REG, 0x00000030 },
1231 { SUN4I_I2S_FIFO_CTRL_REG, 0x000400f0 },
1232 { SUN4I_I2S_DMA_INT_CTRL_REG, 0x00000000 },
1233 { SUN4I_I2S_CLK_DIV_REG, 0x00000000 },
1234 { SUN8I_I2S_CHAN_CFG_REG, 0x00000000 },
1235 { SUN50I_H6_I2S_TX_CHAN_SEL_REG(0), 0x00000000 },
1236 { SUN50I_H6_I2S_TX_CHAN_MAP0_REG(0), 0x00000000 },
1237 { SUN50I_H6_I2S_TX_CHAN_MAP1_REG(0), 0x00000000 },
1238 { SUN50I_H6_I2S_RX_CHAN_SEL_REG, 0x00000000 },
1239 { SUN50I_H6_I2S_RX_CHAN_MAP0_REG, 0x00000000 },
1240 { SUN50I_H6_I2S_RX_CHAN_MAP1_REG, 0x00000000 },
1241 };
1242
1243 static const struct regmap_config sun4i_i2s_regmap_config = {
1244 .reg_bits = 32,
1245 .reg_stride = 4,
1246 .val_bits = 32,
1247 .max_register = SUN4I_I2S_RX_CHAN_MAP_REG,
1248
1249 .cache_type = REGCACHE_FLAT,
1250 .reg_defaults = sun4i_i2s_reg_defaults,
1251 .num_reg_defaults = ARRAY_SIZE(sun4i_i2s_reg_defaults),
1252 .writeable_reg = sun4i_i2s_wr_reg,
1253 .readable_reg = sun4i_i2s_rd_reg,
1254 .volatile_reg = sun4i_i2s_volatile_reg,
1255 };
1256
1257 static const struct regmap_config sun8i_i2s_regmap_config = {
1258 .reg_bits = 32,
1259 .reg_stride = 4,
1260 .val_bits = 32,
1261 .max_register = SUN8I_I2S_RX_CHAN_MAP_REG,
1262 .cache_type = REGCACHE_FLAT,
1263 .reg_defaults = sun8i_i2s_reg_defaults,
1264 .num_reg_defaults = ARRAY_SIZE(sun8i_i2s_reg_defaults),
1265 .writeable_reg = sun4i_i2s_wr_reg,
1266 .readable_reg = sun8i_i2s_rd_reg,
1267 .volatile_reg = sun8i_i2s_volatile_reg,
1268 };
1269
1270 static const struct regmap_config sun50i_h6_i2s_regmap_config = {
1271 .reg_bits = 32,
1272 .reg_stride = 4,
1273 .val_bits = 32,
1274 .max_register = SUN50I_R329_I2S_RX_CHAN_MAP3_REG,
1275 .cache_type = REGCACHE_FLAT,
1276 .reg_defaults = sun50i_h6_i2s_reg_defaults,
1277 .num_reg_defaults = ARRAY_SIZE(sun50i_h6_i2s_reg_defaults),
1278 .writeable_reg = sun4i_i2s_wr_reg,
1279 .readable_reg = sun8i_i2s_rd_reg,
1280 .volatile_reg = sun8i_i2s_volatile_reg,
1281 };
1282
sun4i_i2s_runtime_resume(struct device * dev)1283 static int sun4i_i2s_runtime_resume(struct device *dev)
1284 {
1285 struct sun4i_i2s *i2s = dev_get_drvdata(dev);
1286 int ret;
1287
1288 ret = clk_prepare_enable(i2s->bus_clk);
1289 if (ret) {
1290 dev_err(dev, "Failed to enable bus clock\n");
1291 return ret;
1292 }
1293
1294 regcache_cache_only(i2s->regmap, false);
1295 regcache_mark_dirty(i2s->regmap);
1296
1297 ret = regcache_sync(i2s->regmap);
1298 if (ret) {
1299 dev_err(dev, "Failed to sync regmap cache\n");
1300 goto err_disable_clk;
1301 }
1302
1303 /* Enable the whole hardware block */
1304 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
1305 SUN4I_I2S_CTRL_GL_EN, SUN4I_I2S_CTRL_GL_EN);
1306
1307 /* Enable the first output line */
1308 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
1309 SUN4I_I2S_CTRL_SDO_EN_MASK,
1310 SUN4I_I2S_CTRL_SDO_EN(0));
1311
1312 ret = clk_prepare_enable(i2s->mod_clk);
1313 if (ret) {
1314 dev_err(dev, "Failed to enable module clock\n");
1315 goto err_disable_clk;
1316 }
1317
1318 return 0;
1319
1320 err_disable_clk:
1321 clk_disable_unprepare(i2s->bus_clk);
1322 return ret;
1323 }
1324
sun4i_i2s_runtime_suspend(struct device * dev)1325 static int sun4i_i2s_runtime_suspend(struct device *dev)
1326 {
1327 struct sun4i_i2s *i2s = dev_get_drvdata(dev);
1328
1329 clk_disable_unprepare(i2s->mod_clk);
1330
1331 /* Disable our output lines */
1332 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
1333 SUN4I_I2S_CTRL_SDO_EN_MASK, 0);
1334
1335 /* Disable the whole hardware block */
1336 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
1337 SUN4I_I2S_CTRL_GL_EN, 0);
1338
1339 regcache_cache_only(i2s->regmap, true);
1340
1341 clk_disable_unprepare(i2s->bus_clk);
1342
1343 return 0;
1344 }
1345
1346 static const struct sun4i_i2s_quirks sun4i_a10_i2s_quirks = {
1347 .has_reset = false,
1348 .reg_offset_txdata = SUN4I_I2S_FIFO_TX_REG,
1349 .sun4i_i2s_regmap = &sun4i_i2s_regmap_config,
1350 .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
1351 .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
1352 .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
1353 .bclk_dividers = sun4i_i2s_bclk_div,
1354 .num_bclk_dividers = ARRAY_SIZE(sun4i_i2s_bclk_div),
1355 .mclk_dividers = sun4i_i2s_mclk_div,
1356 .num_mclk_dividers = ARRAY_SIZE(sun4i_i2s_mclk_div),
1357 .get_bclk_parent_rate = sun4i_i2s_get_bclk_parent_rate,
1358 .get_sr = sun4i_i2s_get_sr,
1359 .get_wss = sun4i_i2s_get_wss,
1360 .set_chan_cfg = sun4i_i2s_set_chan_cfg,
1361 .set_fmt = sun4i_i2s_set_soc_fmt,
1362 };
1363
1364 static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = {
1365 .has_reset = true,
1366 .reg_offset_txdata = SUN4I_I2S_FIFO_TX_REG,
1367 .sun4i_i2s_regmap = &sun4i_i2s_regmap_config,
1368 .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
1369 .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
1370 .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
1371 .bclk_dividers = sun4i_i2s_bclk_div,
1372 .num_bclk_dividers = ARRAY_SIZE(sun4i_i2s_bclk_div),
1373 .mclk_dividers = sun4i_i2s_mclk_div,
1374 .num_mclk_dividers = ARRAY_SIZE(sun4i_i2s_mclk_div),
1375 .get_bclk_parent_rate = sun4i_i2s_get_bclk_parent_rate,
1376 .get_sr = sun4i_i2s_get_sr,
1377 .get_wss = sun4i_i2s_get_wss,
1378 .set_chan_cfg = sun4i_i2s_set_chan_cfg,
1379 .set_fmt = sun4i_i2s_set_soc_fmt,
1380 };
1381
1382 /*
1383 * This doesn't describe the TDM controller documented in the A83t
1384 * datasheet, but the three undocumented I2S controller that use the
1385 * older design.
1386 */
1387 static const struct sun4i_i2s_quirks sun8i_a83t_i2s_quirks = {
1388 .has_reset = true,
1389 .reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG,
1390 .sun4i_i2s_regmap = &sun4i_i2s_regmap_config,
1391 .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
1392 .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
1393 .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
1394 .bclk_dividers = sun4i_i2s_bclk_div,
1395 .num_bclk_dividers = ARRAY_SIZE(sun4i_i2s_bclk_div),
1396 .mclk_dividers = sun4i_i2s_mclk_div,
1397 .num_mclk_dividers = ARRAY_SIZE(sun4i_i2s_mclk_div),
1398 .get_bclk_parent_rate = sun4i_i2s_get_bclk_parent_rate,
1399 .get_sr = sun4i_i2s_get_sr,
1400 .get_wss = sun4i_i2s_get_wss,
1401 .set_chan_cfg = sun4i_i2s_set_chan_cfg,
1402 .set_fmt = sun4i_i2s_set_soc_fmt,
1403 };
1404
1405 static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = {
1406 .has_reset = true,
1407 .reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG,
1408 .sun4i_i2s_regmap = &sun8i_i2s_regmap_config,
1409 .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 8, 8),
1410 .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 2),
1411 .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 6),
1412 .bclk_dividers = sun8i_i2s_clk_div,
1413 .num_bclk_dividers = ARRAY_SIZE(sun8i_i2s_clk_div),
1414 .mclk_dividers = sun8i_i2s_clk_div,
1415 .num_mclk_dividers = ARRAY_SIZE(sun8i_i2s_clk_div),
1416 .get_bclk_parent_rate = sun8i_i2s_get_bclk_parent_rate,
1417 .get_sr = sun8i_i2s_get_sr_wss,
1418 .get_wss = sun8i_i2s_get_sr_wss,
1419 .set_chan_cfg = sun8i_i2s_set_chan_cfg,
1420 .set_fmt = sun8i_i2s_set_soc_fmt,
1421 };
1422
1423 static const struct sun4i_i2s_quirks sun50i_a64_codec_i2s_quirks = {
1424 .has_reset = true,
1425 .reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG,
1426 .sun4i_i2s_regmap = &sun4i_i2s_regmap_config,
1427 .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
1428 .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
1429 .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
1430 .bclk_dividers = sun4i_i2s_bclk_div,
1431 .num_bclk_dividers = ARRAY_SIZE(sun4i_i2s_bclk_div),
1432 .mclk_dividers = sun4i_i2s_mclk_div,
1433 .num_mclk_dividers = ARRAY_SIZE(sun4i_i2s_mclk_div),
1434 .get_bclk_parent_rate = sun4i_i2s_get_bclk_parent_rate,
1435 .get_sr = sun4i_i2s_get_sr,
1436 .get_wss = sun4i_i2s_get_wss,
1437 .set_chan_cfg = sun4i_i2s_set_chan_cfg,
1438 .set_fmt = sun4i_i2s_set_soc_fmt,
1439 };
1440
1441 static const struct sun4i_i2s_quirks sun50i_h6_i2s_quirks = {
1442 .has_reset = true,
1443 .reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG,
1444 .sun4i_i2s_regmap = &sun50i_h6_i2s_regmap_config,
1445 .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 8, 8),
1446 .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 2),
1447 .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 6),
1448 .bclk_dividers = sun8i_i2s_clk_div,
1449 .num_bclk_dividers = ARRAY_SIZE(sun8i_i2s_clk_div),
1450 .mclk_dividers = sun8i_i2s_clk_div,
1451 .num_mclk_dividers = ARRAY_SIZE(sun8i_i2s_clk_div),
1452 .get_bclk_parent_rate = sun8i_i2s_get_bclk_parent_rate,
1453 .get_sr = sun8i_i2s_get_sr_wss,
1454 .get_wss = sun8i_i2s_get_sr_wss,
1455 .set_chan_cfg = sun50i_h6_i2s_set_chan_cfg,
1456 .set_fmt = sun50i_h6_i2s_set_soc_fmt,
1457 };
1458
1459 static const struct sun4i_i2s_quirks sun50i_r329_i2s_quirks = {
1460 .has_reset = true,
1461 .reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG,
1462 .sun4i_i2s_regmap = &sun50i_h6_i2s_regmap_config,
1463 .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 8, 8),
1464 .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 2),
1465 .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 6),
1466 .num_din_pins = 4,
1467 .num_dout_pins = 4,
1468 .bclk_dividers = sun8i_i2s_clk_div,
1469 .num_bclk_dividers = ARRAY_SIZE(sun8i_i2s_clk_div),
1470 .mclk_dividers = sun8i_i2s_clk_div,
1471 .num_mclk_dividers = ARRAY_SIZE(sun8i_i2s_clk_div),
1472 .get_bclk_parent_rate = sun8i_i2s_get_bclk_parent_rate,
1473 .get_sr = sun8i_i2s_get_sr_wss,
1474 .get_wss = sun8i_i2s_get_sr_wss,
1475 .set_chan_cfg = sun50i_h6_i2s_set_chan_cfg,
1476 .set_fmt = sun50i_h6_i2s_set_soc_fmt,
1477 };
1478
sun4i_i2s_init_regmap_fields(struct device * dev,struct sun4i_i2s * i2s)1479 static int sun4i_i2s_init_regmap_fields(struct device *dev,
1480 struct sun4i_i2s *i2s)
1481 {
1482 i2s->field_clkdiv_mclk_en =
1483 devm_regmap_field_alloc(dev, i2s->regmap,
1484 i2s->variant->field_clkdiv_mclk_en);
1485 if (IS_ERR(i2s->field_clkdiv_mclk_en))
1486 return PTR_ERR(i2s->field_clkdiv_mclk_en);
1487
1488 i2s->field_fmt_wss =
1489 devm_regmap_field_alloc(dev, i2s->regmap,
1490 i2s->variant->field_fmt_wss);
1491 if (IS_ERR(i2s->field_fmt_wss))
1492 return PTR_ERR(i2s->field_fmt_wss);
1493
1494 i2s->field_fmt_sr =
1495 devm_regmap_field_alloc(dev, i2s->regmap,
1496 i2s->variant->field_fmt_sr);
1497 if (IS_ERR(i2s->field_fmt_sr))
1498 return PTR_ERR(i2s->field_fmt_sr);
1499
1500 return 0;
1501 }
1502
sun4i_i2s_probe(struct platform_device * pdev)1503 static int sun4i_i2s_probe(struct platform_device *pdev)
1504 {
1505 struct sun4i_i2s *i2s;
1506 struct resource *res;
1507 void __iomem *regs;
1508 int irq, ret;
1509
1510 i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
1511 if (!i2s)
1512 return -ENOMEM;
1513 platform_set_drvdata(pdev, i2s);
1514
1515 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1516 if (IS_ERR(regs))
1517 return PTR_ERR(regs);
1518
1519 irq = platform_get_irq(pdev, 0);
1520 if (irq < 0)
1521 return irq;
1522
1523 i2s->variant = of_device_get_match_data(&pdev->dev);
1524 if (!i2s->variant) {
1525 dev_err(&pdev->dev, "Failed to determine the quirks to use\n");
1526 return -ENODEV;
1527 }
1528
1529 i2s->bus_clk = devm_clk_get(&pdev->dev, "apb");
1530 if (IS_ERR(i2s->bus_clk)) {
1531 dev_err(&pdev->dev, "Can't get our bus clock\n");
1532 return PTR_ERR(i2s->bus_clk);
1533 }
1534
1535 i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
1536 i2s->variant->sun4i_i2s_regmap);
1537 if (IS_ERR(i2s->regmap)) {
1538 dev_err(&pdev->dev, "Regmap initialisation failed\n");
1539 return PTR_ERR(i2s->regmap);
1540 }
1541
1542 i2s->mod_clk = devm_clk_get(&pdev->dev, "mod");
1543 if (IS_ERR(i2s->mod_clk)) {
1544 dev_err(&pdev->dev, "Can't get our mod clock\n");
1545 return PTR_ERR(i2s->mod_clk);
1546 }
1547
1548 if (i2s->variant->has_reset) {
1549 i2s->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
1550 if (IS_ERR(i2s->rst)) {
1551 dev_err(&pdev->dev, "Failed to get reset control\n");
1552 return PTR_ERR(i2s->rst);
1553 }
1554 }
1555
1556 if (!IS_ERR(i2s->rst)) {
1557 ret = reset_control_deassert(i2s->rst);
1558 if (ret) {
1559 dev_err(&pdev->dev,
1560 "Failed to deassert the reset control\n");
1561 return -EINVAL;
1562 }
1563 }
1564
1565 i2s->playback_dma_data.addr = res->start +
1566 i2s->variant->reg_offset_txdata;
1567 i2s->playback_dma_data.maxburst = 8;
1568
1569 i2s->capture_dma_data.addr = res->start + SUN4I_I2S_FIFO_RX_REG;
1570 i2s->capture_dma_data.maxburst = 8;
1571
1572 pm_runtime_enable(&pdev->dev);
1573 if (!pm_runtime_enabled(&pdev->dev)) {
1574 ret = sun4i_i2s_runtime_resume(&pdev->dev);
1575 if (ret)
1576 goto err_pm_disable;
1577 }
1578
1579 ret = sun4i_i2s_init_regmap_fields(&pdev->dev, i2s);
1580 if (ret) {
1581 dev_err(&pdev->dev, "Could not initialise regmap fields\n");
1582 goto err_suspend;
1583 }
1584
1585 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
1586 if (ret) {
1587 dev_err(&pdev->dev, "Could not register PCM\n");
1588 goto err_suspend;
1589 }
1590
1591 ret = devm_snd_soc_register_component(&pdev->dev,
1592 &sun4i_i2s_component,
1593 &sun4i_i2s_dai, 1);
1594 if (ret) {
1595 dev_err(&pdev->dev, "Could not register DAI\n");
1596 goto err_suspend;
1597 }
1598
1599 return 0;
1600
1601 err_suspend:
1602 if (!pm_runtime_status_suspended(&pdev->dev))
1603 sun4i_i2s_runtime_suspend(&pdev->dev);
1604 err_pm_disable:
1605 pm_runtime_disable(&pdev->dev);
1606 if (!IS_ERR(i2s->rst))
1607 reset_control_assert(i2s->rst);
1608
1609 return ret;
1610 }
1611
sun4i_i2s_remove(struct platform_device * pdev)1612 static void sun4i_i2s_remove(struct platform_device *pdev)
1613 {
1614 struct sun4i_i2s *i2s = dev_get_drvdata(&pdev->dev);
1615
1616 pm_runtime_disable(&pdev->dev);
1617 if (!pm_runtime_status_suspended(&pdev->dev))
1618 sun4i_i2s_runtime_suspend(&pdev->dev);
1619
1620 if (!IS_ERR(i2s->rst))
1621 reset_control_assert(i2s->rst);
1622 }
1623
1624 static const struct of_device_id sun4i_i2s_match[] = {
1625 {
1626 .compatible = "allwinner,sun4i-a10-i2s",
1627 .data = &sun4i_a10_i2s_quirks,
1628 },
1629 {
1630 .compatible = "allwinner,sun6i-a31-i2s",
1631 .data = &sun6i_a31_i2s_quirks,
1632 },
1633 {
1634 .compatible = "allwinner,sun8i-a83t-i2s",
1635 .data = &sun8i_a83t_i2s_quirks,
1636 },
1637 {
1638 .compatible = "allwinner,sun8i-h3-i2s",
1639 .data = &sun8i_h3_i2s_quirks,
1640 },
1641 {
1642 .compatible = "allwinner,sun50i-a64-codec-i2s",
1643 .data = &sun50i_a64_codec_i2s_quirks,
1644 },
1645 {
1646 .compatible = "allwinner,sun50i-h6-i2s",
1647 .data = &sun50i_h6_i2s_quirks,
1648 },
1649 {
1650 .compatible = "allwinner,sun50i-r329-i2s",
1651 .data = &sun50i_r329_i2s_quirks,
1652 },
1653 {}
1654 };
1655 MODULE_DEVICE_TABLE(of, sun4i_i2s_match);
1656
1657 static const struct dev_pm_ops sun4i_i2s_pm_ops = {
1658 .runtime_resume = sun4i_i2s_runtime_resume,
1659 .runtime_suspend = sun4i_i2s_runtime_suspend,
1660 };
1661
1662 static struct platform_driver sun4i_i2s_driver = {
1663 .probe = sun4i_i2s_probe,
1664 .remove_new = sun4i_i2s_remove,
1665 .driver = {
1666 .name = "sun4i-i2s",
1667 .of_match_table = sun4i_i2s_match,
1668 .pm = &sun4i_i2s_pm_ops,
1669 },
1670 };
1671 module_platform_driver(sun4i_i2s_driver);
1672
1673 MODULE_AUTHOR("Andrea Venturi <be17068@iperbole.bo.it>");
1674 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
1675 MODULE_DESCRIPTION("Allwinner A10 I2S driver");
1676 MODULE_LICENSE("GPL");
1677