xref: /openbmc/linux/drivers/scsi/stex.c (revision 6d074ce2)
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * SuperTrak EX Series Storage Controller driver for Linux
4  *
5  *	Copyright (C) 2005-2015 Promise Technology Inc.
6  *
7  *	Written By:
8  *		Ed Lin <promise_linux@promise.com>
9  */
10 
11 #include <linux/init.h>
12 #include <linux/errno.h>
13 #include <linux/kernel.h>
14 #include <linux/delay.h>
15 #include <linux/slab.h>
16 #include <linux/time.h>
17 #include <linux/pci.h>
18 #include <linux/blkdev.h>
19 #include <linux/interrupt.h>
20 #include <linux/types.h>
21 #include <linux/module.h>
22 #include <linux/spinlock.h>
23 #include <linux/ktime.h>
24 #include <linux/reboot.h>
25 #include <asm/io.h>
26 #include <asm/irq.h>
27 #include <asm/byteorder.h>
28 #include <scsi/scsi.h>
29 #include <scsi/scsi_device.h>
30 #include <scsi/scsi_cmnd.h>
31 #include <scsi/scsi_host.h>
32 #include <scsi/scsi_tcq.h>
33 #include <scsi/scsi_dbg.h>
34 #include <scsi/scsi_eh.h>
35 
36 #define DRV_NAME "stex"
37 #define ST_DRIVER_VERSION	"6.02.0000.01"
38 #define ST_VER_MAJOR		6
39 #define ST_VER_MINOR		02
40 #define ST_OEM				0000
41 #define ST_BUILD_VER		01
42 
43 enum {
44 	/* MU register offset */
45 	IMR0	= 0x10,	/* MU_INBOUND_MESSAGE_REG0 */
46 	IMR1	= 0x14,	/* MU_INBOUND_MESSAGE_REG1 */
47 	OMR0	= 0x18,	/* MU_OUTBOUND_MESSAGE_REG0 */
48 	OMR1	= 0x1c,	/* MU_OUTBOUND_MESSAGE_REG1 */
49 	IDBL	= 0x20,	/* MU_INBOUND_DOORBELL */
50 	IIS	= 0x24,	/* MU_INBOUND_INTERRUPT_STATUS */
51 	IIM	= 0x28,	/* MU_INBOUND_INTERRUPT_MASK */
52 	ODBL	= 0x2c,	/* MU_OUTBOUND_DOORBELL */
53 	OIS	= 0x30,	/* MU_OUTBOUND_INTERRUPT_STATUS */
54 	OIM	= 0x3c,	/* MU_OUTBOUND_INTERRUPT_MASK */
55 
56 	YIOA_STATUS				= 0x00,
57 	YH2I_INT				= 0x20,
58 	YINT_EN					= 0x34,
59 	YI2H_INT				= 0x9c,
60 	YI2H_INT_C				= 0xa0,
61 	YH2I_REQ				= 0xc0,
62 	YH2I_REQ_HI				= 0xc4,
63 	PSCRATCH0				= 0xb0,
64 	PSCRATCH1				= 0xb4,
65 	PSCRATCH2				= 0xb8,
66 	PSCRATCH3				= 0xbc,
67 	PSCRATCH4				= 0xc8,
68 	MAILBOX_BASE			= 0x1000,
69 	MAILBOX_HNDSHK_STS		= 0x0,
70 
71 	/* MU register value */
72 	MU_INBOUND_DOORBELL_HANDSHAKE		= (1 << 0),
73 	MU_INBOUND_DOORBELL_REQHEADCHANGED	= (1 << 1),
74 	MU_INBOUND_DOORBELL_STATUSTAILCHANGED	= (1 << 2),
75 	MU_INBOUND_DOORBELL_HMUSTOPPED		= (1 << 3),
76 	MU_INBOUND_DOORBELL_RESET		= (1 << 4),
77 
78 	MU_OUTBOUND_DOORBELL_HANDSHAKE		= (1 << 0),
79 	MU_OUTBOUND_DOORBELL_REQUESTTAILCHANGED	= (1 << 1),
80 	MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED	= (1 << 2),
81 	MU_OUTBOUND_DOORBELL_BUSCHANGE		= (1 << 3),
82 	MU_OUTBOUND_DOORBELL_HASEVENT		= (1 << 4),
83 	MU_OUTBOUND_DOORBELL_REQUEST_RESET	= (1 << 27),
84 
85 	/* MU status code */
86 	MU_STATE_STARTING			= 1,
87 	MU_STATE_STARTED			= 2,
88 	MU_STATE_RESETTING			= 3,
89 	MU_STATE_FAILED				= 4,
90 	MU_STATE_STOP				= 5,
91 	MU_STATE_NOCONNECT			= 6,
92 
93 	MU_MAX_DELAY				= 50,
94 	MU_HANDSHAKE_SIGNATURE			= 0x55aaaa55,
95 	MU_HANDSHAKE_SIGNATURE_HALF		= 0x5a5a0000,
96 	MU_HARD_RESET_WAIT			= 30000,
97 	HMU_PARTNER_TYPE			= 2,
98 
99 	/* firmware returned values */
100 	SRB_STATUS_SUCCESS			= 0x01,
101 	SRB_STATUS_ERROR			= 0x04,
102 	SRB_STATUS_BUSY				= 0x05,
103 	SRB_STATUS_INVALID_REQUEST		= 0x06,
104 	SRB_STATUS_SELECTION_TIMEOUT		= 0x0A,
105 	SRB_SEE_SENSE 				= 0x80,
106 
107 	/* task attribute */
108 	TASK_ATTRIBUTE_SIMPLE			= 0x0,
109 	TASK_ATTRIBUTE_HEADOFQUEUE		= 0x1,
110 	TASK_ATTRIBUTE_ORDERED			= 0x2,
111 	TASK_ATTRIBUTE_ACA			= 0x4,
112 };
113 
114 enum {
115 	SS_STS_NORMAL				= 0x80000000,
116 	SS_STS_DONE				= 0x40000000,
117 	SS_STS_HANDSHAKE			= 0x20000000,
118 
119 	SS_HEAD_HANDSHAKE			= 0x80,
120 
121 	SS_H2I_INT_RESET			= 0x100,
122 
123 	SS_I2H_REQUEST_RESET			= 0x2000,
124 
125 	SS_MU_OPERATIONAL			= 0x80000000,
126 };
127 
128 enum {
129 	STEX_CDB_LENGTH				= 16,
130 	STATUS_VAR_LEN				= 128,
131 
132 	/* sg flags */
133 	SG_CF_EOT				= 0x80,	/* end of table */
134 	SG_CF_64B				= 0x40,	/* 64 bit item */
135 	SG_CF_HOST				= 0x20,	/* sg in host memory */
136 	MSG_DATA_DIR_ND				= 0,
137 	MSG_DATA_DIR_IN				= 1,
138 	MSG_DATA_DIR_OUT			= 2,
139 
140 	st_shasta				= 0,
141 	st_vsc					= 1,
142 	st_yosemite				= 2,
143 	st_seq					= 3,
144 	st_yel					= 4,
145 	st_P3					= 5,
146 
147 	PASSTHRU_REQ_TYPE			= 0x00000001,
148 	PASSTHRU_REQ_NO_WAKEUP			= 0x00000100,
149 	ST_INTERNAL_TIMEOUT			= 180,
150 
151 	ST_TO_CMD				= 0,
152 	ST_FROM_CMD				= 1,
153 
154 	/* vendor specific commands of Promise */
155 	MGT_CMD					= 0xd8,
156 	SINBAND_MGT_CMD				= 0xd9,
157 	ARRAY_CMD				= 0xe0,
158 	CONTROLLER_CMD				= 0xe1,
159 	DEBUGGING_CMD				= 0xe2,
160 	PASSTHRU_CMD				= 0xe3,
161 
162 	PASSTHRU_GET_ADAPTER			= 0x05,
163 	PASSTHRU_GET_DRVVER			= 0x10,
164 
165 	CTLR_CONFIG_CMD				= 0x03,
166 	CTLR_SHUTDOWN				= 0x0d,
167 
168 	CTLR_POWER_STATE_CHANGE			= 0x0e,
169 	CTLR_POWER_SAVING			= 0x01,
170 
171 	PASSTHRU_SIGNATURE			= 0x4e415041,
172 	MGT_CMD_SIGNATURE			= 0xba,
173 
174 	INQUIRY_EVPD				= 0x01,
175 
176 	ST_ADDITIONAL_MEM			= 0x200000,
177 	ST_ADDITIONAL_MEM_MIN			= 0x80000,
178 	PMIC_SHUTDOWN				= 0x0D,
179 	PMIC_REUMSE					= 0x10,
180 	ST_IGNORED					= -1,
181 	ST_NOTHANDLED				= 7,
182 	ST_S3						= 3,
183 	ST_S4						= 4,
184 	ST_S5						= 5,
185 	ST_S6						= 6,
186 };
187 
188 struct st_sgitem {
189 	u8 ctrl;	/* SG_CF_xxx */
190 	u8 reserved[3];
191 	__le32 count;
192 	__le64 addr;
193 };
194 
195 struct st_ss_sgitem {
196 	__le32 addr;
197 	__le32 addr_hi;
198 	__le32 count;
199 };
200 
201 struct st_sgtable {
202 	__le16 sg_count;
203 	__le16 max_sg_count;
204 	__le32 sz_in_byte;
205 };
206 
207 struct st_msg_header {
208 	__le64 handle;
209 	u8 flag;
210 	u8 channel;
211 	__le16 timeout;
212 	u32 reserved;
213 };
214 
215 struct handshake_frame {
216 	__le64 rb_phy;		/* request payload queue physical address */
217 	__le16 req_sz;		/* size of each request payload */
218 	__le16 req_cnt;		/* count of reqs the buffer can hold */
219 	__le16 status_sz;	/* size of each status payload */
220 	__le16 status_cnt;	/* count of status the buffer can hold */
221 	__le64 hosttime;	/* seconds from Jan 1, 1970 (GMT) */
222 	u8 partner_type;	/* who sends this frame */
223 	u8 reserved0[7];
224 	__le32 partner_ver_major;
225 	__le32 partner_ver_minor;
226 	__le32 partner_ver_oem;
227 	__le32 partner_ver_build;
228 	__le32 extra_offset;	/* NEW */
229 	__le32 extra_size;	/* NEW */
230 	__le32 scratch_size;
231 	u32 reserved1;
232 };
233 
234 struct req_msg {
235 	__le16 tag;
236 	u8 lun;
237 	u8 target;
238 	u8 task_attr;
239 	u8 task_manage;
240 	u8 data_dir;
241 	u8 payload_sz;		/* payload size in 4-byte, not used */
242 	u8 cdb[STEX_CDB_LENGTH];
243 	u32 variable[];
244 };
245 
246 struct status_msg {
247 	__le16 tag;
248 	u8 lun;
249 	u8 target;
250 	u8 srb_status;
251 	u8 scsi_status;
252 	u8 reserved;
253 	u8 payload_sz;		/* payload size in 4-byte */
254 	u8 variable[STATUS_VAR_LEN];
255 };
256 
257 struct ver_info {
258 	u32 major;
259 	u32 minor;
260 	u32 oem;
261 	u32 build;
262 	u32 reserved[2];
263 };
264 
265 struct st_frame {
266 	u32 base[6];
267 	u32 rom_addr;
268 
269 	struct ver_info drv_ver;
270 	struct ver_info bios_ver;
271 
272 	u32 bus;
273 	u32 slot;
274 	u32 irq_level;
275 	u32 irq_vec;
276 	u32 id;
277 	u32 subid;
278 
279 	u32 dimm_size;
280 	u8 dimm_type;
281 	u8 reserved[3];
282 
283 	u32 channel;
284 	u32 reserved1;
285 };
286 
287 struct st_drvver {
288 	u32 major;
289 	u32 minor;
290 	u32 oem;
291 	u32 build;
292 	u32 signature[2];
293 	u8 console_id;
294 	u8 host_no;
295 	u8 reserved0[2];
296 	u32 reserved[3];
297 };
298 
299 struct st_ccb {
300 	struct req_msg *req;
301 	struct scsi_cmnd *cmd;
302 
303 	void *sense_buffer;
304 	unsigned int sense_bufflen;
305 	int sg_count;
306 
307 	u32 req_type;
308 	u8 srb_status;
309 	u8 scsi_status;
310 	u8 reserved[2];
311 };
312 
313 struct st_hba {
314 	void __iomem *mmio_base;	/* iomapped PCI memory space */
315 	void *dma_mem;
316 	dma_addr_t dma_handle;
317 	size_t dma_size;
318 
319 	struct Scsi_Host *host;
320 	struct pci_dev *pdev;
321 
322 	struct req_msg * (*alloc_rq) (struct st_hba *);
323 	int (*map_sg)(struct st_hba *, struct req_msg *, struct st_ccb *);
324 	void (*send) (struct st_hba *, struct req_msg *, u16);
325 
326 	u32 req_head;
327 	u32 req_tail;
328 	u32 status_head;
329 	u32 status_tail;
330 
331 	struct status_msg *status_buffer;
332 	void *copy_buffer; /* temp buffer for driver-handled commands */
333 	struct st_ccb *ccb;
334 	struct st_ccb *wait_ccb;
335 	__le32 *scratch;
336 
337 	char work_q_name[20];
338 	struct workqueue_struct *work_q;
339 	struct work_struct reset_work;
340 	wait_queue_head_t reset_waitq;
341 	unsigned int mu_status;
342 	unsigned int cardtype;
343 	int msi_enabled;
344 	int out_req_cnt;
345 	u32 extra_offset;
346 	u16 rq_count;
347 	u16 rq_size;
348 	u16 sts_count;
349 	u8  supports_pm;
350 	int msi_lock;
351 };
352 
353 struct st_card_info {
354 	struct req_msg * (*alloc_rq) (struct st_hba *);
355 	int (*map_sg)(struct st_hba *, struct req_msg *, struct st_ccb *);
356 	void (*send) (struct st_hba *, struct req_msg *, u16);
357 	unsigned int max_id;
358 	unsigned int max_lun;
359 	unsigned int max_channel;
360 	u16 rq_count;
361 	u16 rq_size;
362 	u16 sts_count;
363 };
364 
365 static int S6flag;
366 static int stex_halt(struct notifier_block *nb, ulong event, void *buf);
367 static struct notifier_block stex_notifier = {
368 	stex_halt, NULL, 0
369 };
370 
371 static int msi;
372 module_param(msi, int, 0);
373 MODULE_PARM_DESC(msi, "Enable Message Signaled Interrupts(0=off, 1=on)");
374 
375 static const char console_inq_page[] =
376 {
377 	0x03,0x00,0x03,0x03,0xFA,0x00,0x00,0x30,
378 	0x50,0x72,0x6F,0x6D,0x69,0x73,0x65,0x20,	/* "Promise " */
379 	0x52,0x41,0x49,0x44,0x20,0x43,0x6F,0x6E,	/* "RAID Con" */
380 	0x73,0x6F,0x6C,0x65,0x20,0x20,0x20,0x20,	/* "sole    " */
381 	0x31,0x2E,0x30,0x30,0x20,0x20,0x20,0x20,	/* "1.00    " */
382 	0x53,0x58,0x2F,0x52,0x53,0x41,0x46,0x2D,	/* "SX/RSAF-" */
383 	0x54,0x45,0x31,0x2E,0x30,0x30,0x20,0x20,	/* "TE1.00  " */
384 	0x0C,0x20,0x20,0x20,0x20,0x20,0x20,0x20
385 };
386 
387 MODULE_AUTHOR("Ed Lin");
388 MODULE_DESCRIPTION("Promise Technology SuperTrak EX Controllers");
389 MODULE_LICENSE("GPL");
390 MODULE_VERSION(ST_DRIVER_VERSION);
391 
stex_get_status(struct st_hba * hba)392 static struct status_msg *stex_get_status(struct st_hba *hba)
393 {
394 	struct status_msg *status = hba->status_buffer + hba->status_tail;
395 
396 	++hba->status_tail;
397 	hba->status_tail %= hba->sts_count+1;
398 
399 	return status;
400 }
401 
stex_invalid_field(struct scsi_cmnd * cmd,void (* done)(struct scsi_cmnd *))402 static void stex_invalid_field(struct scsi_cmnd *cmd,
403 			       void (*done)(struct scsi_cmnd *))
404 {
405 	/* "Invalid field in cdb" */
406 	scsi_build_sense(cmd, 0, ILLEGAL_REQUEST, 0x24, 0x0);
407 	done(cmd);
408 }
409 
stex_alloc_req(struct st_hba * hba)410 static struct req_msg *stex_alloc_req(struct st_hba *hba)
411 {
412 	struct req_msg *req = hba->dma_mem + hba->req_head * hba->rq_size;
413 
414 	++hba->req_head;
415 	hba->req_head %= hba->rq_count+1;
416 
417 	return req;
418 }
419 
stex_ss_alloc_req(struct st_hba * hba)420 static struct req_msg *stex_ss_alloc_req(struct st_hba *hba)
421 {
422 	return (struct req_msg *)(hba->dma_mem +
423 		hba->req_head * hba->rq_size + sizeof(struct st_msg_header));
424 }
425 
stex_map_sg(struct st_hba * hba,struct req_msg * req,struct st_ccb * ccb)426 static int stex_map_sg(struct st_hba *hba,
427 	struct req_msg *req, struct st_ccb *ccb)
428 {
429 	struct scsi_cmnd *cmd;
430 	struct scatterlist *sg;
431 	struct st_sgtable *dst;
432 	struct st_sgitem *table;
433 	int i, nseg;
434 
435 	cmd = ccb->cmd;
436 	nseg = scsi_dma_map(cmd);
437 	BUG_ON(nseg < 0);
438 	if (nseg) {
439 		dst = (struct st_sgtable *)req->variable;
440 
441 		ccb->sg_count = nseg;
442 		dst->sg_count = cpu_to_le16((u16)nseg);
443 		dst->max_sg_count = cpu_to_le16(hba->host->sg_tablesize);
444 		dst->sz_in_byte = cpu_to_le32(scsi_bufflen(cmd));
445 
446 		table = (struct st_sgitem *)(dst + 1);
447 		scsi_for_each_sg(cmd, sg, nseg, i) {
448 			table[i].count = cpu_to_le32((u32)sg_dma_len(sg));
449 			table[i].addr = cpu_to_le64(sg_dma_address(sg));
450 			table[i].ctrl = SG_CF_64B | SG_CF_HOST;
451 		}
452 		table[--i].ctrl |= SG_CF_EOT;
453 	}
454 
455 	return nseg;
456 }
457 
stex_ss_map_sg(struct st_hba * hba,struct req_msg * req,struct st_ccb * ccb)458 static int stex_ss_map_sg(struct st_hba *hba,
459 	struct req_msg *req, struct st_ccb *ccb)
460 {
461 	struct scsi_cmnd *cmd;
462 	struct scatterlist *sg;
463 	struct st_sgtable *dst;
464 	struct st_ss_sgitem *table;
465 	int i, nseg;
466 
467 	cmd = ccb->cmd;
468 	nseg = scsi_dma_map(cmd);
469 	BUG_ON(nseg < 0);
470 	if (nseg) {
471 		dst = (struct st_sgtable *)req->variable;
472 
473 		ccb->sg_count = nseg;
474 		dst->sg_count = cpu_to_le16((u16)nseg);
475 		dst->max_sg_count = cpu_to_le16(hba->host->sg_tablesize);
476 		dst->sz_in_byte = cpu_to_le32(scsi_bufflen(cmd));
477 
478 		table = (struct st_ss_sgitem *)(dst + 1);
479 		scsi_for_each_sg(cmd, sg, nseg, i) {
480 			table[i].count = cpu_to_le32((u32)sg_dma_len(sg));
481 			table[i].addr =
482 				cpu_to_le32(sg_dma_address(sg) & 0xffffffff);
483 			table[i].addr_hi =
484 				cpu_to_le32((sg_dma_address(sg) >> 16) >> 16);
485 		}
486 	}
487 
488 	return nseg;
489 }
490 
stex_controller_info(struct st_hba * hba,struct st_ccb * ccb)491 static void stex_controller_info(struct st_hba *hba, struct st_ccb *ccb)
492 {
493 	struct st_frame *p;
494 	size_t count = sizeof(struct st_frame);
495 
496 	p = hba->copy_buffer;
497 	scsi_sg_copy_to_buffer(ccb->cmd, p, count);
498 	memset(p->base, 0, sizeof(u32)*6);
499 	*(unsigned long *)(p->base) = pci_resource_start(hba->pdev, 0);
500 	p->rom_addr = 0;
501 
502 	p->drv_ver.major = ST_VER_MAJOR;
503 	p->drv_ver.minor = ST_VER_MINOR;
504 	p->drv_ver.oem = ST_OEM;
505 	p->drv_ver.build = ST_BUILD_VER;
506 
507 	p->bus = hba->pdev->bus->number;
508 	p->slot = hba->pdev->devfn;
509 	p->irq_level = 0;
510 	p->irq_vec = hba->pdev->irq;
511 	p->id = hba->pdev->vendor << 16 | hba->pdev->device;
512 	p->subid =
513 		hba->pdev->subsystem_vendor << 16 | hba->pdev->subsystem_device;
514 
515 	scsi_sg_copy_from_buffer(ccb->cmd, p, count);
516 }
517 
518 static void
stex_send_cmd(struct st_hba * hba,struct req_msg * req,u16 tag)519 stex_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
520 {
521 	req->tag = cpu_to_le16(tag);
522 
523 	hba->ccb[tag].req = req;
524 	hba->out_req_cnt++;
525 
526 	writel(hba->req_head, hba->mmio_base + IMR0);
527 	writel(MU_INBOUND_DOORBELL_REQHEADCHANGED, hba->mmio_base + IDBL);
528 	readl(hba->mmio_base + IDBL); /* flush */
529 }
530 
531 static void
stex_ss_send_cmd(struct st_hba * hba,struct req_msg * req,u16 tag)532 stex_ss_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
533 {
534 	struct scsi_cmnd *cmd;
535 	struct st_msg_header *msg_h;
536 	dma_addr_t addr;
537 
538 	req->tag = cpu_to_le16(tag);
539 
540 	hba->ccb[tag].req = req;
541 	hba->out_req_cnt++;
542 
543 	cmd = hba->ccb[tag].cmd;
544 	msg_h = (struct st_msg_header *)req - 1;
545 	if (likely(cmd)) {
546 		msg_h->channel = (u8)cmd->device->channel;
547 		msg_h->timeout = cpu_to_le16(scsi_cmd_to_rq(cmd)->timeout / HZ);
548 	}
549 	addr = hba->dma_handle + hba->req_head * hba->rq_size;
550 	addr += (hba->ccb[tag].sg_count+4)/11;
551 	msg_h->handle = cpu_to_le64(addr);
552 
553 	++hba->req_head;
554 	hba->req_head %= hba->rq_count+1;
555 	if (hba->cardtype == st_P3) {
556 		writel((addr >> 16) >> 16, hba->mmio_base + YH2I_REQ_HI);
557 		writel(addr, hba->mmio_base + YH2I_REQ);
558 	} else {
559 		writel((addr >> 16) >> 16, hba->mmio_base + YH2I_REQ_HI);
560 		readl(hba->mmio_base + YH2I_REQ_HI); /* flush */
561 		writel(addr, hba->mmio_base + YH2I_REQ);
562 		readl(hba->mmio_base + YH2I_REQ); /* flush */
563 	}
564 }
565 
return_abnormal_state(struct st_hba * hba,int status)566 static void return_abnormal_state(struct st_hba *hba, int status)
567 {
568 	struct st_ccb *ccb;
569 	unsigned long flags;
570 	u16 tag;
571 
572 	spin_lock_irqsave(hba->host->host_lock, flags);
573 	for (tag = 0; tag < hba->host->can_queue; tag++) {
574 		ccb = &hba->ccb[tag];
575 		if (ccb->req == NULL)
576 			continue;
577 		ccb->req = NULL;
578 		if (ccb->cmd) {
579 			scsi_dma_unmap(ccb->cmd);
580 			ccb->cmd->result = status << 16;
581 			scsi_done(ccb->cmd);
582 			ccb->cmd = NULL;
583 		}
584 	}
585 	spin_unlock_irqrestore(hba->host->host_lock, flags);
586 }
587 static int
stex_slave_config(struct scsi_device * sdev)588 stex_slave_config(struct scsi_device *sdev)
589 {
590 	sdev->use_10_for_rw = 1;
591 	sdev->use_10_for_ms = 1;
592 	blk_queue_rq_timeout(sdev->request_queue, 60 * HZ);
593 
594 	return 0;
595 }
596 
stex_queuecommand_lck(struct scsi_cmnd * cmd)597 static int stex_queuecommand_lck(struct scsi_cmnd *cmd)
598 {
599 	void (*done)(struct scsi_cmnd *) = scsi_done;
600 	struct st_hba *hba;
601 	struct Scsi_Host *host;
602 	unsigned int id, lun;
603 	struct req_msg *req;
604 	u16 tag;
605 
606 	host = cmd->device->host;
607 	id = cmd->device->id;
608 	lun = cmd->device->lun;
609 	hba = (struct st_hba *) &host->hostdata[0];
610 	if (hba->mu_status == MU_STATE_NOCONNECT) {
611 		cmd->result = DID_NO_CONNECT;
612 		done(cmd);
613 		return 0;
614 	}
615 	if (unlikely(hba->mu_status != MU_STATE_STARTED))
616 		return SCSI_MLQUEUE_HOST_BUSY;
617 
618 	switch (cmd->cmnd[0]) {
619 	case MODE_SENSE_10:
620 	{
621 		static char ms10_caching_page[12] =
622 			{ 0, 0x12, 0, 0, 0, 0, 0, 0, 0x8, 0xa, 0x4, 0 };
623 		unsigned char page;
624 
625 		page = cmd->cmnd[2] & 0x3f;
626 		if (page == 0x8 || page == 0x3f) {
627 			scsi_sg_copy_from_buffer(cmd, ms10_caching_page,
628 						 sizeof(ms10_caching_page));
629 			cmd->result = DID_OK << 16;
630 			done(cmd);
631 		} else
632 			stex_invalid_field(cmd, done);
633 		return 0;
634 	}
635 	case REPORT_LUNS:
636 		/*
637 		 * The shasta firmware does not report actual luns in the
638 		 * target, so fail the command to force sequential lun scan.
639 		 * Also, the console device does not support this command.
640 		 */
641 		if (hba->cardtype == st_shasta || id == host->max_id - 1) {
642 			stex_invalid_field(cmd, done);
643 			return 0;
644 		}
645 		break;
646 	case TEST_UNIT_READY:
647 		if (id == host->max_id - 1) {
648 			cmd->result = DID_OK << 16;
649 			done(cmd);
650 			return 0;
651 		}
652 		break;
653 	case INQUIRY:
654 		if (lun >= host->max_lun) {
655 			cmd->result = DID_NO_CONNECT << 16;
656 			done(cmd);
657 			return 0;
658 		}
659 		if (id != host->max_id - 1)
660 			break;
661 		if (!lun && !cmd->device->channel &&
662 			(cmd->cmnd[1] & INQUIRY_EVPD) == 0) {
663 			scsi_sg_copy_from_buffer(cmd, (void *)console_inq_page,
664 						 sizeof(console_inq_page));
665 			cmd->result = DID_OK << 16;
666 			done(cmd);
667 		} else
668 			stex_invalid_field(cmd, done);
669 		return 0;
670 	case PASSTHRU_CMD:
671 		if (cmd->cmnd[1] == PASSTHRU_GET_DRVVER) {
672 			const struct st_drvver ver = {
673 				.major = ST_VER_MAJOR,
674 				.minor = ST_VER_MINOR,
675 				.oem = ST_OEM,
676 				.build = ST_BUILD_VER,
677 				.signature[0] = PASSTHRU_SIGNATURE,
678 				.console_id = host->max_id - 1,
679 				.host_no = hba->host->host_no,
680 			};
681 			size_t cp_len = sizeof(ver);
682 
683 			cp_len = scsi_sg_copy_from_buffer(cmd, &ver, cp_len);
684 			if (sizeof(ver) == cp_len)
685 				cmd->result = DID_OK << 16;
686 			else
687 				cmd->result = DID_ERROR << 16;
688 			done(cmd);
689 			return 0;
690 		}
691 		break;
692 	default:
693 		break;
694 	}
695 
696 	tag = scsi_cmd_to_rq(cmd)->tag;
697 
698 	if (unlikely(tag >= host->can_queue))
699 		return SCSI_MLQUEUE_HOST_BUSY;
700 
701 	req = hba->alloc_rq(hba);
702 
703 	req->lun = lun;
704 	req->target = id;
705 
706 	/* cdb */
707 	memcpy(req->cdb, cmd->cmnd, STEX_CDB_LENGTH);
708 
709 	if (cmd->sc_data_direction == DMA_FROM_DEVICE)
710 		req->data_dir = MSG_DATA_DIR_IN;
711 	else if (cmd->sc_data_direction == DMA_TO_DEVICE)
712 		req->data_dir = MSG_DATA_DIR_OUT;
713 	else
714 		req->data_dir = MSG_DATA_DIR_ND;
715 
716 	hba->ccb[tag].cmd = cmd;
717 	hba->ccb[tag].sense_bufflen = SCSI_SENSE_BUFFERSIZE;
718 	hba->ccb[tag].sense_buffer = cmd->sense_buffer;
719 
720 	if (!hba->map_sg(hba, req, &hba->ccb[tag])) {
721 		hba->ccb[tag].sg_count = 0;
722 		memset(&req->variable[0], 0, 8);
723 	}
724 
725 	hba->send(hba, req, tag);
726 	return 0;
727 }
728 
DEF_SCSI_QCMD(stex_queuecommand)729 static DEF_SCSI_QCMD(stex_queuecommand)
730 
731 static void stex_scsi_done(struct st_ccb *ccb)
732 {
733 	struct scsi_cmnd *cmd = ccb->cmd;
734 	int result;
735 
736 	if (ccb->srb_status == SRB_STATUS_SUCCESS || ccb->srb_status == 0) {
737 		result = ccb->scsi_status;
738 		switch (ccb->scsi_status) {
739 		case SAM_STAT_GOOD:
740 			result |= DID_OK << 16;
741 			break;
742 		case SAM_STAT_CHECK_CONDITION:
743 			result |= DID_OK << 16;
744 			break;
745 		case SAM_STAT_BUSY:
746 			result |= DID_BUS_BUSY << 16;
747 			break;
748 		default:
749 			result |= DID_ERROR << 16;
750 			break;
751 		}
752 	}
753 	else if (ccb->srb_status & SRB_SEE_SENSE)
754 		result = SAM_STAT_CHECK_CONDITION;
755 	else switch (ccb->srb_status) {
756 		case SRB_STATUS_SELECTION_TIMEOUT:
757 			result = DID_NO_CONNECT << 16;
758 			break;
759 		case SRB_STATUS_BUSY:
760 			result = DID_BUS_BUSY << 16;
761 			break;
762 		case SRB_STATUS_INVALID_REQUEST:
763 		case SRB_STATUS_ERROR:
764 		default:
765 			result = DID_ERROR << 16;
766 			break;
767 	}
768 
769 	cmd->result = result;
770 	scsi_done(cmd);
771 }
772 
stex_copy_data(struct st_ccb * ccb,struct status_msg * resp,unsigned int variable)773 static void stex_copy_data(struct st_ccb *ccb,
774 	struct status_msg *resp, unsigned int variable)
775 {
776 	if (resp->scsi_status != SAM_STAT_GOOD) {
777 		if (ccb->sense_buffer != NULL)
778 			memcpy(ccb->sense_buffer, resp->variable,
779 				min(variable, ccb->sense_bufflen));
780 		return;
781 	}
782 
783 	if (ccb->cmd == NULL)
784 		return;
785 	scsi_sg_copy_from_buffer(ccb->cmd, resp->variable, variable);
786 }
787 
stex_check_cmd(struct st_hba * hba,struct st_ccb * ccb,struct status_msg * resp)788 static void stex_check_cmd(struct st_hba *hba,
789 	struct st_ccb *ccb, struct status_msg *resp)
790 {
791 	if (ccb->cmd->cmnd[0] == MGT_CMD &&
792 		resp->scsi_status != SAM_STAT_CHECK_CONDITION)
793 		scsi_set_resid(ccb->cmd, scsi_bufflen(ccb->cmd) -
794 			le32_to_cpu(*(__le32 *)&resp->variable[0]));
795 }
796 
stex_mu_intr(struct st_hba * hba,u32 doorbell)797 static void stex_mu_intr(struct st_hba *hba, u32 doorbell)
798 {
799 	void __iomem *base = hba->mmio_base;
800 	struct status_msg *resp;
801 	struct st_ccb *ccb;
802 	unsigned int size;
803 	u16 tag;
804 
805 	if (unlikely(!(doorbell & MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED)))
806 		return;
807 
808 	/* status payloads */
809 	hba->status_head = readl(base + OMR1);
810 	if (unlikely(hba->status_head > hba->sts_count)) {
811 		printk(KERN_WARNING DRV_NAME "(%s): invalid status head\n",
812 			pci_name(hba->pdev));
813 		return;
814 	}
815 
816 	/*
817 	 * it's not a valid status payload if:
818 	 * 1. there are no pending requests(e.g. during init stage)
819 	 * 2. there are some pending requests, but the controller is in
820 	 *     reset status, and its type is not st_yosemite
821 	 * firmware of st_yosemite in reset status will return pending requests
822 	 * to driver, so we allow it to pass
823 	 */
824 	if (unlikely(hba->out_req_cnt <= 0 ||
825 			(hba->mu_status == MU_STATE_RESETTING &&
826 			 hba->cardtype != st_yosemite))) {
827 		hba->status_tail = hba->status_head;
828 		goto update_status;
829 	}
830 
831 	while (hba->status_tail != hba->status_head) {
832 		resp = stex_get_status(hba);
833 		tag = le16_to_cpu(resp->tag);
834 		if (unlikely(tag >= hba->host->can_queue)) {
835 			printk(KERN_WARNING DRV_NAME
836 				"(%s): invalid tag\n", pci_name(hba->pdev));
837 			continue;
838 		}
839 
840 		hba->out_req_cnt--;
841 		ccb = &hba->ccb[tag];
842 		if (unlikely(hba->wait_ccb == ccb))
843 			hba->wait_ccb = NULL;
844 		if (unlikely(ccb->req == NULL)) {
845 			printk(KERN_WARNING DRV_NAME
846 				"(%s): lagging req\n", pci_name(hba->pdev));
847 			continue;
848 		}
849 
850 		size = resp->payload_sz * sizeof(u32); /* payload size */
851 		if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
852 			size > sizeof(*resp))) {
853 			printk(KERN_WARNING DRV_NAME "(%s): bad status size\n",
854 				pci_name(hba->pdev));
855 		} else {
856 			size -= sizeof(*resp) - STATUS_VAR_LEN; /* copy size */
857 			if (size)
858 				stex_copy_data(ccb, resp, size);
859 		}
860 
861 		ccb->req = NULL;
862 		ccb->srb_status = resp->srb_status;
863 		ccb->scsi_status = resp->scsi_status;
864 
865 		if (likely(ccb->cmd != NULL)) {
866 			if (hba->cardtype == st_yosemite)
867 				stex_check_cmd(hba, ccb, resp);
868 
869 			if (unlikely(ccb->cmd->cmnd[0] == PASSTHRU_CMD &&
870 				ccb->cmd->cmnd[1] == PASSTHRU_GET_ADAPTER))
871 				stex_controller_info(hba, ccb);
872 
873 			scsi_dma_unmap(ccb->cmd);
874 			stex_scsi_done(ccb);
875 		} else
876 			ccb->req_type = 0;
877 	}
878 
879 update_status:
880 	writel(hba->status_head, base + IMR1);
881 	readl(base + IMR1); /* flush */
882 }
883 
stex_intr(int irq,void * __hba)884 static irqreturn_t stex_intr(int irq, void *__hba)
885 {
886 	struct st_hba *hba = __hba;
887 	void __iomem *base = hba->mmio_base;
888 	u32 data;
889 	unsigned long flags;
890 
891 	spin_lock_irqsave(hba->host->host_lock, flags);
892 
893 	data = readl(base + ODBL);
894 
895 	if (data && data != 0xffffffff) {
896 		/* clear the interrupt */
897 		writel(data, base + ODBL);
898 		readl(base + ODBL); /* flush */
899 		stex_mu_intr(hba, data);
900 		spin_unlock_irqrestore(hba->host->host_lock, flags);
901 		if (unlikely(data & MU_OUTBOUND_DOORBELL_REQUEST_RESET &&
902 			hba->cardtype == st_shasta))
903 			queue_work(hba->work_q, &hba->reset_work);
904 		return IRQ_HANDLED;
905 	}
906 
907 	spin_unlock_irqrestore(hba->host->host_lock, flags);
908 
909 	return IRQ_NONE;
910 }
911 
stex_ss_mu_intr(struct st_hba * hba)912 static void stex_ss_mu_intr(struct st_hba *hba)
913 {
914 	struct status_msg *resp;
915 	struct st_ccb *ccb;
916 	__le32 *scratch;
917 	unsigned int size;
918 	int count = 0;
919 	u32 value;
920 	u16 tag;
921 
922 	if (unlikely(hba->out_req_cnt <= 0 ||
923 			hba->mu_status == MU_STATE_RESETTING))
924 		return;
925 
926 	while (count < hba->sts_count) {
927 		scratch = hba->scratch + hba->status_tail;
928 		value = le32_to_cpu(*scratch);
929 		if (unlikely(!(value & SS_STS_NORMAL)))
930 			return;
931 
932 		resp = hba->status_buffer + hba->status_tail;
933 		*scratch = 0;
934 		++count;
935 		++hba->status_tail;
936 		hba->status_tail %= hba->sts_count+1;
937 
938 		tag = (u16)value;
939 		if (unlikely(tag >= hba->host->can_queue)) {
940 			printk(KERN_WARNING DRV_NAME
941 				"(%s): invalid tag\n", pci_name(hba->pdev));
942 			continue;
943 		}
944 
945 		hba->out_req_cnt--;
946 		ccb = &hba->ccb[tag];
947 		if (unlikely(hba->wait_ccb == ccb))
948 			hba->wait_ccb = NULL;
949 		if (unlikely(ccb->req == NULL)) {
950 			printk(KERN_WARNING DRV_NAME
951 				"(%s): lagging req\n", pci_name(hba->pdev));
952 			continue;
953 		}
954 
955 		ccb->req = NULL;
956 		if (likely(value & SS_STS_DONE)) { /* normal case */
957 			ccb->srb_status = SRB_STATUS_SUCCESS;
958 			ccb->scsi_status = SAM_STAT_GOOD;
959 		} else {
960 			ccb->srb_status = resp->srb_status;
961 			ccb->scsi_status = resp->scsi_status;
962 			size = resp->payload_sz * sizeof(u32);
963 			if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
964 				size > sizeof(*resp))) {
965 				printk(KERN_WARNING DRV_NAME
966 					"(%s): bad status size\n",
967 					pci_name(hba->pdev));
968 			} else {
969 				size -= sizeof(*resp) - STATUS_VAR_LEN;
970 				if (size)
971 					stex_copy_data(ccb, resp, size);
972 			}
973 			if (likely(ccb->cmd != NULL))
974 				stex_check_cmd(hba, ccb, resp);
975 		}
976 
977 		if (likely(ccb->cmd != NULL)) {
978 			scsi_dma_unmap(ccb->cmd);
979 			stex_scsi_done(ccb);
980 		} else
981 			ccb->req_type = 0;
982 	}
983 }
984 
stex_ss_intr(int irq,void * __hba)985 static irqreturn_t stex_ss_intr(int irq, void *__hba)
986 {
987 	struct st_hba *hba = __hba;
988 	void __iomem *base = hba->mmio_base;
989 	u32 data;
990 	unsigned long flags;
991 
992 	spin_lock_irqsave(hba->host->host_lock, flags);
993 
994 	if (hba->cardtype == st_yel) {
995 		data = readl(base + YI2H_INT);
996 		if (data && data != 0xffffffff) {
997 			/* clear the interrupt */
998 			writel(data, base + YI2H_INT_C);
999 			stex_ss_mu_intr(hba);
1000 			spin_unlock_irqrestore(hba->host->host_lock, flags);
1001 			if (unlikely(data & SS_I2H_REQUEST_RESET))
1002 				queue_work(hba->work_q, &hba->reset_work);
1003 			return IRQ_HANDLED;
1004 		}
1005 	} else {
1006 		data = readl(base + PSCRATCH4);
1007 		if (data != 0xffffffff) {
1008 			if (data != 0) {
1009 				/* clear the interrupt */
1010 				writel(data, base + PSCRATCH1);
1011 				writel((1 << 22), base + YH2I_INT);
1012 			}
1013 			stex_ss_mu_intr(hba);
1014 			spin_unlock_irqrestore(hba->host->host_lock, flags);
1015 			if (unlikely(data & SS_I2H_REQUEST_RESET))
1016 				queue_work(hba->work_q, &hba->reset_work);
1017 			return IRQ_HANDLED;
1018 		}
1019 	}
1020 
1021 	spin_unlock_irqrestore(hba->host->host_lock, flags);
1022 
1023 	return IRQ_NONE;
1024 }
1025 
stex_common_handshake(struct st_hba * hba)1026 static int stex_common_handshake(struct st_hba *hba)
1027 {
1028 	void __iomem *base = hba->mmio_base;
1029 	struct handshake_frame *h;
1030 	dma_addr_t status_phys;
1031 	u32 data;
1032 	unsigned long before;
1033 
1034 	if (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
1035 		writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
1036 		readl(base + IDBL);
1037 		before = jiffies;
1038 		while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
1039 			if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1040 				printk(KERN_ERR DRV_NAME
1041 					"(%s): no handshake signature\n",
1042 					pci_name(hba->pdev));
1043 				return -1;
1044 			}
1045 			rmb();
1046 			msleep(1);
1047 		}
1048 	}
1049 
1050 	udelay(10);
1051 
1052 	data = readl(base + OMR1);
1053 	if ((data & 0xffff0000) == MU_HANDSHAKE_SIGNATURE_HALF) {
1054 		data &= 0x0000ffff;
1055 		if (hba->host->can_queue > data) {
1056 			hba->host->can_queue = data;
1057 			hba->host->cmd_per_lun = data;
1058 		}
1059 	}
1060 
1061 	h = (struct handshake_frame *)hba->status_buffer;
1062 	h->rb_phy = cpu_to_le64(hba->dma_handle);
1063 	h->req_sz = cpu_to_le16(hba->rq_size);
1064 	h->req_cnt = cpu_to_le16(hba->rq_count+1);
1065 	h->status_sz = cpu_to_le16(sizeof(struct status_msg));
1066 	h->status_cnt = cpu_to_le16(hba->sts_count+1);
1067 	h->hosttime = cpu_to_le64(ktime_get_real_seconds());
1068 	h->partner_type = HMU_PARTNER_TYPE;
1069 	if (hba->extra_offset) {
1070 		h->extra_offset = cpu_to_le32(hba->extra_offset);
1071 		h->extra_size = cpu_to_le32(hba->dma_size - hba->extra_offset);
1072 	} else
1073 		h->extra_offset = h->extra_size = 0;
1074 
1075 	status_phys = hba->dma_handle + (hba->rq_count+1) * hba->rq_size;
1076 	writel(status_phys, base + IMR0);
1077 	readl(base + IMR0);
1078 	writel((status_phys >> 16) >> 16, base + IMR1);
1079 	readl(base + IMR1);
1080 
1081 	writel((status_phys >> 16) >> 16, base + OMR0); /* old fw compatible */
1082 	readl(base + OMR0);
1083 	writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
1084 	readl(base + IDBL); /* flush */
1085 
1086 	udelay(10);
1087 	before = jiffies;
1088 	while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
1089 		if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1090 			printk(KERN_ERR DRV_NAME
1091 				"(%s): no signature after handshake frame\n",
1092 				pci_name(hba->pdev));
1093 			return -1;
1094 		}
1095 		rmb();
1096 		msleep(1);
1097 	}
1098 
1099 	writel(0, base + IMR0);
1100 	readl(base + IMR0);
1101 	writel(0, base + OMR0);
1102 	readl(base + OMR0);
1103 	writel(0, base + IMR1);
1104 	readl(base + IMR1);
1105 	writel(0, base + OMR1);
1106 	readl(base + OMR1); /* flush */
1107 	return 0;
1108 }
1109 
stex_ss_handshake(struct st_hba * hba)1110 static int stex_ss_handshake(struct st_hba *hba)
1111 {
1112 	void __iomem *base = hba->mmio_base;
1113 	struct st_msg_header *msg_h;
1114 	struct handshake_frame *h;
1115 	__le32 *scratch;
1116 	u32 data, scratch_size, mailboxdata, operationaldata;
1117 	unsigned long before;
1118 	int ret = 0;
1119 
1120 	before = jiffies;
1121 
1122 	if (hba->cardtype == st_yel) {
1123 		operationaldata = readl(base + YIOA_STATUS);
1124 		while (operationaldata != SS_MU_OPERATIONAL) {
1125 			if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1126 				printk(KERN_ERR DRV_NAME
1127 					"(%s): firmware not operational\n",
1128 					pci_name(hba->pdev));
1129 				return -1;
1130 			}
1131 			msleep(1);
1132 			operationaldata = readl(base + YIOA_STATUS);
1133 		}
1134 	} else {
1135 		operationaldata = readl(base + PSCRATCH3);
1136 		while (operationaldata != SS_MU_OPERATIONAL) {
1137 			if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1138 				printk(KERN_ERR DRV_NAME
1139 					"(%s): firmware not operational\n",
1140 					pci_name(hba->pdev));
1141 				return -1;
1142 			}
1143 			msleep(1);
1144 			operationaldata = readl(base + PSCRATCH3);
1145 		}
1146 	}
1147 
1148 	msg_h = (struct st_msg_header *)hba->dma_mem;
1149 	msg_h->handle = cpu_to_le64(hba->dma_handle);
1150 	msg_h->flag = SS_HEAD_HANDSHAKE;
1151 
1152 	h = (struct handshake_frame *)(msg_h + 1);
1153 	h->rb_phy = cpu_to_le64(hba->dma_handle);
1154 	h->req_sz = cpu_to_le16(hba->rq_size);
1155 	h->req_cnt = cpu_to_le16(hba->rq_count+1);
1156 	h->status_sz = cpu_to_le16(sizeof(struct status_msg));
1157 	h->status_cnt = cpu_to_le16(hba->sts_count+1);
1158 	h->hosttime = cpu_to_le64(ktime_get_real_seconds());
1159 	h->partner_type = HMU_PARTNER_TYPE;
1160 	h->extra_offset = h->extra_size = 0;
1161 	scratch_size = (hba->sts_count+1)*sizeof(u32);
1162 	h->scratch_size = cpu_to_le32(scratch_size);
1163 
1164 	if (hba->cardtype == st_yel) {
1165 		data = readl(base + YINT_EN);
1166 		data &= ~4;
1167 		writel(data, base + YINT_EN);
1168 		writel((hba->dma_handle >> 16) >> 16, base + YH2I_REQ_HI);
1169 		readl(base + YH2I_REQ_HI);
1170 		writel(hba->dma_handle, base + YH2I_REQ);
1171 		readl(base + YH2I_REQ); /* flush */
1172 	} else {
1173 		data = readl(base + YINT_EN);
1174 		data &= ~(1 << 0);
1175 		data &= ~(1 << 2);
1176 		writel(data, base + YINT_EN);
1177 		if (hba->msi_lock == 0) {
1178 			/* P3 MSI Register cannot access twice */
1179 			writel((1 << 6), base + YH2I_INT);
1180 			hba->msi_lock  = 1;
1181 		}
1182 		writel((hba->dma_handle >> 16) >> 16, base + YH2I_REQ_HI);
1183 		writel(hba->dma_handle, base + YH2I_REQ);
1184 	}
1185 
1186 	before = jiffies;
1187 	scratch = hba->scratch;
1188 	if (hba->cardtype == st_yel) {
1189 		while (!(le32_to_cpu(*scratch) & SS_STS_HANDSHAKE)) {
1190 			if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1191 				printk(KERN_ERR DRV_NAME
1192 					"(%s): no signature after handshake frame\n",
1193 					pci_name(hba->pdev));
1194 				ret = -1;
1195 				break;
1196 			}
1197 			rmb();
1198 			msleep(1);
1199 		}
1200 	} else {
1201 		mailboxdata = readl(base + MAILBOX_BASE + MAILBOX_HNDSHK_STS);
1202 		while (mailboxdata != SS_STS_HANDSHAKE) {
1203 			if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1204 				printk(KERN_ERR DRV_NAME
1205 					"(%s): no signature after handshake frame\n",
1206 					pci_name(hba->pdev));
1207 				ret = -1;
1208 				break;
1209 			}
1210 			rmb();
1211 			msleep(1);
1212 			mailboxdata = readl(base + MAILBOX_BASE + MAILBOX_HNDSHK_STS);
1213 		}
1214 	}
1215 	memset(scratch, 0, scratch_size);
1216 	msg_h->flag = 0;
1217 
1218 	return ret;
1219 }
1220 
stex_handshake(struct st_hba * hba)1221 static int stex_handshake(struct st_hba *hba)
1222 {
1223 	int err;
1224 	unsigned long flags;
1225 	unsigned int mu_status;
1226 
1227 	if (hba->cardtype == st_yel || hba->cardtype == st_P3)
1228 		err = stex_ss_handshake(hba);
1229 	else
1230 		err = stex_common_handshake(hba);
1231 	spin_lock_irqsave(hba->host->host_lock, flags);
1232 	mu_status = hba->mu_status;
1233 	if (err == 0) {
1234 		hba->req_head = 0;
1235 		hba->req_tail = 0;
1236 		hba->status_head = 0;
1237 		hba->status_tail = 0;
1238 		hba->out_req_cnt = 0;
1239 		hba->mu_status = MU_STATE_STARTED;
1240 	} else
1241 		hba->mu_status = MU_STATE_FAILED;
1242 	if (mu_status == MU_STATE_RESETTING)
1243 		wake_up_all(&hba->reset_waitq);
1244 	spin_unlock_irqrestore(hba->host->host_lock, flags);
1245 	return err;
1246 }
1247 
stex_abort(struct scsi_cmnd * cmd)1248 static int stex_abort(struct scsi_cmnd *cmd)
1249 {
1250 	struct Scsi_Host *host = cmd->device->host;
1251 	struct st_hba *hba = (struct st_hba *)host->hostdata;
1252 	u16 tag = scsi_cmd_to_rq(cmd)->tag;
1253 	void __iomem *base;
1254 	u32 data;
1255 	int result = SUCCESS;
1256 	unsigned long flags;
1257 
1258 	scmd_printk(KERN_INFO, cmd, "aborting command\n");
1259 
1260 	base = hba->mmio_base;
1261 	spin_lock_irqsave(host->host_lock, flags);
1262 	if (tag < host->can_queue &&
1263 		hba->ccb[tag].req && hba->ccb[tag].cmd == cmd)
1264 		hba->wait_ccb = &hba->ccb[tag];
1265 	else
1266 		goto out;
1267 
1268 	if (hba->cardtype == st_yel) {
1269 		data = readl(base + YI2H_INT);
1270 		if (data == 0 || data == 0xffffffff)
1271 			goto fail_out;
1272 
1273 		writel(data, base + YI2H_INT_C);
1274 		stex_ss_mu_intr(hba);
1275 	} else if (hba->cardtype == st_P3) {
1276 		data = readl(base + PSCRATCH4);
1277 		if (data == 0xffffffff)
1278 			goto fail_out;
1279 		if (data != 0) {
1280 			writel(data, base + PSCRATCH1);
1281 			writel((1 << 22), base + YH2I_INT);
1282 		}
1283 		stex_ss_mu_intr(hba);
1284 	} else {
1285 		data = readl(base + ODBL);
1286 		if (data == 0 || data == 0xffffffff)
1287 			goto fail_out;
1288 
1289 		writel(data, base + ODBL);
1290 		readl(base + ODBL); /* flush */
1291 		stex_mu_intr(hba, data);
1292 	}
1293 	if (hba->wait_ccb == NULL) {
1294 		printk(KERN_WARNING DRV_NAME
1295 			"(%s): lost interrupt\n", pci_name(hba->pdev));
1296 		goto out;
1297 	}
1298 
1299 fail_out:
1300 	scsi_dma_unmap(cmd);
1301 	hba->wait_ccb->req = NULL; /* nullify the req's future return */
1302 	hba->wait_ccb = NULL;
1303 	result = FAILED;
1304 out:
1305 	spin_unlock_irqrestore(host->host_lock, flags);
1306 	return result;
1307 }
1308 
stex_hard_reset(struct st_hba * hba)1309 static void stex_hard_reset(struct st_hba *hba)
1310 {
1311 	struct pci_bus *bus;
1312 	int i;
1313 	u16 pci_cmd;
1314 	u8 pci_bctl;
1315 
1316 	for (i = 0; i < 16; i++)
1317 		pci_read_config_dword(hba->pdev, i * 4,
1318 			&hba->pdev->saved_config_space[i]);
1319 
1320 	/* Reset secondary bus. Our controller(MU/ATU) is the only device on
1321 	   secondary bus. Consult Intel 80331/3 developer's manual for detail */
1322 	bus = hba->pdev->bus;
1323 	pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &pci_bctl);
1324 	pci_bctl |= PCI_BRIDGE_CTL_BUS_RESET;
1325 	pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
1326 
1327 	/*
1328 	 * 1 ms may be enough for 8-port controllers. But 16-port controllers
1329 	 * require more time to finish bus reset. Use 100 ms here for safety
1330 	 */
1331 	msleep(100);
1332 	pci_bctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
1333 	pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
1334 
1335 	for (i = 0; i < MU_HARD_RESET_WAIT; i++) {
1336 		pci_read_config_word(hba->pdev, PCI_COMMAND, &pci_cmd);
1337 		if (pci_cmd != 0xffff && (pci_cmd & PCI_COMMAND_MASTER))
1338 			break;
1339 		msleep(1);
1340 	}
1341 
1342 	ssleep(5);
1343 	for (i = 0; i < 16; i++)
1344 		pci_write_config_dword(hba->pdev, i * 4,
1345 			hba->pdev->saved_config_space[i]);
1346 }
1347 
stex_yos_reset(struct st_hba * hba)1348 static int stex_yos_reset(struct st_hba *hba)
1349 {
1350 	void __iomem *base;
1351 	unsigned long flags, before;
1352 	int ret = 0;
1353 
1354 	base = hba->mmio_base;
1355 	writel(MU_INBOUND_DOORBELL_RESET, base + IDBL);
1356 	readl(base + IDBL); /* flush */
1357 	before = jiffies;
1358 	while (hba->out_req_cnt > 0) {
1359 		if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
1360 			printk(KERN_WARNING DRV_NAME
1361 				"(%s): reset timeout\n", pci_name(hba->pdev));
1362 			ret = -1;
1363 			break;
1364 		}
1365 		msleep(1);
1366 	}
1367 
1368 	spin_lock_irqsave(hba->host->host_lock, flags);
1369 	if (ret == -1)
1370 		hba->mu_status = MU_STATE_FAILED;
1371 	else
1372 		hba->mu_status = MU_STATE_STARTED;
1373 	wake_up_all(&hba->reset_waitq);
1374 	spin_unlock_irqrestore(hba->host->host_lock, flags);
1375 
1376 	return ret;
1377 }
1378 
stex_ss_reset(struct st_hba * hba)1379 static void stex_ss_reset(struct st_hba *hba)
1380 {
1381 	writel(SS_H2I_INT_RESET, hba->mmio_base + YH2I_INT);
1382 	readl(hba->mmio_base + YH2I_INT);
1383 	ssleep(5);
1384 }
1385 
stex_p3_reset(struct st_hba * hba)1386 static void stex_p3_reset(struct st_hba *hba)
1387 {
1388 	writel(SS_H2I_INT_RESET, hba->mmio_base + YH2I_INT);
1389 	ssleep(5);
1390 }
1391 
stex_do_reset(struct st_hba * hba)1392 static int stex_do_reset(struct st_hba *hba)
1393 {
1394 	unsigned long flags;
1395 	unsigned int mu_status = MU_STATE_RESETTING;
1396 
1397 	spin_lock_irqsave(hba->host->host_lock, flags);
1398 	if (hba->mu_status == MU_STATE_STARTING) {
1399 		spin_unlock_irqrestore(hba->host->host_lock, flags);
1400 		printk(KERN_INFO DRV_NAME "(%s): request reset during init\n",
1401 			pci_name(hba->pdev));
1402 		return 0;
1403 	}
1404 	while (hba->mu_status == MU_STATE_RESETTING) {
1405 		spin_unlock_irqrestore(hba->host->host_lock, flags);
1406 		wait_event_timeout(hba->reset_waitq,
1407 				   hba->mu_status != MU_STATE_RESETTING,
1408 				   MU_MAX_DELAY * HZ);
1409 		spin_lock_irqsave(hba->host->host_lock, flags);
1410 		mu_status = hba->mu_status;
1411 	}
1412 
1413 	if (mu_status != MU_STATE_RESETTING) {
1414 		spin_unlock_irqrestore(hba->host->host_lock, flags);
1415 		return (mu_status == MU_STATE_STARTED) ? 0 : -1;
1416 	}
1417 
1418 	hba->mu_status = MU_STATE_RESETTING;
1419 	spin_unlock_irqrestore(hba->host->host_lock, flags);
1420 
1421 	if (hba->cardtype == st_yosemite)
1422 		return stex_yos_reset(hba);
1423 
1424 	if (hba->cardtype == st_shasta)
1425 		stex_hard_reset(hba);
1426 	else if (hba->cardtype == st_yel)
1427 		stex_ss_reset(hba);
1428 	else if (hba->cardtype == st_P3)
1429 		stex_p3_reset(hba);
1430 
1431 	return_abnormal_state(hba, DID_RESET);
1432 
1433 	if (stex_handshake(hba) == 0)
1434 		return 0;
1435 
1436 	printk(KERN_WARNING DRV_NAME "(%s): resetting: handshake failed\n",
1437 		pci_name(hba->pdev));
1438 	return -1;
1439 }
1440 
stex_reset(struct scsi_cmnd * cmd)1441 static int stex_reset(struct scsi_cmnd *cmd)
1442 {
1443 	struct st_hba *hba;
1444 
1445 	hba = (struct st_hba *) &cmd->device->host->hostdata[0];
1446 
1447 	shost_printk(KERN_INFO, cmd->device->host,
1448 		     "resetting host\n");
1449 
1450 	return stex_do_reset(hba) ? FAILED : SUCCESS;
1451 }
1452 
stex_reset_work(struct work_struct * work)1453 static void stex_reset_work(struct work_struct *work)
1454 {
1455 	struct st_hba *hba = container_of(work, struct st_hba, reset_work);
1456 
1457 	stex_do_reset(hba);
1458 }
1459 
stex_biosparam(struct scsi_device * sdev,struct block_device * bdev,sector_t capacity,int geom[])1460 static int stex_biosparam(struct scsi_device *sdev,
1461 	struct block_device *bdev, sector_t capacity, int geom[])
1462 {
1463 	int heads = 255, sectors = 63;
1464 
1465 	if (capacity < 0x200000) {
1466 		heads = 64;
1467 		sectors = 32;
1468 	}
1469 
1470 	sector_div(capacity, heads * sectors);
1471 
1472 	geom[0] = heads;
1473 	geom[1] = sectors;
1474 	geom[2] = capacity;
1475 
1476 	return 0;
1477 }
1478 
1479 static const struct scsi_host_template driver_template = {
1480 	.module				= THIS_MODULE,
1481 	.name				= DRV_NAME,
1482 	.proc_name			= DRV_NAME,
1483 	.bios_param			= stex_biosparam,
1484 	.queuecommand			= stex_queuecommand,
1485 	.slave_configure		= stex_slave_config,
1486 	.eh_abort_handler		= stex_abort,
1487 	.eh_host_reset_handler		= stex_reset,
1488 	.this_id			= -1,
1489 	.dma_boundary			= PAGE_SIZE - 1,
1490 };
1491 
1492 static struct pci_device_id stex_pci_tbl[] = {
1493 	/* st_shasta */
1494 	{ 0x105a, 0x8350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1495 		st_shasta }, /* SuperTrak EX8350/8300/16350/16300 */
1496 	{ 0x105a, 0xc350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1497 		st_shasta }, /* SuperTrak EX12350 */
1498 	{ 0x105a, 0x4302, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1499 		st_shasta }, /* SuperTrak EX4350 */
1500 	{ 0x105a, 0xe350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1501 		st_shasta }, /* SuperTrak EX24350 */
1502 
1503 	/* st_vsc */
1504 	{ 0x105a, 0x7250, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_vsc },
1505 
1506 	/* st_yosemite */
1507 	{ 0x105a, 0x8650, 0x105a, PCI_ANY_ID, 0, 0, st_yosemite },
1508 
1509 	/* st_seq */
1510 	{ 0x105a, 0x3360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_seq },
1511 
1512 	/* st_yel */
1513 	{ 0x105a, 0x8650, 0x1033, PCI_ANY_ID, 0, 0, st_yel },
1514 	{ 0x105a, 0x8760, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_yel },
1515 
1516 	/* st_P3, pluto */
1517 	{ PCI_VENDOR_ID_PROMISE, 0x8870, PCI_VENDOR_ID_PROMISE,
1518 		0x8870, 0, 0, st_P3 },
1519 	/* st_P3, p3 */
1520 	{ PCI_VENDOR_ID_PROMISE, 0x8870, PCI_VENDOR_ID_PROMISE,
1521 		0x4300, 0, 0, st_P3 },
1522 
1523 	/* st_P3, SymplyStor4E */
1524 	{ PCI_VENDOR_ID_PROMISE, 0x8871, PCI_VENDOR_ID_PROMISE,
1525 		0x4311, 0, 0, st_P3 },
1526 	/* st_P3, SymplyStor8E */
1527 	{ PCI_VENDOR_ID_PROMISE, 0x8871, PCI_VENDOR_ID_PROMISE,
1528 		0x4312, 0, 0, st_P3 },
1529 	/* st_P3, SymplyStor4 */
1530 	{ PCI_VENDOR_ID_PROMISE, 0x8871, PCI_VENDOR_ID_PROMISE,
1531 		0x4321, 0, 0, st_P3 },
1532 	/* st_P3, SymplyStor8 */
1533 	{ PCI_VENDOR_ID_PROMISE, 0x8871, PCI_VENDOR_ID_PROMISE,
1534 		0x4322, 0, 0, st_P3 },
1535 	{ }	/* terminate list */
1536 };
1537 
1538 static struct st_card_info stex_card_info[] = {
1539 	/* st_shasta */
1540 	{
1541 		.max_id		= 17,
1542 		.max_lun	= 8,
1543 		.max_channel	= 0,
1544 		.rq_count	= 32,
1545 		.rq_size	= 1048,
1546 		.sts_count	= 32,
1547 		.alloc_rq	= stex_alloc_req,
1548 		.map_sg		= stex_map_sg,
1549 		.send		= stex_send_cmd,
1550 	},
1551 
1552 	/* st_vsc */
1553 	{
1554 		.max_id		= 129,
1555 		.max_lun	= 1,
1556 		.max_channel	= 0,
1557 		.rq_count	= 32,
1558 		.rq_size	= 1048,
1559 		.sts_count	= 32,
1560 		.alloc_rq	= stex_alloc_req,
1561 		.map_sg		= stex_map_sg,
1562 		.send		= stex_send_cmd,
1563 	},
1564 
1565 	/* st_yosemite */
1566 	{
1567 		.max_id		= 2,
1568 		.max_lun	= 256,
1569 		.max_channel	= 0,
1570 		.rq_count	= 256,
1571 		.rq_size	= 1048,
1572 		.sts_count	= 256,
1573 		.alloc_rq	= stex_alloc_req,
1574 		.map_sg		= stex_map_sg,
1575 		.send		= stex_send_cmd,
1576 	},
1577 
1578 	/* st_seq */
1579 	{
1580 		.max_id		= 129,
1581 		.max_lun	= 1,
1582 		.max_channel	= 0,
1583 		.rq_count	= 32,
1584 		.rq_size	= 1048,
1585 		.sts_count	= 32,
1586 		.alloc_rq	= stex_alloc_req,
1587 		.map_sg		= stex_map_sg,
1588 		.send		= stex_send_cmd,
1589 	},
1590 
1591 	/* st_yel */
1592 	{
1593 		.max_id		= 129,
1594 		.max_lun	= 256,
1595 		.max_channel	= 3,
1596 		.rq_count	= 801,
1597 		.rq_size	= 512,
1598 		.sts_count	= 801,
1599 		.alloc_rq	= stex_ss_alloc_req,
1600 		.map_sg		= stex_ss_map_sg,
1601 		.send		= stex_ss_send_cmd,
1602 	},
1603 
1604 	/* st_P3 */
1605 	{
1606 		.max_id		= 129,
1607 		.max_lun	= 256,
1608 		.max_channel	= 0,
1609 		.rq_count	= 801,
1610 		.rq_size	= 512,
1611 		.sts_count	= 801,
1612 		.alloc_rq	= stex_ss_alloc_req,
1613 		.map_sg		= stex_ss_map_sg,
1614 		.send		= stex_ss_send_cmd,
1615 	},
1616 };
1617 
stex_request_irq(struct st_hba * hba)1618 static int stex_request_irq(struct st_hba *hba)
1619 {
1620 	struct pci_dev *pdev = hba->pdev;
1621 	int status;
1622 
1623 	if (msi || hba->cardtype == st_P3) {
1624 		status = pci_enable_msi(pdev);
1625 		if (status != 0)
1626 			printk(KERN_ERR DRV_NAME
1627 				"(%s): error %d setting up MSI\n",
1628 				pci_name(pdev), status);
1629 		else
1630 			hba->msi_enabled = 1;
1631 	} else
1632 		hba->msi_enabled = 0;
1633 
1634 	status = request_irq(pdev->irq,
1635 		(hba->cardtype == st_yel || hba->cardtype == st_P3) ?
1636 		stex_ss_intr : stex_intr, IRQF_SHARED, DRV_NAME, hba);
1637 
1638 	if (status != 0) {
1639 		if (hba->msi_enabled)
1640 			pci_disable_msi(pdev);
1641 	}
1642 	return status;
1643 }
1644 
stex_free_irq(struct st_hba * hba)1645 static void stex_free_irq(struct st_hba *hba)
1646 {
1647 	struct pci_dev *pdev = hba->pdev;
1648 
1649 	free_irq(pdev->irq, hba);
1650 	if (hba->msi_enabled)
1651 		pci_disable_msi(pdev);
1652 }
1653 
stex_probe(struct pci_dev * pdev,const struct pci_device_id * id)1654 static int stex_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1655 {
1656 	struct st_hba *hba;
1657 	struct Scsi_Host *host;
1658 	const struct st_card_info *ci = NULL;
1659 	u32 sts_offset, cp_offset, scratch_offset;
1660 	int err;
1661 
1662 	err = pci_enable_device(pdev);
1663 	if (err)
1664 		return err;
1665 
1666 	pci_set_master(pdev);
1667 
1668 	S6flag = 0;
1669 	register_reboot_notifier(&stex_notifier);
1670 
1671 	host = scsi_host_alloc(&driver_template, sizeof(struct st_hba));
1672 
1673 	if (!host) {
1674 		printk(KERN_ERR DRV_NAME "(%s): scsi_host_alloc failed\n",
1675 			pci_name(pdev));
1676 		err = -ENOMEM;
1677 		goto out_disable;
1678 	}
1679 
1680 	hba = (struct st_hba *)host->hostdata;
1681 	memset(hba, 0, sizeof(struct st_hba));
1682 
1683 	err = pci_request_regions(pdev, DRV_NAME);
1684 	if (err < 0) {
1685 		printk(KERN_ERR DRV_NAME "(%s): request regions failed\n",
1686 			pci_name(pdev));
1687 		goto out_scsi_host_put;
1688 	}
1689 
1690 	hba->mmio_base = pci_ioremap_bar(pdev, 0);
1691 	if ( !hba->mmio_base) {
1692 		printk(KERN_ERR DRV_NAME "(%s): memory map failed\n",
1693 			pci_name(pdev));
1694 		err = -ENOMEM;
1695 		goto out_release_regions;
1696 	}
1697 
1698 	err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
1699 	if (err)
1700 		err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
1701 	if (err) {
1702 		printk(KERN_ERR DRV_NAME "(%s): set dma mask failed\n",
1703 			pci_name(pdev));
1704 		goto out_iounmap;
1705 	}
1706 
1707 	hba->cardtype = (unsigned int) id->driver_data;
1708 	ci = &stex_card_info[hba->cardtype];
1709 	switch (id->subdevice) {
1710 	case 0x4221:
1711 	case 0x4222:
1712 	case 0x4223:
1713 	case 0x4224:
1714 	case 0x4225:
1715 	case 0x4226:
1716 	case 0x4227:
1717 	case 0x4261:
1718 	case 0x4262:
1719 	case 0x4263:
1720 	case 0x4264:
1721 	case 0x4265:
1722 		break;
1723 	default:
1724 		if (hba->cardtype == st_yel || hba->cardtype == st_P3)
1725 			hba->supports_pm = 1;
1726 	}
1727 
1728 	sts_offset = scratch_offset = (ci->rq_count+1) * ci->rq_size;
1729 	if (hba->cardtype == st_yel || hba->cardtype == st_P3)
1730 		sts_offset += (ci->sts_count+1) * sizeof(u32);
1731 	cp_offset = sts_offset + (ci->sts_count+1) * sizeof(struct status_msg);
1732 	hba->dma_size = cp_offset + sizeof(struct st_frame);
1733 	if (hba->cardtype == st_seq ||
1734 		(hba->cardtype == st_vsc && (pdev->subsystem_device & 1))) {
1735 		hba->extra_offset = hba->dma_size;
1736 		hba->dma_size += ST_ADDITIONAL_MEM;
1737 	}
1738 	hba->dma_mem = dma_alloc_coherent(&pdev->dev,
1739 		hba->dma_size, &hba->dma_handle, GFP_KERNEL);
1740 	if (!hba->dma_mem) {
1741 		/* Retry minimum coherent mapping for st_seq and st_vsc */
1742 		if (hba->cardtype == st_seq ||
1743 		    (hba->cardtype == st_vsc && (pdev->subsystem_device & 1))) {
1744 			printk(KERN_WARNING DRV_NAME
1745 				"(%s): allocating min buffer for controller\n",
1746 				pci_name(pdev));
1747 			hba->dma_size = hba->extra_offset
1748 				+ ST_ADDITIONAL_MEM_MIN;
1749 			hba->dma_mem = dma_alloc_coherent(&pdev->dev,
1750 				hba->dma_size, &hba->dma_handle, GFP_KERNEL);
1751 		}
1752 
1753 		if (!hba->dma_mem) {
1754 			err = -ENOMEM;
1755 			printk(KERN_ERR DRV_NAME "(%s): dma mem alloc failed\n",
1756 				pci_name(pdev));
1757 			goto out_iounmap;
1758 		}
1759 	}
1760 
1761 	hba->ccb = kcalloc(ci->rq_count, sizeof(struct st_ccb), GFP_KERNEL);
1762 	if (!hba->ccb) {
1763 		err = -ENOMEM;
1764 		printk(KERN_ERR DRV_NAME "(%s): ccb alloc failed\n",
1765 			pci_name(pdev));
1766 		goto out_pci_free;
1767 	}
1768 
1769 	if (hba->cardtype == st_yel || hba->cardtype == st_P3)
1770 		hba->scratch = (__le32 *)(hba->dma_mem + scratch_offset);
1771 	hba->status_buffer = (struct status_msg *)(hba->dma_mem + sts_offset);
1772 	hba->copy_buffer = hba->dma_mem + cp_offset;
1773 	hba->rq_count = ci->rq_count;
1774 	hba->rq_size = ci->rq_size;
1775 	hba->sts_count = ci->sts_count;
1776 	hba->alloc_rq = ci->alloc_rq;
1777 	hba->map_sg = ci->map_sg;
1778 	hba->send = ci->send;
1779 	hba->mu_status = MU_STATE_STARTING;
1780 	hba->msi_lock = 0;
1781 
1782 	if (hba->cardtype == st_yel || hba->cardtype == st_P3)
1783 		host->sg_tablesize = 38;
1784 	else
1785 		host->sg_tablesize = 32;
1786 	host->can_queue = ci->rq_count;
1787 	host->cmd_per_lun = ci->rq_count;
1788 	host->max_id = ci->max_id;
1789 	host->max_lun = ci->max_lun;
1790 	host->max_channel = ci->max_channel;
1791 	host->unique_id = host->host_no;
1792 	host->max_cmd_len = STEX_CDB_LENGTH;
1793 
1794 	hba->host = host;
1795 	hba->pdev = pdev;
1796 	init_waitqueue_head(&hba->reset_waitq);
1797 
1798 	snprintf(hba->work_q_name, sizeof(hba->work_q_name),
1799 		 "stex_wq_%d", host->host_no);
1800 	hba->work_q = create_singlethread_workqueue(hba->work_q_name);
1801 	if (!hba->work_q) {
1802 		printk(KERN_ERR DRV_NAME "(%s): create workqueue failed\n",
1803 			pci_name(pdev));
1804 		err = -ENOMEM;
1805 		goto out_ccb_free;
1806 	}
1807 	INIT_WORK(&hba->reset_work, stex_reset_work);
1808 
1809 	err = stex_request_irq(hba);
1810 	if (err) {
1811 		printk(KERN_ERR DRV_NAME "(%s): request irq failed\n",
1812 			pci_name(pdev));
1813 		goto out_free_wq;
1814 	}
1815 
1816 	err = stex_handshake(hba);
1817 	if (err)
1818 		goto out_free_irq;
1819 
1820 	pci_set_drvdata(pdev, hba);
1821 
1822 	err = scsi_add_host(host, &pdev->dev);
1823 	if (err) {
1824 		printk(KERN_ERR DRV_NAME "(%s): scsi_add_host failed\n",
1825 			pci_name(pdev));
1826 		goto out_free_irq;
1827 	}
1828 
1829 	scsi_scan_host(host);
1830 
1831 	return 0;
1832 
1833 out_free_irq:
1834 	stex_free_irq(hba);
1835 out_free_wq:
1836 	destroy_workqueue(hba->work_q);
1837 out_ccb_free:
1838 	kfree(hba->ccb);
1839 out_pci_free:
1840 	dma_free_coherent(&pdev->dev, hba->dma_size,
1841 			  hba->dma_mem, hba->dma_handle);
1842 out_iounmap:
1843 	iounmap(hba->mmio_base);
1844 out_release_regions:
1845 	pci_release_regions(pdev);
1846 out_scsi_host_put:
1847 	scsi_host_put(host);
1848 out_disable:
1849 	pci_disable_device(pdev);
1850 
1851 	return err;
1852 }
1853 
stex_hba_stop(struct st_hba * hba,int st_sleep_mic)1854 static void stex_hba_stop(struct st_hba *hba, int st_sleep_mic)
1855 {
1856 	struct req_msg *req;
1857 	struct st_msg_header *msg_h;
1858 	unsigned long flags;
1859 	unsigned long before;
1860 	u16 tag = 0;
1861 
1862 	spin_lock_irqsave(hba->host->host_lock, flags);
1863 
1864 	if ((hba->cardtype == st_yel || hba->cardtype == st_P3) &&
1865 		hba->supports_pm == 1) {
1866 		if (st_sleep_mic == ST_NOTHANDLED) {
1867 			spin_unlock_irqrestore(hba->host->host_lock, flags);
1868 			return;
1869 		}
1870 	}
1871 	req = hba->alloc_rq(hba);
1872 	if (hba->cardtype == st_yel || hba->cardtype == st_P3) {
1873 		msg_h = (struct st_msg_header *)req - 1;
1874 		memset(msg_h, 0, hba->rq_size);
1875 	} else
1876 		memset(req, 0, hba->rq_size);
1877 
1878 	if ((hba->cardtype == st_yosemite || hba->cardtype == st_yel
1879 		|| hba->cardtype == st_P3)
1880 		&& st_sleep_mic == ST_IGNORED) {
1881 		req->cdb[0] = MGT_CMD;
1882 		req->cdb[1] = MGT_CMD_SIGNATURE;
1883 		req->cdb[2] = CTLR_CONFIG_CMD;
1884 		req->cdb[3] = CTLR_SHUTDOWN;
1885 	} else if ((hba->cardtype == st_yel || hba->cardtype == st_P3)
1886 		&& st_sleep_mic != ST_IGNORED) {
1887 		req->cdb[0] = MGT_CMD;
1888 		req->cdb[1] = MGT_CMD_SIGNATURE;
1889 		req->cdb[2] = CTLR_CONFIG_CMD;
1890 		req->cdb[3] = PMIC_SHUTDOWN;
1891 		req->cdb[4] = st_sleep_mic;
1892 	} else {
1893 		req->cdb[0] = CONTROLLER_CMD;
1894 		req->cdb[1] = CTLR_POWER_STATE_CHANGE;
1895 		req->cdb[2] = CTLR_POWER_SAVING;
1896 	}
1897 	hba->ccb[tag].cmd = NULL;
1898 	hba->ccb[tag].sg_count = 0;
1899 	hba->ccb[tag].sense_bufflen = 0;
1900 	hba->ccb[tag].sense_buffer = NULL;
1901 	hba->ccb[tag].req_type = PASSTHRU_REQ_TYPE;
1902 	hba->send(hba, req, tag);
1903 	spin_unlock_irqrestore(hba->host->host_lock, flags);
1904 	before = jiffies;
1905 	while (hba->ccb[tag].req_type & PASSTHRU_REQ_TYPE) {
1906 		if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
1907 			hba->ccb[tag].req_type = 0;
1908 			hba->mu_status = MU_STATE_STOP;
1909 			return;
1910 		}
1911 		msleep(1);
1912 	}
1913 	hba->mu_status = MU_STATE_STOP;
1914 }
1915 
stex_hba_free(struct st_hba * hba)1916 static void stex_hba_free(struct st_hba *hba)
1917 {
1918 	stex_free_irq(hba);
1919 
1920 	destroy_workqueue(hba->work_q);
1921 
1922 	iounmap(hba->mmio_base);
1923 
1924 	pci_release_regions(hba->pdev);
1925 
1926 	kfree(hba->ccb);
1927 
1928 	dma_free_coherent(&hba->pdev->dev, hba->dma_size,
1929 			  hba->dma_mem, hba->dma_handle);
1930 }
1931 
stex_remove(struct pci_dev * pdev)1932 static void stex_remove(struct pci_dev *pdev)
1933 {
1934 	struct st_hba *hba = pci_get_drvdata(pdev);
1935 
1936 	hba->mu_status = MU_STATE_NOCONNECT;
1937 	return_abnormal_state(hba, DID_NO_CONNECT);
1938 	scsi_remove_host(hba->host);
1939 
1940 	scsi_block_requests(hba->host);
1941 
1942 	stex_hba_free(hba);
1943 
1944 	scsi_host_put(hba->host);
1945 
1946 	pci_disable_device(pdev);
1947 
1948 	unregister_reboot_notifier(&stex_notifier);
1949 }
1950 
stex_shutdown(struct pci_dev * pdev)1951 static void stex_shutdown(struct pci_dev *pdev)
1952 {
1953 	struct st_hba *hba = pci_get_drvdata(pdev);
1954 
1955 	if (hba->supports_pm == 0) {
1956 		stex_hba_stop(hba, ST_IGNORED);
1957 	} else if (hba->supports_pm == 1 && S6flag) {
1958 		unregister_reboot_notifier(&stex_notifier);
1959 		stex_hba_stop(hba, ST_S6);
1960 	} else
1961 		stex_hba_stop(hba, ST_S5);
1962 }
1963 
stex_choice_sleep_mic(struct st_hba * hba,pm_message_t state)1964 static int stex_choice_sleep_mic(struct st_hba *hba, pm_message_t state)
1965 {
1966 	switch (state.event) {
1967 	case PM_EVENT_SUSPEND:
1968 		return ST_S3;
1969 	case PM_EVENT_HIBERNATE:
1970 		hba->msi_lock = 0;
1971 		return ST_S4;
1972 	default:
1973 		return ST_NOTHANDLED;
1974 	}
1975 }
1976 
stex_suspend(struct pci_dev * pdev,pm_message_t state)1977 static int stex_suspend(struct pci_dev *pdev, pm_message_t state)
1978 {
1979 	struct st_hba *hba = pci_get_drvdata(pdev);
1980 
1981 	if ((hba->cardtype == st_yel || hba->cardtype == st_P3)
1982 		&& hba->supports_pm == 1)
1983 		stex_hba_stop(hba, stex_choice_sleep_mic(hba, state));
1984 	else
1985 		stex_hba_stop(hba, ST_IGNORED);
1986 	return 0;
1987 }
1988 
stex_resume(struct pci_dev * pdev)1989 static int stex_resume(struct pci_dev *pdev)
1990 {
1991 	struct st_hba *hba = pci_get_drvdata(pdev);
1992 
1993 	hba->mu_status = MU_STATE_STARTING;
1994 	stex_handshake(hba);
1995 	return 0;
1996 }
1997 
stex_halt(struct notifier_block * nb,unsigned long event,void * buf)1998 static int stex_halt(struct notifier_block *nb, unsigned long event, void *buf)
1999 {
2000 	S6flag = 1;
2001 	return NOTIFY_OK;
2002 }
2003 MODULE_DEVICE_TABLE(pci, stex_pci_tbl);
2004 
2005 static struct pci_driver stex_pci_driver = {
2006 	.name		= DRV_NAME,
2007 	.id_table	= stex_pci_tbl,
2008 	.probe		= stex_probe,
2009 	.remove		= stex_remove,
2010 	.shutdown	= stex_shutdown,
2011 	.suspend	= stex_suspend,
2012 	.resume		= stex_resume,
2013 };
2014 
stex_init(void)2015 static int __init stex_init(void)
2016 {
2017 	printk(KERN_INFO DRV_NAME
2018 		": Promise SuperTrak EX Driver version: %s\n",
2019 		 ST_DRIVER_VERSION);
2020 
2021 	return pci_register_driver(&stex_pci_driver);
2022 }
2023 
stex_exit(void)2024 static void __exit stex_exit(void)
2025 {
2026 	pci_unregister_driver(&stex_pci_driver);
2027 }
2028 
2029 module_init(stex_init);
2030 module_exit(stex_exit);
2031