1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Driver for STMicroelectronics Multi-Function eXpander (STMFX) GPIO expander
4  *
5  * Copyright (C) 2019 STMicroelectronics
6  * Author(s): Amelie Delaunay <amelie.delaunay@st.com>.
7  */
8 #include <linux/gpio/driver.h>
9 #include <linux/interrupt.h>
10 #include <linux/mfd/stmfx.h>
11 #include <linux/module.h>
12 #include <linux/platform_device.h>
13 #include <linux/seq_file.h>
14 
15 #include <linux/pinctrl/pinconf.h>
16 #include <linux/pinctrl/pinmux.h>
17 
18 #include "core.h"
19 #include "pinctrl-utils.h"
20 
21 /* GPIOs expander */
22 /* GPIO_STATE1 0x10, GPIO_STATE2 0x11, GPIO_STATE3 0x12 */
23 #define STMFX_REG_GPIO_STATE		STMFX_REG_GPIO_STATE1 /* R */
24 /* GPIO_DIR1 0x60, GPIO_DIR2 0x61, GPIO_DIR3 0x63 */
25 #define STMFX_REG_GPIO_DIR		STMFX_REG_GPIO_DIR1 /* RW */
26 /* GPIO_TYPE1 0x64, GPIO_TYPE2 0x65, GPIO_TYPE3 0x66 */
27 #define STMFX_REG_GPIO_TYPE		STMFX_REG_GPIO_TYPE1 /* RW */
28 /* GPIO_PUPD1 0x68, GPIO_PUPD2 0x69, GPIO_PUPD3 0x6A */
29 #define STMFX_REG_GPIO_PUPD		STMFX_REG_GPIO_PUPD1 /* RW */
30 /* GPO_SET1 0x6C, GPO_SET2 0x6D, GPO_SET3 0x6E */
31 #define STMFX_REG_GPO_SET		STMFX_REG_GPO_SET1 /* RW */
32 /* GPO_CLR1 0x70, GPO_CLR2 0x71, GPO_CLR3 0x72 */
33 #define STMFX_REG_GPO_CLR		STMFX_REG_GPO_CLR1 /* RW */
34 /* IRQ_GPI_SRC1 0x48, IRQ_GPI_SRC2 0x49, IRQ_GPI_SRC3 0x4A */
35 #define STMFX_REG_IRQ_GPI_SRC		STMFX_REG_IRQ_GPI_SRC1 /* RW */
36 /* IRQ_GPI_EVT1 0x4C, IRQ_GPI_EVT2 0x4D, IRQ_GPI_EVT3 0x4E */
37 #define STMFX_REG_IRQ_GPI_EVT		STMFX_REG_IRQ_GPI_EVT1 /* RW */
38 /* IRQ_GPI_TYPE1 0x50, IRQ_GPI_TYPE2 0x51, IRQ_GPI_TYPE3 0x52 */
39 #define STMFX_REG_IRQ_GPI_TYPE		STMFX_REG_IRQ_GPI_TYPE1 /* RW */
40 /* IRQ_GPI_PENDING1 0x0C, IRQ_GPI_PENDING2 0x0D, IRQ_GPI_PENDING3 0x0E*/
41 #define STMFX_REG_IRQ_GPI_PENDING	STMFX_REG_IRQ_GPI_PENDING1 /* R */
42 /* IRQ_GPI_ACK1 0x54, IRQ_GPI_ACK2 0x55, IRQ_GPI_ACK3 0x56 */
43 #define STMFX_REG_IRQ_GPI_ACK		STMFX_REG_IRQ_GPI_ACK1 /* RW */
44 
45 #define NR_GPIO_REGS			3
46 #define NR_GPIOS_PER_REG		8
47 #define get_reg(offset)			((offset) / NR_GPIOS_PER_REG)
48 #define get_shift(offset)		((offset) % NR_GPIOS_PER_REG)
49 #define get_mask(offset)		(BIT(get_shift(offset)))
50 
51 /*
52  * STMFX pinctrl can have up to 24 pins if STMFX other functions are not used.
53  * Pins availability is managed thanks to gpio-ranges property.
54  */
55 static const struct pinctrl_pin_desc stmfx_pins[] = {
56 	PINCTRL_PIN(0, "gpio0"),
57 	PINCTRL_PIN(1, "gpio1"),
58 	PINCTRL_PIN(2, "gpio2"),
59 	PINCTRL_PIN(3, "gpio3"),
60 	PINCTRL_PIN(4, "gpio4"),
61 	PINCTRL_PIN(5, "gpio5"),
62 	PINCTRL_PIN(6, "gpio6"),
63 	PINCTRL_PIN(7, "gpio7"),
64 	PINCTRL_PIN(8, "gpio8"),
65 	PINCTRL_PIN(9, "gpio9"),
66 	PINCTRL_PIN(10, "gpio10"),
67 	PINCTRL_PIN(11, "gpio11"),
68 	PINCTRL_PIN(12, "gpio12"),
69 	PINCTRL_PIN(13, "gpio13"),
70 	PINCTRL_PIN(14, "gpio14"),
71 	PINCTRL_PIN(15, "gpio15"),
72 	PINCTRL_PIN(16, "agpio0"),
73 	PINCTRL_PIN(17, "agpio1"),
74 	PINCTRL_PIN(18, "agpio2"),
75 	PINCTRL_PIN(19, "agpio3"),
76 	PINCTRL_PIN(20, "agpio4"),
77 	PINCTRL_PIN(21, "agpio5"),
78 	PINCTRL_PIN(22, "agpio6"),
79 	PINCTRL_PIN(23, "agpio7"),
80 };
81 
82 struct stmfx_pinctrl {
83 	struct device *dev;
84 	struct stmfx *stmfx;
85 	struct pinctrl_dev *pctl_dev;
86 	struct pinctrl_desc pctl_desc;
87 	struct gpio_chip gpio_chip;
88 	struct mutex lock; /* IRQ bus lock */
89 	unsigned long gpio_valid_mask;
90 	/* Cache of IRQ_GPI_* registers for bus_lock */
91 	u8 irq_gpi_src[NR_GPIO_REGS];
92 	u8 irq_gpi_type[NR_GPIO_REGS];
93 	u8 irq_gpi_evt[NR_GPIO_REGS];
94 	u8 irq_toggle_edge[NR_GPIO_REGS];
95 #ifdef CONFIG_PM
96 	/* Backup of GPIO_* registers for suspend/resume */
97 	u8 bkp_gpio_state[NR_GPIO_REGS];
98 	u8 bkp_gpio_dir[NR_GPIO_REGS];
99 	u8 bkp_gpio_type[NR_GPIO_REGS];
100 	u8 bkp_gpio_pupd[NR_GPIO_REGS];
101 #endif
102 };
103 
stmfx_gpio_get(struct gpio_chip * gc,unsigned int offset)104 static int stmfx_gpio_get(struct gpio_chip *gc, unsigned int offset)
105 {
106 	struct stmfx_pinctrl *pctl = gpiochip_get_data(gc);
107 	u32 reg = STMFX_REG_GPIO_STATE + get_reg(offset);
108 	u32 mask = get_mask(offset);
109 	u32 value;
110 	int ret;
111 
112 	ret = regmap_read(pctl->stmfx->map, reg, &value);
113 
114 	return ret ? ret : !!(value & mask);
115 }
116 
stmfx_gpio_set(struct gpio_chip * gc,unsigned int offset,int value)117 static void stmfx_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
118 {
119 	struct stmfx_pinctrl *pctl = gpiochip_get_data(gc);
120 	u32 reg = value ? STMFX_REG_GPO_SET : STMFX_REG_GPO_CLR;
121 	u32 mask = get_mask(offset);
122 
123 	regmap_write_bits(pctl->stmfx->map, reg + get_reg(offset),
124 			  mask, mask);
125 }
126 
stmfx_gpio_get_direction(struct gpio_chip * gc,unsigned int offset)127 static int stmfx_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
128 {
129 	struct stmfx_pinctrl *pctl = gpiochip_get_data(gc);
130 	u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset);
131 	u32 mask = get_mask(offset);
132 	u32 val;
133 	int ret;
134 
135 	ret = regmap_read(pctl->stmfx->map, reg, &val);
136 	/*
137 	 * On stmfx, gpio pins direction is (0)input, (1)output.
138 	 */
139 	if (ret)
140 		return ret;
141 
142 	if (val & mask)
143 		return GPIO_LINE_DIRECTION_OUT;
144 
145 	return GPIO_LINE_DIRECTION_IN;
146 }
147 
stmfx_gpio_direction_input(struct gpio_chip * gc,unsigned int offset)148 static int stmfx_gpio_direction_input(struct gpio_chip *gc, unsigned int offset)
149 {
150 	struct stmfx_pinctrl *pctl = gpiochip_get_data(gc);
151 	u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset);
152 	u32 mask = get_mask(offset);
153 
154 	return regmap_write_bits(pctl->stmfx->map, reg, mask, 0);
155 }
156 
stmfx_gpio_direction_output(struct gpio_chip * gc,unsigned int offset,int value)157 static int stmfx_gpio_direction_output(struct gpio_chip *gc,
158 				       unsigned int offset, int value)
159 {
160 	struct stmfx_pinctrl *pctl = gpiochip_get_data(gc);
161 	u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset);
162 	u32 mask = get_mask(offset);
163 
164 	stmfx_gpio_set(gc, offset, value);
165 
166 	return regmap_write_bits(pctl->stmfx->map, reg, mask, mask);
167 }
168 
stmfx_pinconf_get_pupd(struct stmfx_pinctrl * pctl,unsigned int offset)169 static int stmfx_pinconf_get_pupd(struct stmfx_pinctrl *pctl,
170 				  unsigned int offset)
171 {
172 	u32 reg = STMFX_REG_GPIO_PUPD + get_reg(offset);
173 	u32 pupd, mask = get_mask(offset);
174 	int ret;
175 
176 	ret = regmap_read(pctl->stmfx->map, reg, &pupd);
177 	if (ret)
178 		return ret;
179 
180 	return !!(pupd & mask);
181 }
182 
stmfx_pinconf_set_pupd(struct stmfx_pinctrl * pctl,unsigned int offset,u32 pupd)183 static int stmfx_pinconf_set_pupd(struct stmfx_pinctrl *pctl,
184 				  unsigned int offset, u32 pupd)
185 {
186 	u32 reg = STMFX_REG_GPIO_PUPD + get_reg(offset);
187 	u32 mask = get_mask(offset);
188 
189 	return regmap_write_bits(pctl->stmfx->map, reg, mask, pupd ? mask : 0);
190 }
191 
stmfx_pinconf_get_type(struct stmfx_pinctrl * pctl,unsigned int offset)192 static int stmfx_pinconf_get_type(struct stmfx_pinctrl *pctl,
193 				  unsigned int offset)
194 {
195 	u32 reg = STMFX_REG_GPIO_TYPE + get_reg(offset);
196 	u32 type, mask = get_mask(offset);
197 	int ret;
198 
199 	ret = regmap_read(pctl->stmfx->map, reg, &type);
200 	if (ret)
201 		return ret;
202 
203 	return !!(type & mask);
204 }
205 
stmfx_pinconf_set_type(struct stmfx_pinctrl * pctl,unsigned int offset,u32 type)206 static int stmfx_pinconf_set_type(struct stmfx_pinctrl *pctl,
207 				  unsigned int offset, u32 type)
208 {
209 	u32 reg = STMFX_REG_GPIO_TYPE + get_reg(offset);
210 	u32 mask = get_mask(offset);
211 
212 	return regmap_write_bits(pctl->stmfx->map, reg, mask, type ? mask : 0);
213 }
214 
stmfx_pinconf_get(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * config)215 static int stmfx_pinconf_get(struct pinctrl_dev *pctldev,
216 			     unsigned int pin, unsigned long *config)
217 {
218 	struct stmfx_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
219 	u32 param = pinconf_to_config_param(*config);
220 	struct pinctrl_gpio_range *range;
221 	u32 arg = 0;
222 	int ret, dir, type, pupd;
223 
224 	range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
225 	if (!range)
226 		return -EINVAL;
227 
228 	dir = stmfx_gpio_get_direction(&pctl->gpio_chip, pin);
229 	if (dir < 0)
230 		return dir;
231 
232 	/*
233 	 * Currently the gpiolib IN is 1 and OUT is 0 but let's not count
234 	 * on it just to be on the safe side also in the future :)
235 	 */
236 	dir = (dir == GPIO_LINE_DIRECTION_IN) ? 1 : 0;
237 
238 	type = stmfx_pinconf_get_type(pctl, pin);
239 	if (type < 0)
240 		return type;
241 	pupd = stmfx_pinconf_get_pupd(pctl, pin);
242 	if (pupd < 0)
243 		return pupd;
244 
245 	switch (param) {
246 	case PIN_CONFIG_BIAS_DISABLE:
247 		if ((!dir && (!type || !pupd)) || (dir && !type))
248 			arg = 1;
249 		break;
250 	case PIN_CONFIG_BIAS_PULL_DOWN:
251 		if (dir && type && !pupd)
252 			arg = 1;
253 		break;
254 	case PIN_CONFIG_BIAS_PULL_UP:
255 		if (type && pupd)
256 			arg = 1;
257 		break;
258 	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
259 		if ((!dir && type) || (dir && !type))
260 			arg = 1;
261 		break;
262 	case PIN_CONFIG_DRIVE_PUSH_PULL:
263 		if ((!dir && !type) || (dir && type))
264 			arg = 1;
265 		break;
266 	case PIN_CONFIG_OUTPUT:
267 		if (dir)
268 			return -EINVAL;
269 
270 		ret = stmfx_gpio_get(&pctl->gpio_chip, pin);
271 		if (ret < 0)
272 			return ret;
273 
274 		arg = ret;
275 		break;
276 	default:
277 		return -ENOTSUPP;
278 	}
279 
280 	*config = pinconf_to_config_packed(param, arg);
281 
282 	return 0;
283 }
284 
stmfx_pinconf_set(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * configs,unsigned int num_configs)285 static int stmfx_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
286 			     unsigned long *configs, unsigned int num_configs)
287 {
288 	struct stmfx_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
289 	struct pinctrl_gpio_range *range;
290 	enum pin_config_param param;
291 	u32 arg;
292 	int i, ret;
293 
294 	range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
295 	if (!range) {
296 		dev_err(pctldev->dev, "pin %d is not available\n", pin);
297 		return -EINVAL;
298 	}
299 
300 	for (i = 0; i < num_configs; i++) {
301 		param = pinconf_to_config_param(configs[i]);
302 		arg = pinconf_to_config_argument(configs[i]);
303 
304 		switch (param) {
305 		case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
306 		case PIN_CONFIG_BIAS_DISABLE:
307 		case PIN_CONFIG_DRIVE_PUSH_PULL:
308 			ret = stmfx_pinconf_set_type(pctl, pin, 0);
309 			if (ret)
310 				return ret;
311 			break;
312 		case PIN_CONFIG_BIAS_PULL_DOWN:
313 			ret = stmfx_pinconf_set_type(pctl, pin, 1);
314 			if (ret)
315 				return ret;
316 			ret = stmfx_pinconf_set_pupd(pctl, pin, 0);
317 			if (ret)
318 				return ret;
319 			break;
320 		case PIN_CONFIG_BIAS_PULL_UP:
321 			ret = stmfx_pinconf_set_type(pctl, pin, 1);
322 			if (ret)
323 				return ret;
324 			ret = stmfx_pinconf_set_pupd(pctl, pin, 1);
325 			if (ret)
326 				return ret;
327 			break;
328 		case PIN_CONFIG_DRIVE_OPEN_DRAIN:
329 			ret = stmfx_pinconf_set_type(pctl, pin, 1);
330 			if (ret)
331 				return ret;
332 			break;
333 		case PIN_CONFIG_OUTPUT:
334 			ret = stmfx_gpio_direction_output(&pctl->gpio_chip,
335 							  pin, arg);
336 			if (ret)
337 				return ret;
338 			break;
339 		default:
340 			return -ENOTSUPP;
341 		}
342 	}
343 
344 	return 0;
345 }
346 
stmfx_pinconf_dbg_show(struct pinctrl_dev * pctldev,struct seq_file * s,unsigned int offset)347 static void stmfx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
348 				   struct seq_file *s, unsigned int offset)
349 {
350 	struct stmfx_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
351 	struct pinctrl_gpio_range *range;
352 	int dir, type, pupd, val;
353 
354 	range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, offset);
355 	if (!range)
356 		return;
357 
358 	dir = stmfx_gpio_get_direction(&pctl->gpio_chip, offset);
359 	if (dir < 0)
360 		return;
361 	type = stmfx_pinconf_get_type(pctl, offset);
362 	if (type < 0)
363 		return;
364 	pupd = stmfx_pinconf_get_pupd(pctl, offset);
365 	if (pupd < 0)
366 		return;
367 	val = stmfx_gpio_get(&pctl->gpio_chip, offset);
368 	if (val < 0)
369 		return;
370 
371 	if (dir == GPIO_LINE_DIRECTION_OUT) {
372 		seq_printf(s, "output %s ", val ? "high" : "low");
373 		if (type)
374 			seq_printf(s, "open drain %s internal pull-up ",
375 				   pupd ? "with" : "without");
376 		else
377 			seq_puts(s, "push pull no pull ");
378 	} else {
379 		seq_printf(s, "input %s ", val ? "high" : "low");
380 		if (type)
381 			seq_printf(s, "with internal pull-%s ",
382 				   pupd ? "up" : "down");
383 		else
384 			seq_printf(s, "%s ", pupd ? "floating" : "analog");
385 	}
386 }
387 
388 static const struct pinconf_ops stmfx_pinconf_ops = {
389 	.pin_config_get		= stmfx_pinconf_get,
390 	.pin_config_set		= stmfx_pinconf_set,
391 	.pin_config_dbg_show	= stmfx_pinconf_dbg_show,
392 };
393 
stmfx_pinctrl_get_groups_count(struct pinctrl_dev * pctldev)394 static int stmfx_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
395 {
396 	return 0;
397 }
398 
stmfx_pinctrl_get_group_name(struct pinctrl_dev * pctldev,unsigned int selector)399 static const char *stmfx_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
400 						unsigned int selector)
401 {
402 	return NULL;
403 }
404 
stmfx_pinctrl_get_group_pins(struct pinctrl_dev * pctldev,unsigned int selector,const unsigned int ** pins,unsigned int * num_pins)405 static int stmfx_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
406 					unsigned int selector,
407 					const unsigned int **pins,
408 					unsigned int *num_pins)
409 {
410 	return -ENOTSUPP;
411 }
412 
413 static const struct pinctrl_ops stmfx_pinctrl_ops = {
414 	.get_groups_count = stmfx_pinctrl_get_groups_count,
415 	.get_group_name = stmfx_pinctrl_get_group_name,
416 	.get_group_pins = stmfx_pinctrl_get_group_pins,
417 	.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
418 	.dt_free_map = pinctrl_utils_free_map,
419 };
420 
stmfx_pinctrl_irq_mask(struct irq_data * data)421 static void stmfx_pinctrl_irq_mask(struct irq_data *data)
422 {
423 	struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
424 	struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip);
425 	u32 reg = get_reg(data->hwirq);
426 	u32 mask = get_mask(data->hwirq);
427 
428 	pctl->irq_gpi_src[reg] &= ~mask;
429 	gpiochip_disable_irq(gpio_chip, irqd_to_hwirq(data));
430 }
431 
stmfx_pinctrl_irq_unmask(struct irq_data * data)432 static void stmfx_pinctrl_irq_unmask(struct irq_data *data)
433 {
434 	struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
435 	struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip);
436 	u32 reg = get_reg(data->hwirq);
437 	u32 mask = get_mask(data->hwirq);
438 
439 	gpiochip_enable_irq(gpio_chip, irqd_to_hwirq(data));
440 	pctl->irq_gpi_src[reg] |= mask;
441 }
442 
stmfx_pinctrl_irq_set_type(struct irq_data * data,unsigned int type)443 static int stmfx_pinctrl_irq_set_type(struct irq_data *data, unsigned int type)
444 {
445 	struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
446 	struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip);
447 	u32 reg = get_reg(data->hwirq);
448 	u32 mask = get_mask(data->hwirq);
449 
450 	if (type == IRQ_TYPE_NONE)
451 		return -EINVAL;
452 
453 	if (type & IRQ_TYPE_EDGE_BOTH) {
454 		pctl->irq_gpi_evt[reg] |= mask;
455 		irq_set_handler_locked(data, handle_edge_irq);
456 	} else {
457 		pctl->irq_gpi_evt[reg] &= ~mask;
458 		irq_set_handler_locked(data, handle_level_irq);
459 	}
460 
461 	if ((type & IRQ_TYPE_EDGE_RISING) || (type & IRQ_TYPE_LEVEL_HIGH))
462 		pctl->irq_gpi_type[reg] |= mask;
463 	else
464 		pctl->irq_gpi_type[reg] &= ~mask;
465 
466 	/*
467 	 * In case of (type & IRQ_TYPE_EDGE_BOTH), we need to know current
468 	 * GPIO value to set the right edge trigger. But in atomic context
469 	 * here we can't access registers over I2C. That's why (type &
470 	 * IRQ_TYPE_EDGE_BOTH) will be managed in .irq_sync_unlock.
471 	 */
472 
473 	if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
474 		pctl->irq_toggle_edge[reg] |= mask;
475 	else
476 		pctl->irq_toggle_edge[reg] &= mask;
477 
478 	return 0;
479 }
480 
stmfx_pinctrl_irq_bus_lock(struct irq_data * data)481 static void stmfx_pinctrl_irq_bus_lock(struct irq_data *data)
482 {
483 	struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
484 	struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip);
485 
486 	mutex_lock(&pctl->lock);
487 }
488 
stmfx_pinctrl_irq_bus_sync_unlock(struct irq_data * data)489 static void stmfx_pinctrl_irq_bus_sync_unlock(struct irq_data *data)
490 {
491 	struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
492 	struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip);
493 	u32 reg = get_reg(data->hwirq);
494 	u32 mask = get_mask(data->hwirq);
495 
496 	/*
497 	 * In case of IRQ_TYPE_EDGE_BOTH), read the current GPIO value
498 	 * (this couldn't be done in .irq_set_type because of atomic context)
499 	 * to set the right irq trigger type.
500 	 */
501 	if (pctl->irq_toggle_edge[reg] & mask) {
502 		if (stmfx_gpio_get(gpio_chip, data->hwirq))
503 			pctl->irq_gpi_type[reg] &= ~mask;
504 		else
505 			pctl->irq_gpi_type[reg] |= mask;
506 	}
507 
508 	regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_EVT,
509 			  pctl->irq_gpi_evt, NR_GPIO_REGS);
510 	regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_TYPE,
511 			  pctl->irq_gpi_type, NR_GPIO_REGS);
512 	regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_SRC,
513 			  pctl->irq_gpi_src, NR_GPIO_REGS);
514 
515 	mutex_unlock(&pctl->lock);
516 }
517 
stmfx_gpio_irq_request_resources(struct irq_data * data)518 static int stmfx_gpio_irq_request_resources(struct irq_data *data)
519 {
520 	struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
521 	int ret;
522 
523 	ret = stmfx_gpio_direction_input(gpio_chip, data->hwirq);
524 	if (ret)
525 		return ret;
526 
527 	return gpiochip_reqres_irq(gpio_chip, data->hwirq);
528 }
529 
stmfx_gpio_irq_release_resources(struct irq_data * data)530 static void stmfx_gpio_irq_release_resources(struct irq_data *data)
531 {
532 	struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
533 
534 	return gpiochip_relres_irq(gpio_chip, data->hwirq);
535 }
536 
stmfx_pinctrl_irq_toggle_trigger(struct stmfx_pinctrl * pctl,unsigned int offset)537 static void stmfx_pinctrl_irq_toggle_trigger(struct stmfx_pinctrl *pctl,
538 					     unsigned int offset)
539 {
540 	u32 reg = get_reg(offset);
541 	u32 mask = get_mask(offset);
542 	int val;
543 
544 	if (!(pctl->irq_toggle_edge[reg] & mask))
545 		return;
546 
547 	val = stmfx_gpio_get(&pctl->gpio_chip, offset);
548 	if (val < 0)
549 		return;
550 
551 	if (val) {
552 		pctl->irq_gpi_type[reg] &= mask;
553 		regmap_write_bits(pctl->stmfx->map,
554 				  STMFX_REG_IRQ_GPI_TYPE + reg,
555 				  mask, 0);
556 
557 	} else {
558 		pctl->irq_gpi_type[reg] |= mask;
559 		regmap_write_bits(pctl->stmfx->map,
560 				  STMFX_REG_IRQ_GPI_TYPE + reg,
561 				  mask, mask);
562 	}
563 }
564 
stmfx_pinctrl_irq_thread_fn(int irq,void * dev_id)565 static irqreturn_t stmfx_pinctrl_irq_thread_fn(int irq, void *dev_id)
566 {
567 	struct stmfx_pinctrl *pctl = (struct stmfx_pinctrl *)dev_id;
568 	struct gpio_chip *gc = &pctl->gpio_chip;
569 	u8 pending[NR_GPIO_REGS];
570 	u8 src[NR_GPIO_REGS] = {0, 0, 0};
571 	unsigned long n, status;
572 	int i, ret;
573 
574 	ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_IRQ_GPI_PENDING,
575 			       &pending, NR_GPIO_REGS);
576 	if (ret)
577 		return IRQ_NONE;
578 
579 	regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_SRC,
580 			  src, NR_GPIO_REGS);
581 
582 	BUILD_BUG_ON(NR_GPIO_REGS > sizeof(status));
583 	for (i = 0, status = 0; i < NR_GPIO_REGS; i++)
584 		status |= (unsigned long)pending[i] << (i * 8);
585 	for_each_set_bit(n, &status, gc->ngpio) {
586 		handle_nested_irq(irq_find_mapping(gc->irq.domain, n));
587 		stmfx_pinctrl_irq_toggle_trigger(pctl, n);
588 	}
589 
590 	regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_SRC,
591 			  pctl->irq_gpi_src, NR_GPIO_REGS);
592 
593 	return IRQ_HANDLED;
594 }
595 
stmfx_pinctrl_irq_print_chip(struct irq_data * d,struct seq_file * p)596 static void stmfx_pinctrl_irq_print_chip(struct irq_data *d, struct seq_file *p)
597 {
598 	struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(d);
599 	struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip);
600 
601 	seq_printf(p, dev_name(pctl->dev));
602 }
603 
604 static const struct irq_chip stmfx_pinctrl_irq_chip = {
605 	.irq_mask = stmfx_pinctrl_irq_mask,
606 	.irq_unmask = stmfx_pinctrl_irq_unmask,
607 	.irq_set_type = stmfx_pinctrl_irq_set_type,
608 	.irq_bus_lock = stmfx_pinctrl_irq_bus_lock,
609 	.irq_bus_sync_unlock = stmfx_pinctrl_irq_bus_sync_unlock,
610 	.irq_request_resources = stmfx_gpio_irq_request_resources,
611 	.irq_release_resources = stmfx_gpio_irq_release_resources,
612 	.irq_print_chip = stmfx_pinctrl_irq_print_chip,
613 	.flags = IRQCHIP_IMMUTABLE,
614 };
615 
stmfx_pinctrl_gpio_function_enable(struct stmfx_pinctrl * pctl)616 static int stmfx_pinctrl_gpio_function_enable(struct stmfx_pinctrl *pctl)
617 {
618 	struct pinctrl_gpio_range *gpio_range;
619 	struct pinctrl_dev *pctl_dev = pctl->pctl_dev;
620 	u32 func = STMFX_FUNC_GPIO;
621 
622 	pctl->gpio_valid_mask = GENMASK(15, 0);
623 
624 	gpio_range = pinctrl_find_gpio_range_from_pin(pctl_dev, 16);
625 	if (gpio_range) {
626 		func |= STMFX_FUNC_ALTGPIO_LOW;
627 		pctl->gpio_valid_mask |= GENMASK(19, 16);
628 	}
629 
630 	gpio_range = pinctrl_find_gpio_range_from_pin(pctl_dev, 20);
631 	if (gpio_range) {
632 		func |= STMFX_FUNC_ALTGPIO_HIGH;
633 		pctl->gpio_valid_mask |= GENMASK(23, 20);
634 	}
635 
636 	return stmfx_function_enable(pctl->stmfx, func);
637 }
638 
stmfx_pinctrl_probe(struct platform_device * pdev)639 static int stmfx_pinctrl_probe(struct platform_device *pdev)
640 {
641 	struct stmfx *stmfx = dev_get_drvdata(pdev->dev.parent);
642 	struct device_node *np = pdev->dev.of_node;
643 	struct stmfx_pinctrl *pctl;
644 	struct gpio_irq_chip *girq;
645 	int irq, ret;
646 
647 	pctl = devm_kzalloc(stmfx->dev, sizeof(*pctl), GFP_KERNEL);
648 	if (!pctl)
649 		return -ENOMEM;
650 
651 	platform_set_drvdata(pdev, pctl);
652 
653 	pctl->dev = &pdev->dev;
654 	pctl->stmfx = stmfx;
655 
656 	if (!of_property_present(np, "gpio-ranges")) {
657 		dev_err(pctl->dev, "missing required gpio-ranges property\n");
658 		return -EINVAL;
659 	}
660 
661 	irq = platform_get_irq(pdev, 0);
662 	if (irq < 0)
663 		return irq;
664 
665 	mutex_init(&pctl->lock);
666 
667 	/* Register pin controller */
668 	pctl->pctl_desc.name = "stmfx-pinctrl";
669 	pctl->pctl_desc.pctlops = &stmfx_pinctrl_ops;
670 	pctl->pctl_desc.confops = &stmfx_pinconf_ops;
671 	pctl->pctl_desc.pins = stmfx_pins;
672 	pctl->pctl_desc.npins = ARRAY_SIZE(stmfx_pins);
673 	pctl->pctl_desc.owner = THIS_MODULE;
674 	pctl->pctl_desc.link_consumers = true;
675 
676 	ret = devm_pinctrl_register_and_init(pctl->dev, &pctl->pctl_desc,
677 					     pctl, &pctl->pctl_dev);
678 	if (ret) {
679 		dev_err(pctl->dev, "pinctrl registration failed\n");
680 		return ret;
681 	}
682 
683 	ret = pinctrl_enable(pctl->pctl_dev);
684 	if (ret) {
685 		dev_err(pctl->dev, "pinctrl enable failed\n");
686 		return ret;
687 	}
688 
689 	/* Register gpio controller */
690 	pctl->gpio_chip.label = "stmfx-gpio";
691 	pctl->gpio_chip.parent = pctl->dev;
692 	pctl->gpio_chip.get_direction = stmfx_gpio_get_direction;
693 	pctl->gpio_chip.direction_input = stmfx_gpio_direction_input;
694 	pctl->gpio_chip.direction_output = stmfx_gpio_direction_output;
695 	pctl->gpio_chip.get = stmfx_gpio_get;
696 	pctl->gpio_chip.set = stmfx_gpio_set;
697 	pctl->gpio_chip.set_config = gpiochip_generic_config;
698 	pctl->gpio_chip.base = -1;
699 	pctl->gpio_chip.ngpio = pctl->pctl_desc.npins;
700 	pctl->gpio_chip.can_sleep = true;
701 
702 	girq = &pctl->gpio_chip.irq;
703 	gpio_irq_chip_set_chip(girq, &stmfx_pinctrl_irq_chip);
704 	/* This will let us handle the parent IRQ in the driver */
705 	girq->parent_handler = NULL;
706 	girq->num_parents = 0;
707 	girq->parents = NULL;
708 	girq->default_type = IRQ_TYPE_NONE;
709 	girq->handler = handle_bad_irq;
710 	girq->threaded = true;
711 
712 	ret = devm_gpiochip_add_data(pctl->dev, &pctl->gpio_chip, pctl);
713 	if (ret) {
714 		dev_err(pctl->dev, "gpio_chip registration failed\n");
715 		return ret;
716 	}
717 
718 	ret = stmfx_pinctrl_gpio_function_enable(pctl);
719 	if (ret)
720 		return ret;
721 
722 	ret = devm_request_threaded_irq(pctl->dev, irq, NULL,
723 					stmfx_pinctrl_irq_thread_fn,
724 					IRQF_ONESHOT,
725 					dev_name(pctl->dev), pctl);
726 	if (ret) {
727 		dev_err(pctl->dev, "cannot request irq%d\n", irq);
728 		return ret;
729 	}
730 
731 	dev_info(pctl->dev,
732 		 "%ld GPIOs available\n", hweight_long(pctl->gpio_valid_mask));
733 
734 	return 0;
735 }
736 
stmfx_pinctrl_remove(struct platform_device * pdev)737 static int stmfx_pinctrl_remove(struct platform_device *pdev)
738 {
739 	struct stmfx *stmfx = dev_get_drvdata(pdev->dev.parent);
740 
741 	return stmfx_function_disable(stmfx,
742 				      STMFX_FUNC_GPIO |
743 				      STMFX_FUNC_ALTGPIO_LOW |
744 				      STMFX_FUNC_ALTGPIO_HIGH);
745 }
746 
747 #ifdef CONFIG_PM_SLEEP
stmfx_pinctrl_backup_regs(struct stmfx_pinctrl * pctl)748 static int stmfx_pinctrl_backup_regs(struct stmfx_pinctrl *pctl)
749 {
750 	int ret;
751 
752 	ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_GPIO_STATE,
753 			       &pctl->bkp_gpio_state, NR_GPIO_REGS);
754 	if (ret)
755 		return ret;
756 	ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_GPIO_DIR,
757 			       &pctl->bkp_gpio_dir, NR_GPIO_REGS);
758 	if (ret)
759 		return ret;
760 	ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_GPIO_TYPE,
761 			       &pctl->bkp_gpio_type, NR_GPIO_REGS);
762 	if (ret)
763 		return ret;
764 	ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_GPIO_PUPD,
765 			       &pctl->bkp_gpio_pupd, NR_GPIO_REGS);
766 	if (ret)
767 		return ret;
768 
769 	return 0;
770 }
771 
stmfx_pinctrl_restore_regs(struct stmfx_pinctrl * pctl)772 static int stmfx_pinctrl_restore_regs(struct stmfx_pinctrl *pctl)
773 {
774 	int ret;
775 
776 	ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_GPIO_DIR,
777 				pctl->bkp_gpio_dir, NR_GPIO_REGS);
778 	if (ret)
779 		return ret;
780 	ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_GPIO_TYPE,
781 				pctl->bkp_gpio_type, NR_GPIO_REGS);
782 	if (ret)
783 		return ret;
784 	ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_GPIO_PUPD,
785 				pctl->bkp_gpio_pupd, NR_GPIO_REGS);
786 	if (ret)
787 		return ret;
788 	ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_GPO_SET,
789 				pctl->bkp_gpio_state, NR_GPIO_REGS);
790 	if (ret)
791 		return ret;
792 	ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_EVT,
793 				pctl->irq_gpi_evt, NR_GPIO_REGS);
794 	if (ret)
795 		return ret;
796 	ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_TYPE,
797 				pctl->irq_gpi_type, NR_GPIO_REGS);
798 	if (ret)
799 		return ret;
800 	ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_SRC,
801 				pctl->irq_gpi_src, NR_GPIO_REGS);
802 	if (ret)
803 		return ret;
804 
805 	return 0;
806 }
807 
stmfx_pinctrl_suspend(struct device * dev)808 static int stmfx_pinctrl_suspend(struct device *dev)
809 {
810 	struct stmfx_pinctrl *pctl = dev_get_drvdata(dev);
811 	int ret;
812 
813 	ret = stmfx_pinctrl_backup_regs(pctl);
814 	if (ret) {
815 		dev_err(pctl->dev, "registers backup failure\n");
816 		return ret;
817 	}
818 
819 	return 0;
820 }
821 
stmfx_pinctrl_resume(struct device * dev)822 static int stmfx_pinctrl_resume(struct device *dev)
823 {
824 	struct stmfx_pinctrl *pctl = dev_get_drvdata(dev);
825 	int ret;
826 
827 	ret = stmfx_pinctrl_restore_regs(pctl);
828 	if (ret) {
829 		dev_err(pctl->dev, "registers restoration failure\n");
830 		return ret;
831 	}
832 
833 	return 0;
834 }
835 #endif
836 
837 static SIMPLE_DEV_PM_OPS(stmfx_pinctrl_dev_pm_ops,
838 			 stmfx_pinctrl_suspend, stmfx_pinctrl_resume);
839 
840 static const struct of_device_id stmfx_pinctrl_of_match[] = {
841 	{ .compatible = "st,stmfx-0300-pinctrl", },
842 	{},
843 };
844 MODULE_DEVICE_TABLE(of, stmfx_pinctrl_of_match);
845 
846 static struct platform_driver stmfx_pinctrl_driver = {
847 	.driver = {
848 		.name = "stmfx-pinctrl",
849 		.of_match_table = stmfx_pinctrl_of_match,
850 		.pm = &stmfx_pinctrl_dev_pm_ops,
851 	},
852 	.probe = stmfx_pinctrl_probe,
853 	.remove = stmfx_pinctrl_remove,
854 };
855 module_platform_driver(stmfx_pinctrl_driver);
856 
857 MODULE_DESCRIPTION("STMFX pinctrl/GPIO driver");
858 MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>");
859 MODULE_LICENSE("GPL v2");
860