xref: /openbmc/u-boot/arch/arm/mach-imx/init.c (revision e8f80a5a)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright 2015 Freescale Semiconductor, Inc.
4  */
5 
6 #include <asm/io.h>
7 #include <asm/arch/imx-regs.h>
8 #include <asm/arch/clock.h>
9 #include <asm/arch/sys_proto.h>
10 #include <asm/mach-imx/boot_mode.h>
11 #include <asm/arch/crm_regs.h>
12 
init_aips(void)13 void init_aips(void)
14 {
15 	struct aipstz_regs *aips1, *aips2, *aips3;
16 
17 	aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
18 	aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
19 	aips3 = (struct aipstz_regs *)AIPS3_BASE_ADDR;
20 
21 	/*
22 	 * Set all MPROTx to be non-bufferable, trusted for R/W,
23 	 * not forced to user-mode.
24 	 */
25 	writel(0x77777777, &aips1->mprot0);
26 	writel(0x77777777, &aips1->mprot1);
27 	writel(0x77777777, &aips2->mprot0);
28 	writel(0x77777777, &aips2->mprot1);
29 
30 	/*
31 	 * Set all OPACRx to be non-bufferable, not require
32 	 * supervisor privilege level for access,allow for
33 	 * write access and untrusted master access.
34 	 */
35 	writel(0x00000000, &aips1->opacr0);
36 	writel(0x00000000, &aips1->opacr1);
37 	writel(0x00000000, &aips1->opacr2);
38 	writel(0x00000000, &aips1->opacr3);
39 	writel(0x00000000, &aips1->opacr4);
40 	writel(0x00000000, &aips2->opacr0);
41 	writel(0x00000000, &aips2->opacr1);
42 	writel(0x00000000, &aips2->opacr2);
43 	writel(0x00000000, &aips2->opacr3);
44 	writel(0x00000000, &aips2->opacr4);
45 
46 	if (is_mx6ull() || is_mx6sx() || is_mx7()) {
47 		/*
48 		 * Set all MPROTx to be non-bufferable, trusted for R/W,
49 		 * not forced to user-mode.
50 		 */
51 		writel(0x77777777, &aips3->mprot0);
52 		writel(0x77777777, &aips3->mprot1);
53 
54 		/*
55 		 * Set all OPACRx to be non-bufferable, not require
56 		 * supervisor privilege level for access,allow for
57 		 * write access and untrusted master access.
58 		 */
59 		writel(0x00000000, &aips3->opacr0);
60 		writel(0x00000000, &aips3->opacr1);
61 		writel(0x00000000, &aips3->opacr2);
62 		writel(0x00000000, &aips3->opacr3);
63 		writel(0x00000000, &aips3->opacr4);
64 	}
65 }
66 
imx_wdog_disable_powerdown(void)67 void imx_wdog_disable_powerdown(void)
68 {
69 	struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
70 	struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
71 	struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
72 #ifdef CONFIG_MX7D
73 	struct wdog_regs *wdog4 = (struct wdog_regs *)WDOG4_BASE_ADDR;
74 #endif
75 
76 	/* Write to the PDE (Power Down Enable) bit */
77 	writew(0, &wdog1->wmcr);
78 	writew(0, &wdog2->wmcr);
79 
80 	if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx7())
81 		writew(0, &wdog3->wmcr);
82 #ifdef CONFIG_MX7D
83 	writew(0, &wdog4->wmcr);
84 #endif
85 }
86 
87 #define SRC_SCR_WARM_RESET_ENABLE	0
88 
init_src(void)89 void init_src(void)
90 {
91 	struct src *src_regs = (struct src *)SRC_BASE_ADDR;
92 	u32 val;
93 
94 	/*
95 	 * force warm reset sources to generate cold reset
96 	 * for a more reliable restart
97 	 */
98 	val = readl(&src_regs->scr);
99 	val &= ~(1 << SRC_SCR_WARM_RESET_ENABLE);
100 	writel(val, &src_regs->scr);
101 }
102 
103 #ifdef CONFIG_CMD_BMODE
boot_mode_apply(unsigned cfg_val)104 void boot_mode_apply(unsigned cfg_val)
105 {
106 	unsigned reg;
107 	struct src *psrc = (struct src *)SRC_BASE_ADDR;
108 	writel(cfg_val, &psrc->gpr9);
109 	reg = readl(&psrc->gpr10);
110 	if (cfg_val)
111 		reg |= 1 << 28;
112 	else
113 		reg &= ~(1 << 28);
114 	writel(reg, &psrc->gpr10);
115 }
116 #endif
117 
118 #if defined(CONFIG_MX6)
imx6_src_get_boot_mode(void)119 u32 imx6_src_get_boot_mode(void)
120 {
121 	if (imx6_is_bmode_from_gpr9())
122 		return readl(&src_base->gpr9);
123 	else
124 		return readl(&src_base->sbmr1);
125 }
126 #endif
127