1 /*
2  * Copyright 2022 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 #ifndef _gc_9_4_3_SH_MASK_HEADER
24 #define _gc_9_4_3_SH_MASK_HEADER
25 
26 
27 // addressBlock: xcd0_gc_grbmdec
28 //GRBM_CNTL
29 #define GRBM_CNTL__READ_TIMEOUT__SHIFT                                                                        0x0
30 #define GRBM_CNTL__REPORT_LAST_RDERR__SHIFT                                                                   0x1f
31 #define GRBM_CNTL__READ_TIMEOUT_MASK                                                                          0x000000FFL
32 #define GRBM_CNTL__REPORT_LAST_RDERR_MASK                                                                     0x80000000L
33 //GRBM_SKEW_CNTL
34 #define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT                                                             0x0
35 #define GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT                                                                     0x6
36 #define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK                                                               0x0000003FL
37 #define GRBM_SKEW_CNTL__SKEW_COUNT_MASK                                                                       0x00000FC0L
38 //GRBM_STATUS2
39 #define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT                                                           0x0
40 #define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT                                                           0x4
41 #define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT                                                           0x5
42 #define GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT                                                              0x6
43 #define GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT                                                              0x7
44 #define GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT                                                              0x8
45 #define GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT                                                              0x9
46 #define GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT                                                              0xa
47 #define GRBM_STATUS2__ME2PIPE1_RQ_PENDING__SHIFT                                                              0xb
48 #define GRBM_STATUS2__ME2PIPE2_RQ_PENDING__SHIFT                                                              0xc
49 #define GRBM_STATUS2__ME2PIPE3_RQ_PENDING__SHIFT                                                              0xd
50 #define GRBM_STATUS2__RLC_RQ_PENDING__SHIFT                                                                   0xe
51 #define GRBM_STATUS2__UTCL2_BUSY__SHIFT                                                                       0xf
52 #define GRBM_STATUS2__EA_BUSY__SHIFT                                                                          0x10
53 #define GRBM_STATUS2__RMI_BUSY__SHIFT                                                                         0x11
54 #define GRBM_STATUS2__UTCL2_RQ_PENDING__SHIFT                                                                 0x12
55 #define GRBM_STATUS2__CPF_RQ_PENDING__SHIFT                                                                   0x13
56 #define GRBM_STATUS2__EA_LINK_BUSY__SHIFT                                                                     0x14
57 #define GRBM_STATUS2__CANE_BUSY__SHIFT                                                                        0x15
58 #define GRBM_STATUS2__CANE_LINK_BUSY__SHIFT                                                                   0x16
59 #define GRBM_STATUS2__RLC_BUSY__SHIFT                                                                         0x18
60 #define GRBM_STATUS2__TC_BUSY__SHIFT                                                                          0x19
61 #define GRBM_STATUS2__TCC_CC_RESIDENT__SHIFT                                                                  0x1a
62 #define GRBM_STATUS2__CPF_BUSY__SHIFT                                                                         0x1c
63 #define GRBM_STATUS2__CPC_BUSY__SHIFT                                                                         0x1d
64 #define GRBM_STATUS2__CPG_BUSY__SHIFT                                                                         0x1e
65 #define GRBM_STATUS2__CPAXI_BUSY__SHIFT                                                                       0x1f
66 #define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK                                                             0x0000000FL
67 #define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK                                                             0x00000010L
68 #define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK                                                             0x00000020L
69 #define GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK                                                                0x00000040L
70 #define GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK                                                                0x00000080L
71 #define GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK                                                                0x00000100L
72 #define GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK                                                                0x00000200L
73 #define GRBM_STATUS2__ME2PIPE0_RQ_PENDING_MASK                                                                0x00000400L
74 #define GRBM_STATUS2__ME2PIPE1_RQ_PENDING_MASK                                                                0x00000800L
75 #define GRBM_STATUS2__ME2PIPE2_RQ_PENDING_MASK                                                                0x00001000L
76 #define GRBM_STATUS2__ME2PIPE3_RQ_PENDING_MASK                                                                0x00002000L
77 #define GRBM_STATUS2__RLC_RQ_PENDING_MASK                                                                     0x00004000L
78 #define GRBM_STATUS2__UTCL2_BUSY_MASK                                                                         0x00008000L
79 #define GRBM_STATUS2__EA_BUSY_MASK                                                                            0x00010000L
80 #define GRBM_STATUS2__RMI_BUSY_MASK                                                                           0x00020000L
81 #define GRBM_STATUS2__UTCL2_RQ_PENDING_MASK                                                                   0x00040000L
82 #define GRBM_STATUS2__CPF_RQ_PENDING_MASK                                                                     0x00080000L
83 #define GRBM_STATUS2__EA_LINK_BUSY_MASK                                                                       0x00100000L
84 #define GRBM_STATUS2__CANE_BUSY_MASK                                                                          0x00200000L
85 #define GRBM_STATUS2__CANE_LINK_BUSY_MASK                                                                     0x00400000L
86 #define GRBM_STATUS2__RLC_BUSY_MASK                                                                           0x01000000L
87 #define GRBM_STATUS2__TC_BUSY_MASK                                                                            0x02000000L
88 #define GRBM_STATUS2__TCC_CC_RESIDENT_MASK                                                                    0x04000000L
89 #define GRBM_STATUS2__CPF_BUSY_MASK                                                                           0x10000000L
90 #define GRBM_STATUS2__CPC_BUSY_MASK                                                                           0x20000000L
91 #define GRBM_STATUS2__CPG_BUSY_MASK                                                                           0x40000000L
92 #define GRBM_STATUS2__CPAXI_BUSY_MASK                                                                         0x80000000L
93 //GRBM_PWR_CNTL
94 #define GRBM_PWR_CNTL__ALL_REQ_TYPE__SHIFT                                                                    0x0
95 #define GRBM_PWR_CNTL__GFX_REQ_TYPE__SHIFT                                                                    0x2
96 #define GRBM_PWR_CNTL__ALL_RSP_TYPE__SHIFT                                                                    0x4
97 #define GRBM_PWR_CNTL__GFX_RSP_TYPE__SHIFT                                                                    0x6
98 #define GRBM_PWR_CNTL__GFX_REQ_EN__SHIFT                                                                      0xe
99 #define GRBM_PWR_CNTL__ALL_REQ_EN__SHIFT                                                                      0xf
100 #define GRBM_PWR_CNTL__ALL_REQ_TYPE_MASK                                                                      0x00000003L
101 #define GRBM_PWR_CNTL__GFX_REQ_TYPE_MASK                                                                      0x0000000CL
102 #define GRBM_PWR_CNTL__ALL_RSP_TYPE_MASK                                                                      0x00000030L
103 #define GRBM_PWR_CNTL__GFX_RSP_TYPE_MASK                                                                      0x000000C0L
104 #define GRBM_PWR_CNTL__GFX_REQ_EN_MASK                                                                        0x00004000L
105 #define GRBM_PWR_CNTL__ALL_REQ_EN_MASK                                                                        0x00008000L
106 //GRBM_STATUS
107 #define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT                                                            0x0
108 #define GRBM_STATUS__RSMU_RQ_PENDING__SHIFT                                                                   0x5
109 #define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT                                                            0x7
110 #define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT                                                            0x8
111 #define GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT                                                                0x9
112 #define GRBM_STATUS__DB_CLEAN__SHIFT                                                                          0xc
113 #define GRBM_STATUS__CB_CLEAN__SHIFT                                                                          0xd
114 #define GRBM_STATUS__TA_BUSY__SHIFT                                                                           0xe
115 #define GRBM_STATUS__GDS_BUSY__SHIFT                                                                          0xf
116 #define GRBM_STATUS__WD_BUSY_NO_DMA__SHIFT                                                                    0x10
117 #define GRBM_STATUS__VGT_BUSY__SHIFT                                                                          0x11
118 #define GRBM_STATUS__IA_BUSY_NO_DMA__SHIFT                                                                    0x12
119 #define GRBM_STATUS__IA_BUSY__SHIFT                                                                           0x13
120 #define GRBM_STATUS__SX_BUSY__SHIFT                                                                           0x14
121 #define GRBM_STATUS__WD_BUSY__SHIFT                                                                           0x15
122 #define GRBM_STATUS__SPI_BUSY__SHIFT                                                                          0x16
123 #define GRBM_STATUS__BCI_BUSY__SHIFT                                                                          0x17
124 #define GRBM_STATUS__SC_BUSY__SHIFT                                                                           0x18
125 #define GRBM_STATUS__PA_BUSY__SHIFT                                                                           0x19
126 #define GRBM_STATUS__DB_BUSY__SHIFT                                                                           0x1a
127 #define GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT                                                                 0x1c
128 #define GRBM_STATUS__CP_BUSY__SHIFT                                                                           0x1d
129 #define GRBM_STATUS__CB_BUSY__SHIFT                                                                           0x1e
130 #define GRBM_STATUS__GUI_ACTIVE__SHIFT                                                                        0x1f
131 #define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK                                                              0x0000000FL
132 #define GRBM_STATUS__RSMU_RQ_PENDING_MASK                                                                     0x00000020L
133 #define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK                                                              0x00000080L
134 #define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK                                                              0x00000100L
135 #define GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK                                                                  0x00000200L
136 #define GRBM_STATUS__DB_CLEAN_MASK                                                                            0x00001000L
137 #define GRBM_STATUS__CB_CLEAN_MASK                                                                            0x00002000L
138 #define GRBM_STATUS__TA_BUSY_MASK                                                                             0x00004000L
139 #define GRBM_STATUS__GDS_BUSY_MASK                                                                            0x00008000L
140 #define GRBM_STATUS__WD_BUSY_NO_DMA_MASK                                                                      0x00010000L
141 #define GRBM_STATUS__VGT_BUSY_MASK                                                                            0x00020000L
142 #define GRBM_STATUS__IA_BUSY_NO_DMA_MASK                                                                      0x00040000L
143 #define GRBM_STATUS__IA_BUSY_MASK                                                                             0x00080000L
144 #define GRBM_STATUS__SX_BUSY_MASK                                                                             0x00100000L
145 #define GRBM_STATUS__WD_BUSY_MASK                                                                             0x00200000L
146 #define GRBM_STATUS__SPI_BUSY_MASK                                                                            0x00400000L
147 #define GRBM_STATUS__BCI_BUSY_MASK                                                                            0x00800000L
148 #define GRBM_STATUS__SC_BUSY_MASK                                                                             0x01000000L
149 #define GRBM_STATUS__PA_BUSY_MASK                                                                             0x02000000L
150 #define GRBM_STATUS__DB_BUSY_MASK                                                                             0x04000000L
151 #define GRBM_STATUS__CP_COHERENCY_BUSY_MASK                                                                   0x10000000L
152 #define GRBM_STATUS__CP_BUSY_MASK                                                                             0x20000000L
153 #define GRBM_STATUS__CB_BUSY_MASK                                                                             0x40000000L
154 #define GRBM_STATUS__GUI_ACTIVE_MASK                                                                          0x80000000L
155 //GRBM_STATUS_SE0
156 #define GRBM_STATUS_SE0__DB_CLEAN__SHIFT                                                                      0x1
157 #define GRBM_STATUS_SE0__CB_CLEAN__SHIFT                                                                      0x2
158 #define GRBM_STATUS_SE0__RMI_BUSY__SHIFT                                                                      0x15
159 #define GRBM_STATUS_SE0__BCI_BUSY__SHIFT                                                                      0x16
160 #define GRBM_STATUS_SE0__VGT_BUSY__SHIFT                                                                      0x17
161 #define GRBM_STATUS_SE0__PA_BUSY__SHIFT                                                                       0x18
162 #define GRBM_STATUS_SE0__TA_BUSY__SHIFT                                                                       0x19
163 #define GRBM_STATUS_SE0__SX_BUSY__SHIFT                                                                       0x1a
164 #define GRBM_STATUS_SE0__SPI_BUSY__SHIFT                                                                      0x1b
165 #define GRBM_STATUS_SE0__SC_BUSY__SHIFT                                                                       0x1d
166 #define GRBM_STATUS_SE0__DB_BUSY__SHIFT                                                                       0x1e
167 #define GRBM_STATUS_SE0__CB_BUSY__SHIFT                                                                       0x1f
168 #define GRBM_STATUS_SE0__DB_CLEAN_MASK                                                                        0x00000002L
169 #define GRBM_STATUS_SE0__CB_CLEAN_MASK                                                                        0x00000004L
170 #define GRBM_STATUS_SE0__RMI_BUSY_MASK                                                                        0x00200000L
171 #define GRBM_STATUS_SE0__BCI_BUSY_MASK                                                                        0x00400000L
172 #define GRBM_STATUS_SE0__VGT_BUSY_MASK                                                                        0x00800000L
173 #define GRBM_STATUS_SE0__PA_BUSY_MASK                                                                         0x01000000L
174 #define GRBM_STATUS_SE0__TA_BUSY_MASK                                                                         0x02000000L
175 #define GRBM_STATUS_SE0__SX_BUSY_MASK                                                                         0x04000000L
176 #define GRBM_STATUS_SE0__SPI_BUSY_MASK                                                                        0x08000000L
177 #define GRBM_STATUS_SE0__SC_BUSY_MASK                                                                         0x20000000L
178 #define GRBM_STATUS_SE0__DB_BUSY_MASK                                                                         0x40000000L
179 #define GRBM_STATUS_SE0__CB_BUSY_MASK                                                                         0x80000000L
180 //GRBM_STATUS_SE1
181 #define GRBM_STATUS_SE1__DB_CLEAN__SHIFT                                                                      0x1
182 #define GRBM_STATUS_SE1__CB_CLEAN__SHIFT                                                                      0x2
183 #define GRBM_STATUS_SE1__RMI_BUSY__SHIFT                                                                      0x15
184 #define GRBM_STATUS_SE1__BCI_BUSY__SHIFT                                                                      0x16
185 #define GRBM_STATUS_SE1__VGT_BUSY__SHIFT                                                                      0x17
186 #define GRBM_STATUS_SE1__PA_BUSY__SHIFT                                                                       0x18
187 #define GRBM_STATUS_SE1__TA_BUSY__SHIFT                                                                       0x19
188 #define GRBM_STATUS_SE1__SX_BUSY__SHIFT                                                                       0x1a
189 #define GRBM_STATUS_SE1__SPI_BUSY__SHIFT                                                                      0x1b
190 #define GRBM_STATUS_SE1__SC_BUSY__SHIFT                                                                       0x1d
191 #define GRBM_STATUS_SE1__DB_BUSY__SHIFT                                                                       0x1e
192 #define GRBM_STATUS_SE1__CB_BUSY__SHIFT                                                                       0x1f
193 #define GRBM_STATUS_SE1__DB_CLEAN_MASK                                                                        0x00000002L
194 #define GRBM_STATUS_SE1__CB_CLEAN_MASK                                                                        0x00000004L
195 #define GRBM_STATUS_SE1__RMI_BUSY_MASK                                                                        0x00200000L
196 #define GRBM_STATUS_SE1__BCI_BUSY_MASK                                                                        0x00400000L
197 #define GRBM_STATUS_SE1__VGT_BUSY_MASK                                                                        0x00800000L
198 #define GRBM_STATUS_SE1__PA_BUSY_MASK                                                                         0x01000000L
199 #define GRBM_STATUS_SE1__TA_BUSY_MASK                                                                         0x02000000L
200 #define GRBM_STATUS_SE1__SX_BUSY_MASK                                                                         0x04000000L
201 #define GRBM_STATUS_SE1__SPI_BUSY_MASK                                                                        0x08000000L
202 #define GRBM_STATUS_SE1__SC_BUSY_MASK                                                                         0x20000000L
203 #define GRBM_STATUS_SE1__DB_BUSY_MASK                                                                         0x40000000L
204 #define GRBM_STATUS_SE1__CB_BUSY_MASK                                                                         0x80000000L
205 //GRBM_SOFT_RESET
206 #define GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT                                                                 0x0
207 #define GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT                                                                0x2
208 #define GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT                                                                0x10
209 #define GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT                                                                0x11
210 #define GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT                                                                0x12
211 #define GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT                                                                0x13
212 #define GRBM_SOFT_RESET__SOFT_RESET_CAC__SHIFT                                                                0x14
213 #define GRBM_SOFT_RESET__SOFT_RESET_CANE__SHIFT                                                               0x15
214 #define GRBM_SOFT_RESET__SOFT_RESET_EA__SHIFT                                                                 0x16
215 #define GRBM_SOFT_RESET__SOFT_RESET_UTCL2__SHIFT                                                              0x17
216 #define GRBM_SOFT_RESET__SOFT_RESET_CP_MASK                                                                   0x00000001L
217 #define GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK                                                                  0x00000004L
218 #define GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK                                                                  0x00010000L
219 #define GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK                                                                  0x00020000L
220 #define GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK                                                                  0x00040000L
221 #define GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK                                                                  0x00080000L
222 #define GRBM_SOFT_RESET__SOFT_RESET_CAC_MASK                                                                  0x00100000L
223 #define GRBM_SOFT_RESET__SOFT_RESET_CANE_MASK                                                                 0x00200000L
224 #define GRBM_SOFT_RESET__SOFT_RESET_EA_MASK                                                                   0x00400000L
225 #define GRBM_SOFT_RESET__SOFT_RESET_UTCL2_MASK                                                                0x00800000L
226 //GRBM_GFX_CLKEN_CNTL
227 #define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT                                                          0x0
228 #define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT                                                            0x8
229 #define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK                                                            0x0000000FL
230 #define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK                                                              0x00001F00L
231 //GRBM_WAIT_IDLE_CLOCKS
232 #define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT                                                        0x0
233 #define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK                                                          0x000000FFL
234 //GRBM_STATUS_SE2
235 #define GRBM_STATUS_SE2__DB_CLEAN__SHIFT                                                                      0x1
236 #define GRBM_STATUS_SE2__CB_CLEAN__SHIFT                                                                      0x2
237 #define GRBM_STATUS_SE2__RMI_BUSY__SHIFT                                                                      0x15
238 #define GRBM_STATUS_SE2__BCI_BUSY__SHIFT                                                                      0x16
239 #define GRBM_STATUS_SE2__VGT_BUSY__SHIFT                                                                      0x17
240 #define GRBM_STATUS_SE2__PA_BUSY__SHIFT                                                                       0x18
241 #define GRBM_STATUS_SE2__TA_BUSY__SHIFT                                                                       0x19
242 #define GRBM_STATUS_SE2__SX_BUSY__SHIFT                                                                       0x1a
243 #define GRBM_STATUS_SE2__SPI_BUSY__SHIFT                                                                      0x1b
244 #define GRBM_STATUS_SE2__SC_BUSY__SHIFT                                                                       0x1d
245 #define GRBM_STATUS_SE2__DB_BUSY__SHIFT                                                                       0x1e
246 #define GRBM_STATUS_SE2__CB_BUSY__SHIFT                                                                       0x1f
247 #define GRBM_STATUS_SE2__DB_CLEAN_MASK                                                                        0x00000002L
248 #define GRBM_STATUS_SE2__CB_CLEAN_MASK                                                                        0x00000004L
249 #define GRBM_STATUS_SE2__RMI_BUSY_MASK                                                                        0x00200000L
250 #define GRBM_STATUS_SE2__BCI_BUSY_MASK                                                                        0x00400000L
251 #define GRBM_STATUS_SE2__VGT_BUSY_MASK                                                                        0x00800000L
252 #define GRBM_STATUS_SE2__PA_BUSY_MASK                                                                         0x01000000L
253 #define GRBM_STATUS_SE2__TA_BUSY_MASK                                                                         0x02000000L
254 #define GRBM_STATUS_SE2__SX_BUSY_MASK                                                                         0x04000000L
255 #define GRBM_STATUS_SE2__SPI_BUSY_MASK                                                                        0x08000000L
256 #define GRBM_STATUS_SE2__SC_BUSY_MASK                                                                         0x20000000L
257 #define GRBM_STATUS_SE2__DB_BUSY_MASK                                                                         0x40000000L
258 #define GRBM_STATUS_SE2__CB_BUSY_MASK                                                                         0x80000000L
259 //GRBM_STATUS_SE3
260 #define GRBM_STATUS_SE3__DB_CLEAN__SHIFT                                                                      0x1
261 #define GRBM_STATUS_SE3__CB_CLEAN__SHIFT                                                                      0x2
262 #define GRBM_STATUS_SE3__RMI_BUSY__SHIFT                                                                      0x15
263 #define GRBM_STATUS_SE3__BCI_BUSY__SHIFT                                                                      0x16
264 #define GRBM_STATUS_SE3__VGT_BUSY__SHIFT                                                                      0x17
265 #define GRBM_STATUS_SE3__PA_BUSY__SHIFT                                                                       0x18
266 #define GRBM_STATUS_SE3__TA_BUSY__SHIFT                                                                       0x19
267 #define GRBM_STATUS_SE3__SX_BUSY__SHIFT                                                                       0x1a
268 #define GRBM_STATUS_SE3__SPI_BUSY__SHIFT                                                                      0x1b
269 #define GRBM_STATUS_SE3__SC_BUSY__SHIFT                                                                       0x1d
270 #define GRBM_STATUS_SE3__DB_BUSY__SHIFT                                                                       0x1e
271 #define GRBM_STATUS_SE3__CB_BUSY__SHIFT                                                                       0x1f
272 #define GRBM_STATUS_SE3__DB_CLEAN_MASK                                                                        0x00000002L
273 #define GRBM_STATUS_SE3__CB_CLEAN_MASK                                                                        0x00000004L
274 #define GRBM_STATUS_SE3__RMI_BUSY_MASK                                                                        0x00200000L
275 #define GRBM_STATUS_SE3__BCI_BUSY_MASK                                                                        0x00400000L
276 #define GRBM_STATUS_SE3__VGT_BUSY_MASK                                                                        0x00800000L
277 #define GRBM_STATUS_SE3__PA_BUSY_MASK                                                                         0x01000000L
278 #define GRBM_STATUS_SE3__TA_BUSY_MASK                                                                         0x02000000L
279 #define GRBM_STATUS_SE3__SX_BUSY_MASK                                                                         0x04000000L
280 #define GRBM_STATUS_SE3__SPI_BUSY_MASK                                                                        0x08000000L
281 #define GRBM_STATUS_SE3__SC_BUSY_MASK                                                                         0x20000000L
282 #define GRBM_STATUS_SE3__DB_BUSY_MASK                                                                         0x40000000L
283 #define GRBM_STATUS_SE3__CB_BUSY_MASK                                                                         0x80000000L
284 //GRBM_READ_ERROR
285 #define GRBM_READ_ERROR__READ_ADDRESS__SHIFT                                                                  0x2
286 #define GRBM_READ_ERROR__READ_PIPEID__SHIFT                                                                   0x14
287 #define GRBM_READ_ERROR__READ_MEID__SHIFT                                                                     0x16
288 #define GRBM_READ_ERROR__READ_ERROR__SHIFT                                                                    0x1f
289 #define GRBM_READ_ERROR__READ_ADDRESS_MASK                                                                    0x0003FFFCL
290 #define GRBM_READ_ERROR__READ_PIPEID_MASK                                                                     0x00300000L
291 #define GRBM_READ_ERROR__READ_MEID_MASK                                                                       0x00C00000L
292 #define GRBM_READ_ERROR__READ_ERROR_MASK                                                                      0x80000000L
293 //GRBM_READ_ERROR2
294 #define GRBM_READ_ERROR2__READ_REQUESTER_CPF__SHIFT                                                           0x10
295 #define GRBM_READ_ERROR2__READ_REQUESTER_RSMU__SHIFT                                                          0x11
296 #define GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT                                                           0x12
297 #define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT                                                       0x13
298 #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT                                                   0x14
299 #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT                                                   0x15
300 #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT                                                   0x16
301 #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT                                                   0x17
302 #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT                                                      0x18
303 #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT                                                      0x19
304 #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT                                                      0x1a
305 #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT                                                      0x1b
306 #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT                                                      0x1c
307 #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT                                                      0x1d
308 #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT                                                      0x1e
309 #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT                                                      0x1f
310 #define GRBM_READ_ERROR2__READ_REQUESTER_CPF_MASK                                                             0x00010000L
311 #define GRBM_READ_ERROR2__READ_REQUESTER_RSMU_MASK                                                            0x00020000L
312 #define GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK                                                             0x00040000L
313 #define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK                                                         0x00080000L
314 #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK                                                     0x00100000L
315 #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK                                                     0x00200000L
316 #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK                                                     0x00400000L
317 #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK                                                     0x00800000L
318 #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK                                                        0x01000000L
319 #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK                                                        0x02000000L
320 #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK                                                        0x04000000L
321 #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK                                                        0x08000000L
322 #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK                                                        0x10000000L
323 #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK                                                        0x20000000L
324 #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK                                                        0x40000000L
325 #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK                                                        0x80000000L
326 //GRBM_INT_CNTL
327 #define GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT                                                                0x0
328 #define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT                                                             0x13
329 #define GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK                                                                  0x00000001L
330 #define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK                                                               0x00080000L
331 //GRBM_TRAP_OP
332 #define GRBM_TRAP_OP__RW__SHIFT                                                                               0x0
333 #define GRBM_TRAP_OP__RW_MASK                                                                                 0x00000001L
334 //GRBM_TRAP_ADDR
335 #define GRBM_TRAP_ADDR__DATA__SHIFT                                                                           0x0
336 #define GRBM_TRAP_ADDR__DATA_MASK                                                                             0x0003FFFFL
337 //GRBM_TRAP_ADDR_MSK
338 #define GRBM_TRAP_ADDR_MSK__DATA__SHIFT                                                                       0x0
339 #define GRBM_TRAP_ADDR_MSK__DATA_MASK                                                                         0x0003FFFFL
340 //GRBM_TRAP_WD
341 #define GRBM_TRAP_WD__DATA__SHIFT                                                                             0x0
342 #define GRBM_TRAP_WD__DATA_MASK                                                                               0xFFFFFFFFL
343 //GRBM_TRAP_WD_MSK
344 #define GRBM_TRAP_WD_MSK__DATA__SHIFT                                                                         0x0
345 #define GRBM_TRAP_WD_MSK__DATA_MASK                                                                           0xFFFFFFFFL
346 //GRBM_WRITE_ERROR
347 #define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC__SHIFT                                                          0x0
348 #define GRBM_WRITE_ERROR__WRITE_REQUESTER_RSMU__SHIFT                                                         0x1
349 #define GRBM_WRITE_ERROR__WRITE_SSRCID__SHIFT                                                                 0x2
350 #define GRBM_WRITE_ERROR__WRITE_VFID__SHIFT                                                                   0x5
351 #define GRBM_WRITE_ERROR__WRITE_VF__SHIFT                                                                     0xc
352 #define GRBM_WRITE_ERROR__WRITE_VMID__SHIFT                                                                   0xd
353 #define GRBM_WRITE_ERROR__TMZ__SHIFT                                                                          0x11
354 #define GRBM_WRITE_ERROR__CP_SECURE_WR_ILLEGAL__SHIFT                                                         0x12
355 #define GRBM_WRITE_ERROR__WRITE_PIPEID__SHIFT                                                                 0x14
356 #define GRBM_WRITE_ERROR__WRITE_MEID__SHIFT                                                                   0x16
357 #define GRBM_WRITE_ERROR__WRITE_ERROR__SHIFT                                                                  0x1f
358 #define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC_MASK                                                            0x00000001L
359 #define GRBM_WRITE_ERROR__WRITE_REQUESTER_RSMU_MASK                                                           0x00000002L
360 #define GRBM_WRITE_ERROR__WRITE_SSRCID_MASK                                                                   0x0000001CL
361 #define GRBM_WRITE_ERROR__WRITE_VFID_MASK                                                                     0x000001E0L
362 #define GRBM_WRITE_ERROR__WRITE_VF_MASK                                                                       0x00001000L
363 #define GRBM_WRITE_ERROR__WRITE_VMID_MASK                                                                     0x0001E000L
364 #define GRBM_WRITE_ERROR__TMZ_MASK                                                                            0x00020000L
365 #define GRBM_WRITE_ERROR__CP_SECURE_WR_ILLEGAL_MASK                                                           0x00040000L
366 #define GRBM_WRITE_ERROR__WRITE_PIPEID_MASK                                                                   0x00300000L
367 #define GRBM_WRITE_ERROR__WRITE_MEID_MASK                                                                     0x00C00000L
368 #define GRBM_WRITE_ERROR__WRITE_ERROR_MASK                                                                    0x80000000L
369 //GRBM_IOV_ERROR
370 #define GRBM_IOV_ERROR__IOV_ADDR__SHIFT                                                                       0x2
371 #define GRBM_IOV_ERROR__IOV_VFID__SHIFT                                                                       0x14
372 #define GRBM_IOV_ERROR__IOV_VF__SHIFT                                                                         0x1a
373 #define GRBM_IOV_ERROR__IOV_OP__SHIFT                                                                         0x1b
374 #define GRBM_IOV_ERROR__IOV_ERROR__SHIFT                                                                      0x1f
375 #define GRBM_IOV_ERROR__IOV_ADDR_MASK                                                                         0x000FFFFCL
376 #define GRBM_IOV_ERROR__IOV_VFID_MASK                                                                         0x03F00000L
377 #define GRBM_IOV_ERROR__IOV_VF_MASK                                                                           0x04000000L
378 #define GRBM_IOV_ERROR__IOV_OP_MASK                                                                           0x08000000L
379 #define GRBM_IOV_ERROR__IOV_ERROR_MASK                                                                        0x80000000L
380 //GRBM_CHIP_REVISION
381 #define GRBM_CHIP_REVISION__CHIP_REVISION__SHIFT                                                              0x0
382 #define GRBM_CHIP_REVISION__CHIP_REVISION_MASK                                                                0x000000FFL
383 //GRBM_GFX_CNTL
384 #define GRBM_GFX_CNTL__PIPEID__SHIFT                                                                          0x0
385 #define GRBM_GFX_CNTL__MEID__SHIFT                                                                            0x2
386 #define GRBM_GFX_CNTL__VMID__SHIFT                                                                            0x4
387 #define GRBM_GFX_CNTL__QUEUEID__SHIFT                                                                         0x8
388 #define GRBM_GFX_CNTL__PIPEID_MASK                                                                            0x00000003L
389 #define GRBM_GFX_CNTL__MEID_MASK                                                                              0x0000000CL
390 #define GRBM_GFX_CNTL__VMID_MASK                                                                              0x000000F0L
391 #define GRBM_GFX_CNTL__QUEUEID_MASK                                                                           0x00000700L
392 //GRBM_RSMU_CFG
393 #define GRBM_RSMU_CFG__APERTURE_ID__SHIFT                                                                     0x0
394 #define GRBM_RSMU_CFG__QOS__SHIFT                                                                             0xc
395 #define GRBM_RSMU_CFG__POSTED_WR__SHIFT                                                                       0x10
396 #define GRBM_RSMU_CFG__DEBUG_MASK__SHIFT                                                                      0x11
397 #define GRBM_RSMU_CFG__APERTURE_ID_MASK                                                                       0x00000FFFL
398 #define GRBM_RSMU_CFG__QOS_MASK                                                                               0x0000F000L
399 #define GRBM_RSMU_CFG__POSTED_WR_MASK                                                                         0x00010000L
400 #define GRBM_RSMU_CFG__DEBUG_MASK_MASK                                                                        0x00020000L
401 //GRBM_IH_CREDIT
402 #define GRBM_IH_CREDIT__CREDIT_VALUE__SHIFT                                                                   0x0
403 #define GRBM_IH_CREDIT__IH_CLIENT_ID__SHIFT                                                                   0x10
404 #define GRBM_IH_CREDIT__CREDIT_VALUE_MASK                                                                     0x00000003L
405 #define GRBM_IH_CREDIT__IH_CLIENT_ID_MASK                                                                     0x00FF0000L
406 //GRBM_PWR_CNTL2
407 #define GRBM_PWR_CNTL2__PWR_REQUEST_HALT__SHIFT                                                               0x10
408 #define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT__SHIFT                                                         0x14
409 #define GRBM_PWR_CNTL2__PWR_REQUEST_HALT_MASK                                                                 0x00010000L
410 #define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT_MASK                                                           0x00100000L
411 //GRBM_UTCL2_INVAL_RANGE_START
412 #define GRBM_UTCL2_INVAL_RANGE_START__DATA__SHIFT                                                             0x0
413 #define GRBM_UTCL2_INVAL_RANGE_START__DATA_MASK                                                               0x0003FFFFL
414 //GRBM_UTCL2_INVAL_RANGE_END
415 #define GRBM_UTCL2_INVAL_RANGE_END__DATA__SHIFT                                                               0x0
416 #define GRBM_UTCL2_INVAL_RANGE_END__DATA_MASK                                                                 0x0003FFFFL
417 //GRBM_RSMU_READ_ERROR
418 #define GRBM_RSMU_READ_ERROR__RSMU_READ_ADDRESS__SHIFT                                                        0x2
419 #define GRBM_RSMU_READ_ERROR__RSMU_READ_VF__SHIFT                                                             0x14
420 #define GRBM_RSMU_READ_ERROR__RSMU_READ_VFID__SHIFT                                                           0x15
421 #define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_TYPE__SHIFT                                                     0x1b
422 #define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR__SHIFT                                                          0x1f
423 #define GRBM_RSMU_READ_ERROR__RSMU_READ_ADDRESS_MASK                                                          0x000FFFFCL
424 #define GRBM_RSMU_READ_ERROR__RSMU_READ_VF_MASK                                                               0x00100000L
425 #define GRBM_RSMU_READ_ERROR__RSMU_READ_VFID_MASK                                                             0x07E00000L
426 #define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_TYPE_MASK                                                       0x08000000L
427 #define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_MASK                                                            0x80000000L
428 //GRBM_CHICKEN_BITS
429 #define GRBM_CHICKEN_BITS__DISABLE_CP_VMID_RESET_REQ__SHIFT                                                   0x0
430 #define GRBM_CHICKEN_BITS__DISABLE_CP_VMID_RESET_REQ_MASK                                                     0x00000001L
431 //GRBM_FENCE_RANGE0
432 #define GRBM_FENCE_RANGE0__START__SHIFT                                                                       0x0
433 #define GRBM_FENCE_RANGE0__END__SHIFT                                                                         0x10
434 #define GRBM_FENCE_RANGE0__START_MASK                                                                         0x0000FFFFL
435 #define GRBM_FENCE_RANGE0__END_MASK                                                                           0xFFFF0000L
436 //GRBM_FENCE_RANGE1
437 #define GRBM_FENCE_RANGE1__START__SHIFT                                                                       0x0
438 #define GRBM_FENCE_RANGE1__END__SHIFT                                                                         0x10
439 #define GRBM_FENCE_RANGE1__START_MASK                                                                         0x0000FFFFL
440 #define GRBM_FENCE_RANGE1__END_MASK                                                                           0xFFFF0000L
441 //GRBM_IOV_READ_ERROR
442 #define GRBM_IOV_READ_ERROR__IOV_ADDR__SHIFT                                                                  0x2
443 #define GRBM_IOV_READ_ERROR__IOV_VFID__SHIFT                                                                  0x14
444 #define GRBM_IOV_READ_ERROR__IOV_VF__SHIFT                                                                    0x1a
445 #define GRBM_IOV_READ_ERROR__IOV_OP__SHIFT                                                                    0x1b
446 #define GRBM_IOV_READ_ERROR__IOV_ERROR__SHIFT                                                                 0x1f
447 #define GRBM_IOV_READ_ERROR__IOV_ADDR_MASK                                                                    0x000FFFFCL
448 #define GRBM_IOV_READ_ERROR__IOV_VFID_MASK                                                                    0x03F00000L
449 #define GRBM_IOV_READ_ERROR__IOV_VF_MASK                                                                      0x04000000L
450 #define GRBM_IOV_READ_ERROR__IOV_OP_MASK                                                                      0x08000000L
451 #define GRBM_IOV_READ_ERROR__IOV_ERROR_MASK                                                                   0x80000000L
452 //GRBM_NOWHERE
453 #define GRBM_NOWHERE__DATA__SHIFT                                                                             0x0
454 #define GRBM_NOWHERE__DATA_MASK                                                                               0xFFFFFFFFL
455 //GRBM_SCRATCH_REG0
456 #define GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT                                                                0x0
457 #define GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK                                                                  0xFFFFFFFFL
458 //GRBM_SCRATCH_REG1
459 #define GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT                                                                0x0
460 #define GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK                                                                  0xFFFFFFFFL
461 //GRBM_SCRATCH_REG2
462 #define GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT                                                                0x0
463 #define GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK                                                                  0xFFFFFFFFL
464 //GRBM_SCRATCH_REG3
465 #define GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT                                                                0x0
466 #define GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK                                                                  0xFFFFFFFFL
467 //GRBM_SCRATCH_REG4
468 #define GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT                                                                0x0
469 #define GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK                                                                  0xFFFFFFFFL
470 //GRBM_SCRATCH_REG5
471 #define GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT                                                                0x0
472 #define GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK                                                                  0xFFFFFFFFL
473 //GRBM_SCRATCH_REG6
474 #define GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT                                                                0x0
475 #define GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK                                                                  0xFFFFFFFFL
476 //GRBM_SCRATCH_REG7
477 #define GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT                                                                0x0
478 #define GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK                                                                  0xFFFFFFFFL
479 //VIOLATION_DATA_ASYNC_VF_PROG
480 #define VIOLATION_DATA_ASYNC_VF_PROG__SSRCID__SHIFT                                                           0x0
481 #define VIOLATION_DATA_ASYNC_VF_PROG__VFID__SHIFT                                                             0x4
482 #define VIOLATION_DATA_ASYNC_VF_PROG__VIOLATION_ERROR__SHIFT                                                  0x1f
483 #define VIOLATION_DATA_ASYNC_VF_PROG__SSRCID_MASK                                                             0x0000000FL
484 #define VIOLATION_DATA_ASYNC_VF_PROG__VFID_MASK                                                               0x000003F0L
485 #define VIOLATION_DATA_ASYNC_VF_PROG__VIOLATION_ERROR_MASK                                                    0x80000000L
486 
487 
488 // addressBlock: xcd0_gc_cpdec
489 //CP_CPC_DEBUG_CNTL
490 #define CP_CPC_DEBUG_CNTL__DEBUG_INDX__SHIFT                                                                  0x0
491 #define CP_CPC_DEBUG_CNTL__DEBUG_BUS_DC_GD_SEL__SHIFT                                                         0x8
492 #define CP_CPC_DEBUG_CNTL__DEBUG_BUS_SELECT_BITS__SHIFT                                                       0x10
493 #define CP_CPC_DEBUG_CNTL__DEBUG_BUS_FLOP_EN__SHIFT                                                           0x1f
494 #define CP_CPC_DEBUG_CNTL__DEBUG_INDX_MASK                                                                    0x0000007FL
495 #define CP_CPC_DEBUG_CNTL__DEBUG_BUS_DC_GD_SEL_MASK                                                           0x00000700L
496 #define CP_CPC_DEBUG_CNTL__DEBUG_BUS_SELECT_BITS_MASK                                                         0x003F0000L
497 #define CP_CPC_DEBUG_CNTL__DEBUG_BUS_FLOP_EN_MASK                                                             0x80000000L
498 //CP_CPF_DEBUG_CNTL
499 #define CP_CPF_DEBUG_CNTL__DEBUG_INDX__SHIFT                                                                  0x0
500 #define CP_CPF_DEBUG_CNTL__DEBUG_BUS_SELECT_BITS__SHIFT                                                       0x10
501 #define CP_CPF_DEBUG_CNTL__DEBUG_BUS_FLOP_EN__SHIFT                                                           0x1f
502 #define CP_CPF_DEBUG_CNTL__DEBUG_INDX_MASK                                                                    0x0000007FL
503 #define CP_CPF_DEBUG_CNTL__DEBUG_BUS_SELECT_BITS_MASK                                                         0x003F0000L
504 #define CP_CPF_DEBUG_CNTL__DEBUG_BUS_FLOP_EN_MASK                                                             0x80000000L
505 //CP_CPC_STATUS
506 #define CP_CPC_STATUS__MEC1_BUSY__SHIFT                                                                       0x0
507 #define CP_CPC_STATUS__MEC2_BUSY__SHIFT                                                                       0x1
508 #define CP_CPC_STATUS__DC0_BUSY__SHIFT                                                                        0x2
509 #define CP_CPC_STATUS__DC1_BUSY__SHIFT                                                                        0x3
510 #define CP_CPC_STATUS__RCIU1_BUSY__SHIFT                                                                      0x4
511 #define CP_CPC_STATUS__RCIU2_BUSY__SHIFT                                                                      0x5
512 #define CP_CPC_STATUS__ROQ1_BUSY__SHIFT                                                                       0x6
513 #define CP_CPC_STATUS__ROQ2_BUSY__SHIFT                                                                       0x7
514 #define CP_CPC_STATUS__TCIU_BUSY__SHIFT                                                                       0xa
515 #define CP_CPC_STATUS__SCRATCH_RAM_BUSY__SHIFT                                                                0xb
516 #define CP_CPC_STATUS__QU_BUSY__SHIFT                                                                         0xc
517 #define CP_CPC_STATUS__UTCL2IU_BUSY__SHIFT                                                                    0xd
518 #define CP_CPC_STATUS__SAVE_RESTORE_BUSY__SHIFT                                                               0xe
519 #define CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT                                                                    0x1d
520 #define CP_CPC_STATUS__CPF_CPC_BUSY__SHIFT                                                                    0x1e
521 #define CP_CPC_STATUS__CPC_BUSY__SHIFT                                                                        0x1f
522 #define CP_CPC_STATUS__MEC1_BUSY_MASK                                                                         0x00000001L
523 #define CP_CPC_STATUS__MEC2_BUSY_MASK                                                                         0x00000002L
524 #define CP_CPC_STATUS__DC0_BUSY_MASK                                                                          0x00000004L
525 #define CP_CPC_STATUS__DC1_BUSY_MASK                                                                          0x00000008L
526 #define CP_CPC_STATUS__RCIU1_BUSY_MASK                                                                        0x00000010L
527 #define CP_CPC_STATUS__RCIU2_BUSY_MASK                                                                        0x00000020L
528 #define CP_CPC_STATUS__ROQ1_BUSY_MASK                                                                         0x00000040L
529 #define CP_CPC_STATUS__ROQ2_BUSY_MASK                                                                         0x00000080L
530 #define CP_CPC_STATUS__TCIU_BUSY_MASK                                                                         0x00000400L
531 #define CP_CPC_STATUS__SCRATCH_RAM_BUSY_MASK                                                                  0x00000800L
532 #define CP_CPC_STATUS__QU_BUSY_MASK                                                                           0x00001000L
533 #define CP_CPC_STATUS__UTCL2IU_BUSY_MASK                                                                      0x00002000L
534 #define CP_CPC_STATUS__SAVE_RESTORE_BUSY_MASK                                                                 0x00004000L
535 #define CP_CPC_STATUS__CPG_CPC_BUSY_MASK                                                                      0x20000000L
536 #define CP_CPC_STATUS__CPF_CPC_BUSY_MASK                                                                      0x40000000L
537 #define CP_CPC_STATUS__CPC_BUSY_MASK                                                                          0x80000000L
538 //CP_CPC_BUSY_STAT
539 #define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT                                                               0x0
540 #define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY__SHIFT                                                          0x1
541 #define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT                                                              0x2
542 #define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT                                                            0x3
543 #define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT                                                          0x4
544 #define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT                                                           0x5
545 #define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT                                                           0x6
546 #define CP_CPC_BUSY_STAT__MEC1_TC_BUSY__SHIFT                                                                 0x7
547 #define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY__SHIFT                                                                0x8
548 #define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT                                                      0x9
549 #define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT                                                              0xa
550 #define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT                                                              0xb
551 #define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT                                                              0xc
552 #define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT                                                              0xd
553 #define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT                                                               0x10
554 #define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY__SHIFT                                                          0x11
555 #define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT                                                              0x12
556 #define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT                                                            0x13
557 #define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT                                                          0x14
558 #define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT                                                           0x15
559 #define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT                                                           0x16
560 #define CP_CPC_BUSY_STAT__MEC2_TC_BUSY__SHIFT                                                                 0x17
561 #define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY__SHIFT                                                                0x18
562 #define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT                                                      0x19
563 #define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT                                                              0x1a
564 #define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT                                                              0x1b
565 #define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT                                                              0x1c
566 #define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT                                                              0x1d
567 #define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY_MASK                                                                 0x00000001L
568 #define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY_MASK                                                            0x00000002L
569 #define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY_MASK                                                                0x00000004L
570 #define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK                                                              0x00000008L
571 #define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK                                                            0x00000010L
572 #define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK                                                             0x00000020L
573 #define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK                                                             0x00000040L
574 #define CP_CPC_BUSY_STAT__MEC1_TC_BUSY_MASK                                                                   0x00000080L
575 #define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY_MASK                                                                  0x00000100L
576 #define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK                                                        0x00000200L
577 #define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK                                                                0x00000400L
578 #define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK                                                                0x00000800L
579 #define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY_MASK                                                                0x00001000L
580 #define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY_MASK                                                                0x00002000L
581 #define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY_MASK                                                                 0x00010000L
582 #define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY_MASK                                                            0x00020000L
583 #define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY_MASK                                                                0x00040000L
584 #define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK                                                              0x00080000L
585 #define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK                                                            0x00100000L
586 #define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK                                                             0x00200000L
587 #define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK                                                             0x00400000L
588 #define CP_CPC_BUSY_STAT__MEC2_TC_BUSY_MASK                                                                   0x00800000L
589 #define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY_MASK                                                                  0x01000000L
590 #define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK                                                        0x02000000L
591 #define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY_MASK                                                                0x04000000L
592 #define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY_MASK                                                                0x08000000L
593 #define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY_MASK                                                                0x10000000L
594 #define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY_MASK                                                                0x20000000L
595 //CP_CPC_STALLED_STAT1
596 #define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT                                                       0x3
597 #define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT                                                      0x4
598 #define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT                                                       0x6
599 #define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT                                                     0x8
600 #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT                                                        0x9
601 #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT                                                   0xa
602 #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT                                                    0xd
603 #define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT                                                     0x10
604 #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT                                                        0x11
605 #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT                                                   0x12
606 #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT                                                    0x15
607 #define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT                                                  0x16
608 #define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT                                                  0x17
609 #define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS__SHIFT                                                   0x18
610 #define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK                                                         0x00000008L
611 #define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK                                                        0x00000010L
612 #define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK                                                         0x00000040L
613 #define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET_MASK                                                       0x00000100L
614 #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK                                                          0x00000200L
615 #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK                                                     0x00000400L
616 #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK                                                      0x00002000L
617 #define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET_MASK                                                       0x00010000L
618 #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK                                                          0x00020000L
619 #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK                                                     0x00040000L
620 #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK                                                      0x00200000L
621 #define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK                                                    0x00400000L
622 #define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK                                                    0x00800000L
623 #define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS_MASK                                                     0x01000000L
624 //CP_CPF_STATUS
625 #define CP_CPF_STATUS__POST_WPTR_GFX_BUSY__SHIFT                                                              0x0
626 #define CP_CPF_STATUS__CSF_BUSY__SHIFT                                                                        0x1
627 #define CP_CPF_STATUS__ROQ_ALIGN_BUSY__SHIFT                                                                  0x4
628 #define CP_CPF_STATUS__ROQ_RING_BUSY__SHIFT                                                                   0x5
629 #define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY__SHIFT                                                              0x6
630 #define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY__SHIFT                                                              0x7
631 #define CP_CPF_STATUS__ROQ_STATE_BUSY__SHIFT                                                                  0x8
632 #define CP_CPF_STATUS__ROQ_CE_RING_BUSY__SHIFT                                                                0x9
633 #define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT                                                           0xa
634 #define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY__SHIFT                                                           0xb
635 #define CP_CPF_STATUS__SEMAPHORE_BUSY__SHIFT                                                                  0xc
636 #define CP_CPF_STATUS__INTERRUPT_BUSY__SHIFT                                                                  0xd
637 #define CP_CPF_STATUS__TCIU_BUSY__SHIFT                                                                       0xe
638 #define CP_CPF_STATUS__HQD_BUSY__SHIFT                                                                        0xf
639 #define CP_CPF_STATUS__PRT_BUSY__SHIFT                                                                        0x10
640 #define CP_CPF_STATUS__UTCL2IU_BUSY__SHIFT                                                                    0x11
641 #define CP_CPF_STATUS__CPF_GFX_BUSY__SHIFT                                                                    0x1a
642 #define CP_CPF_STATUS__CPF_CMP_BUSY__SHIFT                                                                    0x1b
643 #define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY__SHIFT                                                              0x1c
644 #define CP_CPF_STATUS__CPC_CPF_BUSY__SHIFT                                                                    0x1e
645 #define CP_CPF_STATUS__CPF_BUSY__SHIFT                                                                        0x1f
646 #define CP_CPF_STATUS__POST_WPTR_GFX_BUSY_MASK                                                                0x00000001L
647 #define CP_CPF_STATUS__CSF_BUSY_MASK                                                                          0x00000002L
648 #define CP_CPF_STATUS__ROQ_ALIGN_BUSY_MASK                                                                    0x00000010L
649 #define CP_CPF_STATUS__ROQ_RING_BUSY_MASK                                                                     0x00000020L
650 #define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY_MASK                                                                0x00000040L
651 #define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY_MASK                                                                0x00000080L
652 #define CP_CPF_STATUS__ROQ_STATE_BUSY_MASK                                                                    0x00000100L
653 #define CP_CPF_STATUS__ROQ_CE_RING_BUSY_MASK                                                                  0x00000200L
654 #define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY_MASK                                                             0x00000400L
655 #define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY_MASK                                                             0x00000800L
656 #define CP_CPF_STATUS__SEMAPHORE_BUSY_MASK                                                                    0x00001000L
657 #define CP_CPF_STATUS__INTERRUPT_BUSY_MASK                                                                    0x00002000L
658 #define CP_CPF_STATUS__TCIU_BUSY_MASK                                                                         0x00004000L
659 #define CP_CPF_STATUS__HQD_BUSY_MASK                                                                          0x00008000L
660 #define CP_CPF_STATUS__PRT_BUSY_MASK                                                                          0x00010000L
661 #define CP_CPF_STATUS__UTCL2IU_BUSY_MASK                                                                      0x00020000L
662 #define CP_CPF_STATUS__CPF_GFX_BUSY_MASK                                                                      0x04000000L
663 #define CP_CPF_STATUS__CPF_CMP_BUSY_MASK                                                                      0x08000000L
664 #define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY_MASK                                                                0x30000000L
665 #define CP_CPF_STATUS__CPC_CPF_BUSY_MASK                                                                      0x40000000L
666 #define CP_CPF_STATUS__CPF_BUSY_MASK                                                                          0x80000000L
667 //CP_CPF_BUSY_STAT
668 #define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT                                                            0x0
669 #define CP_CPF_BUSY_STAT__CSF_RING_BUSY__SHIFT                                                                0x1
670 #define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY__SHIFT                                                           0x2
671 #define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY__SHIFT                                                           0x3
672 #define CP_CPF_BUSY_STAT__CSF_STATE_BUSY__SHIFT                                                               0x4
673 #define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY__SHIFT                                                            0x5
674 #define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY__SHIFT                                                            0x6
675 #define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY__SHIFT                                                             0x7
676 #define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY__SHIFT                                                               0x8
677 #define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS__SHIFT                                                        0x9
678 #define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY__SHIFT                                                      0xb
679 #define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY__SHIFT                                                            0xc
680 #define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY__SHIFT                                                            0xd
681 #define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY__SHIFT                                                         0xe
682 #define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY__SHIFT                                                      0xf
683 #define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY__SHIFT                                                    0x10
684 #define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY__SHIFT                                                             0x11
685 #define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY__SHIFT                                                          0x12
686 #define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY__SHIFT                                                          0x13
687 #define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY__SHIFT                                                          0x14
688 #define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY__SHIFT                                                         0x15
689 #define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY__SHIFT                                                       0x16
690 #define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY__SHIFT                                                         0x17
691 #define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY__SHIFT                                                           0x18
692 #define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY__SHIFT                                                             0x19
693 #define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY__SHIFT                                                              0x1a
694 #define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY__SHIFT                                                              0x1b
695 #define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY__SHIFT                                                              0x1c
696 #define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT                                                           0x1d
697 #define CP_CPF_BUSY_STAT__HQD_PQ_BUSY__SHIFT                                                                  0x1e
698 #define CP_CPF_BUSY_STAT__HQD_IB_BUSY__SHIFT                                                                  0x1f
699 #define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK                                                              0x00000001L
700 #define CP_CPF_BUSY_STAT__CSF_RING_BUSY_MASK                                                                  0x00000002L
701 #define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY_MASK                                                             0x00000004L
702 #define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY_MASK                                                             0x00000008L
703 #define CP_CPF_BUSY_STAT__CSF_STATE_BUSY_MASK                                                                 0x00000010L
704 #define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY_MASK                                                              0x00000020L
705 #define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY_MASK                                                              0x00000040L
706 #define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY_MASK                                                               0x00000080L
707 #define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY_MASK                                                                 0x00000100L
708 #define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS_MASK                                                          0x00000200L
709 #define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY_MASK                                                        0x00000800L
710 #define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY_MASK                                                              0x00001000L
711 #define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY_MASK                                                              0x00002000L
712 #define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY_MASK                                                           0x00004000L
713 #define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY_MASK                                                        0x00008000L
714 #define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY_MASK                                                      0x00010000L
715 #define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY_MASK                                                               0x00020000L
716 #define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY_MASK                                                            0x00040000L
717 #define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY_MASK                                                            0x00080000L
718 #define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY_MASK                                                            0x00100000L
719 #define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY_MASK                                                           0x00200000L
720 #define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY_MASK                                                         0x00400000L
721 #define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY_MASK                                                           0x00800000L
722 #define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY_MASK                                                             0x01000000L
723 #define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY_MASK                                                               0x02000000L
724 #define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY_MASK                                                                0x04000000L
725 #define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY_MASK                                                                0x08000000L
726 #define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY_MASK                                                                0x10000000L
727 #define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY_MASK                                                             0x20000000L
728 #define CP_CPF_BUSY_STAT__HQD_PQ_BUSY_MASK                                                                    0x40000000L
729 #define CP_CPF_BUSY_STAT__HQD_IB_BUSY_MASK                                                                    0x80000000L
730 //CP_CPF_STALLED_STAT1
731 #define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA__SHIFT                                                       0x0
732 #define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA__SHIFT                                                      0x1
733 #define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA__SHIFT                                                      0x2
734 #define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA__SHIFT                                                      0x3
735 #define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE__SHIFT                                                     0x5
736 #define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT                                                     0x6
737 #define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT                                                  0x7
738 #define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT                                                  0x8
739 #define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS__SHIFT                                               0x9
740 #define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS__SHIFT                                               0xa
741 #define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE__SHIFT                                                     0xb
742 #define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA_MASK                                                         0x00000001L
743 #define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA_MASK                                                        0x00000002L
744 #define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA_MASK                                                        0x00000004L
745 #define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA_MASK                                                        0x00000008L
746 #define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE_MASK                                                       0x00000020L
747 #define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK                                                       0x00000040L
748 #define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK                                                    0x00000080L
749 #define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK                                                    0x00000100L
750 #define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS_MASK                                                 0x00000200L
751 #define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS_MASK                                                 0x00000400L
752 #define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE_MASK                                                       0x00000800L
753 //CP_CPC_GRBM_FREE_COUNT
754 #define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT__SHIFT                                                             0x0
755 #define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT_MASK                                                               0x0000003FL
756 //CP_CPC_PRIV_VIOLATION_ADDR
757 #define CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_STATUS__SHIFT                                              0x0
758 #define CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_OP__SHIFT                                                  0x1
759 #define CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR__SHIFT                                                0x2
760 #define CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_APERTURE_ID__SHIFT                                         0x14
761 #define CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_STATUS_MASK                                                0x00000001L
762 #define CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_OP_MASK                                                    0x00000002L
763 #define CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR_MASK                                                  0x000FFFFCL
764 #define CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_APERTURE_ID_MASK                                           0xFFF00000L
765 //CP_MEC_CNTL
766 #define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE__SHIFT                                                             0x4
767 #define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET__SHIFT                                                               0x10
768 #define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET__SHIFT                                                               0x11
769 #define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET__SHIFT                                                               0x12
770 #define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET__SHIFT                                                               0x13
771 #define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET__SHIFT                                                               0x14
772 #define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET__SHIFT                                                               0x15
773 #define CP_MEC_CNTL__MEC_ME2_HALT__SHIFT                                                                      0x1c
774 #define CP_MEC_CNTL__MEC_ME2_STEP__SHIFT                                                                      0x1d
775 #define CP_MEC_CNTL__MEC_ME1_HALT__SHIFT                                                                      0x1e
776 #define CP_MEC_CNTL__MEC_ME1_STEP__SHIFT                                                                      0x1f
777 #define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK                                                               0x00000010L
778 #define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK                                                                 0x00010000L
779 #define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK                                                                 0x00020000L
780 #define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK                                                                 0x00040000L
781 #define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK                                                                 0x00080000L
782 #define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK                                                                 0x00100000L
783 #define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK                                                                 0x00200000L
784 #define CP_MEC_CNTL__MEC_ME2_HALT_MASK                                                                        0x10000000L
785 #define CP_MEC_CNTL__MEC_ME2_STEP_MASK                                                                        0x20000000L
786 #define CP_MEC_CNTL__MEC_ME1_HALT_MASK                                                                        0x40000000L
787 #define CP_MEC_CNTL__MEC_ME1_STEP_MASK                                                                        0x80000000L
788 //CP_MEC_ME1_HEADER_DUMP
789 #define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP__SHIFT                                                            0x0
790 #define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP_MASK                                                              0xFFFFFFFFL
791 //CP_MEC_ME2_HEADER_DUMP
792 #define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP__SHIFT                                                            0x0
793 #define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP_MASK                                                              0xFFFFFFFFL
794 //CP_CPC_SCRATCH_INDEX
795 #define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT                                                            0x0
796 #define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_MASK                                                              0x000003FFL
797 //CP_CPC_SCRATCH_DATA
798 #define CP_CPC_SCRATCH_DATA__SCRATCH_DATA__SHIFT                                                              0x0
799 #define CP_CPC_SCRATCH_DATA__SCRATCH_DATA_MASK                                                                0xFFFFFFFFL
800 //CP_CPF_GRBM_FREE_COUNT
801 #define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT__SHIFT                                                             0x0
802 #define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT_MASK                                                               0x00000007L
803 //CP_CPC_HALT_HYST_COUNT
804 #define CP_CPC_HALT_HYST_COUNT__COUNT__SHIFT                                                                  0x0
805 #define CP_CPC_HALT_HYST_COUNT__COUNT_MASK                                                                    0x0000000FL
806 //CP_CE_COMPARE_COUNT
807 #define CP_CE_COMPARE_COUNT__COMPARE_COUNT__SHIFT                                                             0x0
808 #define CP_CE_COMPARE_COUNT__COMPARE_COUNT_MASK                                                               0xFFFFFFFFL
809 //CP_CE_DE_COUNT
810 #define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT                                                              0x0
811 #define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT_MASK                                                                0xFFFFFFFFL
812 //CP_DE_CE_COUNT
813 #define CP_DE_CE_COUNT__CONST_ENGINE_COUNT__SHIFT                                                             0x0
814 #define CP_DE_CE_COUNT__CONST_ENGINE_COUNT_MASK                                                               0xFFFFFFFFL
815 //CP_DE_LAST_INVAL_COUNT
816 #define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT__SHIFT                                                       0x0
817 #define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT_MASK                                                         0xFFFFFFFFL
818 //CP_DE_DE_COUNT
819 #define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT                                                              0x0
820 #define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT_MASK                                                                0xFFFFFFFFL
821 //CP_STALLED_STAT3
822 #define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT                                                     0x0
823 #define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT                                        0x1
824 #define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT                                     0x2
825 #define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT                                                       0x3
826 #define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT                                                       0x4
827 #define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT                                                      0x5
828 #define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT                                                0x6
829 #define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT                                                 0x7
830 #define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT                                                    0xa
831 #define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT                                                 0xb
832 #define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT                                                     0xc
833 #define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT                                           0xd
834 #define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT                                                         0xe
835 #define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT                                                         0xf
836 #define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM__SHIFT                                                  0x10
837 #define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA__SHIFT                                                0x11
838 #define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE__SHIFT                                                      0x12
839 #define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS__SHIFT                                                      0x13
840 #define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS__SHIFT                                                       0x14
841 #define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK                                                       0x00000001L
842 #define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK                                          0x00000002L
843 #define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK                                       0x00000004L
844 #define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK                                                         0x00000008L
845 #define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK                                                         0x00000010L
846 #define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK                                                        0x00000020L
847 #define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK                                                  0x00000040L
848 #define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK                                                   0x00000080L
849 #define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK                                                      0x00000400L
850 #define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK                                                   0x00000800L
851 #define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK                                                       0x00001000L
852 #define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK                                             0x00002000L
853 #define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK                                                           0x00004000L
854 #define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK                                                           0x00008000L
855 #define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM_MASK                                                    0x00010000L
856 #define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA_MASK                                                  0x00020000L
857 #define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE_MASK                                                        0x00040000L
858 #define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS_MASK                                                        0x00080000L
859 #define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS_MASK                                                         0x00100000L
860 //CP_STALLED_STAT1
861 #define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT                                                   0x0
862 #define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV__SHIFT                                                   0x2
863 #define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV__SHIFT                                                 0x4
864 #define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT                                                 0xa
865 #define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT                                                 0xb
866 #define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT                                                  0xc
867 #define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT                                                0xd
868 #define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA__SHIFT                                                   0xe
869 #define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT                                                  0xf
870 #define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT                                                     0x17
871 #define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT                                                    0x18
872 #define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT                                                     0x19
873 #define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT                                                      0x1a
874 #define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT                                                     0x1b
875 #define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT                                                  0x1c
876 #define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT                                                 0x1d
877 #define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK                                                     0x00000001L
878 #define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_MASK                                                     0x00000004L
879 #define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_MASK                                                   0x00000010L
880 #define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK                                                   0x00000400L
881 #define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK                                                   0x00000800L
882 #define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK                                                    0x00001000L
883 #define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK                                                  0x00002000L
884 #define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA_MASK                                                     0x00004000L
885 #define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK                                                    0x00008000L
886 #define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK                                                       0x00800000L
887 #define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK                                                      0x01000000L
888 #define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK                                                       0x02000000L
889 #define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK                                                        0x04000000L
890 #define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK                                                       0x08000000L
891 #define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK                                                    0x10000000L
892 #define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK                                                   0x20000000L
893 //CP_STALLED_STAT2
894 #define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT                                                    0x0
895 #define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT                                                    0x1
896 #define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT                                                   0x2
897 #define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT                                                    0x4
898 #define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT                                                        0x5
899 #define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT                                                   0x8
900 #define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT                                                        0x9
901 #define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT                                                      0xa
902 #define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT                                                     0xb
903 #define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT                                                       0xc
904 #define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT                                                   0xd
905 #define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT                                                     0xe
906 #define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT                                                  0xf
907 #define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT                                                     0x10
908 #define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT                                                     0x11
909 #define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT                                                     0x12
910 #define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT                                                 0x13
911 #define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT                                               0x14
912 #define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE__SHIFT                                                  0x15
913 #define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM__SHIFT                                                   0x16
914 #define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT                                                0x17
915 #define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT                                                   0x18
916 #define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT                                                   0x19
917 #define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT                                                   0x1a
918 #define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT                                                    0x1b
919 #define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT                                                      0x1c
920 #define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT                                              0x1d
921 #define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT                                                   0x1e
922 #define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT                                                    0x1f
923 #define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK                                                      0x00000001L
924 #define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK                                                      0x00000002L
925 #define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK                                                     0x00000004L
926 #define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK                                                      0x00000010L
927 #define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK                                                          0x00000020L
928 #define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK                                                     0x00000100L
929 #define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK                                                          0x00000200L
930 #define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK                                                        0x00000400L
931 #define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK                                                       0x00000800L
932 #define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK                                                         0x00001000L
933 #define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK                                                     0x00002000L
934 #define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK                                                       0x00004000L
935 #define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK                                                    0x00008000L
936 #define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK                                                       0x00010000L
937 #define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK                                                       0x00020000L
938 #define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK                                                       0x00040000L
939 #define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK                                                   0x00080000L
940 #define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK                                                 0x00100000L
941 #define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE_MASK                                                    0x00200000L
942 #define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM_MASK                                                     0x00400000L
943 #define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK                                                  0x00800000L
944 #define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK                                                     0x01000000L
945 #define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK                                                     0x02000000L
946 #define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK                                                     0x04000000L
947 #define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK                                                      0x08000000L
948 #define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK                                                        0x10000000L
949 #define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK                                                0x20000000L
950 #define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK                                                     0x40000000L
951 #define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK                                                      0x80000000L
952 //CP_BUSY_STAT
953 #define CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT                                                                0x0
954 #define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT                                                               0x6
955 #define CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT                                                              0x7
956 #define CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT                                                               0x8
957 #define CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT                                                                    0x9
958 #define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT                                                                     0xa
959 #define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT                                                            0xc
960 #define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT                                                           0xd
961 #define CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT                                                             0xe
962 #define CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT                                                                 0xf
963 #define CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT                                                                   0x11
964 #define CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT                                                                    0x12
965 #define CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT                                                                    0x13
966 #define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT                                                                  0x14
967 #define CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT                                                                     0x15
968 #define CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT                                                               0x16
969 #define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK                                                                  0x00000001L
970 #define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK                                                                 0x00000040L
971 #define CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK                                                                0x00000080L
972 #define CP_BUSY_STAT__ME_PARSING_PACKETS_MASK                                                                 0x00000100L
973 #define CP_BUSY_STAT__RCIU_PFP_BUSY_MASK                                                                      0x00000200L
974 #define CP_BUSY_STAT__RCIU_ME_BUSY_MASK                                                                       0x00000400L
975 #define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK                                                              0x00001000L
976 #define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK                                                             0x00002000L
977 #define CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK                                                               0x00004000L
978 #define CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK                                                                   0x00008000L
979 #define CP_BUSY_STAT__ME_PARSER_BUSY_MASK                                                                     0x00020000L
980 #define CP_BUSY_STAT__EOP_DONE_BUSY_MASK                                                                      0x00040000L
981 #define CP_BUSY_STAT__STRM_OUT_BUSY_MASK                                                                      0x00080000L
982 #define CP_BUSY_STAT__PIPE_STATS_BUSY_MASK                                                                    0x00100000L
983 #define CP_BUSY_STAT__RCIU_CE_BUSY_MASK                                                                       0x00200000L
984 #define CP_BUSY_STAT__CE_PARSING_PACKETS_MASK                                                                 0x00400000L
985 //CP_STAT
986 #define CP_STAT__ROQ_RING_BUSY__SHIFT                                                                         0x9
987 #define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT                                                                    0xa
988 #define CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT                                                                    0xb
989 #define CP_STAT__ROQ_STATE_BUSY__SHIFT                                                                        0xc
990 #define CP_STAT__DC_BUSY__SHIFT                                                                               0xd
991 #define CP_STAT__UTCL2IU_BUSY__SHIFT                                                                          0xe
992 #define CP_STAT__PFP_BUSY__SHIFT                                                                              0xf
993 #define CP_STAT__MEQ_BUSY__SHIFT                                                                              0x10
994 #define CP_STAT__ME_BUSY__SHIFT                                                                               0x11
995 #define CP_STAT__QUERY_BUSY__SHIFT                                                                            0x12
996 #define CP_STAT__SEMAPHORE_BUSY__SHIFT                                                                        0x13
997 #define CP_STAT__INTERRUPT_BUSY__SHIFT                                                                        0x14
998 #define CP_STAT__SURFACE_SYNC_BUSY__SHIFT                                                                     0x15
999 #define CP_STAT__DMA_BUSY__SHIFT                                                                              0x16
1000 #define CP_STAT__RCIU_BUSY__SHIFT                                                                             0x17
1001 #define CP_STAT__SCRATCH_RAM_BUSY__SHIFT                                                                      0x18
1002 #define CP_STAT__CE_BUSY__SHIFT                                                                               0x1a
1003 #define CP_STAT__TCIU_BUSY__SHIFT                                                                             0x1b
1004 #define CP_STAT__ROQ_CE_RING_BUSY__SHIFT                                                                      0x1c
1005 #define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT                                                                 0x1d
1006 #define CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT                                                                 0x1e
1007 #define CP_STAT__CP_BUSY__SHIFT                                                                               0x1f
1008 #define CP_STAT__ROQ_RING_BUSY_MASK                                                                           0x00000200L
1009 #define CP_STAT__ROQ_INDIRECT1_BUSY_MASK                                                                      0x00000400L
1010 #define CP_STAT__ROQ_INDIRECT2_BUSY_MASK                                                                      0x00000800L
1011 #define CP_STAT__ROQ_STATE_BUSY_MASK                                                                          0x00001000L
1012 #define CP_STAT__DC_BUSY_MASK                                                                                 0x00002000L
1013 #define CP_STAT__UTCL2IU_BUSY_MASK                                                                            0x00004000L
1014 #define CP_STAT__PFP_BUSY_MASK                                                                                0x00008000L
1015 #define CP_STAT__MEQ_BUSY_MASK                                                                                0x00010000L
1016 #define CP_STAT__ME_BUSY_MASK                                                                                 0x00020000L
1017 #define CP_STAT__QUERY_BUSY_MASK                                                                              0x00040000L
1018 #define CP_STAT__SEMAPHORE_BUSY_MASK                                                                          0x00080000L
1019 #define CP_STAT__INTERRUPT_BUSY_MASK                                                                          0x00100000L
1020 #define CP_STAT__SURFACE_SYNC_BUSY_MASK                                                                       0x00200000L
1021 #define CP_STAT__DMA_BUSY_MASK                                                                                0x00400000L
1022 #define CP_STAT__RCIU_BUSY_MASK                                                                               0x00800000L
1023 #define CP_STAT__SCRATCH_RAM_BUSY_MASK                                                                        0x01000000L
1024 #define CP_STAT__CE_BUSY_MASK                                                                                 0x04000000L
1025 #define CP_STAT__TCIU_BUSY_MASK                                                                               0x08000000L
1026 #define CP_STAT__ROQ_CE_RING_BUSY_MASK                                                                        0x10000000L
1027 #define CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK                                                                   0x20000000L
1028 #define CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK                                                                   0x40000000L
1029 #define CP_STAT__CP_BUSY_MASK                                                                                 0x80000000L
1030 //CP_ME_HEADER_DUMP
1031 #define CP_ME_HEADER_DUMP__ME_HEADER_DUMP__SHIFT                                                              0x0
1032 #define CP_ME_HEADER_DUMP__ME_HEADER_DUMP_MASK                                                                0xFFFFFFFFL
1033 //CP_PFP_HEADER_DUMP
1034 #define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP__SHIFT                                                            0x0
1035 #define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP_MASK                                                              0xFFFFFFFFL
1036 //CP_GRBM_FREE_COUNT
1037 #define CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT                                                                 0x0
1038 #define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT                                                             0x8
1039 #define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT                                                             0x10
1040 #define CP_GRBM_FREE_COUNT__FREE_COUNT_MASK                                                                   0x0000003FL
1041 #define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK                                                               0x00003F00L
1042 #define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK                                                               0x003F0000L
1043 //CP_CE_HEADER_DUMP
1044 #define CP_CE_HEADER_DUMP__CE_HEADER_DUMP__SHIFT                                                              0x0
1045 #define CP_CE_HEADER_DUMP__CE_HEADER_DUMP_MASK                                                                0xFFFFFFFFL
1046 //CP_PFP_INSTR_PNTR
1047 #define CP_PFP_INSTR_PNTR__INSTR_PNTR__SHIFT                                                                  0x0
1048 #define CP_PFP_INSTR_PNTR__INSTR_PNTR_MASK                                                                    0x0000FFFFL
1049 //CP_ME_INSTR_PNTR
1050 #define CP_ME_INSTR_PNTR__INSTR_PNTR__SHIFT                                                                   0x0
1051 #define CP_ME_INSTR_PNTR__INSTR_PNTR_MASK                                                                     0x0000FFFFL
1052 //CP_CE_INSTR_PNTR
1053 #define CP_CE_INSTR_PNTR__INSTR_PNTR__SHIFT                                                                   0x0
1054 #define CP_CE_INSTR_PNTR__INSTR_PNTR_MASK                                                                     0x0000FFFFL
1055 //CP_MEC1_INSTR_PNTR
1056 #define CP_MEC1_INSTR_PNTR__INSTR_PNTR__SHIFT                                                                 0x0
1057 #define CP_MEC1_INSTR_PNTR__INSTR_PNTR_MASK                                                                   0x0000FFFFL
1058 //CP_MEC2_INSTR_PNTR
1059 #define CP_MEC2_INSTR_PNTR__INSTR_PNTR__SHIFT                                                                 0x0
1060 #define CP_MEC2_INSTR_PNTR__INSTR_PNTR_MASK                                                                   0x0000FFFFL
1061 //CP_CSF_STAT
1062 #define CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT                                                              0x8
1063 #define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK                                                                0x0001FF00L
1064 //CP_ME_CNTL
1065 #define CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT                                                               0x4
1066 #define CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT                                                              0x6
1067 #define CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT                                                               0x8
1068 #define CP_ME_CNTL__CE_PIPE0_RESET__SHIFT                                                                     0x10
1069 #define CP_ME_CNTL__CE_PIPE1_RESET__SHIFT                                                                     0x11
1070 #define CP_ME_CNTL__PFP_PIPE0_RESET__SHIFT                                                                    0x12
1071 #define CP_ME_CNTL__PFP_PIPE1_RESET__SHIFT                                                                    0x13
1072 #define CP_ME_CNTL__ME_PIPE0_RESET__SHIFT                                                                     0x14
1073 #define CP_ME_CNTL__ME_PIPE1_RESET__SHIFT                                                                     0x15
1074 #define CP_ME_CNTL__CE_HALT__SHIFT                                                                            0x18
1075 #define CP_ME_CNTL__CE_STEP__SHIFT                                                                            0x19
1076 #define CP_ME_CNTL__PFP_HALT__SHIFT                                                                           0x1a
1077 #define CP_ME_CNTL__PFP_STEP__SHIFT                                                                           0x1b
1078 #define CP_ME_CNTL__ME_HALT__SHIFT                                                                            0x1c
1079 #define CP_ME_CNTL__ME_STEP__SHIFT                                                                            0x1d
1080 #define CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK                                                                 0x00000010L
1081 #define CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK                                                                0x00000040L
1082 #define CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK                                                                 0x00000100L
1083 #define CP_ME_CNTL__CE_PIPE0_RESET_MASK                                                                       0x00010000L
1084 #define CP_ME_CNTL__CE_PIPE1_RESET_MASK                                                                       0x00020000L
1085 #define CP_ME_CNTL__PFP_PIPE0_RESET_MASK                                                                      0x00040000L
1086 #define CP_ME_CNTL__PFP_PIPE1_RESET_MASK                                                                      0x00080000L
1087 #define CP_ME_CNTL__ME_PIPE0_RESET_MASK                                                                       0x00100000L
1088 #define CP_ME_CNTL__ME_PIPE1_RESET_MASK                                                                       0x00200000L
1089 #define CP_ME_CNTL__CE_HALT_MASK                                                                              0x01000000L
1090 #define CP_ME_CNTL__CE_STEP_MASK                                                                              0x02000000L
1091 #define CP_ME_CNTL__PFP_HALT_MASK                                                                             0x04000000L
1092 #define CP_ME_CNTL__PFP_STEP_MASK                                                                             0x08000000L
1093 #define CP_ME_CNTL__ME_HALT_MASK                                                                              0x10000000L
1094 #define CP_ME_CNTL__ME_STEP_MASK                                                                              0x20000000L
1095 //CP_CNTX_STAT
1096 #define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT                                                             0x0
1097 #define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT                                                             0x8
1098 #define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT                                                              0x14
1099 #define CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT                                                              0x1c
1100 #define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK                                                               0x000000FFL
1101 #define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK                                                               0x00000700L
1102 #define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK                                                                0x0FF00000L
1103 #define CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK                                                                0x70000000L
1104 //CP_ME_PREEMPTION
1105 #define CP_ME_PREEMPTION__OBSOLETE__SHIFT                                                                     0x0
1106 #define CP_ME_PREEMPTION__OBSOLETE_MASK                                                                       0x00000001L
1107 //CP_ROQ_THRESHOLDS
1108 #define CP_ROQ_THRESHOLDS__IB1_START__SHIFT                                                                   0x0
1109 #define CP_ROQ_THRESHOLDS__IB2_START__SHIFT                                                                   0x8
1110 #define CP_ROQ_THRESHOLDS__IB1_START_MASK                                                                     0x000000FFL
1111 #define CP_ROQ_THRESHOLDS__IB2_START_MASK                                                                     0x0000FF00L
1112 //CP_MEQ_STQ_THRESHOLD
1113 #define CP_MEQ_STQ_THRESHOLD__STQ_START__SHIFT                                                                0x0
1114 #define CP_MEQ_STQ_THRESHOLD__STQ_START_MASK                                                                  0x000000FFL
1115 //CP_RB2_RPTR
1116 #define CP_RB2_RPTR__RB_RPTR__SHIFT                                                                           0x0
1117 #define CP_RB2_RPTR__RB_RPTR_MASK                                                                             0x000FFFFFL
1118 //CP_RB1_RPTR
1119 #define CP_RB1_RPTR__RB_RPTR__SHIFT                                                                           0x0
1120 #define CP_RB1_RPTR__RB_RPTR_MASK                                                                             0x000FFFFFL
1121 //CP_RB0_RPTR
1122 #define CP_RB0_RPTR__RB_RPTR__SHIFT                                                                           0x0
1123 #define CP_RB0_RPTR__RB_RPTR_MASK                                                                             0x000FFFFFL
1124 //CP_RB_RPTR
1125 #define CP_RB_RPTR__RB_RPTR__SHIFT                                                                            0x0
1126 #define CP_RB_RPTR__RB_RPTR_MASK                                                                              0x000FFFFFL
1127 //CP_RB_WPTR_DELAY
1128 #define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT                                                              0x0
1129 #define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT                                                              0x1c
1130 #define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK                                                                0x0FFFFFFFL
1131 #define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK                                                                0xF0000000L
1132 //CP_RB_WPTR_POLL_CNTL
1133 #define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT                                                           0x0
1134 #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                          0x10
1135 #define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK                                                             0x0000FFFFL
1136 #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                            0xFFFF0000L
1137 //CP_ROQ1_THRESHOLDS
1138 #define CP_ROQ1_THRESHOLDS__RB1_START__SHIFT                                                                  0x0
1139 #define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT                                                                  0x8
1140 #define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT                                                               0x10
1141 #define CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT                                                               0x18
1142 #define CP_ROQ1_THRESHOLDS__RB1_START_MASK                                                                    0x000000FFL
1143 #define CP_ROQ1_THRESHOLDS__RB2_START_MASK                                                                    0x0000FF00L
1144 #define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK                                                                 0x00FF0000L
1145 #define CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK                                                                 0xFF000000L
1146 //CP_ROQ2_THRESHOLDS
1147 #define CP_ROQ2_THRESHOLDS__R2_IB1_START__SHIFT                                                               0x0
1148 #define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT                                                               0x8
1149 #define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT                                                               0x10
1150 #define CP_ROQ2_THRESHOLDS__R2_IB2_START__SHIFT                                                               0x18
1151 #define CP_ROQ2_THRESHOLDS__R2_IB1_START_MASK                                                                 0x000000FFL
1152 #define CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK                                                                 0x0000FF00L
1153 #define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK                                                                 0x00FF0000L
1154 #define CP_ROQ2_THRESHOLDS__R2_IB2_START_MASK                                                                 0xFF000000L
1155 //CP_STQ_THRESHOLDS
1156 #define CP_STQ_THRESHOLDS__STQ0_START__SHIFT                                                                  0x0
1157 #define CP_STQ_THRESHOLDS__STQ1_START__SHIFT                                                                  0x8
1158 #define CP_STQ_THRESHOLDS__STQ2_START__SHIFT                                                                  0x10
1159 #define CP_STQ_THRESHOLDS__STQ0_START_MASK                                                                    0x000000FFL
1160 #define CP_STQ_THRESHOLDS__STQ1_START_MASK                                                                    0x0000FF00L
1161 #define CP_STQ_THRESHOLDS__STQ2_START_MASK                                                                    0x00FF0000L
1162 //CP_QUEUE_THRESHOLDS
1163 #define CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT                                                             0x0
1164 #define CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT                                                             0x8
1165 #define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK                                                               0x0000003FL
1166 #define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK                                                               0x00003F00L
1167 //CP_MEQ_THRESHOLDS
1168 #define CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT                                                                  0x0
1169 #define CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT                                                                  0x8
1170 #define CP_MEQ_THRESHOLDS__MEQ1_START_MASK                                                                    0x000000FFL
1171 #define CP_MEQ_THRESHOLDS__MEQ2_START_MASK                                                                    0x0000FF00L
1172 //CP_ROQ_AVAIL
1173 #define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT                                                                     0x0
1174 #define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT                                                                      0x10
1175 #define CP_ROQ_AVAIL__ROQ_CNT_RING_MASK                                                                       0x000007FFL
1176 #define CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK                                                                        0x07FF0000L
1177 //CP_STQ_AVAIL
1178 #define CP_STQ_AVAIL__STQ_CNT__SHIFT                                                                          0x0
1179 #define CP_STQ_AVAIL__STQ_CNT_MASK                                                                            0x000001FFL
1180 //CP_ROQ2_AVAIL
1181 #define CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT                                                                     0x0
1182 #define CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK                                                                       0x000007FFL
1183 //CP_MEQ_AVAIL
1184 #define CP_MEQ_AVAIL__MEQ_CNT__SHIFT                                                                          0x0
1185 #define CP_MEQ_AVAIL__MEQ_CNT_MASK                                                                            0x000003FFL
1186 //CP_CMD_INDEX
1187 #define CP_CMD_INDEX__CMD_INDEX__SHIFT                                                                        0x0
1188 #define CP_CMD_INDEX__CMD_ME_SEL__SHIFT                                                                       0xc
1189 #define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT                                                                    0x10
1190 #define CP_CMD_INDEX__CMD_INDEX_MASK                                                                          0x000007FFL
1191 #define CP_CMD_INDEX__CMD_ME_SEL_MASK                                                                         0x00003000L
1192 #define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK                                                                      0x00070000L
1193 //CP_CMD_DATA
1194 #define CP_CMD_DATA__CMD_DATA__SHIFT                                                                          0x0
1195 #define CP_CMD_DATA__CMD_DATA_MASK                                                                            0xFFFFFFFFL
1196 //CP_ROQ_RB_STAT
1197 #define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT                                                               0x0
1198 #define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT                                                               0x10
1199 #define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK                                                                 0x000003FFL
1200 #define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK                                                                 0x03FF0000L
1201 //CP_ROQ_IB1_STAT
1202 #define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT                                                            0x0
1203 #define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT                                                            0x10
1204 #define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK                                                              0x000003FFL
1205 #define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK                                                              0x03FF0000L
1206 //CP_ROQ_IB2_STAT
1207 #define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT                                                            0x0
1208 #define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT                                                            0x10
1209 #define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK                                                              0x000003FFL
1210 #define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK                                                              0x03FF0000L
1211 //CP_STQ_STAT
1212 #define CP_STQ_STAT__STQ_RPTR__SHIFT                                                                          0x0
1213 #define CP_STQ_STAT__STQ_RPTR_MASK                                                                            0x000003FFL
1214 //CP_STQ_WR_STAT
1215 #define CP_STQ_WR_STAT__STQ_WPTR__SHIFT                                                                       0x0
1216 #define CP_STQ_WR_STAT__STQ_WPTR_MASK                                                                         0x000003FFL
1217 //CP_MEQ_STAT
1218 #define CP_MEQ_STAT__MEQ_RPTR__SHIFT                                                                          0x0
1219 #define CP_MEQ_STAT__MEQ_WPTR__SHIFT                                                                          0x10
1220 #define CP_MEQ_STAT__MEQ_RPTR_MASK                                                                            0x000003FFL
1221 #define CP_MEQ_STAT__MEQ_WPTR_MASK                                                                            0x03FF0000L
1222 //CP_CEQ1_AVAIL
1223 #define CP_CEQ1_AVAIL__CEQ_CNT_RING__SHIFT                                                                    0x0
1224 #define CP_CEQ1_AVAIL__CEQ_CNT_IB1__SHIFT                                                                     0x10
1225 #define CP_CEQ1_AVAIL__CEQ_CNT_RING_MASK                                                                      0x000007FFL
1226 #define CP_CEQ1_AVAIL__CEQ_CNT_IB1_MASK                                                                       0x07FF0000L
1227 //CP_CEQ2_AVAIL
1228 #define CP_CEQ2_AVAIL__CEQ_CNT_IB2__SHIFT                                                                     0x0
1229 #define CP_CEQ2_AVAIL__CEQ_CNT_IB2_MASK                                                                       0x000007FFL
1230 //CP_CE_ROQ_RB_STAT
1231 #define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT                                                            0x0
1232 #define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT                                                            0x10
1233 #define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY_MASK                                                              0x000003FFL
1234 #define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK                                                              0x03FF0000L
1235 //CP_CE_ROQ_IB1_STAT
1236 #define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1__SHIFT                                                         0x0
1237 #define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT                                                         0x10
1238 #define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1_MASK                                                           0x000003FFL
1239 #define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1_MASK                                                           0x03FF0000L
1240 //CP_CE_ROQ_IB2_STAT
1241 #define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2__SHIFT                                                         0x0
1242 #define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2__SHIFT                                                         0x10
1243 #define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2_MASK                                                           0x000003FFL
1244 #define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2_MASK                                                           0x03FF0000L
1245 //CP_INT_STAT_DEBUG
1246 #define CP_INT_STAT_DEBUG__CP_VM_DOORBELL_WR_INT_ASSERTED__SHIFT                                              0xb
1247 #define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT                                                   0xe
1248 #define CP_INT_STAT_DEBUG__GPF_INT_ASSERTED__SHIFT                                                            0x10
1249 #define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT                                               0x11
1250 #define CP_INT_STAT_DEBUG__CMP_BUSY_INT_ASSERTED__SHIFT                                                       0x12
1251 #define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED__SHIFT                                                      0x13
1252 #define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED__SHIFT                                                     0x14
1253 #define CP_INT_STAT_DEBUG__GFX_IDLE_INT_ASSERTED__SHIFT                                                       0x15
1254 #define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT                                                     0x16
1255 #define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT                                                       0x17
1256 #define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT                                                   0x18
1257 #define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT                                                     0x1a
1258 #define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT                                             0x1b
1259 #define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT                                                       0x1d
1260 #define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT                                                       0x1e
1261 #define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT                                                       0x1f
1262 #define CP_INT_STAT_DEBUG__CP_VM_DOORBELL_WR_INT_ASSERTED_MASK                                                0x00000800L
1263 #define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK                                                     0x00004000L
1264 #define CP_INT_STAT_DEBUG__GPF_INT_ASSERTED_MASK                                                              0x00010000L
1265 #define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK                                                 0x00020000L
1266 #define CP_INT_STAT_DEBUG__CMP_BUSY_INT_ASSERTED_MASK                                                         0x00040000L
1267 #define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED_MASK                                                        0x00080000L
1268 #define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED_MASK                                                       0x00100000L
1269 #define CP_INT_STAT_DEBUG__GFX_IDLE_INT_ASSERTED_MASK                                                         0x00200000L
1270 #define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK                                                       0x00400000L
1271 #define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK                                                         0x00800000L
1272 #define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK                                                     0x01000000L
1273 #define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK                                                       0x04000000L
1274 #define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK                                               0x08000000L
1275 #define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK                                                         0x20000000L
1276 #define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK                                                         0x40000000L
1277 #define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK                                                         0x80000000L
1278 //CP_DEBUG_CNTL
1279 #define CP_DEBUG_CNTL__DEBUG_INDX__SHIFT                                                                      0x0
1280 #define CP_DEBUG_CNTL__DEBUG_BUS_SELECT_BITS__SHIFT                                                           0x10
1281 #define CP_DEBUG_CNTL__DEBUG_BUS_FLOP_EN__SHIFT                                                               0x1f
1282 #define CP_DEBUG_CNTL__DEBUG_INDX_MASK                                                                        0x0000007FL
1283 #define CP_DEBUG_CNTL__DEBUG_BUS_SELECT_BITS_MASK                                                             0x003F0000L
1284 #define CP_DEBUG_CNTL__DEBUG_BUS_FLOP_EN_MASK                                                                 0x80000000L
1285 //CP_PRIV_VIOLATION_ADDR
1286 #define CP_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR__SHIFT                                                    0x0
1287 #define CP_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR_MASK                                                      0x0000FFFFL
1288 
1289 
1290 // addressBlock: xcd0_gc_padec
1291 //VGT_VTX_VECT_EJECT_REG
1292 #define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT                                                             0x0
1293 #define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK                                                               0x0000007FL
1294 //VGT_DMA_DATA_FIFO_DEPTH
1295 #define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH__SHIFT                                                   0x0
1296 #define VGT_DMA_DATA_FIFO_DEPTH__DMA2DRAW_FIFO_DEPTH__SHIFT                                                   0x9
1297 #define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH_MASK                                                     0x000001FFL
1298 #define VGT_DMA_DATA_FIFO_DEPTH__DMA2DRAW_FIFO_DEPTH_MASK                                                     0x0007FE00L
1299 //VGT_DMA_REQ_FIFO_DEPTH
1300 #define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH__SHIFT                                                     0x0
1301 #define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH_MASK                                                       0x0000003FL
1302 //VGT_DRAW_INIT_FIFO_DEPTH
1303 #define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH__SHIFT                                                 0x0
1304 #define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH_MASK                                                   0x0000003FL
1305 //VGT_LAST_COPY_STATE
1306 #define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT                                                              0x0
1307 #define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT                                                              0x10
1308 #define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK                                                                0x00000007L
1309 #define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK                                                                0x00070000L
1310 //VGT_CACHE_INVALIDATION
1311 #define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT                                                     0x0
1312 #define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT__SHIFT                                                     0x4
1313 #define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER__SHIFT                                                     0x5
1314 #define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT                                                          0x6
1315 #define VGT_CACHE_INVALIDATION__USE_GS_DONE__SHIFT                                                            0x9
1316 #define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD__SHIFT                                                   0xb
1317 #define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN__SHIFT                                                       0xc
1318 #define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH__SHIFT                                                   0xd
1319 #define VGT_CACHE_INVALIDATION__ES_LIMIT__SHIFT                                                               0x10
1320 #define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG__SHIFT                                                       0x15
1321 #define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1__SHIFT                                                        0x16
1322 #define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2__SHIFT                                                        0x19
1323 #define VGT_CACHE_INVALIDATION__EN_WAVE_MERGE__SHIFT                                                          0x1c
1324 #define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI__SHIFT                                                   0x1d
1325 #define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_MASK                                                       0x00000003L
1326 #define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT_MASK                                                       0x00000010L
1327 #define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER_MASK                                                       0x00000020L
1328 #define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN_MASK                                                            0x000000C0L
1329 #define VGT_CACHE_INVALIDATION__USE_GS_DONE_MASK                                                              0x00000200L
1330 #define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD_MASK                                                     0x00000800L
1331 #define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN_MASK                                                         0x00001000L
1332 #define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH_MASK                                                     0x00002000L
1333 #define VGT_CACHE_INVALIDATION__ES_LIMIT_MASK                                                                 0x001F0000L
1334 #define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_MASK                                                         0x00200000L
1335 #define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1_MASK                                                          0x01C00000L
1336 #define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2_MASK                                                          0x0E000000L
1337 #define VGT_CACHE_INVALIDATION__EN_WAVE_MERGE_MASK                                                            0x10000000L
1338 #define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI_MASK                                                     0x20000000L
1339 //VGT_RESET_DEBUG
1340 #define VGT_RESET_DEBUG__GS_DISABLE__SHIFT                                                                    0x0
1341 #define VGT_RESET_DEBUG__TESS_DISABLE__SHIFT                                                                  0x1
1342 #define VGT_RESET_DEBUG__WD_DISABLE__SHIFT                                                                    0x2
1343 #define VGT_RESET_DEBUG__GS_DISABLE_MASK                                                                      0x00000001L
1344 #define VGT_RESET_DEBUG__TESS_DISABLE_MASK                                                                    0x00000002L
1345 #define VGT_RESET_DEBUG__WD_DISABLE_MASK                                                                      0x00000004L
1346 //VGT_STRMOUT_DELAY
1347 #define VGT_STRMOUT_DELAY__SKIP_DELAY__SHIFT                                                                  0x0
1348 #define VGT_STRMOUT_DELAY__SE0_WD_DELAY__SHIFT                                                                0x8
1349 #define VGT_STRMOUT_DELAY__SE1_WD_DELAY__SHIFT                                                                0xb
1350 #define VGT_STRMOUT_DELAY__SE2_WD_DELAY__SHIFT                                                                0xe
1351 #define VGT_STRMOUT_DELAY__SE3_WD_DELAY__SHIFT                                                                0x11
1352 #define VGT_STRMOUT_DELAY__SKIP_DELAY_MASK                                                                    0x000000FFL
1353 #define VGT_STRMOUT_DELAY__SE0_WD_DELAY_MASK                                                                  0x00000700L
1354 #define VGT_STRMOUT_DELAY__SE1_WD_DELAY_MASK                                                                  0x00003800L
1355 #define VGT_STRMOUT_DELAY__SE2_WD_DELAY_MASK                                                                  0x0001C000L
1356 #define VGT_STRMOUT_DELAY__SE3_WD_DELAY_MASK                                                                  0x000E0000L
1357 //VGT_FIFO_DEPTHS
1358 #define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH__SHIFT                                                          0x0
1359 #define VGT_FIFO_DEPTHS__RESERVED_0__SHIFT                                                                    0x7
1360 #define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH__SHIFT                                                              0x8
1361 #define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH__SHIFT                                                            0x16
1362 #define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH_MASK                                                            0x0000007FL
1363 #define VGT_FIFO_DEPTHS__RESERVED_0_MASK                                                                      0x00000080L
1364 #define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH_MASK                                                                0x003FFF00L
1365 #define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH_MASK                                                              0x0FC00000L
1366 //VGT_GS_VERTEX_REUSE
1367 #define VGT_GS_VERTEX_REUSE__VERT_REUSE__SHIFT                                                                0x0
1368 #define VGT_GS_VERTEX_REUSE__VERT_REUSE_MASK                                                                  0x0000001FL
1369 //VGT_MC_LAT_CNTL
1370 #define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES__SHIFT                                                             0x0
1371 #define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES_MASK                                                               0x0000000FL
1372 //IA_CNTL_STATUS
1373 #define IA_CNTL_STATUS__IA_BUSY__SHIFT                                                                        0x0
1374 #define IA_CNTL_STATUS__IA_DMA_BUSY__SHIFT                                                                    0x1
1375 #define IA_CNTL_STATUS__IA_DMA_REQ_BUSY__SHIFT                                                                0x2
1376 #define IA_CNTL_STATUS__IA_GRP_BUSY__SHIFT                                                                    0x3
1377 #define IA_CNTL_STATUS__IA_ADC_BUSY__SHIFT                                                                    0x4
1378 #define IA_CNTL_STATUS__IA_BUSY_MASK                                                                          0x00000001L
1379 #define IA_CNTL_STATUS__IA_DMA_BUSY_MASK                                                                      0x00000002L
1380 #define IA_CNTL_STATUS__IA_DMA_REQ_BUSY_MASK                                                                  0x00000004L
1381 #define IA_CNTL_STATUS__IA_GRP_BUSY_MASK                                                                      0x00000008L
1382 #define IA_CNTL_STATUS__IA_ADC_BUSY_MASK                                                                      0x00000010L
1383 //VGT_CNTL_STATUS
1384 #define VGT_CNTL_STATUS__VGT_BUSY__SHIFT                                                                      0x0
1385 #define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT                                                             0x1
1386 #define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT                                                                  0x2
1387 #define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT                                                                   0x3
1388 #define VGT_CNTL_STATUS__VGT_TE_BUSY__SHIFT                                                                   0x4
1389 #define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT                                                                   0x5
1390 #define VGT_CNTL_STATUS__VGT_PI_BUSY__SHIFT                                                                   0x6
1391 #define VGT_CNTL_STATUS__VGT_GS_BUSY__SHIFT                                                                   0x7
1392 #define VGT_CNTL_STATUS__VGT_HS_BUSY__SHIFT                                                                   0x8
1393 #define VGT_CNTL_STATUS__VGT_TE11_BUSY__SHIFT                                                                 0x9
1394 #define VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY__SHIFT                                                              0xa
1395 #define VGT_CNTL_STATUS__VGT_BUSY_MASK                                                                        0x00000001L
1396 #define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK                                                               0x00000002L
1397 #define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK                                                                    0x00000004L
1398 #define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK                                                                     0x00000008L
1399 #define VGT_CNTL_STATUS__VGT_TE_BUSY_MASK                                                                     0x00000010L
1400 #define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK                                                                     0x00000020L
1401 #define VGT_CNTL_STATUS__VGT_PI_BUSY_MASK                                                                     0x00000040L
1402 #define VGT_CNTL_STATUS__VGT_GS_BUSY_MASK                                                                     0x00000080L
1403 #define VGT_CNTL_STATUS__VGT_HS_BUSY_MASK                                                                     0x00000100L
1404 #define VGT_CNTL_STATUS__VGT_TE11_BUSY_MASK                                                                   0x00000200L
1405 #define VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY_MASK                                                                0x00000400L
1406 //WD_CNTL_STATUS
1407 #define WD_CNTL_STATUS__WD_BUSY__SHIFT                                                                        0x0
1408 #define WD_CNTL_STATUS__WD_SPL_DMA_BUSY__SHIFT                                                                0x1
1409 #define WD_CNTL_STATUS__WD_SPL_DI_BUSY__SHIFT                                                                 0x2
1410 #define WD_CNTL_STATUS__WD_ADC_BUSY__SHIFT                                                                    0x3
1411 #define WD_CNTL_STATUS__WD_BUSY_MASK                                                                          0x00000001L
1412 #define WD_CNTL_STATUS__WD_SPL_DMA_BUSY_MASK                                                                  0x00000002L
1413 #define WD_CNTL_STATUS__WD_SPL_DI_BUSY_MASK                                                                   0x00000004L
1414 #define WD_CNTL_STATUS__WD_ADC_BUSY_MASK                                                                      0x00000008L
1415 //CC_GC_PRIM_CONFIG
1416 #define CC_GC_PRIM_CONFIG__WRITE_DIS__SHIFT                                                                   0x0
1417 #define CC_GC_PRIM_CONFIG__INACTIVE_IA__SHIFT                                                                 0x10
1418 #define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT                                                             0x18
1419 #define CC_GC_PRIM_CONFIG__WRITE_DIS_MASK                                                                     0x00000001L
1420 #define CC_GC_PRIM_CONFIG__INACTIVE_IA_MASK                                                                   0x00030000L
1421 #define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA_MASK                                                               0x0F000000L
1422 //GC_USER_PRIM_CONFIG
1423 #define GC_USER_PRIM_CONFIG__INACTIVE_IA__SHIFT                                                               0x10
1424 #define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT                                                           0x18
1425 #define GC_USER_PRIM_CONFIG__INACTIVE_IA_MASK                                                                 0x00030000L
1426 #define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA_MASK                                                             0x0F000000L
1427 //WD_QOS
1428 #define WD_QOS__DRAW_STALL__SHIFT                                                                             0x0
1429 #define WD_QOS__DRAW_STALL_MASK                                                                               0x00000001L
1430 //WD_UTCL1_CNTL
1431 #define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT                                                            0x0
1432 #define WD_UTCL1_CNTL__VMID_RESET_MODE__SHIFT                                                                 0x17
1433 #define WD_UTCL1_CNTL__DROP_MODE__SHIFT                                                                       0x18
1434 #define WD_UTCL1_CNTL__BYPASS__SHIFT                                                                          0x19
1435 #define WD_UTCL1_CNTL__INVALIDATE__SHIFT                                                                      0x1a
1436 #define WD_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT                                                                 0x1b
1437 #define WD_UTCL1_CNTL__FORCE_SNOOP__SHIFT                                                                     0x1c
1438 #define WD_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT                                                             0x1d
1439 #define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK                                                              0x000FFFFFL
1440 #define WD_UTCL1_CNTL__VMID_RESET_MODE_MASK                                                                   0x00800000L
1441 #define WD_UTCL1_CNTL__DROP_MODE_MASK                                                                         0x01000000L
1442 #define WD_UTCL1_CNTL__BYPASS_MASK                                                                            0x02000000L
1443 #define WD_UTCL1_CNTL__INVALIDATE_MASK                                                                        0x04000000L
1444 #define WD_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK                                                                   0x08000000L
1445 #define WD_UTCL1_CNTL__FORCE_SNOOP_MASK                                                                       0x10000000L
1446 #define WD_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK                                                               0x20000000L
1447 //WD_UTCL1_STATUS
1448 #define WD_UTCL1_STATUS__FAULT_DETECTED__SHIFT                                                                0x0
1449 #define WD_UTCL1_STATUS__RETRY_DETECTED__SHIFT                                                                0x1
1450 #define WD_UTCL1_STATUS__PRT_DETECTED__SHIFT                                                                  0x2
1451 #define WD_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT                                                                 0x8
1452 #define WD_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT                                                                 0x10
1453 #define WD_UTCL1_STATUS__PRT_UTCL1ID__SHIFT                                                                   0x18
1454 #define WD_UTCL1_STATUS__FAULT_DETECTED_MASK                                                                  0x00000001L
1455 #define WD_UTCL1_STATUS__RETRY_DETECTED_MASK                                                                  0x00000002L
1456 #define WD_UTCL1_STATUS__PRT_DETECTED_MASK                                                                    0x00000004L
1457 #define WD_UTCL1_STATUS__FAULT_UTCL1ID_MASK                                                                   0x00003F00L
1458 #define WD_UTCL1_STATUS__RETRY_UTCL1ID_MASK                                                                   0x003F0000L
1459 #define WD_UTCL1_STATUS__PRT_UTCL1ID_MASK                                                                     0x3F000000L
1460 //IA_UTCL1_CNTL
1461 #define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT                                                            0x0
1462 #define IA_UTCL1_CNTL__VMID_RESET_MODE__SHIFT                                                                 0x17
1463 #define IA_UTCL1_CNTL__DROP_MODE__SHIFT                                                                       0x18
1464 #define IA_UTCL1_CNTL__BYPASS__SHIFT                                                                          0x19
1465 #define IA_UTCL1_CNTL__INVALIDATE__SHIFT                                                                      0x1a
1466 #define IA_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT                                                                 0x1b
1467 #define IA_UTCL1_CNTL__FORCE_SNOOP__SHIFT                                                                     0x1c
1468 #define IA_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT                                                             0x1d
1469 #define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK                                                              0x000FFFFFL
1470 #define IA_UTCL1_CNTL__VMID_RESET_MODE_MASK                                                                   0x00800000L
1471 #define IA_UTCL1_CNTL__DROP_MODE_MASK                                                                         0x01000000L
1472 #define IA_UTCL1_CNTL__BYPASS_MASK                                                                            0x02000000L
1473 #define IA_UTCL1_CNTL__INVALIDATE_MASK                                                                        0x04000000L
1474 #define IA_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK                                                                   0x08000000L
1475 #define IA_UTCL1_CNTL__FORCE_SNOOP_MASK                                                                       0x10000000L
1476 #define IA_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK                                                               0x20000000L
1477 //IA_UTCL1_STATUS
1478 #define IA_UTCL1_STATUS__FAULT_DETECTED__SHIFT                                                                0x0
1479 #define IA_UTCL1_STATUS__RETRY_DETECTED__SHIFT                                                                0x1
1480 #define IA_UTCL1_STATUS__PRT_DETECTED__SHIFT                                                                  0x2
1481 #define IA_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT                                                                 0x8
1482 #define IA_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT                                                                 0x10
1483 #define IA_UTCL1_STATUS__PRT_UTCL1ID__SHIFT                                                                   0x18
1484 #define IA_UTCL1_STATUS__FAULT_DETECTED_MASK                                                                  0x00000001L
1485 #define IA_UTCL1_STATUS__RETRY_DETECTED_MASK                                                                  0x00000002L
1486 #define IA_UTCL1_STATUS__PRT_DETECTED_MASK                                                                    0x00000004L
1487 #define IA_UTCL1_STATUS__FAULT_UTCL1ID_MASK                                                                   0x00003F00L
1488 #define IA_UTCL1_STATUS__RETRY_UTCL1ID_MASK                                                                   0x003F0000L
1489 #define IA_UTCL1_STATUS__PRT_UTCL1ID_MASK                                                                     0x3F000000L
1490 //VGT_SYS_CONFIG
1491 #define VGT_SYS_CONFIG__DUAL_CORE_EN__SHIFT                                                                   0x0
1492 #define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP__SHIFT                                                               0x1
1493 #define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE__SHIFT                                                       0x7
1494 #define VGT_SYS_CONFIG__DUAL_CORE_EN_MASK                                                                     0x00000001L
1495 #define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP_MASK                                                                 0x0000007EL
1496 #define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE_MASK                                                         0x00000080L
1497 //VGT_VS_MAX_WAVE_ID
1498 #define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT                                                                0x0
1499 #define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID_MASK                                                                  0x00000FFFL
1500 //VGT_GS_MAX_WAVE_ID
1501 #define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT                                                                0x0
1502 #define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID_MASK                                                                  0x00000FFFL
1503 //GFX_PIPE_CONTROL
1504 #define GFX_PIPE_CONTROL__HYSTERESIS_CNT__SHIFT                                                               0x0
1505 #define GFX_PIPE_CONTROL__RESERVED__SHIFT                                                                     0xd
1506 #define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN__SHIFT                                                           0x10
1507 #define GFX_PIPE_CONTROL__HYSTERESIS_CNT_MASK                                                                 0x00001FFFL
1508 #define GFX_PIPE_CONTROL__RESERVED_MASK                                                                       0x0000E000L
1509 #define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN_MASK                                                             0x00010000L
1510 //CC_GC_SHADER_ARRAY_CONFIG
1511 #define CC_GC_SHADER_ARRAY_CONFIG__WRITE_DIS__SHIFT                                                           0x0
1512 #define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT                                                        0x10
1513 #define CC_GC_SHADER_ARRAY_CONFIG__WRITE_DIS_MASK                                                             0x00000001L
1514 #define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK                                                          0xFFFF0000L
1515 //GC_USER_SHADER_ARRAY_CONFIG
1516 #define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT                                                      0x10
1517 #define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK                                                        0xFFFF0000L
1518 //VGT_DMA_PRIMITIVE_TYPE
1519 #define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT                                                              0x0
1520 #define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE_MASK                                                                0x0000003FL
1521 //VGT_DMA_CONTROL
1522 #define VGT_DMA_CONTROL__PRIMGROUP_SIZE__SHIFT                                                                0x0
1523 #define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP__SHIFT                                                              0x11
1524 #define VGT_DMA_CONTROL__SWITCH_ON_EOI__SHIFT                                                                 0x13
1525 #define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP__SHIFT                                                              0x14
1526 #define VGT_DMA_CONTROL__EN_INST_OPT_BASIC__SHIFT                                                             0x15
1527 #define VGT_DMA_CONTROL__EN_INST_OPT_ADV__SHIFT                                                               0x16
1528 #define VGT_DMA_CONTROL__HW_USE_ONLY__SHIFT                                                                   0x17
1529 #define VGT_DMA_CONTROL__PRIMGROUP_SIZE_MASK                                                                  0x0000FFFFL
1530 #define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP_MASK                                                                0x00020000L
1531 #define VGT_DMA_CONTROL__SWITCH_ON_EOI_MASK                                                                   0x00080000L
1532 #define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP_MASK                                                                0x00100000L
1533 #define VGT_DMA_CONTROL__EN_INST_OPT_BASIC_MASK                                                               0x00200000L
1534 #define VGT_DMA_CONTROL__EN_INST_OPT_ADV_MASK                                                                 0x00400000L
1535 #define VGT_DMA_CONTROL__HW_USE_ONLY_MASK                                                                     0x00800000L
1536 //VGT_DMA_LS_HS_CONFIG
1537 #define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT                                                          0x8
1538 #define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK                                                            0x00003F00L
1539 //WD_BUF_RESOURCE_1
1540 #define WD_BUF_RESOURCE_1__POS_BUF_SIZE__SHIFT                                                                0x0
1541 #define WD_BUF_RESOURCE_1__INDEX_BUF_SIZE__SHIFT                                                              0x10
1542 #define WD_BUF_RESOURCE_1__POS_BUF_SIZE_MASK                                                                  0x0000FFFFL
1543 #define WD_BUF_RESOURCE_1__INDEX_BUF_SIZE_MASK                                                                0xFFFF0000L
1544 //WD_BUF_RESOURCE_2
1545 #define WD_BUF_RESOURCE_2__PARAM_BUF_SIZE__SHIFT                                                              0x0
1546 #define WD_BUF_RESOURCE_2__ADDR_MODE__SHIFT                                                                   0xf
1547 #define WD_BUF_RESOURCE_2__CNTL_SB_BUF_SIZE__SHIFT                                                            0x10
1548 #define WD_BUF_RESOURCE_2__PARAM_BUF_SIZE_MASK                                                                0x00001FFFL
1549 #define WD_BUF_RESOURCE_2__ADDR_MODE_MASK                                                                     0x00008000L
1550 #define WD_BUF_RESOURCE_2__CNTL_SB_BUF_SIZE_MASK                                                              0xFFFF0000L
1551 //PA_CL_CNTL_STATUS
1552 #define PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED__SHIFT                                                          0x0
1553 #define PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED__SHIFT                                                          0x1
1554 #define PA_CL_CNTL_STATUS__UTC_PRT_DETECTED__SHIFT                                                            0x2
1555 #define PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED_MASK                                                            0x00000001L
1556 #define PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED_MASK                                                            0x00000002L
1557 #define PA_CL_CNTL_STATUS__UTC_PRT_DETECTED_MASK                                                              0x00000004L
1558 //PA_CL_ENHANCE
1559 #define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT                                                            0x0
1560 #define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT                                                                    0x1
1561 #define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT                                                          0x3
1562 #define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT                                                             0x4
1563 #define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL__SHIFT                                                              0x5
1564 #define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET__SHIFT                                                           0x6
1565 #define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS__SHIFT                                                           0x7
1566 #define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC__SHIFT                                                                0x8
1567 #define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION__SHIFT                                                0x9
1568 #define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER__SHIFT                                                          0xb
1569 #define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH__SHIFT                                                       0xc
1570 #define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH__SHIFT                                                     0xe
1571 #define PA_CL_ENHANCE__PROG_NEAR_CLIP_PLANE_ENABLE__SHIFT                                                     0x11
1572 #define PA_CL_ENHANCE__OUTPUT_SWITCH_TO_LEGACY_EVENT__SHIFT                                                   0x12
1573 #define PA_CL_ENHANCE__NO_SWITCH_TO_LEGACY_AFTER_VMID_RESET__SHIFT                                            0x13
1574 #define PA_CL_ENHANCE__POLY_INNER_EDGE_FLAG_DISABLE__SHIFT                                                    0x14
1575 #define PA_CL_ENHANCE__TC_REQUEST_PERF_CNTR_ENABLE__SHIFT                                                     0x15
1576 #define PA_CL_ENHANCE__ECO_SPARE3__SHIFT                                                                      0x1c
1577 #define PA_CL_ENHANCE__ECO_SPARE2__SHIFT                                                                      0x1d
1578 #define PA_CL_ENHANCE__ECO_SPARE1__SHIFT                                                                      0x1e
1579 #define PA_CL_ENHANCE__ECO_SPARE0__SHIFT                                                                      0x1f
1580 #define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK                                                              0x00000001L
1581 #define PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK                                                                      0x00000006L
1582 #define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK                                                            0x00000008L
1583 #define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK                                                               0x00000010L
1584 #define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL_MASK                                                                0x00000020L
1585 #define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET_MASK                                                             0x00000040L
1586 #define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS_MASK                                                             0x00000080L
1587 #define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC_MASK                                                                  0x00000100L
1588 #define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION_MASK                                                  0x00000600L
1589 #define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER_MASK                                                            0x00000800L
1590 #define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH_MASK                                                         0x00003000L
1591 #define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH_MASK                                                       0x0001C000L
1592 #define PA_CL_ENHANCE__PROG_NEAR_CLIP_PLANE_ENABLE_MASK                                                       0x00020000L
1593 #define PA_CL_ENHANCE__OUTPUT_SWITCH_TO_LEGACY_EVENT_MASK                                                     0x00040000L
1594 #define PA_CL_ENHANCE__NO_SWITCH_TO_LEGACY_AFTER_VMID_RESET_MASK                                              0x00080000L
1595 #define PA_CL_ENHANCE__POLY_INNER_EDGE_FLAG_DISABLE_MASK                                                      0x00100000L
1596 #define PA_CL_ENHANCE__TC_REQUEST_PERF_CNTR_ENABLE_MASK                                                       0x00200000L
1597 #define PA_CL_ENHANCE__ECO_SPARE3_MASK                                                                        0x10000000L
1598 #define PA_CL_ENHANCE__ECO_SPARE2_MASK                                                                        0x20000000L
1599 #define PA_CL_ENHANCE__ECO_SPARE1_MASK                                                                        0x40000000L
1600 #define PA_CL_ENHANCE__ECO_SPARE0_MASK                                                                        0x80000000L
1601 //PA_CL_RESET_DEBUG
1602 #define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE__SHIFT                                                        0x0
1603 #define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE_MASK                                                          0x00000001L
1604 //PA_SU_CNTL_STATUS
1605 #define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT                                                                     0x1f
1606 #define PA_SU_CNTL_STATUS__SU_BUSY_MASK                                                                       0x80000000L
1607 //PA_SC_FIFO_DEPTH_CNTL
1608 #define PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT                                                                   0x0
1609 #define PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK                                                                     0x000003FFL
1610 //PA_SC_P3D_TRAP_SCREEN_HV_LOCK
1611 #define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT                                         0x0
1612 #define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK                                           0x00000001L
1613 //PA_SC_HP3D_TRAP_SCREEN_HV_LOCK
1614 #define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT                                        0x0
1615 #define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK                                          0x00000001L
1616 //PA_SC_TRAP_SCREEN_HV_LOCK
1617 #define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT                                             0x0
1618 #define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK                                               0x00000001L
1619 //PA_SC_FORCE_EOV_MAX_CNTS
1620 #define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT                                                0x0
1621 #define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT                                                0x10
1622 #define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK                                                  0x0000FFFFL
1623 #define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK                                                  0xFFFF0000L
1624 //PA_SC_BINNER_EVENT_CNTL_0
1625 #define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0__SHIFT                                                          0x0
1626 #define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1__SHIFT                                              0x2
1627 #define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2__SHIFT                                              0x4
1628 #define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3__SHIFT                                              0x6
1629 #define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS__SHIFT                                                      0x8
1630 #define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE__SHIFT                                                        0xa
1631 #define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH__SHIFT                                                         0xc
1632 #define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH__SHIFT                                                    0xe
1633 #define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC__SHIFT                                                  0x10
1634 #define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9__SHIFT                                                          0x12
1635 #define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET__SHIFT                                                 0x14
1636 #define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE__SHIFT                                                 0x16
1637 #define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END__SHIFT                                                  0x18
1638 #define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT__SHIFT                                                         0x1a
1639 #define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH__SHIFT                                                         0x1c
1640 #define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH__SHIFT                                                    0x1e
1641 #define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0_MASK                                                            0x00000003L
1642 #define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1_MASK                                                0x0000000CL
1643 #define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2_MASK                                                0x00000030L
1644 #define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3_MASK                                                0x000000C0L
1645 #define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS_MASK                                                        0x00000300L
1646 #define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE_MASK                                                          0x00000C00L
1647 #define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_MASK                                                           0x00003000L
1648 #define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH_MASK                                                      0x0000C000L
1649 #define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC_MASK                                                    0x00030000L
1650 #define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9_MASK                                                            0x000C0000L
1651 #define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET_MASK                                                   0x00300000L
1652 #define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE_MASK                                                   0x00C00000L
1653 #define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END_MASK                                                    0x03000000L
1654 #define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT_MASK                                                           0x0C000000L
1655 #define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH_MASK                                                           0x30000000L
1656 #define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH_MASK                                                      0xC0000000L
1657 //PA_SC_BINNER_EVENT_CNTL_1
1658 #define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH__SHIFT                                                    0x0
1659 #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT__SHIFT                                                     0x2
1660 #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM__SHIFT                                                          0x4
1661 #define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT__SHIFT                                                 0x6
1662 #define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT__SHIFT                                        0x8
1663 #define PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE__SHIFT                                                          0xa
1664 #define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT__SHIFT                                           0xc
1665 #define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START__SHIFT                                                   0xe
1666 #define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP__SHIFT                                                    0x10
1667 #define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START__SHIFT                                                  0x12
1668 #define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP__SHIFT                                                   0x14
1669 #define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE__SHIFT                                                  0x16
1670 #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT__SHIFT                                                     0x18
1671 #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_GS_OUTPUT__SHIFT                                                     0x1a
1672 #define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT__SHIFT                                                 0x1c
1673 #define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH__SHIFT                                               0x1e
1674 #define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH_MASK                                                      0x00000003L
1675 #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT_MASK                                                       0x0000000CL
1676 #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM_MASK                                                            0x00000030L
1677 #define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT_MASK                                                   0x000000C0L
1678 #define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT_MASK                                          0x00000300L
1679 #define PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE_MASK                                                            0x00000C00L
1680 #define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT_MASK                                             0x00003000L
1681 #define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START_MASK                                                     0x0000C000L
1682 #define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP_MASK                                                      0x00030000L
1683 #define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START_MASK                                                    0x000C0000L
1684 #define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP_MASK                                                     0x00300000L
1685 #define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE_MASK                                                    0x00C00000L
1686 #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT_MASK                                                       0x03000000L
1687 #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_GS_OUTPUT_MASK                                                       0x0C000000L
1688 #define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT_MASK                                                   0x30000000L
1689 #define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH_MASK                                                 0xC0000000L
1690 //PA_SC_BINNER_EVENT_CNTL_2
1691 #define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS__SHIFT                                               0x0
1692 #define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT__SHIFT                                                       0x2
1693 #define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE__SHIFT                                                  0x4
1694 #define PA_SC_BINNER_EVENT_CNTL_2__CS_CONTEXT_DONE__SHIFT                                                     0x6
1695 #define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH__SHIFT                                                           0x8
1696 #define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER__SHIFT                                                       0xa
1697 #define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT__SHIFT                                                        0xc
1698 #define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ__SHIFT                                                      0xe
1699 #define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS__SHIFT                                                   0x10
1700 #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_SX_TS__SHIFT                                                         0x12
1701 #define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV__SHIFT                                              0x14
1702 #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS__SHIFT                                            0x16
1703 #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META__SHIFT                                               0x18
1704 #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS__SHIFT                                            0x1a
1705 #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META__SHIFT                                               0x1c
1706 #define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE__SHIFT                                                             0x1e
1707 #define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS_MASK                                                 0x00000003L
1708 #define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT_MASK                                                         0x0000000CL
1709 #define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE_MASK                                                    0x00000030L
1710 #define PA_SC_BINNER_EVENT_CNTL_2__CS_CONTEXT_DONE_MASK                                                       0x000000C0L
1711 #define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH_MASK                                                             0x00000300L
1712 #define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER_MASK                                                         0x00000C00L
1713 #define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT_MASK                                                          0x00003000L
1714 #define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ_MASK                                                        0x0000C000L
1715 #define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS_MASK                                                     0x00030000L
1716 #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_SX_TS_MASK                                                           0x000C0000L
1717 #define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV_MASK                                                0x00300000L
1718 #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS_MASK                                              0x00C00000L
1719 #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META_MASK                                                 0x03000000L
1720 #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS_MASK                                              0x0C000000L
1721 #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META_MASK                                                 0x30000000L
1722 #define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE_MASK                                                               0xC0000000L
1723 //PA_SC_BINNER_EVENT_CNTL_3
1724 #define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE__SHIFT                                                             0x0
1725 #define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA__SHIFT                                         0x2
1726 #define PA_SC_BINNER_EVENT_CNTL_3__SX_CB_RAT_ACK_REQUEST__SHIFT                                               0x4
1727 #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START__SHIFT                                                  0x6
1728 #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP__SHIFT                                                   0x8
1729 #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER__SHIFT                                                 0xa
1730 #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FLUSH__SHIFT                                                  0xc
1731 #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH__SHIFT                                                 0xe
1732 #define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL__SHIFT                                             0x10
1733 #define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP__SHIFT                                                0x12
1734 #define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET__SHIFT                                               0x14
1735 #define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND__SHIFT                                                     0x16
1736 #define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC__SHIFT                                                  0x18
1737 #define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE__SHIFT                                                 0x1a
1738 #define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE__SHIFT                                              0x1c
1739 #define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_63__SHIFT                                                         0x1e
1740 #define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE_MASK                                                               0x00000003L
1741 #define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA_MASK                                           0x0000000CL
1742 #define PA_SC_BINNER_EVENT_CNTL_3__SX_CB_RAT_ACK_REQUEST_MASK                                                 0x00000030L
1743 #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START_MASK                                                    0x000000C0L
1744 #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP_MASK                                                     0x00000300L
1745 #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER_MASK                                                   0x00000C00L
1746 #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FLUSH_MASK                                                    0x00003000L
1747 #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH_MASK                                                   0x0000C000L
1748 #define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL_MASK                                               0x00030000L
1749 #define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP_MASK                                                  0x000C0000L
1750 #define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET_MASK                                                 0x00300000L
1751 #define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND_MASK                                                       0x00C00000L
1752 #define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC_MASK                                                    0x03000000L
1753 #define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE_MASK                                                   0x0C000000L
1754 #define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE_MASK                                                0x30000000L
1755 #define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_63_MASK                                                           0xC0000000L
1756 //PA_SC_BINNER_TIMEOUT_COUNTER
1757 #define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD__SHIFT                                                        0x0
1758 #define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD_MASK                                                          0xFFFFFFFFL
1759 //PA_SC_BINNER_PERF_CNTL_0
1760 #define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD__SHIFT                                         0x0
1761 #define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD__SHIFT                                       0xa
1762 #define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD__SHIFT                                       0x14
1763 #define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD__SHIFT                                     0x17
1764 #define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD_MASK                                           0x000003FFL
1765 #define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD_MASK                                         0x000FFC00L
1766 #define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD_MASK                                         0x00700000L
1767 #define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD_MASK                                       0x03800000L
1768 //PA_SC_BINNER_PERF_CNTL_1
1769 #define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT                              0x0
1770 #define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT                            0x5
1771 #define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD__SHIFT                         0xa
1772 #define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK                                0x0000001FL
1773 #define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK                              0x000003E0L
1774 #define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD_MASK                           0x03FFFC00L
1775 //PA_SC_BINNER_PERF_CNTL_2
1776 #define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD__SHIFT                               0x0
1777 #define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD__SHIFT                             0xb
1778 #define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD_MASK                                 0x000007FFL
1779 #define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD_MASK                               0x003FF800L
1780 //PA_SC_BINNER_PERF_CNTL_3
1781 #define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD__SHIFT                              0x0
1782 #define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD_MASK                                0xFFFFFFFFL
1783 //PA_SC_ENHANCE_2
1784 #define PA_SC_ENHANCE_2__RESERVED_0__SHIFT                                                                    0x0
1785 #define PA_SC_ENHANCE_2__RESERVED_1__SHIFT                                                                    0x1
1786 #define PA_SC_ENHANCE_2__RESERVED_2__SHIFT                                                                    0x2
1787 #define PA_SC_ENHANCE_2__RESERVED_3__SHIFT                                                                    0x3
1788 #define PA_SC_ENHANCE_2__RESERVED_4__SHIFT                                                                    0x4
1789 #define PA_SC_ENHANCE_2__RESERVED_5__SHIFT                                                                    0x5
1790 #define PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_COMPOUND_INDEX_EN__SHIFT                                   0x6
1791 #define PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_EN_PIPELINE_PRIMID__SHIFT                                  0x7
1792 #define PA_SC_ENHANCE_2__RSVD__SHIFT                                                                          0x8
1793 #define PA_SC_ENHANCE_2__RESERVED_0_MASK                                                                      0x00000001L
1794 #define PA_SC_ENHANCE_2__RESERVED_1_MASK                                                                      0x00000002L
1795 #define PA_SC_ENHANCE_2__RESERVED_2_MASK                                                                      0x00000004L
1796 #define PA_SC_ENHANCE_2__RESERVED_3_MASK                                                                      0x00000008L
1797 #define PA_SC_ENHANCE_2__RESERVED_4_MASK                                                                      0x00000010L
1798 #define PA_SC_ENHANCE_2__RESERVED_5_MASK                                                                      0x00000020L
1799 #define PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_COMPOUND_INDEX_EN_MASK                                     0x00000040L
1800 #define PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_EN_PIPELINE_PRIMID_MASK                                    0x00000080L
1801 #define PA_SC_ENHANCE_2__RSVD_MASK                                                                            0xFFFFFF00L
1802 //PA_SC_FIFO_SIZE
1803 #define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT                                                    0x0
1804 #define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT                                                     0x6
1805 #define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT                                                         0xf
1806 #define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT                                                      0x15
1807 #define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK                                                      0x0000003FL
1808 #define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK                                                       0x00007FC0L
1809 #define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK                                                           0x001F8000L
1810 #define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK                                                        0xFFE00000L
1811 //PA_SC_IF_FIFO_SIZE
1812 #define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT                                                    0x0
1813 #define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT                                                    0x6
1814 #define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT                                                        0xc
1815 #define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT                                                        0x12
1816 #define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK                                                      0x0000003FL
1817 #define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK                                                      0x00000FC0L
1818 #define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK                                                          0x0003F000L
1819 #define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK                                                          0x00FC0000L
1820 //PA_SC_PKR_WAVE_TABLE_CNTL
1821 #define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE__SHIFT                                                                0x0
1822 #define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE_MASK                                                                  0x0000003FL
1823 //PA_UTCL1_CNTL1
1824 #define PA_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT                                                               0x0
1825 #define PA_UTCL1_CNTL1__GPUVM_64K_DEFAULT__SHIFT                                                              0x1
1826 #define PA_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT                                                                0x2
1827 #define PA_UTCL1_CNTL1__RESP_MODE__SHIFT                                                                      0x3
1828 #define PA_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT                                                                0x5
1829 #define PA_UTCL1_CNTL1__CLIENTID__SHIFT                                                                       0x7
1830 #define PA_UTCL1_CNTL1__SPARE__SHIFT                                                                          0x10
1831 #define PA_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT                                                              0x11
1832 #define PA_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT                                                           0x12
1833 #define PA_UTCL1_CNTL1__REG_INV_VMID__SHIFT                                                                   0x13
1834 #define PA_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT                                                               0x17
1835 #define PA_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT                                                                 0x18
1836 #define PA_UTCL1_CNTL1__INVALIDATE_ALL_VMID__SHIFT                                                            0x19
1837 #define PA_UTCL1_CNTL1__FORCE_MISS__SHIFT                                                                     0x1a
1838 #define PA_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT                                                                 0x1b
1839 #define PA_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT                                                         0x1c
1840 #define PA_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT                                                         0x1e
1841 #define PA_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK                                                                 0x00000001L
1842 #define PA_UTCL1_CNTL1__GPUVM_64K_DEFAULT_MASK                                                                0x00000002L
1843 #define PA_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK                                                                  0x00000004L
1844 #define PA_UTCL1_CNTL1__RESP_MODE_MASK                                                                        0x00000018L
1845 #define PA_UTCL1_CNTL1__RESP_FAULT_MODE_MASK                                                                  0x00000060L
1846 #define PA_UTCL1_CNTL1__CLIENTID_MASK                                                                         0x0000FF80L
1847 #define PA_UTCL1_CNTL1__SPARE_MASK                                                                            0x00010000L
1848 #define PA_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK                                                                0x00020000L
1849 #define PA_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK                                                             0x00040000L
1850 #define PA_UTCL1_CNTL1__REG_INV_VMID_MASK                                                                     0x00780000L
1851 #define PA_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK                                                                 0x00800000L
1852 #define PA_UTCL1_CNTL1__REG_INV_TOGGLE_MASK                                                                   0x01000000L
1853 #define PA_UTCL1_CNTL1__INVALIDATE_ALL_VMID_MASK                                                              0x02000000L
1854 #define PA_UTCL1_CNTL1__FORCE_MISS_MASK                                                                       0x04000000L
1855 #define PA_UTCL1_CNTL1__FORCE_IN_ORDER_MASK                                                                   0x08000000L
1856 #define PA_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK                                                           0x30000000L
1857 #define PA_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK                                                           0xC0000000L
1858 //PA_UTCL1_CNTL2
1859 #define PA_UTCL1_CNTL2__SPARE1__SHIFT                                                                         0x0
1860 #define PA_UTCL1_CNTL2__SPARE2__SHIFT                                                                         0x8
1861 #define PA_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT                                                                 0x9
1862 #define PA_UTCL1_CNTL2__LINE_VALID__SHIFT                                                                     0xa
1863 #define PA_UTCL1_CNTL2__SPARE3__SHIFT                                                                         0xb
1864 #define PA_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT                                                                 0xc
1865 #define PA_UTCL1_CNTL2__ENABLE_SHOOTDOWN_OPT__SHIFT                                                           0xd
1866 #define PA_UTCL1_CNTL2__FORCE_SNOOP__SHIFT                                                                    0xe
1867 #define PA_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT                                                            0xf
1868 #define PA_UTCL1_CNTL2__SPARE4__SHIFT                                                                         0x10
1869 #define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT                                                        0x12
1870 #define PA_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT                                                               0x13
1871 #define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT                                                         0x14
1872 #define PA_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT                                                                0x15
1873 #define PA_UTCL1_CNTL2__SPARE5__SHIFT                                                                         0x19
1874 #define PA_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT                                                           0x1a
1875 #define PA_UTCL1_CNTL2__RESERVED__SHIFT                                                                       0x1b
1876 #define PA_UTCL1_CNTL2__SPARE1_MASK                                                                           0x000000FFL
1877 #define PA_UTCL1_CNTL2__SPARE2_MASK                                                                           0x00000100L
1878 #define PA_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK                                                                   0x00000200L
1879 #define PA_UTCL1_CNTL2__LINE_VALID_MASK                                                                       0x00000400L
1880 #define PA_UTCL1_CNTL2__SPARE3_MASK                                                                           0x00000800L
1881 #define PA_UTCL1_CNTL2__GPUVM_INV_MODE_MASK                                                                   0x00001000L
1882 #define PA_UTCL1_CNTL2__ENABLE_SHOOTDOWN_OPT_MASK                                                             0x00002000L
1883 #define PA_UTCL1_CNTL2__FORCE_SNOOP_MASK                                                                      0x00004000L
1884 #define PA_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK                                                              0x00008000L
1885 #define PA_UTCL1_CNTL2__SPARE4_MASK                                                                           0x00030000L
1886 #define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK                                                          0x00040000L
1887 #define PA_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK                                                                 0x00080000L
1888 #define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK                                                           0x00100000L
1889 #define PA_UTCL1_CNTL2__PERF_EVENT_VMID_MASK                                                                  0x01E00000L
1890 #define PA_UTCL1_CNTL2__SPARE5_MASK                                                                           0x02000000L
1891 #define PA_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK                                                             0x04000000L
1892 #define PA_UTCL1_CNTL2__RESERVED_MASK                                                                         0xF8000000L
1893 //PA_SIDEBAND_REQUEST_DELAYS
1894 #define PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY__SHIFT                                                        0x0
1895 #define PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY__SHIFT                                                      0x10
1896 #define PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY_MASK                                                          0x0000FFFFL
1897 #define PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY_MASK                                                        0xFFFF0000L
1898 //PA_SC_ENHANCE
1899 #define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT                                                       0x0
1900 #define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT                                                          0x1
1901 #define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT                                                        0x2
1902 #define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT                                                  0x3
1903 #define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT                                               0x4
1904 #define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT                                                             0x5
1905 #define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT                                                     0x6
1906 #define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT                                              0x7
1907 #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT                                                   0x8
1908 #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT                                              0x9
1909 #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT                                                   0xa
1910 #define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT                                                          0xb
1911 #define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT                                          0xc
1912 #define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT                                                 0xd
1913 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT                                             0xe
1914 #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT                                                   0xf
1915 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT                                   0x10
1916 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT                                        0x11
1917 #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT                               0x12
1918 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT                               0x13
1919 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT                              0x14
1920 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT                                 0x15
1921 #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT                                   0x16
1922 #define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO__SHIFT                           0x17
1923 #define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT                                          0x18
1924 #define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING__SHIFT                                       0x19
1925 #define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET__SHIFT                                                  0x1a
1926 #define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET__SHIFT                                              0x1b
1927 #define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE__SHIFT                      0x1c
1928 #define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING__SHIFT                              0x1d
1929 #define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK                                                         0x00000001L
1930 #define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK                                                            0x00000002L
1931 #define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK                                                          0x00000004L
1932 #define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK                                                    0x00000008L
1933 #define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK                                                 0x00000010L
1934 #define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK                                                               0x00000020L
1935 #define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK                                                       0x00000040L
1936 #define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK                                                0x00000080L
1937 #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK                                                     0x00000100L
1938 #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK                                                0x00000200L
1939 #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK                                                     0x00000400L
1940 #define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK                                                            0x00000800L
1941 #define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK                                            0x00001000L
1942 #define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK                                                   0x00002000L
1943 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK                                               0x00004000L
1944 #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK                                                     0x00008000L
1945 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK                                     0x00010000L
1946 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK                                          0x00020000L
1947 #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK                                 0x00040000L
1948 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK                                 0x00080000L
1949 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK                                0x00100000L
1950 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK                                   0x00200000L
1951 #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK                                     0x00400000L
1952 #define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO_MASK                             0x00800000L
1953 #define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK                                            0x01000000L
1954 #define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING_MASK                                         0x02000000L
1955 #define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET_MASK                                                    0x04000000L
1956 #define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET_MASK                                                0x08000000L
1957 #define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE_MASK                        0x10000000L
1958 #define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING_MASK                                0x20000000L
1959 //PA_SC_ENHANCE_1
1960 #define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE__SHIFT                                                0x0
1961 #define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE__SHIFT                                                       0x1
1962 #define PA_SC_ENHANCE_1__DISABLE_SC_BINNING__SHIFT                                                            0x3
1963 #define PA_SC_ENHANCE_1__BYPASS_PBB__SHIFT                                                                    0x4
1964 #define PA_SC_ENHANCE_1__ECO_SPARE0__SHIFT                                                                    0x5
1965 #define PA_SC_ENHANCE_1__ECO_SPARE1__SHIFT                                                                    0x6
1966 #define PA_SC_ENHANCE_1__ECO_SPARE2__SHIFT                                                                    0x7
1967 #define PA_SC_ENHANCE_1__ECO_SPARE3__SHIFT                                                                    0x8
1968 #define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB__SHIFT                                                  0x9
1969 #define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT__SHIFT                                                       0xa
1970 #define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM__SHIFT                                     0xb
1971 #define PA_SC_ENHANCE_1__DEBUG_PIXEL_PICKER_XY_UNPACK__SHIFT                                                  0xc
1972 #define PA_SC_ENHANCE_1__DISABLE_PACKER_GRAD_FDCE_ENHANCE__SHIFT                                              0xd
1973 #define PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE__SHIFT                                       0xe
1974 #define PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION__SHIFT                              0xf
1975 #define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE__SHIFT                                                    0x10
1976 #define PA_SC_ENHANCE_1__ALLOW_SCALE_LINE_WIDTH_PAD_WITH_BINNING__SHIFT                                       0x11
1977 #define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION__SHIFT                                                         0x12
1978 #define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS__SHIFT                                                  0x13
1979 #define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION__SHIFT                                                  0x14
1980 #define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION__SHIFT                                          0x15
1981 #define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION__SHIFT                                          0x16
1982 #define PA_SC_ENHANCE_1__DISABLE_INTF_CG__SHIFT                                                               0x17
1983 #define PA_SC_ENHANCE_1__IOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT                                        0x18
1984 #define PA_SC_ENHANCE_1__DISABLE_SHADER_PROFILING_FOR_POWER__SHIFT                                            0x19
1985 #define PA_SC_ENHANCE_1__FLUSH_ON_BINNING_TRANSITION__SHIFT                                                   0x1a
1986 #define PA_SC_ENHANCE_1__DISABLE_QUAD_PROC_FDCE_ENHANCE__SHIFT                                                0x1b
1987 #define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX__SHIFT                                                  0x1c
1988 #define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_1__SHIFT                                                0x1d
1989 #define PA_SC_ENHANCE_1__PASS_VPZ_EVENT_TO_SPI__SHIFT                                                         0x1e
1990 #define PA_SC_ENHANCE_1__RSVD__SHIFT                                                                          0x1f
1991 #define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE_MASK                                                  0x00000001L
1992 #define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_MASK                                                         0x00000006L
1993 #define PA_SC_ENHANCE_1__DISABLE_SC_BINNING_MASK                                                              0x00000008L
1994 #define PA_SC_ENHANCE_1__BYPASS_PBB_MASK                                                                      0x00000010L
1995 #define PA_SC_ENHANCE_1__ECO_SPARE0_MASK                                                                      0x00000020L
1996 #define PA_SC_ENHANCE_1__ECO_SPARE1_MASK                                                                      0x00000040L
1997 #define PA_SC_ENHANCE_1__ECO_SPARE2_MASK                                                                      0x00000080L
1998 #define PA_SC_ENHANCE_1__ECO_SPARE3_MASK                                                                      0x00000100L
1999 #define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB_MASK                                                    0x00000200L
2000 #define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT_MASK                                                         0x00000400L
2001 #define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM_MASK                                       0x00000800L
2002 #define PA_SC_ENHANCE_1__DEBUG_PIXEL_PICKER_XY_UNPACK_MASK                                                    0x00001000L
2003 #define PA_SC_ENHANCE_1__DISABLE_PACKER_GRAD_FDCE_ENHANCE_MASK                                                0x00002000L
2004 #define PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE_MASK                                         0x00004000L
2005 #define PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION_MASK                                0x00008000L
2006 #define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE_MASK                                                      0x00010000L
2007 #define PA_SC_ENHANCE_1__ALLOW_SCALE_LINE_WIDTH_PAD_WITH_BINNING_MASK                                         0x00020000L
2008 #define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION_MASK                                                           0x00040000L
2009 #define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS_MASK                                                    0x00080000L
2010 #define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION_MASK                                                    0x00100000L
2011 #define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION_MASK                                            0x00200000L
2012 #define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION_MASK                                            0x00400000L
2013 #define PA_SC_ENHANCE_1__DISABLE_INTF_CG_MASK                                                                 0x00800000L
2014 #define PA_SC_ENHANCE_1__IOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK                                          0x01000000L
2015 #define PA_SC_ENHANCE_1__DISABLE_SHADER_PROFILING_FOR_POWER_MASK                                              0x02000000L
2016 #define PA_SC_ENHANCE_1__FLUSH_ON_BINNING_TRANSITION_MASK                                                     0x04000000L
2017 #define PA_SC_ENHANCE_1__DISABLE_QUAD_PROC_FDCE_ENHANCE_MASK                                                  0x08000000L
2018 #define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_MASK                                                    0x10000000L
2019 #define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_1_MASK                                                  0x20000000L
2020 #define PA_SC_ENHANCE_1__PASS_VPZ_EVENT_TO_SPI_MASK                                                           0x40000000L
2021 #define PA_SC_ENHANCE_1__RSVD_MASK                                                                            0x80000000L
2022 //PA_SC_DSM_CNTL
2023 #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT                                                                0x0
2024 #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1__SHIFT                                                                0x1
2025 #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0_MASK                                                                  0x00000001L
2026 #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1_MASK                                                                  0x00000002L
2027 //PA_SC_TILE_STEERING_CREST_OVERRIDE
2028 #define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE__SHIFT                                         0x0
2029 #define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT__SHIFT                                                  0x1
2030 #define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT__SHIFT                                                  0x5
2031 #define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE_MASK                                           0x00000001L
2032 #define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT_MASK                                                    0x00000006L
2033 #define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT_MASK                                                    0x00000060L
2034 
2035 
2036 // addressBlock: xcd0_gc_sqdec
2037 //SQ_CONFIG
2038 #define SQ_CONFIG__DISABLE_BARRIER_WAITCNT__SHIFT                                                             0x0
2039 #define SQ_CONFIG__DISABLE_REPEATER_FGCG_CLOCK_GATING__SHIFT                                                  0x1
2040 #define SQ_CONFIG__DISABLE_SPIPRIO_OVER_USERPRIO__SHIFT                                                       0x2
2041 #define SQ_CONFIG__OVERRIDE_SP_MAI_ALU_BUSY__SHIFT                                                            0x3
2042 #define SQ_CONFIG__DISABLE_RAM_CLOCK_GATING__SHIFT                                                            0x4
2043 #define SQ_CONFIG__DISABLE_MAI_CO_EXEC__SHIFT                                                                 0x5
2044 #define SQ_CONFIG__OVERRIDE_MAI_ALU_BUSY__SHIFT                                                               0x6
2045 #define SQ_CONFIG__OVERRIDE_ALU_BUSY__SHIFT                                                                   0x7
2046 #define SQ_CONFIG__DEBUG_EN__SHIFT                                                                            0x8
2047 #define SQ_CONFIG__DEBUG_SINGLE_MEMOP__SHIFT                                                                  0x9
2048 #define SQ_CONFIG__DEBUG_ONE_INST_CLAUSE__SHIFT                                                               0xa
2049 #define SQ_CONFIG__OVERRIDE_LDS_IDX_BUSY__SHIFT                                                               0xb
2050 #define SQ_CONFIG__EARLY_TA_DONE_DISABLE__SHIFT                                                               0xc
2051 #define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE__SHIFT                                                                0xd
2052 #define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE__SHIFT                                                              0xe
2053 #define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE__SHIFT                                                       0xf
2054 #define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE__SHIFT                                                            0x10
2055 #define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE__SHIFT                                                            0x11
2056 #define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS__SHIFT                                                         0x12
2057 #define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS__SHIFT                                                              0x13
2058 #define SQ_CONFIG__REPLAY_SLEEP_CNT__SHIFT                                                                    0x15
2059 #define SQ_CONFIG__DISABLE_SP_VGPR_WRITE_SKIP__SHIFT                                                          0x1c
2060 #define SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING__SHIFT                                                  0x1d
2061 #define SQ_CONFIG__DISABLE_FLAT_SOFT_CLAUSE__SHIFT                                                            0x1e
2062 #define SQ_CONFIG__DISABLE_MIMG_SOFT_CLAUSE__SHIFT                                                            0x1f
2063 #define SQ_CONFIG__DISABLE_BARRIER_WAITCNT_MASK                                                               0x00000001L
2064 #define SQ_CONFIG__DISABLE_REPEATER_FGCG_CLOCK_GATING_MASK                                                    0x00000002L
2065 #define SQ_CONFIG__DISABLE_SPIPRIO_OVER_USERPRIO_MASK                                                         0x00000004L
2066 #define SQ_CONFIG__OVERRIDE_SP_MAI_ALU_BUSY_MASK                                                              0x00000008L
2067 #define SQ_CONFIG__DISABLE_RAM_CLOCK_GATING_MASK                                                              0x00000010L
2068 #define SQ_CONFIG__DISABLE_MAI_CO_EXEC_MASK                                                                   0x00000020L
2069 #define SQ_CONFIG__OVERRIDE_MAI_ALU_BUSY_MASK                                                                 0x00000040L
2070 #define SQ_CONFIG__OVERRIDE_ALU_BUSY_MASK                                                                     0x00000080L
2071 #define SQ_CONFIG__DEBUG_EN_MASK                                                                              0x00000100L
2072 #define SQ_CONFIG__DEBUG_SINGLE_MEMOP_MASK                                                                    0x00000200L
2073 #define SQ_CONFIG__DEBUG_ONE_INST_CLAUSE_MASK                                                                 0x00000400L
2074 #define SQ_CONFIG__OVERRIDE_LDS_IDX_BUSY_MASK                                                                 0x00000800L
2075 #define SQ_CONFIG__EARLY_TA_DONE_DISABLE_MASK                                                                 0x00001000L
2076 #define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE_MASK                                                                  0x00002000L
2077 #define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE_MASK                                                                0x00004000L
2078 #define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE_MASK                                                         0x00008000L
2079 #define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE_MASK                                                              0x00010000L
2080 #define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE_MASK                                                              0x00020000L
2081 #define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS_MASK                                                           0x00040000L
2082 #define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS_MASK                                                                0x00180000L
2083 #define SQ_CONFIG__REPLAY_SLEEP_CNT_MASK                                                                      0x0FE00000L
2084 #define SQ_CONFIG__DISABLE_SP_VGPR_WRITE_SKIP_MASK                                                            0x10000000L
2085 #define SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING_MASK                                                    0x20000000L
2086 #define SQ_CONFIG__DISABLE_FLAT_SOFT_CLAUSE_MASK                                                              0x40000000L
2087 #define SQ_CONFIG__DISABLE_MIMG_SOFT_CLAUSE_MASK                                                              0x80000000L
2088 //SQC_CONFIG
2089 #define SQC_CONFIG__INST_CACHE_SIZE__SHIFT                                                                    0x0
2090 #define SQC_CONFIG__DATA_CACHE_SIZE__SHIFT                                                                    0x2
2091 #define SQC_CONFIG__MISS_FIFO_DEPTH__SHIFT                                                                    0x4
2092 #define SQC_CONFIG__HIT_FIFO_DEPTH__SHIFT                                                                     0x6
2093 #define SQC_CONFIG__FORCE_ALWAYS_MISS__SHIFT                                                                  0x7
2094 #define SQC_CONFIG__FORCE_IN_ORDER__SHIFT                                                                     0x8
2095 #define SQC_CONFIG__IDENTITY_HASH_BANK__SHIFT                                                                 0x9
2096 #define SQC_CONFIG__IDENTITY_HASH_SET__SHIFT                                                                  0xa
2097 #define SQC_CONFIG__PER_VMID_INV_DISABLE__SHIFT                                                               0xb
2098 #define SQC_CONFIG__EVICT_LRU__SHIFT                                                                          0xc
2099 #define SQC_CONFIG__FORCE_2_BANK__SHIFT                                                                       0xe
2100 #define SQC_CONFIG__FORCE_1_BANK__SHIFT                                                                       0xf
2101 #define SQC_CONFIG__LS_DISABLE_CLOCKS__SHIFT                                                                  0x10
2102 #define SQC_CONFIG__INST_PRF_COUNT__SHIFT                                                                     0x18
2103 #define SQC_CONFIG__INST_PRF_FILTER_DIS__SHIFT                                                                0x1d
2104 #define SQC_CONFIG__DISABLE_PREFETCH_CROSS_4K_BOUNDARY_CHECK__SHIFT                                           0x1e
2105 #define SQC_CONFIG__MEM_LS_DISABLE__SHIFT                                                                     0x1f
2106 #define SQC_CONFIG__INST_CACHE_SIZE_MASK                                                                      0x00000003L
2107 #define SQC_CONFIG__DATA_CACHE_SIZE_MASK                                                                      0x0000000CL
2108 #define SQC_CONFIG__MISS_FIFO_DEPTH_MASK                                                                      0x00000030L
2109 #define SQC_CONFIG__HIT_FIFO_DEPTH_MASK                                                                       0x00000040L
2110 #define SQC_CONFIG__FORCE_ALWAYS_MISS_MASK                                                                    0x00000080L
2111 #define SQC_CONFIG__FORCE_IN_ORDER_MASK                                                                       0x00000100L
2112 #define SQC_CONFIG__IDENTITY_HASH_BANK_MASK                                                                   0x00000200L
2113 #define SQC_CONFIG__IDENTITY_HASH_SET_MASK                                                                    0x00000400L
2114 #define SQC_CONFIG__PER_VMID_INV_DISABLE_MASK                                                                 0x00000800L
2115 #define SQC_CONFIG__EVICT_LRU_MASK                                                                            0x00003000L
2116 #define SQC_CONFIG__FORCE_2_BANK_MASK                                                                         0x00004000L
2117 #define SQC_CONFIG__FORCE_1_BANK_MASK                                                                         0x00008000L
2118 #define SQC_CONFIG__LS_DISABLE_CLOCKS_MASK                                                                    0x00FF0000L
2119 #define SQC_CONFIG__INST_PRF_COUNT_MASK                                                                       0x1F000000L
2120 #define SQC_CONFIG__INST_PRF_FILTER_DIS_MASK                                                                  0x20000000L
2121 #define SQC_CONFIG__DISABLE_PREFETCH_CROSS_4K_BOUNDARY_CHECK_MASK                                             0x40000000L
2122 #define SQC_CONFIG__MEM_LS_DISABLE_MASK                                                                       0x80000000L
2123 //LDS_CONFIG
2124 #define LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING__SHIFT                                                        0x0
2125 #define LDS_CONFIG__TMZ_VIOLATION_REPORTING__SHIFT                                                            0x1
2126 #define LDS_CONFIG__DISABLE_RAM_CLOCK_GATING__SHIFT                                                           0x2
2127 #define LDS_CONFIG__DISABLE_IDXCLK_MGCG__SHIFT                                                                0x3
2128 #define LDS_CONFIG__DISABLE_MEMCLK_MGCG__SHIFT                                                                0x4
2129 #define LDS_CONFIG__DISABLE_ATTRCLK_MGCG__SHIFT                                                               0x5
2130 #define LDS_CONFIG__DISABLE_ATODFPCLK_MGCG__SHIFT                                                             0x6
2131 #define LDS_CONFIG__DISABLE_PHASE_FGCG__SHIFT                                                                 0x7
2132 #define LDS_CONFIG__DISABLE_LDS_SP_READ_FGCG__SHIFT                                                           0x8
2133 #define LDS_CONFIG__DISABLE_SP_DATA_CLOCK_GATING__SHIFT                                                       0x9
2134 #define LDS_CONFIG__DISABLE_TD_DATA_CLOCK_GATING__SHIFT                                                       0xa
2135 #define LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING_MASK                                                          0x00000001L
2136 #define LDS_CONFIG__TMZ_VIOLATION_REPORTING_MASK                                                              0x00000002L
2137 #define LDS_CONFIG__DISABLE_RAM_CLOCK_GATING_MASK                                                             0x00000004L
2138 #define LDS_CONFIG__DISABLE_IDXCLK_MGCG_MASK                                                                  0x00000008L
2139 #define LDS_CONFIG__DISABLE_MEMCLK_MGCG_MASK                                                                  0x00000010L
2140 #define LDS_CONFIG__DISABLE_ATTRCLK_MGCG_MASK                                                                 0x00000020L
2141 #define LDS_CONFIG__DISABLE_ATODFPCLK_MGCG_MASK                                                               0x00000040L
2142 #define LDS_CONFIG__DISABLE_PHASE_FGCG_MASK                                                                   0x00000080L
2143 #define LDS_CONFIG__DISABLE_LDS_SP_READ_FGCG_MASK                                                             0x00000100L
2144 #define LDS_CONFIG__DISABLE_SP_DATA_CLOCK_GATING_MASK                                                         0x00000200L
2145 #define LDS_CONFIG__DISABLE_TD_DATA_CLOCK_GATING_MASK                                                         0x00000400L
2146 //SQ_RANDOM_WAVE_PRI
2147 #define SQ_RANDOM_WAVE_PRI__RET__SHIFT                                                                        0x0
2148 #define SQ_RANDOM_WAVE_PRI__RUI__SHIFT                                                                        0x7
2149 #define SQ_RANDOM_WAVE_PRI__RNG__SHIFT                                                                        0xa
2150 #define SQ_RANDOM_WAVE_PRI__RET_MASK                                                                          0x0000007FL
2151 #define SQ_RANDOM_WAVE_PRI__RUI_MASK                                                                          0x00000380L
2152 #define SQ_RANDOM_WAVE_PRI__RNG_MASK                                                                          0x007FFC00L
2153 //SQ_REG_CREDITS
2154 #define SQ_REG_CREDITS__SRBM_CREDITS__SHIFT                                                                   0x0
2155 #define SQ_REG_CREDITS__CMD_CREDITS__SHIFT                                                                    0x8
2156 #define SQ_REG_CREDITS__REG_BUSY__SHIFT                                                                       0x1c
2157 #define SQ_REG_CREDITS__SRBM_OVERFLOW__SHIFT                                                                  0x1d
2158 #define SQ_REG_CREDITS__IMMED_OVERFLOW__SHIFT                                                                 0x1e
2159 #define SQ_REG_CREDITS__CMD_OVERFLOW__SHIFT                                                                   0x1f
2160 #define SQ_REG_CREDITS__SRBM_CREDITS_MASK                                                                     0x0000003FL
2161 #define SQ_REG_CREDITS__CMD_CREDITS_MASK                                                                      0x00000F00L
2162 #define SQ_REG_CREDITS__REG_BUSY_MASK                                                                         0x10000000L
2163 #define SQ_REG_CREDITS__SRBM_OVERFLOW_MASK                                                                    0x20000000L
2164 #define SQ_REG_CREDITS__IMMED_OVERFLOW_MASK                                                                   0x40000000L
2165 #define SQ_REG_CREDITS__CMD_OVERFLOW_MASK                                                                     0x80000000L
2166 //SQ_FIFO_SIZES
2167 #define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE__SHIFT                                                             0x0
2168 #define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE__SHIFT                                                                0x8
2169 #define SQ_FIFO_SIZES__EXPORT_BUF_SIZE__SHIFT                                                                 0x10
2170 #define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE__SHIFT                                                             0x12
2171 #define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE_MASK                                                               0x0000000FL
2172 #define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE_MASK                                                                  0x00000F00L
2173 #define SQ_FIFO_SIZES__EXPORT_BUF_SIZE_MASK                                                                   0x00030000L
2174 #define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE_MASK                                                               0x000C0000L
2175 //SQ_DSM_CNTL
2176 #define SQ_DSM_CNTL__WAVEFRONT_STALL_0__SHIFT                                                                 0x0
2177 #define SQ_DSM_CNTL__WAVEFRONT_STALL_1__SHIFT                                                                 0x1
2178 #define SQ_DSM_CNTL__SPI_BACKPRESSURE_0__SHIFT                                                                0x2
2179 #define SQ_DSM_CNTL__SPI_BACKPRESSURE_1__SHIFT                                                                0x3
2180 #define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0__SHIFT                                                      0x8
2181 #define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1__SHIFT                                                      0x9
2182 #define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT                                                          0xa
2183 #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0__SHIFT                                                       0x10
2184 #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1__SHIFT                                                       0x11
2185 #define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01__SHIFT                                                         0x12
2186 #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2__SHIFT                                                       0x13
2187 #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3__SHIFT                                                       0x14
2188 #define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23__SHIFT                                                         0x15
2189 #define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0__SHIFT                                                        0x18
2190 #define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1__SHIFT                                                        0x19
2191 #define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE__SHIFT                                                            0x1a
2192 #define SQ_DSM_CNTL__WAVEFRONT_STALL_0_MASK                                                                   0x00000001L
2193 #define SQ_DSM_CNTL__WAVEFRONT_STALL_1_MASK                                                                   0x00000002L
2194 #define SQ_DSM_CNTL__SPI_BACKPRESSURE_0_MASK                                                                  0x00000004L
2195 #define SQ_DSM_CNTL__SPI_BACKPRESSURE_1_MASK                                                                  0x00000008L
2196 #define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0_MASK                                                        0x00000100L
2197 #define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1_MASK                                                        0x00000200L
2198 #define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE_MASK                                                            0x00000400L
2199 #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0_MASK                                                         0x00010000L
2200 #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1_MASK                                                         0x00020000L
2201 #define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01_MASK                                                           0x00040000L
2202 #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2_MASK                                                         0x00080000L
2203 #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3_MASK                                                         0x00100000L
2204 #define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23_MASK                                                           0x00200000L
2205 #define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0_MASK                                                          0x01000000L
2206 #define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1_MASK                                                          0x02000000L
2207 #define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE_MASK                                                              0x04000000L
2208 //SQ_DSM_CNTL2
2209 #define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT__SHIFT                                                         0x0
2210 #define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY__SHIFT                                                         0x2
2211 #define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT__SHIFT                                                        0x3
2212 #define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY__SHIFT                                                        0x5
2213 #define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT__SHIFT                                                        0x6
2214 #define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY__SHIFT                                                        0x8
2215 #define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT__SHIFT                                                           0x9
2216 #define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY__SHIFT                                                           0xb
2217 #define SQ_DSM_CNTL2__LDS_INJECT_DELAY__SHIFT                                                                 0xe
2218 #define SQ_DSM_CNTL2__SP_INJECT_DELAY__SHIFT                                                                  0x14
2219 #define SQ_DSM_CNTL2__SQ_INJECT_DELAY__SHIFT                                                                  0x1a
2220 #define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT_MASK                                                           0x00000003L
2221 #define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY_MASK                                                           0x00000004L
2222 #define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT_MASK                                                          0x00000018L
2223 #define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY_MASK                                                          0x00000020L
2224 #define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT_MASK                                                          0x000000C0L
2225 #define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY_MASK                                                          0x00000100L
2226 #define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT_MASK                                                             0x00000600L
2227 #define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY_MASK                                                             0x00000800L
2228 #define SQ_DSM_CNTL2__LDS_INJECT_DELAY_MASK                                                                   0x000FC000L
2229 #define SQ_DSM_CNTL2__SP_INJECT_DELAY_MASK                                                                    0x03F00000L
2230 #define SQ_DSM_CNTL2__SQ_INJECT_DELAY_MASK                                                                    0xFC000000L
2231 //SQ_RUNTIME_CONFIG
2232 #define SQ_RUNTIME_CONFIG__ENABLE_TEX_ARB_OLDEST__SHIFT                                                       0x0
2233 #define SQ_RUNTIME_CONFIG__ENABLE_TEX_ARB_OLDEST_MASK                                                         0x00000001L
2234 //SQ_DEBUG_STS_GLOBAL
2235 #define SQ_DEBUG_STS_GLOBAL__BUSY__SHIFT                                                                      0x0
2236 #define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY__SHIFT                                                        0x1
2237 #define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0__SHIFT                                                            0x4
2238 #define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1__SHIFT                                                            0x10
2239 #define SQ_DEBUG_STS_GLOBAL__BUSY_MASK                                                                        0x00000001L
2240 #define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY_MASK                                                          0x00000002L
2241 #define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0_MASK                                                              0x0000FFF0L
2242 #define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1_MASK                                                              0x0FFF0000L
2243 //SH_MEM_BASES
2244 #define SH_MEM_BASES__PRIVATE_BASE__SHIFT                                                                     0x0
2245 #define SH_MEM_BASES__SHARED_BASE__SHIFT                                                                      0x10
2246 #define SH_MEM_BASES__PRIVATE_BASE_MASK                                                                       0x0000FFFFL
2247 #define SH_MEM_BASES__SHARED_BASE_MASK                                                                        0xFFFF0000L
2248 //SQ_TIMEOUT_CONFIG
2249 #define SQ_TIMEOUT_CONFIG__PERIOD_SEL__SHIFT                                                                  0x0
2250 #define SQ_TIMEOUT_CONFIG__TIMEOUT_FATAL_DISABLE__SHIFT                                                       0x6
2251 #define SQ_TIMEOUT_CONFIG__TIMER_LONGER_SEL__SHIFT                                                            0x7
2252 #define SQ_TIMEOUT_CONFIG__TIMEOUT_CONDITIONS_MASK__SHIFT                                                     0x8
2253 #define SQ_TIMEOUT_CONFIG__PERIOD_SEL_MASK                                                                    0x0000003FL
2254 #define SQ_TIMEOUT_CONFIG__TIMEOUT_FATAL_DISABLE_MASK                                                         0x00000040L
2255 #define SQ_TIMEOUT_CONFIG__TIMER_LONGER_SEL_MASK                                                              0x00000080L
2256 #define SQ_TIMEOUT_CONFIG__TIMEOUT_CONDITIONS_MASK_MASK                                                       0x07FFFF00L
2257 //SQ_TIMEOUT_STATUS
2258 #define SQ_TIMEOUT_STATUS__WAVE_TIMEOUT__SHIFT                                                                0x0
2259 #define SQ_TIMEOUT_STATUS__WAVE_TIMEOUT_MASK                                                                  0xFFFFFFFFL
2260 //SH_MEM_CONFIG
2261 #define SH_MEM_CONFIG__ADDRESS_MODE__SHIFT                                                                    0x0
2262 #define SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT                                                                  0x3
2263 #define SH_MEM_CONFIG__F8_MODE__SHIFT                                                                         0x8
2264 #define SH_MEM_CONFIG__RETRY_DISABLE__SHIFT                                                                   0xc
2265 #define SH_MEM_CONFIG__PRIVATE_NV__SHIFT                                                                      0xd
2266 #define SH_MEM_CONFIG__ADDRESS_MODE_MASK                                                                      0x00000001L
2267 #define SH_MEM_CONFIG__ALIGNMENT_MODE_MASK                                                                    0x00000018L
2268 #define SH_MEM_CONFIG__F8_MODE_MASK                                                                           0x00000100L
2269 #define SH_MEM_CONFIG__RETRY_DISABLE_MASK                                                                     0x00001000L
2270 #define SH_MEM_CONFIG__PRIVATE_NV_MASK                                                                        0x00002000L
2271 //SP_MFMA_PORTD_RD_CONFIG
2272 #define SP_MFMA_PORTD_RD_CONFIG__SET__SHIFT                                                                   0x0
2273 #define SP_MFMA_PORTD_RD_CONFIG__TYPE__SHIFT                                                                  0x1
2274 #define SP_MFMA_PORTD_RD_CONFIG__LAST_PASS__SHIFT                                                             0x4
2275 #define SP_MFMA_PORTD_RD_CONFIG__PORTD_PATTERN__SHIFT                                                         0x9
2276 #define SP_MFMA_PORTD_RD_CONFIG__SET_MASK                                                                     0x00000001L
2277 #define SP_MFMA_PORTD_RD_CONFIG__TYPE_MASK                                                                    0x0000000EL
2278 #define SP_MFMA_PORTD_RD_CONFIG__LAST_PASS_MASK                                                               0x000001F0L
2279 #define SP_MFMA_PORTD_RD_CONFIG__PORTD_PATTERN_MASK                                                           0x1FFFFE00L
2280 //SH_CAC_CONFIG
2281 #define SH_CAC_CONFIG__SQG_UTCL1_REPEATER_FGCG_DISABLE__SHIFT                                                 0x0
2282 #define SH_CAC_CONFIG__SQC_UTCL1_REPEATER_FGCG_DISABLE__SHIFT                                                 0x1
2283 #define SH_CAC_CONFIG__SPI_SQ_CMD_REPEATER_FGCG_DISABLE__SHIFT                                                0x2
2284 #define SH_CAC_CONFIG__SQ_MSG_REPEATER_FGCG_DISABLE__SHIFT                                                    0x3
2285 #define SH_CAC_CONFIG__SQC_TC_REPEATER_FGCG_DISABLE__SHIFT                                                    0x4
2286 #define SH_CAC_CONFIG__SQC_SQ_REPEATER_FGCG_DISABLE__SHIFT                                                    0x5
2287 #define SH_CAC_CONFIG__SQG_TC_REPEATER_FGCG_DISABLE__SHIFT                                                    0x6
2288 #define SH_CAC_CONFIG__SQC_DISABLE_RAM_CLOCK_GATING__SHIFT                                                    0x8
2289 #define SH_CAC_CONFIG__SQG_DISABLE_RAM_CLOCK_GATING__SHIFT                                                    0x9
2290 #define SH_CAC_CONFIG__SQC_MGCG_CLOCK_OFF_DELAY_CNT__SHIFT                                                    0x10
2291 #define SH_CAC_CONFIG__SQC_MGCG_DISABLE__SHIFT                                                                0x14
2292 #define SH_CAC_CONFIG__SQC_TC_REQ_CLKEN_CHICKENBIT__SHIFT                                                     0x1c
2293 #define SH_CAC_CONFIG__SQC_ICACHE_CTRL_MGCG_DISABLE__SHIFT                                                    0x1d
2294 #define SH_CAC_CONFIG__SQC_DCACHE_CTRL_MGCG_DISABLE__SHIFT                                                    0x1e
2295 #define SH_CAC_CONFIG__SQC_DISABLE_UTCL1_FGCG_PADDR__SHIFT                                                    0x1f
2296 #define SH_CAC_CONFIG__SQG_UTCL1_REPEATER_FGCG_DISABLE_MASK                                                   0x00000001L
2297 #define SH_CAC_CONFIG__SQC_UTCL1_REPEATER_FGCG_DISABLE_MASK                                                   0x00000002L
2298 #define SH_CAC_CONFIG__SPI_SQ_CMD_REPEATER_FGCG_DISABLE_MASK                                                  0x00000004L
2299 #define SH_CAC_CONFIG__SQ_MSG_REPEATER_FGCG_DISABLE_MASK                                                      0x00000008L
2300 #define SH_CAC_CONFIG__SQC_TC_REPEATER_FGCG_DISABLE_MASK                                                      0x00000010L
2301 #define SH_CAC_CONFIG__SQC_SQ_REPEATER_FGCG_DISABLE_MASK                                                      0x00000020L
2302 #define SH_CAC_CONFIG__SQG_TC_REPEATER_FGCG_DISABLE_MASK                                                      0x00000040L
2303 #define SH_CAC_CONFIG__SQC_DISABLE_RAM_CLOCK_GATING_MASK                                                      0x00000100L
2304 #define SH_CAC_CONFIG__SQG_DISABLE_RAM_CLOCK_GATING_MASK                                                      0x00000200L
2305 #define SH_CAC_CONFIG__SQC_MGCG_CLOCK_OFF_DELAY_CNT_MASK                                                      0x000F0000L
2306 #define SH_CAC_CONFIG__SQC_MGCG_DISABLE_MASK                                                                  0x0FF00000L
2307 #define SH_CAC_CONFIG__SQC_TC_REQ_CLKEN_CHICKENBIT_MASK                                                       0x10000000L
2308 #define SH_CAC_CONFIG__SQC_ICACHE_CTRL_MGCG_DISABLE_MASK                                                      0x20000000L
2309 #define SH_CAC_CONFIG__SQC_DCACHE_CTRL_MGCG_DISABLE_MASK                                                      0x40000000L
2310 #define SH_CAC_CONFIG__SQC_DISABLE_UTCL1_FGCG_PADDR_MASK                                                      0x80000000L
2311 //SQ_DEBUG_STS_GLOBAL2
2312 #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0__SHIFT                                                          0x0
2313 #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1__SHIFT                                                          0x8
2314 #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED__SHIFT                                                         0x10
2315 #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST__SHIFT                                                          0x18
2316 #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0_MASK                                                            0x000000FFL
2317 #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1_MASK                                                            0x0000FF00L
2318 #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED_MASK                                                           0x00FF0000L
2319 #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST_MASK                                                            0xFF000000L
2320 //SQ_DEBUG_STS_GLOBAL3
2321 #define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD__SHIFT                                                      0x0
2322 #define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG__SHIFT                                                      0x4
2323 #define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD_MASK                                                        0x0000000FL
2324 #define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG_MASK                                                        0x000003F0L
2325 //CC_GC_SHADER_RATE_CONFIG
2326 #define CC_GC_SHADER_RATE_CONFIG__WRITE_DIS__SHIFT                                                            0x0
2327 #define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT                                                            0x1
2328 #define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT                                                  0x3
2329 #define CC_GC_SHADER_RATE_CONFIG__HALF_LDS__SHIFT                                                             0x4
2330 #define CC_GC_SHADER_RATE_CONFIG__WRITE_DIS_MASK                                                              0x00000001L
2331 #define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE_MASK                                                              0x00000006L
2332 #define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK                                                    0x00000008L
2333 #define CC_GC_SHADER_RATE_CONFIG__HALF_LDS_MASK                                                               0x00000010L
2334 //GC_USER_SHADER_RATE_CONFIG
2335 #define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT                                                          0x1
2336 #define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT                                                0x3
2337 #define GC_USER_SHADER_RATE_CONFIG__HALF_LDS__SHIFT                                                           0x4
2338 #define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE_MASK                                                            0x00000006L
2339 #define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK                                                  0x00000008L
2340 #define GC_USER_SHADER_RATE_CONFIG__HALF_LDS_MASK                                                             0x00000010L
2341 //SQ_INTERRUPT_AUTO_MASK
2342 #define SQ_INTERRUPT_AUTO_MASK__MASK__SHIFT                                                                   0x0
2343 #define SQ_INTERRUPT_AUTO_MASK__MASK_MASK                                                                     0x00FFFFFFL
2344 //SQ_INTERRUPT_MSG_CTRL
2345 #define SQ_INTERRUPT_MSG_CTRL__STALL__SHIFT                                                                   0x0
2346 #define SQ_INTERRUPT_MSG_CTRL__STALL_MASK                                                                     0x00000001L
2347 //SQ_DEBUG_PERFCOUNT_TRAP
2348 #define SQ_DEBUG_PERFCOUNT_TRAP__ENABLE__SHIFT                                                                0x0
2349 #define SQ_DEBUG_PERFCOUNT_TRAP__COUNTER__SHIFT                                                               0x1
2350 #define SQ_DEBUG_PERFCOUNT_TRAP__LIMIT__SHIFT                                                                 0x4
2351 #define SQ_DEBUG_PERFCOUNT_TRAP__ENABLE_MASK                                                                  0x00000001L
2352 #define SQ_DEBUG_PERFCOUNT_TRAP__COUNTER_MASK                                                                 0x0000000EL
2353 #define SQ_DEBUG_PERFCOUNT_TRAP__LIMIT_MASK                                                                   0x0FFFFFF0L
2354 //SQ_UTCL1_CNTL1
2355 #define SQ_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT                                                               0x0
2356 #define SQ_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT                                                                  0x1
2357 #define SQ_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT                                                                0x2
2358 #define SQ_UTCL1_CNTL1__RESP_MODE__SHIFT                                                                      0x3
2359 #define SQ_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT                                                                0x5
2360 #define SQ_UTCL1_CNTL1__CLIENTID__SHIFT                                                                       0x7
2361 #define SQ_UTCL1_CNTL1__USERVM_DIS__SHIFT                                                                     0x10
2362 #define SQ_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT                                                              0x11
2363 #define SQ_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT                                                           0x12
2364 #define SQ_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT                                                            0x13
2365 #define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT                                                        0x17
2366 #define SQ_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT                                                          0x18
2367 #define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL__SHIFT                                                             0x19
2368 #define SQ_UTCL1_CNTL1__FORCE_MISS__SHIFT                                                                     0x1a
2369 #define SQ_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT                                                                 0x1b
2370 #define SQ_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT                                                         0x1c
2371 #define SQ_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT                                                         0x1e
2372 #define SQ_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK                                                                 0x00000001L
2373 #define SQ_UTCL1_CNTL1__GPUVM_64K_DEF_MASK                                                                    0x00000002L
2374 #define SQ_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK                                                                  0x00000004L
2375 #define SQ_UTCL1_CNTL1__RESP_MODE_MASK                                                                        0x00000018L
2376 #define SQ_UTCL1_CNTL1__RESP_FAULT_MODE_MASK                                                                  0x00000060L
2377 #define SQ_UTCL1_CNTL1__CLIENTID_MASK                                                                         0x0000FF80L
2378 #define SQ_UTCL1_CNTL1__USERVM_DIS_MASK                                                                       0x00010000L
2379 #define SQ_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK                                                                0x00020000L
2380 #define SQ_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK                                                             0x00040000L
2381 #define SQ_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK                                                              0x00780000L
2382 #define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK                                                          0x00800000L
2383 #define SQ_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK                                                            0x01000000L
2384 #define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_MASK                                                               0x02000000L
2385 #define SQ_UTCL1_CNTL1__FORCE_MISS_MASK                                                                       0x04000000L
2386 #define SQ_UTCL1_CNTL1__FORCE_IN_ORDER_MASK                                                                   0x08000000L
2387 #define SQ_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK                                                           0x30000000L
2388 #define SQ_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK                                                           0xC0000000L
2389 //SQ_UTCL1_CNTL2
2390 #define SQ_UTCL1_CNTL2__SPARE__SHIFT                                                                          0x0
2391 #define SQ_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT                                                             0x8
2392 #define SQ_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT                                                                 0x9
2393 #define SQ_UTCL1_CNTL2__LINE_VALID__SHIFT                                                                     0xa
2394 #define SQ_UTCL1_CNTL2__DIS_EDC__SHIFT                                                                        0xb
2395 #define SQ_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT                                                                 0xc
2396 #define SQ_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT                                                                  0xd
2397 #define SQ_UTCL1_CNTL2__FORCE_SNOOP__SHIFT                                                                    0xe
2398 #define SQ_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT                                                            0xf
2399 #define SQ_UTCL1_CNTL2__RETRY_TIMER__SHIFT                                                                    0x10
2400 #define SQ_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT                                                           0x1a
2401 #define SQ_UTCL1_CNTL2__PREFETCH_PAGE__SHIFT                                                                  0x1c
2402 #define SQ_UTCL1_CNTL2__SPARE_MASK                                                                            0x000000FFL
2403 #define SQ_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK                                                               0x00000100L
2404 #define SQ_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK                                                                   0x00000200L
2405 #define SQ_UTCL1_CNTL2__LINE_VALID_MASK                                                                       0x00000400L
2406 #define SQ_UTCL1_CNTL2__DIS_EDC_MASK                                                                          0x00000800L
2407 #define SQ_UTCL1_CNTL2__GPUVM_INV_MODE_MASK                                                                   0x00001000L
2408 #define SQ_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK                                                                    0x00002000L
2409 #define SQ_UTCL1_CNTL2__FORCE_SNOOP_MASK                                                                      0x00004000L
2410 #define SQ_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK                                                              0x00008000L
2411 #define SQ_UTCL1_CNTL2__RETRY_TIMER_MASK                                                                      0x007F0000L
2412 #define SQ_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK                                                             0x04000000L
2413 #define SQ_UTCL1_CNTL2__PREFETCH_PAGE_MASK                                                                    0xF0000000L
2414 //SQ_UTCL1_STATUS
2415 #define SQ_UTCL1_STATUS__FAULT_DETECTED__SHIFT                                                                0x0
2416 #define SQ_UTCL1_STATUS__RETRY_DETECTED__SHIFT                                                                0x1
2417 #define SQ_UTCL1_STATUS__PRT_DETECTED__SHIFT                                                                  0x2
2418 #define SQ_UTCL1_STATUS__RESERVED__SHIFT                                                                      0x3
2419 #define SQ_UTCL1_STATUS__UNUSED__SHIFT                                                                        0x10
2420 #define SQ_UTCL1_STATUS__FAULT_DETECTED_MASK                                                                  0x00000001L
2421 #define SQ_UTCL1_STATUS__RETRY_DETECTED_MASK                                                                  0x00000002L
2422 #define SQ_UTCL1_STATUS__PRT_DETECTED_MASK                                                                    0x00000004L
2423 #define SQ_UTCL1_STATUS__RESERVED_MASK                                                                        0x0000FFF8L
2424 #define SQ_UTCL1_STATUS__UNUSED_MASK                                                                          0xFFFF0000L
2425 //SQ_FED_INTERRUPT_STATUS
2426 #define SQ_FED_INTERRUPT_STATUS__INTERRUPT_STATUS__SHIFT                                                      0x0
2427 #define SQ_FED_INTERRUPT_STATUS__INTERRUPT_SIMD_ID__SHIFT                                                     0x2
2428 #define SQ_FED_INTERRUPT_STATUS__INTERRUPT_WAVE_ID__SHIFT                                                     0x4
2429 #define SQ_FED_INTERRUPT_STATUS__INTERRUPT_CU_ID__SHIFT                                                       0x8
2430 #define SQ_FED_INTERRUPT_STATUS__INTERRUPT_VM_ID__SHIFT                                                       0xc
2431 #define SQ_FED_INTERRUPT_STATUS__TO_RSMU_DISABLE__SHIFT                                                       0x10
2432 #define SQ_FED_INTERRUPT_STATUS__TO_IH_DISABLE__SHIFT                                                         0x11
2433 #define SQ_FED_INTERRUPT_STATUS__FED_HALT_DISABLE__SHIFT                                                      0x12
2434 #define SQ_FED_INTERRUPT_STATUS__INTERRUPT_STATUS_MASK                                                        0x00000001L
2435 #define SQ_FED_INTERRUPT_STATUS__INTERRUPT_SIMD_ID_MASK                                                       0x0000000CL
2436 #define SQ_FED_INTERRUPT_STATUS__INTERRUPT_WAVE_ID_MASK                                                       0x000000F0L
2437 #define SQ_FED_INTERRUPT_STATUS__INTERRUPT_CU_ID_MASK                                                         0x00000F00L
2438 #define SQ_FED_INTERRUPT_STATUS__INTERRUPT_VM_ID_MASK                                                         0x0000F000L
2439 #define SQ_FED_INTERRUPT_STATUS__TO_RSMU_DISABLE_MASK                                                         0x00010000L
2440 #define SQ_FED_INTERRUPT_STATUS__TO_IH_DISABLE_MASK                                                           0x00020000L
2441 #define SQ_FED_INTERRUPT_STATUS__FED_HALT_DISABLE_MASK                                                        0x00040000L
2442 //SQ_CGTS_CONFIG
2443 #define SQ_CGTS_CONFIG__DGEMM_EXTRA_BUSY_PASS__SHIFT                                                          0x0
2444 #define SQ_CGTS_CONFIG__XDL_EXTRA_BUSY_PASS__SHIFT                                                            0x4
2445 #define SQ_CGTS_CONFIG__VALU_EXTRA_BUSY_PASS__SHIFT                                                           0x8
2446 #define SQ_CGTS_CONFIG__DLOP_EXTRA_BUSY_PASS__SHIFT                                                           0xc
2447 #define SQ_CGTS_CONFIG__XDL_EXTRA_GAP_PASS__SHIFT                                                             0x10
2448 #define SQ_CGTS_CONFIG__DGEMM_EXTRA_GAP_PASS__SHIFT                                                           0x12
2449 #define SQ_CGTS_CONFIG__DLOP_EXTRA_GAP_PASS__SHIFT                                                            0x14
2450 #define SQ_CGTS_CONFIG__DGEMM_EXTRA_BUSY_PASS_MASK                                                            0x0000000FL
2451 #define SQ_CGTS_CONFIG__XDL_EXTRA_BUSY_PASS_MASK                                                              0x000000F0L
2452 #define SQ_CGTS_CONFIG__VALU_EXTRA_BUSY_PASS_MASK                                                             0x00000F00L
2453 #define SQ_CGTS_CONFIG__DLOP_EXTRA_BUSY_PASS_MASK                                                             0x0000F000L
2454 #define SQ_CGTS_CONFIG__XDL_EXTRA_GAP_PASS_MASK                                                               0x00030000L
2455 #define SQ_CGTS_CONFIG__DGEMM_EXTRA_GAP_PASS_MASK                                                             0x000C0000L
2456 #define SQ_CGTS_CONFIG__DLOP_EXTRA_GAP_PASS_MASK                                                              0x00300000L
2457 //SQ_SHADER_TBA_LO
2458 #define SQ_SHADER_TBA_LO__ADDR_LO__SHIFT                                                                      0x0
2459 #define SQ_SHADER_TBA_LO__ADDR_LO_MASK                                                                        0xFFFFFFFFL
2460 //SQ_SHADER_TBA_HI
2461 #define SQ_SHADER_TBA_HI__ADDR_HI__SHIFT                                                                      0x0
2462 #define SQ_SHADER_TBA_HI__ADDR_HI_MASK                                                                        0x000000FFL
2463 //SQ_SHADER_TMA_LO
2464 #define SQ_SHADER_TMA_LO__ADDR_LO__SHIFT                                                                      0x0
2465 #define SQ_SHADER_TMA_LO__ADDR_LO_MASK                                                                        0xFFFFFFFFL
2466 //SQ_SHADER_TMA_HI
2467 #define SQ_SHADER_TMA_HI__ADDR_HI__SHIFT                                                                      0x0
2468 #define SQ_SHADER_TMA_HI__ADDR_HI_MASK                                                                        0x000000FFL
2469 //SQC_DSM_CNTL
2470 #define SQC_DSM_CNTL__INST_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT                                              0x0
2471 #define SQC_DSM_CNTL__INST_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT                                             0x2
2472 #define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT                                       0x3
2473 #define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT                                      0x5
2474 #define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT                                          0x6
2475 #define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT                                         0x8
2476 #define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT                                       0x9
2477 #define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT                                      0xb
2478 #define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT                                          0xc
2479 #define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT                                         0xe
2480 #define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT                                       0xf
2481 #define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT                                      0x11
2482 #define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT                                          0x12
2483 #define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT                                         0x14
2484 #define SQC_DSM_CNTL__DATA_CU3_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT                                       0x15
2485 #define SQC_DSM_CNTL__DATA_CU3_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT                                      0x17
2486 #define SQC_DSM_CNTL__DATA_CU3_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT                                          0x18
2487 #define SQC_DSM_CNTL__DATA_CU3_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT                                         0x1a
2488 #define SQC_DSM_CNTL__INST_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK                                                0x00000003L
2489 #define SQC_DSM_CNTL__INST_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK                                               0x00000004L
2490 #define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK                                         0x00000018L
2491 #define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK                                        0x00000020L
2492 #define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK                                            0x000000C0L
2493 #define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK                                           0x00000100L
2494 #define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK                                         0x00000600L
2495 #define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK                                        0x00000800L
2496 #define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK                                            0x00003000L
2497 #define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK                                           0x00004000L
2498 #define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK                                         0x00018000L
2499 #define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK                                        0x00020000L
2500 #define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK                                            0x000C0000L
2501 #define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK                                           0x00100000L
2502 #define SQC_DSM_CNTL__DATA_CU3_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK                                         0x00600000L
2503 #define SQC_DSM_CNTL__DATA_CU3_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK                                        0x00800000L
2504 #define SQC_DSM_CNTL__DATA_CU3_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK                                            0x03000000L
2505 #define SQC_DSM_CNTL__DATA_CU3_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK                                           0x04000000L
2506 //SQC_DSM_CNTLA
2507 #define SQC_DSM_CNTLA__INST_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT                                                 0x0
2508 #define SQC_DSM_CNTLA__INST_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT                                                0x2
2509 #define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT                                         0x3
2510 #define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT                                        0x5
2511 #define SQC_DSM_CNTLA__INST_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT                                               0x6
2512 #define SQC_DSM_CNTLA__INST_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT                                              0x8
2513 #define SQC_DSM_CNTLA__INST_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT                                                0x9
2514 #define SQC_DSM_CNTLA__INST_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT                                               0xb
2515 #define SQC_DSM_CNTLA__DATA_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT                                                 0xc
2516 #define SQC_DSM_CNTLA__DATA_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT                                                0xe
2517 #define SQC_DSM_CNTLA__DATA_HIT_FIFO_DSM_IRRITATOR_DATA__SHIFT                                                0xf
2518 #define SQC_DSM_CNTLA__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE__SHIFT                                               0x11
2519 #define SQC_DSM_CNTLA__DATA_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT                                               0x12
2520 #define SQC_DSM_CNTLA__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT                                              0x14
2521 #define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA__SHIFT                                           0x15
2522 #define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE__SHIFT                                          0x17
2523 #define SQC_DSM_CNTLA__DATA_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT                                                0x18
2524 #define SQC_DSM_CNTLA__DATA_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT                                               0x1a
2525 #define SQC_DSM_CNTLA__INST_TAG_RAM_DSM_IRRITATOR_DATA_MASK                                                   0x00000003L
2526 #define SQC_DSM_CNTLA__INST_TAG_RAM_ENABLE_SINGLE_WRITE_MASK                                                  0x00000004L
2527 #define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA_MASK                                           0x00000018L
2528 #define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK                                          0x00000020L
2529 #define SQC_DSM_CNTLA__INST_MISS_FIFO_DSM_IRRITATOR_DATA_MASK                                                 0x000000C0L
2530 #define SQC_DSM_CNTLA__INST_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK                                                0x00000100L
2531 #define SQC_DSM_CNTLA__INST_BANK_RAM_DSM_IRRITATOR_DATA_MASK                                                  0x00000600L
2532 #define SQC_DSM_CNTLA__INST_BANK_RAM_ENABLE_SINGLE_WRITE_MASK                                                 0x00000800L
2533 #define SQC_DSM_CNTLA__DATA_TAG_RAM_DSM_IRRITATOR_DATA_MASK                                                   0x00003000L
2534 #define SQC_DSM_CNTLA__DATA_TAG_RAM_ENABLE_SINGLE_WRITE_MASK                                                  0x00004000L
2535 #define SQC_DSM_CNTLA__DATA_HIT_FIFO_DSM_IRRITATOR_DATA_MASK                                                  0x00018000L
2536 #define SQC_DSM_CNTLA__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE_MASK                                                 0x00020000L
2537 #define SQC_DSM_CNTLA__DATA_MISS_FIFO_DSM_IRRITATOR_DATA_MASK                                                 0x000C0000L
2538 #define SQC_DSM_CNTLA__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK                                                0x00100000L
2539 #define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA_MASK                                             0x00600000L
2540 #define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE_MASK                                            0x00800000L
2541 #define SQC_DSM_CNTLA__DATA_BANK_RAM_DSM_IRRITATOR_DATA_MASK                                                  0x03000000L
2542 #define SQC_DSM_CNTLA__DATA_BANK_RAM_ENABLE_SINGLE_WRITE_MASK                                                 0x04000000L
2543 //SQC_DSM_CNTLB
2544 #define SQC_DSM_CNTLB__INST_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT                                                 0x0
2545 #define SQC_DSM_CNTLB__INST_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT                                                0x2
2546 #define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT                                         0x3
2547 #define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT                                        0x5
2548 #define SQC_DSM_CNTLB__INST_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT                                               0x6
2549 #define SQC_DSM_CNTLB__INST_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT                                              0x8
2550 #define SQC_DSM_CNTLB__INST_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT                                                0x9
2551 #define SQC_DSM_CNTLB__INST_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT                                               0xb
2552 #define SQC_DSM_CNTLB__DATA_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT                                                 0xc
2553 #define SQC_DSM_CNTLB__DATA_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT                                                0xe
2554 #define SQC_DSM_CNTLB__DATA_HIT_FIFO_DSM_IRRITATOR_DATA__SHIFT                                                0xf
2555 #define SQC_DSM_CNTLB__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE__SHIFT                                               0x11
2556 #define SQC_DSM_CNTLB__DATA_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT                                               0x12
2557 #define SQC_DSM_CNTLB__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT                                              0x14
2558 #define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA__SHIFT                                           0x15
2559 #define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE__SHIFT                                          0x17
2560 #define SQC_DSM_CNTLB__DATA_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT                                                0x18
2561 #define SQC_DSM_CNTLB__DATA_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT                                               0x1a
2562 #define SQC_DSM_CNTLB__INST_TAG_RAM_DSM_IRRITATOR_DATA_MASK                                                   0x00000003L
2563 #define SQC_DSM_CNTLB__INST_TAG_RAM_ENABLE_SINGLE_WRITE_MASK                                                  0x00000004L
2564 #define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA_MASK                                           0x00000018L
2565 #define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK                                          0x00000020L
2566 #define SQC_DSM_CNTLB__INST_MISS_FIFO_DSM_IRRITATOR_DATA_MASK                                                 0x000000C0L
2567 #define SQC_DSM_CNTLB__INST_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK                                                0x00000100L
2568 #define SQC_DSM_CNTLB__INST_BANK_RAM_DSM_IRRITATOR_DATA_MASK                                                  0x00000600L
2569 #define SQC_DSM_CNTLB__INST_BANK_RAM_ENABLE_SINGLE_WRITE_MASK                                                 0x00000800L
2570 #define SQC_DSM_CNTLB__DATA_TAG_RAM_DSM_IRRITATOR_DATA_MASK                                                   0x00003000L
2571 #define SQC_DSM_CNTLB__DATA_TAG_RAM_ENABLE_SINGLE_WRITE_MASK                                                  0x00004000L
2572 #define SQC_DSM_CNTLB__DATA_HIT_FIFO_DSM_IRRITATOR_DATA_MASK                                                  0x00018000L
2573 #define SQC_DSM_CNTLB__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE_MASK                                                 0x00020000L
2574 #define SQC_DSM_CNTLB__DATA_MISS_FIFO_DSM_IRRITATOR_DATA_MASK                                                 0x000C0000L
2575 #define SQC_DSM_CNTLB__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK                                                0x00100000L
2576 #define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA_MASK                                             0x00600000L
2577 #define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE_MASK                                            0x00800000L
2578 #define SQC_DSM_CNTLB__DATA_BANK_RAM_DSM_IRRITATOR_DATA_MASK                                                  0x03000000L
2579 #define SQC_DSM_CNTLB__DATA_BANK_RAM_ENABLE_SINGLE_WRITE_MASK                                                 0x04000000L
2580 //SQC_DSM_CNTL2
2581 #define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT                                            0x0
2582 #define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT                                            0x2
2583 #define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT                                     0x3
2584 #define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT                                     0x5
2585 #define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT                                        0x6
2586 #define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT                                        0x8
2587 #define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT                                     0x9
2588 #define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT                                     0xb
2589 #define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT                                        0xc
2590 #define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT                                        0xe
2591 #define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT                                     0xf
2592 #define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT                                     0x11
2593 #define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT                                        0x12
2594 #define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT                                        0x14
2595 #define SQC_DSM_CNTL2__INJECT_DELAY__SHIFT                                                                    0x1a
2596 #define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK                                              0x00000003L
2597 #define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK                                              0x00000004L
2598 #define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK                                       0x00000018L
2599 #define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK                                       0x00000020L
2600 #define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK                                          0x000000C0L
2601 #define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK                                          0x00000100L
2602 #define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK                                       0x00000600L
2603 #define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK                                       0x00000800L
2604 #define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK                                          0x00003000L
2605 #define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK                                          0x00004000L
2606 #define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK                                       0x00018000L
2607 #define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK                                       0x00020000L
2608 #define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK                                          0x000C0000L
2609 #define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK                                          0x00100000L
2610 #define SQC_DSM_CNTL2__INJECT_DELAY_MASK                                                                      0xFC000000L
2611 //SQC_DSM_CNTL2A
2612 #define SQC_DSM_CNTL2A__INST_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT                                               0x0
2613 #define SQC_DSM_CNTL2A__INST_TAG_RAM_SELECT_INJECT_DELAY__SHIFT                                               0x2
2614 #define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT                                       0x3
2615 #define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT                                       0x5
2616 #define SQC_DSM_CNTL2A__INST_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT                                             0x6
2617 #define SQC_DSM_CNTL2A__INST_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT                                             0x8
2618 #define SQC_DSM_CNTL2A__INST_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT                                              0x9
2619 #define SQC_DSM_CNTL2A__INST_BANK_RAM_SELECT_INJECT_DELAY__SHIFT                                              0xb
2620 #define SQC_DSM_CNTL2A__DATA_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT                                               0xc
2621 #define SQC_DSM_CNTL2A__DATA_TAG_RAM_SELECT_INJECT_DELAY__SHIFT                                               0xe
2622 #define SQC_DSM_CNTL2A__DATA_HIT_FIFO_ENABLE_ERROR_INJECT__SHIFT                                              0xf
2623 #define SQC_DSM_CNTL2A__DATA_HIT_FIFO_SELECT_INJECT_DELAY__SHIFT                                              0x11
2624 #define SQC_DSM_CNTL2A__DATA_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT                                             0x12
2625 #define SQC_DSM_CNTL2A__DATA_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT                                             0x14
2626 #define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT__SHIFT                                         0x15
2627 #define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY__SHIFT                                         0x17
2628 #define SQC_DSM_CNTL2A__DATA_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT                                              0x18
2629 #define SQC_DSM_CNTL2A__DATA_BANK_RAM_SELECT_INJECT_DELAY__SHIFT                                              0x1a
2630 #define SQC_DSM_CNTL2A__INST_TAG_RAM_ENABLE_ERROR_INJECT_MASK                                                 0x00000003L
2631 #define SQC_DSM_CNTL2A__INST_TAG_RAM_SELECT_INJECT_DELAY_MASK                                                 0x00000004L
2632 #define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT_MASK                                         0x00000018L
2633 #define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY_MASK                                         0x00000020L
2634 #define SQC_DSM_CNTL2A__INST_MISS_FIFO_ENABLE_ERROR_INJECT_MASK                                               0x000000C0L
2635 #define SQC_DSM_CNTL2A__INST_MISS_FIFO_SELECT_INJECT_DELAY_MASK                                               0x00000100L
2636 #define SQC_DSM_CNTL2A__INST_BANK_RAM_ENABLE_ERROR_INJECT_MASK                                                0x00000600L
2637 #define SQC_DSM_CNTL2A__INST_BANK_RAM_SELECT_INJECT_DELAY_MASK                                                0x00000800L
2638 #define SQC_DSM_CNTL2A__DATA_TAG_RAM_ENABLE_ERROR_INJECT_MASK                                                 0x00003000L
2639 #define SQC_DSM_CNTL2A__DATA_TAG_RAM_SELECT_INJECT_DELAY_MASK                                                 0x00004000L
2640 #define SQC_DSM_CNTL2A__DATA_HIT_FIFO_ENABLE_ERROR_INJECT_MASK                                                0x00018000L
2641 #define SQC_DSM_CNTL2A__DATA_HIT_FIFO_SELECT_INJECT_DELAY_MASK                                                0x00020000L
2642 #define SQC_DSM_CNTL2A__DATA_MISS_FIFO_ENABLE_ERROR_INJECT_MASK                                               0x000C0000L
2643 #define SQC_DSM_CNTL2A__DATA_MISS_FIFO_SELECT_INJECT_DELAY_MASK                                               0x00100000L
2644 #define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT_MASK                                           0x00600000L
2645 #define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY_MASK                                           0x00800000L
2646 #define SQC_DSM_CNTL2A__DATA_BANK_RAM_ENABLE_ERROR_INJECT_MASK                                                0x03000000L
2647 #define SQC_DSM_CNTL2A__DATA_BANK_RAM_SELECT_INJECT_DELAY_MASK                                                0x04000000L
2648 //SQC_DSM_CNTL2B
2649 #define SQC_DSM_CNTL2B__INST_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT                                               0x0
2650 #define SQC_DSM_CNTL2B__INST_TAG_RAM_SELECT_INJECT_DELAY__SHIFT                                               0x2
2651 #define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT                                       0x3
2652 #define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT                                       0x5
2653 #define SQC_DSM_CNTL2B__INST_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT                                             0x6
2654 #define SQC_DSM_CNTL2B__INST_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT                                             0x8
2655 #define SQC_DSM_CNTL2B__INST_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT                                              0x9
2656 #define SQC_DSM_CNTL2B__INST_BANK_RAM_SELECT_INJECT_DELAY__SHIFT                                              0xb
2657 #define SQC_DSM_CNTL2B__DATA_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT                                               0xc
2658 #define SQC_DSM_CNTL2B__DATA_TAG_RAM_SELECT_INJECT_DELAY__SHIFT                                               0xe
2659 #define SQC_DSM_CNTL2B__DATA_HIT_FIFO_ENABLE_ERROR_INJECT__SHIFT                                              0xf
2660 #define SQC_DSM_CNTL2B__DATA_HIT_FIFO_SELECT_INJECT_DELAY__SHIFT                                              0x11
2661 #define SQC_DSM_CNTL2B__DATA_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT                                             0x12
2662 #define SQC_DSM_CNTL2B__DATA_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT                                             0x14
2663 #define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT__SHIFT                                         0x15
2664 #define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY__SHIFT                                         0x17
2665 #define SQC_DSM_CNTL2B__DATA_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT                                              0x18
2666 #define SQC_DSM_CNTL2B__DATA_BANK_RAM_SELECT_INJECT_DELAY__SHIFT                                              0x1a
2667 #define SQC_DSM_CNTL2B__INST_TAG_RAM_ENABLE_ERROR_INJECT_MASK                                                 0x00000003L
2668 #define SQC_DSM_CNTL2B__INST_TAG_RAM_SELECT_INJECT_DELAY_MASK                                                 0x00000004L
2669 #define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT_MASK                                         0x00000018L
2670 #define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY_MASK                                         0x00000020L
2671 #define SQC_DSM_CNTL2B__INST_MISS_FIFO_ENABLE_ERROR_INJECT_MASK                                               0x000000C0L
2672 #define SQC_DSM_CNTL2B__INST_MISS_FIFO_SELECT_INJECT_DELAY_MASK                                               0x00000100L
2673 #define SQC_DSM_CNTL2B__INST_BANK_RAM_ENABLE_ERROR_INJECT_MASK                                                0x00000600L
2674 #define SQC_DSM_CNTL2B__INST_BANK_RAM_SELECT_INJECT_DELAY_MASK                                                0x00000800L
2675 #define SQC_DSM_CNTL2B__DATA_TAG_RAM_ENABLE_ERROR_INJECT_MASK                                                 0x00003000L
2676 #define SQC_DSM_CNTL2B__DATA_TAG_RAM_SELECT_INJECT_DELAY_MASK                                                 0x00004000L
2677 #define SQC_DSM_CNTL2B__DATA_HIT_FIFO_ENABLE_ERROR_INJECT_MASK                                                0x00018000L
2678 #define SQC_DSM_CNTL2B__DATA_HIT_FIFO_SELECT_INJECT_DELAY_MASK                                                0x00020000L
2679 #define SQC_DSM_CNTL2B__DATA_MISS_FIFO_ENABLE_ERROR_INJECT_MASK                                               0x000C0000L
2680 #define SQC_DSM_CNTL2B__DATA_MISS_FIFO_SELECT_INJECT_DELAY_MASK                                               0x00100000L
2681 #define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT_MASK                                           0x00600000L
2682 #define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY_MASK                                           0x00800000L
2683 #define SQC_DSM_CNTL2B__DATA_BANK_RAM_ENABLE_ERROR_INJECT_MASK                                                0x03000000L
2684 #define SQC_DSM_CNTL2B__DATA_BANK_RAM_SELECT_INJECT_DELAY_MASK                                                0x04000000L
2685 //SQC_DSM_CNTL2E
2686 #define SQC_DSM_CNTL2E__DATA_CU3_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT                                    0x0
2687 #define SQC_DSM_CNTL2E__DATA_CU3_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT                                    0x2
2688 #define SQC_DSM_CNTL2E__DATA_CU3_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT                                       0x3
2689 #define SQC_DSM_CNTL2E__DATA_CU3_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT                                       0x5
2690 #define SQC_DSM_CNTL2E__DATA_CU3_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK                                      0x00000003L
2691 #define SQC_DSM_CNTL2E__DATA_CU3_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK                                      0x00000004L
2692 #define SQC_DSM_CNTL2E__DATA_CU3_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK                                         0x00000018L
2693 #define SQC_DSM_CNTL2E__DATA_CU3_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK                                         0x00000020L
2694 //SQC_EDC_FUE_CNTL
2695 #define SQC_EDC_FUE_CNTL__BLOCK_FUE_FLAGS__SHIFT                                                              0x0
2696 #define SQC_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES__SHIFT                                                        0x10
2697 #define SQC_EDC_FUE_CNTL__BLOCK_FUE_FLAGS_MASK                                                                0x0000FFFFL
2698 #define SQC_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES_MASK                                                          0xFFFF0000L
2699 //SQC_EDC_CNT2
2700 #define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_SEC_COUNT__SHIFT                                                     0x0
2701 #define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_DED_COUNT__SHIFT                                                     0x2
2702 #define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_SEC_COUNT__SHIFT                                                    0x4
2703 #define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_DED_COUNT__SHIFT                                                    0x6
2704 #define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_SEC_COUNT__SHIFT                                                     0x8
2705 #define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_DED_COUNT__SHIFT                                                     0xa
2706 #define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_SEC_COUNT__SHIFT                                                    0xc
2707 #define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_DED_COUNT__SHIFT                                                    0xe
2708 #define SQC_EDC_CNT2__INST_UTCL1_LFIFO_SEC_COUNT__SHIFT                                                       0x10
2709 #define SQC_EDC_CNT2__INST_UTCL1_LFIFO_DED_COUNT__SHIFT                                                       0x12
2710 #define SQC_EDC_CNT2__DATA_BANKA_DIRTY_BIT_RAM_SEC_COUNT__SHIFT                                               0x14
2711 #define SQC_EDC_CNT2__DATA_BANKA_DIRTY_BIT_RAM_DED_COUNT__SHIFT                                               0x16
2712 #define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_SEC_COUNT_MASK                                                       0x00000003L
2713 #define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_DED_COUNT_MASK                                                       0x0000000CL
2714 #define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_SEC_COUNT_MASK                                                      0x00000030L
2715 #define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_DED_COUNT_MASK                                                      0x000000C0L
2716 #define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_SEC_COUNT_MASK                                                       0x00000300L
2717 #define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_DED_COUNT_MASK                                                       0x00000C00L
2718 #define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_SEC_COUNT_MASK                                                      0x00003000L
2719 #define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_DED_COUNT_MASK                                                      0x0000C000L
2720 #define SQC_EDC_CNT2__INST_UTCL1_LFIFO_SEC_COUNT_MASK                                                         0x00030000L
2721 #define SQC_EDC_CNT2__INST_UTCL1_LFIFO_DED_COUNT_MASK                                                         0x000C0000L
2722 #define SQC_EDC_CNT2__DATA_BANKA_DIRTY_BIT_RAM_SEC_COUNT_MASK                                                 0x00300000L
2723 #define SQC_EDC_CNT2__DATA_BANKA_DIRTY_BIT_RAM_DED_COUNT_MASK                                                 0x00C00000L
2724 //SQC_EDC_CNT3
2725 #define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_SEC_COUNT__SHIFT                                                     0x0
2726 #define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_DED_COUNT__SHIFT                                                     0x2
2727 #define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_SEC_COUNT__SHIFT                                                    0x4
2728 #define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_DED_COUNT__SHIFT                                                    0x6
2729 #define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_SEC_COUNT__SHIFT                                                     0x8
2730 #define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_DED_COUNT__SHIFT                                                     0xa
2731 #define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_SEC_COUNT__SHIFT                                                    0xc
2732 #define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_DED_COUNT__SHIFT                                                    0xe
2733 #define SQC_EDC_CNT3__DATA_BANKB_DIRTY_BIT_RAM_SEC_COUNT__SHIFT                                               0x10
2734 #define SQC_EDC_CNT3__DATA_BANKB_DIRTY_BIT_RAM_DED_COUNT__SHIFT                                               0x12
2735 #define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_SEC_COUNT_MASK                                                       0x00000003L
2736 #define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_DED_COUNT_MASK                                                       0x0000000CL
2737 #define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_SEC_COUNT_MASK                                                      0x00000030L
2738 #define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_DED_COUNT_MASK                                                      0x000000C0L
2739 #define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_SEC_COUNT_MASK                                                       0x00000300L
2740 #define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_DED_COUNT_MASK                                                       0x00000C00L
2741 #define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_SEC_COUNT_MASK                                                      0x00003000L
2742 #define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_DED_COUNT_MASK                                                      0x0000C000L
2743 #define SQC_EDC_CNT3__DATA_BANKB_DIRTY_BIT_RAM_SEC_COUNT_MASK                                                 0x00030000L
2744 #define SQC_EDC_CNT3__DATA_BANKB_DIRTY_BIT_RAM_DED_COUNT_MASK                                                 0x000C0000L
2745 //SQC_EDC_PARITY_CNT3
2746 #define SQC_EDC_PARITY_CNT3__INST_BANKA_UTCL1_MISS_FIFO_SEC_COUNT__SHIFT                                      0x0
2747 #define SQC_EDC_PARITY_CNT3__INST_BANKA_UTCL1_MISS_FIFO_DED_COUNT__SHIFT                                      0x2
2748 #define SQC_EDC_PARITY_CNT3__INST_BANKA_MISS_FIFO_SEC_COUNT__SHIFT                                            0x4
2749 #define SQC_EDC_PARITY_CNT3__INST_BANKA_MISS_FIFO_DED_COUNT__SHIFT                                            0x6
2750 #define SQC_EDC_PARITY_CNT3__DATA_BANKA_HIT_FIFO_SEC_COUNT__SHIFT                                             0x8
2751 #define SQC_EDC_PARITY_CNT3__DATA_BANKA_HIT_FIFO_DED_COUNT__SHIFT                                             0xa
2752 #define SQC_EDC_PARITY_CNT3__DATA_BANKA_MISS_FIFO_SEC_COUNT__SHIFT                                            0xc
2753 #define SQC_EDC_PARITY_CNT3__DATA_BANKA_MISS_FIFO_DED_COUNT__SHIFT                                            0xe
2754 #define SQC_EDC_PARITY_CNT3__INST_BANKB_UTCL1_MISS_FIFO_SEC_COUNT__SHIFT                                      0x10
2755 #define SQC_EDC_PARITY_CNT3__INST_BANKB_UTCL1_MISS_FIFO_DED_COUNT__SHIFT                                      0x12
2756 #define SQC_EDC_PARITY_CNT3__INST_BANKB_MISS_FIFO_SEC_COUNT__SHIFT                                            0x14
2757 #define SQC_EDC_PARITY_CNT3__INST_BANKB_MISS_FIFO_DED_COUNT__SHIFT                                            0x16
2758 #define SQC_EDC_PARITY_CNT3__DATA_BANKB_HIT_FIFO_SEC_COUNT__SHIFT                                             0x18
2759 #define SQC_EDC_PARITY_CNT3__DATA_BANKB_HIT_FIFO_DED_COUNT__SHIFT                                             0x1a
2760 #define SQC_EDC_PARITY_CNT3__DATA_BANKB_MISS_FIFO_SEC_COUNT__SHIFT                                            0x1c
2761 #define SQC_EDC_PARITY_CNT3__DATA_BANKB_MISS_FIFO_DED_COUNT__SHIFT                                            0x1e
2762 #define SQC_EDC_PARITY_CNT3__INST_BANKA_UTCL1_MISS_FIFO_SEC_COUNT_MASK                                        0x00000003L
2763 #define SQC_EDC_PARITY_CNT3__INST_BANKA_UTCL1_MISS_FIFO_DED_COUNT_MASK                                        0x0000000CL
2764 #define SQC_EDC_PARITY_CNT3__INST_BANKA_MISS_FIFO_SEC_COUNT_MASK                                              0x00000030L
2765 #define SQC_EDC_PARITY_CNT3__INST_BANKA_MISS_FIFO_DED_COUNT_MASK                                              0x000000C0L
2766 #define SQC_EDC_PARITY_CNT3__DATA_BANKA_HIT_FIFO_SEC_COUNT_MASK                                               0x00000300L
2767 #define SQC_EDC_PARITY_CNT3__DATA_BANKA_HIT_FIFO_DED_COUNT_MASK                                               0x00000C00L
2768 #define SQC_EDC_PARITY_CNT3__DATA_BANKA_MISS_FIFO_SEC_COUNT_MASK                                              0x00003000L
2769 #define SQC_EDC_PARITY_CNT3__DATA_BANKA_MISS_FIFO_DED_COUNT_MASK                                              0x0000C000L
2770 #define SQC_EDC_PARITY_CNT3__INST_BANKB_UTCL1_MISS_FIFO_SEC_COUNT_MASK                                        0x00030000L
2771 #define SQC_EDC_PARITY_CNT3__INST_BANKB_UTCL1_MISS_FIFO_DED_COUNT_MASK                                        0x000C0000L
2772 #define SQC_EDC_PARITY_CNT3__INST_BANKB_MISS_FIFO_SEC_COUNT_MASK                                              0x00300000L
2773 #define SQC_EDC_PARITY_CNT3__INST_BANKB_MISS_FIFO_DED_COUNT_MASK                                              0x00C00000L
2774 #define SQC_EDC_PARITY_CNT3__DATA_BANKB_HIT_FIFO_SEC_COUNT_MASK                                               0x03000000L
2775 #define SQC_EDC_PARITY_CNT3__DATA_BANKB_HIT_FIFO_DED_COUNT_MASK                                               0x0C000000L
2776 #define SQC_EDC_PARITY_CNT3__DATA_BANKB_MISS_FIFO_SEC_COUNT_MASK                                              0x30000000L
2777 #define SQC_EDC_PARITY_CNT3__DATA_BANKB_MISS_FIFO_DED_COUNT_MASK                                              0xC0000000L
2778 //SQ_DEBUG
2779 #define SQ_DEBUG__SINGLE_MEMOP__SHIFT                                                                         0x0
2780 #define SQ_DEBUG__SINGLE_ALU_OP__SHIFT                                                                        0x1
2781 #define SQ_DEBUG__SINGLE_MEMOP_MASK                                                                           0x00000001L
2782 #define SQ_DEBUG__SINGLE_ALU_OP_MASK                                                                          0x00000002L
2783 //SQ_PERF_SNAPSHOT_CTRL
2784 #define SQ_PERF_SNAPSHOT_CTRL__COUNT_INTVAL__SHIFT                                                            0x0
2785 #define SQ_PERF_SNAPSHOT_CTRL__COUNT_SEL__SHIFT                                                               0x5
2786 #define SQ_PERF_SNAPSHOT_CTRL__VMID_MASK__SHIFT                                                               0x6
2787 #define SQ_PERF_SNAPSHOT_CTRL__ENABLE__SHIFT                                                                  0x16
2788 #define SQ_PERF_SNAPSHOT_CTRL__TEST_MODE__SHIFT                                                               0x17
2789 #define SQ_PERF_SNAPSHOT_CTRL__COUNT_INTVAL_MASK                                                              0x0000001FL
2790 #define SQ_PERF_SNAPSHOT_CTRL__COUNT_SEL_MASK                                                                 0x00000020L
2791 #define SQ_PERF_SNAPSHOT_CTRL__VMID_MASK_MASK                                                                 0x003FFFC0L
2792 #define SQ_PERF_SNAPSHOT_CTRL__ENABLE_MASK                                                                    0x00400000L
2793 #define SQ_PERF_SNAPSHOT_CTRL__TEST_MODE_MASK                                                                 0x00800000L
2794 //SQ_DEBUG_FOR_INTERNAL_CTRL
2795 #define SQ_DEBUG_FOR_INTERNAL_CTRL__FLAG_WR_ADDR_MATCH_FLAT_SCRATCH__SHIFT                                    0x0
2796 #define SQ_DEBUG_FOR_INTERNAL_CTRL__FLAG_RD_FLAT_SCRATCH_RETURN_ZERO__SHIFT                                   0x1
2797 #define SQ_DEBUG_FOR_INTERNAL_CTRL__DISABLE_FLAT_SCRATCH_WRITE_PROTECT__SHIFT                                 0x2
2798 #define SQ_DEBUG_FOR_INTERNAL_CTRL__DISABLE_FLAT_SCRATCH_READ_PROTECT__SHIFT                                  0x3
2799 #define SQ_DEBUG_FOR_INTERNAL_CTRL__DISABLE_SNAPSHOT_TRAP_ON_BARRIER__SHIFT                                   0x4
2800 #define SQ_DEBUG_FOR_INTERNAL_CTRL__ENABLE_DED_TRIGGER_HALT__SHIFT                                            0x5
2801 #define SQ_DEBUG_FOR_INTERNAL_CTRL__FLAG_WR_ADDR_MATCH_FLAT_SCRATCH_MASK                                      0x00000001L
2802 #define SQ_DEBUG_FOR_INTERNAL_CTRL__FLAG_RD_FLAT_SCRATCH_RETURN_ZERO_MASK                                     0x00000002L
2803 #define SQ_DEBUG_FOR_INTERNAL_CTRL__DISABLE_FLAT_SCRATCH_WRITE_PROTECT_MASK                                   0x00000004L
2804 #define SQ_DEBUG_FOR_INTERNAL_CTRL__DISABLE_FLAT_SCRATCH_READ_PROTECT_MASK                                    0x00000008L
2805 #define SQ_DEBUG_FOR_INTERNAL_CTRL__DISABLE_SNAPSHOT_TRAP_ON_BARRIER_MASK                                     0x00000010L
2806 #define SQ_DEBUG_FOR_INTERNAL_CTRL__ENABLE_DED_TRIGGER_HALT_MASK                                              0x00000020L
2807 //SQ_REG_TIMESTAMP
2808 #define SQ_REG_TIMESTAMP__TIMESTAMP__SHIFT                                                                    0x0
2809 #define SQ_REG_TIMESTAMP__TIMESTAMP_MASK                                                                      0x000000FFL
2810 //SQ_CMD_TIMESTAMP
2811 #define SQ_CMD_TIMESTAMP__TIMESTAMP__SHIFT                                                                    0x0
2812 #define SQ_CMD_TIMESTAMP__TIMESTAMP_MASK                                                                      0x000000FFL
2813 //SQ_HOSTTRAP_STATUS
2814 #define SQ_HOSTTRAP_STATUS__HTPENDINGCOUNT__SHIFT                                                             0x0
2815 #define SQ_HOSTTRAP_STATUS__HTPENDING_OVERRIDE__SHIFT                                                         0x8
2816 #define SQ_HOSTTRAP_STATUS__HTPENDINGCOUNT_MASK                                                               0x000000FFL
2817 #define SQ_HOSTTRAP_STATUS__HTPENDING_OVERRIDE_MASK                                                           0x00000100L
2818 //SQ_IND_INDEX
2819 #define SQ_IND_INDEX__WAVE_ID__SHIFT                                                                          0x0
2820 #define SQ_IND_INDEX__SIMD_ID__SHIFT                                                                          0x4
2821 #define SQ_IND_INDEX__THREAD_ID__SHIFT                                                                        0x6
2822 #define SQ_IND_INDEX__AUTO_INCR__SHIFT                                                                        0xc
2823 #define SQ_IND_INDEX__FORCE_READ__SHIFT                                                                       0xd
2824 #define SQ_IND_INDEX__READ_TIMEOUT__SHIFT                                                                     0xe
2825 #define SQ_IND_INDEX__UNINDEXED__SHIFT                                                                        0xf
2826 #define SQ_IND_INDEX__INDEX__SHIFT                                                                            0x10
2827 #define SQ_IND_INDEX__WAVE_ID_MASK                                                                            0x0000000FL
2828 #define SQ_IND_INDEX__SIMD_ID_MASK                                                                            0x00000030L
2829 #define SQ_IND_INDEX__THREAD_ID_MASK                                                                          0x00000FC0L
2830 #define SQ_IND_INDEX__AUTO_INCR_MASK                                                                          0x00001000L
2831 #define SQ_IND_INDEX__FORCE_READ_MASK                                                                         0x00002000L
2832 #define SQ_IND_INDEX__READ_TIMEOUT_MASK                                                                       0x00004000L
2833 #define SQ_IND_INDEX__UNINDEXED_MASK                                                                          0x00008000L
2834 #define SQ_IND_INDEX__INDEX_MASK                                                                              0xFFFF0000L
2835 //SQ_IND_DATA
2836 #define SQ_IND_DATA__DATA__SHIFT                                                                              0x0
2837 #define SQ_IND_DATA__DATA_MASK                                                                                0xFFFFFFFFL
2838 //SQ_CONFIG1
2839 #define SQ_CONFIG1__DISABLE_XDL_PORTD_CO_EXEC__SHIFT                                                          0x0
2840 #define SQ_CONFIG1__DISABLE_MGCG_ON_IBUF__SHIFT                                                               0x1
2841 #define SQ_CONFIG1__DISABLE_MGCG_ON_PERF__SHIFT                                                               0x2
2842 #define SQ_CONFIG1__DISABLE_MGCG_ON_EXP__SHIFT                                                                0x3
2843 #define SQ_CONFIG1__DISABLE_MGCG_ON_SCA__SHIFT                                                                0x4
2844 #define SQ_CONFIG1__DISABLE_MGCG_ON_SREG__SHIFT                                                               0x5
2845 #define SQ_CONFIG1__DISABLE_MGCG_ON_VDEC__SHIFT                                                               0x6
2846 #define SQ_CONFIG1__EXTRA_DGEMM_PROTECT_EN__SHIFT                                                             0x7
2847 #define SQ_CONFIG1__DISABLE_VALU_COEXEC__SHIFT                                                                0x8
2848 #define SQ_CONFIG1__DISABLE_WAVE_VALU_COEXEC__SHIFT                                                           0x9
2849 #define SQ_CONFIG1__VGPR_ARB_PLUS1__SHIFT                                                                     0xa
2850 #define SQ_CONFIG1__DISABLE_VGPR_COLLAPSE__SHIFT                                                              0xb
2851 #define SQ_CONFIG1__DISABLE_XNACK_CHECK_IN_RETRY_DISABLE__SHIFT                                               0xc
2852 #define SQ_CONFIG1__DISABLE_BARRIER_ADDR_WATCH__SHIFT                                                         0xd
2853 #define SQ_CONFIG1__DISABLE_BARRIER_MEMVIOL_WAIT__SHIFT                                                       0xe
2854 #define SQ_CONFIG1__DISABLE_BARRIER_MEMVIOL_BACKOFF__SHIFT                                                    0xf
2855 #define SQ_CONFIG1__EXPAND_SP_CMD_FGCG__SHIFT                                                                 0x10
2856 #define SQ_CONFIG1__EXPAND_SP_EXPORT_FGCG__SHIFT                                                              0x11
2857 #define SQ_CONFIG1__DISABLE_MGCG_ON_PERF_SNAP__SHIFT                                                          0x12
2858 #define SQ_CONFIG1__DISABLE_VALU_COEXEC_MODE_AUTO_CLEAN__SHIFT                                                0x13
2859 #define SQ_CONFIG1__SP_CORE1_MGCG_OVERRIDE__SHIFT                                                             0x14
2860 #define SQ_CONFIG1__SP_CORE4_MGCG_OVERRIDE__SHIFT                                                             0x15
2861 #define SQ_CONFIG1__SP_CORE5_MGCG_OVERRIDE__SHIFT                                                             0x16
2862 #define SQ_CONFIG1__DISABLE_SP_VGPR_COLLAPSE__SHIFT                                                           0x17
2863 #define SQ_CONFIG1__SP_FGCG_REP_OVERRIDE__SHIFT                                                               0x18
2864 #define SQ_CONFIG1__DPMACC_MGCG_OVERRIDE__SHIFT                                                               0x19
2865 #define SQ_CONFIG1__XDLMACC_MGCG_OVERRIDE__SHIFT                                                              0x1a
2866 #define SQ_CONFIG1__TRANSMACC_MGCG_OVERRIDE__SHIFT                                                            0x1b
2867 #define SQ_CONFIG1__SPMACC_MGCG_OVERRIDE__SHIFT                                                               0x1c
2868 #define SQ_CONFIG1__DPMACC_DGEMM2X_MGCG_OVERRIDE__SHIFT                                                       0x1d
2869 #define SQ_CONFIG1__DISABLE_SP_VGPR_READ_SKIP__SHIFT                                                          0x1e
2870 #define SQ_CONFIG1__SP_SRC_1ST_BUFFER_MGCG_OVERRIDE__SHIFT                                                    0x1f
2871 #define SQ_CONFIG1__DISABLE_XDL_PORTD_CO_EXEC_MASK                                                            0x00000001L
2872 #define SQ_CONFIG1__DISABLE_MGCG_ON_IBUF_MASK                                                                 0x00000002L
2873 #define SQ_CONFIG1__DISABLE_MGCG_ON_PERF_MASK                                                                 0x00000004L
2874 #define SQ_CONFIG1__DISABLE_MGCG_ON_EXP_MASK                                                                  0x00000008L
2875 #define SQ_CONFIG1__DISABLE_MGCG_ON_SCA_MASK                                                                  0x00000010L
2876 #define SQ_CONFIG1__DISABLE_MGCG_ON_SREG_MASK                                                                 0x00000020L
2877 #define SQ_CONFIG1__DISABLE_MGCG_ON_VDEC_MASK                                                                 0x00000040L
2878 #define SQ_CONFIG1__EXTRA_DGEMM_PROTECT_EN_MASK                                                               0x00000080L
2879 #define SQ_CONFIG1__DISABLE_VALU_COEXEC_MASK                                                                  0x00000100L
2880 #define SQ_CONFIG1__DISABLE_WAVE_VALU_COEXEC_MASK                                                             0x00000200L
2881 #define SQ_CONFIG1__VGPR_ARB_PLUS1_MASK                                                                       0x00000400L
2882 #define SQ_CONFIG1__DISABLE_VGPR_COLLAPSE_MASK                                                                0x00000800L
2883 #define SQ_CONFIG1__DISABLE_XNACK_CHECK_IN_RETRY_DISABLE_MASK                                                 0x00001000L
2884 #define SQ_CONFIG1__DISABLE_BARRIER_ADDR_WATCH_MASK                                                           0x00002000L
2885 #define SQ_CONFIG1__DISABLE_BARRIER_MEMVIOL_WAIT_MASK                                                         0x00004000L
2886 #define SQ_CONFIG1__DISABLE_BARRIER_MEMVIOL_BACKOFF_MASK                                                      0x00008000L
2887 #define SQ_CONFIG1__EXPAND_SP_CMD_FGCG_MASK                                                                   0x00010000L
2888 #define SQ_CONFIG1__EXPAND_SP_EXPORT_FGCG_MASK                                                                0x00020000L
2889 #define SQ_CONFIG1__DISABLE_MGCG_ON_PERF_SNAP_MASK                                                            0x00040000L
2890 #define SQ_CONFIG1__DISABLE_VALU_COEXEC_MODE_AUTO_CLEAN_MASK                                                  0x00080000L
2891 #define SQ_CONFIG1__SP_CORE1_MGCG_OVERRIDE_MASK                                                               0x00100000L
2892 #define SQ_CONFIG1__SP_CORE4_MGCG_OVERRIDE_MASK                                                               0x00200000L
2893 #define SQ_CONFIG1__SP_CORE5_MGCG_OVERRIDE_MASK                                                               0x00400000L
2894 #define SQ_CONFIG1__DISABLE_SP_VGPR_COLLAPSE_MASK                                                             0x00800000L
2895 #define SQ_CONFIG1__SP_FGCG_REP_OVERRIDE_MASK                                                                 0x01000000L
2896 #define SQ_CONFIG1__DPMACC_MGCG_OVERRIDE_MASK                                                                 0x02000000L
2897 #define SQ_CONFIG1__XDLMACC_MGCG_OVERRIDE_MASK                                                                0x04000000L
2898 #define SQ_CONFIG1__TRANSMACC_MGCG_OVERRIDE_MASK                                                              0x08000000L
2899 #define SQ_CONFIG1__SPMACC_MGCG_OVERRIDE_MASK                                                                 0x10000000L
2900 #define SQ_CONFIG1__DPMACC_DGEMM2X_MGCG_OVERRIDE_MASK                                                         0x20000000L
2901 #define SQ_CONFIG1__DISABLE_SP_VGPR_READ_SKIP_MASK                                                            0x40000000L
2902 #define SQ_CONFIG1__SP_SRC_1ST_BUFFER_MGCG_OVERRIDE_MASK                                                      0x80000000L
2903 //SQ_CMD
2904 #define SQ_CMD__CMD__SHIFT                                                                                    0x0
2905 #define SQ_CMD__MODE__SHIFT                                                                                   0x4
2906 #define SQ_CMD__CHECK_VMID__SHIFT                                                                             0x7
2907 #define SQ_CMD__DATA__SHIFT                                                                                   0x8
2908 #define SQ_CMD__WAVE_ID__SHIFT                                                                                0x10
2909 #define SQ_CMD__SIMD_ID__SHIFT                                                                                0x14
2910 #define SQ_CMD__QUEUE_ID__SHIFT                                                                               0x18
2911 #define SQ_CMD__VM_ID__SHIFT                                                                                  0x1c
2912 #define SQ_CMD__CMD_MASK                                                                                      0x00000007L
2913 #define SQ_CMD__MODE_MASK                                                                                     0x00000070L
2914 #define SQ_CMD__CHECK_VMID_MASK                                                                               0x00000080L
2915 #define SQ_CMD__DATA_MASK                                                                                     0x00000F00L
2916 #define SQ_CMD__WAVE_ID_MASK                                                                                  0x000F0000L
2917 #define SQ_CMD__SIMD_ID_MASK                                                                                  0x00300000L
2918 #define SQ_CMD__QUEUE_ID_MASK                                                                                 0x07000000L
2919 #define SQ_CMD__VM_ID_MASK                                                                                    0xF0000000L
2920 //SQ_TIME_HI
2921 #define SQ_TIME_HI__TIME__SHIFT                                                                               0x0
2922 #define SQ_TIME_HI__TIME_MASK                                                                                 0xFFFFFFFFL
2923 //SQ_TIME_LO
2924 #define SQ_TIME_LO__TIME__SHIFT                                                                               0x0
2925 #define SQ_TIME_LO__TIME_MASK                                                                                 0xFFFFFFFFL
2926 //SQ_DS_0
2927 #define SQ_DS_0__OFFSET0__SHIFT                                                                               0x0
2928 #define SQ_DS_0__OFFSET1__SHIFT                                                                               0x8
2929 #define SQ_DS_0__GDS__SHIFT                                                                                   0x10
2930 #define SQ_DS_0__OP__SHIFT                                                                                    0x11
2931 #define SQ_DS_0__ACC__SHIFT                                                                                   0x19
2932 #define SQ_DS_0__ENCODING__SHIFT                                                                              0x1a
2933 #define SQ_DS_0__OFFSET0_MASK                                                                                 0x000000FFL
2934 #define SQ_DS_0__OFFSET1_MASK                                                                                 0x0000FF00L
2935 #define SQ_DS_0__GDS_MASK                                                                                     0x00010000L
2936 #define SQ_DS_0__OP_MASK                                                                                      0x01FE0000L
2937 #define SQ_DS_0__ACC_MASK                                                                                     0x02000000L
2938 #define SQ_DS_0__ENCODING_MASK                                                                                0xFC000000L
2939 //SQ_DS_1
2940 #define SQ_DS_1__ADDR__SHIFT                                                                                  0x0
2941 #define SQ_DS_1__DATA0__SHIFT                                                                                 0x8
2942 #define SQ_DS_1__DATA1__SHIFT                                                                                 0x10
2943 #define SQ_DS_1__VDST__SHIFT                                                                                  0x18
2944 #define SQ_DS_1__ADDR_MASK                                                                                    0x000000FFL
2945 #define SQ_DS_1__DATA0_MASK                                                                                   0x0000FF00L
2946 #define SQ_DS_1__DATA1_MASK                                                                                   0x00FF0000L
2947 #define SQ_DS_1__VDST_MASK                                                                                    0xFF000000L
2948 //SQ_EXP_0
2949 #define SQ_EXP_0__EN__SHIFT                                                                                   0x0
2950 #define SQ_EXP_0__TGT__SHIFT                                                                                  0x4
2951 #define SQ_EXP_0__COMPR__SHIFT                                                                                0xa
2952 #define SQ_EXP_0__DONE__SHIFT                                                                                 0xb
2953 #define SQ_EXP_0__VM__SHIFT                                                                                   0xc
2954 #define SQ_EXP_0__ENCODING__SHIFT                                                                             0x1a
2955 #define SQ_EXP_0__EN_MASK                                                                                     0x0000000FL
2956 #define SQ_EXP_0__TGT_MASK                                                                                    0x000003F0L
2957 #define SQ_EXP_0__COMPR_MASK                                                                                  0x00000400L
2958 #define SQ_EXP_0__DONE_MASK                                                                                   0x00000800L
2959 #define SQ_EXP_0__VM_MASK                                                                                     0x00001000L
2960 #define SQ_EXP_0__ENCODING_MASK                                                                               0xFC000000L
2961 //SQ_EXP_1
2962 #define SQ_EXP_1__VSRC0__SHIFT                                                                                0x0
2963 #define SQ_EXP_1__VSRC1__SHIFT                                                                                0x8
2964 #define SQ_EXP_1__VSRC2__SHIFT                                                                                0x10
2965 #define SQ_EXP_1__VSRC3__SHIFT                                                                                0x18
2966 #define SQ_EXP_1__VSRC0_MASK                                                                                  0x000000FFL
2967 #define SQ_EXP_1__VSRC1_MASK                                                                                  0x0000FF00L
2968 #define SQ_EXP_1__VSRC2_MASK                                                                                  0x00FF0000L
2969 #define SQ_EXP_1__VSRC3_MASK                                                                                  0xFF000000L
2970 //SQ_FLAT_0
2971 #define SQ_FLAT_0__OFFSET__SHIFT                                                                              0x0
2972 #define SQ_FLAT_0__SVE__SHIFT                                                                                 0xd
2973 #define SQ_FLAT_0__SEG__SHIFT                                                                                 0xe
2974 #define SQ_FLAT_0__SC0__SHIFT                                                                                 0x10
2975 #define SQ_FLAT_0__NT__SHIFT                                                                                  0x11
2976 #define SQ_FLAT_0__OP__SHIFT                                                                                  0x12
2977 #define SQ_FLAT_0__SC1__SHIFT                                                                                 0x19
2978 #define SQ_FLAT_0__ENCODING__SHIFT                                                                            0x1a
2979 #define SQ_FLAT_0__OFFSET_MASK                                                                                0x00000FFFL
2980 #define SQ_FLAT_0__SVE_MASK                                                                                   0x00002000L
2981 #define SQ_FLAT_0__SEG_MASK                                                                                   0x0000C000L
2982 #define SQ_FLAT_0__SC0_MASK                                                                                   0x00010000L
2983 #define SQ_FLAT_0__NT_MASK                                                                                    0x00020000L
2984 #define SQ_FLAT_0__OP_MASK                                                                                    0x01FC0000L
2985 #define SQ_FLAT_0__SC1_MASK                                                                                   0x02000000L
2986 #define SQ_FLAT_0__ENCODING_MASK                                                                              0xFC000000L
2987 //SQ_FLAT_1
2988 #define SQ_FLAT_1__ADDR__SHIFT                                                                                0x0
2989 #define SQ_FLAT_1__DATA__SHIFT                                                                                0x8
2990 #define SQ_FLAT_1__SADDR__SHIFT                                                                               0x10
2991 #define SQ_FLAT_1__ACC__SHIFT                                                                                 0x17
2992 #define SQ_FLAT_1__VDST__SHIFT                                                                                0x18
2993 #define SQ_FLAT_1__ADDR_MASK                                                                                  0x000000FFL
2994 #define SQ_FLAT_1__DATA_MASK                                                                                  0x0000FF00L
2995 #define SQ_FLAT_1__SADDR_MASK                                                                                 0x007F0000L
2996 #define SQ_FLAT_1__ACC_MASK                                                                                   0x00800000L
2997 #define SQ_FLAT_1__VDST_MASK                                                                                  0xFF000000L
2998 //SQ_GLBL_0
2999 #define SQ_GLBL_0__OFFSET__SHIFT                                                                              0x0
3000 #define SQ_GLBL_0__SVE__SHIFT                                                                                 0xd
3001 #define SQ_GLBL_0__SEG__SHIFT                                                                                 0xe
3002 #define SQ_GLBL_0__SC0__SHIFT                                                                                 0x10
3003 #define SQ_GLBL_0__NT__SHIFT                                                                                  0x11
3004 #define SQ_GLBL_0__OP__SHIFT                                                                                  0x12
3005 #define SQ_GLBL_0__SC1__SHIFT                                                                                 0x19
3006 #define SQ_GLBL_0__ENCODING__SHIFT                                                                            0x1a
3007 #define SQ_GLBL_0__OFFSET_MASK                                                                                0x00001FFFL
3008 #define SQ_GLBL_0__SVE_MASK                                                                                   0x00002000L
3009 #define SQ_GLBL_0__SEG_MASK                                                                                   0x0000C000L
3010 #define SQ_GLBL_0__SC0_MASK                                                                                   0x00010000L
3011 #define SQ_GLBL_0__NT_MASK                                                                                    0x00020000L
3012 #define SQ_GLBL_0__OP_MASK                                                                                    0x01FC0000L
3013 #define SQ_GLBL_0__SC1_MASK                                                                                   0x02000000L
3014 #define SQ_GLBL_0__ENCODING_MASK                                                                              0xFC000000L
3015 //SQ_GLBL_1
3016 #define SQ_GLBL_1__ADDR__SHIFT                                                                                0x0
3017 #define SQ_GLBL_1__DATA__SHIFT                                                                                0x8
3018 #define SQ_GLBL_1__SADDR__SHIFT                                                                               0x10
3019 #define SQ_GLBL_1__ACC__SHIFT                                                                                 0x17
3020 #define SQ_GLBL_1__VDST__SHIFT                                                                                0x18
3021 #define SQ_GLBL_1__ADDR_MASK                                                                                  0x000000FFL
3022 #define SQ_GLBL_1__DATA_MASK                                                                                  0x0000FF00L
3023 #define SQ_GLBL_1__SADDR_MASK                                                                                 0x007F0000L
3024 #define SQ_GLBL_1__ACC_MASK                                                                                   0x00800000L
3025 #define SQ_GLBL_1__VDST_MASK                                                                                  0xFF000000L
3026 //SQ_INST
3027 #define SQ_INST__ENCODING__SHIFT                                                                              0x0
3028 #define SQ_INST__ENCODING_MASK                                                                                0xFFFFFFFFL
3029 //SQ_MIMG_0
3030 #define SQ_MIMG_0__OPM__SHIFT                                                                                 0x0
3031 #define SQ_MIMG_0__SC1__SHIFT                                                                                 0x7
3032 #define SQ_MIMG_0__DMASK__SHIFT                                                                               0x8
3033 #define SQ_MIMG_0__UNORM__SHIFT                                                                               0xc
3034 #define SQ_MIMG_0__SC0__SHIFT                                                                                 0xd
3035 #define SQ_MIMG_0__DA__SHIFT                                                                                  0xe
3036 #define SQ_MIMG_0__A16__SHIFT                                                                                 0xf
3037 #define SQ_MIMG_0__ACC__SHIFT                                                                                 0x10
3038 #define SQ_MIMG_0__LWE__SHIFT                                                                                 0x11
3039 #define SQ_MIMG_0__OP__SHIFT                                                                                  0x12
3040 #define SQ_MIMG_0__NT__SHIFT                                                                                  0x19
3041 #define SQ_MIMG_0__ENCODING__SHIFT                                                                            0x1a
3042 #define SQ_MIMG_0__OPM_MASK                                                                                   0x00000001L
3043 #define SQ_MIMG_0__SC1_MASK                                                                                   0x00000080L
3044 #define SQ_MIMG_0__DMASK_MASK                                                                                 0x00000F00L
3045 #define SQ_MIMG_0__UNORM_MASK                                                                                 0x00001000L
3046 #define SQ_MIMG_0__SC0_MASK                                                                                   0x00002000L
3047 #define SQ_MIMG_0__DA_MASK                                                                                    0x00004000L
3048 #define SQ_MIMG_0__A16_MASK                                                                                   0x00008000L
3049 #define SQ_MIMG_0__ACC_MASK                                                                                   0x00010000L
3050 #define SQ_MIMG_0__LWE_MASK                                                                                   0x00020000L
3051 #define SQ_MIMG_0__OP_MASK                                                                                    0x01FC0000L
3052 #define SQ_MIMG_0__NT_MASK                                                                                    0x02000000L
3053 #define SQ_MIMG_0__ENCODING_MASK                                                                              0xFC000000L
3054 //SQ_MIMG_1
3055 #define SQ_MIMG_1__VADDR__SHIFT                                                                               0x0
3056 #define SQ_MIMG_1__VDATA__SHIFT                                                                               0x8
3057 #define SQ_MIMG_1__SRSRC__SHIFT                                                                               0x10
3058 #define SQ_MIMG_1__SSAMP__SHIFT                                                                               0x15
3059 #define SQ_MIMG_1__D16__SHIFT                                                                                 0x1f
3060 #define SQ_MIMG_1__VADDR_MASK                                                                                 0x000000FFL
3061 #define SQ_MIMG_1__VDATA_MASK                                                                                 0x0000FF00L
3062 #define SQ_MIMG_1__SRSRC_MASK                                                                                 0x001F0000L
3063 #define SQ_MIMG_1__SSAMP_MASK                                                                                 0x03E00000L
3064 #define SQ_MIMG_1__D16_MASK                                                                                   0x80000000L
3065 //SQ_MTBUF_0
3066 #define SQ_MTBUF_0__OFFSET__SHIFT                                                                             0x0
3067 #define SQ_MTBUF_0__OFFEN__SHIFT                                                                              0xc
3068 #define SQ_MTBUF_0__IDXEN__SHIFT                                                                              0xd
3069 #define SQ_MTBUF_0__SC0__SHIFT                                                                                0xe
3070 #define SQ_MTBUF_0__OP__SHIFT                                                                                 0xf
3071 #define SQ_MTBUF_0__DFMT__SHIFT                                                                               0x13
3072 #define SQ_MTBUF_0__NFMT__SHIFT                                                                               0x17
3073 #define SQ_MTBUF_0__ENCODING__SHIFT                                                                           0x1a
3074 #define SQ_MTBUF_0__OFFSET_MASK                                                                               0x00000FFFL
3075 #define SQ_MTBUF_0__OFFEN_MASK                                                                                0x00001000L
3076 #define SQ_MTBUF_0__IDXEN_MASK                                                                                0x00002000L
3077 #define SQ_MTBUF_0__SC0_MASK                                                                                  0x00004000L
3078 #define SQ_MTBUF_0__OP_MASK                                                                                   0x00078000L
3079 #define SQ_MTBUF_0__DFMT_MASK                                                                                 0x00780000L
3080 #define SQ_MTBUF_0__NFMT_MASK                                                                                 0x03800000L
3081 #define SQ_MTBUF_0__ENCODING_MASK                                                                             0xFC000000L
3082 //SQ_MTBUF_1
3083 #define SQ_MTBUF_1__VADDR__SHIFT                                                                              0x0
3084 #define SQ_MTBUF_1__VDATA__SHIFT                                                                              0x8
3085 #define SQ_MTBUF_1__SRSRC__SHIFT                                                                              0x10
3086 #define SQ_MTBUF_1__SC1__SHIFT                                                                                0x15
3087 #define SQ_MTBUF_1__NT__SHIFT                                                                                 0x16
3088 #define SQ_MTBUF_1__ACC__SHIFT                                                                                0x17
3089 #define SQ_MTBUF_1__SOFFSET__SHIFT                                                                            0x18
3090 #define SQ_MTBUF_1__VADDR_MASK                                                                                0x000000FFL
3091 #define SQ_MTBUF_1__VDATA_MASK                                                                                0x0000FF00L
3092 #define SQ_MTBUF_1__SRSRC_MASK                                                                                0x001F0000L
3093 #define SQ_MTBUF_1__SC1_MASK                                                                                  0x00200000L
3094 #define SQ_MTBUF_1__NT_MASK                                                                                   0x00400000L
3095 #define SQ_MTBUF_1__ACC_MASK                                                                                  0x00800000L
3096 #define SQ_MTBUF_1__SOFFSET_MASK                                                                              0xFF000000L
3097 //SQ_MUBUF_0
3098 #define SQ_MUBUF_0__OFFSET__SHIFT                                                                             0x0
3099 #define SQ_MUBUF_0__OFFEN__SHIFT                                                                              0xc
3100 #define SQ_MUBUF_0__IDXEN__SHIFT                                                                              0xd
3101 #define SQ_MUBUF_0__SC0__SHIFT                                                                                0xe
3102 #define SQ_MUBUF_0__SC1__SHIFT                                                                                0xf
3103 #define SQ_MUBUF_0__LDS__SHIFT                                                                                0x10
3104 #define SQ_MUBUF_0__NT__SHIFT                                                                                 0x11
3105 #define SQ_MUBUF_0__OP__SHIFT                                                                                 0x12
3106 #define SQ_MUBUF_0__ENCODING__SHIFT                                                                           0x1a
3107 #define SQ_MUBUF_0__OFFSET_MASK                                                                               0x00000FFFL
3108 #define SQ_MUBUF_0__OFFEN_MASK                                                                                0x00001000L
3109 #define SQ_MUBUF_0__IDXEN_MASK                                                                                0x00002000L
3110 #define SQ_MUBUF_0__SC0_MASK                                                                                  0x00004000L
3111 #define SQ_MUBUF_0__SC1_MASK                                                                                  0x00008000L
3112 #define SQ_MUBUF_0__LDS_MASK                                                                                  0x00010000L
3113 #define SQ_MUBUF_0__NT_MASK                                                                                   0x00020000L
3114 #define SQ_MUBUF_0__OP_MASK                                                                                   0x01FC0000L
3115 #define SQ_MUBUF_0__ENCODING_MASK                                                                             0xFC000000L
3116 //SQ_MUBUF_1
3117 #define SQ_MUBUF_1__VADDR__SHIFT                                                                              0x0
3118 #define SQ_MUBUF_1__VDATA__SHIFT                                                                              0x8
3119 #define SQ_MUBUF_1__SRSRC__SHIFT                                                                              0x10
3120 #define SQ_MUBUF_1__ACC__SHIFT                                                                                0x17
3121 #define SQ_MUBUF_1__SOFFSET__SHIFT                                                                            0x18
3122 #define SQ_MUBUF_1__VADDR_MASK                                                                                0x000000FFL
3123 #define SQ_MUBUF_1__VDATA_MASK                                                                                0x0000FF00L
3124 #define SQ_MUBUF_1__SRSRC_MASK                                                                                0x001F0000L
3125 #define SQ_MUBUF_1__ACC_MASK                                                                                  0x00800000L
3126 #define SQ_MUBUF_1__SOFFSET_MASK                                                                              0xFF000000L
3127 //SQ_SCRATCH_0
3128 #define SQ_SCRATCH_0__OFFSET__SHIFT                                                                           0x0
3129 #define SQ_SCRATCH_0__SVE__SHIFT                                                                              0xd
3130 #define SQ_SCRATCH_0__SEG__SHIFT                                                                              0xe
3131 #define SQ_SCRATCH_0__SC0__SHIFT                                                                              0x10
3132 #define SQ_SCRATCH_0__NT__SHIFT                                                                               0x11
3133 #define SQ_SCRATCH_0__OP__SHIFT                                                                               0x12
3134 #define SQ_SCRATCH_0__SC1__SHIFT                                                                              0x19
3135 #define SQ_SCRATCH_0__ENCODING__SHIFT                                                                         0x1a
3136 #define SQ_SCRATCH_0__OFFSET_MASK                                                                             0x00001FFFL
3137 #define SQ_SCRATCH_0__SVE_MASK                                                                                0x00002000L
3138 #define SQ_SCRATCH_0__SEG_MASK                                                                                0x0000C000L
3139 #define SQ_SCRATCH_0__SC0_MASK                                                                                0x00010000L
3140 #define SQ_SCRATCH_0__NT_MASK                                                                                 0x00020000L
3141 #define SQ_SCRATCH_0__OP_MASK                                                                                 0x01FC0000L
3142 #define SQ_SCRATCH_0__SC1_MASK                                                                                0x02000000L
3143 #define SQ_SCRATCH_0__ENCODING_MASK                                                                           0xFC000000L
3144 //SQ_SCRATCH_1
3145 #define SQ_SCRATCH_1__ADDR__SHIFT                                                                             0x0
3146 #define SQ_SCRATCH_1__DATA__SHIFT                                                                             0x8
3147 #define SQ_SCRATCH_1__SADDR__SHIFT                                                                            0x10
3148 #define SQ_SCRATCH_1__ACC__SHIFT                                                                              0x17
3149 #define SQ_SCRATCH_1__VDST__SHIFT                                                                             0x18
3150 #define SQ_SCRATCH_1__ADDR_MASK                                                                               0x000000FFL
3151 #define SQ_SCRATCH_1__DATA_MASK                                                                               0x0000FF00L
3152 #define SQ_SCRATCH_1__SADDR_MASK                                                                              0x007F0000L
3153 #define SQ_SCRATCH_1__ACC_MASK                                                                                0x00800000L
3154 #define SQ_SCRATCH_1__VDST_MASK                                                                               0xFF000000L
3155 //SQ_SMEM_0
3156 #define SQ_SMEM_0__SBASE__SHIFT                                                                               0x0
3157 #define SQ_SMEM_0__SDATA__SHIFT                                                                               0x6
3158 #define SQ_SMEM_0__SOFFSET_EN__SHIFT                                                                          0xe
3159 #define SQ_SMEM_0__NV__SHIFT                                                                                  0xf
3160 #define SQ_SMEM_0__GLC__SHIFT                                                                                 0x10
3161 #define SQ_SMEM_0__IMM__SHIFT                                                                                 0x11
3162 #define SQ_SMEM_0__OP__SHIFT                                                                                  0x12
3163 #define SQ_SMEM_0__ENCODING__SHIFT                                                                            0x1a
3164 #define SQ_SMEM_0__SBASE_MASK                                                                                 0x0000003FL
3165 #define SQ_SMEM_0__SDATA_MASK                                                                                 0x00001FC0L
3166 #define SQ_SMEM_0__SOFFSET_EN_MASK                                                                            0x00004000L
3167 #define SQ_SMEM_0__NV_MASK                                                                                    0x00008000L
3168 #define SQ_SMEM_0__GLC_MASK                                                                                   0x00010000L
3169 #define SQ_SMEM_0__IMM_MASK                                                                                   0x00020000L
3170 #define SQ_SMEM_0__OP_MASK                                                                                    0x03FC0000L
3171 #define SQ_SMEM_0__ENCODING_MASK                                                                              0xFC000000L
3172 //SQ_SMEM_1
3173 #define SQ_SMEM_1__OFFSET__SHIFT                                                                              0x0
3174 #define SQ_SMEM_1__SOFFSET__SHIFT                                                                             0x19
3175 #define SQ_SMEM_1__OFFSET_MASK                                                                                0x001FFFFFL
3176 #define SQ_SMEM_1__SOFFSET_MASK                                                                               0xFE000000L
3177 //SQ_SOP1
3178 #define SQ_SOP1__SSRC0__SHIFT                                                                                 0x0
3179 #define SQ_SOP1__OP__SHIFT                                                                                    0x8
3180 #define SQ_SOP1__SDST__SHIFT                                                                                  0x10
3181 #define SQ_SOP1__ENCODING__SHIFT                                                                              0x17
3182 #define SQ_SOP1__SSRC0_MASK                                                                                   0x000000FFL
3183 #define SQ_SOP1__OP_MASK                                                                                      0x0000FF00L
3184 #define SQ_SOP1__SDST_MASK                                                                                    0x007F0000L
3185 #define SQ_SOP1__ENCODING_MASK                                                                                0xFF800000L
3186 //SQ_SOP2
3187 #define SQ_SOP2__SSRC0__SHIFT                                                                                 0x0
3188 #define SQ_SOP2__SSRC1__SHIFT                                                                                 0x8
3189 #define SQ_SOP2__SDST__SHIFT                                                                                  0x10
3190 #define SQ_SOP2__OP__SHIFT                                                                                    0x17
3191 #define SQ_SOP2__ENCODING__SHIFT                                                                              0x1e
3192 #define SQ_SOP2__SSRC0_MASK                                                                                   0x000000FFL
3193 #define SQ_SOP2__SSRC1_MASK                                                                                   0x0000FF00L
3194 #define SQ_SOP2__SDST_MASK                                                                                    0x007F0000L
3195 #define SQ_SOP2__OP_MASK                                                                                      0x3F800000L
3196 #define SQ_SOP2__ENCODING_MASK                                                                                0xC0000000L
3197 //SQ_SOPC
3198 #define SQ_SOPC__SSRC0__SHIFT                                                                                 0x0
3199 #define SQ_SOPC__SSRC1__SHIFT                                                                                 0x8
3200 #define SQ_SOPC__OP__SHIFT                                                                                    0x10
3201 #define SQ_SOPC__ENCODING__SHIFT                                                                              0x17
3202 #define SQ_SOPC__SSRC0_MASK                                                                                   0x000000FFL
3203 #define SQ_SOPC__SSRC1_MASK                                                                                   0x0000FF00L
3204 #define SQ_SOPC__OP_MASK                                                                                      0x007F0000L
3205 #define SQ_SOPC__ENCODING_MASK                                                                                0xFF800000L
3206 //SQ_SOPK
3207 #define SQ_SOPK__SIMM16__SHIFT                                                                                0x0
3208 #define SQ_SOPK__SDST__SHIFT                                                                                  0x10
3209 #define SQ_SOPK__OP__SHIFT                                                                                    0x17
3210 #define SQ_SOPK__ENCODING__SHIFT                                                                              0x1c
3211 #define SQ_SOPK__SIMM16_MASK                                                                                  0x0000FFFFL
3212 #define SQ_SOPK__SDST_MASK                                                                                    0x007F0000L
3213 #define SQ_SOPK__OP_MASK                                                                                      0x0F800000L
3214 #define SQ_SOPK__ENCODING_MASK                                                                                0xF0000000L
3215 //SQ_SOPP
3216 #define SQ_SOPP__SIMM16__SHIFT                                                                                0x0
3217 #define SQ_SOPP__OP__SHIFT                                                                                    0x10
3218 #define SQ_SOPP__ENCODING__SHIFT                                                                              0x17
3219 #define SQ_SOPP__SIMM16_MASK                                                                                  0x0000FFFFL
3220 #define SQ_SOPP__OP_MASK                                                                                      0x007F0000L
3221 #define SQ_SOPP__ENCODING_MASK                                                                                0xFF800000L
3222 //SQ_VINTRP
3223 #define SQ_VINTRP__VSRC__SHIFT                                                                                0x0
3224 #define SQ_VINTRP__ATTRCHAN__SHIFT                                                                            0x8
3225 #define SQ_VINTRP__ATTR__SHIFT                                                                                0xa
3226 #define SQ_VINTRP__OP__SHIFT                                                                                  0x10
3227 #define SQ_VINTRP__VDST__SHIFT                                                                                0x12
3228 #define SQ_VINTRP__ENCODING__SHIFT                                                                            0x1a
3229 #define SQ_VINTRP__VSRC_MASK                                                                                  0x000000FFL
3230 #define SQ_VINTRP__ATTRCHAN_MASK                                                                              0x00000300L
3231 #define SQ_VINTRP__ATTR_MASK                                                                                  0x0000FC00L
3232 #define SQ_VINTRP__OP_MASK                                                                                    0x00030000L
3233 #define SQ_VINTRP__VDST_MASK                                                                                  0x03FC0000L
3234 #define SQ_VINTRP__ENCODING_MASK                                                                              0xFC000000L
3235 //SQ_VOP1
3236 #define SQ_VOP1__SRC0__SHIFT                                                                                  0x0
3237 #define SQ_VOP1__OP__SHIFT                                                                                    0x9
3238 #define SQ_VOP1__VDST__SHIFT                                                                                  0x11
3239 #define SQ_VOP1__ENCODING__SHIFT                                                                              0x19
3240 #define SQ_VOP1__SRC0_MASK                                                                                    0x000001FFL
3241 #define SQ_VOP1__OP_MASK                                                                                      0x0001FE00L
3242 #define SQ_VOP1__VDST_MASK                                                                                    0x01FE0000L
3243 #define SQ_VOP1__ENCODING_MASK                                                                                0xFE000000L
3244 //SQ_VOP2
3245 #define SQ_VOP2__SRC0__SHIFT                                                                                  0x0
3246 #define SQ_VOP2__VSRC1__SHIFT                                                                                 0x9
3247 #define SQ_VOP2__VDST__SHIFT                                                                                  0x11
3248 #define SQ_VOP2__OP__SHIFT                                                                                    0x19
3249 #define SQ_VOP2__ENCODING__SHIFT                                                                              0x1f
3250 #define SQ_VOP2__SRC0_MASK                                                                                    0x000001FFL
3251 #define SQ_VOP2__VSRC1_MASK                                                                                   0x0001FE00L
3252 #define SQ_VOP2__VDST_MASK                                                                                    0x01FE0000L
3253 #define SQ_VOP2__OP_MASK                                                                                      0x7E000000L
3254 #define SQ_VOP2__ENCODING_MASK                                                                                0x80000000L
3255 //SQ_VOP3P_0
3256 #define SQ_VOP3P_0__VDST__SHIFT                                                                               0x0
3257 #define SQ_VOP3P_0__NEG_HI__SHIFT                                                                             0x8
3258 #define SQ_VOP3P_0__OP_SEL__SHIFT                                                                             0xb
3259 #define SQ_VOP3P_0__OP_SEL_HI_2__SHIFT                                                                        0xe
3260 #define SQ_VOP3P_0__CLAMP__SHIFT                                                                              0xf
3261 #define SQ_VOP3P_0__OP__SHIFT                                                                                 0x10
3262 #define SQ_VOP3P_0__ENCODING__SHIFT                                                                           0x17
3263 #define SQ_VOP3P_0__VDST_MASK                                                                                 0x000000FFL
3264 #define SQ_VOP3P_0__NEG_HI_MASK                                                                               0x00000700L
3265 #define SQ_VOP3P_0__OP_SEL_MASK                                                                               0x00003800L
3266 #define SQ_VOP3P_0__OP_SEL_HI_2_MASK                                                                          0x00004000L
3267 #define SQ_VOP3P_0__CLAMP_MASK                                                                                0x00008000L
3268 #define SQ_VOP3P_0__OP_MASK                                                                                   0x007F0000L
3269 #define SQ_VOP3P_0__ENCODING_MASK                                                                             0xFF800000L
3270 //SQ_VOP3P_1
3271 #define SQ_VOP3P_1__SRC0__SHIFT                                                                               0x0
3272 #define SQ_VOP3P_1__SRC1__SHIFT                                                                               0x9
3273 #define SQ_VOP3P_1__SRC2__SHIFT                                                                               0x12
3274 #define SQ_VOP3P_1__OP_SEL_HI__SHIFT                                                                          0x1b
3275 #define SQ_VOP3P_1__NEG__SHIFT                                                                                0x1d
3276 #define SQ_VOP3P_1__SRC0_MASK                                                                                 0x000001FFL
3277 #define SQ_VOP3P_1__SRC1_MASK                                                                                 0x0003FE00L
3278 #define SQ_VOP3P_1__SRC2_MASK                                                                                 0x07FC0000L
3279 #define SQ_VOP3P_1__OP_SEL_HI_MASK                                                                            0x18000000L
3280 #define SQ_VOP3P_1__NEG_MASK                                                                                  0xE0000000L
3281 //SQ_VOP3P_MFMA_0
3282 #define SQ_VOP3P_MFMA_0__VDST__SHIFT                                                                          0x0
3283 #define SQ_VOP3P_MFMA_0__CBSZ__SHIFT                                                                          0x8
3284 #define SQ_VOP3P_MFMA_0__ABID__SHIFT                                                                          0xb
3285 #define SQ_VOP3P_MFMA_0__ACC_CD__SHIFT                                                                        0xf
3286 #define SQ_VOP3P_MFMA_0__OP__SHIFT                                                                            0x10
3287 #define SQ_VOP3P_MFMA_0__ENCODING__SHIFT                                                                      0x17
3288 #define SQ_VOP3P_MFMA_0__VDST_MASK                                                                            0x000000FFL
3289 #define SQ_VOP3P_MFMA_0__CBSZ_MASK                                                                            0x00000700L
3290 #define SQ_VOP3P_MFMA_0__ABID_MASK                                                                            0x00007800L
3291 #define SQ_VOP3P_MFMA_0__ACC_CD_MASK                                                                          0x00008000L
3292 #define SQ_VOP3P_MFMA_0__OP_MASK                                                                              0x007F0000L
3293 #define SQ_VOP3P_MFMA_0__ENCODING_MASK                                                                        0xFF800000L
3294 //SQ_VOP3P_MFMA_1
3295 #define SQ_VOP3P_MFMA_1__SRC0__SHIFT                                                                          0x0
3296 #define SQ_VOP3P_MFMA_1__SRC1__SHIFT                                                                          0x9
3297 #define SQ_VOP3P_MFMA_1__SRC2__SHIFT                                                                          0x12
3298 #define SQ_VOP3P_MFMA_1__ACC__SHIFT                                                                           0x1b
3299 #define SQ_VOP3P_MFMA_1__BLGP__SHIFT                                                                          0x1d
3300 #define SQ_VOP3P_MFMA_1__SRC0_MASK                                                                            0x000001FFL
3301 #define SQ_VOP3P_MFMA_1__SRC1_MASK                                                                            0x0003FE00L
3302 #define SQ_VOP3P_MFMA_1__SRC2_MASK                                                                            0x07FC0000L
3303 #define SQ_VOP3P_MFMA_1__ACC_MASK                                                                             0x18000000L
3304 #define SQ_VOP3P_MFMA_1__BLGP_MASK                                                                            0xE0000000L
3305 //SQ_VOP3_0
3306 #define SQ_VOP3_0__VDST__SHIFT                                                                                0x0
3307 #define SQ_VOP3_0__ABS__SHIFT                                                                                 0x8
3308 #define SQ_VOP3_0__OP_SEL__SHIFT                                                                              0xb
3309 #define SQ_VOP3_0__CLAMP__SHIFT                                                                               0xf
3310 #define SQ_VOP3_0__OP__SHIFT                                                                                  0x10
3311 #define SQ_VOP3_0__ENCODING__SHIFT                                                                            0x1a
3312 #define SQ_VOP3_0__VDST_MASK                                                                                  0x000000FFL
3313 #define SQ_VOP3_0__ABS_MASK                                                                                   0x00000700L
3314 #define SQ_VOP3_0__OP_SEL_MASK                                                                                0x00007800L
3315 #define SQ_VOP3_0__CLAMP_MASK                                                                                 0x00008000L
3316 #define SQ_VOP3_0__OP_MASK                                                                                    0x03FF0000L
3317 #define SQ_VOP3_0__ENCODING_MASK                                                                              0xFC000000L
3318 //SQ_VOP3_0_SDST_ENC
3319 #define SQ_VOP3_0_SDST_ENC__VDST__SHIFT                                                                       0x0
3320 #define SQ_VOP3_0_SDST_ENC__SDST__SHIFT                                                                       0x8
3321 #define SQ_VOP3_0_SDST_ENC__CLAMP__SHIFT                                                                      0xf
3322 #define SQ_VOP3_0_SDST_ENC__OP__SHIFT                                                                         0x10
3323 #define SQ_VOP3_0_SDST_ENC__ENCODING__SHIFT                                                                   0x1a
3324 #define SQ_VOP3_0_SDST_ENC__VDST_MASK                                                                         0x000000FFL
3325 #define SQ_VOP3_0_SDST_ENC__SDST_MASK                                                                         0x00007F00L
3326 #define SQ_VOP3_0_SDST_ENC__CLAMP_MASK                                                                        0x00008000L
3327 #define SQ_VOP3_0_SDST_ENC__OP_MASK                                                                           0x03FF0000L
3328 #define SQ_VOP3_0_SDST_ENC__ENCODING_MASK                                                                     0xFC000000L
3329 //SQ_VOP3_1
3330 #define SQ_VOP3_1__SRC0__SHIFT                                                                                0x0
3331 #define SQ_VOP3_1__SRC1__SHIFT                                                                                0x9
3332 #define SQ_VOP3_1__SRC2__SHIFT                                                                                0x12
3333 #define SQ_VOP3_1__OMOD__SHIFT                                                                                0x1b
3334 #define SQ_VOP3_1__NEG__SHIFT                                                                                 0x1d
3335 #define SQ_VOP3_1__SRC0_MASK                                                                                  0x000001FFL
3336 #define SQ_VOP3_1__SRC1_MASK                                                                                  0x0003FE00L
3337 #define SQ_VOP3_1__SRC2_MASK                                                                                  0x07FC0000L
3338 #define SQ_VOP3_1__OMOD_MASK                                                                                  0x18000000L
3339 #define SQ_VOP3_1__NEG_MASK                                                                                   0xE0000000L
3340 //SQ_VOPC
3341 #define SQ_VOPC__SRC0__SHIFT                                                                                  0x0
3342 #define SQ_VOPC__VSRC1__SHIFT                                                                                 0x9
3343 #define SQ_VOPC__OP__SHIFT                                                                                    0x11
3344 #define SQ_VOPC__ENCODING__SHIFT                                                                              0x19
3345 #define SQ_VOPC__SRC0_MASK                                                                                    0x000001FFL
3346 #define SQ_VOPC__VSRC1_MASK                                                                                   0x0001FE00L
3347 #define SQ_VOPC__OP_MASK                                                                                      0x01FE0000L
3348 #define SQ_VOPC__ENCODING_MASK                                                                                0xFE000000L
3349 //SQ_VOP_DPP
3350 #define SQ_VOP_DPP__SRC0__SHIFT                                                                               0x0
3351 #define SQ_VOP_DPP__DPP_CTRL__SHIFT                                                                           0x8
3352 #define SQ_VOP_DPP__BOUND_CTRL__SHIFT                                                                         0x13
3353 #define SQ_VOP_DPP__SRC0_NEG__SHIFT                                                                           0x14
3354 #define SQ_VOP_DPP__SRC0_ABS__SHIFT                                                                           0x15
3355 #define SQ_VOP_DPP__SRC1_NEG__SHIFT                                                                           0x16
3356 #define SQ_VOP_DPP__SRC1_ABS__SHIFT                                                                           0x17
3357 #define SQ_VOP_DPP__BANK_MASK__SHIFT                                                                          0x18
3358 #define SQ_VOP_DPP__ROW_MASK__SHIFT                                                                           0x1c
3359 #define SQ_VOP_DPP__SRC0_MASK                                                                                 0x000000FFL
3360 #define SQ_VOP_DPP__DPP_CTRL_MASK                                                                             0x0001FF00L
3361 #define SQ_VOP_DPP__BOUND_CTRL_MASK                                                                           0x00080000L
3362 #define SQ_VOP_DPP__SRC0_NEG_MASK                                                                             0x00100000L
3363 #define SQ_VOP_DPP__SRC0_ABS_MASK                                                                             0x00200000L
3364 #define SQ_VOP_DPP__SRC1_NEG_MASK                                                                             0x00400000L
3365 #define SQ_VOP_DPP__SRC1_ABS_MASK                                                                             0x00800000L
3366 #define SQ_VOP_DPP__BANK_MASK_MASK                                                                            0x0F000000L
3367 #define SQ_VOP_DPP__ROW_MASK_MASK                                                                             0xF0000000L
3368 //SQ_VOP_SDWA
3369 #define SQ_VOP_SDWA__SRC0__SHIFT                                                                              0x0
3370 #define SQ_VOP_SDWA__DST_SEL__SHIFT                                                                           0x8
3371 #define SQ_VOP_SDWA__DST_UNUSED__SHIFT                                                                        0xb
3372 #define SQ_VOP_SDWA__CLAMP__SHIFT                                                                             0xd
3373 #define SQ_VOP_SDWA__OMOD__SHIFT                                                                              0xe
3374 #define SQ_VOP_SDWA__SRC0_SEL__SHIFT                                                                          0x10
3375 #define SQ_VOP_SDWA__SRC0_SEXT__SHIFT                                                                         0x13
3376 #define SQ_VOP_SDWA__SRC0_NEG__SHIFT                                                                          0x14
3377 #define SQ_VOP_SDWA__SRC0_ABS__SHIFT                                                                          0x15
3378 #define SQ_VOP_SDWA__S0__SHIFT                                                                                0x17
3379 #define SQ_VOP_SDWA__SRC1_SEL__SHIFT                                                                          0x18
3380 #define SQ_VOP_SDWA__SRC1_SEXT__SHIFT                                                                         0x1b
3381 #define SQ_VOP_SDWA__SRC1_NEG__SHIFT                                                                          0x1c
3382 #define SQ_VOP_SDWA__SRC1_ABS__SHIFT                                                                          0x1d
3383 #define SQ_VOP_SDWA__S1__SHIFT                                                                                0x1f
3384 #define SQ_VOP_SDWA__SRC0_MASK                                                                                0x000000FFL
3385 #define SQ_VOP_SDWA__DST_SEL_MASK                                                                             0x00000700L
3386 #define SQ_VOP_SDWA__DST_UNUSED_MASK                                                                          0x00001800L
3387 #define SQ_VOP_SDWA__CLAMP_MASK                                                                               0x00002000L
3388 #define SQ_VOP_SDWA__OMOD_MASK                                                                                0x0000C000L
3389 #define SQ_VOP_SDWA__SRC0_SEL_MASK                                                                            0x00070000L
3390 #define SQ_VOP_SDWA__SRC0_SEXT_MASK                                                                           0x00080000L
3391 #define SQ_VOP_SDWA__SRC0_NEG_MASK                                                                            0x00100000L
3392 #define SQ_VOP_SDWA__SRC0_ABS_MASK                                                                            0x00200000L
3393 #define SQ_VOP_SDWA__S0_MASK                                                                                  0x00800000L
3394 #define SQ_VOP_SDWA__SRC1_SEL_MASK                                                                            0x07000000L
3395 #define SQ_VOP_SDWA__SRC1_SEXT_MASK                                                                           0x08000000L
3396 #define SQ_VOP_SDWA__SRC1_NEG_MASK                                                                            0x10000000L
3397 #define SQ_VOP_SDWA__SRC1_ABS_MASK                                                                            0x20000000L
3398 #define SQ_VOP_SDWA__S1_MASK                                                                                  0x80000000L
3399 //SQ_VOP_SDWA_SDST_ENC
3400 #define SQ_VOP_SDWA_SDST_ENC__SRC0__SHIFT                                                                     0x0
3401 #define SQ_VOP_SDWA_SDST_ENC__SDST__SHIFT                                                                     0x8
3402 #define SQ_VOP_SDWA_SDST_ENC__SD__SHIFT                                                                       0xf
3403 #define SQ_VOP_SDWA_SDST_ENC__SRC0_SEL__SHIFT                                                                 0x10
3404 #define SQ_VOP_SDWA_SDST_ENC__SRC0_SEXT__SHIFT                                                                0x13
3405 #define SQ_VOP_SDWA_SDST_ENC__SRC0_NEG__SHIFT                                                                 0x14
3406 #define SQ_VOP_SDWA_SDST_ENC__SRC0_ABS__SHIFT                                                                 0x15
3407 #define SQ_VOP_SDWA_SDST_ENC__S0__SHIFT                                                                       0x17
3408 #define SQ_VOP_SDWA_SDST_ENC__SRC1_SEL__SHIFT                                                                 0x18
3409 #define SQ_VOP_SDWA_SDST_ENC__SRC1_SEXT__SHIFT                                                                0x1b
3410 #define SQ_VOP_SDWA_SDST_ENC__SRC1_NEG__SHIFT                                                                 0x1c
3411 #define SQ_VOP_SDWA_SDST_ENC__SRC1_ABS__SHIFT                                                                 0x1d
3412 #define SQ_VOP_SDWA_SDST_ENC__S1__SHIFT                                                                       0x1f
3413 #define SQ_VOP_SDWA_SDST_ENC__SRC0_MASK                                                                       0x000000FFL
3414 #define SQ_VOP_SDWA_SDST_ENC__SDST_MASK                                                                       0x00007F00L
3415 #define SQ_VOP_SDWA_SDST_ENC__SD_MASK                                                                         0x00008000L
3416 #define SQ_VOP_SDWA_SDST_ENC__SRC0_SEL_MASK                                                                   0x00070000L
3417 #define SQ_VOP_SDWA_SDST_ENC__SRC0_SEXT_MASK                                                                  0x00080000L
3418 #define SQ_VOP_SDWA_SDST_ENC__SRC0_NEG_MASK                                                                   0x00100000L
3419 #define SQ_VOP_SDWA_SDST_ENC__SRC0_ABS_MASK                                                                   0x00200000L
3420 #define SQ_VOP_SDWA_SDST_ENC__S0_MASK                                                                         0x00800000L
3421 #define SQ_VOP_SDWA_SDST_ENC__SRC1_SEL_MASK                                                                   0x07000000L
3422 #define SQ_VOP_SDWA_SDST_ENC__SRC1_SEXT_MASK                                                                  0x08000000L
3423 #define SQ_VOP_SDWA_SDST_ENC__SRC1_NEG_MASK                                                                   0x10000000L
3424 #define SQ_VOP_SDWA_SDST_ENC__SRC1_ABS_MASK                                                                   0x20000000L
3425 #define SQ_VOP_SDWA_SDST_ENC__S1_MASK                                                                         0x80000000L
3426 //SQ_LB_CTR_CTRL
3427 #define SQ_LB_CTR_CTRL__START__SHIFT                                                                          0x0
3428 #define SQ_LB_CTR_CTRL__LOAD__SHIFT                                                                           0x1
3429 #define SQ_LB_CTR_CTRL__CLEAR__SHIFT                                                                          0x2
3430 #define SQ_LB_CTR_CTRL__START_MASK                                                                            0x00000001L
3431 #define SQ_LB_CTR_CTRL__LOAD_MASK                                                                             0x00000002L
3432 #define SQ_LB_CTR_CTRL__CLEAR_MASK                                                                            0x00000004L
3433 //SQ_LB_DATA0
3434 #define SQ_LB_DATA0__DATA__SHIFT                                                                              0x0
3435 #define SQ_LB_DATA0__DATA_MASK                                                                                0xFFFFFFFFL
3436 //SQ_LB_DATA1
3437 #define SQ_LB_DATA1__DATA__SHIFT                                                                              0x0
3438 #define SQ_LB_DATA1__DATA_MASK                                                                                0xFFFFFFFFL
3439 //SQ_LB_DATA2
3440 #define SQ_LB_DATA2__DATA__SHIFT                                                                              0x0
3441 #define SQ_LB_DATA2__DATA_MASK                                                                                0xFFFFFFFFL
3442 //SQ_LB_DATA3
3443 #define SQ_LB_DATA3__DATA__SHIFT                                                                              0x0
3444 #define SQ_LB_DATA3__DATA_MASK                                                                                0xFFFFFFFFL
3445 //SQ_LB_CTR_SEL
3446 #define SQ_LB_CTR_SEL__SEL0__SHIFT                                                                            0x0
3447 #define SQ_LB_CTR_SEL__SEL1__SHIFT                                                                            0x4
3448 #define SQ_LB_CTR_SEL__SEL2__SHIFT                                                                            0x8
3449 #define SQ_LB_CTR_SEL__SEL3__SHIFT                                                                            0xc
3450 #define SQ_LB_CTR_SEL__SEL0_MASK                                                                              0x0000000FL
3451 #define SQ_LB_CTR_SEL__SEL1_MASK                                                                              0x000000F0L
3452 #define SQ_LB_CTR_SEL__SEL2_MASK                                                                              0x00000F00L
3453 #define SQ_LB_CTR_SEL__SEL3_MASK                                                                              0x0000F000L
3454 //SQ_LB_CTR0_CU
3455 #define SQ_LB_CTR0_CU__SH0_MASK__SHIFT                                                                        0x0
3456 #define SQ_LB_CTR0_CU__SH1_MASK__SHIFT                                                                        0x10
3457 #define SQ_LB_CTR0_CU__SH0_MASK_MASK                                                                          0x0000FFFFL
3458 #define SQ_LB_CTR0_CU__SH1_MASK_MASK                                                                          0xFFFF0000L
3459 //SQ_LB_CTR1_CU
3460 #define SQ_LB_CTR1_CU__SH0_MASK__SHIFT                                                                        0x0
3461 #define SQ_LB_CTR1_CU__SH1_MASK__SHIFT                                                                        0x10
3462 #define SQ_LB_CTR1_CU__SH0_MASK_MASK                                                                          0x0000FFFFL
3463 #define SQ_LB_CTR1_CU__SH1_MASK_MASK                                                                          0xFFFF0000L
3464 //SQ_LB_CTR2_CU
3465 #define SQ_LB_CTR2_CU__SH0_MASK__SHIFT                                                                        0x0
3466 #define SQ_LB_CTR2_CU__SH1_MASK__SHIFT                                                                        0x10
3467 #define SQ_LB_CTR2_CU__SH0_MASK_MASK                                                                          0x0000FFFFL
3468 #define SQ_LB_CTR2_CU__SH1_MASK_MASK                                                                          0xFFFF0000L
3469 //SQ_LB_CTR3_CU
3470 #define SQ_LB_CTR3_CU__SH0_MASK__SHIFT                                                                        0x0
3471 #define SQ_LB_CTR3_CU__SH1_MASK__SHIFT                                                                        0x10
3472 #define SQ_LB_CTR3_CU__SH0_MASK_MASK                                                                          0x0000FFFFL
3473 #define SQ_LB_CTR3_CU__SH1_MASK_MASK                                                                          0xFFFF0000L
3474 //SQC_EDC_CNT
3475 #define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_SEC_COUNT__SHIFT                                                 0x0
3476 #define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_DED_COUNT__SHIFT                                                 0x2
3477 #define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_SEC_COUNT__SHIFT                                                    0x4
3478 #define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_DED_COUNT__SHIFT                                                    0x6
3479 #define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_SEC_COUNT__SHIFT                                                 0x8
3480 #define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_DED_COUNT__SHIFT                                                 0xa
3481 #define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_SEC_COUNT__SHIFT                                                    0xc
3482 #define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_DED_COUNT__SHIFT                                                    0xe
3483 #define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_SEC_COUNT__SHIFT                                                 0x10
3484 #define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_DED_COUNT__SHIFT                                                 0x12
3485 #define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_SEC_COUNT__SHIFT                                                    0x14
3486 #define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_DED_COUNT__SHIFT                                                    0x16
3487 #define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_SEC_COUNT__SHIFT                                                 0x18
3488 #define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_DED_COUNT__SHIFT                                                 0x1a
3489 #define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_SEC_COUNT__SHIFT                                                    0x1c
3490 #define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_DED_COUNT__SHIFT                                                    0x1e
3491 #define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_SEC_COUNT_MASK                                                   0x00000003L
3492 #define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_DED_COUNT_MASK                                                   0x0000000CL
3493 #define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_SEC_COUNT_MASK                                                      0x00000030L
3494 #define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_DED_COUNT_MASK                                                      0x000000C0L
3495 #define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_SEC_COUNT_MASK                                                   0x00000300L
3496 #define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_DED_COUNT_MASK                                                   0x00000C00L
3497 #define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_SEC_COUNT_MASK                                                      0x00003000L
3498 #define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_DED_COUNT_MASK                                                      0x0000C000L
3499 #define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_SEC_COUNT_MASK                                                   0x00030000L
3500 #define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_DED_COUNT_MASK                                                   0x000C0000L
3501 #define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_SEC_COUNT_MASK                                                      0x00300000L
3502 #define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_DED_COUNT_MASK                                                      0x00C00000L
3503 #define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_SEC_COUNT_MASK                                                   0x03000000L
3504 #define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_DED_COUNT_MASK                                                   0x0C000000L
3505 #define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_SEC_COUNT_MASK                                                      0x30000000L
3506 #define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_DED_COUNT_MASK                                                      0xC0000000L
3507 //SQ_EDC_SEC_CNT
3508 #define SQ_EDC_SEC_CNT__LDS_SEC__SHIFT                                                                        0x0
3509 #define SQ_EDC_SEC_CNT__SGPR_SEC__SHIFT                                                                       0x8
3510 #define SQ_EDC_SEC_CNT__VGPR_SEC__SHIFT                                                                       0x10
3511 #define SQ_EDC_SEC_CNT__LDS_SEC_MASK                                                                          0x000000FFL
3512 #define SQ_EDC_SEC_CNT__SGPR_SEC_MASK                                                                         0x0000FF00L
3513 #define SQ_EDC_SEC_CNT__VGPR_SEC_MASK                                                                         0x00FF0000L
3514 //SQ_EDC_DED_CNT
3515 #define SQ_EDC_DED_CNT__LDS_DED__SHIFT                                                                        0x0
3516 #define SQ_EDC_DED_CNT__SGPR_DED__SHIFT                                                                       0x8
3517 #define SQ_EDC_DED_CNT__VGPR_DED__SHIFT                                                                       0x10
3518 #define SQ_EDC_DED_CNT__LDS_DED_MASK                                                                          0x000000FFL
3519 #define SQ_EDC_DED_CNT__SGPR_DED_MASK                                                                         0x0000FF00L
3520 #define SQ_EDC_DED_CNT__VGPR_DED_MASK                                                                         0x00FF0000L
3521 //SQ_EDC_INFO
3522 #define SQ_EDC_INFO__WAVE_ID__SHIFT                                                                           0x0
3523 #define SQ_EDC_INFO__SIMD_ID__SHIFT                                                                           0x4
3524 #define SQ_EDC_INFO__SOURCE__SHIFT                                                                            0x6
3525 #define SQ_EDC_INFO__VM_ID__SHIFT                                                                             0x9
3526 #define SQ_EDC_INFO__WAVE_ID_MASK                                                                             0x0000000FL
3527 #define SQ_EDC_INFO__SIMD_ID_MASK                                                                             0x00000030L
3528 #define SQ_EDC_INFO__SOURCE_MASK                                                                              0x000001C0L
3529 #define SQ_EDC_INFO__VM_ID_MASK                                                                               0x00001E00L
3530 //SQ_EDC_CNT
3531 #define SQ_EDC_CNT__LDS_D_SEC_COUNT__SHIFT                                                                    0x0
3532 #define SQ_EDC_CNT__LDS_D_DED_COUNT__SHIFT                                                                    0x2
3533 #define SQ_EDC_CNT__LDS_I_SEC_COUNT__SHIFT                                                                    0x4
3534 #define SQ_EDC_CNT__LDS_I_DED_COUNT__SHIFT                                                                    0x6
3535 #define SQ_EDC_CNT__SGPR_SEC_COUNT__SHIFT                                                                     0x8
3536 #define SQ_EDC_CNT__SGPR_DED_COUNT__SHIFT                                                                     0xa
3537 #define SQ_EDC_CNT__VGPR0_SEC_COUNT__SHIFT                                                                    0xc
3538 #define SQ_EDC_CNT__VGPR0_DED_COUNT__SHIFT                                                                    0xe
3539 #define SQ_EDC_CNT__VGPR1_SEC_COUNT__SHIFT                                                                    0x10
3540 #define SQ_EDC_CNT__VGPR1_DED_COUNT__SHIFT                                                                    0x12
3541 #define SQ_EDC_CNT__VGPR2_SEC_COUNT__SHIFT                                                                    0x14
3542 #define SQ_EDC_CNT__VGPR2_DED_COUNT__SHIFT                                                                    0x16
3543 #define SQ_EDC_CNT__VGPR3_SEC_COUNT__SHIFT                                                                    0x18
3544 #define SQ_EDC_CNT__VGPR3_DED_COUNT__SHIFT                                                                    0x1a
3545 #define SQ_EDC_CNT__LDS_D_SEC_COUNT_MASK                                                                      0x00000003L
3546 #define SQ_EDC_CNT__LDS_D_DED_COUNT_MASK                                                                      0x0000000CL
3547 #define SQ_EDC_CNT__LDS_I_SEC_COUNT_MASK                                                                      0x00000030L
3548 #define SQ_EDC_CNT__LDS_I_DED_COUNT_MASK                                                                      0x000000C0L
3549 #define SQ_EDC_CNT__SGPR_SEC_COUNT_MASK                                                                       0x00000300L
3550 #define SQ_EDC_CNT__SGPR_DED_COUNT_MASK                                                                       0x00000C00L
3551 #define SQ_EDC_CNT__VGPR0_SEC_COUNT_MASK                                                                      0x00003000L
3552 #define SQ_EDC_CNT__VGPR0_DED_COUNT_MASK                                                                      0x0000C000L
3553 #define SQ_EDC_CNT__VGPR1_SEC_COUNT_MASK                                                                      0x00030000L
3554 #define SQ_EDC_CNT__VGPR1_DED_COUNT_MASK                                                                      0x000C0000L
3555 #define SQ_EDC_CNT__VGPR2_SEC_COUNT_MASK                                                                      0x00300000L
3556 #define SQ_EDC_CNT__VGPR2_DED_COUNT_MASK                                                                      0x00C00000L
3557 #define SQ_EDC_CNT__VGPR3_SEC_COUNT_MASK                                                                      0x03000000L
3558 #define SQ_EDC_CNT__VGPR3_DED_COUNT_MASK                                                                      0x0C000000L
3559 //SQ_EDC_FUE_CNTL
3560 #define SQ_EDC_FUE_CNTL__BLOCK_FUE_FLAGS__SHIFT                                                               0x0
3561 #define SQ_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES__SHIFT                                                         0x10
3562 #define SQ_EDC_FUE_CNTL__BLOCK_FUE_FLAGS_MASK                                                                 0x0000FFFFL
3563 #define SQ_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES_MASK                                                           0xFFFF0000L
3564 //SQ_THREAD_TRACE_WORD_CMN
3565 #define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE__SHIFT                                                           0x0
3566 #define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA__SHIFT                                                           0x4
3567 #define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE_MASK                                                             0x000FL
3568 #define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA_MASK                                                             0x0010L
3569 //SQ_THREAD_TRACE_WORD_EVENT
3570 #define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE__SHIFT                                                         0x0
3571 #define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA__SHIFT                                                         0x4
3572 #define SQ_THREAD_TRACE_WORD_EVENT__SH_ID__SHIFT                                                              0x5
3573 #define SQ_THREAD_TRACE_WORD_EVENT__STAGE__SHIFT                                                              0x6
3574 #define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE__SHIFT                                                         0xa
3575 #define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE_MASK                                                           0x000FL
3576 #define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA_MASK                                                           0x0010L
3577 #define SQ_THREAD_TRACE_WORD_EVENT__SH_ID_MASK                                                                0x0020L
3578 #define SQ_THREAD_TRACE_WORD_EVENT__STAGE_MASK                                                                0x01C0L
3579 #define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE_MASK                                                           0xFC00L
3580 //SQ_THREAD_TRACE_WORD_INST
3581 #define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE__SHIFT                                                          0x0
3582 #define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA__SHIFT                                                          0x4
3583 #define SQ_THREAD_TRACE_WORD_INST__WAVE_ID__SHIFT                                                             0x5
3584 #define SQ_THREAD_TRACE_WORD_INST__SIMD_ID__SHIFT                                                             0x9
3585 #define SQ_THREAD_TRACE_WORD_INST__INST_TYPE__SHIFT                                                           0xb
3586 #define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE_MASK                                                            0x000FL
3587 #define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA_MASK                                                            0x0010L
3588 #define SQ_THREAD_TRACE_WORD_INST__WAVE_ID_MASK                                                               0x01E0L
3589 #define SQ_THREAD_TRACE_WORD_INST__SIMD_ID_MASK                                                               0x0600L
3590 #define SQ_THREAD_TRACE_WORD_INST__INST_TYPE_MASK                                                             0xF800L
3591 //SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2
3592 #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE__SHIFT                                                0x0
3593 #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA__SHIFT                                                0x4
3594 #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID__SHIFT                                                   0x5
3595 #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID__SHIFT                                                   0x9
3596 #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TRAP_ERROR__SHIFT                                                0xf
3597 #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO__SHIFT                                                     0x10
3598 #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE_MASK                                                  0x0000000FL
3599 #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA_MASK                                                  0x00000010L
3600 #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID_MASK                                                     0x000001E0L
3601 #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID_MASK                                                     0x00000600L
3602 #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TRAP_ERROR_MASK                                                  0x00008000L
3603 #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO_MASK                                                       0xFFFF0000L
3604 //SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2
3605 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE__SHIFT                                          0x0
3606 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA__SHIFT                                          0x4
3607 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__PRIV__SHIFT                                                0x5
3608 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID__SHIFT                                               0x6
3609 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID__SHIFT                                             0xa
3610 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID__SHIFT                                             0xe
3611 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO__SHIFT                                             0x10
3612 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE_MASK                                            0x0000000FL
3613 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA_MASK                                            0x00000010L
3614 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__PRIV_MASK                                                  0x00000020L
3615 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID_MASK                                                 0x000003C0L
3616 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID_MASK                                               0x00003C00L
3617 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID_MASK                                               0x0000C000L
3618 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO_MASK                                               0xFFFF0000L
3619 //SQ_THREAD_TRACE_WORD_ISSUE
3620 #define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE__SHIFT                                                         0x0
3621 #define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA__SHIFT                                                         0x4
3622 #define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID__SHIFT                                                            0x5
3623 #define SQ_THREAD_TRACE_WORD_ISSUE__INST0__SHIFT                                                              0x8
3624 #define SQ_THREAD_TRACE_WORD_ISSUE__INST1__SHIFT                                                              0xa
3625 #define SQ_THREAD_TRACE_WORD_ISSUE__INST2__SHIFT                                                              0xc
3626 #define SQ_THREAD_TRACE_WORD_ISSUE__INST3__SHIFT                                                              0xe
3627 #define SQ_THREAD_TRACE_WORD_ISSUE__INST4__SHIFT                                                              0x10
3628 #define SQ_THREAD_TRACE_WORD_ISSUE__INST5__SHIFT                                                              0x12
3629 #define SQ_THREAD_TRACE_WORD_ISSUE__INST6__SHIFT                                                              0x14
3630 #define SQ_THREAD_TRACE_WORD_ISSUE__INST7__SHIFT                                                              0x16
3631 #define SQ_THREAD_TRACE_WORD_ISSUE__INST8__SHIFT                                                              0x18
3632 #define SQ_THREAD_TRACE_WORD_ISSUE__INST9__SHIFT                                                              0x1a
3633 #define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE_MASK                                                           0x0000000FL
3634 #define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA_MASK                                                           0x00000010L
3635 #define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID_MASK                                                              0x00000060L
3636 #define SQ_THREAD_TRACE_WORD_ISSUE__INST0_MASK                                                                0x00000300L
3637 #define SQ_THREAD_TRACE_WORD_ISSUE__INST1_MASK                                                                0x00000C00L
3638 #define SQ_THREAD_TRACE_WORD_ISSUE__INST2_MASK                                                                0x00003000L
3639 #define SQ_THREAD_TRACE_WORD_ISSUE__INST3_MASK                                                                0x0000C000L
3640 #define SQ_THREAD_TRACE_WORD_ISSUE__INST4_MASK                                                                0x00030000L
3641 #define SQ_THREAD_TRACE_WORD_ISSUE__INST5_MASK                                                                0x000C0000L
3642 #define SQ_THREAD_TRACE_WORD_ISSUE__INST6_MASK                                                                0x00300000L
3643 #define SQ_THREAD_TRACE_WORD_ISSUE__INST7_MASK                                                                0x00C00000L
3644 #define SQ_THREAD_TRACE_WORD_ISSUE__INST8_MASK                                                                0x03000000L
3645 #define SQ_THREAD_TRACE_WORD_ISSUE__INST9_MASK                                                                0x0C000000L
3646 //SQ_THREAD_TRACE_WORD_MISC
3647 #define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE__SHIFT                                                          0x0
3648 #define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA__SHIFT                                                          0x4
3649 #define SQ_THREAD_TRACE_WORD_MISC__SH_ID__SHIFT                                                               0xc
3650 #define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE__SHIFT                                                     0xd
3651 #define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE_MASK                                                            0x000FL
3652 #define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA_MASK                                                            0x0FF0L
3653 #define SQ_THREAD_TRACE_WORD_MISC__SH_ID_MASK                                                                 0x1000L
3654 #define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE_MASK                                                       0xE000L
3655 //SQ_THREAD_TRACE_WORD_PERF_1_OF_2
3656 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE__SHIFT                                                   0x0
3657 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA__SHIFT                                                   0x4
3658 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID__SHIFT                                                        0x5
3659 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID__SHIFT                                                        0x6
3660 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK__SHIFT                                                    0xa
3661 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0__SHIFT                                                        0xc
3662 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO__SHIFT                                                     0x19
3663 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE_MASK                                                     0x0000000FL
3664 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA_MASK                                                     0x00000010L
3665 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID_MASK                                                          0x00000020L
3666 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID_MASK                                                          0x000003C0L
3667 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK_MASK                                                      0x00000C00L
3668 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0_MASK                                                          0x01FFF000L
3669 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO_MASK                                                       0xFE000000L
3670 //SQ_THREAD_TRACE_WORD_REG_1_OF_2
3671 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE__SHIFT                                                    0x0
3672 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA__SHIFT                                                    0x4
3673 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID__SHIFT                                                       0x5
3674 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID__SHIFT                                                         0x7
3675 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV__SHIFT                                              0x9
3676 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE__SHIFT                                                      0xa
3677 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV__SHIFT                                                      0xe
3678 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP__SHIFT                                                        0xf
3679 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR__SHIFT                                                      0x10
3680 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE_MASK                                                      0x0000000FL
3681 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA_MASK                                                      0x00000010L
3682 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID_MASK                                                         0x00000060L
3683 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID_MASK                                                           0x00000180L
3684 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV_MASK                                                0x00000200L
3685 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE_MASK                                                        0x00001C00L
3686 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV_MASK                                                        0x00004000L
3687 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP_MASK                                                          0x00008000L
3688 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR_MASK                                                        0xFFFF0000L
3689 //SQ_THREAD_TRACE_WORD_REG_2_OF_2
3690 #define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA__SHIFT                                                          0x0
3691 #define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA_MASK                                                            0xFFFFFFFFL
3692 //SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2
3693 #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE__SHIFT                                                 0x0
3694 #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA__SHIFT                                                 0x4
3695 #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID__SHIFT                                                    0x5
3696 #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID__SHIFT                                                      0x7
3697 #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR__SHIFT                                                   0x9
3698 #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO__SHIFT                                                    0x10
3699 #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE_MASK                                                   0x0000000FL
3700 #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA_MASK                                                   0x00000010L
3701 #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID_MASK                                                      0x00000060L
3702 #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID_MASK                                                        0x00000180L
3703 #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR_MASK                                                     0x0000FE00L
3704 #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO_MASK                                                      0xFFFF0000L
3705 //SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2
3706 #define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI__SHIFT                                                    0x0
3707 #define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI_MASK                                                      0x0000FFFFL
3708 //SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2
3709 #define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE__SHIFT                                              0x0
3710 #define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO__SHIFT                                                 0x10
3711 #define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE_MASK                                                0x0000000FL
3712 #define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO_MASK                                                   0xFFFF0000L
3713 //SQ_THREAD_TRACE_WORD_WAVE
3714 #define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE__SHIFT                                                          0x0
3715 #define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA__SHIFT                                                          0x4
3716 #define SQ_THREAD_TRACE_WORD_WAVE__SH_ID__SHIFT                                                               0x5
3717 #define SQ_THREAD_TRACE_WORD_WAVE__CU_ID__SHIFT                                                               0x6
3718 #define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID__SHIFT                                                             0xa
3719 #define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID__SHIFT                                                             0xe
3720 #define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE_MASK                                                            0x000FL
3721 #define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA_MASK                                                            0x0010L
3722 #define SQ_THREAD_TRACE_WORD_WAVE__SH_ID_MASK                                                                 0x0020L
3723 #define SQ_THREAD_TRACE_WORD_WAVE__CU_ID_MASK                                                                 0x03C0L
3724 #define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID_MASK                                                               0x3C00L
3725 #define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID_MASK                                                               0xC000L
3726 //SQ_THREAD_TRACE_WORD_WAVE_START
3727 #define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE__SHIFT                                                    0x0
3728 #define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA__SHIFT                                                    0x4
3729 #define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID__SHIFT                                                         0x5
3730 #define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID__SHIFT                                                         0x6
3731 #define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID__SHIFT                                                       0xa
3732 #define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID__SHIFT                                                       0xe
3733 #define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER__SHIFT                                                    0x10
3734 #define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED__SHIFT                                        0x15
3735 #define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT__SHIFT                                                         0x16
3736 #define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID__SHIFT                                                         0x1d
3737 #define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE_MASK                                                      0x0000000FL
3738 #define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA_MASK                                                      0x00000010L
3739 #define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID_MASK                                                           0x00000020L
3740 #define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID_MASK                                                           0x000003C0L
3741 #define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID_MASK                                                         0x00003C00L
3742 #define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID_MASK                                                         0x0000C000L
3743 #define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER_MASK                                                      0x001F0000L
3744 #define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED_MASK                                          0x00200000L
3745 #define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT_MASK                                                           0x1FC00000L
3746 #define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID_MASK                                                           0xE0000000L
3747 //SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2
3748 #define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI__SHIFT                                                     0x0
3749 #define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI_MASK                                                       0x00FFFFFFL
3750 //SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2
3751 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI__SHIFT                                             0x0
3752 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI_MASK                                               0xFFFFL
3753 //SQ_THREAD_TRACE_WORD_PERF_2_OF_2
3754 #define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI__SHIFT                                                     0x0
3755 #define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2__SHIFT                                                        0x6
3756 #define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3__SHIFT                                                        0x13
3757 #define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI_MASK                                                       0x0000003FL
3758 #define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2_MASK                                                          0x0007FFC0L
3759 #define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3_MASK                                                          0xFFF80000L
3760 //SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2
3761 #define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI__SHIFT                                                 0x0
3762 #define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI_MASK                                                   0xFFFFFFFFL
3763 //SQ_WREXEC_EXEC_HI
3764 #define SQ_WREXEC_EXEC_HI__ADDR_HI__SHIFT                                                                     0x0
3765 #define SQ_WREXEC_EXEC_HI__FIRST_WAVE__SHIFT                                                                  0x1a
3766 #define SQ_WREXEC_EXEC_HI__ATC__SHIFT                                                                         0x1b
3767 #define SQ_WREXEC_EXEC_HI__MTYPE__SHIFT                                                                       0x1c
3768 #define SQ_WREXEC_EXEC_HI__MSB__SHIFT                                                                         0x1f
3769 #define SQ_WREXEC_EXEC_HI__ADDR_HI_MASK                                                                       0x0000FFFFL
3770 #define SQ_WREXEC_EXEC_HI__FIRST_WAVE_MASK                                                                    0x04000000L
3771 #define SQ_WREXEC_EXEC_HI__ATC_MASK                                                                           0x08000000L
3772 #define SQ_WREXEC_EXEC_HI__MTYPE_MASK                                                                         0x70000000L
3773 #define SQ_WREXEC_EXEC_HI__MSB_MASK                                                                           0x80000000L
3774 //SQ_WREXEC_EXEC_LO
3775 #define SQ_WREXEC_EXEC_LO__ADDR_LO__SHIFT                                                                     0x0
3776 #define SQ_WREXEC_EXEC_LO__ADDR_LO_MASK                                                                       0xFFFFFFFFL
3777 //SQ_BUF_RSRC_WORD0
3778 #define SQ_BUF_RSRC_WORD0__BASE_ADDRESS__SHIFT                                                                0x0
3779 #define SQ_BUF_RSRC_WORD0__BASE_ADDRESS_MASK                                                                  0xFFFFFFFFL
3780 //SQ_BUF_RSRC_WORD1
3781 #define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT                                                             0x0
3782 #define SQ_BUF_RSRC_WORD1__STRIDE__SHIFT                                                                      0x10
3783 #define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE__SHIFT                                                               0x1e
3784 #define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE__SHIFT                                                              0x1f
3785 #define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI_MASK                                                               0x0000FFFFL
3786 #define SQ_BUF_RSRC_WORD1__STRIDE_MASK                                                                        0x3FFF0000L
3787 #define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE_MASK                                                                 0x40000000L
3788 #define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE_MASK                                                                0x80000000L
3789 //SQ_BUF_RSRC_WORD2
3790 #define SQ_BUF_RSRC_WORD2__NUM_RECORDS__SHIFT                                                                 0x0
3791 #define SQ_BUF_RSRC_WORD2__NUM_RECORDS_MASK                                                                   0xFFFFFFFFL
3792 //SQ_BUF_RSRC_WORD3
3793 #define SQ_BUF_RSRC_WORD3__DST_SEL_X__SHIFT                                                                   0x0
3794 #define SQ_BUF_RSRC_WORD3__DST_SEL_Y__SHIFT                                                                   0x3
3795 #define SQ_BUF_RSRC_WORD3__DST_SEL_Z__SHIFT                                                                   0x6
3796 #define SQ_BUF_RSRC_WORD3__DST_SEL_W__SHIFT                                                                   0x9
3797 #define SQ_BUF_RSRC_WORD3__NUM_FORMAT__SHIFT                                                                  0xc
3798 #define SQ_BUF_RSRC_WORD3__DATA_FORMAT__SHIFT                                                                 0xf
3799 #define SQ_BUF_RSRC_WORD3__USER_VM_ENABLE__SHIFT                                                              0x13
3800 #define SQ_BUF_RSRC_WORD3__USER_VM_MODE__SHIFT                                                                0x14
3801 #define SQ_BUF_RSRC_WORD3__INDEX_STRIDE__SHIFT                                                                0x15
3802 #define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE__SHIFT                                                              0x17
3803 #define SQ_BUF_RSRC_WORD3__NV__SHIFT                                                                          0x1b
3804 #define SQ_BUF_RSRC_WORD3__TYPE__SHIFT                                                                        0x1e
3805 #define SQ_BUF_RSRC_WORD3__DST_SEL_X_MASK                                                                     0x00000007L
3806 #define SQ_BUF_RSRC_WORD3__DST_SEL_Y_MASK                                                                     0x00000038L
3807 #define SQ_BUF_RSRC_WORD3__DST_SEL_Z_MASK                                                                     0x000001C0L
3808 #define SQ_BUF_RSRC_WORD3__DST_SEL_W_MASK                                                                     0x00000E00L
3809 #define SQ_BUF_RSRC_WORD3__NUM_FORMAT_MASK                                                                    0x00007000L
3810 #define SQ_BUF_RSRC_WORD3__DATA_FORMAT_MASK                                                                   0x00078000L
3811 #define SQ_BUF_RSRC_WORD3__USER_VM_ENABLE_MASK                                                                0x00080000L
3812 #define SQ_BUF_RSRC_WORD3__USER_VM_MODE_MASK                                                                  0x00100000L
3813 #define SQ_BUF_RSRC_WORD3__INDEX_STRIDE_MASK                                                                  0x00600000L
3814 #define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE_MASK                                                                0x00800000L
3815 #define SQ_BUF_RSRC_WORD3__NV_MASK                                                                            0x08000000L
3816 #define SQ_BUF_RSRC_WORD3__TYPE_MASK                                                                          0xC0000000L
3817 //SQ_IMG_RSRC_WORD0
3818 #define SQ_IMG_RSRC_WORD0__BASE_ADDRESS__SHIFT                                                                0x0
3819 #define SQ_IMG_RSRC_WORD0__BASE_ADDRESS_MASK                                                                  0xFFFFFFFFL
3820 //SQ_IMG_RSRC_WORD1
3821 #define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT                                                             0x0
3822 #define SQ_IMG_RSRC_WORD1__MIN_LOD__SHIFT                                                                     0x8
3823 #define SQ_IMG_RSRC_WORD1__DATA_FORMAT__SHIFT                                                                 0x14
3824 #define SQ_IMG_RSRC_WORD1__NUM_FORMAT__SHIFT                                                                  0x1a
3825 #define SQ_IMG_RSRC_WORD1__NV__SHIFT                                                                          0x1e
3826 #define SQ_IMG_RSRC_WORD1__META_DIRECT__SHIFT                                                                 0x1f
3827 #define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI_MASK                                                               0x000000FFL
3828 #define SQ_IMG_RSRC_WORD1__MIN_LOD_MASK                                                                       0x000FFF00L
3829 #define SQ_IMG_RSRC_WORD1__DATA_FORMAT_MASK                                                                   0x03F00000L
3830 #define SQ_IMG_RSRC_WORD1__NUM_FORMAT_MASK                                                                    0x3C000000L
3831 #define SQ_IMG_RSRC_WORD1__NV_MASK                                                                            0x40000000L
3832 #define SQ_IMG_RSRC_WORD1__META_DIRECT_MASK                                                                   0x80000000L
3833 //SQ_IMG_RSRC_WORD2
3834 #define SQ_IMG_RSRC_WORD2__WIDTH__SHIFT                                                                       0x0
3835 #define SQ_IMG_RSRC_WORD2__HEIGHT__SHIFT                                                                      0xe
3836 #define SQ_IMG_RSRC_WORD2__PERF_MOD__SHIFT                                                                    0x1c
3837 #define SQ_IMG_RSRC_WORD2__WIDTH_MASK                                                                         0x00003FFFL
3838 #define SQ_IMG_RSRC_WORD2__HEIGHT_MASK                                                                        0x0FFFC000L
3839 #define SQ_IMG_RSRC_WORD2__PERF_MOD_MASK                                                                      0x70000000L
3840 //SQ_IMG_RSRC_WORD3
3841 #define SQ_IMG_RSRC_WORD3__DST_SEL_X__SHIFT                                                                   0x0
3842 #define SQ_IMG_RSRC_WORD3__DST_SEL_Y__SHIFT                                                                   0x3
3843 #define SQ_IMG_RSRC_WORD3__DST_SEL_Z__SHIFT                                                                   0x6
3844 #define SQ_IMG_RSRC_WORD3__DST_SEL_W__SHIFT                                                                   0x9
3845 #define SQ_IMG_RSRC_WORD3__BASE_LEVEL__SHIFT                                                                  0xc
3846 #define SQ_IMG_RSRC_WORD3__LAST_LEVEL__SHIFT                                                                  0x10
3847 #define SQ_IMG_RSRC_WORD3__SW_MODE__SHIFT                                                                     0x14
3848 #define SQ_IMG_RSRC_WORD3__TYPE__SHIFT                                                                        0x1c
3849 #define SQ_IMG_RSRC_WORD3__DST_SEL_X_MASK                                                                     0x00000007L
3850 #define SQ_IMG_RSRC_WORD3__DST_SEL_Y_MASK                                                                     0x00000038L
3851 #define SQ_IMG_RSRC_WORD3__DST_SEL_Z_MASK                                                                     0x000001C0L
3852 #define SQ_IMG_RSRC_WORD3__DST_SEL_W_MASK                                                                     0x00000E00L
3853 #define SQ_IMG_RSRC_WORD3__BASE_LEVEL_MASK                                                                    0x0000F000L
3854 #define SQ_IMG_RSRC_WORD3__LAST_LEVEL_MASK                                                                    0x000F0000L
3855 #define SQ_IMG_RSRC_WORD3__SW_MODE_MASK                                                                       0x01F00000L
3856 #define SQ_IMG_RSRC_WORD3__TYPE_MASK                                                                          0xF0000000L
3857 //SQ_IMG_RSRC_WORD4
3858 #define SQ_IMG_RSRC_WORD4__DEPTH__SHIFT                                                                       0x0
3859 #define SQ_IMG_RSRC_WORD4__PITCH__SHIFT                                                                       0xd
3860 #define SQ_IMG_RSRC_WORD4__BC_SWIZZLE__SHIFT                                                                  0x1d
3861 #define SQ_IMG_RSRC_WORD4__DEPTH_MASK                                                                         0x00001FFFL
3862 #define SQ_IMG_RSRC_WORD4__PITCH_MASK                                                                         0x1FFFE000L
3863 #define SQ_IMG_RSRC_WORD4__BC_SWIZZLE_MASK                                                                    0xE0000000L
3864 //SQ_IMG_RSRC_WORD5
3865 #define SQ_IMG_RSRC_WORD5__BASE_ARRAY__SHIFT                                                                  0x0
3866 #define SQ_IMG_RSRC_WORD5__ARRAY_PITCH__SHIFT                                                                 0xd
3867 #define SQ_IMG_RSRC_WORD5__META_DATA_ADDRESS__SHIFT                                                           0x11
3868 #define SQ_IMG_RSRC_WORD5__META_LINEAR__SHIFT                                                                 0x19
3869 #define SQ_IMG_RSRC_WORD5__META_PIPE_ALIGNED__SHIFT                                                           0x1a
3870 #define SQ_IMG_RSRC_WORD5__META_RB_ALIGNED__SHIFT                                                             0x1b
3871 #define SQ_IMG_RSRC_WORD5__MAX_MIP__SHIFT                                                                     0x1c
3872 #define SQ_IMG_RSRC_WORD5__BASE_ARRAY_MASK                                                                    0x00001FFFL
3873 #define SQ_IMG_RSRC_WORD5__ARRAY_PITCH_MASK                                                                   0x0001E000L
3874 #define SQ_IMG_RSRC_WORD5__META_DATA_ADDRESS_MASK                                                             0x01FE0000L
3875 #define SQ_IMG_RSRC_WORD5__META_LINEAR_MASK                                                                   0x02000000L
3876 #define SQ_IMG_RSRC_WORD5__META_PIPE_ALIGNED_MASK                                                             0x04000000L
3877 #define SQ_IMG_RSRC_WORD5__META_RB_ALIGNED_MASK                                                               0x08000000L
3878 #define SQ_IMG_RSRC_WORD5__MAX_MIP_MASK                                                                       0xF0000000L
3879 //SQ_IMG_RSRC_WORD6
3880 #define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN__SHIFT                                                                0x0
3881 #define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID__SHIFT                                                             0xc
3882 #define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN__SHIFT                                                              0x14
3883 #define SQ_IMG_RSRC_WORD6__COMPRESSION_EN__SHIFT                                                              0x15
3884 #define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB__SHIFT                                                             0x16
3885 #define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM__SHIFT                                                             0x17
3886 #define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS__SHIFT                                                             0x18
3887 #define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS__SHIFT                                                             0x1c
3888 #define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN_MASK                                                                  0x00000FFFL
3889 #define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID_MASK                                                               0x000FF000L
3890 #define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN_MASK                                                                0x00100000L
3891 #define SQ_IMG_RSRC_WORD6__COMPRESSION_EN_MASK                                                                0x00200000L
3892 #define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB_MASK                                                               0x00400000L
3893 #define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM_MASK                                                               0x00800000L
3894 #define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS_MASK                                                               0x0F000000L
3895 #define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS_MASK                                                               0xF0000000L
3896 //SQ_IMG_RSRC_WORD7
3897 #define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS__SHIFT                                                           0x0
3898 #define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS_MASK                                                             0xFFFFFFFFL
3899 //SQ_IMG_SAMP_WORD0
3900 #define SQ_IMG_SAMP_WORD0__CLAMP_X__SHIFT                                                                     0x0
3901 #define SQ_IMG_SAMP_WORD0__CLAMP_Y__SHIFT                                                                     0x3
3902 #define SQ_IMG_SAMP_WORD0__CLAMP_Z__SHIFT                                                                     0x6
3903 #define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO__SHIFT                                                             0x9
3904 #define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC__SHIFT                                                          0xc
3905 #define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED__SHIFT                                                          0xf
3906 #define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD__SHIFT                                                             0x10
3907 #define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC__SHIFT                                                              0x13
3908 #define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA__SHIFT                                                               0x14
3909 #define SQ_IMG_SAMP_WORD0__ANISO_BIAS__SHIFT                                                                  0x15
3910 #define SQ_IMG_SAMP_WORD0__TRUNC_COORD__SHIFT                                                                 0x1b
3911 #define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP__SHIFT                                                           0x1c
3912 #define SQ_IMG_SAMP_WORD0__FILTER_MODE__SHIFT                                                                 0x1d
3913 #define SQ_IMG_SAMP_WORD0__COMPAT_MODE__SHIFT                                                                 0x1f
3914 #define SQ_IMG_SAMP_WORD0__CLAMP_X_MASK                                                                       0x00000007L
3915 #define SQ_IMG_SAMP_WORD0__CLAMP_Y_MASK                                                                       0x00000038L
3916 #define SQ_IMG_SAMP_WORD0__CLAMP_Z_MASK                                                                       0x000001C0L
3917 #define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO_MASK                                                               0x00000E00L
3918 #define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC_MASK                                                            0x00007000L
3919 #define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED_MASK                                                            0x00008000L
3920 #define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD_MASK                                                               0x00070000L
3921 #define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC_MASK                                                                0x00080000L
3922 #define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA_MASK                                                                 0x00100000L
3923 #define SQ_IMG_SAMP_WORD0__ANISO_BIAS_MASK                                                                    0x07E00000L
3924 #define SQ_IMG_SAMP_WORD0__TRUNC_COORD_MASK                                                                   0x08000000L
3925 #define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP_MASK                                                             0x10000000L
3926 #define SQ_IMG_SAMP_WORD0__FILTER_MODE_MASK                                                                   0x60000000L
3927 #define SQ_IMG_SAMP_WORD0__COMPAT_MODE_MASK                                                                   0x80000000L
3928 //SQ_IMG_SAMP_WORD1
3929 #define SQ_IMG_SAMP_WORD1__MIN_LOD__SHIFT                                                                     0x0
3930 #define SQ_IMG_SAMP_WORD1__MAX_LOD__SHIFT                                                                     0xc
3931 #define SQ_IMG_SAMP_WORD1__PERF_MIP__SHIFT                                                                    0x18
3932 #define SQ_IMG_SAMP_WORD1__PERF_Z__SHIFT                                                                      0x1c
3933 #define SQ_IMG_SAMP_WORD1__MIN_LOD_MASK                                                                       0x00000FFFL
3934 #define SQ_IMG_SAMP_WORD1__MAX_LOD_MASK                                                                       0x00FFF000L
3935 #define SQ_IMG_SAMP_WORD1__PERF_MIP_MASK                                                                      0x0F000000L
3936 #define SQ_IMG_SAMP_WORD1__PERF_Z_MASK                                                                        0xF0000000L
3937 //SQ_IMG_SAMP_WORD2
3938 #define SQ_IMG_SAMP_WORD2__LOD_BIAS__SHIFT                                                                    0x0
3939 #define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC__SHIFT                                                                0xe
3940 #define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER__SHIFT                                                               0x14
3941 #define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER__SHIFT                                                               0x16
3942 #define SQ_IMG_SAMP_WORD2__Z_FILTER__SHIFT                                                                    0x18
3943 #define SQ_IMG_SAMP_WORD2__MIP_FILTER__SHIFT                                                                  0x1a
3944 #define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP__SHIFT                                                          0x1c
3945 #define SQ_IMG_SAMP_WORD2__BLEND_ZERO_PRT__SHIFT                                                              0x1d
3946 #define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX__SHIFT                                                             0x1e
3947 #define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE__SHIFT                                                              0x1f
3948 #define SQ_IMG_SAMP_WORD2__LOD_BIAS_MASK                                                                      0x00003FFFL
3949 #define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC_MASK                                                                  0x000FC000L
3950 #define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER_MASK                                                                 0x00300000L
3951 #define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER_MASK                                                                 0x00C00000L
3952 #define SQ_IMG_SAMP_WORD2__Z_FILTER_MASK                                                                      0x03000000L
3953 #define SQ_IMG_SAMP_WORD2__MIP_FILTER_MASK                                                                    0x0C000000L
3954 #define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP_MASK                                                            0x10000000L
3955 #define SQ_IMG_SAMP_WORD2__BLEND_ZERO_PRT_MASK                                                                0x20000000L
3956 #define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX_MASK                                                               0x40000000L
3957 #define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE_MASK                                                                0x80000000L
3958 //SQ_IMG_SAMP_WORD3
3959 #define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR__SHIFT                                                            0x0
3960 #define SQ_IMG_SAMP_WORD3__SKIP_DEGAMMA__SHIFT                                                                0xc
3961 #define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE__SHIFT                                                           0x1e
3962 #define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR_MASK                                                              0x00000FFFL
3963 #define SQ_IMG_SAMP_WORD3__SKIP_DEGAMMA_MASK                                                                  0x00001000L
3964 #define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE_MASK                                                             0xC0000000L
3965 //SQ_FLAT_SCRATCH_WORD0
3966 #define SQ_FLAT_SCRATCH_WORD0__SIZE__SHIFT                                                                    0x0
3967 #define SQ_FLAT_SCRATCH_WORD0__SIZE_MASK                                                                      0x0007FFFFL
3968 //SQ_FLAT_SCRATCH_WORD1
3969 #define SQ_FLAT_SCRATCH_WORD1__OFFSET__SHIFT                                                                  0x0
3970 #define SQ_FLAT_SCRATCH_WORD1__OFFSET_MASK                                                                    0x00FFFFFFL
3971 //SQ_M0_GPR_IDX_WORD
3972 #define SQ_M0_GPR_IDX_WORD__INDEX__SHIFT                                                                      0x0
3973 #define SQ_M0_GPR_IDX_WORD__VSRC0_REL__SHIFT                                                                  0xc
3974 #define SQ_M0_GPR_IDX_WORD__VSRC1_REL__SHIFT                                                                  0xd
3975 #define SQ_M0_GPR_IDX_WORD__VSRC2_REL__SHIFT                                                                  0xe
3976 #define SQ_M0_GPR_IDX_WORD__VDST_REL__SHIFT                                                                   0xf
3977 #define SQ_M0_GPR_IDX_WORD__INDEX_MASK                                                                        0x000000FFL
3978 #define SQ_M0_GPR_IDX_WORD__VSRC0_REL_MASK                                                                    0x00001000L
3979 #define SQ_M0_GPR_IDX_WORD__VSRC1_REL_MASK                                                                    0x00002000L
3980 #define SQ_M0_GPR_IDX_WORD__VSRC2_REL_MASK                                                                    0x00004000L
3981 #define SQ_M0_GPR_IDX_WORD__VDST_REL_MASK                                                                     0x00008000L
3982 //SQC_ICACHE_UTCL1_CNTL1
3983 #define SQC_ICACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT                                                       0x0
3984 #define SQC_ICACHE_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT                                                          0x1
3985 #define SQC_ICACHE_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT                                                        0x2
3986 #define SQC_ICACHE_UTCL1_CNTL1__RESP_MODE__SHIFT                                                              0x3
3987 #define SQC_ICACHE_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT                                                        0x5
3988 #define SQC_ICACHE_UTCL1_CNTL1__CLIENTID__SHIFT                                                               0x7
3989 #define SQC_ICACHE_UTCL1_CNTL1__RESERVED__SHIFT                                                               0x10
3990 #define SQC_ICACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT                                                      0x11
3991 #define SQC_ICACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT                                                   0x12
3992 #define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT                                                    0x13
3993 #define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT                                                0x17
3994 #define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT                                                  0x18
3995 #define SQC_ICACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT                                             0x19
3996 #define SQC_ICACHE_UTCL1_CNTL1__FORCE_MISS__SHIFT                                                             0x1a
3997 #define SQC_ICACHE_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT                                                         0x1b
3998 #define SQC_ICACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT                                                 0x1c
3999 #define SQC_ICACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT                                                 0x1e
4000 #define SQC_ICACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK                                                         0x00000001L
4001 #define SQC_ICACHE_UTCL1_CNTL1__GPUVM_64K_DEF_MASK                                                            0x00000002L
4002 #define SQC_ICACHE_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK                                                          0x00000004L
4003 #define SQC_ICACHE_UTCL1_CNTL1__RESP_MODE_MASK                                                                0x00000018L
4004 #define SQC_ICACHE_UTCL1_CNTL1__RESP_FAULT_MODE_MASK                                                          0x00000060L
4005 #define SQC_ICACHE_UTCL1_CNTL1__CLIENTID_MASK                                                                 0x0000FF80L
4006 #define SQC_ICACHE_UTCL1_CNTL1__RESERVED_MASK                                                                 0x00010000L
4007 #define SQC_ICACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK                                                        0x00020000L
4008 #define SQC_ICACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK                                                     0x00040000L
4009 #define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK                                                      0x00780000L
4010 #define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK                                                  0x00800000L
4011 #define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK                                                    0x01000000L
4012 #define SQC_ICACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK                                               0x02000000L
4013 #define SQC_ICACHE_UTCL1_CNTL1__FORCE_MISS_MASK                                                               0x04000000L
4014 #define SQC_ICACHE_UTCL1_CNTL1__FORCE_IN_ORDER_MASK                                                           0x08000000L
4015 #define SQC_ICACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK                                                   0x30000000L
4016 #define SQC_ICACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK                                                   0xC0000000L
4017 //SQC_ICACHE_UTCL1_CNTL2
4018 #define SQC_ICACHE_UTCL1_CNTL2__SPARE__SHIFT                                                                  0x0
4019 #define SQC_ICACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT                                                     0x8
4020 #define SQC_ICACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT                                                         0x9
4021 #define SQC_ICACHE_UTCL1_CNTL2__LINE_VALID__SHIFT                                                             0xa
4022 #define SQC_ICACHE_UTCL1_CNTL2__DIS_EDC__SHIFT                                                                0xb
4023 #define SQC_ICACHE_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT                                                         0xc
4024 #define SQC_ICACHE_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT                                                          0xd
4025 #define SQC_ICACHE_UTCL1_CNTL2__FORCE_SNOOP__SHIFT                                                            0xe
4026 #define SQC_ICACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT                                                    0xf
4027 #define SQC_ICACHE_UTCL1_CNTL2__ARB_BURST_MODE__SHIFT                                                         0x10
4028 #define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT                                                0x12
4029 #define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT                                                       0x13
4030 #define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT                                                 0x14
4031 #define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT                                                        0x15
4032 #define SQC_ICACHE_UTCL1_CNTL2__RESERVED__SHIFT                                                               0x19
4033 #define SQC_ICACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT                                                   0x1a
4034 #define SQC_ICACHE_UTCL1_CNTL2__SPARE_MASK                                                                    0x000000FFL
4035 #define SQC_ICACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK                                                       0x00000100L
4036 #define SQC_ICACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK                                                           0x00000200L
4037 #define SQC_ICACHE_UTCL1_CNTL2__LINE_VALID_MASK                                                               0x00000400L
4038 #define SQC_ICACHE_UTCL1_CNTL2__DIS_EDC_MASK                                                                  0x00000800L
4039 #define SQC_ICACHE_UTCL1_CNTL2__GPUVM_INV_MODE_MASK                                                           0x00001000L
4040 #define SQC_ICACHE_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK                                                            0x00002000L
4041 #define SQC_ICACHE_UTCL1_CNTL2__FORCE_SNOOP_MASK                                                              0x00004000L
4042 #define SQC_ICACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK                                                      0x00008000L
4043 #define SQC_ICACHE_UTCL1_CNTL2__ARB_BURST_MODE_MASK                                                           0x00030000L
4044 #define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK                                                  0x00040000L
4045 #define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK                                                         0x00080000L
4046 #define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK                                                   0x00100000L
4047 #define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_VMID_MASK                                                          0x01E00000L
4048 #define SQC_ICACHE_UTCL1_CNTL2__RESERVED_MASK                                                                 0x02000000L
4049 #define SQC_ICACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK                                                     0x04000000L
4050 //SQC_DCACHE_UTCL1_CNTL1
4051 #define SQC_DCACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT                                                       0x0
4052 #define SQC_DCACHE_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT                                                          0x1
4053 #define SQC_DCACHE_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT                                                        0x2
4054 #define SQC_DCACHE_UTCL1_CNTL1__RESP_MODE__SHIFT                                                              0x3
4055 #define SQC_DCACHE_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT                                                        0x5
4056 #define SQC_DCACHE_UTCL1_CNTL1__CLIENTID__SHIFT                                                               0x7
4057 #define SQC_DCACHE_UTCL1_CNTL1__RESERVED__SHIFT                                                               0x10
4058 #define SQC_DCACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT                                                      0x11
4059 #define SQC_DCACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT                                                   0x12
4060 #define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT                                                    0x13
4061 #define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT                                                0x17
4062 #define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT                                                  0x18
4063 #define SQC_DCACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT                                             0x19
4064 #define SQC_DCACHE_UTCL1_CNTL1__FORCE_MISS__SHIFT                                                             0x1a
4065 #define SQC_DCACHE_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT                                                         0x1b
4066 #define SQC_DCACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT                                                 0x1c
4067 #define SQC_DCACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT                                                 0x1e
4068 #define SQC_DCACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK                                                         0x00000001L
4069 #define SQC_DCACHE_UTCL1_CNTL1__GPUVM_64K_DEF_MASK                                                            0x00000002L
4070 #define SQC_DCACHE_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK                                                          0x00000004L
4071 #define SQC_DCACHE_UTCL1_CNTL1__RESP_MODE_MASK                                                                0x00000018L
4072 #define SQC_DCACHE_UTCL1_CNTL1__RESP_FAULT_MODE_MASK                                                          0x00000060L
4073 #define SQC_DCACHE_UTCL1_CNTL1__CLIENTID_MASK                                                                 0x0000FF80L
4074 #define SQC_DCACHE_UTCL1_CNTL1__RESERVED_MASK                                                                 0x00010000L
4075 #define SQC_DCACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK                                                        0x00020000L
4076 #define SQC_DCACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK                                                     0x00040000L
4077 #define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK                                                      0x00780000L
4078 #define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK                                                  0x00800000L
4079 #define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK                                                    0x01000000L
4080 #define SQC_DCACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK                                               0x02000000L
4081 #define SQC_DCACHE_UTCL1_CNTL1__FORCE_MISS_MASK                                                               0x04000000L
4082 #define SQC_DCACHE_UTCL1_CNTL1__FORCE_IN_ORDER_MASK                                                           0x08000000L
4083 #define SQC_DCACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK                                                   0x30000000L
4084 #define SQC_DCACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK                                                   0xC0000000L
4085 //SQC_DCACHE_UTCL1_CNTL2
4086 #define SQC_DCACHE_UTCL1_CNTL2__SPARE__SHIFT                                                                  0x0
4087 #define SQC_DCACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT                                                     0x8
4088 #define SQC_DCACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT                                                         0x9
4089 #define SQC_DCACHE_UTCL1_CNTL2__LINE_VALID__SHIFT                                                             0xa
4090 #define SQC_DCACHE_UTCL1_CNTL2__DIS_EDC__SHIFT                                                                0xb
4091 #define SQC_DCACHE_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT                                                         0xc
4092 #define SQC_DCACHE_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT                                                          0xd
4093 #define SQC_DCACHE_UTCL1_CNTL2__FORCE_SNOOP__SHIFT                                                            0xe
4094 #define SQC_DCACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT                                                    0xf
4095 #define SQC_DCACHE_UTCL1_CNTL2__ARB_BURST_MODE__SHIFT                                                         0x10
4096 #define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT                                                0x12
4097 #define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT                                                       0x13
4098 #define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT                                                 0x14
4099 #define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT                                                        0x15
4100 #define SQC_DCACHE_UTCL1_CNTL2__RESERVED__SHIFT                                                               0x19
4101 #define SQC_DCACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT                                                   0x1a
4102 #define SQC_DCACHE_UTCL1_CNTL2__SPARE_MASK                                                                    0x000000FFL
4103 #define SQC_DCACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK                                                       0x00000100L
4104 #define SQC_DCACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK                                                           0x00000200L
4105 #define SQC_DCACHE_UTCL1_CNTL2__LINE_VALID_MASK                                                               0x00000400L
4106 #define SQC_DCACHE_UTCL1_CNTL2__DIS_EDC_MASK                                                                  0x00000800L
4107 #define SQC_DCACHE_UTCL1_CNTL2__GPUVM_INV_MODE_MASK                                                           0x00001000L
4108 #define SQC_DCACHE_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK                                                            0x00002000L
4109 #define SQC_DCACHE_UTCL1_CNTL2__FORCE_SNOOP_MASK                                                              0x00004000L
4110 #define SQC_DCACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK                                                      0x00008000L
4111 #define SQC_DCACHE_UTCL1_CNTL2__ARB_BURST_MODE_MASK                                                           0x00030000L
4112 #define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK                                                  0x00040000L
4113 #define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK                                                         0x00080000L
4114 #define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK                                                   0x00100000L
4115 #define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_VMID_MASK                                                          0x01E00000L
4116 #define SQC_DCACHE_UTCL1_CNTL2__RESERVED_MASK                                                                 0x02000000L
4117 #define SQC_DCACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK                                                     0x04000000L
4118 //SQC_ICACHE_UTCL1_STATUS
4119 #define SQC_ICACHE_UTCL1_STATUS__FAULT_DETECTED__SHIFT                                                        0x0
4120 #define SQC_ICACHE_UTCL1_STATUS__RETRY_DETECTED__SHIFT                                                        0x1
4121 #define SQC_ICACHE_UTCL1_STATUS__PRT_DETECTED__SHIFT                                                          0x2
4122 #define SQC_ICACHE_UTCL1_STATUS__FAULT_DETECTED_MASK                                                          0x00000001L
4123 #define SQC_ICACHE_UTCL1_STATUS__RETRY_DETECTED_MASK                                                          0x00000002L
4124 #define SQC_ICACHE_UTCL1_STATUS__PRT_DETECTED_MASK                                                            0x00000004L
4125 //SQC_DCACHE_UTCL1_STATUS
4126 #define SQC_DCACHE_UTCL1_STATUS__FAULT_DETECTED__SHIFT                                                        0x0
4127 #define SQC_DCACHE_UTCL1_STATUS__RETRY_DETECTED__SHIFT                                                        0x1
4128 #define SQC_DCACHE_UTCL1_STATUS__PRT_DETECTED__SHIFT                                                          0x2
4129 #define SQC_DCACHE_UTCL1_STATUS__FAULT_DETECTED_MASK                                                          0x00000001L
4130 #define SQC_DCACHE_UTCL1_STATUS__RETRY_DETECTED_MASK                                                          0x00000002L
4131 #define SQC_DCACHE_UTCL1_STATUS__PRT_DETECTED_MASK                                                            0x00000004L
4132 //SQC_UE_EDC_LO
4133 #define SQC_UE_EDC_LO__STATUS_VALID_FLAG__SHIFT                                                               0x0
4134 #define SQC_UE_EDC_LO__ADDRESS_INFO_VALID_FLAG__SHIFT                                                         0x1
4135 #define SQC_UE_EDC_LO__ADDRESS__SHIFT                                                                         0x2
4136 #define SQC_UE_EDC_LO__MEM_ID__SHIFT                                                                          0x18
4137 #define SQC_UE_EDC_LO__STATUS_VALID_FLAG_MASK                                                                 0x00000001L
4138 #define SQC_UE_EDC_LO__ADDRESS_INFO_VALID_FLAG_MASK                                                           0x00000002L
4139 #define SQC_UE_EDC_LO__ADDRESS_MASK                                                                           0x00FFFFFCL
4140 #define SQC_UE_EDC_LO__MEM_ID_MASK                                                                            0xFF000000L
4141 //SQC_UE_EDC_HI
4142 #define SQC_UE_EDC_HI__ECC__SHIFT                                                                             0x0
4143 #define SQC_UE_EDC_HI__PARITY__SHIFT                                                                          0x1
4144 #define SQC_UE_EDC_HI__ERR_INFO_VALID_FLAG__SHIFT                                                             0x2
4145 #define SQC_UE_EDC_HI__ERR_INFO__SHIFT                                                                        0x3
4146 #define SQC_UE_EDC_HI__UE_CNT__SHIFT                                                                          0x17
4147 #define SQC_UE_EDC_HI__FED_CNT__SHIFT                                                                         0x1a
4148 #define SQC_UE_EDC_HI__ECC_MASK                                                                               0x00000001L
4149 #define SQC_UE_EDC_HI__PARITY_MASK                                                                            0x00000002L
4150 #define SQC_UE_EDC_HI__ERR_INFO_VALID_FLAG_MASK                                                               0x00000004L
4151 #define SQC_UE_EDC_HI__ERR_INFO_MASK                                                                          0x007FFFF8L
4152 #define SQC_UE_EDC_HI__UE_CNT_MASK                                                                            0x03800000L
4153 #define SQC_UE_EDC_HI__FED_CNT_MASK                                                                           0x1C000000L
4154 //SQC_CE_EDC_LO
4155 #define SQC_CE_EDC_LO__STATUS_VALID_FLAG__SHIFT                                                               0x0
4156 #define SQC_CE_EDC_LO__ADDRESS_INFO_VALID_FLAG__SHIFT                                                         0x1
4157 #define SQC_CE_EDC_LO__ADDRESS__SHIFT                                                                         0x2
4158 #define SQC_CE_EDC_LO__MEM_ID__SHIFT                                                                          0x18
4159 #define SQC_CE_EDC_LO__STATUS_VALID_FLAG_MASK                                                                 0x00000001L
4160 #define SQC_CE_EDC_LO__ADDRESS_INFO_VALID_FLAG_MASK                                                           0x00000002L
4161 #define SQC_CE_EDC_LO__ADDRESS_MASK                                                                           0x00FFFFFCL
4162 #define SQC_CE_EDC_LO__MEM_ID_MASK                                                                            0xFF000000L
4163 //SQC_CE_EDC_HI
4164 #define SQC_CE_EDC_HI__ECC__SHIFT                                                                             0x0
4165 #define SQC_CE_EDC_HI__ERR_INFO_VALID_FLAG__SHIFT                                                             0x2
4166 #define SQC_CE_EDC_HI__ERR_INFO__SHIFT                                                                        0x3
4167 #define SQC_CE_EDC_HI__CE_CNT__SHIFT                                                                          0x17
4168 #define SQC_CE_EDC_HI__POSION__SHIFT                                                                          0x1a
4169 #define SQC_CE_EDC_HI__ECC_MASK                                                                               0x00000001L
4170 #define SQC_CE_EDC_HI__ERR_INFO_VALID_FLAG_MASK                                                               0x00000004L
4171 #define SQC_CE_EDC_HI__ERR_INFO_MASK                                                                          0x007FFFF8L
4172 #define SQC_CE_EDC_HI__CE_CNT_MASK                                                                            0x03800000L
4173 #define SQC_CE_EDC_HI__POSION_MASK                                                                            0x04000000L
4174 //SQ_UE_ERR_STATUS_LO
4175 #define SQ_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT                                                     0x0
4176 #define SQ_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT                                                        0x1
4177 #define SQ_UE_ERR_STATUS_LO__ADDRESS__SHIFT                                                                   0x2
4178 #define SQ_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT                                                                 0x18
4179 #define SQ_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK                                                       0x00000001L
4180 #define SQ_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK                                                          0x00000002L
4181 #define SQ_UE_ERR_STATUS_LO__ADDRESS_MASK                                                                     0x00FFFFFCL
4182 #define SQ_UE_ERR_STATUS_LO__MEMORY_ID_MASK                                                                   0xFF000000L
4183 //SQ_UE_ERR_STATUS_HI
4184 #define SQ_UE_ERR_STATUS_HI__ECC__SHIFT                                                                       0x0
4185 #define SQ_UE_ERR_STATUS_HI__PARITY__SHIFT                                                                    0x1
4186 #define SQ_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT                                                       0x2
4187 #define SQ_UE_ERR_STATUS_HI__ERR_INFO__SHIFT                                                                  0x3
4188 #define SQ_UE_ERR_STATUS_HI__UE_CNT__SHIFT                                                                    0x17
4189 #define SQ_UE_ERR_STATUS_HI__FED_CNT__SHIFT                                                                   0x1a
4190 #define SQ_UE_ERR_STATUS_HI__RESERVED__SHIFT                                                                  0x1d
4191 #define SQ_UE_ERR_STATUS_HI__ECC_MASK                                                                         0x00000001L
4192 #define SQ_UE_ERR_STATUS_HI__PARITY_MASK                                                                      0x00000002L
4193 #define SQ_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK                                                         0x00000004L
4194 #define SQ_UE_ERR_STATUS_HI__ERR_INFO_MASK                                                                    0x007FFFF8L
4195 #define SQ_UE_ERR_STATUS_HI__UE_CNT_MASK                                                                      0x03800000L
4196 #define SQ_UE_ERR_STATUS_HI__FED_CNT_MASK                                                                     0x1C000000L
4197 #define SQ_UE_ERR_STATUS_HI__RESERVED_MASK                                                                    0xE0000000L
4198 //SQ_CE_ERR_STATUS_LO
4199 #define SQ_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT                                                     0x0
4200 #define SQ_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT                                                        0x1
4201 #define SQ_CE_ERR_STATUS_LO__ADDRESS__SHIFT                                                                   0x2
4202 #define SQ_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT                                                                 0x18
4203 #define SQ_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK                                                       0x00000001L
4204 #define SQ_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK                                                          0x00000002L
4205 #define SQ_CE_ERR_STATUS_LO__ADDRESS_MASK                                                                     0x00FFFFFCL
4206 #define SQ_CE_ERR_STATUS_LO__MEMORY_ID_MASK                                                                   0xFF000000L
4207 //SQ_CE_ERR_STATUS_HI
4208 #define SQ_CE_ERR_STATUS_HI__ECC__SHIFT                                                                       0x0
4209 #define SQ_CE_ERR_STATUS_HI__OTHER__SHIFT                                                                     0x1
4210 #define SQ_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT                                                       0x2
4211 #define SQ_CE_ERR_STATUS_HI__ERR_INFO__SHIFT                                                                  0x3
4212 #define SQ_CE_ERR_STATUS_HI__CE_CNT__SHIFT                                                                    0x17
4213 #define SQ_CE_ERR_STATUS_HI__POISON__SHIFT                                                                    0x1a
4214 #define SQ_CE_ERR_STATUS_HI__RESERVED__SHIFT                                                                  0x1b
4215 #define SQ_CE_ERR_STATUS_HI__ECC_MASK                                                                         0x00000001L
4216 #define SQ_CE_ERR_STATUS_HI__OTHER_MASK                                                                       0x00000002L
4217 #define SQ_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK                                                         0x00000004L
4218 #define SQ_CE_ERR_STATUS_HI__ERR_INFO_MASK                                                                    0x007FFFF8L
4219 #define SQ_CE_ERR_STATUS_HI__CE_CNT_MASK                                                                      0x03800000L
4220 #define SQ_CE_ERR_STATUS_HI__POISON_MASK                                                                      0x04000000L
4221 #define SQ_CE_ERR_STATUS_HI__RESERVED_MASK                                                                    0xF8000000L
4222 //LDS_UE_ERR_STATUS_LO
4223 #define LDS_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT                                                    0x0
4224 #define LDS_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT                                                       0x1
4225 #define LDS_UE_ERR_STATUS_LO__ADDRESS__SHIFT                                                                  0x2
4226 #define LDS_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT                                                                0x18
4227 #define LDS_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK                                                      0x00000001L
4228 #define LDS_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK                                                         0x00000002L
4229 #define LDS_UE_ERR_STATUS_LO__ADDRESS_MASK                                                                    0x00FFFFFCL
4230 #define LDS_UE_ERR_STATUS_LO__MEMORY_ID_MASK                                                                  0xFF000000L
4231 //LDS_UE_ERR_STATUS_HI
4232 #define LDS_UE_ERR_STATUS_HI__ECC__SHIFT                                                                      0x0
4233 #define LDS_UE_ERR_STATUS_HI__PARITY__SHIFT                                                                   0x1
4234 #define LDS_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT                                                      0x2
4235 #define LDS_UE_ERR_STATUS_HI__ERR_INFO__SHIFT                                                                 0x3
4236 #define LDS_UE_ERR_STATUS_HI__UE_CNT__SHIFT                                                                   0x17
4237 #define LDS_UE_ERR_STATUS_HI__FED_CNT__SHIFT                                                                  0x1a
4238 #define LDS_UE_ERR_STATUS_HI__RESERVED__SHIFT                                                                 0x1d
4239 #define LDS_UE_ERR_STATUS_HI__ECC_MASK                                                                        0x00000001L
4240 #define LDS_UE_ERR_STATUS_HI__PARITY_MASK                                                                     0x00000002L
4241 #define LDS_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK                                                        0x00000004L
4242 #define LDS_UE_ERR_STATUS_HI__ERR_INFO_MASK                                                                   0x007FFFF8L
4243 #define LDS_UE_ERR_STATUS_HI__UE_CNT_MASK                                                                     0x03800000L
4244 #define LDS_UE_ERR_STATUS_HI__FED_CNT_MASK                                                                    0x1C000000L
4245 #define LDS_UE_ERR_STATUS_HI__RESERVED_MASK                                                                   0xE0000000L
4246 //LDS_CE_ERR_STATUS_LO
4247 #define LDS_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT                                                    0x0
4248 #define LDS_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT                                                       0x1
4249 #define LDS_CE_ERR_STATUS_LO__ADDRESS__SHIFT                                                                  0x2
4250 #define LDS_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT                                                                0x18
4251 #define LDS_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK                                                      0x00000001L
4252 #define LDS_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK                                                         0x00000002L
4253 #define LDS_CE_ERR_STATUS_LO__ADDRESS_MASK                                                                    0x00FFFFFCL
4254 #define LDS_CE_ERR_STATUS_LO__MEMORY_ID_MASK                                                                  0xFF000000L
4255 //LDS_CE_ERR_STATUS_HI
4256 #define LDS_CE_ERR_STATUS_HI__ECC__SHIFT                                                                      0x0
4257 #define LDS_CE_ERR_STATUS_HI__OTHER__SHIFT                                                                    0x1
4258 #define LDS_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT                                                      0x2
4259 #define LDS_CE_ERR_STATUS_HI__ERR_INFO__SHIFT                                                                 0x3
4260 #define LDS_CE_ERR_STATUS_HI__CE_CNT__SHIFT                                                                   0x17
4261 #define LDS_CE_ERR_STATUS_HI__POISON__SHIFT                                                                   0x1a
4262 #define LDS_CE_ERR_STATUS_HI__RESERVED__SHIFT                                                                 0x1b
4263 #define LDS_CE_ERR_STATUS_HI__ECC_MASK                                                                        0x00000001L
4264 #define LDS_CE_ERR_STATUS_HI__OTHER_MASK                                                                      0x00000002L
4265 #define LDS_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK                                                        0x00000004L
4266 #define LDS_CE_ERR_STATUS_HI__ERR_INFO_MASK                                                                   0x007FFFF8L
4267 #define LDS_CE_ERR_STATUS_HI__CE_CNT_MASK                                                                     0x03800000L
4268 #define LDS_CE_ERR_STATUS_HI__POISON_MASK                                                                     0x04000000L
4269 #define LDS_CE_ERR_STATUS_HI__RESERVED_MASK                                                                   0xF8000000L
4270 //SP0_UE_ERR_STATUS_LO
4271 #define SP0_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT                                                    0x0
4272 #define SP0_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT                                                       0x1
4273 #define SP0_UE_ERR_STATUS_LO__ADDRESS__SHIFT                                                                  0x2
4274 #define SP0_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT                                                                0x18
4275 #define SP0_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK                                                      0x00000001L
4276 #define SP0_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK                                                         0x00000002L
4277 #define SP0_UE_ERR_STATUS_LO__ADDRESS_MASK                                                                    0x00FFFFFCL
4278 #define SP0_UE_ERR_STATUS_LO__MEMORY_ID_MASK                                                                  0xFF000000L
4279 //SP0_UE_ERR_STATUS_HI
4280 #define SP0_UE_ERR_STATUS_HI__ECC__SHIFT                                                                      0x0
4281 #define SP0_UE_ERR_STATUS_HI__PARITY__SHIFT                                                                   0x1
4282 #define SP0_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT                                                      0x2
4283 #define SP0_UE_ERR_STATUS_HI__ERR_INFO__SHIFT                                                                 0x3
4284 #define SP0_UE_ERR_STATUS_HI__UE_CNT__SHIFT                                                                   0x17
4285 #define SP0_UE_ERR_STATUS_HI__FED_CNT__SHIFT                                                                  0x1a
4286 #define SP0_UE_ERR_STATUS_HI__RESERVED__SHIFT                                                                 0x1d
4287 #define SP0_UE_ERR_STATUS_HI__ECC_MASK                                                                        0x00000001L
4288 #define SP0_UE_ERR_STATUS_HI__PARITY_MASK                                                                     0x00000002L
4289 #define SP0_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK                                                        0x00000004L
4290 #define SP0_UE_ERR_STATUS_HI__ERR_INFO_MASK                                                                   0x007FFFF8L
4291 #define SP0_UE_ERR_STATUS_HI__UE_CNT_MASK                                                                     0x03800000L
4292 #define SP0_UE_ERR_STATUS_HI__FED_CNT_MASK                                                                    0x1C000000L
4293 #define SP0_UE_ERR_STATUS_HI__RESERVED_MASK                                                                   0xE0000000L
4294 //SP0_CE_ERR_STATUS_LO
4295 #define SP0_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT                                                    0x0
4296 #define SP0_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT                                                       0x1
4297 #define SP0_CE_ERR_STATUS_LO__ADDRESS__SHIFT                                                                  0x2
4298 #define SP0_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT                                                                0x18
4299 #define SP0_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK                                                      0x00000001L
4300 #define SP0_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK                                                         0x00000002L
4301 #define SP0_CE_ERR_STATUS_LO__ADDRESS_MASK                                                                    0x00FFFFFCL
4302 #define SP0_CE_ERR_STATUS_LO__MEMORY_ID_MASK                                                                  0xFF000000L
4303 //SP0_CE_ERR_STATUS_HI
4304 #define SP0_CE_ERR_STATUS_HI__ECC__SHIFT                                                                      0x0
4305 #define SP0_CE_ERR_STATUS_HI__OTHER__SHIFT                                                                    0x1
4306 #define SP0_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT                                                      0x2
4307 #define SP0_CE_ERR_STATUS_HI__ERR_INFO__SHIFT                                                                 0x3
4308 #define SP0_CE_ERR_STATUS_HI__CE_CNT__SHIFT                                                                   0x17
4309 #define SP0_CE_ERR_STATUS_HI__POISON__SHIFT                                                                   0x1a
4310 #define SP0_CE_ERR_STATUS_HI__RESERVED__SHIFT                                                                 0x1b
4311 #define SP0_CE_ERR_STATUS_HI__ECC_MASK                                                                        0x00000001L
4312 #define SP0_CE_ERR_STATUS_HI__OTHER_MASK                                                                      0x00000002L
4313 #define SP0_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK                                                        0x00000004L
4314 #define SP0_CE_ERR_STATUS_HI__ERR_INFO_MASK                                                                   0x007FFFF8L
4315 #define SP0_CE_ERR_STATUS_HI__CE_CNT_MASK                                                                     0x03800000L
4316 #define SP0_CE_ERR_STATUS_HI__POISON_MASK                                                                     0x04000000L
4317 #define SP0_CE_ERR_STATUS_HI__RESERVED_MASK                                                                   0xF8000000L
4318 //SP1_UE_ERR_STATUS_LO
4319 #define SP1_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT                                                    0x0
4320 #define SP1_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT                                                       0x1
4321 #define SP1_UE_ERR_STATUS_LO__ADDRESS__SHIFT                                                                  0x2
4322 #define SP1_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT                                                                0x18
4323 #define SP1_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK                                                      0x00000001L
4324 #define SP1_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK                                                         0x00000002L
4325 #define SP1_UE_ERR_STATUS_LO__ADDRESS_MASK                                                                    0x00FFFFFCL
4326 #define SP1_UE_ERR_STATUS_LO__MEMORY_ID_MASK                                                                  0xFF000000L
4327 //SP1_UE_ERR_STATUS_HI
4328 #define SP1_UE_ERR_STATUS_HI__ECC__SHIFT                                                                      0x0
4329 #define SP1_UE_ERR_STATUS_HI__PARITY__SHIFT                                                                   0x1
4330 #define SP1_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT                                                      0x2
4331 #define SP1_UE_ERR_STATUS_HI__ERR_INFO__SHIFT                                                                 0x3
4332 #define SP1_UE_ERR_STATUS_HI__UE_CNT__SHIFT                                                                   0x17
4333 #define SP1_UE_ERR_STATUS_HI__FED_CNT__SHIFT                                                                  0x1a
4334 #define SP1_UE_ERR_STATUS_HI__RESERVED__SHIFT                                                                 0x1d
4335 #define SP1_UE_ERR_STATUS_HI__ECC_MASK                                                                        0x00000001L
4336 #define SP1_UE_ERR_STATUS_HI__PARITY_MASK                                                                     0x00000002L
4337 #define SP1_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK                                                        0x00000004L
4338 #define SP1_UE_ERR_STATUS_HI__ERR_INFO_MASK                                                                   0x007FFFF8L
4339 #define SP1_UE_ERR_STATUS_HI__UE_CNT_MASK                                                                     0x03800000L
4340 #define SP1_UE_ERR_STATUS_HI__FED_CNT_MASK                                                                    0x1C000000L
4341 #define SP1_UE_ERR_STATUS_HI__RESERVED_MASK                                                                   0xE0000000L
4342 //SP1_CE_ERR_STATUS_LO
4343 #define SP1_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT                                                    0x0
4344 #define SP1_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT                                                       0x1
4345 #define SP1_CE_ERR_STATUS_LO__ADDRESS__SHIFT                                                                  0x2
4346 #define SP1_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT                                                                0x18
4347 #define SP1_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK                                                      0x00000001L
4348 #define SP1_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK                                                         0x00000002L
4349 #define SP1_CE_ERR_STATUS_LO__ADDRESS_MASK                                                                    0x00FFFFFCL
4350 #define SP1_CE_ERR_STATUS_LO__MEMORY_ID_MASK                                                                  0xFF000000L
4351 //SP1_CE_ERR_STATUS_HI
4352 #define SP1_CE_ERR_STATUS_HI__ECC__SHIFT                                                                      0x0
4353 #define SP1_CE_ERR_STATUS_HI__OTHER__SHIFT                                                                    0x1
4354 #define SP1_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT                                                      0x2
4355 #define SP1_CE_ERR_STATUS_HI__ERR_INFO__SHIFT                                                                 0x3
4356 #define SP1_CE_ERR_STATUS_HI__CE_CNT__SHIFT                                                                   0x17
4357 #define SP1_CE_ERR_STATUS_HI__POISON__SHIFT                                                                   0x1a
4358 #define SP1_CE_ERR_STATUS_HI__RESERVED__SHIFT                                                                 0x1b
4359 #define SP1_CE_ERR_STATUS_HI__ECC_MASK                                                                        0x00000001L
4360 #define SP1_CE_ERR_STATUS_HI__OTHER_MASK                                                                      0x00000002L
4361 #define SP1_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK                                                        0x00000004L
4362 #define SP1_CE_ERR_STATUS_HI__ERR_INFO_MASK                                                                   0x007FFFF8L
4363 #define SP1_CE_ERR_STATUS_HI__CE_CNT_MASK                                                                     0x03800000L
4364 #define SP1_CE_ERR_STATUS_HI__POISON_MASK                                                                     0x04000000L
4365 #define SP1_CE_ERR_STATUS_HI__RESERVED_MASK                                                                   0xF8000000L
4366 
4367 
4368 // addressBlock: xcd0_gc_shsdec
4369 //SX_DEBUG_BUSY
4370 #define SX_DEBUG_BUSY__RESERVED__SHIFT                                                                        0x0
4371 #define SX_DEBUG_BUSY__PCCMD_VALID__SHIFT                                                                     0x1b
4372 #define SX_DEBUG_BUSY__VDATA1_VALID__SHIFT                                                                    0x1c
4373 #define SX_DEBUG_BUSY__VDATA0_VALID__SHIFT                                                                    0x1d
4374 #define SX_DEBUG_BUSY__CMD_BUSYORVAL__SHIFT                                                                   0x1e
4375 #define SX_DEBUG_BUSY__PCDATA_VALID__SHIFT                                                                    0x1f
4376 #define SX_DEBUG_BUSY__RESERVED_MASK                                                                          0x07FFFFFFL
4377 #define SX_DEBUG_BUSY__PCCMD_VALID_MASK                                                                       0x08000000L
4378 #define SX_DEBUG_BUSY__VDATA1_VALID_MASK                                                                      0x10000000L
4379 #define SX_DEBUG_BUSY__VDATA0_VALID_MASK                                                                      0x20000000L
4380 #define SX_DEBUG_BUSY__CMD_BUSYORVAL_MASK                                                                     0x40000000L
4381 #define SX_DEBUG_BUSY__PCDATA_VALID_MASK                                                                      0x80000000L
4382 //SX_DEBUG_1
4383 #define SX_DEBUG_1__RESERVED__SHIFT                                                                           0x0
4384 #define SX_DEBUG_1__DISABLE_REP_FGCG__SHIFT                                                                   0xd
4385 #define SX_DEBUG_1__RESERVED_MASK                                                                             0x00001FFFL
4386 #define SX_DEBUG_1__DISABLE_REP_FGCG_MASK                                                                     0x00002000L
4387 //SPI_PS_MAX_WAVE_ID
4388 #define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT                                                                0x0
4389 #define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID__SHIFT                                                      0x10
4390 #define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID_MASK                                                                  0x00000FFFL
4391 #define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID_MASK                                                        0x03FF0000L
4392 //SPI_START_PHASE
4393 #define SPI_START_PHASE__VGPR_START_PHASE__SHIFT                                                              0x0
4394 #define SPI_START_PHASE__SGPR_START_PHASE__SHIFT                                                              0x2
4395 #define SPI_START_PHASE__WAVE_START_PHASE__SHIFT                                                              0x4
4396 #define SPI_START_PHASE__SPI_TD_GAP__SHIFT                                                                    0x6
4397 #define SPI_START_PHASE__VGPR_START_PHASE_MASK                                                                0x00000003L
4398 #define SPI_START_PHASE__SGPR_START_PHASE_MASK                                                                0x0000000CL
4399 #define SPI_START_PHASE__WAVE_START_PHASE_MASK                                                                0x00000030L
4400 #define SPI_START_PHASE__SPI_TD_GAP_MASK                                                                      0x000003C0L
4401 //SPI_GFX_CNTL
4402 #define SPI_GFX_CNTL__RESET_COUNTS__SHIFT                                                                     0x0
4403 #define SPI_GFX_CNTL__RESET_COUNTS_MASK                                                                       0x00000001L
4404 //SPI_DEBUG_READ
4405 #define SPI_DEBUG_READ__DATA__SHIFT                                                                           0x0
4406 #define SPI_DEBUG_READ__DATA_MASK                                                                             0xFFFFFFFFL
4407 //SPI_DSM_CNTL
4408 #define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA__SHIFT                                                    0x0
4409 #define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE__SHIFT                                                   0x2
4410 #define SPI_DSM_CNTL__SPI_GDS_EXPREQ_MEM_DSM_IRRITATOR_DATA__SHIFT                                            0x3
4411 #define SPI_DSM_CNTL__SPI_GDS_EXPREQ_MEM_ENABLE_SINGLE_WRITE__SHIFT                                           0x5
4412 #define SPI_DSM_CNTL__SPI_WB_GRANT_30_MEM_DSM_IRRITATOR_DATA__SHIFT                                           0x6
4413 #define SPI_DSM_CNTL__SPI_WB_GRANT_30_MEM_ENABLE_SINGLE_WRITE__SHIFT                                          0x8
4414 #define SPI_DSM_CNTL__RESERVED__SHIFT                                                                         0x9
4415 #define SPI_DSM_CNTL__SPI_LIFE_CNT_MEM_DSM_IRRITATOR_DATA__SHIFT                                              0xc
4416 #define SPI_DSM_CNTL__SPI_LIFE_CNT_MEM_ENABLE_SINGLE_WRITE__SHIFT                                             0xe
4417 #define SPI_DSM_CNTL__UNUSED__SHIFT                                                                           0xf
4418 #define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA_MASK                                                      0x00000003L
4419 #define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE_MASK                                                     0x00000004L
4420 #define SPI_DSM_CNTL__SPI_GDS_EXPREQ_MEM_DSM_IRRITATOR_DATA_MASK                                              0x00000018L
4421 #define SPI_DSM_CNTL__SPI_GDS_EXPREQ_MEM_ENABLE_SINGLE_WRITE_MASK                                             0x00000020L
4422 #define SPI_DSM_CNTL__SPI_WB_GRANT_30_MEM_DSM_IRRITATOR_DATA_MASK                                             0x000000C0L
4423 #define SPI_DSM_CNTL__SPI_WB_GRANT_30_MEM_ENABLE_SINGLE_WRITE_MASK                                            0x00000100L
4424 #define SPI_DSM_CNTL__RESERVED_MASK                                                                           0x00000E00L
4425 #define SPI_DSM_CNTL__SPI_LIFE_CNT_MEM_DSM_IRRITATOR_DATA_MASK                                                0x00003000L
4426 #define SPI_DSM_CNTL__SPI_LIFE_CNT_MEM_ENABLE_SINGLE_WRITE_MASK                                               0x00004000L
4427 #define SPI_DSM_CNTL__UNUSED_MASK                                                                             0xFFFF8000L
4428 //SPI_DSM_CNTL2
4429 #define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT__SHIFT                                                  0x0
4430 #define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY__SHIFT                                                  0x2
4431 #define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY__SHIFT                                                         0x4
4432 #define SPI_DSM_CNTL2__SPI_GDS_EXPREQ_MEM_ENABLE_ERROR_INJECT__SHIFT                                          0xa
4433 #define SPI_DSM_CNTL2__SPI_GDS_EXPREQ_MEM_SELECT_INJECT_DELAY__SHIFT                                          0xc
4434 #define SPI_DSM_CNTL2__SPI_WB_GRANT_30_MEM_ENABLE_ERROR_INJECT__SHIFT                                         0xd
4435 #define SPI_DSM_CNTL2__SPI_WB_GRANT_30_MEM_SELECT_INJECT_DELAY__SHIFT                                         0xf
4436 #define SPI_DSM_CNTL2__RESERVED__SHIFT                                                                        0x10
4437 #define SPI_DSM_CNTL2__SPI_LIFE_CNT_MEM_ENABLE_ERROR_INJECT__SHIFT                                            0x13
4438 #define SPI_DSM_CNTL2__SPI_LIFE_CNT_MEM_SELECT_INJECT_DELAY__SHIFT                                            0x15
4439 #define SPI_DSM_CNTL2__UNUSED__SHIFT                                                                          0x16
4440 #define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT_MASK                                                    0x00000003L
4441 #define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY_MASK                                                    0x00000004L
4442 #define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY_MASK                                                           0x000003F0L
4443 #define SPI_DSM_CNTL2__SPI_GDS_EXPREQ_MEM_ENABLE_ERROR_INJECT_MASK                                            0x00000C00L
4444 #define SPI_DSM_CNTL2__SPI_GDS_EXPREQ_MEM_SELECT_INJECT_DELAY_MASK                                            0x00001000L
4445 #define SPI_DSM_CNTL2__SPI_WB_GRANT_30_MEM_ENABLE_ERROR_INJECT_MASK                                           0x00006000L
4446 #define SPI_DSM_CNTL2__SPI_WB_GRANT_30_MEM_SELECT_INJECT_DELAY_MASK                                           0x00008000L
4447 #define SPI_DSM_CNTL2__RESERVED_MASK                                                                          0x00070000L
4448 #define SPI_DSM_CNTL2__SPI_LIFE_CNT_MEM_ENABLE_ERROR_INJECT_MASK                                              0x00180000L
4449 #define SPI_DSM_CNTL2__SPI_LIFE_CNT_MEM_SELECT_INJECT_DELAY_MASK                                              0x00200000L
4450 #define SPI_DSM_CNTL2__UNUSED_MASK                                                                            0xFFC00000L
4451 //SPI_EDC_CNT
4452 #define SPI_EDC_CNT__SPI_SR_MEM_SEC_COUNT__SHIFT                                                              0x0
4453 #define SPI_EDC_CNT__SPI_SR_MEM_DED_COUNT__SHIFT                                                              0x2
4454 #define SPI_EDC_CNT__SPI_GDS_EXPREQ_SEC_COUNT__SHIFT                                                          0x4
4455 #define SPI_EDC_CNT__SPI_GDS_EXPREQ_DED_COUNT__SHIFT                                                          0x6
4456 #define SPI_EDC_CNT__SPI_WB_GRANT_30_SEC_COUNT__SHIFT                                                         0x8
4457 #define SPI_EDC_CNT__SPI_WB_GRANT_30_DED_COUNT__SHIFT                                                         0xa
4458 #define SPI_EDC_CNT__RESERVED__SHIFT                                                                          0xc
4459 #define SPI_EDC_CNT__SPI_LIFE_CNT_SEC_COUNT__SHIFT                                                            0x10
4460 #define SPI_EDC_CNT__SPI_LIFE_CNT_DED_COUNT__SHIFT                                                            0x12
4461 #define SPI_EDC_CNT__UNUSED__SHIFT                                                                            0x14
4462 #define SPI_EDC_CNT__SPI_SR_MEM_SEC_COUNT_MASK                                                                0x00000003L
4463 #define SPI_EDC_CNT__SPI_SR_MEM_DED_COUNT_MASK                                                                0x0000000CL
4464 #define SPI_EDC_CNT__SPI_GDS_EXPREQ_SEC_COUNT_MASK                                                            0x00000030L
4465 #define SPI_EDC_CNT__SPI_GDS_EXPREQ_DED_COUNT_MASK                                                            0x000000C0L
4466 #define SPI_EDC_CNT__SPI_WB_GRANT_30_SEC_COUNT_MASK                                                           0x00000300L
4467 #define SPI_EDC_CNT__SPI_WB_GRANT_30_DED_COUNT_MASK                                                           0x00000C00L
4468 #define SPI_EDC_CNT__RESERVED_MASK                                                                            0x0000F000L
4469 #define SPI_EDC_CNT__SPI_LIFE_CNT_SEC_COUNT_MASK                                                              0x00030000L
4470 #define SPI_EDC_CNT__SPI_LIFE_CNT_DED_COUNT_MASK                                                              0x000C0000L
4471 #define SPI_EDC_CNT__UNUSED_MASK                                                                              0xFFF00000L
4472 //SPI_UE_ERR_STATUS_LO
4473 #define SPI_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT                                                    0x0
4474 #define SPI_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT                                                       0x1
4475 #define SPI_UE_ERR_STATUS_LO__ADDRESS__SHIFT                                                                  0x2
4476 #define SPI_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT                                                                0x18
4477 #define SPI_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK                                                      0x00000001L
4478 #define SPI_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK                                                         0x00000002L
4479 #define SPI_UE_ERR_STATUS_LO__ADDRESS_MASK                                                                    0x00FFFFFCL
4480 #define SPI_UE_ERR_STATUS_LO__MEMORY_ID_MASK                                                                  0xFF000000L
4481 //SPI_UE_ERR_STATUS_HI
4482 #define SPI_UE_ERR_STATUS_HI__ECC__SHIFT                                                                      0x0
4483 #define SPI_UE_ERR_STATUS_HI__PARITY__SHIFT                                                                   0x1
4484 #define SPI_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT                                                      0x2
4485 #define SPI_UE_ERR_STATUS_HI__ERR_INFO__SHIFT                                                                 0x3
4486 #define SPI_UE_ERR_STATUS_HI__UE_CNT__SHIFT                                                                   0x17
4487 #define SPI_UE_ERR_STATUS_HI__FED_CNT__SHIFT                                                                  0x1a
4488 #define SPI_UE_ERR_STATUS_HI__RESERVED__SHIFT                                                                 0x1d
4489 #define SPI_UE_ERR_STATUS_HI__ECC_MASK                                                                        0x00000001L
4490 #define SPI_UE_ERR_STATUS_HI__PARITY_MASK                                                                     0x00000002L
4491 #define SPI_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK                                                        0x00000004L
4492 #define SPI_UE_ERR_STATUS_HI__ERR_INFO_MASK                                                                   0x007FFFF8L
4493 #define SPI_UE_ERR_STATUS_HI__UE_CNT_MASK                                                                     0x03800000L
4494 #define SPI_UE_ERR_STATUS_HI__FED_CNT_MASK                                                                    0x1C000000L
4495 #define SPI_UE_ERR_STATUS_HI__RESERVED_MASK                                                                   0xE0000000L
4496 //SPI_CE_ERR_STATUS_LO
4497 #define SPI_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT                                                    0x0
4498 #define SPI_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT                                                       0x1
4499 #define SPI_CE_ERR_STATUS_LO__ADDRESS__SHIFT                                                                  0x2
4500 #define SPI_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT                                                                0x18
4501 #define SPI_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK                                                      0x00000001L
4502 #define SPI_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK                                                         0x00000002L
4503 #define SPI_CE_ERR_STATUS_LO__ADDRESS_MASK                                                                    0x00FFFFFCL
4504 #define SPI_CE_ERR_STATUS_LO__MEMORY_ID_MASK                                                                  0xFF000000L
4505 //SPI_CE_ERR_STATUS_HI
4506 #define SPI_CE_ERR_STATUS_HI__ECC__SHIFT                                                                      0x0
4507 #define SPI_CE_ERR_STATUS_HI__OTHER__SHIFT                                                                    0x1
4508 #define SPI_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT                                                      0x2
4509 #define SPI_CE_ERR_STATUS_HI__ERR_INFO__SHIFT                                                                 0x3
4510 #define SPI_CE_ERR_STATUS_HI__CE_CNT__SHIFT                                                                   0x17
4511 #define SPI_CE_ERR_STATUS_HI__POISON__SHIFT                                                                   0x1a
4512 #define SPI_CE_ERR_STATUS_HI__RESERVED__SHIFT                                                                 0x1b
4513 #define SPI_CE_ERR_STATUS_HI__ECC_MASK                                                                        0x00000001L
4514 #define SPI_CE_ERR_STATUS_HI__OTHER_MASK                                                                      0x00000002L
4515 #define SPI_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK                                                        0x00000004L
4516 #define SPI_CE_ERR_STATUS_HI__ERR_INFO_MASK                                                                   0x007FFFF8L
4517 #define SPI_CE_ERR_STATUS_HI__CE_CNT_MASK                                                                     0x03800000L
4518 #define SPI_CE_ERR_STATUS_HI__POISON_MASK                                                                     0x04000000L
4519 #define SPI_CE_ERR_STATUS_HI__RESERVED_MASK                                                                   0xF8000000L
4520 //SPI_DEBUG_BUSY
4521 #define SPI_DEBUG_BUSY__HS_BUSY__SHIFT                                                                        0x0
4522 #define SPI_DEBUG_BUSY__GS_BUSY__SHIFT                                                                        0x1
4523 #define SPI_DEBUG_BUSY__VS_BUSY__SHIFT                                                                        0x2
4524 #define SPI_DEBUG_BUSY__PS0_BUSY__SHIFT                                                                       0x3
4525 #define SPI_DEBUG_BUSY__PS1_BUSY__SHIFT                                                                       0x4
4526 #define SPI_DEBUG_BUSY__CSG_BUSY__SHIFT                                                                       0x5
4527 #define SPI_DEBUG_BUSY__CS0_BUSY__SHIFT                                                                       0x6
4528 #define SPI_DEBUG_BUSY__CS1_BUSY__SHIFT                                                                       0x7
4529 #define SPI_DEBUG_BUSY__CS2_BUSY__SHIFT                                                                       0x8
4530 #define SPI_DEBUG_BUSY__CS3_BUSY__SHIFT                                                                       0x9
4531 #define SPI_DEBUG_BUSY__CS4_BUSY__SHIFT                                                                       0xa
4532 #define SPI_DEBUG_BUSY__CS5_BUSY__SHIFT                                                                       0xb
4533 #define SPI_DEBUG_BUSY__CS6_BUSY__SHIFT                                                                       0xc
4534 #define SPI_DEBUG_BUSY__CS7_BUSY__SHIFT                                                                       0xd
4535 #define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY__SHIFT                                                               0xe
4536 #define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY__SHIFT                                                               0xf
4537 #define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY__SHIFT                                                               0x10
4538 #define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY__SHIFT                                                               0x11
4539 #define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY__SHIFT                                                                0x12
4540 #define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY__SHIFT                                                               0x13
4541 #define SPI_DEBUG_BUSY__GRBM_BUSY__SHIFT                                                                      0x14
4542 #define SPI_DEBUG_BUSY__SPIS_BUSY__SHIFT                                                                      0x15
4543 #define SPI_DEBUG_BUSY__HS_BUSY_MASK                                                                          0x00000001L
4544 #define SPI_DEBUG_BUSY__GS_BUSY_MASK                                                                          0x00000002L
4545 #define SPI_DEBUG_BUSY__VS_BUSY_MASK                                                                          0x00000004L
4546 #define SPI_DEBUG_BUSY__PS0_BUSY_MASK                                                                         0x00000008L
4547 #define SPI_DEBUG_BUSY__PS1_BUSY_MASK                                                                         0x00000010L
4548 #define SPI_DEBUG_BUSY__CSG_BUSY_MASK                                                                         0x00000020L
4549 #define SPI_DEBUG_BUSY__CS0_BUSY_MASK                                                                         0x00000040L
4550 #define SPI_DEBUG_BUSY__CS1_BUSY_MASK                                                                         0x00000080L
4551 #define SPI_DEBUG_BUSY__CS2_BUSY_MASK                                                                         0x00000100L
4552 #define SPI_DEBUG_BUSY__CS3_BUSY_MASK                                                                         0x00000200L
4553 #define SPI_DEBUG_BUSY__CS4_BUSY_MASK                                                                         0x00000400L
4554 #define SPI_DEBUG_BUSY__CS5_BUSY_MASK                                                                         0x00000800L
4555 #define SPI_DEBUG_BUSY__CS6_BUSY_MASK                                                                         0x00001000L
4556 #define SPI_DEBUG_BUSY__CS7_BUSY_MASK                                                                         0x00002000L
4557 #define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY_MASK                                                                 0x00004000L
4558 #define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY_MASK                                                                 0x00008000L
4559 #define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY_MASK                                                                 0x00010000L
4560 #define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY_MASK                                                                 0x00020000L
4561 #define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY_MASK                                                                  0x00040000L
4562 #define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY_MASK                                                                 0x00080000L
4563 #define SPI_DEBUG_BUSY__GRBM_BUSY_MASK                                                                        0x00100000L
4564 #define SPI_DEBUG_BUSY__SPIS_BUSY_MASK                                                                        0x00200000L
4565 //SPI_CONFIG_PS_CU_EN
4566 #define SPI_CONFIG_PS_CU_EN__ENABLE__SHIFT                                                                    0x0
4567 #define SPI_CONFIG_PS_CU_EN__PKR0_CU_EN__SHIFT                                                                0x1
4568 #define SPI_CONFIG_PS_CU_EN__PKR1_CU_EN__SHIFT                                                                0x10
4569 #define SPI_CONFIG_PS_CU_EN__ENABLE_MASK                                                                      0x00000001L
4570 #define SPI_CONFIG_PS_CU_EN__PKR0_CU_EN_MASK                                                                  0x0000FFFEL
4571 #define SPI_CONFIG_PS_CU_EN__PKR1_CU_EN_MASK                                                                  0xFFFF0000L
4572 //SPI_WF_LIFETIME_CNTL
4573 #define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD__SHIFT                                                            0x0
4574 #define SPI_WF_LIFETIME_CNTL__EN__SHIFT                                                                       0x4
4575 #define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD_MASK                                                              0x0000000FL
4576 #define SPI_WF_LIFETIME_CNTL__EN_MASK                                                                         0x00000010L
4577 //SPI_WF_LIFETIME_LIMIT_0
4578 #define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT__SHIFT                                                               0x0
4579 #define SPI_WF_LIFETIME_LIMIT_0__EN_WARN__SHIFT                                                               0x1f
4580 #define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT_MASK                                                                 0x7FFFFFFFL
4581 #define SPI_WF_LIFETIME_LIMIT_0__EN_WARN_MASK                                                                 0x80000000L
4582 //SPI_WF_LIFETIME_LIMIT_1
4583 #define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT__SHIFT                                                               0x0
4584 #define SPI_WF_LIFETIME_LIMIT_1__EN_WARN__SHIFT                                                               0x1f
4585 #define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT_MASK                                                                 0x7FFFFFFFL
4586 #define SPI_WF_LIFETIME_LIMIT_1__EN_WARN_MASK                                                                 0x80000000L
4587 //SPI_WF_LIFETIME_LIMIT_2
4588 #define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT__SHIFT                                                               0x0
4589 #define SPI_WF_LIFETIME_LIMIT_2__EN_WARN__SHIFT                                                               0x1f
4590 #define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT_MASK                                                                 0x7FFFFFFFL
4591 #define SPI_WF_LIFETIME_LIMIT_2__EN_WARN_MASK                                                                 0x80000000L
4592 //SPI_WF_LIFETIME_LIMIT_3
4593 #define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT__SHIFT                                                               0x0
4594 #define SPI_WF_LIFETIME_LIMIT_3__EN_WARN__SHIFT                                                               0x1f
4595 #define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT_MASK                                                                 0x7FFFFFFFL
4596 #define SPI_WF_LIFETIME_LIMIT_3__EN_WARN_MASK                                                                 0x80000000L
4597 //SPI_WF_LIFETIME_LIMIT_4
4598 #define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT__SHIFT                                                               0x0
4599 #define SPI_WF_LIFETIME_LIMIT_4__EN_WARN__SHIFT                                                               0x1f
4600 #define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT_MASK                                                                 0x7FFFFFFFL
4601 #define SPI_WF_LIFETIME_LIMIT_4__EN_WARN_MASK                                                                 0x80000000L
4602 //SPI_WF_LIFETIME_LIMIT_5
4603 #define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT__SHIFT                                                               0x0
4604 #define SPI_WF_LIFETIME_LIMIT_5__EN_WARN__SHIFT                                                               0x1f
4605 #define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT_MASK                                                                 0x7FFFFFFFL
4606 #define SPI_WF_LIFETIME_LIMIT_5__EN_WARN_MASK                                                                 0x80000000L
4607 //SPI_WF_LIFETIME_LIMIT_6
4608 #define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT__SHIFT                                                               0x0
4609 #define SPI_WF_LIFETIME_LIMIT_6__EN_WARN__SHIFT                                                               0x1f
4610 #define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT_MASK                                                                 0x7FFFFFFFL
4611 #define SPI_WF_LIFETIME_LIMIT_6__EN_WARN_MASK                                                                 0x80000000L
4612 //SPI_WF_LIFETIME_LIMIT_7
4613 #define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT__SHIFT                                                               0x0
4614 #define SPI_WF_LIFETIME_LIMIT_7__EN_WARN__SHIFT                                                               0x1f
4615 #define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT_MASK                                                                 0x7FFFFFFFL
4616 #define SPI_WF_LIFETIME_LIMIT_7__EN_WARN_MASK                                                                 0x80000000L
4617 //SPI_WF_LIFETIME_LIMIT_8
4618 #define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT__SHIFT                                                               0x0
4619 #define SPI_WF_LIFETIME_LIMIT_8__EN_WARN__SHIFT                                                               0x1f
4620 #define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT_MASK                                                                 0x7FFFFFFFL
4621 #define SPI_WF_LIFETIME_LIMIT_8__EN_WARN_MASK                                                                 0x80000000L
4622 //SPI_WF_LIFETIME_LIMIT_9
4623 #define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT__SHIFT                                                               0x0
4624 #define SPI_WF_LIFETIME_LIMIT_9__EN_WARN__SHIFT                                                               0x1f
4625 #define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT_MASK                                                                 0x7FFFFFFFL
4626 #define SPI_WF_LIFETIME_LIMIT_9__EN_WARN_MASK                                                                 0x80000000L
4627 //SPI_WF_LIFETIME_STATUS_0
4628 #define SPI_WF_LIFETIME_STATUS_0__MAX_CNT__SHIFT                                                              0x0
4629 #define SPI_WF_LIFETIME_STATUS_0__INT_SENT__SHIFT                                                             0x1f
4630 #define SPI_WF_LIFETIME_STATUS_0__MAX_CNT_MASK                                                                0x7FFFFFFFL
4631 #define SPI_WF_LIFETIME_STATUS_0__INT_SENT_MASK                                                               0x80000000L
4632 //SPI_WF_LIFETIME_STATUS_1
4633 #define SPI_WF_LIFETIME_STATUS_1__MAX_CNT__SHIFT                                                              0x0
4634 #define SPI_WF_LIFETIME_STATUS_1__INT_SENT__SHIFT                                                             0x1f
4635 #define SPI_WF_LIFETIME_STATUS_1__MAX_CNT_MASK                                                                0x7FFFFFFFL
4636 #define SPI_WF_LIFETIME_STATUS_1__INT_SENT_MASK                                                               0x80000000L
4637 //SPI_WF_LIFETIME_STATUS_2
4638 #define SPI_WF_LIFETIME_STATUS_2__MAX_CNT__SHIFT                                                              0x0
4639 #define SPI_WF_LIFETIME_STATUS_2__INT_SENT__SHIFT                                                             0x1f
4640 #define SPI_WF_LIFETIME_STATUS_2__MAX_CNT_MASK                                                                0x7FFFFFFFL
4641 #define SPI_WF_LIFETIME_STATUS_2__INT_SENT_MASK                                                               0x80000000L
4642 //SPI_WF_LIFETIME_STATUS_3
4643 #define SPI_WF_LIFETIME_STATUS_3__MAX_CNT__SHIFT                                                              0x0
4644 #define SPI_WF_LIFETIME_STATUS_3__INT_SENT__SHIFT                                                             0x1f
4645 #define SPI_WF_LIFETIME_STATUS_3__MAX_CNT_MASK                                                                0x7FFFFFFFL
4646 #define SPI_WF_LIFETIME_STATUS_3__INT_SENT_MASK                                                               0x80000000L
4647 //SPI_WF_LIFETIME_STATUS_4
4648 #define SPI_WF_LIFETIME_STATUS_4__MAX_CNT__SHIFT                                                              0x0
4649 #define SPI_WF_LIFETIME_STATUS_4__INT_SENT__SHIFT                                                             0x1f
4650 #define SPI_WF_LIFETIME_STATUS_4__MAX_CNT_MASK                                                                0x7FFFFFFFL
4651 #define SPI_WF_LIFETIME_STATUS_4__INT_SENT_MASK                                                               0x80000000L
4652 //SPI_WF_LIFETIME_STATUS_5
4653 #define SPI_WF_LIFETIME_STATUS_5__MAX_CNT__SHIFT                                                              0x0
4654 #define SPI_WF_LIFETIME_STATUS_5__INT_SENT__SHIFT                                                             0x1f
4655 #define SPI_WF_LIFETIME_STATUS_5__MAX_CNT_MASK                                                                0x7FFFFFFFL
4656 #define SPI_WF_LIFETIME_STATUS_5__INT_SENT_MASK                                                               0x80000000L
4657 //SPI_WF_LIFETIME_STATUS_6
4658 #define SPI_WF_LIFETIME_STATUS_6__MAX_CNT__SHIFT                                                              0x0
4659 #define SPI_WF_LIFETIME_STATUS_6__INT_SENT__SHIFT                                                             0x1f
4660 #define SPI_WF_LIFETIME_STATUS_6__MAX_CNT_MASK                                                                0x7FFFFFFFL
4661 #define SPI_WF_LIFETIME_STATUS_6__INT_SENT_MASK                                                               0x80000000L
4662 //SPI_WF_LIFETIME_STATUS_7
4663 #define SPI_WF_LIFETIME_STATUS_7__MAX_CNT__SHIFT                                                              0x0
4664 #define SPI_WF_LIFETIME_STATUS_7__INT_SENT__SHIFT                                                             0x1f
4665 #define SPI_WF_LIFETIME_STATUS_7__MAX_CNT_MASK                                                                0x7FFFFFFFL
4666 #define SPI_WF_LIFETIME_STATUS_7__INT_SENT_MASK                                                               0x80000000L
4667 //SPI_WF_LIFETIME_STATUS_8
4668 #define SPI_WF_LIFETIME_STATUS_8__MAX_CNT__SHIFT                                                              0x0
4669 #define SPI_WF_LIFETIME_STATUS_8__INT_SENT__SHIFT                                                             0x1f
4670 #define SPI_WF_LIFETIME_STATUS_8__MAX_CNT_MASK                                                                0x7FFFFFFFL
4671 #define SPI_WF_LIFETIME_STATUS_8__INT_SENT_MASK                                                               0x80000000L
4672 //SPI_WF_LIFETIME_STATUS_9
4673 #define SPI_WF_LIFETIME_STATUS_9__MAX_CNT__SHIFT                                                              0x0
4674 #define SPI_WF_LIFETIME_STATUS_9__INT_SENT__SHIFT                                                             0x1f
4675 #define SPI_WF_LIFETIME_STATUS_9__MAX_CNT_MASK                                                                0x7FFFFFFFL
4676 #define SPI_WF_LIFETIME_STATUS_9__INT_SENT_MASK                                                               0x80000000L
4677 //SPI_WF_LIFETIME_STATUS_10
4678 #define SPI_WF_LIFETIME_STATUS_10__MAX_CNT__SHIFT                                                             0x0
4679 #define SPI_WF_LIFETIME_STATUS_10__INT_SENT__SHIFT                                                            0x1f
4680 #define SPI_WF_LIFETIME_STATUS_10__MAX_CNT_MASK                                                               0x7FFFFFFFL
4681 #define SPI_WF_LIFETIME_STATUS_10__INT_SENT_MASK                                                              0x80000000L
4682 //SPI_WF_LIFETIME_STATUS_11
4683 #define SPI_WF_LIFETIME_STATUS_11__MAX_CNT__SHIFT                                                             0x0
4684 #define SPI_WF_LIFETIME_STATUS_11__INT_SENT__SHIFT                                                            0x1f
4685 #define SPI_WF_LIFETIME_STATUS_11__MAX_CNT_MASK                                                               0x7FFFFFFFL
4686 #define SPI_WF_LIFETIME_STATUS_11__INT_SENT_MASK                                                              0x80000000L
4687 //SPI_WF_LIFETIME_STATUS_12
4688 #define SPI_WF_LIFETIME_STATUS_12__MAX_CNT__SHIFT                                                             0x0
4689 #define SPI_WF_LIFETIME_STATUS_12__INT_SENT__SHIFT                                                            0x1f
4690 #define SPI_WF_LIFETIME_STATUS_12__MAX_CNT_MASK                                                               0x7FFFFFFFL
4691 #define SPI_WF_LIFETIME_STATUS_12__INT_SENT_MASK                                                              0x80000000L
4692 //SPI_WF_LIFETIME_STATUS_13
4693 #define SPI_WF_LIFETIME_STATUS_13__MAX_CNT__SHIFT                                                             0x0
4694 #define SPI_WF_LIFETIME_STATUS_13__INT_SENT__SHIFT                                                            0x1f
4695 #define SPI_WF_LIFETIME_STATUS_13__MAX_CNT_MASK                                                               0x7FFFFFFFL
4696 #define SPI_WF_LIFETIME_STATUS_13__INT_SENT_MASK                                                              0x80000000L
4697 //SPI_WF_LIFETIME_STATUS_14
4698 #define SPI_WF_LIFETIME_STATUS_14__MAX_CNT__SHIFT                                                             0x0
4699 #define SPI_WF_LIFETIME_STATUS_14__INT_SENT__SHIFT                                                            0x1f
4700 #define SPI_WF_LIFETIME_STATUS_14__MAX_CNT_MASK                                                               0x7FFFFFFFL
4701 #define SPI_WF_LIFETIME_STATUS_14__INT_SENT_MASK                                                              0x80000000L
4702 //SPI_WF_LIFETIME_STATUS_15
4703 #define SPI_WF_LIFETIME_STATUS_15__MAX_CNT__SHIFT                                                             0x0
4704 #define SPI_WF_LIFETIME_STATUS_15__INT_SENT__SHIFT                                                            0x1f
4705 #define SPI_WF_LIFETIME_STATUS_15__MAX_CNT_MASK                                                               0x7FFFFFFFL
4706 #define SPI_WF_LIFETIME_STATUS_15__INT_SENT_MASK                                                              0x80000000L
4707 //SPI_WF_LIFETIME_STATUS_16
4708 #define SPI_WF_LIFETIME_STATUS_16__MAX_CNT__SHIFT                                                             0x0
4709 #define SPI_WF_LIFETIME_STATUS_16__INT_SENT__SHIFT                                                            0x1f
4710 #define SPI_WF_LIFETIME_STATUS_16__MAX_CNT_MASK                                                               0x7FFFFFFFL
4711 #define SPI_WF_LIFETIME_STATUS_16__INT_SENT_MASK                                                              0x80000000L
4712 //SPI_WF_LIFETIME_STATUS_17
4713 #define SPI_WF_LIFETIME_STATUS_17__MAX_CNT__SHIFT                                                             0x0
4714 #define SPI_WF_LIFETIME_STATUS_17__INT_SENT__SHIFT                                                            0x1f
4715 #define SPI_WF_LIFETIME_STATUS_17__MAX_CNT_MASK                                                               0x7FFFFFFFL
4716 #define SPI_WF_LIFETIME_STATUS_17__INT_SENT_MASK                                                              0x80000000L
4717 //SPI_WF_LIFETIME_STATUS_18
4718 #define SPI_WF_LIFETIME_STATUS_18__MAX_CNT__SHIFT                                                             0x0
4719 #define SPI_WF_LIFETIME_STATUS_18__INT_SENT__SHIFT                                                            0x1f
4720 #define SPI_WF_LIFETIME_STATUS_18__MAX_CNT_MASK                                                               0x7FFFFFFFL
4721 #define SPI_WF_LIFETIME_STATUS_18__INT_SENT_MASK                                                              0x80000000L
4722 //SPI_WF_LIFETIME_STATUS_19
4723 #define SPI_WF_LIFETIME_STATUS_19__MAX_CNT__SHIFT                                                             0x0
4724 #define SPI_WF_LIFETIME_STATUS_19__INT_SENT__SHIFT                                                            0x1f
4725 #define SPI_WF_LIFETIME_STATUS_19__MAX_CNT_MASK                                                               0x7FFFFFFFL
4726 #define SPI_WF_LIFETIME_STATUS_19__INT_SENT_MASK                                                              0x80000000L
4727 //SPI_WF_LIFETIME_STATUS_20
4728 #define SPI_WF_LIFETIME_STATUS_20__MAX_CNT__SHIFT                                                             0x0
4729 #define SPI_WF_LIFETIME_STATUS_20__INT_SENT__SHIFT                                                            0x1f
4730 #define SPI_WF_LIFETIME_STATUS_20__MAX_CNT_MASK                                                               0x7FFFFFFFL
4731 #define SPI_WF_LIFETIME_STATUS_20__INT_SENT_MASK                                                              0x80000000L
4732 //SPI_WF_LIFETIME_DEBUG
4733 #define SPI_WF_LIFETIME_DEBUG__START_VALUE__SHIFT                                                             0x0
4734 #define SPI_WF_LIFETIME_DEBUG__OVERRIDE_EN__SHIFT                                                             0x1f
4735 #define SPI_WF_LIFETIME_DEBUG__START_VALUE_MASK                                                               0x7FFFFFFFL
4736 #define SPI_WF_LIFETIME_DEBUG__OVERRIDE_EN_MASK                                                               0x80000000L
4737 //SPI_LB_CTR_CTRL
4738 #define SPI_LB_CTR_CTRL__LOAD__SHIFT                                                                          0x0
4739 #define SPI_LB_CTR_CTRL__WAVES_SELECT__SHIFT                                                                  0x1
4740 #define SPI_LB_CTR_CTRL__CLEAR_ON_READ__SHIFT                                                                 0x3
4741 #define SPI_LB_CTR_CTRL__RESET_COUNTS__SHIFT                                                                  0x4
4742 #define SPI_LB_CTR_CTRL__LOAD_MASK                                                                            0x00000001L
4743 #define SPI_LB_CTR_CTRL__WAVES_SELECT_MASK                                                                    0x00000006L
4744 #define SPI_LB_CTR_CTRL__CLEAR_ON_READ_MASK                                                                   0x00000008L
4745 #define SPI_LB_CTR_CTRL__RESET_COUNTS_MASK                                                                    0x00000010L
4746 //SPI_LB_CU_MASK
4747 #define SPI_LB_CU_MASK__CU_MASK__SHIFT                                                                        0x0
4748 #define SPI_LB_CU_MASK__CU_MASK_MASK                                                                          0xFFFFL
4749 //SPI_LB_DATA_REG
4750 #define SPI_LB_DATA_REG__CNT_DATA__SHIFT                                                                      0x0
4751 #define SPI_LB_DATA_REG__CNT_DATA_MASK                                                                        0xFFFFFFFFL
4752 //SPI_PG_ENABLE_STATIC_CU_MASK
4753 #define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK__SHIFT                                                          0x0
4754 #define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK_MASK                                                            0xFFFFL
4755 //SPI_GDS_CREDITS
4756 #define SPI_GDS_CREDITS__DS_DATA_CREDITS__SHIFT                                                               0x0
4757 #define SPI_GDS_CREDITS__DS_CMD_CREDITS__SHIFT                                                                0x8
4758 #define SPI_GDS_CREDITS__UNUSED__SHIFT                                                                        0x10
4759 #define SPI_GDS_CREDITS__DS_DATA_CREDITS_MASK                                                                 0x000000FFL
4760 #define SPI_GDS_CREDITS__DS_CMD_CREDITS_MASK                                                                  0x0000FF00L
4761 #define SPI_GDS_CREDITS__UNUSED_MASK                                                                          0xFFFF0000L
4762 //SPI_SX_EXPORT_BUFFER_SIZES
4763 #define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE__SHIFT                                                  0x0
4764 #define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE__SHIFT                                               0x10
4765 #define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE_MASK                                                    0x0000FFFFL
4766 #define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE_MASK                                                 0xFFFF0000L
4767 //SPI_SX_SCOREBOARD_BUFFER_SIZES
4768 #define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE__SHIFT                                          0x0
4769 #define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE__SHIFT                                       0x10
4770 #define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE_MASK                                            0x0000FFFFL
4771 #define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE_MASK                                         0xFFFF0000L
4772 //SPI_CSQ_WF_ACTIVE_STATUS
4773 #define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE__SHIFT                                                               0x0
4774 #define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE_MASK                                                                 0xFFFFFFFFL
4775 //SPI_CSQ_WF_ACTIVE_COUNT_0
4776 #define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT__SHIFT                                                               0x0
4777 #define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS__SHIFT                                                              0x10
4778 #define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK                                                                 0x000001FFL
4779 #define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS_MASK                                                                0x01FF0000L
4780 //SPI_CSQ_WF_ACTIVE_COUNT_1
4781 #define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT__SHIFT                                                               0x0
4782 #define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS__SHIFT                                                              0x10
4783 #define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK                                                                 0x000001FFL
4784 #define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS_MASK                                                                0x01FF0000L
4785 //SPI_CSQ_WF_ACTIVE_COUNT_2
4786 #define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT__SHIFT                                                               0x0
4787 #define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS__SHIFT                                                              0x10
4788 #define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT_MASK                                                                 0x000001FFL
4789 #define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS_MASK                                                                0x01FF0000L
4790 //SPI_CSQ_WF_ACTIVE_COUNT_3
4791 #define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT__SHIFT                                                               0x0
4792 #define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS__SHIFT                                                              0x10
4793 #define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT_MASK                                                                 0x000001FFL
4794 #define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS_MASK                                                                0x01FF0000L
4795 //SPI_CSQ_WF_ACTIVE_COUNT_4
4796 #define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT__SHIFT                                                               0x0
4797 #define SPI_CSQ_WF_ACTIVE_COUNT_4__EVENTS__SHIFT                                                              0x10
4798 #define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT_MASK                                                                 0x000001FFL
4799 #define SPI_CSQ_WF_ACTIVE_COUNT_4__EVENTS_MASK                                                                0x01FF0000L
4800 //SPI_CSQ_WF_ACTIVE_COUNT_5
4801 #define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT__SHIFT                                                               0x0
4802 #define SPI_CSQ_WF_ACTIVE_COUNT_5__EVENTS__SHIFT                                                              0x10
4803 #define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT_MASK                                                                 0x000001FFL
4804 #define SPI_CSQ_WF_ACTIVE_COUNT_5__EVENTS_MASK                                                                0x01FF0000L
4805 //SPI_CSQ_WF_ACTIVE_COUNT_6
4806 #define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT__SHIFT                                                               0x0
4807 #define SPI_CSQ_WF_ACTIVE_COUNT_6__EVENTS__SHIFT                                                              0x10
4808 #define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT_MASK                                                                 0x000001FFL
4809 #define SPI_CSQ_WF_ACTIVE_COUNT_6__EVENTS_MASK                                                                0x01FF0000L
4810 //SPI_CSQ_WF_ACTIVE_COUNT_7
4811 #define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT__SHIFT                                                               0x0
4812 #define SPI_CSQ_WF_ACTIVE_COUNT_7__EVENTS__SHIFT                                                              0x10
4813 #define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT_MASK                                                                 0x000001FFL
4814 #define SPI_CSQ_WF_ACTIVE_COUNT_7__EVENTS_MASK                                                                0x01FF0000L
4815 //SPI_LB_DATA_WAVES
4816 #define SPI_LB_DATA_WAVES__COUNT0__SHIFT                                                                      0x0
4817 #define SPI_LB_DATA_WAVES__COUNT1__SHIFT                                                                      0x10
4818 #define SPI_LB_DATA_WAVES__COUNT0_MASK                                                                        0x0000FFFFL
4819 #define SPI_LB_DATA_WAVES__COUNT1_MASK                                                                        0xFFFF0000L
4820 //SPI_LB_DATA_PERCU_WAVE_HSGS
4821 #define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_HS__SHIFT                                                        0x0
4822 #define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_GS__SHIFT                                                        0x10
4823 #define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_HS_MASK                                                          0x0000FFFFL
4824 #define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_GS_MASK                                                          0xFFFF0000L
4825 //SPI_LB_DATA_PERCU_WAVE_VSPS
4826 #define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_VS__SHIFT                                                        0x0
4827 #define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_PS__SHIFT                                                        0x10
4828 #define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_VS_MASK                                                          0x0000FFFFL
4829 #define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_PS_MASK                                                          0xFFFF0000L
4830 //SPI_LB_DATA_PERCU_WAVE_CS
4831 #define SPI_LB_DATA_PERCU_WAVE_CS__ACTIVE__SHIFT                                                              0x0
4832 #define SPI_LB_DATA_PERCU_WAVE_CS__ACTIVE_MASK                                                                0xFFFFL
4833 //SPIS_DEBUG_READ
4834 #define SPIS_DEBUG_READ__DATA__SHIFT                                                                          0x0
4835 #define SPIS_DEBUG_READ__DATA_MASK                                                                            0xFFFFFFFFL
4836 //BCI_DEBUG_READ
4837 #define BCI_DEBUG_READ__DATA__SHIFT                                                                           0x0
4838 #define BCI_DEBUG_READ__DATA_MASK                                                                             0xFFFFFFL
4839 //SPI_P0_TRAP_SCREEN_PSBA_LO
4840 #define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT                                                           0x0
4841 #define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK                                                             0xFFFFFFFFL
4842 //SPI_P0_TRAP_SCREEN_PSBA_HI
4843 #define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT                                                           0x0
4844 #define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK                                                             0xFFL
4845 //SPI_P0_TRAP_SCREEN_PSMA_LO
4846 #define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT                                                           0x0
4847 #define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK                                                             0xFFFFFFFFL
4848 //SPI_P0_TRAP_SCREEN_PSMA_HI
4849 #define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT                                                           0x0
4850 #define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK                                                             0xFFL
4851 //SPI_P0_TRAP_SCREEN_GPR_MIN
4852 #define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT                                                           0x0
4853 #define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT                                                           0x6
4854 #define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK                                                             0x003FL
4855 #define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK                                                             0x03C0L
4856 //SPI_P1_TRAP_SCREEN_PSBA_LO
4857 #define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT                                                           0x0
4858 #define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK                                                             0xFFFFFFFFL
4859 //SPI_P1_TRAP_SCREEN_PSBA_HI
4860 #define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT                                                           0x0
4861 #define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK                                                             0xFFL
4862 //SPI_P1_TRAP_SCREEN_PSMA_LO
4863 #define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT                                                           0x0
4864 #define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK                                                             0xFFFFFFFFL
4865 //SPI_P1_TRAP_SCREEN_PSMA_HI
4866 #define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT                                                           0x0
4867 #define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK                                                             0xFFL
4868 //SPI_P1_TRAP_SCREEN_GPR_MIN
4869 #define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT                                                           0x0
4870 #define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT                                                           0x6
4871 #define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK                                                             0x003FL
4872 #define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK                                                             0x03C0L
4873 
4874 
4875 // addressBlock: xcd0_gc_tpdec
4876 //TD_CNTL
4877 #define TD_CNTL__SYNC_PHASE_SH__SHIFT                                                                         0x0
4878 #define TD_CNTL__TD_IN_CAC_CHICKENBITS__SHIFT                                                                 0x2
4879 #define TD_CNTL__TD_OUT_CAC_CHICKENBITS__SHIFT                                                                0x6
4880 #define TD_CNTL__EXTEND_LDS_STALL__SHIFT                                                                      0x9
4881 #define TD_CNTL__LDS_STALL_PHASE_ADJUST__SHIFT                                                                0xb
4882 #define TD_CNTL__DISABLE_POWER_THROTTLE__SHIFT                                                                0x14
4883 #define TD_CNTL__ENABLE_ROUND_TO_ZERO__SHIFT                                                                  0x15
4884 #define TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT__SHIFT                                                            0x17
4885 #define TD_CNTL__SRAM_FGCG_TD_KCLARR_LG__SHIFT                                                                0x1b
4886 #define TD_CNTL__RFGCG_CHICKEN__SHIFT                                                                         0x1c
4887 #define TD_CNTL__SYNC_PHASE_SH_MASK                                                                           0x00000003L
4888 #define TD_CNTL__TD_IN_CAC_CHICKENBITS_MASK                                                                   0x0000000CL
4889 #define TD_CNTL__TD_OUT_CAC_CHICKENBITS_MASK                                                                  0x000000C0L
4890 #define TD_CNTL__EXTEND_LDS_STALL_MASK                                                                        0x00000600L
4891 #define TD_CNTL__LDS_STALL_PHASE_ADJUST_MASK                                                                  0x00001800L
4892 #define TD_CNTL__DISABLE_POWER_THROTTLE_MASK                                                                  0x00100000L
4893 #define TD_CNTL__ENABLE_ROUND_TO_ZERO_MASK                                                                    0x00200000L
4894 #define TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT_MASK                                                              0x00800000L
4895 #define TD_CNTL__SRAM_FGCG_TD_KCLARR_LG_MASK                                                                  0x08000000L
4896 #define TD_CNTL__RFGCG_CHICKEN_MASK                                                                           0x70000000L
4897 //TD_STATUS
4898 #define TD_STATUS__BUSY__SHIFT                                                                                0x1f
4899 #define TD_STATUS__BUSY_MASK                                                                                  0x80000000L
4900 //TD_POWER_CNTL
4901 #define TD_POWER_CNTL__MGCG_OUTPUTSTAGE__SHIFT                                                                0x1
4902 #define TD_POWER_CNTL__MID0_THREAD_DATA__SHIFT                                                                0x2
4903 #define TD_POWER_CNTL__MID2_ACCUM_DATA__SHIFT                                                                 0x3
4904 #define TD_POWER_CNTL__MGCG_OUTPUTSTAGE_MASK                                                                  0x00000002L
4905 #define TD_POWER_CNTL__MID0_THREAD_DATA_MASK                                                                  0x00000004L
4906 #define TD_POWER_CNTL__MID2_ACCUM_DATA_MASK                                                                   0x00000008L
4907 //TD_UE_EDC_LO
4908 #define TD_UE_EDC_LO__STATUS_VALID_FLAG__SHIFT                                                                0x0
4909 #define TD_UE_EDC_LO__ADDRESS_INFO_VALID_FLAG__SHIFT                                                          0x1
4910 #define TD_UE_EDC_LO__ADDRESS__SHIFT                                                                          0x2
4911 #define TD_UE_EDC_LO__MEM_ID__SHIFT                                                                           0x18
4912 #define TD_UE_EDC_LO__STATUS_VALID_FLAG_MASK                                                                  0x00000001L
4913 #define TD_UE_EDC_LO__ADDRESS_INFO_VALID_FLAG_MASK                                                            0x00000002L
4914 #define TD_UE_EDC_LO__ADDRESS_MASK                                                                            0x00FFFFFCL
4915 #define TD_UE_EDC_LO__MEM_ID_MASK                                                                             0xFF000000L
4916 //TD_UE_EDC_HI
4917 #define TD_UE_EDC_HI__ECC__SHIFT                                                                              0x0
4918 #define TD_UE_EDC_HI__PARITY__SHIFT                                                                           0x1
4919 #define TD_UE_EDC_HI__ERR_INFO_VALID_FLAG__SHIFT                                                              0x2
4920 #define TD_UE_EDC_HI__ERR_INFO__SHIFT                                                                         0x3
4921 #define TD_UE_EDC_HI__UE_CNT__SHIFT                                                                           0x17
4922 #define TD_UE_EDC_HI__FED_CNT__SHIFT                                                                          0x1a
4923 #define TD_UE_EDC_HI__ECC_MASK                                                                                0x00000001L
4924 #define TD_UE_EDC_HI__PARITY_MASK                                                                             0x00000002L
4925 #define TD_UE_EDC_HI__ERR_INFO_VALID_FLAG_MASK                                                                0x00000004L
4926 #define TD_UE_EDC_HI__ERR_INFO_MASK                                                                           0x007FFFF8L
4927 #define TD_UE_EDC_HI__UE_CNT_MASK                                                                             0x03800000L
4928 #define TD_UE_EDC_HI__FED_CNT_MASK                                                                            0x1C000000L
4929 //TD_CE_EDC_LO
4930 #define TD_CE_EDC_LO__STATUS_VALID_FLAG__SHIFT                                                                0x0
4931 #define TD_CE_EDC_LO__ADDRESS_INFO_VALID_FLAG__SHIFT                                                          0x1
4932 #define TD_CE_EDC_LO__ADDRESS__SHIFT                                                                          0x2
4933 #define TD_CE_EDC_LO__MEM_ID__SHIFT                                                                           0x18
4934 #define TD_CE_EDC_LO__STATUS_VALID_FLAG_MASK                                                                  0x00000001L
4935 #define TD_CE_EDC_LO__ADDRESS_INFO_VALID_FLAG_MASK                                                            0x00000002L
4936 #define TD_CE_EDC_LO__ADDRESS_MASK                                                                            0x00FFFFFCL
4937 #define TD_CE_EDC_LO__MEM_ID_MASK                                                                             0xFF000000L
4938 //TD_CE_EDC_HI
4939 #define TD_CE_EDC_HI__ECC__SHIFT                                                                              0x0
4940 #define TD_CE_EDC_HI__ERR_INFO_VALID_FLAG__SHIFT                                                              0x2
4941 #define TD_CE_EDC_HI__ERR_INFO__SHIFT                                                                         0x3
4942 #define TD_CE_EDC_HI__CE_CNT__SHIFT                                                                           0x17
4943 #define TD_CE_EDC_HI__POISON__SHIFT                                                                           0x1a
4944 #define TD_CE_EDC_HI__ECC_MASK                                                                                0x00000001L
4945 #define TD_CE_EDC_HI__ERR_INFO_VALID_FLAG_MASK                                                                0x00000004L
4946 #define TD_CE_EDC_HI__ERR_INFO_MASK                                                                           0x007FFFF8L
4947 #define TD_CE_EDC_HI__CE_CNT_MASK                                                                             0x03800000L
4948 #define TD_CE_EDC_HI__POISON_MASK                                                                             0x04000000L
4949 //TD_DSM_CNTL
4950 #define TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA__SHIFT                                                  0x0
4951 #define TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE__SHIFT                                                 0x2
4952 #define TD_DSM_CNTL__TD_SS_FIFO_HI_DSM_IRRITATOR_DATA__SHIFT                                                  0x3
4953 #define TD_DSM_CNTL__TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE__SHIFT                                                 0x5
4954 #define TD_DSM_CNTL__TD_CS_FIFO_DSM_IRRITATOR_DATA__SHIFT                                                     0x6
4955 #define TD_DSM_CNTL__TD_CS_FIFO_ENABLE_SINGLE_WRITE__SHIFT                                                    0x8
4956 #define TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA_MASK                                                    0x00000003L
4957 #define TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE_MASK                                                   0x00000004L
4958 #define TD_DSM_CNTL__TD_SS_FIFO_HI_DSM_IRRITATOR_DATA_MASK                                                    0x00000018L
4959 #define TD_DSM_CNTL__TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE_MASK                                                   0x00000020L
4960 #define TD_DSM_CNTL__TD_CS_FIFO_DSM_IRRITATOR_DATA_MASK                                                       0x000000C0L
4961 #define TD_DSM_CNTL__TD_CS_FIFO_ENABLE_SINGLE_WRITE_MASK                                                      0x00000100L
4962 //TD_DSM_CNTL2
4963 #define TD_DSM_CNTL2__TD_SS_FIFO_LO_ENABLE_ERROR_INJECT__SHIFT                                                0x0
4964 #define TD_DSM_CNTL2__TD_SS_FIFO_LO_SELECT_INJECT_DELAY__SHIFT                                                0x2
4965 #define TD_DSM_CNTL2__TD_SS_FIFO_HI_ENABLE_ERROR_INJECT__SHIFT                                                0x3
4966 #define TD_DSM_CNTL2__TD_SS_FIFO_HI_SELECT_INJECT_DELAY__SHIFT                                                0x5
4967 #define TD_DSM_CNTL2__TD_CS_FIFO_ENABLE_ERROR_INJECT__SHIFT                                                   0x6
4968 #define TD_DSM_CNTL2__TD_CS_FIFO_SELECT_INJECT_DELAY__SHIFT                                                   0x8
4969 #define TD_DSM_CNTL2__TD_INJECT_DELAY__SHIFT                                                                  0x1a
4970 #define TD_DSM_CNTL2__TD_SS_FIFO_LO_ENABLE_ERROR_INJECT_MASK                                                  0x00000003L
4971 #define TD_DSM_CNTL2__TD_SS_FIFO_LO_SELECT_INJECT_DELAY_MASK                                                  0x00000004L
4972 #define TD_DSM_CNTL2__TD_SS_FIFO_HI_ENABLE_ERROR_INJECT_MASK                                                  0x00000018L
4973 #define TD_DSM_CNTL2__TD_SS_FIFO_HI_SELECT_INJECT_DELAY_MASK                                                  0x00000020L
4974 #define TD_DSM_CNTL2__TD_CS_FIFO_ENABLE_ERROR_INJECT_MASK                                                     0x000000C0L
4975 #define TD_DSM_CNTL2__TD_CS_FIFO_SELECT_INJECT_DELAY_MASK                                                     0x00000100L
4976 #define TD_DSM_CNTL2__TD_INJECT_DELAY_MASK                                                                    0xFC000000L
4977 //TD_SCRATCH
4978 #define TD_SCRATCH__SCRATCH__SHIFT                                                                            0x0
4979 #define TD_SCRATCH__SCRATCH_MASK                                                                              0xFFFFFFFFL
4980 //TA_POWER_CNTL
4981 #define TA_POWER_CNTL__INPUT_CLK_EN_MODE__SHIFT                                                               0x0
4982 #define TA_POWER_CNTL__LOD_CLK_EN_MODE__SHIFT                                                                 0x1
4983 #define TA_POWER_CNTL__WDP_CLK_EN_MODE__SHIFT                                                                 0x2
4984 #define TA_POWER_CNTL__INPUT_CLK_EN_MODE_MASK                                                                 0x00000001L
4985 #define TA_POWER_CNTL__LOD_CLK_EN_MODE_MASK                                                                   0x00000002L
4986 #define TA_POWER_CNTL__WDP_CLK_EN_MODE_MASK                                                                   0x00000004L
4987 //TA_CNTL
4988 #define TA_CNTL__FX_XNACK_CREDIT__SHIFT                                                                       0x0
4989 #define TA_CNTL__SQ_XNACK_CREDIT__SHIFT                                                                       0x9
4990 #define TA_CNTL__TC_DATA_CREDIT__SHIFT                                                                        0xd
4991 #define TA_CNTL__ALIGNER_CREDIT__SHIFT                                                                        0x10
4992 #define TA_CNTL__TD_FIFO_CREDIT__SHIFT                                                                        0x16
4993 #define TA_CNTL__FX_XNACK_CREDIT_MASK                                                                         0x0000007FL
4994 #define TA_CNTL__SQ_XNACK_CREDIT_MASK                                                                         0x00001E00L
4995 #define TA_CNTL__TC_DATA_CREDIT_MASK                                                                          0x0000E000L
4996 #define TA_CNTL__ALIGNER_CREDIT_MASK                                                                          0x001F0000L
4997 #define TA_CNTL__TD_FIFO_CREDIT_MASK                                                                          0xFFC00000L
4998 //TA_CNTL_AUX
4999 #define TA_CNTL_AUX__SCOAL_DSWIZZLE_N__SHIFT                                                                  0x0
5000 #define TA_CNTL_AUX__RESERVED__SHIFT                                                                          0x1
5001 #define TA_CNTL_AUX__TFAULT_EN_OVERRIDE__SHIFT                                                                0x5
5002 #define TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE__SHIFT                                                        0x7
5003 #define TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE__SHIFT                                                      0x14
5004 #define TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE__SHIFT                                                 0x15
5005 #define TA_CNTL_AUX__DETERMINISM_MISC_DISABLE__SHIFT                                                          0x16
5006 #define TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE__SHIFT                                                 0x17
5007 #define TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE__SHIFT                                                  0x18
5008 #define TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE__SHIFT                                               0x19
5009 #define TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE__SHIFT                                                     0x1a
5010 #define TA_CNTL_AUX__SCOAL_DSWIZZLE_N_MASK                                                                    0x00000001L
5011 #define TA_CNTL_AUX__RESERVED_MASK                                                                            0x0000000EL
5012 #define TA_CNTL_AUX__TFAULT_EN_OVERRIDE_MASK                                                                  0x00000020L
5013 #define TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE_MASK                                                          0x00000080L
5014 #define TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE_MASK                                                        0x00100000L
5015 #define TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE_MASK                                                   0x00200000L
5016 #define TA_CNTL_AUX__DETERMINISM_MISC_DISABLE_MASK                                                            0x00400000L
5017 #define TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE_MASK                                                   0x00800000L
5018 #define TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE_MASK                                                    0x01000000L
5019 #define TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE_MASK                                                 0x02000000L
5020 #define TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE_MASK                                                       0x04000000L
5021 //TA_FEATURE_CNTL
5022 #define TA_FEATURE_CNTL__ATOMIC_COALESCING_EN__SHIFT                                                          0x4
5023 #define TA_FEATURE_CNTL__TA_ACFIFO_CHICKEN__SHIFT                                                             0xb
5024 #define TA_FEATURE_CNTL__TA_CAC_CHICKEN__SHIFT                                                                0xc
5025 #define TA_FEATURE_CNTL__AFIFO_SPLIT_CHICKEN__SHIFT                                                           0xd
5026 #define TA_FEATURE_CNTL__TA_DXFIFO_CHICKEN__SHIFT                                                             0xe
5027 #define TA_FEATURE_CNTL__ATOMIC_COALESCING_EN_MASK                                                            0x00000030L
5028 #define TA_FEATURE_CNTL__TA_ACFIFO_CHICKEN_MASK                                                               0x00000800L
5029 #define TA_FEATURE_CNTL__TA_CAC_CHICKEN_MASK                                                                  0x00001000L
5030 #define TA_FEATURE_CNTL__AFIFO_SPLIT_CHICKEN_MASK                                                             0x00002000L
5031 #define TA_FEATURE_CNTL__TA_DXFIFO_CHICKEN_MASK                                                               0x00004000L
5032 //TA_STATUS
5033 #define TA_STATUS__FG_PFIFO_EMPTYB__SHIFT                                                                     0xc
5034 #define TA_STATUS__FL_PFIFO_EMPTYB__SHIFT                                                                     0x10
5035 #define TA_STATUS__FA_PFIFO_EMPTYB__SHIFT                                                                     0x14
5036 #define TA_STATUS__IN_BUSY__SHIFT                                                                             0x18
5037 #define TA_STATUS__FG_BUSY__SHIFT                                                                             0x19
5038 #define TA_STATUS__TA_BUSY__SHIFT                                                                             0x1c
5039 #define TA_STATUS__FA_BUSY__SHIFT                                                                             0x1d
5040 #define TA_STATUS__AL_BUSY__SHIFT                                                                             0x1e
5041 #define TA_STATUS__BUSY__SHIFT                                                                                0x1f
5042 #define TA_STATUS__FG_PFIFO_EMPTYB_MASK                                                                       0x00001000L
5043 #define TA_STATUS__FL_PFIFO_EMPTYB_MASK                                                                       0x00010000L
5044 #define TA_STATUS__FA_PFIFO_EMPTYB_MASK                                                                       0x00100000L
5045 #define TA_STATUS__IN_BUSY_MASK                                                                               0x01000000L
5046 #define TA_STATUS__FG_BUSY_MASK                                                                               0x02000000L
5047 #define TA_STATUS__TA_BUSY_MASK                                                                               0x10000000L
5048 #define TA_STATUS__FA_BUSY_MASK                                                                               0x20000000L
5049 #define TA_STATUS__AL_BUSY_MASK                                                                               0x40000000L
5050 #define TA_STATUS__BUSY_MASK                                                                                  0x80000000L
5051 //TA_SCRATCH
5052 #define TA_SCRATCH__SCRATCH__SHIFT                                                                            0x0
5053 #define TA_SCRATCH__SCRATCH_MASK                                                                              0xFFFFFFFFL
5054 //TA_DSM_CNTL
5055 #define TA_DSM_CNTL__TA_FS_DFIFO_DSM_IRRITATOR_DATA__SHIFT                                                    0x0
5056 #define TA_DSM_CNTL__TA_FS_DFIFO_ENABLE_SINGLE_WRITE__SHIFT                                                   0x2
5057 #define TA_DSM_CNTL__TA_FX_LFIFO_DSM_IRRITATOR_DATA__SHIFT                                                    0x9
5058 #define TA_DSM_CNTL__TA_FX_LFIFO_ENABLE_SINGLE_WRITE__SHIFT                                                   0xb
5059 #define TA_DSM_CNTL__TA_FS_CFIFO_DSM_IRRITATOR_DATA__SHIFT                                                    0xc
5060 #define TA_DSM_CNTL__TA_FS_CFIFO_ENABLE_SINGLE_WRITE__SHIFT                                                   0xe
5061 #define TA_DSM_CNTL__TA_FS_AFIFO_LO_DSM_IRRITATOR_DATA__SHIFT                                                 0xf
5062 #define TA_DSM_CNTL__TA_FS_AFIFO_LO_ENABLE_SINGLE_WRITE__SHIFT                                                0x11
5063 #define TA_DSM_CNTL__TA_FS_AFIFO_HI_DSM_IRRITATOR_DATA__SHIFT                                                 0x12
5064 #define TA_DSM_CNTL__TA_FS_AFIFO_HI_ENABLE_SINGLE_WRITE__SHIFT                                                0x14
5065 #define TA_DSM_CNTL__TA_FS_DFIFO_DSM_IRRITATOR_DATA_MASK                                                      0x00000003L
5066 #define TA_DSM_CNTL__TA_FS_DFIFO_ENABLE_SINGLE_WRITE_MASK                                                     0x00000004L
5067 #define TA_DSM_CNTL__TA_FX_LFIFO_DSM_IRRITATOR_DATA_MASK                                                      0x00000600L
5068 #define TA_DSM_CNTL__TA_FX_LFIFO_ENABLE_SINGLE_WRITE_MASK                                                     0x00000800L
5069 #define TA_DSM_CNTL__TA_FS_CFIFO_DSM_IRRITATOR_DATA_MASK                                                      0x00003000L
5070 #define TA_DSM_CNTL__TA_FS_CFIFO_ENABLE_SINGLE_WRITE_MASK                                                     0x00004000L
5071 #define TA_DSM_CNTL__TA_FS_AFIFO_LO_DSM_IRRITATOR_DATA_MASK                                                   0x00018000L
5072 #define TA_DSM_CNTL__TA_FS_AFIFO_LO_ENABLE_SINGLE_WRITE_MASK                                                  0x00020000L
5073 #define TA_DSM_CNTL__TA_FS_AFIFO_HI_DSM_IRRITATOR_DATA_MASK                                                   0x000C0000L
5074 #define TA_DSM_CNTL__TA_FS_AFIFO_HI_ENABLE_SINGLE_WRITE_MASK                                                  0x00100000L
5075 //TA_DSM_CNTL2
5076 #define TA_DSM_CNTL2__TA_FS_DFIFO_ENABLE_ERROR_INJECT__SHIFT                                                  0x0
5077 #define TA_DSM_CNTL2__TA_FS_DFIFO_SELECT_INJECT_DELAY__SHIFT                                                  0x2
5078 #define TA_DSM_CNTL2__TA_FX_LFIFO_ENABLE_ERROR_INJECT__SHIFT                                                  0x9
5079 #define TA_DSM_CNTL2__TA_FX_LFIFO_SELECT_INJECT_DELAY__SHIFT                                                  0xb
5080 #define TA_DSM_CNTL2__TA_FS_CFIFO_ENABLE_ERROR_INJECT__SHIFT                                                  0xc
5081 #define TA_DSM_CNTL2__TA_FS_CFIFO_SELECT_INJECT_DELAY__SHIFT                                                  0xe
5082 #define TA_DSM_CNTL2__TA_FS_AFIFO_LO_ENABLE_ERROR_INJECT__SHIFT                                               0xf
5083 #define TA_DSM_CNTL2__TA_FS_AFIFO_LO_SELECT_INJECT_DELAY__SHIFT                                               0x11
5084 #define TA_DSM_CNTL2__TA_FS_AFIFO_HI_ENABLE_ERROR_INJECT__SHIFT                                               0x12
5085 #define TA_DSM_CNTL2__TA_FS_AFIFO_HI_SELECT_INJECT_DELAY__SHIFT                                               0x14
5086 #define TA_DSM_CNTL2__TA_INJECT_DELAY__SHIFT                                                                  0x1a
5087 #define TA_DSM_CNTL2__TA_FS_DFIFO_ENABLE_ERROR_INJECT_MASK                                                    0x00000003L
5088 #define TA_DSM_CNTL2__TA_FS_DFIFO_SELECT_INJECT_DELAY_MASK                                                    0x00000004L
5089 #define TA_DSM_CNTL2__TA_FX_LFIFO_ENABLE_ERROR_INJECT_MASK                                                    0x00000600L
5090 #define TA_DSM_CNTL2__TA_FX_LFIFO_SELECT_INJECT_DELAY_MASK                                                    0x00000800L
5091 #define TA_DSM_CNTL2__TA_FS_CFIFO_ENABLE_ERROR_INJECT_MASK                                                    0x00003000L
5092 #define TA_DSM_CNTL2__TA_FS_CFIFO_SELECT_INJECT_DELAY_MASK                                                    0x00004000L
5093 #define TA_DSM_CNTL2__TA_FS_AFIFO_LO_ENABLE_ERROR_INJECT_MASK                                                 0x00018000L
5094 #define TA_DSM_CNTL2__TA_FS_AFIFO_LO_SELECT_INJECT_DELAY_MASK                                                 0x00020000L
5095 #define TA_DSM_CNTL2__TA_FS_AFIFO_HI_ENABLE_ERROR_INJECT_MASK                                                 0x000C0000L
5096 #define TA_DSM_CNTL2__TA_FS_AFIFO_HI_SELECT_INJECT_DELAY_MASK                                                 0x00100000L
5097 #define TA_DSM_CNTL2__TA_INJECT_DELAY_MASK                                                                    0xFC000000L
5098 //TA_UE_EDC_LO
5099 #define TA_UE_EDC_LO__STATUS_VALID_FLAG__SHIFT                                                                0x0
5100 #define TA_UE_EDC_LO__ADDRESS_INFO_VALID_FLAG__SHIFT                                                          0x1
5101 #define TA_UE_EDC_LO__ADDRESS__SHIFT                                                                          0x2
5102 #define TA_UE_EDC_LO__MEM_ID__SHIFT                                                                           0x18
5103 #define TA_UE_EDC_LO__STATUS_VALID_FLAG_MASK                                                                  0x00000001L
5104 #define TA_UE_EDC_LO__ADDRESS_INFO_VALID_FLAG_MASK                                                            0x00000002L
5105 #define TA_UE_EDC_LO__ADDRESS_MASK                                                                            0x00FFFFFCL
5106 #define TA_UE_EDC_LO__MEM_ID_MASK                                                                             0xFF000000L
5107 //TA_UE_EDC_HI
5108 #define TA_UE_EDC_HI__ECC__SHIFT                                                                              0x0
5109 #define TA_UE_EDC_HI__PARITY__SHIFT                                                                           0x1
5110 #define TA_UE_EDC_HI__ERR_INFO_VALID_FLAG__SHIFT                                                              0x2
5111 #define TA_UE_EDC_HI__ERR_INFO__SHIFT                                                                         0x3
5112 #define TA_UE_EDC_HI__UE_CNT__SHIFT                                                                           0x17
5113 #define TA_UE_EDC_HI__FED_CNT__SHIFT                                                                          0x1a
5114 #define TA_UE_EDC_HI__ECC_MASK                                                                                0x00000001L
5115 #define TA_UE_EDC_HI__PARITY_MASK                                                                             0x00000002L
5116 #define TA_UE_EDC_HI__ERR_INFO_VALID_FLAG_MASK                                                                0x00000004L
5117 #define TA_UE_EDC_HI__ERR_INFO_MASK                                                                           0x007FFFF8L
5118 #define TA_UE_EDC_HI__UE_CNT_MASK                                                                             0x03800000L
5119 #define TA_UE_EDC_HI__FED_CNT_MASK                                                                            0x1C000000L
5120 //TA_CE_EDC_LO
5121 #define TA_CE_EDC_LO__STATUS_VALID_FLAG__SHIFT                                                                0x0
5122 #define TA_CE_EDC_LO__ADDRESS_INFO_VALID_FLAG__SHIFT                                                          0x1
5123 #define TA_CE_EDC_LO__ADDRESS__SHIFT                                                                          0x2
5124 #define TA_CE_EDC_LO__MEM_ID__SHIFT                                                                           0x18
5125 #define TA_CE_EDC_LO__STATUS_VALID_FLAG_MASK                                                                  0x00000001L
5126 #define TA_CE_EDC_LO__ADDRESS_INFO_VALID_FLAG_MASK                                                            0x00000002L
5127 #define TA_CE_EDC_LO__ADDRESS_MASK                                                                            0x00FFFFFCL
5128 #define TA_CE_EDC_LO__MEM_ID_MASK                                                                             0xFF000000L
5129 //TA_CE_EDC_HI
5130 #define TA_CE_EDC_HI__ECC__SHIFT                                                                              0x0
5131 #define TA_CE_EDC_HI__ERR_INFO_VALID_FLAG__SHIFT                                                              0x2
5132 #define TA_CE_EDC_HI__ERR_INFO__SHIFT                                                                         0x3
5133 #define TA_CE_EDC_HI__CE_CNT__SHIFT                                                                           0x17
5134 #define TA_CE_EDC_HI__POISON__SHIFT                                                                           0x1a
5135 #define TA_CE_EDC_HI__ECC_MASK                                                                                0x00000001L
5136 #define TA_CE_EDC_HI__ERR_INFO_VALID_FLAG_MASK                                                                0x00000004L
5137 #define TA_CE_EDC_HI__ERR_INFO_MASK                                                                           0x007FFFF8L
5138 #define TA_CE_EDC_HI__CE_CNT_MASK                                                                             0x03800000L
5139 #define TA_CE_EDC_HI__POISON_MASK                                                                             0x04000000L
5140 
5141 
5142 // addressBlock: xcd0_gc_gdsdec
5143 //GDS_CONFIG
5144 #define GDS_CONFIG__WRITE_DIS__SHIFT                                                                          0x0
5145 #define GDS_CONFIG__SH0_GPR_PHASE_SEL__SHIFT                                                                  0x1
5146 #define GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT                                                                  0x3
5147 #define GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT                                                                  0x5
5148 #define GDS_CONFIG__SH3_GPR_PHASE_SEL__SHIFT                                                                  0x7
5149 #define GDS_CONFIG__SH4_GPR_PHASE_SEL__SHIFT                                                                  0x9
5150 #define GDS_CONFIG__SH5_GPR_PHASE_SEL__SHIFT                                                                  0xb
5151 #define GDS_CONFIG__SH6_GPR_PHASE_SEL__SHIFT                                                                  0xd
5152 #define GDS_CONFIG__SH7_GPR_PHASE_SEL__SHIFT                                                                  0xf
5153 #define GDS_CONFIG__WRITE_DIS_MASK                                                                            0x00000001L
5154 #define GDS_CONFIG__SH0_GPR_PHASE_SEL_MASK                                                                    0x00000006L
5155 #define GDS_CONFIG__SH1_GPR_PHASE_SEL_MASK                                                                    0x00000018L
5156 #define GDS_CONFIG__SH2_GPR_PHASE_SEL_MASK                                                                    0x00000060L
5157 #define GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK                                                                    0x00000180L
5158 #define GDS_CONFIG__SH4_GPR_PHASE_SEL_MASK                                                                    0x00000600L
5159 #define GDS_CONFIG__SH5_GPR_PHASE_SEL_MASK                                                                    0x00001800L
5160 #define GDS_CONFIG__SH6_GPR_PHASE_SEL_MASK                                                                    0x00006000L
5161 #define GDS_CONFIG__SH7_GPR_PHASE_SEL_MASK                                                                    0x00018000L
5162 //GDS_CNTL_STATUS
5163 #define GDS_CNTL_STATUS__GDS_BUSY__SHIFT                                                                      0x0
5164 #define GDS_CNTL_STATUS__GRBM_WBUF_BUSY__SHIFT                                                                0x1
5165 #define GDS_CNTL_STATUS__ORD_APP_BUSY__SHIFT                                                                  0x2
5166 #define GDS_CNTL_STATUS__DS_BANK_CONFLICT__SHIFT                                                              0x3
5167 #define GDS_CNTL_STATUS__DS_ADDR_CONFLICT__SHIFT                                                              0x4
5168 #define GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT                                                                   0x5
5169 #define GDS_CNTL_STATUS__DS_RD_CLAMP__SHIFT                                                                   0x6
5170 #define GDS_CNTL_STATUS__GRBM_RBUF_BUSY__SHIFT                                                                0x7
5171 #define GDS_CNTL_STATUS__DS_BUSY__SHIFT                                                                       0x8
5172 #define GDS_CNTL_STATUS__GWS_BUSY__SHIFT                                                                      0x9
5173 #define GDS_CNTL_STATUS__ORD_FIFO_BUSY__SHIFT                                                                 0xa
5174 #define GDS_CNTL_STATUS__CREDIT_BUSY0__SHIFT                                                                  0xb
5175 #define GDS_CNTL_STATUS__CREDIT_BUSY1__SHIFT                                                                  0xc
5176 #define GDS_CNTL_STATUS__CREDIT_BUSY2__SHIFT                                                                  0xd
5177 #define GDS_CNTL_STATUS__CREDIT_BUSY3__SHIFT                                                                  0xe
5178 #define GDS_CNTL_STATUS__CREDIT_BUSY4__SHIFT                                                                  0xf
5179 #define GDS_CNTL_STATUS__CREDIT_BUSY5__SHIFT                                                                  0x10
5180 #define GDS_CNTL_STATUS__CREDIT_BUSY6__SHIFT                                                                  0x11
5181 #define GDS_CNTL_STATUS__CREDIT_BUSY7__SHIFT                                                                  0x12
5182 #define GDS_CNTL_STATUS__GDS_BUSY_MASK                                                                        0x00000001L
5183 #define GDS_CNTL_STATUS__GRBM_WBUF_BUSY_MASK                                                                  0x00000002L
5184 #define GDS_CNTL_STATUS__ORD_APP_BUSY_MASK                                                                    0x00000004L
5185 #define GDS_CNTL_STATUS__DS_BANK_CONFLICT_MASK                                                                0x00000008L
5186 #define GDS_CNTL_STATUS__DS_ADDR_CONFLICT_MASK                                                                0x00000010L
5187 #define GDS_CNTL_STATUS__DS_WR_CLAMP_MASK                                                                     0x00000020L
5188 #define GDS_CNTL_STATUS__DS_RD_CLAMP_MASK                                                                     0x00000040L
5189 #define GDS_CNTL_STATUS__GRBM_RBUF_BUSY_MASK                                                                  0x00000080L
5190 #define GDS_CNTL_STATUS__DS_BUSY_MASK                                                                         0x00000100L
5191 #define GDS_CNTL_STATUS__GWS_BUSY_MASK                                                                        0x00000200L
5192 #define GDS_CNTL_STATUS__ORD_FIFO_BUSY_MASK                                                                   0x00000400L
5193 #define GDS_CNTL_STATUS__CREDIT_BUSY0_MASK                                                                    0x00000800L
5194 #define GDS_CNTL_STATUS__CREDIT_BUSY1_MASK                                                                    0x00001000L
5195 #define GDS_CNTL_STATUS__CREDIT_BUSY2_MASK                                                                    0x00002000L
5196 #define GDS_CNTL_STATUS__CREDIT_BUSY3_MASK                                                                    0x00004000L
5197 #define GDS_CNTL_STATUS__CREDIT_BUSY4_MASK                                                                    0x00008000L
5198 #define GDS_CNTL_STATUS__CREDIT_BUSY5_MASK                                                                    0x00010000L
5199 #define GDS_CNTL_STATUS__CREDIT_BUSY6_MASK                                                                    0x00020000L
5200 #define GDS_CNTL_STATUS__CREDIT_BUSY7_MASK                                                                    0x00040000L
5201 //GDS_ENHANCE2
5202 #define GDS_ENHANCE2__MISC__SHIFT                                                                             0x0
5203 #define GDS_ENHANCE2__GDS_TD_INTERFACES_FGCG_OVERRIDE__SHIFT                                                  0x10
5204 #define GDS_ENHANCE2__GDS_PHY_CMD_RAM_FGCG_OVERRIDE__SHIFT                                                    0x11
5205 #define GDS_ENHANCE2__GDS_FED_IN_PROPAGATE__SHIFT                                                             0x12
5206 #define GDS_ENHANCE2__UNUSED__SHIFT                                                                           0x13
5207 #define GDS_ENHANCE2__MISC_MASK                                                                               0x0000FFFFL
5208 #define GDS_ENHANCE2__GDS_TD_INTERFACES_FGCG_OVERRIDE_MASK                                                    0x00010000L
5209 #define GDS_ENHANCE2__GDS_PHY_CMD_RAM_FGCG_OVERRIDE_MASK                                                      0x00020000L
5210 #define GDS_ENHANCE2__GDS_FED_IN_PROPAGATE_MASK                                                               0x00040000L
5211 #define GDS_ENHANCE2__UNUSED_MASK                                                                             0xFFF80000L
5212 //GDS_PROTECTION_FAULT
5213 #define GDS_PROTECTION_FAULT__WRITE_DIS__SHIFT                                                                0x0
5214 #define GDS_PROTECTION_FAULT__FAULT_DETECTED__SHIFT                                                           0x1
5215 #define GDS_PROTECTION_FAULT__GRBM__SHIFT                                                                     0x2
5216 #define GDS_PROTECTION_FAULT__SH_ID__SHIFT                                                                    0x3
5217 #define GDS_PROTECTION_FAULT__CU_ID__SHIFT                                                                    0x6
5218 #define GDS_PROTECTION_FAULT__SIMD_ID__SHIFT                                                                  0xa
5219 #define GDS_PROTECTION_FAULT__WAVE_ID__SHIFT                                                                  0xc
5220 #define GDS_PROTECTION_FAULT__ADDRESS__SHIFT                                                                  0x10
5221 #define GDS_PROTECTION_FAULT__WRITE_DIS_MASK                                                                  0x00000001L
5222 #define GDS_PROTECTION_FAULT__FAULT_DETECTED_MASK                                                             0x00000002L
5223 #define GDS_PROTECTION_FAULT__GRBM_MASK                                                                       0x00000004L
5224 #define GDS_PROTECTION_FAULT__SH_ID_MASK                                                                      0x00000038L
5225 #define GDS_PROTECTION_FAULT__CU_ID_MASK                                                                      0x000003C0L
5226 #define GDS_PROTECTION_FAULT__SIMD_ID_MASK                                                                    0x00000C00L
5227 #define GDS_PROTECTION_FAULT__WAVE_ID_MASK                                                                    0x0000F000L
5228 #define GDS_PROTECTION_FAULT__ADDRESS_MASK                                                                    0xFFFF0000L
5229 //GDS_VM_PROTECTION_FAULT
5230 #define GDS_VM_PROTECTION_FAULT__WRITE_DIS__SHIFT                                                             0x0
5231 #define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED__SHIFT                                                        0x1
5232 #define GDS_VM_PROTECTION_FAULT__GWS__SHIFT                                                                   0x2
5233 #define GDS_VM_PROTECTION_FAULT__OA__SHIFT                                                                    0x3
5234 #define GDS_VM_PROTECTION_FAULT__GRBM__SHIFT                                                                  0x4
5235 #define GDS_VM_PROTECTION_FAULT__TMZ__SHIFT                                                                   0x5
5236 #define GDS_VM_PROTECTION_FAULT__VMID__SHIFT                                                                  0x8
5237 #define GDS_VM_PROTECTION_FAULT__ADDRESS__SHIFT                                                               0x10
5238 #define GDS_VM_PROTECTION_FAULT__WRITE_DIS_MASK                                                               0x00000001L
5239 #define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED_MASK                                                          0x00000002L
5240 #define GDS_VM_PROTECTION_FAULT__GWS_MASK                                                                     0x00000004L
5241 #define GDS_VM_PROTECTION_FAULT__OA_MASK                                                                      0x00000008L
5242 #define GDS_VM_PROTECTION_FAULT__GRBM_MASK                                                                    0x00000010L
5243 #define GDS_VM_PROTECTION_FAULT__TMZ_MASK                                                                     0x00000020L
5244 #define GDS_VM_PROTECTION_FAULT__VMID_MASK                                                                    0x00000F00L
5245 #define GDS_VM_PROTECTION_FAULT__ADDRESS_MASK                                                                 0xFFFF0000L
5246 //GDS_EDC_CNT
5247 #define GDS_EDC_CNT__GDS_MEM_DED__SHIFT                                                                       0x0
5248 #define GDS_EDC_CNT__GDS_MEM_SEC__SHIFT                                                                       0x4
5249 #define GDS_EDC_CNT__UNUSED__SHIFT                                                                            0x6
5250 #define GDS_EDC_CNT__GDS_MEM_DED_MASK                                                                         0x00000003L
5251 #define GDS_EDC_CNT__GDS_MEM_SEC_MASK                                                                         0x00000030L
5252 #define GDS_EDC_CNT__UNUSED_MASK                                                                              0xFFFFFFC0L
5253 //GDS_EDC_GRBM_CNT
5254 #define GDS_EDC_GRBM_CNT__DED__SHIFT                                                                          0x0
5255 #define GDS_EDC_GRBM_CNT__SEC__SHIFT                                                                          0x2
5256 #define GDS_EDC_GRBM_CNT__UNUSED__SHIFT                                                                       0x4
5257 #define GDS_EDC_GRBM_CNT__DED_MASK                                                                            0x00000003L
5258 #define GDS_EDC_GRBM_CNT__SEC_MASK                                                                            0x0000000CL
5259 #define GDS_EDC_GRBM_CNT__UNUSED_MASK                                                                         0xFFFFFFF0L
5260 //GDS_EDC_OA_DED
5261 #define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED__SHIFT                                                            0x0
5262 #define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED__SHIFT                                                            0x1
5263 #define GDS_EDC_OA_DED__ME0_CS_DED__SHIFT                                                                     0x2
5264 #define GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED__SHIFT                                                             0x3
5265 #define GDS_EDC_OA_DED__ME1_PIPE0_DED__SHIFT                                                                  0x4
5266 #define GDS_EDC_OA_DED__ME1_PIPE1_DED__SHIFT                                                                  0x5
5267 #define GDS_EDC_OA_DED__ME1_PIPE2_DED__SHIFT                                                                  0x6
5268 #define GDS_EDC_OA_DED__ME1_PIPE3_DED__SHIFT                                                                  0x7
5269 #define GDS_EDC_OA_DED__ME2_PIPE0_DED__SHIFT                                                                  0x8
5270 #define GDS_EDC_OA_DED__ME2_PIPE1_DED__SHIFT                                                                  0x9
5271 #define GDS_EDC_OA_DED__ME2_PIPE2_DED__SHIFT                                                                  0xa
5272 #define GDS_EDC_OA_DED__ME2_PIPE3_DED__SHIFT                                                                  0xb
5273 #define GDS_EDC_OA_DED__UNUSED1__SHIFT                                                                        0xc
5274 #define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED_MASK                                                              0x00000001L
5275 #define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED_MASK                                                              0x00000002L
5276 #define GDS_EDC_OA_DED__ME0_CS_DED_MASK                                                                       0x00000004L
5277 #define GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED_MASK                                                               0x00000008L
5278 #define GDS_EDC_OA_DED__ME1_PIPE0_DED_MASK                                                                    0x00000010L
5279 #define GDS_EDC_OA_DED__ME1_PIPE1_DED_MASK                                                                    0x00000020L
5280 #define GDS_EDC_OA_DED__ME1_PIPE2_DED_MASK                                                                    0x00000040L
5281 #define GDS_EDC_OA_DED__ME1_PIPE3_DED_MASK                                                                    0x00000080L
5282 #define GDS_EDC_OA_DED__ME2_PIPE0_DED_MASK                                                                    0x00000100L
5283 #define GDS_EDC_OA_DED__ME2_PIPE1_DED_MASK                                                                    0x00000200L
5284 #define GDS_EDC_OA_DED__ME2_PIPE2_DED_MASK                                                                    0x00000400L
5285 #define GDS_EDC_OA_DED__ME2_PIPE3_DED_MASK                                                                    0x00000800L
5286 #define GDS_EDC_OA_DED__UNUSED1_MASK                                                                          0xFFFFF000L
5287 //GDS_DSM_CNTL
5288 #define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0__SHIFT                                                 0x0
5289 #define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1__SHIFT                                                 0x1
5290 #define GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE__SHIFT                                                      0x2
5291 #define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0__SHIFT                                         0x3
5292 #define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1__SHIFT                                         0x4
5293 #define GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE__SHIFT                                              0x5
5294 #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0__SHIFT                                         0x6
5295 #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1__SHIFT                                         0x7
5296 #define GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE__SHIFT                                              0x8
5297 #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0__SHIFT                                        0x9
5298 #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1__SHIFT                                        0xa
5299 #define GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE__SHIFT                                             0xb
5300 #define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0__SHIFT                                            0xc
5301 #define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1__SHIFT                                            0xd
5302 #define GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE__SHIFT                                                 0xe
5303 #define GDS_DSM_CNTL__UNUSED__SHIFT                                                                           0xf
5304 #define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0_MASK                                                   0x00000001L
5305 #define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1_MASK                                                   0x00000002L
5306 #define GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE_MASK                                                        0x00000004L
5307 #define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0_MASK                                           0x00000008L
5308 #define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1_MASK                                           0x00000010L
5309 #define GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE_MASK                                                0x00000020L
5310 #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0_MASK                                           0x00000040L
5311 #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1_MASK                                           0x00000080L
5312 #define GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE_MASK                                                0x00000100L
5313 #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0_MASK                                          0x00000200L
5314 #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1_MASK                                          0x00000400L
5315 #define GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE_MASK                                               0x00000800L
5316 #define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0_MASK                                              0x00001000L
5317 #define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1_MASK                                              0x00002000L
5318 #define GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE_MASK                                                   0x00004000L
5319 #define GDS_DSM_CNTL__UNUSED_MASK                                                                             0xFFFF8000L
5320 //GDS_EDC_OA_PHY_CNT
5321 #define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC__SHIFT                                                        0x0
5322 #define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED__SHIFT                                                        0x2
5323 #define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC__SHIFT                                                        0x4
5324 #define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED__SHIFT                                                        0x6
5325 #define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SEC__SHIFT                                                       0x8
5326 #define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_DED__SHIFT                                                       0xa
5327 #define GDS_EDC_OA_PHY_CNT__UNUSED1__SHIFT                                                                    0xc
5328 #define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC_MASK                                                          0x00000003L
5329 #define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED_MASK                                                          0x0000000CL
5330 #define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC_MASK                                                          0x00000030L
5331 #define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED_MASK                                                          0x000000C0L
5332 #define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SEC_MASK                                                         0x00000300L
5333 #define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_DED_MASK                                                         0x00000C00L
5334 #define GDS_EDC_OA_PHY_CNT__UNUSED1_MASK                                                                      0xFFFFF000L
5335 //GDS_EDC_OA_PIPE_CNT
5336 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC__SHIFT                                                    0x0
5337 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED__SHIFT                                                    0x2
5338 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC__SHIFT                                                    0x4
5339 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED__SHIFT                                                    0x6
5340 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC__SHIFT                                                    0x8
5341 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED__SHIFT                                                    0xa
5342 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC__SHIFT                                                    0xc
5343 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED__SHIFT                                                    0xe
5344 #define GDS_EDC_OA_PIPE_CNT__UNUSED__SHIFT                                                                    0x10
5345 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC_MASK                                                      0x00000003L
5346 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED_MASK                                                      0x0000000CL
5347 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC_MASK                                                      0x00000030L
5348 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED_MASK                                                      0x000000C0L
5349 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC_MASK                                                      0x00000300L
5350 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED_MASK                                                      0x00000C00L
5351 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC_MASK                                                      0x00003000L
5352 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED_MASK                                                      0x0000C000L
5353 #define GDS_EDC_OA_PIPE_CNT__UNUSED_MASK                                                                      0xFFFF0000L
5354 //GDS_DSM_CNTL2
5355 #define GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT__SHIFT                                                     0x0
5356 #define GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY__SHIFT                                                     0x2
5357 #define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT__SHIFT                                             0x3
5358 #define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY__SHIFT                                             0x5
5359 #define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT__SHIFT                                             0x6
5360 #define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY__SHIFT                                             0x8
5361 #define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT__SHIFT                                            0x9
5362 #define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY__SHIFT                                            0xb
5363 #define GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT__SHIFT                                                0xc
5364 #define GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY__SHIFT                                                0xe
5365 #define GDS_DSM_CNTL2__UNUSED__SHIFT                                                                          0xf
5366 #define GDS_DSM_CNTL2__GDS_INJECT_DELAY__SHIFT                                                                0x1a
5367 #define GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT_MASK                                                       0x00000003L
5368 #define GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY_MASK                                                       0x00000004L
5369 #define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT_MASK                                               0x00000018L
5370 #define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY_MASK                                               0x00000020L
5371 #define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT_MASK                                               0x000000C0L
5372 #define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY_MASK                                               0x00000100L
5373 #define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT_MASK                                              0x00000600L
5374 #define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY_MASK                                              0x00000800L
5375 #define GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT_MASK                                                  0x00003000L
5376 #define GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY_MASK                                                  0x00004000L
5377 #define GDS_DSM_CNTL2__UNUSED_MASK                                                                            0x03FF8000L
5378 #define GDS_DSM_CNTL2__GDS_INJECT_DELAY_MASK                                                                  0xFC000000L
5379 //GDS_WD_GDS_CSB
5380 #define GDS_WD_GDS_CSB__COUNTER__SHIFT                                                                        0x0
5381 #define GDS_WD_GDS_CSB__UNUSED__SHIFT                                                                         0xd
5382 #define GDS_WD_GDS_CSB__COUNTER_MASK                                                                          0x00001FFFL
5383 #define GDS_WD_GDS_CSB__UNUSED_MASK                                                                           0xFFFFE000L
5384 //GDS_UE_ERR_STATUS_LO
5385 #define GDS_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT                                                    0x0
5386 #define GDS_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT                                                       0x1
5387 #define GDS_UE_ERR_STATUS_LO__ADDRESS__SHIFT                                                                  0x2
5388 #define GDS_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT                                                                0x18
5389 #define GDS_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK                                                      0x00000001L
5390 #define GDS_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK                                                         0x00000002L
5391 #define GDS_UE_ERR_STATUS_LO__ADDRESS_MASK                                                                    0x00FFFFFCL
5392 #define GDS_UE_ERR_STATUS_LO__MEMORY_ID_MASK                                                                  0xFF000000L
5393 //GDS_UE_ERR_STATUS_HI
5394 #define GDS_UE_ERR_STATUS_HI__ECC__SHIFT                                                                      0x0
5395 #define GDS_UE_ERR_STATUS_HI__PARITY__SHIFT                                                                   0x1
5396 #define GDS_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT                                                      0x2
5397 #define GDS_UE_ERR_STATUS_HI__ERR_INFO__SHIFT                                                                 0x3
5398 #define GDS_UE_ERR_STATUS_HI__UE_CNT__SHIFT                                                                   0x17
5399 #define GDS_UE_ERR_STATUS_HI__FED_CNT__SHIFT                                                                  0x1a
5400 #define GDS_UE_ERR_STATUS_HI__RESERVED__SHIFT                                                                 0x1d
5401 #define GDS_UE_ERR_STATUS_HI__ECC_MASK                                                                        0x00000001L
5402 #define GDS_UE_ERR_STATUS_HI__PARITY_MASK                                                                     0x00000002L
5403 #define GDS_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK                                                        0x00000004L
5404 #define GDS_UE_ERR_STATUS_HI__ERR_INFO_MASK                                                                   0x007FFFF8L
5405 #define GDS_UE_ERR_STATUS_HI__UE_CNT_MASK                                                                     0x03800000L
5406 #define GDS_UE_ERR_STATUS_HI__FED_CNT_MASK                                                                    0x1C000000L
5407 #define GDS_UE_ERR_STATUS_HI__RESERVED_MASK                                                                   0xE0000000L
5408 //GDS_CE_ERR_STATUS_LO
5409 #define GDS_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT                                                    0x0
5410 #define GDS_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT                                                       0x1
5411 #define GDS_CE_ERR_STATUS_LO__ADDRESS__SHIFT                                                                  0x2
5412 #define GDS_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT                                                                0x18
5413 #define GDS_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK                                                      0x00000001L
5414 #define GDS_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK                                                         0x00000002L
5415 #define GDS_CE_ERR_STATUS_LO__ADDRESS_MASK                                                                    0x00FFFFFCL
5416 #define GDS_CE_ERR_STATUS_LO__MEMORY_ID_MASK                                                                  0xFF000000L
5417 //GDS_CE_ERR_STATUS_HI
5418 #define GDS_CE_ERR_STATUS_HI__ECC__SHIFT                                                                      0x0
5419 #define GDS_CE_ERR_STATUS_HI__OTHER__SHIFT                                                                    0x1
5420 #define GDS_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT                                                      0x2
5421 #define GDS_CE_ERR_STATUS_HI__ERR_INFO__SHIFT                                                                 0x3
5422 #define GDS_CE_ERR_STATUS_HI__CE_CNT__SHIFT                                                                   0x17
5423 #define GDS_CE_ERR_STATUS_HI__POISON__SHIFT                                                                   0x1a
5424 #define GDS_CE_ERR_STATUS_HI__RESERVED__SHIFT                                                                 0x1b
5425 #define GDS_CE_ERR_STATUS_HI__ECC_MASK                                                                        0x00000001L
5426 #define GDS_CE_ERR_STATUS_HI__OTHER_MASK                                                                      0x00000002L
5427 #define GDS_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK                                                        0x00000004L
5428 #define GDS_CE_ERR_STATUS_HI__ERR_INFO_MASK                                                                   0x007FFFF8L
5429 #define GDS_CE_ERR_STATUS_HI__CE_CNT_MASK                                                                     0x03800000L
5430 #define GDS_CE_ERR_STATUS_HI__POISON_MASK                                                                     0x04000000L
5431 #define GDS_CE_ERR_STATUS_HI__RESERVED_MASK                                                                   0xF8000000L
5432 
5433 
5434 // addressBlock: xcd0_gc_rbdec
5435 //DB_DEBUG
5436 #define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT                                                       0x0
5437 #define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT                                                         0x1
5438 #define DB_DEBUG__FETCH_FULL_Z_TILE__SHIFT                                                                    0x2
5439 #define DB_DEBUG__FETCH_FULL_STENCIL_TILE__SHIFT                                                              0x3
5440 #define DB_DEBUG__FORCE_Z_MODE__SHIFT                                                                         0x4
5441 #define DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT                                                               0x6
5442 #define DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT                                                             0x7
5443 #define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT                                                               0x8
5444 #define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT                                                              0xa
5445 #define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT                                                              0xc
5446 #define DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT                                                                 0xe
5447 #define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT                                                           0xf
5448 #define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT                                                              0x10
5449 #define DB_DEBUG__DISABLE_SUMM_SQUADS__SHIFT                                                                  0x11
5450 #define DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT                                                               0x12
5451 #define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT                                                             0x13
5452 #define DB_DEBUG__NEVER_FREE_Z_ONLY__SHIFT                                                                    0x15
5453 #define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT                                                0x16
5454 #define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT                                                    0x17
5455 #define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT                                                           0x18
5456 #define DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT                                                                   0x1c
5457 #define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT                                                           0x1d
5458 #define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC__SHIFT                                                           0x1e
5459 #define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC__SHIFT                                                           0x1f
5460 #define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK                                                         0x00000001L
5461 #define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK                                                           0x00000002L
5462 #define DB_DEBUG__FETCH_FULL_Z_TILE_MASK                                                                      0x00000004L
5463 #define DB_DEBUG__FETCH_FULL_STENCIL_TILE_MASK                                                                0x00000008L
5464 #define DB_DEBUG__FORCE_Z_MODE_MASK                                                                           0x00000030L
5465 #define DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK                                                                 0x00000040L
5466 #define DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK                                                               0x00000080L
5467 #define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK                                                                 0x00000300L
5468 #define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK                                                                0x00000C00L
5469 #define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK                                                                0x00003000L
5470 #define DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK                                                                   0x00004000L
5471 #define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK                                                             0x00008000L
5472 #define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK                                                                0x00010000L
5473 #define DB_DEBUG__DISABLE_SUMM_SQUADS_MASK                                                                    0x00020000L
5474 #define DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK                                                                 0x00040000L
5475 #define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK                                                               0x00180000L
5476 #define DB_DEBUG__NEVER_FREE_Z_ONLY_MASK                                                                      0x00200000L
5477 #define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK                                                  0x00400000L
5478 #define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK                                                      0x00800000L
5479 #define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK                                                             0x0F000000L
5480 #define DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK                                                                     0x10000000L
5481 #define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK                                                             0x20000000L
5482 #define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC_MASK                                                             0x40000000L
5483 #define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC_MASK                                                             0x80000000L
5484 //DB_DEBUG2
5485 #define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING__SHIFT                                                            0x0
5486 #define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE__SHIFT                                                          0x1
5487 #define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE__SHIFT                                                            0x2
5488 #define DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT                                                                 0x3
5489 #define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT                                                        0x4
5490 #define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL__SHIFT                                                            0x5
5491 #define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ__SHIFT                                                        0x6
5492 #define DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL__SHIFT                                                        0x7
5493 #define DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE__SHIFT                                                     0x8
5494 #define DB_DEBUG2__CLK_OFF_DELAY__SHIFT                                                                       0x9
5495 #define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER__SHIFT                                                    0xe
5496 #define DB_DEBUG2__ENABLE_SUBTILE_GROUPING__SHIFT                                                             0xf
5497 #define DB_DEBUG2__RESERVED__SHIFT                                                                            0x10
5498 #define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT                                                         0x11
5499 #define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT                                                         0x12
5500 #define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT                                                        0x13
5501 #define DB_DEBUG2__DISABLE_VR_OBJ_PRIM_ID__SHIFT                                                              0x1a
5502 #define DB_DEBUG2__DISABLE_VR_PS_INVOKE__SHIFT                                                                0x1b
5503 #define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM__SHIFT                                                             0x1c
5504 #define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT                                                        0x1d
5505 #define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT                                                    0x1e
5506 #define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT__SHIFT                                                0x1f
5507 #define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING_MASK                                                              0x00000001L
5508 #define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE_MASK                                                            0x00000002L
5509 #define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE_MASK                                                              0x00000004L
5510 #define DB_DEBUG2__DTR_ROUND_ROBIN_ARB_MASK                                                                   0x00000008L
5511 #define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK                                                          0x00000010L
5512 #define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_MASK                                                              0x00000020L
5513 #define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ_MASK                                                          0x00000040L
5514 #define DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL_MASK                                                          0x00000080L
5515 #define DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE_MASK                                                       0x00000100L
5516 #define DB_DEBUG2__CLK_OFF_DELAY_MASK                                                                         0x00003E00L
5517 #define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER_MASK                                                      0x00004000L
5518 #define DB_DEBUG2__ENABLE_SUBTILE_GROUPING_MASK                                                               0x00008000L
5519 #define DB_DEBUG2__RESERVED_MASK                                                                              0x00010000L
5520 #define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING_MASK                                                           0x00020000L
5521 #define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING_MASK                                                           0x00040000L
5522 #define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL_MASK                                                          0x00080000L
5523 #define DB_DEBUG2__DISABLE_VR_OBJ_PRIM_ID_MASK                                                                0x04000000L
5524 #define DB_DEBUG2__DISABLE_VR_PS_INVOKE_MASK                                                                  0x08000000L
5525 #define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM_MASK                                                               0x10000000L
5526 #define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL_MASK                                                          0x20000000L
5527 #define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK                                                      0x40000000L
5528 #define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT_MASK                                                  0x80000000L
5529 //DB_DEBUG3
5530 #define DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION__SHIFT                                                     0x0
5531 #define DB_DEBUG3__ROUND_ZRANGE_CORRECTION__SHIFT                                                             0x1
5532 #define DB_DEBUG3__FORCE_DB_IS_GOOD__SHIFT                                                                    0x2
5533 #define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION__SHIFT                                                     0x3
5534 #define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT                                                          0x4
5535 #define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z__SHIFT                                                             0x5
5536 #define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z__SHIFT                                                              0x6
5537 #define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS__SHIFT                                                              0x7
5538 #define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION__SHIFT                                                      0x8
5539 #define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT__SHIFT                                                 0x9
5540 #define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT                                            0xa
5541 #define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS__SHIFT                                                        0xb
5542 #define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING__SHIFT                                                        0xc
5543 #define DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT                                                                0xd
5544 #define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT                                                         0xe
5545 #define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT                                                       0xf
5546 #define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION__SHIFT                                                             0x10
5547 #define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT                                                         0x11
5548 #define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING__SHIFT                                                        0x12
5549 #define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE__SHIFT                                                     0x13
5550 #define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE__SHIFT                                                         0x14
5551 #define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT                                                0x15
5552 #define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB__SHIFT                                                        0x16
5553 #define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD__SHIFT                                                  0x17
5554 #define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT__SHIFT                                                           0x18
5555 #define DB_DEBUG3__DISABLE_DI_DT_STALL__SHIFT                                                                 0x19
5556 #define DB_DEBUG3__ENABLE_DB_PROCESS_RESET__SHIFT                                                             0x1a
5557 #define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX__SHIFT                                                       0x1b
5558 #define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND__SHIFT                                                         0x1c
5559 #define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND__SHIFT                                                         0x1d
5560 #define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE__SHIFT                                                       0x1e
5561 #define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK__SHIFT                                                   0x1f
5562 #define DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION_MASK                                                       0x00000001L
5563 #define DB_DEBUG3__ROUND_ZRANGE_CORRECTION_MASK                                                               0x00000002L
5564 #define DB_DEBUG3__FORCE_DB_IS_GOOD_MASK                                                                      0x00000004L
5565 #define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION_MASK                                                       0x00000008L
5566 #define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP_MASK                                                            0x00000010L
5567 #define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z_MASK                                                               0x00000020L
5568 #define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z_MASK                                                                0x00000040L
5569 #define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS_MASK                                                                0x00000080L
5570 #define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION_MASK                                                        0x00000100L
5571 #define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT_MASK                                                   0x00000200L
5572 #define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK                                              0x00000400L
5573 #define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS_MASK                                                          0x00000800L
5574 #define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING_MASK                                                          0x00001000L
5575 #define DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK                                                                  0x00002000L
5576 #define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK                                                           0x00004000L
5577 #define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK                                                         0x00008000L
5578 #define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION_MASK                                                               0x00010000L
5579 #define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK                                                           0x00020000L
5580 #define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING_MASK                                                          0x00040000L
5581 #define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK                                                       0x00080000L
5582 #define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK                                                           0x00100000L
5583 #define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK                                                  0x00200000L
5584 #define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB_MASK                                                          0x00400000L
5585 #define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD_MASK                                                    0x00800000L
5586 #define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT_MASK                                                             0x01000000L
5587 #define DB_DEBUG3__DISABLE_DI_DT_STALL_MASK                                                                   0x02000000L
5588 #define DB_DEBUG3__ENABLE_DB_PROCESS_RESET_MASK                                                               0x04000000L
5589 #define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX_MASK                                                         0x08000000L
5590 #define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND_MASK                                                           0x10000000L
5591 #define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND_MASK                                                           0x20000000L
5592 #define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE_MASK                                                         0x40000000L
5593 #define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK_MASK                                                     0x80000000L
5594 //DB_DEBUG4
5595 #define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION__SHIFT                                                         0x0
5596 #define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION__SHIFT                                                   0x1
5597 #define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL__SHIFT                                                    0x2
5598 #define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT                                             0x3
5599 #define DB_DEBUG4__DISABLE_4XAA_2P_ZD_HOLDOFF__SHIFT                                                          0x4
5600 #define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION__SHIFT                                                       0x5
5601 #define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE__SHIFT                                                    0x6
5602 #define DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN__SHIFT                                                                0x7
5603 #define DB_DEBUG4__DFSM_CONVERT_PASSTHROUGH_TO_BYPASS__SHIFT                                                  0x8
5604 #define DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR__SHIFT                                                        0x9
5605 #define DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR__SHIFT                                                        0xa
5606 #define DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR__SHIFT                                                        0xb
5607 #define DB_DEBUG4__DISABLE_SEPARATE_DFSM_CLK__SHIFT                                                           0xc
5608 #define DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP__SHIFT                                                   0xd
5609 #define DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION__SHIFT                                              0xe
5610 #define DB_DEBUG4__DISABLE_TS_WRITE_L0__SHIFT                                                                 0xf
5611 #define DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE__SHIFT                                                0x10
5612 #define DB_DEBUG4__DISABLE_HIZ_Q1_TS_COLLISION_DETECT__SHIFT                                                  0x11
5613 #define DB_DEBUG4__DISABLE_HIZ_Q2_TS_COLLISION_DETECT__SHIFT                                                  0x12
5614 #define DB_DEBUG4__DB_EXTRA_DEBUG4__SHIFT                                                                     0x13
5615 #define DB_DEBUG4__DISABLE_8PPC_OBJPRIMID_WHEN_NO_SHADER_EXPORTS__SHIFT                                       0x1e
5616 #define DB_DEBUG4__FULL_TILE_CACHE_EVICT_ON_HALF_FULL__SHIFT                                                  0x1f
5617 #define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION_MASK                                                           0x00000001L
5618 #define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION_MASK                                                     0x00000002L
5619 #define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL_MASK                                                      0x00000004L
5620 #define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK                                               0x00000008L
5621 #define DB_DEBUG4__DISABLE_4XAA_2P_ZD_HOLDOFF_MASK                                                            0x00000010L
5622 #define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION_MASK                                                         0x00000020L
5623 #define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE_MASK                                                      0x00000040L
5624 #define DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN_MASK                                                                  0x00000080L
5625 #define DB_DEBUG4__DFSM_CONVERT_PASSTHROUGH_TO_BYPASS_MASK                                                    0x00000100L
5626 #define DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR_MASK                                                          0x00000200L
5627 #define DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR_MASK                                                          0x00000400L
5628 #define DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR_MASK                                                          0x00000800L
5629 #define DB_DEBUG4__DISABLE_SEPARATE_DFSM_CLK_MASK                                                             0x00001000L
5630 #define DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP_MASK                                                     0x00002000L
5631 #define DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION_MASK                                                0x00004000L
5632 #define DB_DEBUG4__DISABLE_TS_WRITE_L0_MASK                                                                   0x00008000L
5633 #define DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE_MASK                                                  0x00010000L
5634 #define DB_DEBUG4__DISABLE_HIZ_Q1_TS_COLLISION_DETECT_MASK                                                    0x00020000L
5635 #define DB_DEBUG4__DISABLE_HIZ_Q2_TS_COLLISION_DETECT_MASK                                                    0x00040000L
5636 #define DB_DEBUG4__DB_EXTRA_DEBUG4_MASK                                                                       0x3FF80000L
5637 #define DB_DEBUG4__DISABLE_8PPC_OBJPRIMID_WHEN_NO_SHADER_EXPORTS_MASK                                         0x40000000L
5638 #define DB_DEBUG4__FULL_TILE_CACHE_EVICT_ON_HALF_FULL_MASK                                                    0x80000000L
5639 //DB_CREDIT_LIMIT
5640 #define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS__SHIFT                                                            0x0
5641 #define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS__SHIFT                                                            0x5
5642 #define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT                                                           0xa
5643 #define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS__SHIFT                                                            0x18
5644 #define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS_MASK                                                              0x0000001FL
5645 #define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS_MASK                                                              0x000003E0L
5646 #define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS_MASK                                                             0x00001C00L
5647 #define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS_MASK                                                              0x7F000000L
5648 //DB_WATERMARKS
5649 #define DB_WATERMARKS__DEPTH_FREE__SHIFT                                                                      0x0
5650 #define DB_WATERMARKS__DEPTH_FLUSH__SHIFT                                                                     0x5
5651 #define DB_WATERMARKS__FORCE_SUMMARIZE__SHIFT                                                                 0xb
5652 #define DB_WATERMARKS__DEPTH_PENDING_FREE__SHIFT                                                              0xf
5653 #define DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT                                                            0x14
5654 #define DB_WATERMARKS__AUTO_FLUSH_HTILE__SHIFT                                                                0x1e
5655 #define DB_WATERMARKS__AUTO_FLUSH_QUAD__SHIFT                                                                 0x1f
5656 #define DB_WATERMARKS__DEPTH_FREE_MASK                                                                        0x0000001FL
5657 #define DB_WATERMARKS__DEPTH_FLUSH_MASK                                                                       0x000007E0L
5658 #define DB_WATERMARKS__FORCE_SUMMARIZE_MASK                                                                   0x00007800L
5659 #define DB_WATERMARKS__DEPTH_PENDING_FREE_MASK                                                                0x000F8000L
5660 #define DB_WATERMARKS__DEPTH_CACHELINE_FREE_MASK                                                              0x0FF00000L
5661 #define DB_WATERMARKS__AUTO_FLUSH_HTILE_MASK                                                                  0x40000000L
5662 #define DB_WATERMARKS__AUTO_FLUSH_QUAD_MASK                                                                   0x80000000L
5663 //DB_SUBTILE_CONTROL
5664 #define DB_SUBTILE_CONTROL__MSAA1_X__SHIFT                                                                    0x0
5665 #define DB_SUBTILE_CONTROL__MSAA1_Y__SHIFT                                                                    0x2
5666 #define DB_SUBTILE_CONTROL__MSAA2_X__SHIFT                                                                    0x4
5667 #define DB_SUBTILE_CONTROL__MSAA2_Y__SHIFT                                                                    0x6
5668 #define DB_SUBTILE_CONTROL__MSAA4_X__SHIFT                                                                    0x8
5669 #define DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT                                                                    0xa
5670 #define DB_SUBTILE_CONTROL__MSAA8_X__SHIFT                                                                    0xc
5671 #define DB_SUBTILE_CONTROL__MSAA8_Y__SHIFT                                                                    0xe
5672 #define DB_SUBTILE_CONTROL__MSAA16_X__SHIFT                                                                   0x10
5673 #define DB_SUBTILE_CONTROL__MSAA16_Y__SHIFT                                                                   0x12
5674 #define DB_SUBTILE_CONTROL__MSAA1_X_MASK                                                                      0x00000003L
5675 #define DB_SUBTILE_CONTROL__MSAA1_Y_MASK                                                                      0x0000000CL
5676 #define DB_SUBTILE_CONTROL__MSAA2_X_MASK                                                                      0x00000030L
5677 #define DB_SUBTILE_CONTROL__MSAA2_Y_MASK                                                                      0x000000C0L
5678 #define DB_SUBTILE_CONTROL__MSAA4_X_MASK                                                                      0x00000300L
5679 #define DB_SUBTILE_CONTROL__MSAA4_Y_MASK                                                                      0x00000C00L
5680 #define DB_SUBTILE_CONTROL__MSAA8_X_MASK                                                                      0x00003000L
5681 #define DB_SUBTILE_CONTROL__MSAA8_Y_MASK                                                                      0x0000C000L
5682 #define DB_SUBTILE_CONTROL__MSAA16_X_MASK                                                                     0x00030000L
5683 #define DB_SUBTILE_CONTROL__MSAA16_Y_MASK                                                                     0x000C0000L
5684 //DB_FREE_CACHELINES
5685 #define DB_FREE_CACHELINES__FREE_DTILE_DEPTH__SHIFT                                                           0x0
5686 #define DB_FREE_CACHELINES__FREE_PLANE_DEPTH__SHIFT                                                           0x7
5687 #define DB_FREE_CACHELINES__FREE_Z_DEPTH__SHIFT                                                               0xe
5688 #define DB_FREE_CACHELINES__FREE_HTILE_DEPTH__SHIFT                                                           0x14
5689 #define DB_FREE_CACHELINES__QUAD_READ_REQS__SHIFT                                                             0x18
5690 #define DB_FREE_CACHELINES__FREE_DTILE_DEPTH_MASK                                                             0x0000007FL
5691 #define DB_FREE_CACHELINES__FREE_PLANE_DEPTH_MASK                                                             0x00003F80L
5692 #define DB_FREE_CACHELINES__FREE_Z_DEPTH_MASK                                                                 0x000FC000L
5693 #define DB_FREE_CACHELINES__FREE_HTILE_DEPTH_MASK                                                             0x00F00000L
5694 #define DB_FREE_CACHELINES__QUAD_READ_REQS_MASK                                                               0xFF000000L
5695 //DB_FIFO_DEPTH1
5696 #define DB_FIFO_DEPTH1__DB_RMI_RDREQ_CREDITS__SHIFT                                                           0x0
5697 #define DB_FIFO_DEPTH1__DB_RMI_WRREQ_CREDITS__SHIFT                                                           0x5
5698 #define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT                                                                      0xa
5699 #define DB_FIFO_DEPTH1__QC_DEPTH__SHIFT                                                                       0x10
5700 #define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH__SHIFT                                                         0x15
5701 #define DB_FIFO_DEPTH1__DB_RMI_RDREQ_CREDITS_MASK                                                             0x0000001FL
5702 #define DB_FIFO_DEPTH1__DB_RMI_WRREQ_CREDITS_MASK                                                             0x000003E0L
5703 #define DB_FIFO_DEPTH1__MCC_DEPTH_MASK                                                                        0x0000FC00L
5704 #define DB_FIFO_DEPTH1__QC_DEPTH_MASK                                                                         0x001F0000L
5705 #define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH_MASK                                                           0x1FE00000L
5706 //DB_FIFO_DEPTH2
5707 #define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH__SHIFT                                                               0x0
5708 #define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH__SHIFT                                                            0x8
5709 #define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH__SHIFT                                                               0xf
5710 #define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH__SHIFT                                                            0x19
5711 #define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH_MASK                                                                 0x000000FFL
5712 #define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH_MASK                                                              0x00007F00L
5713 #define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH_MASK                                                                 0x01FF8000L
5714 #define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH_MASK                                                              0xFE000000L
5715 //DB_EXCEPTION_CONTROL
5716 #define DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE__SHIFT                                                    0x0
5717 #define DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE__SHIFT                                                     0x1
5718 #define DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE__SHIFT                                                       0x2
5719 #define DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE_MASK                                                      0x00000001L
5720 #define DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE_MASK                                                       0x00000002L
5721 #define DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE_MASK                                                         0x00000004L
5722 //DB_RING_CONTROL
5723 #define DB_RING_CONTROL__COUNTER_CONTROL__SHIFT                                                               0x0
5724 #define DB_RING_CONTROL__COUNTER_CONTROL_MASK                                                                 0x00000003L
5725 //DB_MEM_ARB_WATERMARKS
5726 #define DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK__SHIFT                                                       0x0
5727 #define DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK__SHIFT                                                       0x8
5728 #define DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK__SHIFT                                                       0x10
5729 #define DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK__SHIFT                                                       0x18
5730 #define DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK_MASK                                                         0x00000007L
5731 #define DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK_MASK                                                         0x00000700L
5732 #define DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK_MASK                                                         0x00070000L
5733 #define DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK_MASK                                                         0x07000000L
5734 //DB_RMI_CACHE_POLICY
5735 #define DB_RMI_CACHE_POLICY__Z_RD__SHIFT                                                                      0x0
5736 #define DB_RMI_CACHE_POLICY__S_RD__SHIFT                                                                      0x1
5737 #define DB_RMI_CACHE_POLICY__HTILE_RD__SHIFT                                                                  0x2
5738 #define DB_RMI_CACHE_POLICY__Z_WR__SHIFT                                                                      0x8
5739 #define DB_RMI_CACHE_POLICY__S_WR__SHIFT                                                                      0x9
5740 #define DB_RMI_CACHE_POLICY__HTILE_WR__SHIFT                                                                  0xa
5741 #define DB_RMI_CACHE_POLICY__ZPCPSD_WR__SHIFT                                                                 0xb
5742 #define DB_RMI_CACHE_POLICY__CC_RD__SHIFT                                                                     0x10
5743 #define DB_RMI_CACHE_POLICY__FMASK_RD__SHIFT                                                                  0x11
5744 #define DB_RMI_CACHE_POLICY__CMASK_RD__SHIFT                                                                  0x12
5745 #define DB_RMI_CACHE_POLICY__DCC_RD__SHIFT                                                                    0x13
5746 #define DB_RMI_CACHE_POLICY__CC_WR__SHIFT                                                                     0x18
5747 #define DB_RMI_CACHE_POLICY__FMASK_WR__SHIFT                                                                  0x19
5748 #define DB_RMI_CACHE_POLICY__CMASK_WR__SHIFT                                                                  0x1a
5749 #define DB_RMI_CACHE_POLICY__DCC_WR__SHIFT                                                                    0x1b
5750 #define DB_RMI_CACHE_POLICY__Z_RD_MASK                                                                        0x00000001L
5751 #define DB_RMI_CACHE_POLICY__S_RD_MASK                                                                        0x00000002L
5752 #define DB_RMI_CACHE_POLICY__HTILE_RD_MASK                                                                    0x00000004L
5753 #define DB_RMI_CACHE_POLICY__Z_WR_MASK                                                                        0x00000100L
5754 #define DB_RMI_CACHE_POLICY__S_WR_MASK                                                                        0x00000200L
5755 #define DB_RMI_CACHE_POLICY__HTILE_WR_MASK                                                                    0x00000400L
5756 #define DB_RMI_CACHE_POLICY__ZPCPSD_WR_MASK                                                                   0x00000800L
5757 #define DB_RMI_CACHE_POLICY__CC_RD_MASK                                                                       0x00010000L
5758 #define DB_RMI_CACHE_POLICY__FMASK_RD_MASK                                                                    0x00020000L
5759 #define DB_RMI_CACHE_POLICY__CMASK_RD_MASK                                                                    0x00040000L
5760 #define DB_RMI_CACHE_POLICY__DCC_RD_MASK                                                                      0x00080000L
5761 #define DB_RMI_CACHE_POLICY__CC_WR_MASK                                                                       0x01000000L
5762 #define DB_RMI_CACHE_POLICY__FMASK_WR_MASK                                                                    0x02000000L
5763 #define DB_RMI_CACHE_POLICY__CMASK_WR_MASK                                                                    0x04000000L
5764 #define DB_RMI_CACHE_POLICY__DCC_WR_MASK                                                                      0x08000000L
5765 //DB_DFSM_CONFIG
5766 #define DB_DFSM_CONFIG__BYPASS_DFSM__SHIFT                                                                    0x0
5767 #define DB_DFSM_CONFIG__DISABLE_PUNCHOUT__SHIFT                                                               0x1
5768 #define DB_DFSM_CONFIG__DISABLE_POPS__SHIFT                                                                   0x2
5769 #define DB_DFSM_CONFIG__FORCE_FLUSH__SHIFT                                                                    0x3
5770 #define DB_DFSM_CONFIG__MIDDLE_PIPE_MAX_DEPTH__SHIFT                                                          0x8
5771 #define DB_DFSM_CONFIG__BYPASS_DFSM_MASK                                                                      0x00000001L
5772 #define DB_DFSM_CONFIG__DISABLE_PUNCHOUT_MASK                                                                 0x00000002L
5773 #define DB_DFSM_CONFIG__DISABLE_POPS_MASK                                                                     0x00000004L
5774 #define DB_DFSM_CONFIG__FORCE_FLUSH_MASK                                                                      0x00000008L
5775 #define DB_DFSM_CONFIG__MIDDLE_PIPE_MAX_DEPTH_MASK                                                            0x00007F00L
5776 //DB_DFSM_WATERMARK
5777 #define DB_DFSM_WATERMARK__DFSM_HIGH_WATERMARK__SHIFT                                                         0x0
5778 #define DB_DFSM_WATERMARK__POPS_HIGH_WATERMARK__SHIFT                                                         0x10
5779 #define DB_DFSM_WATERMARK__DFSM_HIGH_WATERMARK_MASK                                                           0x0000FFFFL
5780 #define DB_DFSM_WATERMARK__POPS_HIGH_WATERMARK_MASK                                                           0xFFFF0000L
5781 //DB_DFSM_TILES_IN_FLIGHT
5782 #define DB_DFSM_TILES_IN_FLIGHT__HIGH_WATERMARK__SHIFT                                                        0x0
5783 #define DB_DFSM_TILES_IN_FLIGHT__HARD_LIMIT__SHIFT                                                            0x10
5784 #define DB_DFSM_TILES_IN_FLIGHT__HIGH_WATERMARK_MASK                                                          0x0000FFFFL
5785 #define DB_DFSM_TILES_IN_FLIGHT__HARD_LIMIT_MASK                                                              0xFFFF0000L
5786 //DB_DFSM_PRIMS_IN_FLIGHT
5787 #define DB_DFSM_PRIMS_IN_FLIGHT__HIGH_WATERMARK__SHIFT                                                        0x0
5788 #define DB_DFSM_PRIMS_IN_FLIGHT__HARD_LIMIT__SHIFT                                                            0x10
5789 #define DB_DFSM_PRIMS_IN_FLIGHT__HIGH_WATERMARK_MASK                                                          0x0000FFFFL
5790 #define DB_DFSM_PRIMS_IN_FLIGHT__HARD_LIMIT_MASK                                                              0xFFFF0000L
5791 //DB_DFSM_WATCHDOG
5792 #define DB_DFSM_WATCHDOG__TIMER_TARGET__SHIFT                                                                 0x0
5793 #define DB_DFSM_WATCHDOG__TIMER_TARGET_MASK                                                                   0xFFFFFFFFL
5794 //DB_DFSM_FLUSH_ENABLE
5795 #define DB_DFSM_FLUSH_ENABLE__PRIMARY_EVENTS__SHIFT                                                           0x0
5796 #define DB_DFSM_FLUSH_ENABLE__AUX_FORCE_PASSTHRU__SHIFT                                                       0x18
5797 #define DB_DFSM_FLUSH_ENABLE__AUX_EVENTS__SHIFT                                                               0x1c
5798 #define DB_DFSM_FLUSH_ENABLE__PRIMARY_EVENTS_MASK                                                             0x000003FFL
5799 #define DB_DFSM_FLUSH_ENABLE__AUX_FORCE_PASSTHRU_MASK                                                         0x0F000000L
5800 #define DB_DFSM_FLUSH_ENABLE__AUX_EVENTS_MASK                                                                 0xF0000000L
5801 //DB_DFSM_FLUSH_AUX_EVENT
5802 #define DB_DFSM_FLUSH_AUX_EVENT__EVENT_A__SHIFT                                                               0x0
5803 #define DB_DFSM_FLUSH_AUX_EVENT__EVENT_B__SHIFT                                                               0x8
5804 #define DB_DFSM_FLUSH_AUX_EVENT__EVENT_C__SHIFT                                                               0x10
5805 #define DB_DFSM_FLUSH_AUX_EVENT__EVENT_D__SHIFT                                                               0x18
5806 #define DB_DFSM_FLUSH_AUX_EVENT__EVENT_A_MASK                                                                 0x000000FFL
5807 #define DB_DFSM_FLUSH_AUX_EVENT__EVENT_B_MASK                                                                 0x0000FF00L
5808 #define DB_DFSM_FLUSH_AUX_EVENT__EVENT_C_MASK                                                                 0x00FF0000L
5809 #define DB_DFSM_FLUSH_AUX_EVENT__EVENT_D_MASK                                                                 0xFF000000L
5810 //CC_RB_REDUNDANCY
5811 #define CC_RB_REDUNDANCY__WRITE_DIS__SHIFT                                                                    0x0
5812 #define CC_RB_REDUNDANCY__FAILED_RB0__SHIFT                                                                   0x8
5813 #define CC_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT                                                               0xc
5814 #define CC_RB_REDUNDANCY__FAILED_RB1__SHIFT                                                                   0x10
5815 #define CC_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT                                                               0x14
5816 #define CC_RB_REDUNDANCY__WRITE_DIS_MASK                                                                      0x00000001L
5817 #define CC_RB_REDUNDANCY__FAILED_RB0_MASK                                                                     0x00000F00L
5818 #define CC_RB_REDUNDANCY__EN_REDUNDANCY0_MASK                                                                 0x00001000L
5819 #define CC_RB_REDUNDANCY__FAILED_RB1_MASK                                                                     0x000F0000L
5820 #define CC_RB_REDUNDANCY__EN_REDUNDANCY1_MASK                                                                 0x00100000L
5821 //CC_RB_BACKEND_DISABLE
5822 #define CC_RB_BACKEND_DISABLE__WRITE_DIS__SHIFT                                                               0x0
5823 #define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT                                                         0x10
5824 #define CC_RB_BACKEND_DISABLE__WRITE_DIS_MASK                                                                 0x00000001L
5825 #define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK                                                           0x00FF0000L
5826 //GB_ADDR_CONFIG
5827 #define GB_ADDR_CONFIG__NUM_PIPES__SHIFT                                                                      0x0
5828 #define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT                                                           0x3
5829 #define GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                           0x6
5830 #define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT                                                           0x8
5831 #define GB_ADDR_CONFIG__NUM_BANKS__SHIFT                                                                      0xc
5832 #define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT                                                        0x10
5833 #define GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT                                                             0x13
5834 #define GB_ADDR_CONFIG__NUM_GPUS__SHIFT                                                                       0x15
5835 #define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT                                                            0x18
5836 #define GB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT                                                                  0x1a
5837 #define GB_ADDR_CONFIG__ROW_SIZE__SHIFT                                                                       0x1c
5838 #define GB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT                                                                0x1e
5839 #define GB_ADDR_CONFIG__SE_ENABLE__SHIFT                                                                      0x1f
5840 #define GB_ADDR_CONFIG__NUM_PIPES_MASK                                                                        0x00000007L
5841 #define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK                                                             0x00000038L
5842 #define GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                             0x000000C0L
5843 #define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK                                                             0x00000700L
5844 #define GB_ADDR_CONFIG__NUM_BANKS_MASK                                                                        0x00007000L
5845 #define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK                                                          0x00070000L
5846 #define GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK                                                               0x00180000L
5847 #define GB_ADDR_CONFIG__NUM_GPUS_MASK                                                                         0x00E00000L
5848 #define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK                                                              0x03000000L
5849 #define GB_ADDR_CONFIG__NUM_RB_PER_SE_MASK                                                                    0x0C000000L
5850 #define GB_ADDR_CONFIG__ROW_SIZE_MASK                                                                         0x30000000L
5851 #define GB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK                                                                  0x40000000L
5852 #define GB_ADDR_CONFIG__SE_ENABLE_MASK                                                                        0x80000000L
5853 //GB_BACKEND_MAP
5854 #define GB_BACKEND_MAP__BACKEND_MAP__SHIFT                                                                    0x0
5855 #define GB_BACKEND_MAP__BACKEND_MAP_MASK                                                                      0xFFFFFFFFL
5856 //GB_GPU_ID
5857 #define GB_GPU_ID__GPU_ID__SHIFT                                                                              0x0
5858 #define GB_GPU_ID__GPU_ID_MASK                                                                                0x0000000FL
5859 //CC_RB_DAISY_CHAIN
5860 #define CC_RB_DAISY_CHAIN__RB_0__SHIFT                                                                        0x0
5861 #define CC_RB_DAISY_CHAIN__RB_1__SHIFT                                                                        0x4
5862 #define CC_RB_DAISY_CHAIN__RB_2__SHIFT                                                                        0x8
5863 #define CC_RB_DAISY_CHAIN__RB_3__SHIFT                                                                        0xc
5864 #define CC_RB_DAISY_CHAIN__RB_4__SHIFT                                                                        0x10
5865 #define CC_RB_DAISY_CHAIN__RB_5__SHIFT                                                                        0x14
5866 #define CC_RB_DAISY_CHAIN__RB_6__SHIFT                                                                        0x18
5867 #define CC_RB_DAISY_CHAIN__RB_7__SHIFT                                                                        0x1c
5868 #define CC_RB_DAISY_CHAIN__RB_0_MASK                                                                          0x0000000FL
5869 #define CC_RB_DAISY_CHAIN__RB_1_MASK                                                                          0x000000F0L
5870 #define CC_RB_DAISY_CHAIN__RB_2_MASK                                                                          0x00000F00L
5871 #define CC_RB_DAISY_CHAIN__RB_3_MASK                                                                          0x0000F000L
5872 #define CC_RB_DAISY_CHAIN__RB_4_MASK                                                                          0x000F0000L
5873 #define CC_RB_DAISY_CHAIN__RB_5_MASK                                                                          0x00F00000L
5874 #define CC_RB_DAISY_CHAIN__RB_6_MASK                                                                          0x0F000000L
5875 #define CC_RB_DAISY_CHAIN__RB_7_MASK                                                                          0xF0000000L
5876 //GB_ADDR_CONFIG_READ
5877 #define GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT                                                                 0x0
5878 #define GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT                                                      0x3
5879 #define GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT                                                      0x6
5880 #define GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT                                                      0x8
5881 #define GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT                                                                 0xc
5882 #define GB_ADDR_CONFIG_READ__SHADER_ENGINE_TILE_SIZE__SHIFT                                                   0x10
5883 #define GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT                                                        0x13
5884 #define GB_ADDR_CONFIG_READ__NUM_GPUS__SHIFT                                                                  0x15
5885 #define GB_ADDR_CONFIG_READ__MULTI_GPU_TILE_SIZE__SHIFT                                                       0x18
5886 #define GB_ADDR_CONFIG_READ__NUM_RB_PER_SE__SHIFT                                                             0x1a
5887 #define GB_ADDR_CONFIG_READ__ROW_SIZE__SHIFT                                                                  0x1c
5888 #define GB_ADDR_CONFIG_READ__NUM_LOWER_PIPES__SHIFT                                                           0x1e
5889 #define GB_ADDR_CONFIG_READ__SE_ENABLE__SHIFT                                                                 0x1f
5890 #define GB_ADDR_CONFIG_READ__NUM_PIPES_MASK                                                                   0x00000007L
5891 #define GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK                                                        0x00000038L
5892 #define GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK                                                        0x000000C0L
5893 #define GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK                                                        0x00000700L
5894 #define GB_ADDR_CONFIG_READ__NUM_BANKS_MASK                                                                   0x00007000L
5895 #define GB_ADDR_CONFIG_READ__SHADER_ENGINE_TILE_SIZE_MASK                                                     0x00070000L
5896 #define GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK                                                          0x00180000L
5897 #define GB_ADDR_CONFIG_READ__NUM_GPUS_MASK                                                                    0x00E00000L
5898 #define GB_ADDR_CONFIG_READ__MULTI_GPU_TILE_SIZE_MASK                                                         0x03000000L
5899 #define GB_ADDR_CONFIG_READ__NUM_RB_PER_SE_MASK                                                               0x0C000000L
5900 #define GB_ADDR_CONFIG_READ__ROW_SIZE_MASK                                                                    0x30000000L
5901 #define GB_ADDR_CONFIG_READ__NUM_LOWER_PIPES_MASK                                                             0x40000000L
5902 #define GB_ADDR_CONFIG_READ__SE_ENABLE_MASK                                                                   0x80000000L
5903 //GB_TILE_MODE0
5904 #define GB_TILE_MODE0__ARRAY_MODE__SHIFT                                                                      0x2
5905 #define GB_TILE_MODE0__PIPE_CONFIG__SHIFT                                                                     0x6
5906 #define GB_TILE_MODE0__TILE_SPLIT__SHIFT                                                                      0xb
5907 #define GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT                                                             0x16
5908 #define GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT                                                                    0x19
5909 #define GB_TILE_MODE0__ARRAY_MODE_MASK                                                                        0x0000003CL
5910 #define GB_TILE_MODE0__PIPE_CONFIG_MASK                                                                       0x000007C0L
5911 #define GB_TILE_MODE0__TILE_SPLIT_MASK                                                                        0x00003800L
5912 #define GB_TILE_MODE0__MICRO_TILE_MODE_NEW_MASK                                                               0x01C00000L
5913 #define GB_TILE_MODE0__SAMPLE_SPLIT_MASK                                                                      0x06000000L
5914 //GB_TILE_MODE1
5915 #define GB_TILE_MODE1__ARRAY_MODE__SHIFT                                                                      0x2
5916 #define GB_TILE_MODE1__PIPE_CONFIG__SHIFT                                                                     0x6
5917 #define GB_TILE_MODE1__TILE_SPLIT__SHIFT                                                                      0xb
5918 #define GB_TILE_MODE1__MICRO_TILE_MODE_NEW__SHIFT                                                             0x16
5919 #define GB_TILE_MODE1__SAMPLE_SPLIT__SHIFT                                                                    0x19
5920 #define GB_TILE_MODE1__ARRAY_MODE_MASK                                                                        0x0000003CL
5921 #define GB_TILE_MODE1__PIPE_CONFIG_MASK                                                                       0x000007C0L
5922 #define GB_TILE_MODE1__TILE_SPLIT_MASK                                                                        0x00003800L
5923 #define GB_TILE_MODE1__MICRO_TILE_MODE_NEW_MASK                                                               0x01C00000L
5924 #define GB_TILE_MODE1__SAMPLE_SPLIT_MASK                                                                      0x06000000L
5925 //GB_TILE_MODE2
5926 #define GB_TILE_MODE2__ARRAY_MODE__SHIFT                                                                      0x2
5927 #define GB_TILE_MODE2__PIPE_CONFIG__SHIFT                                                                     0x6
5928 #define GB_TILE_MODE2__TILE_SPLIT__SHIFT                                                                      0xb
5929 #define GB_TILE_MODE2__MICRO_TILE_MODE_NEW__SHIFT                                                             0x16
5930 #define GB_TILE_MODE2__SAMPLE_SPLIT__SHIFT                                                                    0x19
5931 #define GB_TILE_MODE2__ARRAY_MODE_MASK                                                                        0x0000003CL
5932 #define GB_TILE_MODE2__PIPE_CONFIG_MASK                                                                       0x000007C0L
5933 #define GB_TILE_MODE2__TILE_SPLIT_MASK                                                                        0x00003800L
5934 #define GB_TILE_MODE2__MICRO_TILE_MODE_NEW_MASK                                                               0x01C00000L
5935 #define GB_TILE_MODE2__SAMPLE_SPLIT_MASK                                                                      0x06000000L
5936 //GB_TILE_MODE3
5937 #define GB_TILE_MODE3__ARRAY_MODE__SHIFT                                                                      0x2
5938 #define GB_TILE_MODE3__PIPE_CONFIG__SHIFT                                                                     0x6
5939 #define GB_TILE_MODE3__TILE_SPLIT__SHIFT                                                                      0xb
5940 #define GB_TILE_MODE3__MICRO_TILE_MODE_NEW__SHIFT                                                             0x16
5941 #define GB_TILE_MODE3__SAMPLE_SPLIT__SHIFT                                                                    0x19
5942 #define GB_TILE_MODE3__ARRAY_MODE_MASK                                                                        0x0000003CL
5943 #define GB_TILE_MODE3__PIPE_CONFIG_MASK                                                                       0x000007C0L
5944 #define GB_TILE_MODE3__TILE_SPLIT_MASK                                                                        0x00003800L
5945 #define GB_TILE_MODE3__MICRO_TILE_MODE_NEW_MASK                                                               0x01C00000L
5946 #define GB_TILE_MODE3__SAMPLE_SPLIT_MASK                                                                      0x06000000L
5947 //GB_TILE_MODE4
5948 #define GB_TILE_MODE4__ARRAY_MODE__SHIFT                                                                      0x2
5949 #define GB_TILE_MODE4__PIPE_CONFIG__SHIFT                                                                     0x6
5950 #define GB_TILE_MODE4__TILE_SPLIT__SHIFT                                                                      0xb
5951 #define GB_TILE_MODE4__MICRO_TILE_MODE_NEW__SHIFT                                                             0x16
5952 #define GB_TILE_MODE4__SAMPLE_SPLIT__SHIFT                                                                    0x19
5953 #define GB_TILE_MODE4__ARRAY_MODE_MASK                                                                        0x0000003CL
5954 #define GB_TILE_MODE4__PIPE_CONFIG_MASK                                                                       0x000007C0L
5955 #define GB_TILE_MODE4__TILE_SPLIT_MASK                                                                        0x00003800L
5956 #define GB_TILE_MODE4__MICRO_TILE_MODE_NEW_MASK                                                               0x01C00000L
5957 #define GB_TILE_MODE4__SAMPLE_SPLIT_MASK                                                                      0x06000000L
5958 //GB_TILE_MODE5
5959 #define GB_TILE_MODE5__ARRAY_MODE__SHIFT                                                                      0x2
5960 #define GB_TILE_MODE5__PIPE_CONFIG__SHIFT                                                                     0x6
5961 #define GB_TILE_MODE5__TILE_SPLIT__SHIFT                                                                      0xb
5962 #define GB_TILE_MODE5__MICRO_TILE_MODE_NEW__SHIFT                                                             0x16
5963 #define GB_TILE_MODE5__SAMPLE_SPLIT__SHIFT                                                                    0x19
5964 #define GB_TILE_MODE5__ARRAY_MODE_MASK                                                                        0x0000003CL
5965 #define GB_TILE_MODE5__PIPE_CONFIG_MASK                                                                       0x000007C0L
5966 #define GB_TILE_MODE5__TILE_SPLIT_MASK                                                                        0x00003800L
5967 #define GB_TILE_MODE5__MICRO_TILE_MODE_NEW_MASK                                                               0x01C00000L
5968 #define GB_TILE_MODE5__SAMPLE_SPLIT_MASK                                                                      0x06000000L
5969 //GB_TILE_MODE6
5970 #define GB_TILE_MODE6__ARRAY_MODE__SHIFT                                                                      0x2
5971 #define GB_TILE_MODE6__PIPE_CONFIG__SHIFT                                                                     0x6
5972 #define GB_TILE_MODE6__TILE_SPLIT__SHIFT                                                                      0xb
5973 #define GB_TILE_MODE6__MICRO_TILE_MODE_NEW__SHIFT                                                             0x16
5974 #define GB_TILE_MODE6__SAMPLE_SPLIT__SHIFT                                                                    0x19
5975 #define GB_TILE_MODE6__ARRAY_MODE_MASK                                                                        0x0000003CL
5976 #define GB_TILE_MODE6__PIPE_CONFIG_MASK                                                                       0x000007C0L
5977 #define GB_TILE_MODE6__TILE_SPLIT_MASK                                                                        0x00003800L
5978 #define GB_TILE_MODE6__MICRO_TILE_MODE_NEW_MASK                                                               0x01C00000L
5979 #define GB_TILE_MODE6__SAMPLE_SPLIT_MASK                                                                      0x06000000L
5980 //GB_TILE_MODE7
5981 #define GB_TILE_MODE7__ARRAY_MODE__SHIFT                                                                      0x2
5982 #define GB_TILE_MODE7__PIPE_CONFIG__SHIFT                                                                     0x6
5983 #define GB_TILE_MODE7__TILE_SPLIT__SHIFT                                                                      0xb
5984 #define GB_TILE_MODE7__MICRO_TILE_MODE_NEW__SHIFT                                                             0x16
5985 #define GB_TILE_MODE7__SAMPLE_SPLIT__SHIFT                                                                    0x19
5986 #define GB_TILE_MODE7__ARRAY_MODE_MASK                                                                        0x0000003CL
5987 #define GB_TILE_MODE7__PIPE_CONFIG_MASK                                                                       0x000007C0L
5988 #define GB_TILE_MODE7__TILE_SPLIT_MASK                                                                        0x00003800L
5989 #define GB_TILE_MODE7__MICRO_TILE_MODE_NEW_MASK                                                               0x01C00000L
5990 #define GB_TILE_MODE7__SAMPLE_SPLIT_MASK                                                                      0x06000000L
5991 //GB_TILE_MODE8
5992 #define GB_TILE_MODE8__ARRAY_MODE__SHIFT                                                                      0x2
5993 #define GB_TILE_MODE8__PIPE_CONFIG__SHIFT                                                                     0x6
5994 #define GB_TILE_MODE8__TILE_SPLIT__SHIFT                                                                      0xb
5995 #define GB_TILE_MODE8__MICRO_TILE_MODE_NEW__SHIFT                                                             0x16
5996 #define GB_TILE_MODE8__SAMPLE_SPLIT__SHIFT                                                                    0x19
5997 #define GB_TILE_MODE8__ARRAY_MODE_MASK                                                                        0x0000003CL
5998 #define GB_TILE_MODE8__PIPE_CONFIG_MASK                                                                       0x000007C0L
5999 #define GB_TILE_MODE8__TILE_SPLIT_MASK                                                                        0x00003800L
6000 #define GB_TILE_MODE8__MICRO_TILE_MODE_NEW_MASK                                                               0x01C00000L
6001 #define GB_TILE_MODE8__SAMPLE_SPLIT_MASK                                                                      0x06000000L
6002 //GB_TILE_MODE9
6003 #define GB_TILE_MODE9__ARRAY_MODE__SHIFT                                                                      0x2
6004 #define GB_TILE_MODE9__PIPE_CONFIG__SHIFT                                                                     0x6
6005 #define GB_TILE_MODE9__TILE_SPLIT__SHIFT                                                                      0xb
6006 #define GB_TILE_MODE9__MICRO_TILE_MODE_NEW__SHIFT                                                             0x16
6007 #define GB_TILE_MODE9__SAMPLE_SPLIT__SHIFT                                                                    0x19
6008 #define GB_TILE_MODE9__ARRAY_MODE_MASK                                                                        0x0000003CL
6009 #define GB_TILE_MODE9__PIPE_CONFIG_MASK                                                                       0x000007C0L
6010 #define GB_TILE_MODE9__TILE_SPLIT_MASK                                                                        0x00003800L
6011 #define GB_TILE_MODE9__MICRO_TILE_MODE_NEW_MASK                                                               0x01C00000L
6012 #define GB_TILE_MODE9__SAMPLE_SPLIT_MASK                                                                      0x06000000L
6013 //GB_TILE_MODE10
6014 #define GB_TILE_MODE10__ARRAY_MODE__SHIFT                                                                     0x2
6015 #define GB_TILE_MODE10__PIPE_CONFIG__SHIFT                                                                    0x6
6016 #define GB_TILE_MODE10__TILE_SPLIT__SHIFT                                                                     0xb
6017 #define GB_TILE_MODE10__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
6018 #define GB_TILE_MODE10__SAMPLE_SPLIT__SHIFT                                                                   0x19
6019 #define GB_TILE_MODE10__ARRAY_MODE_MASK                                                                       0x0000003CL
6020 #define GB_TILE_MODE10__PIPE_CONFIG_MASK                                                                      0x000007C0L
6021 #define GB_TILE_MODE10__TILE_SPLIT_MASK                                                                       0x00003800L
6022 #define GB_TILE_MODE10__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
6023 #define GB_TILE_MODE10__SAMPLE_SPLIT_MASK                                                                     0x06000000L
6024 //GB_TILE_MODE11
6025 #define GB_TILE_MODE11__ARRAY_MODE__SHIFT                                                                     0x2
6026 #define GB_TILE_MODE11__PIPE_CONFIG__SHIFT                                                                    0x6
6027 #define GB_TILE_MODE11__TILE_SPLIT__SHIFT                                                                     0xb
6028 #define GB_TILE_MODE11__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
6029 #define GB_TILE_MODE11__SAMPLE_SPLIT__SHIFT                                                                   0x19
6030 #define GB_TILE_MODE11__ARRAY_MODE_MASK                                                                       0x0000003CL
6031 #define GB_TILE_MODE11__PIPE_CONFIG_MASK                                                                      0x000007C0L
6032 #define GB_TILE_MODE11__TILE_SPLIT_MASK                                                                       0x00003800L
6033 #define GB_TILE_MODE11__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
6034 #define GB_TILE_MODE11__SAMPLE_SPLIT_MASK                                                                     0x06000000L
6035 //GB_TILE_MODE12
6036 #define GB_TILE_MODE12__ARRAY_MODE__SHIFT                                                                     0x2
6037 #define GB_TILE_MODE12__PIPE_CONFIG__SHIFT                                                                    0x6
6038 #define GB_TILE_MODE12__TILE_SPLIT__SHIFT                                                                     0xb
6039 #define GB_TILE_MODE12__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
6040 #define GB_TILE_MODE12__SAMPLE_SPLIT__SHIFT                                                                   0x19
6041 #define GB_TILE_MODE12__ARRAY_MODE_MASK                                                                       0x0000003CL
6042 #define GB_TILE_MODE12__PIPE_CONFIG_MASK                                                                      0x000007C0L
6043 #define GB_TILE_MODE12__TILE_SPLIT_MASK                                                                       0x00003800L
6044 #define GB_TILE_MODE12__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
6045 #define GB_TILE_MODE12__SAMPLE_SPLIT_MASK                                                                     0x06000000L
6046 //GB_TILE_MODE13
6047 #define GB_TILE_MODE13__ARRAY_MODE__SHIFT                                                                     0x2
6048 #define GB_TILE_MODE13__PIPE_CONFIG__SHIFT                                                                    0x6
6049 #define GB_TILE_MODE13__TILE_SPLIT__SHIFT                                                                     0xb
6050 #define GB_TILE_MODE13__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
6051 #define GB_TILE_MODE13__SAMPLE_SPLIT__SHIFT                                                                   0x19
6052 #define GB_TILE_MODE13__ARRAY_MODE_MASK                                                                       0x0000003CL
6053 #define GB_TILE_MODE13__PIPE_CONFIG_MASK                                                                      0x000007C0L
6054 #define GB_TILE_MODE13__TILE_SPLIT_MASK                                                                       0x00003800L
6055 #define GB_TILE_MODE13__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
6056 #define GB_TILE_MODE13__SAMPLE_SPLIT_MASK                                                                     0x06000000L
6057 //GB_TILE_MODE14
6058 #define GB_TILE_MODE14__ARRAY_MODE__SHIFT                                                                     0x2
6059 #define GB_TILE_MODE14__PIPE_CONFIG__SHIFT                                                                    0x6
6060 #define GB_TILE_MODE14__TILE_SPLIT__SHIFT                                                                     0xb
6061 #define GB_TILE_MODE14__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
6062 #define GB_TILE_MODE14__SAMPLE_SPLIT__SHIFT                                                                   0x19
6063 #define GB_TILE_MODE14__ARRAY_MODE_MASK                                                                       0x0000003CL
6064 #define GB_TILE_MODE14__PIPE_CONFIG_MASK                                                                      0x000007C0L
6065 #define GB_TILE_MODE14__TILE_SPLIT_MASK                                                                       0x00003800L
6066 #define GB_TILE_MODE14__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
6067 #define GB_TILE_MODE14__SAMPLE_SPLIT_MASK                                                                     0x06000000L
6068 //GB_TILE_MODE15
6069 #define GB_TILE_MODE15__ARRAY_MODE__SHIFT                                                                     0x2
6070 #define GB_TILE_MODE15__PIPE_CONFIG__SHIFT                                                                    0x6
6071 #define GB_TILE_MODE15__TILE_SPLIT__SHIFT                                                                     0xb
6072 #define GB_TILE_MODE15__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
6073 #define GB_TILE_MODE15__SAMPLE_SPLIT__SHIFT                                                                   0x19
6074 #define GB_TILE_MODE15__ARRAY_MODE_MASK                                                                       0x0000003CL
6075 #define GB_TILE_MODE15__PIPE_CONFIG_MASK                                                                      0x000007C0L
6076 #define GB_TILE_MODE15__TILE_SPLIT_MASK                                                                       0x00003800L
6077 #define GB_TILE_MODE15__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
6078 #define GB_TILE_MODE15__SAMPLE_SPLIT_MASK                                                                     0x06000000L
6079 //GB_TILE_MODE16
6080 #define GB_TILE_MODE16__ARRAY_MODE__SHIFT                                                                     0x2
6081 #define GB_TILE_MODE16__PIPE_CONFIG__SHIFT                                                                    0x6
6082 #define GB_TILE_MODE16__TILE_SPLIT__SHIFT                                                                     0xb
6083 #define GB_TILE_MODE16__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
6084 #define GB_TILE_MODE16__SAMPLE_SPLIT__SHIFT                                                                   0x19
6085 #define GB_TILE_MODE16__ARRAY_MODE_MASK                                                                       0x0000003CL
6086 #define GB_TILE_MODE16__PIPE_CONFIG_MASK                                                                      0x000007C0L
6087 #define GB_TILE_MODE16__TILE_SPLIT_MASK                                                                       0x00003800L
6088 #define GB_TILE_MODE16__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
6089 #define GB_TILE_MODE16__SAMPLE_SPLIT_MASK                                                                     0x06000000L
6090 //GB_TILE_MODE17
6091 #define GB_TILE_MODE17__ARRAY_MODE__SHIFT                                                                     0x2
6092 #define GB_TILE_MODE17__PIPE_CONFIG__SHIFT                                                                    0x6
6093 #define GB_TILE_MODE17__TILE_SPLIT__SHIFT                                                                     0xb
6094 #define GB_TILE_MODE17__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
6095 #define GB_TILE_MODE17__SAMPLE_SPLIT__SHIFT                                                                   0x19
6096 #define GB_TILE_MODE17__ARRAY_MODE_MASK                                                                       0x0000003CL
6097 #define GB_TILE_MODE17__PIPE_CONFIG_MASK                                                                      0x000007C0L
6098 #define GB_TILE_MODE17__TILE_SPLIT_MASK                                                                       0x00003800L
6099 #define GB_TILE_MODE17__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
6100 #define GB_TILE_MODE17__SAMPLE_SPLIT_MASK                                                                     0x06000000L
6101 //GB_TILE_MODE18
6102 #define GB_TILE_MODE18__ARRAY_MODE__SHIFT                                                                     0x2
6103 #define GB_TILE_MODE18__PIPE_CONFIG__SHIFT                                                                    0x6
6104 #define GB_TILE_MODE18__TILE_SPLIT__SHIFT                                                                     0xb
6105 #define GB_TILE_MODE18__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
6106 #define GB_TILE_MODE18__SAMPLE_SPLIT__SHIFT                                                                   0x19
6107 #define GB_TILE_MODE18__ARRAY_MODE_MASK                                                                       0x0000003CL
6108 #define GB_TILE_MODE18__PIPE_CONFIG_MASK                                                                      0x000007C0L
6109 #define GB_TILE_MODE18__TILE_SPLIT_MASK                                                                       0x00003800L
6110 #define GB_TILE_MODE18__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
6111 #define GB_TILE_MODE18__SAMPLE_SPLIT_MASK                                                                     0x06000000L
6112 //GB_TILE_MODE19
6113 #define GB_TILE_MODE19__ARRAY_MODE__SHIFT                                                                     0x2
6114 #define GB_TILE_MODE19__PIPE_CONFIG__SHIFT                                                                    0x6
6115 #define GB_TILE_MODE19__TILE_SPLIT__SHIFT                                                                     0xb
6116 #define GB_TILE_MODE19__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
6117 #define GB_TILE_MODE19__SAMPLE_SPLIT__SHIFT                                                                   0x19
6118 #define GB_TILE_MODE19__ARRAY_MODE_MASK                                                                       0x0000003CL
6119 #define GB_TILE_MODE19__PIPE_CONFIG_MASK                                                                      0x000007C0L
6120 #define GB_TILE_MODE19__TILE_SPLIT_MASK                                                                       0x00003800L
6121 #define GB_TILE_MODE19__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
6122 #define GB_TILE_MODE19__SAMPLE_SPLIT_MASK                                                                     0x06000000L
6123 //GB_TILE_MODE20
6124 #define GB_TILE_MODE20__ARRAY_MODE__SHIFT                                                                     0x2
6125 #define GB_TILE_MODE20__PIPE_CONFIG__SHIFT                                                                    0x6
6126 #define GB_TILE_MODE20__TILE_SPLIT__SHIFT                                                                     0xb
6127 #define GB_TILE_MODE20__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
6128 #define GB_TILE_MODE20__SAMPLE_SPLIT__SHIFT                                                                   0x19
6129 #define GB_TILE_MODE20__ARRAY_MODE_MASK                                                                       0x0000003CL
6130 #define GB_TILE_MODE20__PIPE_CONFIG_MASK                                                                      0x000007C0L
6131 #define GB_TILE_MODE20__TILE_SPLIT_MASK                                                                       0x00003800L
6132 #define GB_TILE_MODE20__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
6133 #define GB_TILE_MODE20__SAMPLE_SPLIT_MASK                                                                     0x06000000L
6134 //GB_TILE_MODE21
6135 #define GB_TILE_MODE21__ARRAY_MODE__SHIFT                                                                     0x2
6136 #define GB_TILE_MODE21__PIPE_CONFIG__SHIFT                                                                    0x6
6137 #define GB_TILE_MODE21__TILE_SPLIT__SHIFT                                                                     0xb
6138 #define GB_TILE_MODE21__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
6139 #define GB_TILE_MODE21__SAMPLE_SPLIT__SHIFT                                                                   0x19
6140 #define GB_TILE_MODE21__ARRAY_MODE_MASK                                                                       0x0000003CL
6141 #define GB_TILE_MODE21__PIPE_CONFIG_MASK                                                                      0x000007C0L
6142 #define GB_TILE_MODE21__TILE_SPLIT_MASK                                                                       0x00003800L
6143 #define GB_TILE_MODE21__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
6144 #define GB_TILE_MODE21__SAMPLE_SPLIT_MASK                                                                     0x06000000L
6145 //GB_TILE_MODE22
6146 #define GB_TILE_MODE22__ARRAY_MODE__SHIFT                                                                     0x2
6147 #define GB_TILE_MODE22__PIPE_CONFIG__SHIFT                                                                    0x6
6148 #define GB_TILE_MODE22__TILE_SPLIT__SHIFT                                                                     0xb
6149 #define GB_TILE_MODE22__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
6150 #define GB_TILE_MODE22__SAMPLE_SPLIT__SHIFT                                                                   0x19
6151 #define GB_TILE_MODE22__ARRAY_MODE_MASK                                                                       0x0000003CL
6152 #define GB_TILE_MODE22__PIPE_CONFIG_MASK                                                                      0x000007C0L
6153 #define GB_TILE_MODE22__TILE_SPLIT_MASK                                                                       0x00003800L
6154 #define GB_TILE_MODE22__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
6155 #define GB_TILE_MODE22__SAMPLE_SPLIT_MASK                                                                     0x06000000L
6156 //GB_TILE_MODE23
6157 #define GB_TILE_MODE23__ARRAY_MODE__SHIFT                                                                     0x2
6158 #define GB_TILE_MODE23__PIPE_CONFIG__SHIFT                                                                    0x6
6159 #define GB_TILE_MODE23__TILE_SPLIT__SHIFT                                                                     0xb
6160 #define GB_TILE_MODE23__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
6161 #define GB_TILE_MODE23__SAMPLE_SPLIT__SHIFT                                                                   0x19
6162 #define GB_TILE_MODE23__ARRAY_MODE_MASK                                                                       0x0000003CL
6163 #define GB_TILE_MODE23__PIPE_CONFIG_MASK                                                                      0x000007C0L
6164 #define GB_TILE_MODE23__TILE_SPLIT_MASK                                                                       0x00003800L
6165 #define GB_TILE_MODE23__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
6166 #define GB_TILE_MODE23__SAMPLE_SPLIT_MASK                                                                     0x06000000L
6167 //GB_TILE_MODE24
6168 #define GB_TILE_MODE24__ARRAY_MODE__SHIFT                                                                     0x2
6169 #define GB_TILE_MODE24__PIPE_CONFIG__SHIFT                                                                    0x6
6170 #define GB_TILE_MODE24__TILE_SPLIT__SHIFT                                                                     0xb
6171 #define GB_TILE_MODE24__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
6172 #define GB_TILE_MODE24__SAMPLE_SPLIT__SHIFT                                                                   0x19
6173 #define GB_TILE_MODE24__ARRAY_MODE_MASK                                                                       0x0000003CL
6174 #define GB_TILE_MODE24__PIPE_CONFIG_MASK                                                                      0x000007C0L
6175 #define GB_TILE_MODE24__TILE_SPLIT_MASK                                                                       0x00003800L
6176 #define GB_TILE_MODE24__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
6177 #define GB_TILE_MODE24__SAMPLE_SPLIT_MASK                                                                     0x06000000L
6178 //GB_TILE_MODE25
6179 #define GB_TILE_MODE25__ARRAY_MODE__SHIFT                                                                     0x2
6180 #define GB_TILE_MODE25__PIPE_CONFIG__SHIFT                                                                    0x6
6181 #define GB_TILE_MODE25__TILE_SPLIT__SHIFT                                                                     0xb
6182 #define GB_TILE_MODE25__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
6183 #define GB_TILE_MODE25__SAMPLE_SPLIT__SHIFT                                                                   0x19
6184 #define GB_TILE_MODE25__ARRAY_MODE_MASK                                                                       0x0000003CL
6185 #define GB_TILE_MODE25__PIPE_CONFIG_MASK                                                                      0x000007C0L
6186 #define GB_TILE_MODE25__TILE_SPLIT_MASK                                                                       0x00003800L
6187 #define GB_TILE_MODE25__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
6188 #define GB_TILE_MODE25__SAMPLE_SPLIT_MASK                                                                     0x06000000L
6189 //GB_TILE_MODE26
6190 #define GB_TILE_MODE26__ARRAY_MODE__SHIFT                                                                     0x2
6191 #define GB_TILE_MODE26__PIPE_CONFIG__SHIFT                                                                    0x6
6192 #define GB_TILE_MODE26__TILE_SPLIT__SHIFT                                                                     0xb
6193 #define GB_TILE_MODE26__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
6194 #define GB_TILE_MODE26__SAMPLE_SPLIT__SHIFT                                                                   0x19
6195 #define GB_TILE_MODE26__ARRAY_MODE_MASK                                                                       0x0000003CL
6196 #define GB_TILE_MODE26__PIPE_CONFIG_MASK                                                                      0x000007C0L
6197 #define GB_TILE_MODE26__TILE_SPLIT_MASK                                                                       0x00003800L
6198 #define GB_TILE_MODE26__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
6199 #define GB_TILE_MODE26__SAMPLE_SPLIT_MASK                                                                     0x06000000L
6200 //GB_TILE_MODE27
6201 #define GB_TILE_MODE27__ARRAY_MODE__SHIFT                                                                     0x2
6202 #define GB_TILE_MODE27__PIPE_CONFIG__SHIFT                                                                    0x6
6203 #define GB_TILE_MODE27__TILE_SPLIT__SHIFT                                                                     0xb
6204 #define GB_TILE_MODE27__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
6205 #define GB_TILE_MODE27__SAMPLE_SPLIT__SHIFT                                                                   0x19
6206 #define GB_TILE_MODE27__ARRAY_MODE_MASK                                                                       0x0000003CL
6207 #define GB_TILE_MODE27__PIPE_CONFIG_MASK                                                                      0x000007C0L
6208 #define GB_TILE_MODE27__TILE_SPLIT_MASK                                                                       0x00003800L
6209 #define GB_TILE_MODE27__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
6210 #define GB_TILE_MODE27__SAMPLE_SPLIT_MASK                                                                     0x06000000L
6211 //GB_TILE_MODE28
6212 #define GB_TILE_MODE28__ARRAY_MODE__SHIFT                                                                     0x2
6213 #define GB_TILE_MODE28__PIPE_CONFIG__SHIFT                                                                    0x6
6214 #define GB_TILE_MODE28__TILE_SPLIT__SHIFT                                                                     0xb
6215 #define GB_TILE_MODE28__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
6216 #define GB_TILE_MODE28__SAMPLE_SPLIT__SHIFT                                                                   0x19
6217 #define GB_TILE_MODE28__ARRAY_MODE_MASK                                                                       0x0000003CL
6218 #define GB_TILE_MODE28__PIPE_CONFIG_MASK                                                                      0x000007C0L
6219 #define GB_TILE_MODE28__TILE_SPLIT_MASK                                                                       0x00003800L
6220 #define GB_TILE_MODE28__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
6221 #define GB_TILE_MODE28__SAMPLE_SPLIT_MASK                                                                     0x06000000L
6222 //GB_TILE_MODE29
6223 #define GB_TILE_MODE29__ARRAY_MODE__SHIFT                                                                     0x2
6224 #define GB_TILE_MODE29__PIPE_CONFIG__SHIFT                                                                    0x6
6225 #define GB_TILE_MODE29__TILE_SPLIT__SHIFT                                                                     0xb
6226 #define GB_TILE_MODE29__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
6227 #define GB_TILE_MODE29__SAMPLE_SPLIT__SHIFT                                                                   0x19
6228 #define GB_TILE_MODE29__ARRAY_MODE_MASK                                                                       0x0000003CL
6229 #define GB_TILE_MODE29__PIPE_CONFIG_MASK                                                                      0x000007C0L
6230 #define GB_TILE_MODE29__TILE_SPLIT_MASK                                                                       0x00003800L
6231 #define GB_TILE_MODE29__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
6232 #define GB_TILE_MODE29__SAMPLE_SPLIT_MASK                                                                     0x06000000L
6233 //GB_TILE_MODE30
6234 #define GB_TILE_MODE30__ARRAY_MODE__SHIFT                                                                     0x2
6235 #define GB_TILE_MODE30__PIPE_CONFIG__SHIFT                                                                    0x6
6236 #define GB_TILE_MODE30__TILE_SPLIT__SHIFT                                                                     0xb
6237 #define GB_TILE_MODE30__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
6238 #define GB_TILE_MODE30__SAMPLE_SPLIT__SHIFT                                                                   0x19
6239 #define GB_TILE_MODE30__ARRAY_MODE_MASK                                                                       0x0000003CL
6240 #define GB_TILE_MODE30__PIPE_CONFIG_MASK                                                                      0x000007C0L
6241 #define GB_TILE_MODE30__TILE_SPLIT_MASK                                                                       0x00003800L
6242 #define GB_TILE_MODE30__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
6243 #define GB_TILE_MODE30__SAMPLE_SPLIT_MASK                                                                     0x06000000L
6244 //GB_TILE_MODE31
6245 #define GB_TILE_MODE31__ARRAY_MODE__SHIFT                                                                     0x2
6246 #define GB_TILE_MODE31__PIPE_CONFIG__SHIFT                                                                    0x6
6247 #define GB_TILE_MODE31__TILE_SPLIT__SHIFT                                                                     0xb
6248 #define GB_TILE_MODE31__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
6249 #define GB_TILE_MODE31__SAMPLE_SPLIT__SHIFT                                                                   0x19
6250 #define GB_TILE_MODE31__ARRAY_MODE_MASK                                                                       0x0000003CL
6251 #define GB_TILE_MODE31__PIPE_CONFIG_MASK                                                                      0x000007C0L
6252 #define GB_TILE_MODE31__TILE_SPLIT_MASK                                                                       0x00003800L
6253 #define GB_TILE_MODE31__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
6254 #define GB_TILE_MODE31__SAMPLE_SPLIT_MASK                                                                     0x06000000L
6255 //GB_MACROTILE_MODE0
6256 #define GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT                                                                 0x0
6257 #define GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT                                                                0x2
6258 #define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT                                                          0x4
6259 #define GB_MACROTILE_MODE0__NUM_BANKS__SHIFT                                                                  0x6
6260 #define GB_MACROTILE_MODE0__BANK_WIDTH_MASK                                                                   0x00000003L
6261 #define GB_MACROTILE_MODE0__BANK_HEIGHT_MASK                                                                  0x0000000CL
6262 #define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT_MASK                                                            0x00000030L
6263 #define GB_MACROTILE_MODE0__NUM_BANKS_MASK                                                                    0x000000C0L
6264 //GB_MACROTILE_MODE1
6265 #define GB_MACROTILE_MODE1__BANK_WIDTH__SHIFT                                                                 0x0
6266 #define GB_MACROTILE_MODE1__BANK_HEIGHT__SHIFT                                                                0x2
6267 #define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT__SHIFT                                                          0x4
6268 #define GB_MACROTILE_MODE1__NUM_BANKS__SHIFT                                                                  0x6
6269 #define GB_MACROTILE_MODE1__BANK_WIDTH_MASK                                                                   0x00000003L
6270 #define GB_MACROTILE_MODE1__BANK_HEIGHT_MASK                                                                  0x0000000CL
6271 #define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT_MASK                                                            0x00000030L
6272 #define GB_MACROTILE_MODE1__NUM_BANKS_MASK                                                                    0x000000C0L
6273 //GB_MACROTILE_MODE2
6274 #define GB_MACROTILE_MODE2__BANK_WIDTH__SHIFT                                                                 0x0
6275 #define GB_MACROTILE_MODE2__BANK_HEIGHT__SHIFT                                                                0x2
6276 #define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT__SHIFT                                                          0x4
6277 #define GB_MACROTILE_MODE2__NUM_BANKS__SHIFT                                                                  0x6
6278 #define GB_MACROTILE_MODE2__BANK_WIDTH_MASK                                                                   0x00000003L
6279 #define GB_MACROTILE_MODE2__BANK_HEIGHT_MASK                                                                  0x0000000CL
6280 #define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT_MASK                                                            0x00000030L
6281 #define GB_MACROTILE_MODE2__NUM_BANKS_MASK                                                                    0x000000C0L
6282 //GB_MACROTILE_MODE3
6283 #define GB_MACROTILE_MODE3__BANK_WIDTH__SHIFT                                                                 0x0
6284 #define GB_MACROTILE_MODE3__BANK_HEIGHT__SHIFT                                                                0x2
6285 #define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT__SHIFT                                                          0x4
6286 #define GB_MACROTILE_MODE3__NUM_BANKS__SHIFT                                                                  0x6
6287 #define GB_MACROTILE_MODE3__BANK_WIDTH_MASK                                                                   0x00000003L
6288 #define GB_MACROTILE_MODE3__BANK_HEIGHT_MASK                                                                  0x0000000CL
6289 #define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT_MASK                                                            0x00000030L
6290 #define GB_MACROTILE_MODE3__NUM_BANKS_MASK                                                                    0x000000C0L
6291 //GB_MACROTILE_MODE4
6292 #define GB_MACROTILE_MODE4__BANK_WIDTH__SHIFT                                                                 0x0
6293 #define GB_MACROTILE_MODE4__BANK_HEIGHT__SHIFT                                                                0x2
6294 #define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT__SHIFT                                                          0x4
6295 #define GB_MACROTILE_MODE4__NUM_BANKS__SHIFT                                                                  0x6
6296 #define GB_MACROTILE_MODE4__BANK_WIDTH_MASK                                                                   0x00000003L
6297 #define GB_MACROTILE_MODE4__BANK_HEIGHT_MASK                                                                  0x0000000CL
6298 #define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT_MASK                                                            0x00000030L
6299 #define GB_MACROTILE_MODE4__NUM_BANKS_MASK                                                                    0x000000C0L
6300 //GB_MACROTILE_MODE5
6301 #define GB_MACROTILE_MODE5__BANK_WIDTH__SHIFT                                                                 0x0
6302 #define GB_MACROTILE_MODE5__BANK_HEIGHT__SHIFT                                                                0x2
6303 #define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT__SHIFT                                                          0x4
6304 #define GB_MACROTILE_MODE5__NUM_BANKS__SHIFT                                                                  0x6
6305 #define GB_MACROTILE_MODE5__BANK_WIDTH_MASK                                                                   0x00000003L
6306 #define GB_MACROTILE_MODE5__BANK_HEIGHT_MASK                                                                  0x0000000CL
6307 #define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT_MASK                                                            0x00000030L
6308 #define GB_MACROTILE_MODE5__NUM_BANKS_MASK                                                                    0x000000C0L
6309 //GB_MACROTILE_MODE6
6310 #define GB_MACROTILE_MODE6__BANK_WIDTH__SHIFT                                                                 0x0
6311 #define GB_MACROTILE_MODE6__BANK_HEIGHT__SHIFT                                                                0x2
6312 #define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT__SHIFT                                                          0x4
6313 #define GB_MACROTILE_MODE6__NUM_BANKS__SHIFT                                                                  0x6
6314 #define GB_MACROTILE_MODE6__BANK_WIDTH_MASK                                                                   0x00000003L
6315 #define GB_MACROTILE_MODE6__BANK_HEIGHT_MASK                                                                  0x0000000CL
6316 #define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT_MASK                                                            0x00000030L
6317 #define GB_MACROTILE_MODE6__NUM_BANKS_MASK                                                                    0x000000C0L
6318 //GB_MACROTILE_MODE7
6319 #define GB_MACROTILE_MODE7__BANK_WIDTH__SHIFT                                                                 0x0
6320 #define GB_MACROTILE_MODE7__BANK_HEIGHT__SHIFT                                                                0x2
6321 #define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT__SHIFT                                                          0x4
6322 #define GB_MACROTILE_MODE7__NUM_BANKS__SHIFT                                                                  0x6
6323 #define GB_MACROTILE_MODE7__BANK_WIDTH_MASK                                                                   0x00000003L
6324 #define GB_MACROTILE_MODE7__BANK_HEIGHT_MASK                                                                  0x0000000CL
6325 #define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT_MASK                                                            0x00000030L
6326 #define GB_MACROTILE_MODE7__NUM_BANKS_MASK                                                                    0x000000C0L
6327 //GB_MACROTILE_MODE8
6328 #define GB_MACROTILE_MODE8__BANK_WIDTH__SHIFT                                                                 0x0
6329 #define GB_MACROTILE_MODE8__BANK_HEIGHT__SHIFT                                                                0x2
6330 #define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT__SHIFT                                                          0x4
6331 #define GB_MACROTILE_MODE8__NUM_BANKS__SHIFT                                                                  0x6
6332 #define GB_MACROTILE_MODE8__BANK_WIDTH_MASK                                                                   0x00000003L
6333 #define GB_MACROTILE_MODE8__BANK_HEIGHT_MASK                                                                  0x0000000CL
6334 #define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT_MASK                                                            0x00000030L
6335 #define GB_MACROTILE_MODE8__NUM_BANKS_MASK                                                                    0x000000C0L
6336 //GB_MACROTILE_MODE9
6337 #define GB_MACROTILE_MODE9__BANK_WIDTH__SHIFT                                                                 0x0
6338 #define GB_MACROTILE_MODE9__BANK_HEIGHT__SHIFT                                                                0x2
6339 #define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT__SHIFT                                                          0x4
6340 #define GB_MACROTILE_MODE9__NUM_BANKS__SHIFT                                                                  0x6
6341 #define GB_MACROTILE_MODE9__BANK_WIDTH_MASK                                                                   0x00000003L
6342 #define GB_MACROTILE_MODE9__BANK_HEIGHT_MASK                                                                  0x0000000CL
6343 #define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT_MASK                                                            0x00000030L
6344 #define GB_MACROTILE_MODE9__NUM_BANKS_MASK                                                                    0x000000C0L
6345 //GB_MACROTILE_MODE10
6346 #define GB_MACROTILE_MODE10__BANK_WIDTH__SHIFT                                                                0x0
6347 #define GB_MACROTILE_MODE10__BANK_HEIGHT__SHIFT                                                               0x2
6348 #define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT__SHIFT                                                         0x4
6349 #define GB_MACROTILE_MODE10__NUM_BANKS__SHIFT                                                                 0x6
6350 #define GB_MACROTILE_MODE10__BANK_WIDTH_MASK                                                                  0x00000003L
6351 #define GB_MACROTILE_MODE10__BANK_HEIGHT_MASK                                                                 0x0000000CL
6352 #define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT_MASK                                                           0x00000030L
6353 #define GB_MACROTILE_MODE10__NUM_BANKS_MASK                                                                   0x000000C0L
6354 //GB_MACROTILE_MODE11
6355 #define GB_MACROTILE_MODE11__BANK_WIDTH__SHIFT                                                                0x0
6356 #define GB_MACROTILE_MODE11__BANK_HEIGHT__SHIFT                                                               0x2
6357 #define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT__SHIFT                                                         0x4
6358 #define GB_MACROTILE_MODE11__NUM_BANKS__SHIFT                                                                 0x6
6359 #define GB_MACROTILE_MODE11__BANK_WIDTH_MASK                                                                  0x00000003L
6360 #define GB_MACROTILE_MODE11__BANK_HEIGHT_MASK                                                                 0x0000000CL
6361 #define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT_MASK                                                           0x00000030L
6362 #define GB_MACROTILE_MODE11__NUM_BANKS_MASK                                                                   0x000000C0L
6363 //GB_MACROTILE_MODE12
6364 #define GB_MACROTILE_MODE12__BANK_WIDTH__SHIFT                                                                0x0
6365 #define GB_MACROTILE_MODE12__BANK_HEIGHT__SHIFT                                                               0x2
6366 #define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT__SHIFT                                                         0x4
6367 #define GB_MACROTILE_MODE12__NUM_BANKS__SHIFT                                                                 0x6
6368 #define GB_MACROTILE_MODE12__BANK_WIDTH_MASK                                                                  0x00000003L
6369 #define GB_MACROTILE_MODE12__BANK_HEIGHT_MASK                                                                 0x0000000CL
6370 #define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT_MASK                                                           0x00000030L
6371 #define GB_MACROTILE_MODE12__NUM_BANKS_MASK                                                                   0x000000C0L
6372 //GB_MACROTILE_MODE13
6373 #define GB_MACROTILE_MODE13__BANK_WIDTH__SHIFT                                                                0x0
6374 #define GB_MACROTILE_MODE13__BANK_HEIGHT__SHIFT                                                               0x2
6375 #define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT__SHIFT                                                         0x4
6376 #define GB_MACROTILE_MODE13__NUM_BANKS__SHIFT                                                                 0x6
6377 #define GB_MACROTILE_MODE13__BANK_WIDTH_MASK                                                                  0x00000003L
6378 #define GB_MACROTILE_MODE13__BANK_HEIGHT_MASK                                                                 0x0000000CL
6379 #define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT_MASK                                                           0x00000030L
6380 #define GB_MACROTILE_MODE13__NUM_BANKS_MASK                                                                   0x000000C0L
6381 //GB_MACROTILE_MODE14
6382 #define GB_MACROTILE_MODE14__BANK_WIDTH__SHIFT                                                                0x0
6383 #define GB_MACROTILE_MODE14__BANK_HEIGHT__SHIFT                                                               0x2
6384 #define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT__SHIFT                                                         0x4
6385 #define GB_MACROTILE_MODE14__NUM_BANKS__SHIFT                                                                 0x6
6386 #define GB_MACROTILE_MODE14__BANK_WIDTH_MASK                                                                  0x00000003L
6387 #define GB_MACROTILE_MODE14__BANK_HEIGHT_MASK                                                                 0x0000000CL
6388 #define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT_MASK                                                           0x00000030L
6389 #define GB_MACROTILE_MODE14__NUM_BANKS_MASK                                                                   0x000000C0L
6390 //GB_MACROTILE_MODE15
6391 #define GB_MACROTILE_MODE15__BANK_WIDTH__SHIFT                                                                0x0
6392 #define GB_MACROTILE_MODE15__BANK_HEIGHT__SHIFT                                                               0x2
6393 #define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT__SHIFT                                                         0x4
6394 #define GB_MACROTILE_MODE15__NUM_BANKS__SHIFT                                                                 0x6
6395 #define GB_MACROTILE_MODE15__BANK_WIDTH_MASK                                                                  0x00000003L
6396 #define GB_MACROTILE_MODE15__BANK_HEIGHT_MASK                                                                 0x0000000CL
6397 #define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT_MASK                                                           0x00000030L
6398 #define GB_MACROTILE_MODE15__NUM_BANKS_MASK                                                                   0x000000C0L
6399 //CB_HW_CONTROL
6400 #define CB_HW_CONTROL__CM_CACHE_EVICT_POINT__SHIFT                                                            0x0
6401 #define CB_HW_CONTROL__FC_CACHE_EVICT_POINT__SHIFT                                                            0x6
6402 #define CB_HW_CONTROL__CC_CACHE_EVICT_POINT__SHIFT                                                            0xc
6403 #define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT                                                      0x10
6404 #define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING__SHIFT                                                0x12
6405 #define CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT                                                                 0x13
6406 #define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE__SHIFT                                                             0x14
6407 #define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT                                                0x15
6408 #define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK__SHIFT                                                         0x16
6409 #define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG__SHIFT                                             0x17
6410 #define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT                                                   0x18
6411 #define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT                                                        0x19
6412 #define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT                                                 0x1a
6413 #define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT                                0x1b
6414 #define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT__SHIFT                                   0x1c
6415 #define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT__SHIFT                                0x1d
6416 #define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT                                              0x1e
6417 #define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT                                    0x1f
6418 #define CB_HW_CONTROL__CM_CACHE_EVICT_POINT_MASK                                                              0x0000000FL
6419 #define CB_HW_CONTROL__FC_CACHE_EVICT_POINT_MASK                                                              0x000003C0L
6420 #define CB_HW_CONTROL__CC_CACHE_EVICT_POINT_MASK                                                              0x0000F000L
6421 #define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK                                                        0x00010000L
6422 #define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING_MASK                                                  0x00040000L
6423 #define CB_HW_CONTROL__FORCE_NEEDS_DST_MASK                                                                   0x00080000L
6424 #define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE_MASK                                                               0x00100000L
6425 #define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK                                                  0x00200000L
6426 #define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK_MASK                                                           0x00400000L
6427 #define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG_MASK                                               0x00800000L
6428 #define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK                                                     0x01000000L
6429 #define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK                                                          0x02000000L
6430 #define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK                                                   0x04000000L
6431 #define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK                                  0x08000000L
6432 #define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT_MASK                                     0x10000000L
6433 #define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT_MASK                                  0x20000000L
6434 #define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK                                                0x40000000L
6435 #define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK                                      0x80000000L
6436 //CB_HW_CONTROL_1
6437 #define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS__SHIFT                                                             0x0
6438 #define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS__SHIFT                                                             0x5
6439 #define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT                                                             0xb
6440 #define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH__SHIFT                                                            0x11
6441 #define CB_HW_CONTROL_1__RMI_CREDITS__SHIFT                                                                   0x1a
6442 #define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS_MASK                                                               0x0000001FL
6443 #define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS_MASK                                                               0x000007E0L
6444 #define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK                                                               0x0001F800L
6445 #define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH_MASK                                                              0x03FE0000L
6446 #define CB_HW_CONTROL_1__RMI_CREDITS_MASK                                                                     0xFC000000L
6447 //CB_HW_CONTROL_2
6448 #define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH__SHIFT                                                        0x0
6449 #define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH__SHIFT                                                      0x8
6450 #define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH__SHIFT                                                      0xf
6451 #define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8__SHIFT                                                   0x18
6452 #define CB_HW_CONTROL_2__CHICKEN_BITS__SHIFT                                                                  0x1c
6453 #define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH_MASK                                                          0x000000FFL
6454 #define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH_MASK                                                        0x00007F00L
6455 #define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH_MASK                                                        0x007F8000L
6456 #define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8_MASK                                                     0x0F000000L
6457 #define CB_HW_CONTROL_2__CHICKEN_BITS_MASK                                                                    0xF0000000L
6458 //CB_HW_CONTROL_3
6459 #define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL__SHIFT                                        0x0
6460 #define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED__SHIFT                                              0x1
6461 #define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT__SHIFT                                                  0x2
6462 #define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP__SHIFT                                                 0x3
6463 #define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR__SHIFT                                            0x4
6464 #define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM__SHIFT                                            0x5
6465 #define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_KEY_MOD__SHIFT                                                 0x6
6466 #define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING__SHIFT                                                 0x7
6467 #define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION__SHIFT                             0x8
6468 #define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS__SHIFT                                                 0x9
6469 #define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS__SHIFT                                                     0xa
6470 #define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION__SHIFT                                             0xb
6471 #define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967__SHIFT                                              0xc
6472 #define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657__SHIFT                                              0xd
6473 #define CB_HW_CONTROL_3__DISABLE_OC_FIXES_OF_BUG_522542__SHIFT                                                0xe
6474 #define CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH__SHIFT                                                           0xf
6475 #define CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH__SHIFT                                                          0x10
6476 #define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC__SHIFT                                                       0x11
6477 #define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_FC__SHIFT                                                       0x12
6478 #define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC__SHIFT                                                       0x13
6479 #define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CM__SHIFT                                                       0x14
6480 #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC__SHIFT                                                    0x15
6481 #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_FC__SHIFT                                                    0x16
6482 #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC__SHIFT                                                    0x17
6483 #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CM__SHIFT                                                    0x18
6484 #define CB_HW_CONTROL_3__DISABLE_NACK_COLOR_RD_WR_OPT__SHIFT                                                  0x19
6485 #define CB_HW_CONTROL_3__DISABLE_BLENDER_CLOCK_GATING__SHIFT                                                  0x1a
6486 #define CB_HW_CONTROL_3__DISABLE_DUALSRC_WITH_OBJPRIMID_FIX__SHIFT                                            0x1b
6487 #define CB_HW_CONTROL_3__COLOR_CACHE_PREFETCH_NUM_CLS__SHIFT                                                  0x1c
6488 #define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL_MASK                                          0x00000001L
6489 #define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED_MASK                                                0x00000002L
6490 #define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT_MASK                                                    0x00000004L
6491 #define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP_MASK                                                   0x00000008L
6492 #define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR_MASK                                              0x00000010L
6493 #define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM_MASK                                              0x00000020L
6494 #define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_KEY_MOD_MASK                                                   0x00000040L
6495 #define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING_MASK                                                   0x00000080L
6496 #define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION_MASK                               0x00000100L
6497 #define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS_MASK                                                   0x00000200L
6498 #define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS_MASK                                                       0x00000400L
6499 #define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION_MASK                                               0x00000800L
6500 #define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967_MASK                                                0x00001000L
6501 #define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657_MASK                                                0x00002000L
6502 #define CB_HW_CONTROL_3__DISABLE_OC_FIXES_OF_BUG_522542_MASK                                                  0x00004000L
6503 #define CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH_MASK                                                             0x00008000L
6504 #define CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH_MASK                                                            0x00010000L
6505 #define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC_MASK                                                         0x00020000L
6506 #define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_FC_MASK                                                         0x00040000L
6507 #define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC_MASK                                                         0x00080000L
6508 #define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CM_MASK                                                         0x00100000L
6509 #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC_MASK                                                      0x00200000L
6510 #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_FC_MASK                                                      0x00400000L
6511 #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC_MASK                                                      0x00800000L
6512 #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CM_MASK                                                      0x01000000L
6513 #define CB_HW_CONTROL_3__DISABLE_NACK_COLOR_RD_WR_OPT_MASK                                                    0x02000000L
6514 #define CB_HW_CONTROL_3__DISABLE_BLENDER_CLOCK_GATING_MASK                                                    0x04000000L
6515 #define CB_HW_CONTROL_3__DISABLE_DUALSRC_WITH_OBJPRIMID_FIX_MASK                                              0x08000000L
6516 #define CB_HW_CONTROL_3__COLOR_CACHE_PREFETCH_NUM_CLS_MASK                                                    0x30000000L
6517 //CB_HW_MEM_ARBITER_RD
6518 #define CB_HW_MEM_ARBITER_RD__MODE__SHIFT                                                                     0x0
6519 #define CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE__SHIFT                                                        0x2
6520 #define CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE__SHIFT                                                          0x6
6521 #define CB_HW_MEM_ARBITER_RD__WEIGHT_CC__SHIFT                                                                0xa
6522 #define CB_HW_MEM_ARBITER_RD__WEIGHT_FC__SHIFT                                                                0xc
6523 #define CB_HW_MEM_ARBITER_RD__WEIGHT_CM__SHIFT                                                                0xe
6524 #define CB_HW_MEM_ARBITER_RD__WEIGHT_DC__SHIFT                                                                0x10
6525 #define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS__SHIFT                                                        0x12
6526 #define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS__SHIFT                                                      0x14
6527 #define CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS__SHIFT                                                   0x16
6528 #define CB_HW_MEM_ARBITER_RD__SCALE_AGE__SHIFT                                                                0x17
6529 #define CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT__SHIFT                                                             0x1a
6530 #define CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS__SHIFT                                                 0x1d
6531 #define CB_HW_MEM_ARBITER_RD__MODE_MASK                                                                       0x00000003L
6532 #define CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE_MASK                                                          0x0000003CL
6533 #define CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE_MASK                                                            0x000003C0L
6534 #define CB_HW_MEM_ARBITER_RD__WEIGHT_CC_MASK                                                                  0x00000C00L
6535 #define CB_HW_MEM_ARBITER_RD__WEIGHT_FC_MASK                                                                  0x00003000L
6536 #define CB_HW_MEM_ARBITER_RD__WEIGHT_CM_MASK                                                                  0x0000C000L
6537 #define CB_HW_MEM_ARBITER_RD__WEIGHT_DC_MASK                                                                  0x00030000L
6538 #define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS_MASK                                                          0x000C0000L
6539 #define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS_MASK                                                        0x00300000L
6540 #define CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS_MASK                                                     0x00400000L
6541 #define CB_HW_MEM_ARBITER_RD__SCALE_AGE_MASK                                                                  0x03800000L
6542 #define CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT_MASK                                                               0x1C000000L
6543 #define CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS_MASK                                                   0x20000000L
6544 //CB_HW_MEM_ARBITER_WR
6545 #define CB_HW_MEM_ARBITER_WR__MODE__SHIFT                                                                     0x0
6546 #define CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE__SHIFT                                                        0x2
6547 #define CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE__SHIFT                                                          0x6
6548 #define CB_HW_MEM_ARBITER_WR__WEIGHT_CC__SHIFT                                                                0xa
6549 #define CB_HW_MEM_ARBITER_WR__WEIGHT_FC__SHIFT                                                                0xc
6550 #define CB_HW_MEM_ARBITER_WR__WEIGHT_CM__SHIFT                                                                0xe
6551 #define CB_HW_MEM_ARBITER_WR__WEIGHT_DC__SHIFT                                                                0x10
6552 #define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS__SHIFT                                                        0x12
6553 #define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS__SHIFT                                                      0x14
6554 #define CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK__SHIFT                                                  0x16
6555 #define CB_HW_MEM_ARBITER_WR__SCALE_AGE__SHIFT                                                                0x17
6556 #define CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT__SHIFT                                                             0x1a
6557 #define CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS__SHIFT                                                 0x1d
6558 #define CB_HW_MEM_ARBITER_WR__MODE_MASK                                                                       0x00000003L
6559 #define CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE_MASK                                                          0x0000003CL
6560 #define CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE_MASK                                                            0x000003C0L
6561 #define CB_HW_MEM_ARBITER_WR__WEIGHT_CC_MASK                                                                  0x00000C00L
6562 #define CB_HW_MEM_ARBITER_WR__WEIGHT_FC_MASK                                                                  0x00003000L
6563 #define CB_HW_MEM_ARBITER_WR__WEIGHT_CM_MASK                                                                  0x0000C000L
6564 #define CB_HW_MEM_ARBITER_WR__WEIGHT_DC_MASK                                                                  0x00030000L
6565 #define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS_MASK                                                          0x000C0000L
6566 #define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS_MASK                                                        0x00300000L
6567 #define CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK_MASK                                                    0x00400000L
6568 #define CB_HW_MEM_ARBITER_WR__SCALE_AGE_MASK                                                                  0x03800000L
6569 #define CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT_MASK                                                               0x1C000000L
6570 #define CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS_MASK                                                   0x20000000L
6571 //CB_DCC_CONFIG
6572 #define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH__SHIFT                                                        0x0
6573 #define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE__SHIFT                                                      0x5
6574 #define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE__SHIFT                                               0x6
6575 #define CB_DCC_CONFIG__DISABLE_CONSTANT_ENCODE__SHIFT                                                         0x7
6576 #define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH__SHIFT                                                       0x8
6577 #define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH__SHIFT                                                     0x10
6578 #define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT__SHIFT                                                           0x18
6579 #define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS__SHIFT                                                              0x1c
6580 #define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH_MASK                                                          0x0000001FL
6581 #define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE_MASK                                                        0x00000020L
6582 #define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE_MASK                                                 0x00000040L
6583 #define CB_DCC_CONFIG__DISABLE_CONSTANT_ENCODE_MASK                                                           0x00000080L
6584 #define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH_MASK                                                         0x0000FF00L
6585 #define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH_MASK                                                       0x007F0000L
6586 #define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT_MASK                                                             0x0F000000L
6587 #define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS_MASK                                                                0xF0000000L
6588 //GC_USER_RB_REDUNDANCY
6589 #define GC_USER_RB_REDUNDANCY__FAILED_RB0__SHIFT                                                              0x8
6590 #define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT                                                          0xc
6591 #define GC_USER_RB_REDUNDANCY__FAILED_RB1__SHIFT                                                              0x10
6592 #define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT                                                          0x14
6593 #define GC_USER_RB_REDUNDANCY__FAILED_RB0_MASK                                                                0x00000F00L
6594 #define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0_MASK                                                            0x00001000L
6595 #define GC_USER_RB_REDUNDANCY__FAILED_RB1_MASK                                                                0x000F0000L
6596 #define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1_MASK                                                            0x00100000L
6597 //GC_USER_RB_BACKEND_DISABLE
6598 #define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT                                                    0x10
6599 #define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK                                                      0x00FF0000L
6600 
6601 
6602 // addressBlock: xcd0_gc_ea_gceadec
6603 //GCEA_DRAM_RD_CLI2GRP_MAP0
6604 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                          0x0
6605 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                          0x2
6606 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                          0x4
6607 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                          0x6
6608 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                          0x8
6609 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                          0xa
6610 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                          0xc
6611 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                          0xe
6612 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                          0x10
6613 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                          0x12
6614 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                         0x14
6615 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                         0x16
6616 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                         0x18
6617 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                         0x1a
6618 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                         0x1c
6619 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                         0x1e
6620 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                            0x00000003L
6621 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                            0x0000000CL
6622 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                            0x00000030L
6623 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                            0x000000C0L
6624 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                            0x00000300L
6625 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                            0x00000C00L
6626 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                            0x00003000L
6627 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                            0x0000C000L
6628 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                            0x00030000L
6629 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                            0x000C0000L
6630 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                           0x00300000L
6631 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                           0x00C00000L
6632 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                           0x03000000L
6633 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                           0x0C000000L
6634 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                           0x30000000L
6635 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                           0xC0000000L
6636 //GCEA_DRAM_RD_CLI2GRP_MAP1
6637 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                         0x0
6638 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                         0x2
6639 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                         0x4
6640 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                         0x6
6641 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                         0x8
6642 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                         0xa
6643 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                         0xc
6644 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                         0xe
6645 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                         0x10
6646 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                         0x12
6647 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                         0x14
6648 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                         0x16
6649 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                         0x18
6650 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                         0x1a
6651 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                         0x1c
6652 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                         0x1e
6653 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                           0x00000003L
6654 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                           0x0000000CL
6655 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                           0x00000030L
6656 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                           0x000000C0L
6657 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                           0x00000300L
6658 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                           0x00000C00L
6659 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                           0x00003000L
6660 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                           0x0000C000L
6661 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                           0x00030000L
6662 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                           0x000C0000L
6663 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                           0x00300000L
6664 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                           0x00C00000L
6665 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                           0x03000000L
6666 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                           0x0C000000L
6667 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                           0x30000000L
6668 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                           0xC0000000L
6669 //GCEA_DRAM_WR_CLI2GRP_MAP0
6670 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                          0x0
6671 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                          0x2
6672 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                          0x4
6673 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                          0x6
6674 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                          0x8
6675 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                          0xa
6676 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                          0xc
6677 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                          0xe
6678 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                          0x10
6679 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                          0x12
6680 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                         0x14
6681 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                         0x16
6682 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                         0x18
6683 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                         0x1a
6684 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                         0x1c
6685 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                         0x1e
6686 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                            0x00000003L
6687 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                            0x0000000CL
6688 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                            0x00000030L
6689 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                            0x000000C0L
6690 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                            0x00000300L
6691 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                            0x00000C00L
6692 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                            0x00003000L
6693 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                            0x0000C000L
6694 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                            0x00030000L
6695 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                            0x000C0000L
6696 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                           0x00300000L
6697 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                           0x00C00000L
6698 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                           0x03000000L
6699 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                           0x0C000000L
6700 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                           0x30000000L
6701 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                           0xC0000000L
6702 //GCEA_DRAM_WR_CLI2GRP_MAP1
6703 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                         0x0
6704 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                         0x2
6705 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                         0x4
6706 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                         0x6
6707 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                         0x8
6708 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                         0xa
6709 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                         0xc
6710 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                         0xe
6711 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                         0x10
6712 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                         0x12
6713 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                         0x14
6714 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                         0x16
6715 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                         0x18
6716 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                         0x1a
6717 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                         0x1c
6718 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                         0x1e
6719 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                           0x00000003L
6720 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                           0x0000000CL
6721 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                           0x00000030L
6722 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                           0x000000C0L
6723 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                           0x00000300L
6724 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                           0x00000C00L
6725 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                           0x00003000L
6726 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                           0x0000C000L
6727 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                           0x00030000L
6728 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                           0x000C0000L
6729 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                           0x00300000L
6730 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                           0x00C00000L
6731 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                           0x03000000L
6732 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                           0x0C000000L
6733 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                           0x30000000L
6734 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                           0xC0000000L
6735 //GCEA_DRAM_RD_GRP2VC_MAP
6736 #define GCEA_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT                                                             0x0
6737 #define GCEA_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT                                                             0x3
6738 #define GCEA_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT                                                             0x6
6739 #define GCEA_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT                                                             0x9
6740 #define GCEA_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK                                                               0x00000007L
6741 #define GCEA_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK                                                               0x00000038L
6742 #define GCEA_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK                                                               0x000001C0L
6743 #define GCEA_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK                                                               0x00000E00L
6744 //GCEA_DRAM_WR_GRP2VC_MAP
6745 #define GCEA_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT                                                             0x0
6746 #define GCEA_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT                                                             0x3
6747 #define GCEA_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT                                                             0x6
6748 #define GCEA_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT                                                             0x9
6749 #define GCEA_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK                                                               0x00000007L
6750 #define GCEA_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK                                                               0x00000038L
6751 #define GCEA_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK                                                               0x000001C0L
6752 #define GCEA_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK                                                               0x00000E00L
6753 //GCEA_DRAM_RD_LAZY
6754 #define GCEA_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT                                                                0x0
6755 #define GCEA_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT                                                                0x3
6756 #define GCEA_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT                                                                0x6
6757 #define GCEA_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT                                                                0x9
6758 #define GCEA_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT                                                            0xc
6759 #define GCEA_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                           0x14
6760 #define GCEA_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                           0x1b
6761 #define GCEA_DRAM_RD_LAZY__GROUP0_DELAY_MASK                                                                  0x00000007L
6762 #define GCEA_DRAM_RD_LAZY__GROUP1_DELAY_MASK                                                                  0x00000038L
6763 #define GCEA_DRAM_RD_LAZY__GROUP2_DELAY_MASK                                                                  0x000001C0L
6764 #define GCEA_DRAM_RD_LAZY__GROUP3_DELAY_MASK                                                                  0x00000E00L
6765 #define GCEA_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK                                                              0x0003F000L
6766 #define GCEA_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                             0x07F00000L
6767 #define GCEA_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                             0x78000000L
6768 //GCEA_DRAM_WR_LAZY
6769 #define GCEA_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT                                                                0x0
6770 #define GCEA_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT                                                                0x3
6771 #define GCEA_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT                                                                0x6
6772 #define GCEA_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT                                                                0x9
6773 #define GCEA_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT                                                            0xc
6774 #define GCEA_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                           0x14
6775 #define GCEA_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                           0x1b
6776 #define GCEA_DRAM_WR_LAZY__GROUP0_DELAY_MASK                                                                  0x00000007L
6777 #define GCEA_DRAM_WR_LAZY__GROUP1_DELAY_MASK                                                                  0x00000038L
6778 #define GCEA_DRAM_WR_LAZY__GROUP2_DELAY_MASK                                                                  0x000001C0L
6779 #define GCEA_DRAM_WR_LAZY__GROUP3_DELAY_MASK                                                                  0x00000E00L
6780 #define GCEA_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK                                                              0x0003F000L
6781 #define GCEA_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                             0x07F00000L
6782 #define GCEA_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                             0x78000000L
6783 //GCEA_DRAM_RD_CAM_CNTL
6784 #define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                            0x0
6785 #define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                            0x4
6786 #define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                            0x8
6787 #define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                            0xc
6788 #define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                    0x10
6789 #define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                    0x13
6790 #define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                    0x16
6791 #define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                    0x19
6792 #define GCEA_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT                                                            0x1c
6793 #define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK                                                              0x0000000FL
6794 #define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK                                                              0x000000F0L
6795 #define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK                                                              0x00000F00L
6796 #define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK                                                              0x0000F000L
6797 #define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                      0x00070000L
6798 #define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                      0x00380000L
6799 #define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                      0x01C00000L
6800 #define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                      0x0E000000L
6801 #define GCEA_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK                                                              0x10000000L
6802 //GCEA_DRAM_WR_CAM_CNTL
6803 #define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                            0x0
6804 #define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                            0x4
6805 #define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                            0x8
6806 #define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                            0xc
6807 #define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                    0x10
6808 #define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                    0x13
6809 #define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                    0x16
6810 #define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                    0x19
6811 #define GCEA_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT                                                            0x1c
6812 #define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK                                                              0x0000000FL
6813 #define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK                                                              0x000000F0L
6814 #define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK                                                              0x00000F00L
6815 #define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK                                                              0x0000F000L
6816 #define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                      0x00070000L
6817 #define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                      0x00380000L
6818 #define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                      0x01C00000L
6819 #define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                      0x0E000000L
6820 #define GCEA_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK                                                              0x10000000L
6821 //GCEA_DRAM_PAGE_BURST
6822 #define GCEA_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT                                                              0x0
6823 #define GCEA_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT                                                              0x8
6824 #define GCEA_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT                                                              0x10
6825 #define GCEA_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT                                                              0x18
6826 #define GCEA_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK                                                                0x000000FFL
6827 #define GCEA_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK                                                                0x0000FF00L
6828 #define GCEA_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK                                                                0x00FF0000L
6829 #define GCEA_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK                                                                0xFF000000L
6830 //GCEA_DRAM_RD_PRI_AGE
6831 #define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                        0x0
6832 #define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                        0x3
6833 #define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                        0x6
6834 #define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                        0x9
6835 #define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                   0xc
6836 #define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                   0xf
6837 #define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                   0x12
6838 #define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                   0x15
6839 #define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                          0x00000007L
6840 #define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                          0x00000038L
6841 #define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                          0x000001C0L
6842 #define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                          0x00000E00L
6843 #define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                     0x00007000L
6844 #define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                     0x00038000L
6845 #define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                     0x001C0000L
6846 #define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                     0x00E00000L
6847 //GCEA_DRAM_WR_PRI_AGE
6848 #define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                        0x0
6849 #define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                        0x3
6850 #define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                        0x6
6851 #define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                        0x9
6852 #define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                   0xc
6853 #define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                   0xf
6854 #define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                   0x12
6855 #define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                   0x15
6856 #define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                          0x00000007L
6857 #define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                          0x00000038L
6858 #define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                          0x000001C0L
6859 #define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                          0x00000E00L
6860 #define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                     0x00007000L
6861 #define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                     0x00038000L
6862 #define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                     0x001C0000L
6863 #define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                     0x00E00000L
6864 //GCEA_DRAM_RD_PRI_QUEUING
6865 #define GCEA_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                           0x0
6866 #define GCEA_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                           0x3
6867 #define GCEA_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                           0x6
6868 #define GCEA_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                           0x9
6869 #define GCEA_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                             0x00000007L
6870 #define GCEA_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                             0x00000038L
6871 #define GCEA_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                             0x000001C0L
6872 #define GCEA_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                             0x00000E00L
6873 //GCEA_DRAM_WR_PRI_QUEUING
6874 #define GCEA_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                           0x0
6875 #define GCEA_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                           0x3
6876 #define GCEA_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                           0x6
6877 #define GCEA_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                           0x9
6878 #define GCEA_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                             0x00000007L
6879 #define GCEA_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                             0x00000038L
6880 #define GCEA_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                             0x000001C0L
6881 #define GCEA_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                             0x00000E00L
6882 //GCEA_DRAM_RD_PRI_FIXED
6883 #define GCEA_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                               0x0
6884 #define GCEA_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                               0x3
6885 #define GCEA_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                               0x6
6886 #define GCEA_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                               0x9
6887 #define GCEA_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                 0x00000007L
6888 #define GCEA_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                 0x00000038L
6889 #define GCEA_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                 0x000001C0L
6890 #define GCEA_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                 0x00000E00L
6891 //GCEA_DRAM_WR_PRI_FIXED
6892 #define GCEA_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                               0x0
6893 #define GCEA_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                               0x3
6894 #define GCEA_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                               0x6
6895 #define GCEA_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                               0x9
6896 #define GCEA_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                 0x00000007L
6897 #define GCEA_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                 0x00000038L
6898 #define GCEA_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                 0x000001C0L
6899 #define GCEA_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                 0x00000E00L
6900 //GCEA_DRAM_RD_PRI_URGENCY
6901 #define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                           0x0
6902 #define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                           0x3
6903 #define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                           0x6
6904 #define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                           0x9
6905 #define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                  0xc
6906 #define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                  0xd
6907 #define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                  0xe
6908 #define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                  0xf
6909 #define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                             0x00000007L
6910 #define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                             0x00000038L
6911 #define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                             0x000001C0L
6912 #define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                             0x00000E00L
6913 #define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                    0x00001000L
6914 #define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                    0x00002000L
6915 #define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                    0x00004000L
6916 #define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                    0x00008000L
6917 //GCEA_DRAM_WR_PRI_URGENCY
6918 #define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                           0x0
6919 #define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                           0x3
6920 #define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                           0x6
6921 #define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                           0x9
6922 #define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                  0xc
6923 #define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                  0xd
6924 #define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                  0xe
6925 #define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                  0xf
6926 #define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                             0x00000007L
6927 #define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                             0x00000038L
6928 #define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                             0x000001C0L
6929 #define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                             0x00000E00L
6930 #define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                    0x00001000L
6931 #define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                    0x00002000L
6932 #define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                    0x00004000L
6933 #define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                    0x00008000L
6934 //GCEA_DRAM_RD_PRI_QUANT_PRI1
6935 #define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                  0x0
6936 #define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                  0x8
6937 #define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                  0x10
6938 #define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                  0x18
6939 #define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
6940 #define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
6941 #define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
6942 #define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
6943 //GCEA_DRAM_RD_PRI_QUANT_PRI2
6944 #define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                  0x0
6945 #define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                  0x8
6946 #define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                  0x10
6947 #define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                  0x18
6948 #define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
6949 #define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
6950 #define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
6951 #define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
6952 //GCEA_DRAM_RD_PRI_QUANT_PRI3
6953 #define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                  0x0
6954 #define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                  0x8
6955 #define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                  0x10
6956 #define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                  0x18
6957 #define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
6958 #define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
6959 #define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
6960 #define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
6961 //GCEA_DRAM_WR_PRI_QUANT_PRI1
6962 #define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                  0x0
6963 #define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                  0x8
6964 #define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                  0x10
6965 #define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                  0x18
6966 #define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
6967 #define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
6968 #define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
6969 #define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
6970 //GCEA_DRAM_WR_PRI_QUANT_PRI2
6971 #define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                  0x0
6972 #define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                  0x8
6973 #define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                  0x10
6974 #define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                  0x18
6975 #define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
6976 #define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
6977 #define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
6978 #define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
6979 //GCEA_DRAM_WR_PRI_QUANT_PRI3
6980 #define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                  0x0
6981 #define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                  0x8
6982 #define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                  0x10
6983 #define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                  0x18
6984 #define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
6985 #define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
6986 #define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
6987 #define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
6988 //GCEA_IO_RD_CLI2GRP_MAP0
6989 #define GCEA_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                            0x0
6990 #define GCEA_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                            0x2
6991 #define GCEA_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                            0x4
6992 #define GCEA_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                            0x6
6993 #define GCEA_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                            0x8
6994 #define GCEA_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                            0xa
6995 #define GCEA_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                            0xc
6996 #define GCEA_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                            0xe
6997 #define GCEA_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                            0x10
6998 #define GCEA_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                            0x12
6999 #define GCEA_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                           0x14
7000 #define GCEA_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                           0x16
7001 #define GCEA_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                           0x18
7002 #define GCEA_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                           0x1a
7003 #define GCEA_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                           0x1c
7004 #define GCEA_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                           0x1e
7005 #define GCEA_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                              0x00000003L
7006 #define GCEA_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                              0x0000000CL
7007 #define GCEA_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                              0x00000030L
7008 #define GCEA_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                              0x000000C0L
7009 #define GCEA_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                              0x00000300L
7010 #define GCEA_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                              0x00000C00L
7011 #define GCEA_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                              0x00003000L
7012 #define GCEA_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                              0x0000C000L
7013 #define GCEA_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                              0x00030000L
7014 #define GCEA_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                              0x000C0000L
7015 #define GCEA_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                             0x00300000L
7016 #define GCEA_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                             0x00C00000L
7017 #define GCEA_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                             0x03000000L
7018 #define GCEA_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                             0x0C000000L
7019 #define GCEA_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                             0x30000000L
7020 #define GCEA_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                             0xC0000000L
7021 //GCEA_IO_RD_CLI2GRP_MAP1
7022 #define GCEA_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                           0x0
7023 #define GCEA_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                           0x2
7024 #define GCEA_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                           0x4
7025 #define GCEA_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                           0x6
7026 #define GCEA_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                           0x8
7027 #define GCEA_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                           0xa
7028 #define GCEA_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                           0xc
7029 #define GCEA_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                           0xe
7030 #define GCEA_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                           0x10
7031 #define GCEA_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                           0x12
7032 #define GCEA_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                           0x14
7033 #define GCEA_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                           0x16
7034 #define GCEA_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                           0x18
7035 #define GCEA_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                           0x1a
7036 #define GCEA_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                           0x1c
7037 #define GCEA_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                           0x1e
7038 #define GCEA_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                             0x00000003L
7039 #define GCEA_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                             0x0000000CL
7040 #define GCEA_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                             0x00000030L
7041 #define GCEA_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                             0x000000C0L
7042 #define GCEA_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                             0x00000300L
7043 #define GCEA_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                             0x00000C00L
7044 #define GCEA_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                             0x00003000L
7045 #define GCEA_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                             0x0000C000L
7046 #define GCEA_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                             0x00030000L
7047 #define GCEA_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                             0x000C0000L
7048 #define GCEA_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                             0x00300000L
7049 #define GCEA_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                             0x00C00000L
7050 #define GCEA_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                             0x03000000L
7051 #define GCEA_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                             0x0C000000L
7052 #define GCEA_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                             0x30000000L
7053 #define GCEA_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                             0xC0000000L
7054 //GCEA_IO_WR_CLI2GRP_MAP0
7055 #define GCEA_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                            0x0
7056 #define GCEA_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                            0x2
7057 #define GCEA_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                            0x4
7058 #define GCEA_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                            0x6
7059 #define GCEA_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                            0x8
7060 #define GCEA_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                            0xa
7061 #define GCEA_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                            0xc
7062 #define GCEA_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                            0xe
7063 #define GCEA_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                            0x10
7064 #define GCEA_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                            0x12
7065 #define GCEA_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                           0x14
7066 #define GCEA_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                           0x16
7067 #define GCEA_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                           0x18
7068 #define GCEA_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                           0x1a
7069 #define GCEA_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                           0x1c
7070 #define GCEA_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                           0x1e
7071 #define GCEA_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                              0x00000003L
7072 #define GCEA_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                              0x0000000CL
7073 #define GCEA_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                              0x00000030L
7074 #define GCEA_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                              0x000000C0L
7075 #define GCEA_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                              0x00000300L
7076 #define GCEA_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                              0x00000C00L
7077 #define GCEA_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                              0x00003000L
7078 #define GCEA_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                              0x0000C000L
7079 #define GCEA_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                              0x00030000L
7080 #define GCEA_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                              0x000C0000L
7081 #define GCEA_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                             0x00300000L
7082 #define GCEA_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                             0x00C00000L
7083 #define GCEA_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                             0x03000000L
7084 #define GCEA_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                             0x0C000000L
7085 #define GCEA_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                             0x30000000L
7086 #define GCEA_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                             0xC0000000L
7087 //GCEA_IO_WR_CLI2GRP_MAP1
7088 #define GCEA_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                           0x0
7089 #define GCEA_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                           0x2
7090 #define GCEA_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                           0x4
7091 #define GCEA_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                           0x6
7092 #define GCEA_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                           0x8
7093 #define GCEA_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                           0xa
7094 #define GCEA_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                           0xc
7095 #define GCEA_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                           0xe
7096 #define GCEA_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                           0x10
7097 #define GCEA_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                           0x12
7098 #define GCEA_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                           0x14
7099 #define GCEA_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                           0x16
7100 #define GCEA_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                           0x18
7101 #define GCEA_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                           0x1a
7102 #define GCEA_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                           0x1c
7103 #define GCEA_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                           0x1e
7104 #define GCEA_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                             0x00000003L
7105 #define GCEA_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                             0x0000000CL
7106 #define GCEA_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                             0x00000030L
7107 #define GCEA_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                             0x000000C0L
7108 #define GCEA_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                             0x00000300L
7109 #define GCEA_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                             0x00000C00L
7110 #define GCEA_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                             0x00003000L
7111 #define GCEA_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                             0x0000C000L
7112 #define GCEA_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                             0x00030000L
7113 #define GCEA_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                             0x000C0000L
7114 #define GCEA_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                             0x00300000L
7115 #define GCEA_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                             0x00C00000L
7116 #define GCEA_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                             0x03000000L
7117 #define GCEA_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                             0x0C000000L
7118 #define GCEA_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                             0x30000000L
7119 #define GCEA_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                             0xC0000000L
7120 //GCEA_IO_RD_COMBINE_FLUSH
7121 #define GCEA_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT                                                         0x0
7122 #define GCEA_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT                                                         0x4
7123 #define GCEA_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT                                                         0x8
7124 #define GCEA_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT                                                         0xc
7125 #define GCEA_IO_RD_COMBINE_FLUSH__COMB_MODE__SHIFT                                                            0x10
7126 #define GCEA_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK                                                           0x0000000FL
7127 #define GCEA_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK                                                           0x000000F0L
7128 #define GCEA_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK                                                           0x00000F00L
7129 #define GCEA_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK                                                           0x0000F000L
7130 #define GCEA_IO_RD_COMBINE_FLUSH__COMB_MODE_MASK                                                              0x00030000L
7131 //GCEA_IO_WR_COMBINE_FLUSH
7132 #define GCEA_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT                                                         0x0
7133 #define GCEA_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT                                                         0x4
7134 #define GCEA_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT                                                         0x8
7135 #define GCEA_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT                                                         0xc
7136 #define GCEA_IO_WR_COMBINE_FLUSH__COMB_MODE__SHIFT                                                            0x10
7137 #define GCEA_IO_WR_COMBINE_FLUSH__DISABLE_MAM_CHAINING__SHIFT                                                 0x12
7138 #define GCEA_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK                                                           0x0000000FL
7139 #define GCEA_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK                                                           0x000000F0L
7140 #define GCEA_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK                                                           0x00000F00L
7141 #define GCEA_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK                                                           0x0000F000L
7142 #define GCEA_IO_WR_COMBINE_FLUSH__COMB_MODE_MASK                                                              0x00030000L
7143 #define GCEA_IO_WR_COMBINE_FLUSH__DISABLE_MAM_CHAINING_MASK                                                   0x00040000L
7144 //GCEA_IO_GROUP_BURST
7145 #define GCEA_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT                                                               0x0
7146 #define GCEA_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT                                                               0x8
7147 #define GCEA_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT                                                               0x10
7148 #define GCEA_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT                                                               0x18
7149 #define GCEA_IO_GROUP_BURST__RD_LIMIT_LO_MASK                                                                 0x000000FFL
7150 #define GCEA_IO_GROUP_BURST__RD_LIMIT_HI_MASK                                                                 0x0000FF00L
7151 #define GCEA_IO_GROUP_BURST__WR_LIMIT_LO_MASK                                                                 0x00FF0000L
7152 #define GCEA_IO_GROUP_BURST__WR_LIMIT_HI_MASK                                                                 0xFF000000L
7153 //GCEA_IO_RD_PRI_AGE
7154 #define GCEA_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                          0x0
7155 #define GCEA_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                          0x3
7156 #define GCEA_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                          0x6
7157 #define GCEA_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                          0x9
7158 #define GCEA_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                     0xc
7159 #define GCEA_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                     0xf
7160 #define GCEA_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                     0x12
7161 #define GCEA_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                     0x15
7162 #define GCEA_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                            0x00000007L
7163 #define GCEA_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                            0x00000038L
7164 #define GCEA_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                            0x000001C0L
7165 #define GCEA_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                            0x00000E00L
7166 #define GCEA_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                       0x00007000L
7167 #define GCEA_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                       0x00038000L
7168 #define GCEA_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                       0x001C0000L
7169 #define GCEA_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                       0x00E00000L
7170 //GCEA_IO_WR_PRI_AGE
7171 #define GCEA_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                          0x0
7172 #define GCEA_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                          0x3
7173 #define GCEA_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                          0x6
7174 #define GCEA_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                          0x9
7175 #define GCEA_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                     0xc
7176 #define GCEA_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                     0xf
7177 #define GCEA_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                     0x12
7178 #define GCEA_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                     0x15
7179 #define GCEA_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                            0x00000007L
7180 #define GCEA_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                            0x00000038L
7181 #define GCEA_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                            0x000001C0L
7182 #define GCEA_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                            0x00000E00L
7183 #define GCEA_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                       0x00007000L
7184 #define GCEA_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                       0x00038000L
7185 #define GCEA_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                       0x001C0000L
7186 #define GCEA_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                       0x00E00000L
7187 //GCEA_IO_RD_PRI_QUEUING
7188 #define GCEA_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                             0x0
7189 #define GCEA_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                             0x3
7190 #define GCEA_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                             0x6
7191 #define GCEA_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                             0x9
7192 #define GCEA_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                               0x00000007L
7193 #define GCEA_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                               0x00000038L
7194 #define GCEA_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                               0x000001C0L
7195 #define GCEA_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                               0x00000E00L
7196 //GCEA_IO_WR_PRI_QUEUING
7197 #define GCEA_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                             0x0
7198 #define GCEA_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                             0x3
7199 #define GCEA_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                             0x6
7200 #define GCEA_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                             0x9
7201 #define GCEA_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                               0x00000007L
7202 #define GCEA_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                               0x00000038L
7203 #define GCEA_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                               0x000001C0L
7204 #define GCEA_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                               0x00000E00L
7205 //GCEA_IO_RD_PRI_FIXED
7206 #define GCEA_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                                 0x0
7207 #define GCEA_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                                 0x3
7208 #define GCEA_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                                 0x6
7209 #define GCEA_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                                 0x9
7210 #define GCEA_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                   0x00000007L
7211 #define GCEA_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                   0x00000038L
7212 #define GCEA_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                   0x000001C0L
7213 #define GCEA_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                   0x00000E00L
7214 //GCEA_IO_WR_PRI_FIXED
7215 #define GCEA_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                                 0x0
7216 #define GCEA_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                                 0x3
7217 #define GCEA_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                                 0x6
7218 #define GCEA_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                                 0x9
7219 #define GCEA_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                   0x00000007L
7220 #define GCEA_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                   0x00000038L
7221 #define GCEA_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                   0x000001C0L
7222 #define GCEA_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                   0x00000E00L
7223 //GCEA_IO_RD_PRI_URGENCY
7224 #define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                             0x0
7225 #define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                             0x3
7226 #define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                             0x6
7227 #define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                             0x9
7228 #define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                    0xc
7229 #define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                    0xd
7230 #define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                    0xe
7231 #define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                    0xf
7232 #define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                               0x00000007L
7233 #define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                               0x00000038L
7234 #define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                               0x000001C0L
7235 #define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                               0x00000E00L
7236 #define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                      0x00001000L
7237 #define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                      0x00002000L
7238 #define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                      0x00004000L
7239 #define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                      0x00008000L
7240 //GCEA_IO_WR_PRI_URGENCY
7241 #define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                             0x0
7242 #define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                             0x3
7243 #define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                             0x6
7244 #define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                             0x9
7245 #define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                    0xc
7246 #define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                    0xd
7247 #define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                    0xe
7248 #define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                    0xf
7249 #define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                               0x00000007L
7250 #define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                               0x00000038L
7251 #define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                               0x000001C0L
7252 #define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                               0x00000E00L
7253 #define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                      0x00001000L
7254 #define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                      0x00002000L
7255 #define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                      0x00004000L
7256 #define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                      0x00008000L
7257 //GCEA_IO_RD_PRI_URGENCY_MASKING
7258 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                      0x0
7259 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                      0x1
7260 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                      0x2
7261 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                      0x3
7262 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                      0x4
7263 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                      0x5
7264 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                      0x6
7265 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                      0x7
7266 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                      0x8
7267 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                      0x9
7268 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                     0xa
7269 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                     0xb
7270 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                     0xc
7271 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                     0xd
7272 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                     0xe
7273 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                     0xf
7274 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                     0x10
7275 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                     0x11
7276 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                     0x12
7277 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                     0x13
7278 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                     0x14
7279 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                     0x15
7280 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                     0x16
7281 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                     0x17
7282 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                     0x18
7283 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                     0x19
7284 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                     0x1a
7285 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                     0x1b
7286 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                     0x1c
7287 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                     0x1d
7288 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                     0x1e
7289 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                     0x1f
7290 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                        0x00000001L
7291 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                        0x00000002L
7292 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                        0x00000004L
7293 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                        0x00000008L
7294 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                        0x00000010L
7295 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                        0x00000020L
7296 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                        0x00000040L
7297 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                        0x00000080L
7298 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                        0x00000100L
7299 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                        0x00000200L
7300 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                       0x00000400L
7301 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                       0x00000800L
7302 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                       0x00001000L
7303 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                       0x00002000L
7304 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                       0x00004000L
7305 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                       0x00008000L
7306 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                       0x00010000L
7307 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                       0x00020000L
7308 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                       0x00040000L
7309 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                       0x00080000L
7310 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                       0x00100000L
7311 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                       0x00200000L
7312 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                       0x00400000L
7313 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                       0x00800000L
7314 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                       0x01000000L
7315 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                       0x02000000L
7316 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                       0x04000000L
7317 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                       0x08000000L
7318 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                       0x10000000L
7319 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                       0x20000000L
7320 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                       0x40000000L
7321 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                       0x80000000L
7322 //GCEA_IO_WR_PRI_URGENCY_MASKING
7323 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                      0x0
7324 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                      0x1
7325 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                      0x2
7326 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                      0x3
7327 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                      0x4
7328 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                      0x5
7329 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                      0x6
7330 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                      0x7
7331 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                      0x8
7332 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                      0x9
7333 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                     0xa
7334 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                     0xb
7335 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                     0xc
7336 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                     0xd
7337 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                     0xe
7338 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                     0xf
7339 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                     0x10
7340 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                     0x11
7341 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                     0x12
7342 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                     0x13
7343 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                     0x14
7344 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                     0x15
7345 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                     0x16
7346 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                     0x17
7347 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                     0x18
7348 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                     0x19
7349 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                     0x1a
7350 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                     0x1b
7351 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                     0x1c
7352 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                     0x1d
7353 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                     0x1e
7354 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                     0x1f
7355 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                        0x00000001L
7356 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                        0x00000002L
7357 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                        0x00000004L
7358 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                        0x00000008L
7359 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                        0x00000010L
7360 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                        0x00000020L
7361 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                        0x00000040L
7362 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                        0x00000080L
7363 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                        0x00000100L
7364 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                        0x00000200L
7365 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                       0x00000400L
7366 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                       0x00000800L
7367 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                       0x00001000L
7368 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                       0x00002000L
7369 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                       0x00004000L
7370 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                       0x00008000L
7371 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                       0x00010000L
7372 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                       0x00020000L
7373 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                       0x00040000L
7374 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                       0x00080000L
7375 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                       0x00100000L
7376 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                       0x00200000L
7377 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                       0x00400000L
7378 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                       0x00800000L
7379 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                       0x01000000L
7380 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                       0x02000000L
7381 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                       0x04000000L
7382 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                       0x08000000L
7383 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                       0x10000000L
7384 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                       0x20000000L
7385 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                       0x40000000L
7386 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                       0x80000000L
7387 //GCEA_IO_RD_PRI_QUANT_PRI1
7388 #define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                    0x0
7389 #define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                    0x8
7390 #define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                    0x10
7391 #define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                    0x18
7392 #define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                      0x000000FFL
7393 #define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                      0x0000FF00L
7394 #define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                      0x00FF0000L
7395 #define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                      0xFF000000L
7396 //GCEA_IO_RD_PRI_QUANT_PRI2
7397 #define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                    0x0
7398 #define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                    0x8
7399 #define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                    0x10
7400 #define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                    0x18
7401 #define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                      0x000000FFL
7402 #define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                      0x0000FF00L
7403 #define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                      0x00FF0000L
7404 #define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                      0xFF000000L
7405 //GCEA_IO_RD_PRI_QUANT_PRI3
7406 #define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                    0x0
7407 #define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                    0x8
7408 #define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                    0x10
7409 #define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                    0x18
7410 #define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                      0x000000FFL
7411 #define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                      0x0000FF00L
7412 #define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                      0x00FF0000L
7413 #define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                      0xFF000000L
7414 //GCEA_IO_WR_PRI_QUANT_PRI1
7415 #define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                    0x0
7416 #define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                    0x8
7417 #define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                    0x10
7418 #define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                    0x18
7419 #define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                      0x000000FFL
7420 #define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                      0x0000FF00L
7421 #define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                      0x00FF0000L
7422 #define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                      0xFF000000L
7423 //GCEA_IO_WR_PRI_QUANT_PRI2
7424 #define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                    0x0
7425 #define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                    0x8
7426 #define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                    0x10
7427 #define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                    0x18
7428 #define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                      0x000000FFL
7429 #define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                      0x0000FF00L
7430 #define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                      0x00FF0000L
7431 #define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                      0xFF000000L
7432 //GCEA_IO_WR_PRI_QUANT_PRI3
7433 #define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                    0x0
7434 #define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                    0x8
7435 #define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                    0x10
7436 #define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                    0x18
7437 #define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                      0x000000FFL
7438 #define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                      0x0000FF00L
7439 #define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                      0x00FF0000L
7440 #define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                      0xFF000000L
7441 //GCEA_SDP_ARB_DRAM
7442 #define GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT                                                       0x0
7443 #define GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT                                                       0x8
7444 #define GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT                                                          0x10
7445 #define GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT                                                          0x11
7446 #define GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT                                                          0x12
7447 #define GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT                                                          0x13
7448 #define GCEA_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT                                                               0x14
7449 #define GCEA_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT                                                      0x15
7450 #define GCEA_SDP_ARB_DRAM__ALLOW_CHAIN_BREAKING__SHIFT                                                        0x16
7451 #define GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK                                                         0x0000007FL
7452 #define GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK                                                         0x00007F00L
7453 #define GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK                                                            0x00010000L
7454 #define GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK                                                            0x00020000L
7455 #define GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK                                                            0x00040000L
7456 #define GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK                                                            0x00080000L
7457 #define GCEA_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK                                                                 0x00100000L
7458 #define GCEA_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK                                                        0x00200000L
7459 #define GCEA_SDP_ARB_DRAM__ALLOW_CHAIN_BREAKING_MASK                                                          0x00400000L
7460 //GCEA_SDP_ARB_FINAL
7461 #define GCEA_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT                                                           0x0
7462 #define GCEA_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT                                                            0x5
7463 #define GCEA_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT                                                             0xa
7464 #define GCEA_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT                                                     0xf
7465 #define GCEA_SDP_ARB_FINAL__RDONLY_VC0__SHIFT                                                                 0x11
7466 #define GCEA_SDP_ARB_FINAL__RDONLY_VC1__SHIFT                                                                 0x12
7467 #define GCEA_SDP_ARB_FINAL__RDONLY_VC2__SHIFT                                                                 0x13
7468 #define GCEA_SDP_ARB_FINAL__RDONLY_VC3__SHIFT                                                                 0x14
7469 #define GCEA_SDP_ARB_FINAL__RDONLY_VC4__SHIFT                                                                 0x15
7470 #define GCEA_SDP_ARB_FINAL__RDONLY_VC5__SHIFT                                                                 0x16
7471 #define GCEA_SDP_ARB_FINAL__RDONLY_VC6__SHIFT                                                                 0x17
7472 #define GCEA_SDP_ARB_FINAL__RDONLY_VC7__SHIFT                                                                 0x18
7473 #define GCEA_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT                                                          0x19
7474 #define GCEA_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT                                                           0x1a
7475 #define GCEA_SDP_ARB_FINAL__DRAM_BURST_STRETCH__SHIFT                                                         0x1b
7476 #define GCEA_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT                                                          0x1c
7477 #define GCEA_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK                                                             0x0000001FL
7478 #define GCEA_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK                                                              0x000003E0L
7479 #define GCEA_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK                                                               0x00007C00L
7480 #define GCEA_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK                                                       0x00018000L
7481 #define GCEA_SDP_ARB_FINAL__RDONLY_VC0_MASK                                                                   0x00020000L
7482 #define GCEA_SDP_ARB_FINAL__RDONLY_VC1_MASK                                                                   0x00040000L
7483 #define GCEA_SDP_ARB_FINAL__RDONLY_VC2_MASK                                                                   0x00080000L
7484 #define GCEA_SDP_ARB_FINAL__RDONLY_VC3_MASK                                                                   0x00100000L
7485 #define GCEA_SDP_ARB_FINAL__RDONLY_VC4_MASK                                                                   0x00200000L
7486 #define GCEA_SDP_ARB_FINAL__RDONLY_VC5_MASK                                                                   0x00400000L
7487 #define GCEA_SDP_ARB_FINAL__RDONLY_VC6_MASK                                                                   0x00800000L
7488 #define GCEA_SDP_ARB_FINAL__RDONLY_VC7_MASK                                                                   0x01000000L
7489 #define GCEA_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK                                                            0x02000000L
7490 #define GCEA_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK                                                             0x04000000L
7491 #define GCEA_SDP_ARB_FINAL__DRAM_BURST_STRETCH_MASK                                                           0x08000000L
7492 #define GCEA_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK                                                            0x10000000L
7493 //GCEA_SDP_DRAM_PRIORITY
7494 #define GCEA_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                     0x0
7495 #define GCEA_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                     0x4
7496 #define GCEA_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                     0x8
7497 #define GCEA_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                     0xc
7498 #define GCEA_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                     0x10
7499 #define GCEA_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                     0x14
7500 #define GCEA_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                     0x18
7501 #define GCEA_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                     0x1c
7502 #define GCEA_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                       0x0000000FL
7503 #define GCEA_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                       0x000000F0L
7504 #define GCEA_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                       0x00000F00L
7505 #define GCEA_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                       0x0000F000L
7506 #define GCEA_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                       0x000F0000L
7507 #define GCEA_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                       0x00F00000L
7508 #define GCEA_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                       0x0F000000L
7509 #define GCEA_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                       0xF0000000L
7510 //GCEA_SDP_IO_PRIORITY
7511 #define GCEA_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                       0x0
7512 #define GCEA_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                       0x4
7513 #define GCEA_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                       0x8
7514 #define GCEA_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                       0xc
7515 #define GCEA_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                       0x10
7516 #define GCEA_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                       0x14
7517 #define GCEA_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                       0x18
7518 #define GCEA_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                       0x1c
7519 #define GCEA_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                         0x0000000FL
7520 #define GCEA_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                         0x000000F0L
7521 #define GCEA_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                         0x00000F00L
7522 #define GCEA_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                         0x0000F000L
7523 #define GCEA_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                         0x000F0000L
7524 #define GCEA_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                         0x00F00000L
7525 #define GCEA_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                         0x0F000000L
7526 #define GCEA_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                         0xF0000000L
7527 //GCEA_SDP_CREDITS
7528 #define GCEA_SDP_CREDITS__TAG_LIMIT__SHIFT                                                                    0x0
7529 #define GCEA_SDP_CREDITS__WR_RESP_CREDITS__SHIFT                                                              0x8
7530 #define GCEA_SDP_CREDITS__RD_RESP_CREDITS__SHIFT                                                              0x10
7531 #define GCEA_SDP_CREDITS__PRB_REQ_CREDITS__SHIFT                                                              0x18
7532 #define GCEA_SDP_CREDITS__TAG_LIMIT_MASK                                                                      0x000000FFL
7533 #define GCEA_SDP_CREDITS__WR_RESP_CREDITS_MASK                                                                0x00007F00L
7534 #define GCEA_SDP_CREDITS__RD_RESP_CREDITS_MASK                                                                0x007F0000L
7535 #define GCEA_SDP_CREDITS__PRB_REQ_CREDITS_MASK                                                                0x3F000000L
7536 //GCEA_SDP_TAG_RESERVE0
7537 #define GCEA_SDP_TAG_RESERVE0__VC0__SHIFT                                                                     0x0
7538 #define GCEA_SDP_TAG_RESERVE0__VC1__SHIFT                                                                     0x8
7539 #define GCEA_SDP_TAG_RESERVE0__VC2__SHIFT                                                                     0x10
7540 #define GCEA_SDP_TAG_RESERVE0__VC3__SHIFT                                                                     0x18
7541 #define GCEA_SDP_TAG_RESERVE0__VC0_MASK                                                                       0x000000FFL
7542 #define GCEA_SDP_TAG_RESERVE0__VC1_MASK                                                                       0x0000FF00L
7543 #define GCEA_SDP_TAG_RESERVE0__VC2_MASK                                                                       0x00FF0000L
7544 #define GCEA_SDP_TAG_RESERVE0__VC3_MASK                                                                       0xFF000000L
7545 //GCEA_SDP_TAG_RESERVE1
7546 #define GCEA_SDP_TAG_RESERVE1__VC4__SHIFT                                                                     0x0
7547 #define GCEA_SDP_TAG_RESERVE1__VC5__SHIFT                                                                     0x8
7548 #define GCEA_SDP_TAG_RESERVE1__VC6__SHIFT                                                                     0x10
7549 #define GCEA_SDP_TAG_RESERVE1__VC7__SHIFT                                                                     0x18
7550 #define GCEA_SDP_TAG_RESERVE1__VC4_MASK                                                                       0x000000FFL
7551 #define GCEA_SDP_TAG_RESERVE1__VC5_MASK                                                                       0x0000FF00L
7552 #define GCEA_SDP_TAG_RESERVE1__VC6_MASK                                                                       0x00FF0000L
7553 #define GCEA_SDP_TAG_RESERVE1__VC7_MASK                                                                       0xFF000000L
7554 //GCEA_SDP_VCC_RESERVE0
7555 #define GCEA_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT                                                             0x0
7556 #define GCEA_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT                                                             0x6
7557 #define GCEA_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT                                                             0xc
7558 #define GCEA_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT                                                             0x12
7559 #define GCEA_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT                                                             0x18
7560 #define GCEA_SDP_VCC_RESERVE0__VC0_CREDITS_MASK                                                               0x0000003FL
7561 #define GCEA_SDP_VCC_RESERVE0__VC1_CREDITS_MASK                                                               0x00000FC0L
7562 #define GCEA_SDP_VCC_RESERVE0__VC2_CREDITS_MASK                                                               0x0003F000L
7563 #define GCEA_SDP_VCC_RESERVE0__VC3_CREDITS_MASK                                                               0x00FC0000L
7564 #define GCEA_SDP_VCC_RESERVE0__VC4_CREDITS_MASK                                                               0x3F000000L
7565 //GCEA_SDP_VCC_RESERVE1
7566 #define GCEA_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT                                                             0x0
7567 #define GCEA_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT                                                             0x6
7568 #define GCEA_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT                                                             0xc
7569 #define GCEA_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT                                                         0x1f
7570 #define GCEA_SDP_VCC_RESERVE1__VC5_CREDITS_MASK                                                               0x0000003FL
7571 #define GCEA_SDP_VCC_RESERVE1__VC6_CREDITS_MASK                                                               0x00000FC0L
7572 #define GCEA_SDP_VCC_RESERVE1__VC7_CREDITS_MASK                                                               0x0003F000L
7573 #define GCEA_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK                                                           0x80000000L
7574 //GCEA_SDP_VCD_RESERVE0
7575 #define GCEA_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT                                                             0x0
7576 #define GCEA_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT                                                             0x6
7577 #define GCEA_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT                                                             0xc
7578 #define GCEA_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT                                                             0x12
7579 #define GCEA_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT                                                             0x18
7580 #define GCEA_SDP_VCD_RESERVE0__VC0_CREDITS_MASK                                                               0x0000003FL
7581 #define GCEA_SDP_VCD_RESERVE0__VC1_CREDITS_MASK                                                               0x00000FC0L
7582 #define GCEA_SDP_VCD_RESERVE0__VC2_CREDITS_MASK                                                               0x0003F000L
7583 #define GCEA_SDP_VCD_RESERVE0__VC3_CREDITS_MASK                                                               0x00FC0000L
7584 #define GCEA_SDP_VCD_RESERVE0__VC4_CREDITS_MASK                                                               0x3F000000L
7585 //GCEA_SDP_VCD_RESERVE1
7586 #define GCEA_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT                                                             0x0
7587 #define GCEA_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT                                                             0x6
7588 #define GCEA_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT                                                             0xc
7589 #define GCEA_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT                                                         0x1f
7590 #define GCEA_SDP_VCD_RESERVE1__VC5_CREDITS_MASK                                                               0x0000003FL
7591 #define GCEA_SDP_VCD_RESERVE1__VC6_CREDITS_MASK                                                               0x00000FC0L
7592 #define GCEA_SDP_VCD_RESERVE1__VC7_CREDITS_MASK                                                               0x0003F000L
7593 #define GCEA_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK                                                           0x80000000L
7594 //GCEA_SDP_REQ_CNTL
7595 #define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT                                                   0x0
7596 #define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT                                                  0x1
7597 #define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT                                                 0x2
7598 #define GCEA_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT                                                     0x3
7599 #define GCEA_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT                                                      0x4
7600 #define GCEA_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT                                                           0x5
7601 #define GCEA_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT                                                        0x6
7602 #define GCEA_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT                                                       0x8
7603 #define GCEA_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT                                                      0xa
7604 #define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK                                                     0x00000001L
7605 #define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK                                                    0x00000002L
7606 #define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK                                                   0x00000004L
7607 #define GCEA_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK                                                       0x00000008L
7608 #define GCEA_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK                                                        0x00000010L
7609 #define GCEA_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK                                                             0x00000020L
7610 #define GCEA_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK                                                          0x000000C0L
7611 #define GCEA_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK                                                         0x00000300L
7612 #define GCEA_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK                                                        0x00000C00L
7613 //GCEA_MISC
7614 #define GCEA_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT                                                         0x0
7615 #define GCEA_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT                                                         0x1
7616 #define GCEA_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT                                                          0x2
7617 #define GCEA_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT                                                          0x3
7618 #define GCEA_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT                                                           0x4
7619 #define GCEA_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT                                                           0x5
7620 #define GCEA_MISC__EARLYWRRET_ENABLE_VC0__SHIFT                                                               0x6
7621 #define GCEA_MISC__EARLYWRRET_ENABLE_VC1__SHIFT                                                               0x7
7622 #define GCEA_MISC__EARLYWRRET_ENABLE_VC2__SHIFT                                                               0x8
7623 #define GCEA_MISC__EARLYWRRET_ENABLE_VC3__SHIFT                                                               0x9
7624 #define GCEA_MISC__EARLYWRRET_ENABLE_VC4__SHIFT                                                               0xa
7625 #define GCEA_MISC__EARLYWRRET_ENABLE_VC5__SHIFT                                                               0xb
7626 #define GCEA_MISC__EARLYWRRET_ENABLE_VC6__SHIFT                                                               0xc
7627 #define GCEA_MISC__EARLYWRRET_ENABLE_VC7__SHIFT                                                               0xd
7628 #define GCEA_MISC__EARLY_SDP_ORIGDATA__SHIFT                                                                  0xe
7629 #define GCEA_MISC__LINKMGR_DYNAMIC_MODE__SHIFT                                                                0xf
7630 #define GCEA_MISC__LINKMGR_HALT_THRESHOLD__SHIFT                                                              0x11
7631 #define GCEA_MISC__LINKMGR_RECONNECT_DELAY__SHIFT                                                             0x13
7632 #define GCEA_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT                                                              0x15
7633 #define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT                                                      0x1a
7634 #define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT                                                       0x1b
7635 #define GCEA_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT                                                          0x1c
7636 #define GCEA_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT                                                           0x1d
7637 #define GCEA_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT                                                        0x1e
7638 #define GCEA_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT                                                         0x1f
7639 #define GCEA_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK                                                           0x00000001L
7640 #define GCEA_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK                                                           0x00000002L
7641 #define GCEA_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK                                                            0x00000004L
7642 #define GCEA_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK                                                            0x00000008L
7643 #define GCEA_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK                                                             0x00000010L
7644 #define GCEA_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK                                                             0x00000020L
7645 #define GCEA_MISC__EARLYWRRET_ENABLE_VC0_MASK                                                                 0x00000040L
7646 #define GCEA_MISC__EARLYWRRET_ENABLE_VC1_MASK                                                                 0x00000080L
7647 #define GCEA_MISC__EARLYWRRET_ENABLE_VC2_MASK                                                                 0x00000100L
7648 #define GCEA_MISC__EARLYWRRET_ENABLE_VC3_MASK                                                                 0x00000200L
7649 #define GCEA_MISC__EARLYWRRET_ENABLE_VC4_MASK                                                                 0x00000400L
7650 #define GCEA_MISC__EARLYWRRET_ENABLE_VC5_MASK                                                                 0x00000800L
7651 #define GCEA_MISC__EARLYWRRET_ENABLE_VC6_MASK                                                                 0x00001000L
7652 #define GCEA_MISC__EARLYWRRET_ENABLE_VC7_MASK                                                                 0x00002000L
7653 #define GCEA_MISC__EARLY_SDP_ORIGDATA_MASK                                                                    0x00004000L
7654 #define GCEA_MISC__LINKMGR_DYNAMIC_MODE_MASK                                                                  0x00018000L
7655 #define GCEA_MISC__LINKMGR_HALT_THRESHOLD_MASK                                                                0x00060000L
7656 #define GCEA_MISC__LINKMGR_RECONNECT_DELAY_MASK                                                               0x00180000L
7657 #define GCEA_MISC__LINKMGR_IDLE_THRESHOLD_MASK                                                                0x03E00000L
7658 #define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK                                                        0x04000000L
7659 #define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK                                                         0x08000000L
7660 #define GCEA_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK                                                            0x10000000L
7661 #define GCEA_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK                                                             0x20000000L
7662 #define GCEA_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK                                                          0x40000000L
7663 #define GCEA_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK                                                           0x80000000L
7664 //GCEA_LATENCY_SAMPLING
7665 #define GCEA_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT                                                           0x0
7666 #define GCEA_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT                                                           0x1
7667 #define GCEA_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT                                                            0x2
7668 #define GCEA_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT                                                            0x3
7669 #define GCEA_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT                                                             0x4
7670 #define GCEA_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT                                                             0x5
7671 #define GCEA_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT                                                           0x6
7672 #define GCEA_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT                                                           0x7
7673 #define GCEA_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT                                                          0x8
7674 #define GCEA_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT                                                          0x9
7675 #define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT                                                     0xa
7676 #define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT                                                     0xb
7677 #define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT                                                   0xc
7678 #define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT                                                   0xd
7679 #define GCEA_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT                                                             0xe
7680 #define GCEA_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT                                                             0x16
7681 #define GCEA_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK                                                             0x00000001L
7682 #define GCEA_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK                                                             0x00000002L
7683 #define GCEA_LATENCY_SAMPLING__SAMPLER0_GMI_MASK                                                              0x00000004L
7684 #define GCEA_LATENCY_SAMPLING__SAMPLER1_GMI_MASK                                                              0x00000008L
7685 #define GCEA_LATENCY_SAMPLING__SAMPLER0_IO_MASK                                                               0x00000010L
7686 #define GCEA_LATENCY_SAMPLING__SAMPLER1_IO_MASK                                                               0x00000020L
7687 #define GCEA_LATENCY_SAMPLING__SAMPLER0_READ_MASK                                                             0x00000040L
7688 #define GCEA_LATENCY_SAMPLING__SAMPLER1_READ_MASK                                                             0x00000080L
7689 #define GCEA_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK                                                            0x00000100L
7690 #define GCEA_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK                                                            0x00000200L
7691 #define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK                                                       0x00000400L
7692 #define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK                                                       0x00000800L
7693 #define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK                                                     0x00001000L
7694 #define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK                                                     0x00002000L
7695 #define GCEA_LATENCY_SAMPLING__SAMPLER0_VC_MASK                                                               0x003FC000L
7696 #define GCEA_LATENCY_SAMPLING__SAMPLER1_VC_MASK                                                               0x3FC00000L
7697 //GCEA_PERFCOUNTER_LO
7698 #define GCEA_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                                0x0
7699 #define GCEA_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                  0xFFFFFFFFL
7700 //GCEA_PERFCOUNTER_HI
7701 #define GCEA_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                                0x0
7702 #define GCEA_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                             0x10
7703 #define GCEA_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                  0x0000FFFFL
7704 #define GCEA_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                               0xFFFF0000L
7705 //GCEA_PERFCOUNTER0_CFG
7706 #define GCEA_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                                0x0
7707 #define GCEA_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                            0x8
7708 #define GCEA_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                               0x18
7709 #define GCEA_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                  0x1c
7710 #define GCEA_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                   0x1d
7711 #define GCEA_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                  0x000000FFL
7712 #define GCEA_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                              0x0000FF00L
7713 #define GCEA_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                                 0x0F000000L
7714 #define GCEA_PERFCOUNTER0_CFG__ENABLE_MASK                                                                    0x10000000L
7715 #define GCEA_PERFCOUNTER0_CFG__CLEAR_MASK                                                                     0x20000000L
7716 //GCEA_PERFCOUNTER1_CFG
7717 #define GCEA_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                                0x0
7718 #define GCEA_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                            0x8
7719 #define GCEA_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                               0x18
7720 #define GCEA_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                  0x1c
7721 #define GCEA_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                   0x1d
7722 #define GCEA_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                  0x000000FFL
7723 #define GCEA_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                              0x0000FF00L
7724 #define GCEA_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                                 0x0F000000L
7725 #define GCEA_PERFCOUNTER1_CFG__ENABLE_MASK                                                                    0x10000000L
7726 #define GCEA_PERFCOUNTER1_CFG__CLEAR_MASK                                                                     0x20000000L
7727 
7728 
7729 // addressBlock: xcd0_gc_ea_gceadec2
7730 //GCEA_PERFCOUNTER_RSLT_CNTL
7731 #define GCEA_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                                0x0
7732 #define GCEA_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                      0x8
7733 #define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                       0x10
7734 #define GCEA_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                         0x18
7735 #define GCEA_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                          0x19
7736 #define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                               0x1a
7737 #define GCEA_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                  0x0000000FL
7738 #define GCEA_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                        0x0000FF00L
7739 #define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                         0x00FF0000L
7740 #define GCEA_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                           0x01000000L
7741 #define GCEA_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                            0x02000000L
7742 #define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                                 0x04000000L
7743 //GCEA_MAM_CTRL
7744 #define GCEA_MAM_CTRL__ADRAM_MODE__SHIFT                                                                      0x0
7745 #define GCEA_MAM_CTRL__ADRAM_COALESCE_DISABLE__SHIFT                                                          0x2
7746 #define GCEA_MAM_CTRL__ARAM_FLUSH_CNTR_THRESHOLD__SHIFT                                                       0x3
7747 #define GCEA_MAM_CTRL__ARAM_FLUSH_CNTR_DISABLE__SHIFT                                                         0x6
7748 #define GCEA_MAM_CTRL__ARAM_FORCE_FLUSH__SHIFT                                                                0x7
7749 #define GCEA_MAM_CTRL__ALOG_MODE1_FILTER1_THRESHOLD__SHIFT                                                    0x8
7750 #define GCEA_MAM_CTRL__ALOG_MODE1_FILTER2_BYPASS__SHIFT                                                       0xb
7751 #define GCEA_MAM_CTRL__ALOG_ACTIVE__SHIFT                                                                     0xc
7752 #define GCEA_MAM_CTRL__SDP_PRIORITY__SHIFT                                                                    0xd
7753 #define GCEA_MAM_CTRL__CLIENT_ID__SHIFT                                                                       0x11
7754 #define GCEA_MAM_CTRL__MAM_DISABLE__SHIFT                                                                     0x16
7755 #define GCEA_MAM_CTRL__ARAM_FLUSH_RB_SIZE__SHIFT                                                              0x17
7756 #define GCEA_MAM_CTRL__ALOG_MODE__SHIFT                                                                       0x1b
7757 #define GCEA_MAM_CTRL__ALOG_MODE2_LOCK_WINDOW__SHIFT                                                          0x1c
7758 #define GCEA_MAM_CTRL__ALOG_TRACK_2M_SEGMENT__SHIFT                                                           0x1f
7759 #define GCEA_MAM_CTRL__ADRAM_MODE_MASK                                                                        0x00000003L
7760 #define GCEA_MAM_CTRL__ADRAM_COALESCE_DISABLE_MASK                                                            0x00000004L
7761 #define GCEA_MAM_CTRL__ARAM_FLUSH_CNTR_THRESHOLD_MASK                                                         0x00000038L
7762 #define GCEA_MAM_CTRL__ARAM_FLUSH_CNTR_DISABLE_MASK                                                           0x00000040L
7763 #define GCEA_MAM_CTRL__ARAM_FORCE_FLUSH_MASK                                                                  0x00000080L
7764 #define GCEA_MAM_CTRL__ALOG_MODE1_FILTER1_THRESHOLD_MASK                                                      0x00000700L
7765 #define GCEA_MAM_CTRL__ALOG_MODE1_FILTER2_BYPASS_MASK                                                         0x00000800L
7766 #define GCEA_MAM_CTRL__ALOG_ACTIVE_MASK                                                                       0x00001000L
7767 #define GCEA_MAM_CTRL__SDP_PRIORITY_MASK                                                                      0x0001E000L
7768 #define GCEA_MAM_CTRL__CLIENT_ID_MASK                                                                         0x003E0000L
7769 #define GCEA_MAM_CTRL__MAM_DISABLE_MASK                                                                       0x00400000L
7770 #define GCEA_MAM_CTRL__ARAM_FLUSH_RB_SIZE_MASK                                                                0x07800000L
7771 #define GCEA_MAM_CTRL__ALOG_MODE_MASK                                                                         0x08000000L
7772 #define GCEA_MAM_CTRL__ALOG_MODE2_LOCK_WINDOW_MASK                                                            0x70000000L
7773 #define GCEA_MAM_CTRL__ALOG_TRACK_2M_SEGMENT_MASK                                                             0x80000000L
7774 //GCEA_MAM_CTRL2
7775 #define GCEA_MAM_CTRL2__ALOG_MODE2_INTR_THRESHOLD__SHIFT                                                      0x0
7776 #define GCEA_MAM_CTRL2__ALOG_SPACE_EN__SHIFT                                                                  0x2
7777 #define GCEA_MAM_CTRL2__ARAM_FLUSH_SNOOP_EN__SHIFT                                                            0x5
7778 #define GCEA_MAM_CTRL2__ARAM_FLUSH_NOALLOC__SHIFT                                                             0x6
7779 #define GCEA_MAM_CTRL2__RESERVED_FIELD__SHIFT                                                                 0x7
7780 #define GCEA_MAM_CTRL2__ADDR_HI__SHIFT                                                                        0x18
7781 #define GCEA_MAM_CTRL2__ALOG_MODE2_INTR_THRESHOLD_MASK                                                        0x00000003L
7782 #define GCEA_MAM_CTRL2__ALOG_SPACE_EN_MASK                                                                    0x0000001CL
7783 #define GCEA_MAM_CTRL2__ARAM_FLUSH_SNOOP_EN_MASK                                                              0x00000020L
7784 #define GCEA_MAM_CTRL2__ARAM_FLUSH_NOALLOC_MASK                                                               0x00000040L
7785 #define GCEA_MAM_CTRL2__RESERVED_FIELD_MASK                                                                   0x00FFFF80L
7786 #define GCEA_MAM_CTRL2__ADDR_HI_MASK                                                                          0xFF000000L
7787 //GCEA_UE_ERR_STATUS_LO
7788 #define GCEA_UE_ERR_STATUS_LO__STATUS_VALID_FLAG__SHIFT                                                       0x0
7789 #define GCEA_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT                                                      0x1
7790 #define GCEA_UE_ERR_STATUS_LO__ADDRESS__SHIFT                                                                 0x2
7791 #define GCEA_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT                                                               0x18
7792 #define GCEA_UE_ERR_STATUS_LO__STATUS_VALID_FLAG_MASK                                                         0x00000001L
7793 #define GCEA_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK                                                        0x00000002L
7794 #define GCEA_UE_ERR_STATUS_LO__ADDRESS_MASK                                                                   0x00FFFFFCL
7795 #define GCEA_UE_ERR_STATUS_LO__MEMORY_ID_MASK                                                                 0xFF000000L
7796 //GCEA_UE_ERR_STATUS_HI
7797 #define GCEA_UE_ERR_STATUS_HI__ECC__SHIFT                                                                     0x0
7798 #define GCEA_UE_ERR_STATUS_HI__PARITY__SHIFT                                                                  0x1
7799 #define GCEA_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT                                                     0x2
7800 #define GCEA_UE_ERR_STATUS_HI__ERR_INFO__SHIFT                                                                0x3
7801 #define GCEA_UE_ERR_STATUS_HI__UE_CNT__SHIFT                                                                  0x17
7802 #define GCEA_UE_ERR_STATUS_HI__FED_CNT__SHIFT                                                                 0x1a
7803 #define GCEA_UE_ERR_STATUS_HI__RESERVED_FIELD__SHIFT                                                          0x1d
7804 #define GCEA_UE_ERR_STATUS_HI__ECC_MASK                                                                       0x00000001L
7805 #define GCEA_UE_ERR_STATUS_HI__PARITY_MASK                                                                    0x00000002L
7806 #define GCEA_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK                                                       0x00000004L
7807 #define GCEA_UE_ERR_STATUS_HI__ERR_INFO_MASK                                                                  0x007FFFF8L
7808 #define GCEA_UE_ERR_STATUS_HI__UE_CNT_MASK                                                                    0x03800000L
7809 #define GCEA_UE_ERR_STATUS_HI__FED_CNT_MASK                                                                   0x1C000000L
7810 #define GCEA_UE_ERR_STATUS_HI__RESERVED_FIELD_MASK                                                            0xE0000000L
7811 //GCEA_DSM_CNTL
7812 #define GCEA_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x0
7813 #define GCEA_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x2
7814 #define GCEA_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x3
7815 #define GCEA_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x5
7816 #define GCEA_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x6
7817 #define GCEA_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x8
7818 #define GCEA_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT                                                  0x9
7819 #define GCEA_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT                                                 0xb
7820 #define GCEA_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT                                                  0xc
7821 #define GCEA_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT                                                 0xe
7822 #define GCEA_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                 0xf
7823 #define GCEA_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                                0x11
7824 #define GCEA_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                 0x12
7825 #define GCEA_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                                0x14
7826 #define GCEA_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x15
7827 #define GCEA_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x17
7828 #define GCEA_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x00000003L
7829 #define GCEA_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00000004L
7830 #define GCEA_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x00000018L
7831 #define GCEA_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00000020L
7832 #define GCEA_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                 0x000000C0L
7833 #define GCEA_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00000100L
7834 #define GCEA_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK                                                    0x00000600L
7835 #define GCEA_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK                                                   0x00000800L
7836 #define GCEA_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK                                                    0x00003000L
7837 #define GCEA_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK                                                   0x00004000L
7838 #define GCEA_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                   0x00018000L
7839 #define GCEA_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                  0x00020000L
7840 #define GCEA_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                   0x000C0000L
7841 #define GCEA_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                  0x00100000L
7842 #define GCEA_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                  0x00600000L
7843 #define GCEA_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00800000L
7844 //GCEA_DSM_CNTLA
7845 #define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                              0x0
7846 #define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x2
7847 #define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                              0x3
7848 #define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x5
7849 #define GCEA_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                 0x6
7850 #define GCEA_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                                0x8
7851 #define GCEA_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                 0x9
7852 #define GCEA_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                                0xb
7853 #define GCEA_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                                0xc
7854 #define GCEA_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0xe
7855 #define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                               0xf
7856 #define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x11
7857 #define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x12
7858 #define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x14
7859 #define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                                0x00000003L
7860 #define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00000004L
7861 #define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                                0x00000018L
7862 #define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00000020L
7863 #define GCEA_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                   0x000000C0L
7864 #define GCEA_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                  0x00000100L
7865 #define GCEA_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                   0x00000600L
7866 #define GCEA_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                  0x00000800L
7867 #define GCEA_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                  0x00003000L
7868 #define GCEA_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00004000L
7869 #define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00018000L
7870 #define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00020000L
7871 #define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                                 0x000C0000L
7872 #define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00100000L
7873 //GCEA_DSM_CNTLB
7874 #define GCEA_DSM_CNTLB__MAM_D0MEM_DSM_IRRITATOR_DATA__SHIFT                                                   0x0
7875 #define GCEA_DSM_CNTLB__MAM_D0MEM_ENABLE_SINGLE_WRITE__SHIFT                                                  0x2
7876 #define GCEA_DSM_CNTLB__MAM_D1MEM_DSM_IRRITATOR_DATA__SHIFT                                                   0x3
7877 #define GCEA_DSM_CNTLB__MAM_D1MEM_ENABLE_SINGLE_WRITE__SHIFT                                                  0x5
7878 #define GCEA_DSM_CNTLB__MAM_D2MEM_DSM_IRRITATOR_DATA__SHIFT                                                   0x6
7879 #define GCEA_DSM_CNTLB__MAM_D2MEM_ENABLE_SINGLE_WRITE__SHIFT                                                  0x8
7880 #define GCEA_DSM_CNTLB__MAM_D3MEM_DSM_IRRITATOR_DATA__SHIFT                                                   0x9
7881 #define GCEA_DSM_CNTLB__MAM_D3MEM_ENABLE_SINGLE_WRITE__SHIFT                                                  0xb
7882 #define GCEA_DSM_CNTLB__MAM_A0MEM_DSM_IRRITATOR_DATA__SHIFT                                                   0xc
7883 #define GCEA_DSM_CNTLB__MAM_A0MEM_ENABLE_SINGLE_WRITE__SHIFT                                                  0xe
7884 #define GCEA_DSM_CNTLB__MAM_A1MEM_DSM_IRRITATOR_DATA__SHIFT                                                   0xf
7885 #define GCEA_DSM_CNTLB__MAM_A1MEM_ENABLE_SINGLE_WRITE__SHIFT                                                  0x11
7886 #define GCEA_DSM_CNTLB__MAM_A2MEM_DSM_IRRITATOR_DATA__SHIFT                                                   0x12
7887 #define GCEA_DSM_CNTLB__MAM_A2MEM_ENABLE_SINGLE_WRITE__SHIFT                                                  0x14
7888 #define GCEA_DSM_CNTLB__MAM_A3MEM_DSM_IRRITATOR_DATA__SHIFT                                                   0x15
7889 #define GCEA_DSM_CNTLB__MAM_A3MEM_ENABLE_SINGLE_WRITE__SHIFT                                                  0x17
7890 #define GCEA_DSM_CNTLB__MAM_AFMEM_DSM_IRRITATOR_DATA__SHIFT                                                   0x18
7891 #define GCEA_DSM_CNTLB__MAM_AFMEM_ENABLE_SINGLE_WRITE__SHIFT                                                  0x1a
7892 #define GCEA_DSM_CNTLB__MAM_D0MEM_DSM_IRRITATOR_DATA_MASK                                                     0x00000003L
7893 #define GCEA_DSM_CNTLB__MAM_D0MEM_ENABLE_SINGLE_WRITE_MASK                                                    0x00000004L
7894 #define GCEA_DSM_CNTLB__MAM_D1MEM_DSM_IRRITATOR_DATA_MASK                                                     0x00000018L
7895 #define GCEA_DSM_CNTLB__MAM_D1MEM_ENABLE_SINGLE_WRITE_MASK                                                    0x00000020L
7896 #define GCEA_DSM_CNTLB__MAM_D2MEM_DSM_IRRITATOR_DATA_MASK                                                     0x000000C0L
7897 #define GCEA_DSM_CNTLB__MAM_D2MEM_ENABLE_SINGLE_WRITE_MASK                                                    0x00000100L
7898 #define GCEA_DSM_CNTLB__MAM_D3MEM_DSM_IRRITATOR_DATA_MASK                                                     0x00000600L
7899 #define GCEA_DSM_CNTLB__MAM_D3MEM_ENABLE_SINGLE_WRITE_MASK                                                    0x00000800L
7900 #define GCEA_DSM_CNTLB__MAM_A0MEM_DSM_IRRITATOR_DATA_MASK                                                     0x00003000L
7901 #define GCEA_DSM_CNTLB__MAM_A0MEM_ENABLE_SINGLE_WRITE_MASK                                                    0x00004000L
7902 #define GCEA_DSM_CNTLB__MAM_A1MEM_DSM_IRRITATOR_DATA_MASK                                                     0x00018000L
7903 #define GCEA_DSM_CNTLB__MAM_A1MEM_ENABLE_SINGLE_WRITE_MASK                                                    0x00020000L
7904 #define GCEA_DSM_CNTLB__MAM_A2MEM_DSM_IRRITATOR_DATA_MASK                                                     0x000C0000L
7905 #define GCEA_DSM_CNTLB__MAM_A2MEM_ENABLE_SINGLE_WRITE_MASK                                                    0x00100000L
7906 #define GCEA_DSM_CNTLB__MAM_A3MEM_DSM_IRRITATOR_DATA_MASK                                                     0x00600000L
7907 #define GCEA_DSM_CNTLB__MAM_A3MEM_ENABLE_SINGLE_WRITE_MASK                                                    0x00800000L
7908 #define GCEA_DSM_CNTLB__MAM_AFMEM_DSM_IRRITATOR_DATA_MASK                                                     0x03000000L
7909 #define GCEA_DSM_CNTLB__MAM_AFMEM_ENABLE_SINGLE_WRITE_MASK                                                    0x04000000L
7910 //GCEA_DSM_CNTL2
7911 #define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x0
7912 #define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x2
7913 #define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x3
7914 #define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x5
7915 #define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x6
7916 #define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                             0x8
7917 #define GCEA_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT                                                0x9
7918 #define GCEA_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT                                                0xb
7919 #define GCEA_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT                                                0xc
7920 #define GCEA_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT                                                0xe
7921 #define GCEA_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                               0xf
7922 #define GCEA_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                               0x11
7923 #define GCEA_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                               0x12
7924 #define GCEA_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                               0x14
7925 #define GCEA_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x15
7926 #define GCEA_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                              0x17
7927 #define GCEA_DSM_CNTL2__INJECT_DELAY__SHIFT                                                                   0x1a
7928 #define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x00000003L
7929 #define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00000004L
7930 #define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x00000018L
7931 #define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00000020L
7932 #define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                               0x000000C0L
7933 #define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                               0x00000100L
7934 #define GCEA_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK                                                  0x00000600L
7935 #define GCEA_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK                                                  0x00000800L
7936 #define GCEA_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK                                                  0x00003000L
7937 #define GCEA_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK                                                  0x00004000L
7938 #define GCEA_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                 0x00018000L
7939 #define GCEA_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK                                                 0x00020000L
7940 #define GCEA_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                 0x000C0000L
7941 #define GCEA_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                                 0x00100000L
7942 #define GCEA_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                                0x00600000L
7943 #define GCEA_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                                0x00800000L
7944 #define GCEA_DSM_CNTL2__INJECT_DELAY_MASK                                                                     0xFC000000L
7945 //GCEA_DSM_CNTL2A
7946 #define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                            0x0
7947 #define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                            0x2
7948 #define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                            0x3
7949 #define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                            0x5
7950 #define GCEA_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                               0x6
7951 #define GCEA_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                               0x8
7952 #define GCEA_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                               0x9
7953 #define GCEA_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                               0xb
7954 #define GCEA_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                              0xc
7955 #define GCEA_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                              0xe
7956 #define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                             0xf
7957 #define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                             0x11
7958 #define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x12
7959 #define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                             0x14
7960 #define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                              0x00000003L
7961 #define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK                                              0x00000004L
7962 #define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                              0x00000018L
7963 #define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK                                              0x00000020L
7964 #define GCEA_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                 0x000000C0L
7965 #define GCEA_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK                                                 0x00000100L
7966 #define GCEA_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                 0x00000600L
7967 #define GCEA_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                                 0x00000800L
7968 #define GCEA_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                                0x00003000L
7969 #define GCEA_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                                0x00004000L
7970 #define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                               0x00018000L
7971 #define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK                                               0x00020000L
7972 #define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                               0x000C0000L
7973 #define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK                                               0x00100000L
7974 //GCEA_DSM_CNTL2B
7975 #define GCEA_DSM_CNTL2B__MAM_D0MEM_ENABLE_ERROR_INJECT__SHIFT                                                 0x0
7976 #define GCEA_DSM_CNTL2B__MAM_D0MEM_SELECT_INJECT_DELAY__SHIFT                                                 0x2
7977 #define GCEA_DSM_CNTL2B__MAM_D1MEM_ENABLE_ERROR_INJECT__SHIFT                                                 0x3
7978 #define GCEA_DSM_CNTL2B__MAM_D1MEM_SELECT_INJECT_DELAY__SHIFT                                                 0x5
7979 #define GCEA_DSM_CNTL2B__MAM_D2MEM_ENABLE_ERROR_INJECT__SHIFT                                                 0x6
7980 #define GCEA_DSM_CNTL2B__MAM_D2MEM_SELECT_INJECT_DELAY__SHIFT                                                 0x8
7981 #define GCEA_DSM_CNTL2B__MAM_D3MEM_ENABLE_ERROR_INJECT__SHIFT                                                 0x9
7982 #define GCEA_DSM_CNTL2B__MAM_D3MEM_SELECT_INJECT_DELAY__SHIFT                                                 0xb
7983 #define GCEA_DSM_CNTL2B__MAM_A0MEM_ENABLE_ERROR_INJECT__SHIFT                                                 0xc
7984 #define GCEA_DSM_CNTL2B__MAM_A0MEM_SELECT_INJECT_DELAY__SHIFT                                                 0xe
7985 #define GCEA_DSM_CNTL2B__MAM_A1MEM_ENABLE_ERROR_INJECT__SHIFT                                                 0xf
7986 #define GCEA_DSM_CNTL2B__MAM_A1MEM_SELECT_INJECT_DELAY__SHIFT                                                 0x11
7987 #define GCEA_DSM_CNTL2B__MAM_A2MEM_ENABLE_ERROR_INJECT__SHIFT                                                 0x12
7988 #define GCEA_DSM_CNTL2B__MAM_A2MEM_SELECT_INJECT_DELAY__SHIFT                                                 0x14
7989 #define GCEA_DSM_CNTL2B__MAM_A3MEM_ENABLE_ERROR_INJECT__SHIFT                                                 0x15
7990 #define GCEA_DSM_CNTL2B__MAM_A3MEM_SELECT_INJECT_DELAY__SHIFT                                                 0x17
7991 #define GCEA_DSM_CNTL2B__MAM_AFMEM_ENABLE_ERROR_INJECT__SHIFT                                                 0x18
7992 #define GCEA_DSM_CNTL2B__MAM_AFMEM_SELECT_INJECT_DELAY__SHIFT                                                 0x1a
7993 #define GCEA_DSM_CNTL2B__MAM_D0MEM_ENABLE_ERROR_INJECT_MASK                                                   0x00000003L
7994 #define GCEA_DSM_CNTL2B__MAM_D0MEM_SELECT_INJECT_DELAY_MASK                                                   0x00000004L
7995 #define GCEA_DSM_CNTL2B__MAM_D1MEM_ENABLE_ERROR_INJECT_MASK                                                   0x00000018L
7996 #define GCEA_DSM_CNTL2B__MAM_D1MEM_SELECT_INJECT_DELAY_MASK                                                   0x00000020L
7997 #define GCEA_DSM_CNTL2B__MAM_D2MEM_ENABLE_ERROR_INJECT_MASK                                                   0x000000C0L
7998 #define GCEA_DSM_CNTL2B__MAM_D2MEM_SELECT_INJECT_DELAY_MASK                                                   0x00000100L
7999 #define GCEA_DSM_CNTL2B__MAM_D3MEM_ENABLE_ERROR_INJECT_MASK                                                   0x00000600L
8000 #define GCEA_DSM_CNTL2B__MAM_D3MEM_SELECT_INJECT_DELAY_MASK                                                   0x00000800L
8001 #define GCEA_DSM_CNTL2B__MAM_A0MEM_ENABLE_ERROR_INJECT_MASK                                                   0x00003000L
8002 #define GCEA_DSM_CNTL2B__MAM_A0MEM_SELECT_INJECT_DELAY_MASK                                                   0x00004000L
8003 #define GCEA_DSM_CNTL2B__MAM_A1MEM_ENABLE_ERROR_INJECT_MASK                                                   0x00018000L
8004 #define GCEA_DSM_CNTL2B__MAM_A1MEM_SELECT_INJECT_DELAY_MASK                                                   0x00020000L
8005 #define GCEA_DSM_CNTL2B__MAM_A2MEM_ENABLE_ERROR_INJECT_MASK                                                   0x000C0000L
8006 #define GCEA_DSM_CNTL2B__MAM_A2MEM_SELECT_INJECT_DELAY_MASK                                                   0x00100000L
8007 #define GCEA_DSM_CNTL2B__MAM_A3MEM_ENABLE_ERROR_INJECT_MASK                                                   0x00600000L
8008 #define GCEA_DSM_CNTL2B__MAM_A3MEM_SELECT_INJECT_DELAY_MASK                                                   0x00800000L
8009 #define GCEA_DSM_CNTL2B__MAM_AFMEM_ENABLE_ERROR_INJECT_MASK                                                   0x03000000L
8010 #define GCEA_DSM_CNTL2B__MAM_AFMEM_SELECT_INJECT_DELAY_MASK                                                   0x04000000L
8011 //GCEA_TCC_XBR_CREDITS
8012 #define GCEA_TCC_XBR_CREDITS__DRAM_RD_LIMIT__SHIFT                                                            0x0
8013 #define GCEA_TCC_XBR_CREDITS__DRAM_RD_RESERVE__SHIFT                                                          0x6
8014 #define GCEA_TCC_XBR_CREDITS__IO_RD_LIMIT__SHIFT                                                              0x8
8015 #define GCEA_TCC_XBR_CREDITS__IO_RD_RESERVE__SHIFT                                                            0xe
8016 #define GCEA_TCC_XBR_CREDITS__DRAM_WR_LIMIT__SHIFT                                                            0x10
8017 #define GCEA_TCC_XBR_CREDITS__DRAM_WR_RESERVE__SHIFT                                                          0x16
8018 #define GCEA_TCC_XBR_CREDITS__IO_WR_LIMIT__SHIFT                                                              0x18
8019 #define GCEA_TCC_XBR_CREDITS__IO_WR_RESERVE__SHIFT                                                            0x1e
8020 #define GCEA_TCC_XBR_CREDITS__DRAM_RD_LIMIT_MASK                                                              0x0000003FL
8021 #define GCEA_TCC_XBR_CREDITS__DRAM_RD_RESERVE_MASK                                                            0x000000C0L
8022 #define GCEA_TCC_XBR_CREDITS__IO_RD_LIMIT_MASK                                                                0x00003F00L
8023 #define GCEA_TCC_XBR_CREDITS__IO_RD_RESERVE_MASK                                                              0x0000C000L
8024 #define GCEA_TCC_XBR_CREDITS__DRAM_WR_LIMIT_MASK                                                              0x003F0000L
8025 #define GCEA_TCC_XBR_CREDITS__DRAM_WR_RESERVE_MASK                                                            0x00C00000L
8026 #define GCEA_TCC_XBR_CREDITS__IO_WR_LIMIT_MASK                                                                0x3F000000L
8027 #define GCEA_TCC_XBR_CREDITS__IO_WR_RESERVE_MASK                                                              0xC0000000L
8028 //GCEA_TCC_XBR_MAXBURST
8029 #define GCEA_TCC_XBR_MAXBURST__DRAM_RD__SHIFT                                                                 0x0
8030 #define GCEA_TCC_XBR_MAXBURST__IO_RD__SHIFT                                                                   0x4
8031 #define GCEA_TCC_XBR_MAXBURST__DRAM_WR__SHIFT                                                                 0x8
8032 #define GCEA_TCC_XBR_MAXBURST__IO_WR__SHIFT                                                                   0xc
8033 #define GCEA_TCC_XBR_MAXBURST__DRAM_RD_MASK                                                                   0x0000000FL
8034 #define GCEA_TCC_XBR_MAXBURST__IO_RD_MASK                                                                     0x000000F0L
8035 #define GCEA_TCC_XBR_MAXBURST__DRAM_WR_MASK                                                                   0x00000F00L
8036 #define GCEA_TCC_XBR_MAXBURST__IO_WR_MASK                                                                     0x0000F000L
8037 //GCEA_PROBE_CNTL
8038 #define GCEA_PROBE_CNTL__REQ2RSP_DELAY__SHIFT                                                                 0x0
8039 #define GCEA_PROBE_CNTL__PRB_FILTER_DISABLE__SHIFT                                                            0x5
8040 #define GCEA_PROBE_CNTL__REQ2RSP_DELAY_MASK                                                                   0x0000001FL
8041 #define GCEA_PROBE_CNTL__PRB_FILTER_DISABLE_MASK                                                              0x00000020L
8042 //GCEA_PROBE_MAP
8043 #define GCEA_PROBE_MAP__CHADDR0_TO_RIGHTTCC__SHIFT                                                            0x0
8044 #define GCEA_PROBE_MAP__CHADDR1_TO_RIGHTTCC__SHIFT                                                            0x1
8045 #define GCEA_PROBE_MAP__CHADDR2_TO_RIGHTTCC__SHIFT                                                            0x2
8046 #define GCEA_PROBE_MAP__CHADDR3_TO_RIGHTTCC__SHIFT                                                            0x3
8047 #define GCEA_PROBE_MAP__CHADDR4_TO_RIGHTTCC__SHIFT                                                            0x4
8048 #define GCEA_PROBE_MAP__CHADDR5_TO_RIGHTTCC__SHIFT                                                            0x5
8049 #define GCEA_PROBE_MAP__CHADDR6_TO_RIGHTTCC__SHIFT                                                            0x6
8050 #define GCEA_PROBE_MAP__CHADDR7_TO_RIGHTTCC__SHIFT                                                            0x7
8051 #define GCEA_PROBE_MAP__CHADDR8_TO_RIGHTTCC__SHIFT                                                            0x8
8052 #define GCEA_PROBE_MAP__CHADDR9_TO_RIGHTTCC__SHIFT                                                            0x9
8053 #define GCEA_PROBE_MAP__CHADDR10_TO_RIGHTTCC__SHIFT                                                           0xa
8054 #define GCEA_PROBE_MAP__CHADDR11_TO_RIGHTTCC__SHIFT                                                           0xb
8055 #define GCEA_PROBE_MAP__CHADDR12_TO_RIGHTTCC__SHIFT                                                           0xc
8056 #define GCEA_PROBE_MAP__CHADDR13_TO_RIGHTTCC__SHIFT                                                           0xd
8057 #define GCEA_PROBE_MAP__CHADDR14_TO_RIGHTTCC__SHIFT                                                           0xe
8058 #define GCEA_PROBE_MAP__CHADDR15_TO_RIGHTTCC__SHIFT                                                           0xf
8059 #define GCEA_PROBE_MAP__INTLV_SIZE__SHIFT                                                                     0x10
8060 #define GCEA_PROBE_MAP__CHADDR0_TO_RIGHTTCC_MASK                                                              0x00000001L
8061 #define GCEA_PROBE_MAP__CHADDR1_TO_RIGHTTCC_MASK                                                              0x00000002L
8062 #define GCEA_PROBE_MAP__CHADDR2_TO_RIGHTTCC_MASK                                                              0x00000004L
8063 #define GCEA_PROBE_MAP__CHADDR3_TO_RIGHTTCC_MASK                                                              0x00000008L
8064 #define GCEA_PROBE_MAP__CHADDR4_TO_RIGHTTCC_MASK                                                              0x00000010L
8065 #define GCEA_PROBE_MAP__CHADDR5_TO_RIGHTTCC_MASK                                                              0x00000020L
8066 #define GCEA_PROBE_MAP__CHADDR6_TO_RIGHTTCC_MASK                                                              0x00000040L
8067 #define GCEA_PROBE_MAP__CHADDR7_TO_RIGHTTCC_MASK                                                              0x00000080L
8068 #define GCEA_PROBE_MAP__CHADDR8_TO_RIGHTTCC_MASK                                                              0x00000100L
8069 #define GCEA_PROBE_MAP__CHADDR9_TO_RIGHTTCC_MASK                                                              0x00000200L
8070 #define GCEA_PROBE_MAP__CHADDR10_TO_RIGHTTCC_MASK                                                             0x00000400L
8071 #define GCEA_PROBE_MAP__CHADDR11_TO_RIGHTTCC_MASK                                                             0x00000800L
8072 #define GCEA_PROBE_MAP__CHADDR12_TO_RIGHTTCC_MASK                                                             0x00001000L
8073 #define GCEA_PROBE_MAP__CHADDR13_TO_RIGHTTCC_MASK                                                             0x00002000L
8074 #define GCEA_PROBE_MAP__CHADDR14_TO_RIGHTTCC_MASK                                                             0x00004000L
8075 #define GCEA_PROBE_MAP__CHADDR15_TO_RIGHTTCC_MASK                                                             0x00008000L
8076 #define GCEA_PROBE_MAP__INTLV_SIZE_MASK                                                                       0x00030000L
8077 //GCEA_ERR_STATUS
8078 #define GCEA_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT                                                              0x0
8079 #define GCEA_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT                                                              0x4
8080 #define GCEA_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT                                                          0x8
8081 #define GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT                                                    0xa
8082 #define GCEA_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT                                                            0xb
8083 #define GCEA_ERR_STATUS__BUSY_ON_ERROR__SHIFT                                                                 0xc
8084 #define GCEA_ERR_STATUS__FUE_FLAG__SHIFT                                                                      0xd
8085 #define GCEA_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT                                                              0xe
8086 #define GCEA_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT                                                            0xf
8087 #define GCEA_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT                                                    0x10
8088 #define GCEA_ERR_STATUS__LEVEL_INTERRUPT__SHIFT                                                               0x11
8089 #define GCEA_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR__SHIFT                                                      0x12
8090 #define GCEA_ERR_STATUS__FUE_FLAG_CLIENT__SHIFT                                                               0x13
8091 #define GCEA_ERR_STATUS__SDP_RDRSP_STATUS_MASK                                                                0x0000000FL
8092 #define GCEA_ERR_STATUS__SDP_WRRSP_STATUS_MASK                                                                0x000000F0L
8093 #define GCEA_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK                                                            0x00000300L
8094 #define GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK                                                      0x00000400L
8095 #define GCEA_ERR_STATUS__CLEAR_ERROR_STATUS_MASK                                                              0x00000800L
8096 #define GCEA_ERR_STATUS__BUSY_ON_ERROR_MASK                                                                   0x00001000L
8097 #define GCEA_ERR_STATUS__FUE_FLAG_MASK                                                                        0x00002000L
8098 #define GCEA_ERR_STATUS__IGNORE_RDRSP_FED_MASK                                                                0x00004000L
8099 #define GCEA_ERR_STATUS__INTERRUPT_ON_FATAL_MASK                                                              0x00008000L
8100 #define GCEA_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK                                                      0x00010000L
8101 #define GCEA_ERR_STATUS__LEVEL_INTERRUPT_MASK                                                                 0x00020000L
8102 #define GCEA_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR_MASK                                                        0x00040000L
8103 #define GCEA_ERR_STATUS__FUE_FLAG_CLIENT_MASK                                                                 0x00080000L
8104 //GCEA_MISC2
8105 #define GCEA_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT                                                           0x0
8106 #define GCEA_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT                                                            0x1
8107 #define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT                                                        0x2
8108 #define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT                                                         0x7
8109 #define GCEA_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT                                                            0xc
8110 #define GCEA_MISC2__BLOCK_REQUESTS__SHIFT                                                                     0xd
8111 #define GCEA_MISC2__REQUESTS_BLOCKED__SHIFT                                                                   0xe
8112 #define GCEA_MISC2__FGCLKEN_OVERRIDE__SHIFT                                                                   0xf
8113 #define GCEA_MISC2__DRAM_RD_THROTTLE__SHIFT                                                                   0x10
8114 #define GCEA_MISC2__DRAM_WR_THROTTLE__SHIFT                                                                   0x11
8115 #define GCEA_MISC2__GMI_RD_THROTTLE__SHIFT                                                                    0x12
8116 #define GCEA_MISC2__GMI_WR_THROTTLE__SHIFT                                                                    0x13
8117 #define GCEA_MISC2__CONTAIN_ILLEGAL_OP__SHIFT                                                                 0x14
8118 #define GCEA_MISC2__REPORT_ILLEGAL_OP__SHIFT                                                                  0x15
8119 #define GCEA_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK                                                             0x00000001L
8120 #define GCEA_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK                                                              0x00000002L
8121 #define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK                                                          0x0000007CL
8122 #define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK                                                           0x00000F80L
8123 #define GCEA_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK                                                              0x00001000L
8124 #define GCEA_MISC2__BLOCK_REQUESTS_MASK                                                                       0x00002000L
8125 #define GCEA_MISC2__REQUESTS_BLOCKED_MASK                                                                     0x00004000L
8126 #define GCEA_MISC2__FGCLKEN_OVERRIDE_MASK                                                                     0x00008000L
8127 #define GCEA_MISC2__DRAM_RD_THROTTLE_MASK                                                                     0x00010000L
8128 #define GCEA_MISC2__DRAM_WR_THROTTLE_MASK                                                                     0x00020000L
8129 #define GCEA_MISC2__GMI_RD_THROTTLE_MASK                                                                      0x00040000L
8130 #define GCEA_MISC2__GMI_WR_THROTTLE_MASK                                                                      0x00080000L
8131 #define GCEA_MISC2__CONTAIN_ILLEGAL_OP_MASK                                                                   0x00100000L
8132 #define GCEA_MISC2__REPORT_ILLEGAL_OP_MASK                                                                    0x00200000L
8133 //GCEA_SDP_BACKDOOR_CMDCREDITS0
8134 #define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC0_CREDITS_RECEIVED__SHIFT                                            0x0
8135 #define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC1_CREDITS_RECEIVED__SHIFT                                            0x7
8136 #define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC2_CREDITS_RECEIVED__SHIFT                                            0xe
8137 #define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC3_CREDITS_RECEIVED__SHIFT                                            0x15
8138 #define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC4_CREDITS_RECEIVED__SHIFT                                            0x1c
8139 #define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC0_CREDITS_RECEIVED_MASK                                              0x0000007FL
8140 #define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC1_CREDITS_RECEIVED_MASK                                              0x00003F80L
8141 #define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC2_CREDITS_RECEIVED_MASK                                              0x001FC000L
8142 #define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC3_CREDITS_RECEIVED_MASK                                              0x0FE00000L
8143 #define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC4_CREDITS_RECEIVED_MASK                                              0xF0000000L
8144 //GCEA_SDP_BACKDOOR_CMDCREDITS1
8145 #define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC4_CREDITS_RECEIVED__SHIFT                                            0x0
8146 #define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC5_CREDITS_RECEIVED__SHIFT                                            0x3
8147 #define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC6_CREDITS_RECEIVED__SHIFT                                            0xa
8148 #define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC7_CREDITS_RECEIVED__SHIFT                                            0x11
8149 #define GCEA_SDP_BACKDOOR_CMDCREDITS1__POOL_CREDITS_RECEIVED__SHIFT                                           0x18
8150 #define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC4_CREDITS_RECEIVED_MASK                                              0x00000007L
8151 #define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC5_CREDITS_RECEIVED_MASK                                              0x000003F8L
8152 #define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC6_CREDITS_RECEIVED_MASK                                              0x0001FC00L
8153 #define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC7_CREDITS_RECEIVED_MASK                                              0x00FE0000L
8154 #define GCEA_SDP_BACKDOOR_CMDCREDITS1__POOL_CREDITS_RECEIVED_MASK                                             0x7F000000L
8155 //GCEA_SDP_BACKDOOR_DATACREDITS0
8156 #define GCEA_SDP_BACKDOOR_DATACREDITS0__VC0_CREDITS_RECEIVED__SHIFT                                           0x0
8157 #define GCEA_SDP_BACKDOOR_DATACREDITS0__VC1_CREDITS_RECEIVED__SHIFT                                           0x7
8158 #define GCEA_SDP_BACKDOOR_DATACREDITS0__VC2_CREDITS_RECEIVED__SHIFT                                           0xe
8159 #define GCEA_SDP_BACKDOOR_DATACREDITS0__VC3_CREDITS_RECEIVED__SHIFT                                           0x15
8160 #define GCEA_SDP_BACKDOOR_DATACREDITS0__VC4_CREDITS_RECEIVED__SHIFT                                           0x1c
8161 #define GCEA_SDP_BACKDOOR_DATACREDITS0__VC0_CREDITS_RECEIVED_MASK                                             0x0000007FL
8162 #define GCEA_SDP_BACKDOOR_DATACREDITS0__VC1_CREDITS_RECEIVED_MASK                                             0x00003F80L
8163 #define GCEA_SDP_BACKDOOR_DATACREDITS0__VC2_CREDITS_RECEIVED_MASK                                             0x001FC000L
8164 #define GCEA_SDP_BACKDOOR_DATACREDITS0__VC3_CREDITS_RECEIVED_MASK                                             0x0FE00000L
8165 #define GCEA_SDP_BACKDOOR_DATACREDITS0__VC4_CREDITS_RECEIVED_MASK                                             0xF0000000L
8166 //GCEA_SDP_BACKDOOR_DATACREDITS1
8167 #define GCEA_SDP_BACKDOOR_DATACREDITS1__VC4_CREDITS_RECEIVED__SHIFT                                           0x0
8168 #define GCEA_SDP_BACKDOOR_DATACREDITS1__VC5_CREDITS_RECEIVED__SHIFT                                           0x3
8169 #define GCEA_SDP_BACKDOOR_DATACREDITS1__VC6_CREDITS_RECEIVED__SHIFT                                           0xa
8170 #define GCEA_SDP_BACKDOOR_DATACREDITS1__VC7_CREDITS_RECEIVED__SHIFT                                           0x11
8171 #define GCEA_SDP_BACKDOOR_DATACREDITS1__POOL_CREDITS_RECEIVED__SHIFT                                          0x18
8172 #define GCEA_SDP_BACKDOOR_DATACREDITS1__VC4_CREDITS_RECEIVED_MASK                                             0x00000007L
8173 #define GCEA_SDP_BACKDOOR_DATACREDITS1__VC5_CREDITS_RECEIVED_MASK                                             0x000003F8L
8174 #define GCEA_SDP_BACKDOOR_DATACREDITS1__VC6_CREDITS_RECEIVED_MASK                                             0x0001FC00L
8175 #define GCEA_SDP_BACKDOOR_DATACREDITS1__VC7_CREDITS_RECEIVED_MASK                                             0x00FE0000L
8176 #define GCEA_SDP_BACKDOOR_DATACREDITS1__POOL_CREDITS_RECEIVED_MASK                                            0x7F000000L
8177 //GCEA_SDP_BACKDOOR_MISCCREDITS
8178 #define GCEA_SDP_BACKDOOR_MISCCREDITS__RDRSP_CREDITS_RELEASED__SHIFT                                          0x0
8179 #define GCEA_SDP_BACKDOOR_MISCCREDITS__WRRSP_CREDITS_RELEASED__SHIFT                                          0x8
8180 #define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_REQ_CREDITS_RELEASED__SHIFT                                        0x10
8181 #define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_RSP_CREDITS_RECEIVED__SHIFT                                        0x17
8182 #define GCEA_SDP_BACKDOOR_MISCCREDITS__RDRSP_CREDITS_RELEASED_MASK                                            0x000000FFL
8183 #define GCEA_SDP_BACKDOOR_MISCCREDITS__WRRSP_CREDITS_RELEASED_MASK                                            0x0000FF00L
8184 #define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_REQ_CREDITS_RELEASED_MASK                                          0x007F0000L
8185 #define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_RSP_CREDITS_RECEIVED_MASK                                          0x3F800000L
8186 //GCEA_CE_ERR_STATUS_LO
8187 #define GCEA_CE_ERR_STATUS_LO__STATUS_VALID_FLAG__SHIFT                                                       0x0
8188 #define GCEA_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT                                                      0x1
8189 #define GCEA_CE_ERR_STATUS_LO__ADDRESS__SHIFT                                                                 0x2
8190 #define GCEA_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT                                                               0x18
8191 #define GCEA_CE_ERR_STATUS_LO__STATUS_VALID_FLAG_MASK                                                         0x00000001L
8192 #define GCEA_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK                                                        0x00000002L
8193 #define GCEA_CE_ERR_STATUS_LO__ADDRESS_MASK                                                                   0x00FFFFFCL
8194 #define GCEA_CE_ERR_STATUS_LO__MEMORY_ID_MASK                                                                 0xFF000000L
8195 //GCEA_CE_ERR_STATUS_HI
8196 #define GCEA_CE_ERR_STATUS_HI__ECC__SHIFT                                                                     0x0
8197 #define GCEA_CE_ERR_STATUS_HI__RESERVED_FIELD0__SHIFT                                                         0x1
8198 #define GCEA_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT                                                     0x2
8199 #define GCEA_CE_ERR_STATUS_HI__ERR_INFO__SHIFT                                                                0x3
8200 #define GCEA_CE_ERR_STATUS_HI__CE_CNT__SHIFT                                                                  0x17
8201 #define GCEA_CE_ERR_STATUS_HI__POISON__SHIFT                                                                  0x1a
8202 #define GCEA_CE_ERR_STATUS_HI__RESERVED_FIELD1__SHIFT                                                         0x1b
8203 #define GCEA_CE_ERR_STATUS_HI__ECC_MASK                                                                       0x00000001L
8204 #define GCEA_CE_ERR_STATUS_HI__RESERVED_FIELD0_MASK                                                           0x00000002L
8205 #define GCEA_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK                                                       0x00000004L
8206 #define GCEA_CE_ERR_STATUS_HI__ERR_INFO_MASK                                                                  0x007FFFF8L
8207 #define GCEA_CE_ERR_STATUS_HI__CE_CNT_MASK                                                                    0x03800000L
8208 #define GCEA_CE_ERR_STATUS_HI__POISON_MASK                                                                    0x04000000L
8209 #define GCEA_CE_ERR_STATUS_HI__RESERVED_FIELD1_MASK                                                           0xF8000000L
8210 //GCEA_SDP_ENABLE
8211 #define GCEA_SDP_ENABLE__ENABLE__SHIFT                                                                        0x0
8212 #define GCEA_SDP_ENABLE__ENABLE_MASK                                                                          0x00000001L
8213 
8214 
8215 // addressBlock: xcd0_gc_ea_pwrdec
8216 //GCEA_ICG_CTRL
8217 #define GCEA_ICG_CTRL__SOFT_OVERRIDE_RETURN__SHIFT                                                            0x0
8218 #define GCEA_ICG_CTRL__SOFT_OVERRIDE_READ__SHIFT                                                              0x1
8219 #define GCEA_ICG_CTRL__SOFT_OVERRIDE_WRITE__SHIFT                                                             0x2
8220 #define GCEA_ICG_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT                                                          0x3
8221 #define GCEA_ICG_CTRL__SOFT_OVERRIDE_RETURN_MASK                                                              0x00000001L
8222 #define GCEA_ICG_CTRL__SOFT_OVERRIDE_READ_MASK                                                                0x00000002L
8223 #define GCEA_ICG_CTRL__SOFT_OVERRIDE_WRITE_MASK                                                               0x00000004L
8224 #define GCEA_ICG_CTRL__SOFT_OVERRIDE_REGISTER_MASK                                                            0x00000008L
8225 
8226 
8227 // addressBlock: xcd0_gc_rmi_rmidec
8228 //RMI_GENERAL_CNTL
8229 #define RMI_GENERAL_CNTL__BURST_DISABLE__SHIFT                                                                0x0
8230 #define RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE__SHIFT                                                           0x1
8231 #define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG__SHIFT                                                              0x11
8232 #define RMI_GENERAL_CNTL__RB0_HARVEST_EN__SHIFT                                                               0x13
8233 #define RMI_GENERAL_CNTL__RB1_HARVEST_EN__SHIFT                                                               0x14
8234 #define RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE__SHIFT                                                     0x15
8235 #define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_UPDATE__SHIFT                                                       0x19
8236 #define RMI_GENERAL_CNTL__SKID_FIFO_0_OVERFLOW_ERROR_MASK__SHIFT                                              0x1a
8237 #define RMI_GENERAL_CNTL__SKID_FIFO_0_UNDERFLOW_ERROR_MASK__SHIFT                                             0x1b
8238 #define RMI_GENERAL_CNTL__SKID_FIFO_1_OVERFLOW_ERROR_MASK__SHIFT                                              0x1c
8239 #define RMI_GENERAL_CNTL__SKID_FIFO_1_UNDERFLOW_ERROR_MASK__SHIFT                                             0x1d
8240 #define RMI_GENERAL_CNTL__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK__SHIFT                                       0x1e
8241 #define RMI_GENERAL_CNTL__BURST_DISABLE_MASK                                                                  0x00000001L
8242 #define RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE_MASK                                                             0x0001FFFEL
8243 #define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_MASK                                                                0x00060000L
8244 #define RMI_GENERAL_CNTL__RB0_HARVEST_EN_MASK                                                                 0x00080000L
8245 #define RMI_GENERAL_CNTL__RB1_HARVEST_EN_MASK                                                                 0x00100000L
8246 #define RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE_MASK                                                       0x01E00000L
8247 #define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_UPDATE_MASK                                                         0x02000000L
8248 #define RMI_GENERAL_CNTL__SKID_FIFO_0_OVERFLOW_ERROR_MASK_MASK                                                0x04000000L
8249 #define RMI_GENERAL_CNTL__SKID_FIFO_0_UNDERFLOW_ERROR_MASK_MASK                                               0x08000000L
8250 #define RMI_GENERAL_CNTL__SKID_FIFO_1_OVERFLOW_ERROR_MASK_MASK                                                0x10000000L
8251 #define RMI_GENERAL_CNTL__SKID_FIFO_1_UNDERFLOW_ERROR_MASK_MASK                                               0x20000000L
8252 #define RMI_GENERAL_CNTL__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK_MASK                                         0x40000000L
8253 //RMI_GENERAL_CNTL1
8254 #define RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE__SHIFT                                                0x0
8255 #define RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE__SHIFT                                                     0x4
8256 #define RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE__SHIFT                                                     0x6
8257 #define RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK__SHIFT                                            0x8
8258 #define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE__SHIFT                                                       0x9
8259 #define RMI_GENERAL_CNTL1__POLICY_OVERRIDE__SHIFT                                                             0xa
8260 #define RMI_GENERAL_CNTL1__UTCL1_PROBE0_RR_ARB_BURST_HINT_EN__SHIFT                                           0xb
8261 #define RMI_GENERAL_CNTL1__UTCL1_PROBE1_RR_ARB_BURST_HINT_EN__SHIFT                                           0xc
8262 #define RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE_MASK                                                  0x0000000FL
8263 #define RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE_MASK                                                       0x00000030L
8264 #define RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE_MASK                                                       0x000000C0L
8265 #define RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK_MASK                                              0x00000100L
8266 #define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE_MASK                                                         0x00000200L
8267 #define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_MASK                                                               0x00000400L
8268 #define RMI_GENERAL_CNTL1__UTCL1_PROBE0_RR_ARB_BURST_HINT_EN_MASK                                             0x00000800L
8269 #define RMI_GENERAL_CNTL1__UTCL1_PROBE1_RR_ARB_BURST_HINT_EN_MASK                                             0x00001000L
8270 //RMI_GENERAL_STATUS
8271 #define RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED__SHIFT                                                0x0
8272 #define RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR__SHIFT                                                 0x1
8273 #define RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR__SHIFT                                                0x2
8274 #define RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR__SHIFT                                                 0x3
8275 #define RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR__SHIFT                                                0x4
8276 #define RMI_GENERAL_STATUS__RMI_XBAR_BUSY__SHIFT                                                              0x5
8277 #define RMI_GENERAL_STATUS__RMI_UTCL1_BUSY__SHIFT                                                             0x6
8278 #define RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY__SHIFT                                                        0x7
8279 #define RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY__SHIFT                                                        0x8
8280 #define RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY__SHIFT                                                           0x9
8281 #define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY__SHIFT                                                       0xa
8282 #define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY__SHIFT                                                 0xb
8283 #define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY__SHIFT                                                 0xc
8284 #define RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY__SHIFT                                                        0xd
8285 #define RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY__SHIFT                                                           0xe
8286 #define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY__SHIFT                                                       0xf
8287 #define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_1_BUSY__SHIFT                                                 0x10
8288 #define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_1_BUSY__SHIFT                                                 0x11
8289 #define RMI_GENERAL_STATUS__UTC_PROBE1_BUSY__SHIFT                                                            0x12
8290 #define RMI_GENERAL_STATUS__UTC_PROBE0_BUSY__SHIFT                                                            0x13
8291 #define RMI_GENERAL_STATUS__RMI_XNACK_BUSY__SHIFT                                                             0x14
8292 #define RMI_GENERAL_STATUS__XNACK_FIFO_NUM_USED__SHIFT                                                        0x15
8293 #define RMI_GENERAL_STATUS__XNACK_FIFO_EMPTY__SHIFT                                                           0x1d
8294 #define RMI_GENERAL_STATUS__XNACK_FIFO_FULL__SHIFT                                                            0x1e
8295 #define RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR__SHIFT                                          0x1f
8296 #define RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED_MASK                                                  0x00000001L
8297 #define RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR_MASK                                                   0x00000002L
8298 #define RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR_MASK                                                  0x00000004L
8299 #define RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR_MASK                                                   0x00000008L
8300 #define RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR_MASK                                                  0x00000010L
8301 #define RMI_GENERAL_STATUS__RMI_XBAR_BUSY_MASK                                                                0x00000020L
8302 #define RMI_GENERAL_STATUS__RMI_UTCL1_BUSY_MASK                                                               0x00000040L
8303 #define RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY_MASK                                                          0x00000080L
8304 #define RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY_MASK                                                          0x00000100L
8305 #define RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY_MASK                                                             0x00000200L
8306 #define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY_MASK                                                         0x00000400L
8307 #define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY_MASK                                                   0x00000800L
8308 #define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY_MASK                                                   0x00001000L
8309 #define RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY_MASK                                                          0x00002000L
8310 #define RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY_MASK                                                             0x00004000L
8311 #define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY_MASK                                                         0x00008000L
8312 #define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_1_BUSY_MASK                                                   0x00010000L
8313 #define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_1_BUSY_MASK                                                   0x00020000L
8314 #define RMI_GENERAL_STATUS__UTC_PROBE1_BUSY_MASK                                                              0x00040000L
8315 #define RMI_GENERAL_STATUS__UTC_PROBE0_BUSY_MASK                                                              0x00080000L
8316 #define RMI_GENERAL_STATUS__RMI_XNACK_BUSY_MASK                                                               0x00100000L
8317 #define RMI_GENERAL_STATUS__XNACK_FIFO_NUM_USED_MASK                                                          0x1FE00000L
8318 #define RMI_GENERAL_STATUS__XNACK_FIFO_EMPTY_MASK                                                             0x20000000L
8319 #define RMI_GENERAL_STATUS__XNACK_FIFO_FULL_MASK                                                              0x40000000L
8320 #define RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK                                            0x80000000L
8321 //RMI_SUBBLOCK_STATUS0
8322 #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0__SHIFT                                     0x0
8323 #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0__SHIFT                                         0x7
8324 #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0__SHIFT                                        0x8
8325 #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1__SHIFT                                     0x9
8326 #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1__SHIFT                                         0x10
8327 #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1__SHIFT                                        0x11
8328 #define RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT__SHIFT                                                       0x12
8329 #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0_MASK                                       0x0000007FL
8330 #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0_MASK                                           0x00000080L
8331 #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0_MASK                                          0x00000100L
8332 #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1_MASK                                       0x0000FE00L
8333 #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1_MASK                                           0x00010000L
8334 #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1_MASK                                          0x00020000L
8335 #define RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT_MASK                                                         0x0FFC0000L
8336 //RMI_SUBBLOCK_STATUS1
8337 #define RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE__SHIFT                                                   0x0
8338 #define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE__SHIFT                                                   0xa
8339 #define RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT__SHIFT                                                       0x14
8340 #define RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE_MASK                                                     0x000003FFL
8341 #define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE_MASK                                                     0x000FFC00L
8342 #define RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT_MASK                                                         0x3FF00000L
8343 //RMI_SUBBLOCK_STATUS2
8344 #define RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED__SHIFT                                                      0x0
8345 #define RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED__SHIFT                                                      0x9
8346 #define RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED_MASK                                                        0x000001FFL
8347 #define RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED_MASK                                                        0x0003FE00L
8348 //RMI_SUBBLOCK_STATUS3
8349 #define RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL__SHIFT                                             0x0
8350 #define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL__SHIFT                                             0xa
8351 #define RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL_MASK                                               0x000003FFL
8352 #define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL_MASK                                               0x000FFC00L
8353 //RMI_XBAR_CONFIG
8354 #define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE__SHIFT                                                      0x0
8355 #define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE__SHIFT                                             0x2
8356 #define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE__SHIFT                                                0x6
8357 #define RMI_XBAR_CONFIG__ARBITER_DIS__SHIFT                                                                   0x7
8358 #define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ__SHIFT                                                                0x8
8359 #define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE__SHIFT                                                       0xc
8360 #define RMI_XBAR_CONFIG__XBAR_EN_IN_RB0__SHIFT                                                                0xd
8361 #define RMI_XBAR_CONFIG__XBAR_EN_IN_RB1__SHIFT                                                                0xe
8362 #define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE_MASK                                                        0x00000003L
8363 #define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE_MASK                                               0x0000003CL
8364 #define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE_MASK                                                  0x00000040L
8365 #define RMI_XBAR_CONFIG__ARBITER_DIS_MASK                                                                     0x00000080L
8366 #define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_MASK                                                                  0x00000F00L
8367 #define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE_MASK                                                         0x00001000L
8368 #define RMI_XBAR_CONFIG__XBAR_EN_IN_RB0_MASK                                                                  0x00002000L
8369 #define RMI_XBAR_CONFIG__XBAR_EN_IN_RB1_MASK                                                                  0x00004000L
8370 //RMI_PROBE_POP_LOGIC_CNTL
8371 #define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH__SHIFT                                             0x0
8372 #define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS__SHIFT                                                    0x7
8373 #define RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2__SHIFT                                      0x8
8374 #define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH__SHIFT                                             0xa
8375 #define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS__SHIFT                                                    0x11
8376 #define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH_MASK                                               0x0000007FL
8377 #define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS_MASK                                                      0x00000080L
8378 #define RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2_MASK                                        0x00000300L
8379 #define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH_MASK                                               0x0001FC00L
8380 #define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS_MASK                                                      0x00020000L
8381 //RMI_UTC_XNACK_N_MISC_CNTL
8382 #define RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC__SHIFT                                              0x0
8383 #define RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE__SHIFT                                         0x8
8384 #define RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE__SHIFT                                                     0xc
8385 #define RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE__SHIFT                                       0xd
8386 #define RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC_MASK                                                0x000000FFL
8387 #define RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE_MASK                                           0x00000F00L
8388 #define RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE_MASK                                                       0x00001000L
8389 #define RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE_MASK                                         0x00002000L
8390 //RMI_DEMUX_CNTL
8391 #define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL__SHIFT                                                               0x0
8392 #define RMI_DEMUX_CNTL__DEMUX_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT                                                 0x1
8393 #define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_OVERRIDE__SHIFT                                                0x4
8394 #define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE__SHIFT                                             0x6
8395 #define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE__SHIFT                                                                0xe
8396 #define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL__SHIFT                                                               0x10
8397 #define RMI_DEMUX_CNTL__DEMUX_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT                                                 0x11
8398 #define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_OVERRIDE__SHIFT                                                0x14
8399 #define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE__SHIFT                                             0x16
8400 #define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE__SHIFT                                                                0x1e
8401 #define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_MASK                                                                 0x00000001L
8402 #define RMI_DEMUX_CNTL__DEMUX_ARB0_BREAK_LOB_ON_IDLEIN_MASK                                                   0x00000002L
8403 #define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_OVERRIDE_MASK                                                  0x00000030L
8404 #define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE_MASK                                               0x00003FC0L
8405 #define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE_MASK                                                                  0x0000C000L
8406 #define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_MASK                                                                 0x00010000L
8407 #define RMI_DEMUX_CNTL__DEMUX_ARB1_BREAK_LOB_ON_IDLEIN_MASK                                                   0x00020000L
8408 #define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_OVERRIDE_MASK                                                  0x00300000L
8409 #define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE_MASK                                               0x3FC00000L
8410 #define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE_MASK                                                                  0xC0000000L
8411 //RMI_UTCL1_CNTL1
8412 #define RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT                                                              0x0
8413 #define RMI_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT                                                                 0x1
8414 #define RMI_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT                                                               0x2
8415 #define RMI_UTCL1_CNTL1__RESP_MODE__SHIFT                                                                     0x3
8416 #define RMI_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT                                                               0x5
8417 #define RMI_UTCL1_CNTL1__CLIENTID__SHIFT                                                                      0x7
8418 #define RMI_UTCL1_CNTL1__USERVM_DIS__SHIFT                                                                    0x10
8419 #define RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT                                                             0x11
8420 #define RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT                                                          0x12
8421 #define RMI_UTCL1_CNTL1__REG_INV_VMID__SHIFT                                                                  0x13
8422 #define RMI_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT                                                              0x17
8423 #define RMI_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT                                                                0x18
8424 #define RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT                                                    0x19
8425 #define RMI_UTCL1_CNTL1__FORCE_MISS__SHIFT                                                                    0x1a
8426 #define RMI_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT                                                                0x1b
8427 #define RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT                                                        0x1c
8428 #define RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT                                                        0x1e
8429 #define RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK                                                                0x00000001L
8430 #define RMI_UTCL1_CNTL1__GPUVM_64K_DEF_MASK                                                                   0x00000002L
8431 #define RMI_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK                                                                 0x00000004L
8432 #define RMI_UTCL1_CNTL1__RESP_MODE_MASK                                                                       0x00000018L
8433 #define RMI_UTCL1_CNTL1__RESP_FAULT_MODE_MASK                                                                 0x00000060L
8434 #define RMI_UTCL1_CNTL1__CLIENTID_MASK                                                                        0x0000FF80L
8435 #define RMI_UTCL1_CNTL1__USERVM_DIS_MASK                                                                      0x00010000L
8436 #define RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK                                                               0x00020000L
8437 #define RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK                                                            0x00040000L
8438 #define RMI_UTCL1_CNTL1__REG_INV_VMID_MASK                                                                    0x00780000L
8439 #define RMI_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK                                                                0x00800000L
8440 #define RMI_UTCL1_CNTL1__REG_INV_TOGGLE_MASK                                                                  0x01000000L
8441 #define RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK                                                      0x02000000L
8442 #define RMI_UTCL1_CNTL1__FORCE_MISS_MASK                                                                      0x04000000L
8443 #define RMI_UTCL1_CNTL1__FORCE_IN_ORDER_MASK                                                                  0x08000000L
8444 #define RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK                                                          0x30000000L
8445 #define RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK                                                          0xC0000000L
8446 //RMI_UTCL1_CNTL2
8447 #define RMI_UTCL1_CNTL2__UTC_SPARE__SHIFT                                                                     0x0
8448 #define RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT                                                                0x9
8449 #define RMI_UTCL1_CNTL2__LINE_VALID__SHIFT                                                                    0xa
8450 #define RMI_UTCL1_CNTL2__DIS_EDC__SHIFT                                                                       0xb
8451 #define RMI_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT                                                                0xc
8452 #define RMI_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT                                                                 0xd
8453 #define RMI_UTCL1_CNTL2__FORCE_SNOOP__SHIFT                                                                   0xe
8454 #define RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT                                                           0xf
8455 #define RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE__SHIFT                                                          0x10
8456 #define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR__SHIFT                                                 0x12
8457 #define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR__SHIFT                                                        0x13
8458 #define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID__SHIFT                                                  0x14
8459 #define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID__SHIFT                                                         0x15
8460 #define RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ__SHIFT                                                         0x19
8461 #define RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K__SHIFT                                                    0x1a
8462 #define RMI_UTCL1_CNTL2__UTC_SPARE_MASK                                                                       0x000000FFL
8463 #define RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK                                                                  0x00000200L
8464 #define RMI_UTCL1_CNTL2__LINE_VALID_MASK                                                                      0x00000400L
8465 #define RMI_UTCL1_CNTL2__DIS_EDC_MASK                                                                         0x00000800L
8466 #define RMI_UTCL1_CNTL2__GPUVM_INV_MODE_MASK                                                                  0x00001000L
8467 #define RMI_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK                                                                   0x00002000L
8468 #define RMI_UTCL1_CNTL2__FORCE_SNOOP_MASK                                                                     0x00004000L
8469 #define RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK                                                             0x00008000L
8470 #define RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE_MASK                                                            0x00030000L
8471 #define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR_MASK                                                   0x00040000L
8472 #define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR_MASK                                                          0x00080000L
8473 #define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID_MASK                                                    0x00100000L
8474 #define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID_MASK                                                           0x01E00000L
8475 #define RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ_MASK                                                           0x02000000L
8476 #define RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K_MASK                                                      0x04000000L
8477 //RMI_UTC_UNIT_CONFIG
8478 #define RMI_UTC_UNIT_CONFIG__TMZ_REQ_EN__SHIFT                                                                0x0
8479 #define RMI_UTC_UNIT_CONFIG__TMZ_REQ_EN_MASK                                                                  0x0000FFFFL
8480 //RMI_TCIW_FORMATTER0_CNTL
8481 #define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_OVERRIDE__SHIFT                                             0x0
8482 #define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_TIME_OUT_WINDOW__SHIFT                                          0x1
8483 #define RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ__SHIFT                                       0x9
8484 #define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA__SHIFT                                         0x13
8485 #define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_UPDATE__SHIFT                                  0x1b
8486 #define RMI_TCIW_FORMATTER0_CNTL__TCIW0_REQ_SAFE_MODE__SHIFT                                                  0x1c
8487 #define RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS__SHIFT                                                  0x1d
8488 #define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_AT_LAST_OF_BURST__SHIFT                                     0x1e
8489 #define RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA__SHIFT                                                  0x1f
8490 #define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_OVERRIDE_MASK                                               0x00000001L
8491 #define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_TIME_OUT_WINDOW_MASK                                            0x000001FEL
8492 #define RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ_MASK                                         0x0007FE00L
8493 #define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_MASK                                           0x07F80000L
8494 #define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_UPDATE_MASK                                    0x08000000L
8495 #define RMI_TCIW_FORMATTER0_CNTL__TCIW0_REQ_SAFE_MODE_MASK                                                    0x10000000L
8496 #define RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS_MASK                                                    0x20000000L
8497 #define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_AT_LAST_OF_BURST_MASK                                       0x40000000L
8498 #define RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA_MASK                                                    0x80000000L
8499 //RMI_TCIW_FORMATTER1_CNTL
8500 #define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE__SHIFT                                             0x0
8501 #define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW__SHIFT                                          0x1
8502 #define RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ__SHIFT                                       0x9
8503 #define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA__SHIFT                                         0x13
8504 #define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_UPDATE__SHIFT                                  0x1b
8505 #define RMI_TCIW_FORMATTER1_CNTL__TCIW1_REQ_SAFE_MODE__SHIFT                                                  0x1c
8506 #define RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS__SHIFT                                                  0x1d
8507 #define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST__SHIFT                                     0x1e
8508 #define RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA__SHIFT                                                  0x1f
8509 #define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE_MASK                                               0x00000001L
8510 #define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW_MASK                                            0x000001FEL
8511 #define RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ_MASK                                         0x0007FE00L
8512 #define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_MASK                                           0x07F80000L
8513 #define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_UPDATE_MASK                                    0x08000000L
8514 #define RMI_TCIW_FORMATTER1_CNTL__TCIW1_REQ_SAFE_MODE_MASK                                                    0x10000000L
8515 #define RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS_MASK                                                    0x20000000L
8516 #define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST_MASK                                       0x40000000L
8517 #define RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA_MASK                                                    0x80000000L
8518 //RMI_SCOREBOARD_CNTL
8519 #define RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH__SHIFT                                                        0x0
8520 #define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0__SHIFT                                              0x1
8521 #define RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH__SHIFT                                                        0x2
8522 #define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1__SHIFT                                              0x3
8523 #define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB1__SHIFT                                                      0x4
8524 #define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN__SHIFT                                         0x5
8525 #define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE__SHIFT                                      0x6
8526 #define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB0__SHIFT                                                      0x7
8527 #define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_EN__SHIFT                                                  0x8
8528 #define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE__SHIFT                                   0x9
8529 #define RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH_MASK                                                          0x00000001L
8530 #define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0_MASK                                                0x00000002L
8531 #define RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH_MASK                                                          0x00000004L
8532 #define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1_MASK                                                0x00000008L
8533 #define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB1_MASK                                                        0x00000010L
8534 #define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN_MASK                                           0x00000020L
8535 #define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE_MASK                                        0x00000040L
8536 #define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB0_MASK                                                        0x00000080L
8537 #define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_EN_MASK                                                    0x00000100L
8538 #define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE_MASK                                     0x001FFE00L
8539 //RMI_SCOREBOARD_STATUS0
8540 #define RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID__SHIFT                                                     0x0
8541 #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG__SHIFT                                                    0x1
8542 #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID__SHIFT                                                   0x2
8543 #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE__SHIFT                                                   0x12
8544 #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE__SHIFT                                                       0x13
8545 #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE__SHIFT                                                 0x14
8546 #define RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE__SHIFT                                                    0x15
8547 #define RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID_MASK                                                       0x00000001L
8548 #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG_MASK                                                      0x00000002L
8549 #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID_MASK                                                     0x0003FFFCL
8550 #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE_MASK                                                     0x00040000L
8551 #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE_MASK                                                         0x00080000L
8552 #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE_MASK                                                   0x00100000L
8553 #define RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE_MASK                                                      0x00200000L
8554 //RMI_SCOREBOARD_STATUS1
8555 #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0__SHIFT                                                        0x0
8556 #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0__SHIFT                                              0xc
8557 #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0__SHIFT                                               0xd
8558 #define RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED__SHIFT                                      0xe
8559 #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1__SHIFT                                                        0xf
8560 #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1__SHIFT                                              0x1b
8561 #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1__SHIFT                                               0x1c
8562 #define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1__SHIFT                                                  0x1d
8563 #define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0__SHIFT                                                  0x1e
8564 #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0_MASK                                                          0x00000FFFL
8565 #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0_MASK                                                0x00001000L
8566 #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0_MASK                                                 0x00002000L
8567 #define RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED_MASK                                        0x00004000L
8568 #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1_MASK                                                          0x07FF8000L
8569 #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1_MASK                                                0x08000000L
8570 #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1_MASK                                                 0x10000000L
8571 #define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1_MASK                                                    0x20000000L
8572 #define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0_MASK                                                    0x40000000L
8573 //RMI_SCOREBOARD_STATUS2
8574 #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0__SHIFT                                                       0x0
8575 #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0__SHIFT                                             0xc
8576 #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1__SHIFT                                                       0xd
8577 #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1__SHIFT                                             0x19
8578 #define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1__SHIFT                                                     0x1a
8579 #define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0__SHIFT                                                     0x1b
8580 #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0__SHIFT                                           0x1c
8581 #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1__SHIFT                                           0x1d
8582 #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0__SHIFT                                              0x1e
8583 #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1__SHIFT                                              0x1f
8584 #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0_MASK                                                         0x00000FFFL
8585 #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0_MASK                                               0x00001000L
8586 #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1_MASK                                                         0x01FFE000L
8587 #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1_MASK                                               0x02000000L
8588 #define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1_MASK                                                       0x04000000L
8589 #define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0_MASK                                                       0x08000000L
8590 #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0_MASK                                             0x10000000L
8591 #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1_MASK                                             0x20000000L
8592 #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0_MASK                                                0x40000000L
8593 #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1_MASK                                                0x80000000L
8594 //RMI_XBAR_ARBITER_CONFIG
8595 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE__SHIFT                                                        0x0
8596 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR__SHIFT                                     0x2
8597 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL__SHIFT                                                       0x3
8598 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT                                         0x4
8599 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE__SHIFT                                        0x6
8600 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE__SHIFT                                     0x8
8601 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE__SHIFT                                                        0x10
8602 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR__SHIFT                                     0x12
8603 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL__SHIFT                                                       0x13
8604 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT                                         0x14
8605 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE__SHIFT                                        0x16
8606 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE__SHIFT                                     0x18
8607 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE_MASK                                                          0x00000003L
8608 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR_MASK                                       0x00000004L
8609 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_MASK                                                         0x00000008L
8610 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN_MASK                                           0x00000010L
8611 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE_MASK                                          0x000000C0L
8612 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE_MASK                                       0x0000FF00L
8613 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE_MASK                                                          0x00030000L
8614 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR_MASK                                       0x00040000L
8615 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_MASK                                                         0x00080000L
8616 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN_MASK                                           0x00100000L
8617 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE_MASK                                          0x00C00000L
8618 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE_MASK                                       0xFF000000L
8619 //RMI_XBAR_ARBITER_CONFIG_1
8620 #define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD__SHIFT                                  0x0
8621 #define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR__SHIFT                                  0x8
8622 #define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_RD__SHIFT                                  0x10
8623 #define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_WR__SHIFT                                  0x18
8624 #define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD_MASK                                    0x000000FFL
8625 #define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR_MASK                                    0x0000FF00L
8626 #define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_RD_MASK                                    0x00FF0000L
8627 #define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_WR_MASK                                    0xFF000000L
8628 //RMI_CLOCK_CNTRL
8629 #define RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK__SHIFT                                                         0x0
8630 #define RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK__SHIFT                                                         0x5
8631 #define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK__SHIFT                                                       0xa
8632 #define RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK__SHIFT                                                       0xf
8633 #define RMI_CLOCK_CNTRL__DYN_CLK_RB1_BUSY_MASK__SHIFT                                                         0x14
8634 #define RMI_CLOCK_CNTRL__DYN_CLK_RB1_WAKEUP_MASK__SHIFT                                                       0x19
8635 #define RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK_MASK                                                           0x0000001FL
8636 #define RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK_MASK                                                           0x000003E0L
8637 #define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK_MASK                                                         0x00007C00L
8638 #define RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK_MASK                                                         0x000F8000L
8639 #define RMI_CLOCK_CNTRL__DYN_CLK_RB1_BUSY_MASK_MASK                                                           0x01F00000L
8640 #define RMI_CLOCK_CNTRL__DYN_CLK_RB1_WAKEUP_MASK_MASK                                                         0x3E000000L
8641 //RMI_UTCL1_STATUS
8642 #define RMI_UTCL1_STATUS__FAULT_DETECTED__SHIFT                                                               0x0
8643 #define RMI_UTCL1_STATUS__RETRY_DETECTED__SHIFT                                                               0x1
8644 #define RMI_UTCL1_STATUS__PRT_DETECTED__SHIFT                                                                 0x2
8645 #define RMI_UTCL1_STATUS__FAULT_DETECTED_MASK                                                                 0x00000001L
8646 #define RMI_UTCL1_STATUS__RETRY_DETECTED_MASK                                                                 0x00000002L
8647 #define RMI_UTCL1_STATUS__PRT_DETECTED_MASK                                                                   0x00000004L
8648 //RMI_XNACK_DEBUG
8649 #define RMI_XNACK_DEBUG__XNACK_PER_VMID__SHIFT                                                                0x0
8650 #define RMI_XNACK_DEBUG__XNACK_PER_VMID_MASK                                                                  0x0000FFFFL
8651 //RMI_SPARE
8652 #define RMI_SPARE__RMI_ARBITER_STALL_TIMER_ENABLED_ALLOW_STREAMING__SHIFT                                     0x0
8653 #define RMI_SPARE__SPARE_BIT_1__SHIFT                                                                         0x1
8654 #define RMI_SPARE__SPARE_BIT_2__SHIFT                                                                         0x2
8655 #define RMI_SPARE__SPARE_BIT_3__SHIFT                                                                         0x3
8656 #define RMI_SPARE__SPARE_BIT_4__SHIFT                                                                         0x4
8657 #define RMI_SPARE__SPARE_BIT_5__SHIFT                                                                         0x5
8658 #define RMI_SPARE__SPARE_BIT_6__SHIFT                                                                         0x6
8659 #define RMI_SPARE__SPARE_BIT_7__SHIFT                                                                         0x7
8660 #define RMI_SPARE__SPARE_BIT_8_0__SHIFT                                                                       0x8
8661 #define RMI_SPARE__SPARE_BIT_16_0__SHIFT                                                                      0x10
8662 #define RMI_SPARE__RMI_ARBITER_STALL_TIMER_ENABLED_ALLOW_STREAMING_MASK                                       0x00000001L
8663 #define RMI_SPARE__SPARE_BIT_1_MASK                                                                           0x00000002L
8664 #define RMI_SPARE__SPARE_BIT_2_MASK                                                                           0x00000004L
8665 #define RMI_SPARE__SPARE_BIT_3_MASK                                                                           0x00000008L
8666 #define RMI_SPARE__SPARE_BIT_4_MASK                                                                           0x00000010L
8667 #define RMI_SPARE__SPARE_BIT_5_MASK                                                                           0x00000020L
8668 #define RMI_SPARE__SPARE_BIT_6_MASK                                                                           0x00000040L
8669 #define RMI_SPARE__SPARE_BIT_7_MASK                                                                           0x00000080L
8670 #define RMI_SPARE__SPARE_BIT_8_0_MASK                                                                         0x0000FF00L
8671 #define RMI_SPARE__SPARE_BIT_16_0_MASK                                                                        0xFFFF0000L
8672 //RMI_SPARE_1
8673 #define RMI_SPARE_1__SPARE_BIT_8__SHIFT                                                                       0x0
8674 #define RMI_SPARE_1__SPARE_BIT_9__SHIFT                                                                       0x1
8675 #define RMI_SPARE_1__SPARE_BIT_10__SHIFT                                                                      0x2
8676 #define RMI_SPARE_1__SPARE_BIT_11__SHIFT                                                                      0x3
8677 #define RMI_SPARE_1__SPARE_BIT_12__SHIFT                                                                      0x4
8678 #define RMI_SPARE_1__SPARE_BIT_13__SHIFT                                                                      0x5
8679 #define RMI_SPARE_1__SPARE_BIT_14__SHIFT                                                                      0x6
8680 #define RMI_SPARE_1__SPARE_BIT_15__SHIFT                                                                      0x7
8681 #define RMI_SPARE_1__SPARE_BIT_8_1__SHIFT                                                                     0x8
8682 #define RMI_SPARE_1__SPARE_BIT_16_1__SHIFT                                                                    0x10
8683 #define RMI_SPARE_1__SPARE_BIT_8_MASK                                                                         0x00000001L
8684 #define RMI_SPARE_1__SPARE_BIT_9_MASK                                                                         0x00000002L
8685 #define RMI_SPARE_1__SPARE_BIT_10_MASK                                                                        0x00000004L
8686 #define RMI_SPARE_1__SPARE_BIT_11_MASK                                                                        0x00000008L
8687 #define RMI_SPARE_1__SPARE_BIT_12_MASK                                                                        0x00000010L
8688 #define RMI_SPARE_1__SPARE_BIT_13_MASK                                                                        0x00000020L
8689 #define RMI_SPARE_1__SPARE_BIT_14_MASK                                                                        0x00000040L
8690 #define RMI_SPARE_1__SPARE_BIT_15_MASK                                                                        0x00000080L
8691 #define RMI_SPARE_1__SPARE_BIT_8_1_MASK                                                                       0x0000FF00L
8692 #define RMI_SPARE_1__SPARE_BIT_16_1_MASK                                                                      0xFFFF0000L
8693 //RMI_SPARE_2
8694 #define RMI_SPARE_2__SPARE_BIT_16__SHIFT                                                                      0x0
8695 #define RMI_SPARE_2__SPARE_BIT_17__SHIFT                                                                      0x1
8696 #define RMI_SPARE_2__SPARE_BIT_18__SHIFT                                                                      0x2
8697 #define RMI_SPARE_2__SPARE_BIT_19__SHIFT                                                                      0x3
8698 #define RMI_SPARE_2__SPARE_BIT_20__SHIFT                                                                      0x4
8699 #define RMI_SPARE_2__SPARE_BIT_21__SHIFT                                                                      0x5
8700 #define RMI_SPARE_2__SPARE_BIT_22__SHIFT                                                                      0x6
8701 #define RMI_SPARE_2__SPARE_BIT_23__SHIFT                                                                      0x7
8702 #define RMI_SPARE_2__SPARE_BIT_4_0__SHIFT                                                                     0x8
8703 #define RMI_SPARE_2__SPARE_BIT_4_1__SHIFT                                                                     0xc
8704 #define RMI_SPARE_2__SPARE_BIT_8_2__SHIFT                                                                     0x10
8705 #define RMI_SPARE_2__SPARE_BIT_8_3__SHIFT                                                                     0x18
8706 #define RMI_SPARE_2__SPARE_BIT_16_MASK                                                                        0x00000001L
8707 #define RMI_SPARE_2__SPARE_BIT_17_MASK                                                                        0x00000002L
8708 #define RMI_SPARE_2__SPARE_BIT_18_MASK                                                                        0x00000004L
8709 #define RMI_SPARE_2__SPARE_BIT_19_MASK                                                                        0x00000008L
8710 #define RMI_SPARE_2__SPARE_BIT_20_MASK                                                                        0x00000010L
8711 #define RMI_SPARE_2__SPARE_BIT_21_MASK                                                                        0x00000020L
8712 #define RMI_SPARE_2__SPARE_BIT_22_MASK                                                                        0x00000040L
8713 #define RMI_SPARE_2__SPARE_BIT_23_MASK                                                                        0x00000080L
8714 #define RMI_SPARE_2__SPARE_BIT_4_0_MASK                                                                       0x00000F00L
8715 #define RMI_SPARE_2__SPARE_BIT_4_1_MASK                                                                       0x0000F000L
8716 #define RMI_SPARE_2__SPARE_BIT_8_2_MASK                                                                       0x00FF0000L
8717 #define RMI_SPARE_2__SPARE_BIT_8_3_MASK                                                                       0xFF000000L
8718 
8719 
8720 // addressBlock: xcd0_gc_utcl2_atcl2dec
8721 //ATC_L2_CNTL
8722 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT                                               0x0
8723 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT                                              0x3
8724 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT                                   0x6
8725 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT                                  0x7
8726 #define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS__SHIFT                                          0x8
8727 #define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS__SHIFT                                         0xb
8728 #define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT                              0xe
8729 #define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT                             0xf
8730 #define ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT                                                             0x10
8731 #define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT                                          0x13
8732 #define ATC_L2_CNTL__FRAG_APT_INTXN_MODE__SHIFT                                                               0x14
8733 #define ATC_L2_CNTL__CLI_GPA_REQ_FRAG_SIZE__SHIFT                                                             0x16
8734 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK                                                 0x00000003L
8735 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK                                                0x00000018L
8736 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK                                     0x00000040L
8737 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK                                    0x00000080L
8738 #define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS_MASK                                            0x00000300L
8739 #define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS_MASK                                           0x00001800L
8740 #define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK                                0x00004000L
8741 #define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK                               0x00008000L
8742 #define ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK                                                               0x00070000L
8743 #define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK                                            0x00080000L
8744 #define ATC_L2_CNTL__FRAG_APT_INTXN_MODE_MASK                                                                 0x00300000L
8745 #define ATC_L2_CNTL__CLI_GPA_REQ_FRAG_SIZE_MASK                                                               0x0FC00000L
8746 //ATC_L2_CNTL2
8747 #define ATC_L2_CNTL2__BANK_SELECT__SHIFT                                                                      0x0
8748 #define ATC_L2_CNTL2__NUM_BANKS_LOG2__SHIFT                                                                   0x6
8749 #define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT                                                             0x9
8750 #define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT                                              0xb
8751 #define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT                                                     0xc
8752 #define ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT                                                               0xf
8753 #define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT                                         0x12
8754 #define ATC_L2_CNTL2__BANK_SELECT_MASK                                                                        0x0000003FL
8755 #define ATC_L2_CNTL2__NUM_BANKS_LOG2_MASK                                                                     0x000001C0L
8756 #define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK                                                               0x00000600L
8757 #define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK                                                0x00000800L
8758 #define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK                                                       0x00007000L
8759 #define ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK                                                                 0x00038000L
8760 #define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK                                           0x00FC0000L
8761 //ATC_L2_CACHE_DATA0
8762 #define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT                                                        0x0
8763 #define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT                                                          0x1
8764 #define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT                                                          0x2
8765 #define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT                                                  0x17
8766 #define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK                                                          0x00000001L
8767 #define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK                                                            0x00000002L
8768 #define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK                                                            0x007FFFFCL
8769 #define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK                                                    0x07800000L
8770 //ATC_L2_CACHE_DATA1
8771 #define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT                                                   0x0
8772 #define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK                                                     0xFFFFFFFFL
8773 //ATC_L2_CACHE_DATA2
8774 #define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT                                                      0x0
8775 #define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK                                                        0xFFFFFFFFL
8776 //ATC_L2_CACHE_DATA3
8777 #define ATC_L2_CACHE_DATA3__PHYSICAL_PAGE_ADDRESS__SHIFT                                                      0x0
8778 #define ATC_L2_CACHE_DATA3__PHYSICAL_PAGE_ADDRESS_MASK                                                        0xFFFFFFFFL
8779 //ATC_L2_CNTL3
8780 #define ATC_L2_CNTL3__L2_SMALLK_FRAGMENT_SIZE__SHIFT                                                          0x0
8781 #define ATC_L2_CNTL3__L2_MIDK_FRAGMENT_SIZE__SHIFT                                                            0x6
8782 #define ATC_L2_CNTL3__L2_BIGK_FRAGMENT_SIZE__SHIFT                                                            0xc
8783 #define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT                                                  0x12
8784 #define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT                                                        0x15
8785 #define ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS__SHIFT                                                        0x1b
8786 #define ATC_L2_CNTL3__REPEATER_FGCG_OFF__SHIFT                                                                0x1e
8787 #define ATC_L2_CNTL3__L2_SMALLK_FRAGMENT_SIZE_MASK                                                            0x0000003FL
8788 #define ATC_L2_CNTL3__L2_MIDK_FRAGMENT_SIZE_MASK                                                              0x00000FC0L
8789 #define ATC_L2_CNTL3__L2_BIGK_FRAGMENT_SIZE_MASK                                                              0x0003F000L
8790 #define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK                                                    0x001C0000L
8791 #define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK                                                          0x07E00000L
8792 #define ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS_MASK                                                          0x38000000L
8793 #define ATC_L2_CNTL3__REPEATER_FGCG_OFF_MASK                                                                  0x40000000L
8794 //ATC_L2_STATUS
8795 #define ATC_L2_STATUS__BUSY__SHIFT                                                                            0x0
8796 #define ATC_L2_STATUS__NO_OUTSTANDING_AT_REQUESTS__SHIFT                                                      0x1
8797 #define ATC_L2_STATUS__BUSY_MASK                                                                              0x00000001L
8798 #define ATC_L2_STATUS__NO_OUTSTANDING_AT_REQUESTS_MASK                                                        0x00000002L
8799 //ATC_L2_STATUS2
8800 #define ATC_L2_STATUS2__UCE_MEM_ADDR__SHIFT                                                                   0x0
8801 #define ATC_L2_STATUS2__UCE_MEM_INST__SHIFT                                                                   0xc
8802 #define ATC_L2_STATUS2__UCE_SRT_CACHE__SHIFT                                                                  0x14
8803 #define ATC_L2_STATUS2__UCE__SHIFT                                                                            0x15
8804 #define ATC_L2_STATUS2__UCE_MEM_ADDR_MASK                                                                     0x00000FFFL
8805 #define ATC_L2_STATUS2__UCE_MEM_INST_MASK                                                                     0x000FF000L
8806 #define ATC_L2_STATUS2__UCE_SRT_CACHE_MASK                                                                    0x00100000L
8807 #define ATC_L2_STATUS2__UCE_MASK                                                                              0x00200000L
8808 //ATC_L2_MISC_CG
8809 #define ATC_L2_MISC_CG__OFFDLY__SHIFT                                                                         0x6
8810 #define ATC_L2_MISC_CG__ENABLE__SHIFT                                                                         0x12
8811 #define ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT                                                                  0x13
8812 #define ATC_L2_MISC_CG__OFFDLY_MASK                                                                           0x00000FC0L
8813 #define ATC_L2_MISC_CG__ENABLE_MASK                                                                           0x00040000L
8814 #define ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK                                                                    0x00080000L
8815 //ATC_L2_MEM_POWER_LS
8816 #define ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT                                                                  0x0
8817 #define ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT                                                                   0x6
8818 #define ATC_L2_MEM_POWER_LS__LS_SETUP_MASK                                                                    0x0000003FL
8819 #define ATC_L2_MEM_POWER_LS__LS_HOLD_MASK                                                                     0x00000FC0L
8820 //ATC_L2_CGTT_CLK_CTRL
8821 #define ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                                 0x0
8822 #define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                           0x4
8823 #define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT                                                            0xf
8824 #define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                      0x10
8825 #define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT                                                            0x18
8826 #define ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                   0x0000000FL
8827 #define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                             0x00000FF0L
8828 #define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK                                                              0x00008000L
8829 #define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                        0x00FF0000L
8830 #define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK                                                              0xFF000000L
8831 //ATC_L2_CACHE_4K_DSM_INDEX
8832 #define ATC_L2_CACHE_4K_DSM_INDEX__INDEX__SHIFT                                                               0x0
8833 #define ATC_L2_CACHE_4K_DSM_INDEX__INDEX_MASK                                                                 0x000000FFL
8834 //ATC_L2_CACHE_32K_DSM_INDEX
8835 #define ATC_L2_CACHE_32K_DSM_INDEX__INDEX__SHIFT                                                              0x0
8836 #define ATC_L2_CACHE_32K_DSM_INDEX__INDEX_MASK                                                                0x000000FFL
8837 //ATC_L2_CACHE_2M_DSM_INDEX
8838 #define ATC_L2_CACHE_2M_DSM_INDEX__INDEX__SHIFT                                                               0x0
8839 #define ATC_L2_CACHE_2M_DSM_INDEX__INDEX_MASK                                                                 0x000000FFL
8840 //ATC_L2_CACHE_4K_DSM_CNTL
8841 #define ATC_L2_CACHE_4K_DSM_CNTL__INJECT_DELAY__SHIFT                                                         0x0
8842 #define ATC_L2_CACHE_4K_DSM_CNTL__DSM_IRRITATOR_DATA__SHIFT                                                   0x6
8843 #define ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_SINGLE_WRITE__SHIFT                                                  0x8
8844 #define ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_ERROR_INJECT__SHIFT                                                  0x9
8845 #define ATC_L2_CACHE_4K_DSM_CNTL__SELECT_INJECT_DELAY__SHIFT                                                  0xb
8846 #define ATC_L2_CACHE_4K_DSM_CNTL__WRITE_COUNTERS__SHIFT                                                       0xc
8847 #define ATC_L2_CACHE_4K_DSM_CNTL__SEC_COUNT__SHIFT                                                            0xd
8848 #define ATC_L2_CACHE_4K_DSM_CNTL__DED_COUNT__SHIFT                                                            0xf
8849 #define ATC_L2_CACHE_4K_DSM_CNTL__TEST_FUE__SHIFT                                                             0x11
8850 #define ATC_L2_CACHE_4K_DSM_CNTL__INJECT_DELAY_MASK                                                           0x0000003FL
8851 #define ATC_L2_CACHE_4K_DSM_CNTL__DSM_IRRITATOR_DATA_MASK                                                     0x000000C0L
8852 #define ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_SINGLE_WRITE_MASK                                                    0x00000100L
8853 #define ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_ERROR_INJECT_MASK                                                    0x00000600L
8854 #define ATC_L2_CACHE_4K_DSM_CNTL__SELECT_INJECT_DELAY_MASK                                                    0x00000800L
8855 #define ATC_L2_CACHE_4K_DSM_CNTL__WRITE_COUNTERS_MASK                                                         0x00001000L
8856 #define ATC_L2_CACHE_4K_DSM_CNTL__SEC_COUNT_MASK                                                              0x00006000L
8857 #define ATC_L2_CACHE_4K_DSM_CNTL__DED_COUNT_MASK                                                              0x00018000L
8858 #define ATC_L2_CACHE_4K_DSM_CNTL__TEST_FUE_MASK                                                               0x00020000L
8859 //ATC_L2_CACHE_32K_DSM_CNTL
8860 #define ATC_L2_CACHE_32K_DSM_CNTL__INJECT_DELAY__SHIFT                                                        0x0
8861 #define ATC_L2_CACHE_32K_DSM_CNTL__DSM_IRRITATOR_DATA__SHIFT                                                  0x6
8862 #define ATC_L2_CACHE_32K_DSM_CNTL__ENABLE_SINGLE_WRITE__SHIFT                                                 0x8
8863 #define ATC_L2_CACHE_32K_DSM_CNTL__ENABLE_ERROR_INJECT__SHIFT                                                 0x9
8864 #define ATC_L2_CACHE_32K_DSM_CNTL__SELECT_INJECT_DELAY__SHIFT                                                 0xb
8865 #define ATC_L2_CACHE_32K_DSM_CNTL__WRITE_COUNTERS__SHIFT                                                      0xc
8866 #define ATC_L2_CACHE_32K_DSM_CNTL__SEC_COUNT__SHIFT                                                           0xd
8867 #define ATC_L2_CACHE_32K_DSM_CNTL__DED_COUNT__SHIFT                                                           0xf
8868 #define ATC_L2_CACHE_32K_DSM_CNTL__TEST_FUE__SHIFT                                                            0x11
8869 #define ATC_L2_CACHE_32K_DSM_CNTL__INJECT_DELAY_MASK                                                          0x0000003FL
8870 #define ATC_L2_CACHE_32K_DSM_CNTL__DSM_IRRITATOR_DATA_MASK                                                    0x000000C0L
8871 #define ATC_L2_CACHE_32K_DSM_CNTL__ENABLE_SINGLE_WRITE_MASK                                                   0x00000100L
8872 #define ATC_L2_CACHE_32K_DSM_CNTL__ENABLE_ERROR_INJECT_MASK                                                   0x00000600L
8873 #define ATC_L2_CACHE_32K_DSM_CNTL__SELECT_INJECT_DELAY_MASK                                                   0x00000800L
8874 #define ATC_L2_CACHE_32K_DSM_CNTL__WRITE_COUNTERS_MASK                                                        0x00001000L
8875 #define ATC_L2_CACHE_32K_DSM_CNTL__SEC_COUNT_MASK                                                             0x00006000L
8876 #define ATC_L2_CACHE_32K_DSM_CNTL__DED_COUNT_MASK                                                             0x00018000L
8877 #define ATC_L2_CACHE_32K_DSM_CNTL__TEST_FUE_MASK                                                              0x00020000L
8878 //ATC_L2_CACHE_2M_DSM_CNTL
8879 #define ATC_L2_CACHE_2M_DSM_CNTL__INJECT_DELAY__SHIFT                                                         0x0
8880 #define ATC_L2_CACHE_2M_DSM_CNTL__DSM_IRRITATOR_DATA__SHIFT                                                   0x6
8881 #define ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_SINGLE_WRITE__SHIFT                                                  0x8
8882 #define ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_ERROR_INJECT__SHIFT                                                  0x9
8883 #define ATC_L2_CACHE_2M_DSM_CNTL__SELECT_INJECT_DELAY__SHIFT                                                  0xb
8884 #define ATC_L2_CACHE_2M_DSM_CNTL__WRITE_COUNTERS__SHIFT                                                       0xc
8885 #define ATC_L2_CACHE_2M_DSM_CNTL__SEC_COUNT__SHIFT                                                            0xd
8886 #define ATC_L2_CACHE_2M_DSM_CNTL__DED_COUNT__SHIFT                                                            0xf
8887 #define ATC_L2_CACHE_2M_DSM_CNTL__TEST_FUE__SHIFT                                                             0x11
8888 #define ATC_L2_CACHE_2M_DSM_CNTL__INJECT_DELAY_MASK                                                           0x0000003FL
8889 #define ATC_L2_CACHE_2M_DSM_CNTL__DSM_IRRITATOR_DATA_MASK                                                     0x000000C0L
8890 #define ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_SINGLE_WRITE_MASK                                                    0x00000100L
8891 #define ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_ERROR_INJECT_MASK                                                    0x00000600L
8892 #define ATC_L2_CACHE_2M_DSM_CNTL__SELECT_INJECT_DELAY_MASK                                                    0x00000800L
8893 #define ATC_L2_CACHE_2M_DSM_CNTL__WRITE_COUNTERS_MASK                                                         0x00001000L
8894 #define ATC_L2_CACHE_2M_DSM_CNTL__SEC_COUNT_MASK                                                              0x00006000L
8895 #define ATC_L2_CACHE_2M_DSM_CNTL__DED_COUNT_MASK                                                              0x00018000L
8896 #define ATC_L2_CACHE_2M_DSM_CNTL__TEST_FUE_MASK                                                               0x00020000L
8897 //ATC_L2_CNTL4
8898 #define ATC_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT                                          0x0
8899 #define ATC_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT                                         0xa
8900 #define ATC_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK                                            0x000003FFL
8901 #define ATC_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK                                           0x000FFC00L
8902 //ATC_L2_MM_GROUP_RT_CLASSES
8903 #define ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS__SHIFT                                                     0x0
8904 #define ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS_MASK                                                       0xFFFFFFFFL
8905 //ATC_L2_UE_ERR_STATUS_LO
8906 #define ATC_L2_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT                                                 0x0
8907 #define ATC_L2_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT                                                    0x1
8908 #define ATC_L2_UE_ERR_STATUS_LO__ADDRESS__SHIFT                                                               0x2
8909 #define ATC_L2_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT                                                             0x18
8910 #define ATC_L2_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK                                                   0x00000001L
8911 #define ATC_L2_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK                                                      0x00000002L
8912 #define ATC_L2_UE_ERR_STATUS_LO__ADDRESS_MASK                                                                 0x00FFFFFCL
8913 #define ATC_L2_UE_ERR_STATUS_LO__MEMORY_ID_MASK                                                               0xFF000000L
8914 //ATC_L2_UE_ERR_STATUS_HI
8915 #define ATC_L2_UE_ERR_STATUS_HI__ECC__SHIFT                                                                   0x0
8916 #define ATC_L2_UE_ERR_STATUS_HI__PARITY__SHIFT                                                                0x1
8917 #define ATC_L2_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT                                                   0x2
8918 #define ATC_L2_UE_ERR_STATUS_HI__ERR_INFO__SHIFT                                                              0x3
8919 #define ATC_L2_UE_ERR_STATUS_HI__UE_CNT__SHIFT                                                                0x17
8920 #define ATC_L2_UE_ERR_STATUS_HI__FED_CNT__SHIFT                                                               0x1a
8921 #define ATC_L2_UE_ERR_STATUS_HI__RESERVED__SHIFT                                                              0x1d
8922 #define ATC_L2_UE_ERR_STATUS_HI__ECC_MASK                                                                     0x00000001L
8923 #define ATC_L2_UE_ERR_STATUS_HI__PARITY_MASK                                                                  0x00000002L
8924 #define ATC_L2_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK                                                     0x00000004L
8925 #define ATC_L2_UE_ERR_STATUS_HI__ERR_INFO_MASK                                                                0x007FFFF8L
8926 #define ATC_L2_UE_ERR_STATUS_HI__UE_CNT_MASK                                                                  0x03800000L
8927 #define ATC_L2_UE_ERR_STATUS_HI__FED_CNT_MASK                                                                 0x1C000000L
8928 #define ATC_L2_UE_ERR_STATUS_HI__RESERVED_MASK                                                                0x60000000L
8929 //ATC_L2_CE_ERR_STATUS_LO
8930 #define ATC_L2_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT                                                 0x0
8931 #define ATC_L2_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT                                                    0x1
8932 #define ATC_L2_CE_ERR_STATUS_LO__ADDRESS__SHIFT                                                               0x2
8933 #define ATC_L2_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT                                                             0x18
8934 #define ATC_L2_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK                                                   0x00000001L
8935 #define ATC_L2_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK                                                      0x00000002L
8936 #define ATC_L2_CE_ERR_STATUS_LO__ADDRESS_MASK                                                                 0x00FFFFFCL
8937 #define ATC_L2_CE_ERR_STATUS_LO__MEMORY_ID_MASK                                                               0xFF000000L
8938 //ATC_L2_CE_ERR_STATUS_HI
8939 #define ATC_L2_CE_ERR_STATUS_HI__ECC__SHIFT                                                                   0x0
8940 #define ATC_L2_CE_ERR_STATUS_HI__OTHER__SHIFT                                                                 0x1
8941 #define ATC_L2_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT                                                   0x2
8942 #define ATC_L2_CE_ERR_STATUS_HI__ERR_INFO__SHIFT                                                              0x3
8943 #define ATC_L2_CE_ERR_STATUS_HI__CE_CNT__SHIFT                                                                0x17
8944 #define ATC_L2_CE_ERR_STATUS_HI__POISON__SHIFT                                                                0x1a
8945 #define ATC_L2_CE_ERR_STATUS_HI__RESERVED__SHIFT                                                              0x1b
8946 #define ATC_L2_CE_ERR_STATUS_HI__ECC_MASK                                                                     0x00000001L
8947 #define ATC_L2_CE_ERR_STATUS_HI__OTHER_MASK                                                                   0x00000002L
8948 #define ATC_L2_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK                                                     0x00000004L
8949 #define ATC_L2_CE_ERR_STATUS_HI__ERR_INFO_MASK                                                                0x007FFFF8L
8950 #define ATC_L2_CE_ERR_STATUS_HI__CE_CNT_MASK                                                                  0x03800000L
8951 #define ATC_L2_CE_ERR_STATUS_HI__POISON_MASK                                                                  0x04000000L
8952 #define ATC_L2_CE_ERR_STATUS_HI__RESERVED_MASK                                                                0xF8000000L
8953 
8954 
8955 // addressBlock: xcd0_gc_utcl2_vml2pfdec
8956 //VM_L2_CNTL
8957 #define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT                                                                    0x0
8958 #define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT                                                      0x1
8959 #define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT                                                      0x2
8960 #define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT                                                      0x4
8961 #define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT                                                  0x8
8962 #define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT                                            0x9
8963 #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT                                           0xa
8964 #define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT                                           0xb
8965 #define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT                                                           0xc
8966 #define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT                                                            0xf
8967 #define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT                                                           0x12
8968 #define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT                                                      0x13
8969 #define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT                                                        0x15
8970 #define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT                                                             0x1a
8971 #define VM_L2_CNTL__ENABLE_L2_CACHE_MASK                                                                      0x00000001L
8972 #define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK                                                        0x00000002L
8973 #define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK                                                        0x0000000CL
8974 #define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK                                                        0x00000030L
8975 #define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK                                                    0x00000100L
8976 #define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK                                              0x00000200L
8977 #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK                                             0x00000400L
8978 #define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK                                             0x00000800L
8979 #define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK                                                             0x00007000L
8980 #define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK                                                              0x00038000L
8981 #define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK                                                             0x00040000L
8982 #define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK                                                        0x00180000L
8983 #define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK                                                          0x03E00000L
8984 #define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK                                                               0x0C000000L
8985 //VM_L2_CNTL2
8986 #define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT                                                            0x0
8987 #define VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT                                                               0x1
8988 #define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT                                                     0x15
8989 #define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT                                                   0x16
8990 #define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT                                                            0x17
8991 #define VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT                                                             0x1a
8992 #define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT                                                          0x1c
8993 #define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK                                                              0x00000001L
8994 #define VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK                                                                 0x00000002L
8995 #define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK                                                       0x00200000L
8996 #define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK                                                     0x00400000L
8997 #define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK                                                              0x03800000L
8998 #define VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK                                                               0x0C000000L
8999 #define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK                                                            0x70000000L
9000 //VM_L2_CNTL3
9001 #define VM_L2_CNTL3__BANK_SELECT__SHIFT                                                                       0x0
9002 #define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT                                                              0x6
9003 #define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT                                          0x8
9004 #define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT                                                       0xf
9005 #define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT                                                       0x14
9006 #define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT                                                        0x15
9007 #define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT                                                      0x18
9008 #define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT                                                            0x1c
9009 #define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT                                                          0x1d
9010 #define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT                                                              0x1e
9011 #define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT                                                         0x1f
9012 #define VM_L2_CNTL3__BANK_SELECT_MASK                                                                         0x0000003FL
9013 #define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK                                                                0x000000C0L
9014 #define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK                                            0x00001F00L
9015 #define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                                                         0x000F8000L
9016 #define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK                                                         0x00100000L
9017 #define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK                                                          0x00E00000L
9018 #define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK                                                        0x0F000000L
9019 #define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK                                                              0x10000000L
9020 #define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK                                                            0x20000000L
9021 #define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK                                                                0x40000000L
9022 #define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK                                                           0x80000000L
9023 //VM_L2_STATUS
9024 #define VM_L2_STATUS__L2_BUSY__SHIFT                                                                          0x0
9025 #define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT                                                              0x1
9026 #define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT                                                 0x11
9027 #define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT                                               0x12
9028 #define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT                                                   0x13
9029 #define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT                                                   0x14
9030 #define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT                                                   0x15
9031 #define VM_L2_STATUS__L2_BUSY_MASK                                                                            0x00000001L
9032 #define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK                                                                0x0001FFFEL
9033 #define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK                                                   0x00020000L
9034 #define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK                                                 0x00040000L
9035 #define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK                                                     0x00080000L
9036 #define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK                                                     0x00100000L
9037 #define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK                                                     0x00200000L
9038 //VM_DUMMY_PAGE_FAULT_CNTL
9039 #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT                                              0x0
9040 #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT                                           0x1
9041 #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT                                              0x2
9042 #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK                                                0x00000001L
9043 #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK                                             0x00000002L
9044 #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK                                                0x000000FCL
9045 //VM_DUMMY_PAGE_FAULT_ADDR_LO32
9046 #define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT                                            0x0
9047 #define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK                                              0xFFFFFFFFL
9048 //VM_DUMMY_PAGE_FAULT_ADDR_HI32
9049 #define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT                                             0x0
9050 #define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK                                               0x0000000FL
9051 //VM_L2_PROTECTION_FAULT_CNTL
9052 #define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                0x0
9053 #define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT             0x1
9054 #define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                             0x2
9055 #define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0x3
9056 #define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0x4
9057 #define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0x5
9058 #define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                 0x6
9059 #define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0x7
9060 #define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                        0x8
9061 #define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                             0x9
9062 #define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0xa
9063 #define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                             0xb
9064 #define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                           0xc
9065 #define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT                                0xd
9066 #define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT                          0x1d
9067 #define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT                                           0x1e
9068 #define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT                                              0x1f
9069 #define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                  0x00000001L
9070 #define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK               0x00000002L
9071 #define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                               0x00000004L
9072 #define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x00000008L
9073 #define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x00000010L
9074 #define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x00000020L
9075 #define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                   0x00000040L
9076 #define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x00000080L
9077 #define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                          0x00000100L
9078 #define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                               0x00000200L
9079 #define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x00000400L
9080 #define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                               0x00000800L
9081 #define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                             0x00001000L
9082 #define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK                                  0x1FFFE000L
9083 #define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK                            0x20000000L
9084 #define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK                                             0x40000000L
9085 #define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK                                                0x80000000L
9086 //VM_L2_PROTECTION_FAULT_CNTL2
9087 #define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT                                    0x0
9088 #define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT                              0x10
9089 #define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT                                        0x11
9090 #define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT                             0x12
9091 #define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT                                     0x13
9092 #define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK                                      0x0000FFFFL
9093 #define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK                                0x00010000L
9094 #define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK                                          0x00020000L
9095 #define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK                               0x00040000L
9096 #define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK                                       0x00080000L
9097 //VM_L2_PROTECTION_FAULT_MM_CNTL3
9098 #define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT                  0x0
9099 #define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK                    0xFFFFFFFFL
9100 //VM_L2_PROTECTION_FAULT_MM_CNTL4
9101 #define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT                 0x0
9102 #define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK                   0xFFFFFFFFL
9103 //VM_L2_PROTECTION_FAULT_STATUS
9104 #define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT                                                     0x0
9105 #define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT                                                    0x1
9106 #define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT                                               0x4
9107 #define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT                                                   0x8
9108 #define VM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT                                                             0x9
9109 #define VM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT                                                              0x12
9110 #define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT                                                          0x13
9111 #define VM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT                                                            0x14
9112 #define VM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT                                                              0x18
9113 #define VM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT                                                            0x19
9114 #define VM_L2_PROTECTION_FAULT_STATUS__UCE__SHIFT                                                             0x1d
9115 #define VM_L2_PROTECTION_FAULT_STATUS__FED__SHIFT                                                             0x1e
9116 #define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK                                                       0x00000001L
9117 #define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK                                                      0x0000000EL
9118 #define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK                                                 0x000000F0L
9119 #define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK                                                     0x00000100L
9120 #define VM_L2_PROTECTION_FAULT_STATUS__CID_MASK                                                               0x0003FE00L
9121 #define VM_L2_PROTECTION_FAULT_STATUS__RW_MASK                                                                0x00040000L
9122 #define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK                                                            0x00080000L
9123 #define VM_L2_PROTECTION_FAULT_STATUS__VMID_MASK                                                              0x00F00000L
9124 #define VM_L2_PROTECTION_FAULT_STATUS__VF_MASK                                                                0x01000000L
9125 #define VM_L2_PROTECTION_FAULT_STATUS__VFID_MASK                                                              0x1E000000L
9126 #define VM_L2_PROTECTION_FAULT_STATUS__UCE_MASK                                                               0x20000000L
9127 #define VM_L2_PROTECTION_FAULT_STATUS__FED_MASK                                                               0x40000000L
9128 //VM_L2_PROTECTION_FAULT_ADDR_LO32
9129 #define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT                                       0x0
9130 #define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK                                         0xFFFFFFFFL
9131 //VM_L2_PROTECTION_FAULT_ADDR_HI32
9132 #define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT                                        0x0
9133 #define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK                                          0x0000000FL
9134 //VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32
9135 #define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT                              0x0
9136 #define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK                                0xFFFFFFFFL
9137 //VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32
9138 #define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT                               0x0
9139 #define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK                                 0x0000000FL
9140 //VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32
9141 #define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                       0x0
9142 #define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                         0xFFFFFFFFL
9143 //VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32
9144 #define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                        0x0
9145 #define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                          0x0000000FL
9146 //VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32
9147 #define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                      0x0
9148 #define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                        0xFFFFFFFFL
9149 //VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32
9150 #define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                       0x0
9151 #define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                         0x0000000FL
9152 //VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32
9153 #define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT                         0x0
9154 #define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK                           0xFFFFFFFFL
9155 //VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32
9156 #define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT                          0x0
9157 #define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK                            0x0000000FL
9158 //VM_L2_CNTL4
9159 #define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT                                                       0x0
9160 #define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT                                                      0x6
9161 #define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT                                                      0x7
9162 #define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT                                           0x8
9163 #define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT                                          0x12
9164 #define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT                                                               0x1c
9165 #define VM_L2_CNTL4__GC_CH_FGCG_OFF__SHIFT                                                                    0x1d
9166 #define VM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE__SHIFT                                                               0x1e
9167 #define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK                                                         0x0000003FL
9168 #define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK                                                        0x00000040L
9169 #define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK                                                        0x00000080L
9170 #define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK                                             0x0003FF00L
9171 #define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK                                            0x0FFC0000L
9172 #define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK                                                                 0x10000000L
9173 #define VM_L2_CNTL4__GC_CH_FGCG_OFF_MASK                                                                      0x20000000L
9174 #define VM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE_MASK                                                                 0x40000000L
9175 //VM_L2_CNTL5
9176 #define VM_L2_CNTL5__WALKER_FETCH_PDE_MTYPE_ENABLE__SHIFT                                                     0x0
9177 #define VM_L2_CNTL5__WALKER_FETCH_PDE_NOALLOC_ENABLE__SHIFT                                                   0x1
9178 #define VM_L2_CNTL5__WALKER_FETCH_PDE_MTYPE_ENABLE_MASK                                                       0x00000001L
9179 #define VM_L2_CNTL5__WALKER_FETCH_PDE_NOALLOC_ENABLE_MASK                                                     0x00000002L
9180 //VM_L2_MM_GROUP_RT_CLASSES
9181 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT                                                    0x0
9182 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT                                                    0x1
9183 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT                                                    0x2
9184 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT                                                    0x3
9185 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT                                                    0x4
9186 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT                                                    0x5
9187 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT                                                    0x6
9188 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT                                                    0x7
9189 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT                                                    0x8
9190 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT                                                    0x9
9191 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT                                                   0xa
9192 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT                                                   0xb
9193 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT                                                   0xc
9194 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT                                                   0xd
9195 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT                                                   0xe
9196 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT                                                   0xf
9197 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT                                                   0x10
9198 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT                                                   0x11
9199 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT                                                   0x12
9200 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT                                                   0x13
9201 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT                                                   0x14
9202 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT                                                   0x15
9203 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT                                                   0x16
9204 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT                                                   0x17
9205 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT                                                   0x18
9206 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT                                                   0x19
9207 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT                                                   0x1a
9208 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT                                                   0x1b
9209 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT                                                   0x1c
9210 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT                                                   0x1d
9211 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT                                                   0x1e
9212 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT                                                   0x1f
9213 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK                                                      0x00000001L
9214 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK                                                      0x00000002L
9215 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK                                                      0x00000004L
9216 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK                                                      0x00000008L
9217 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK                                                      0x00000010L
9218 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK                                                      0x00000020L
9219 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK                                                      0x00000040L
9220 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK                                                      0x00000080L
9221 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK                                                      0x00000100L
9222 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK                                                      0x00000200L
9223 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK                                                     0x00000400L
9224 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK                                                     0x00000800L
9225 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK                                                     0x00001000L
9226 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK                                                     0x00002000L
9227 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK                                                     0x00004000L
9228 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK                                                     0x00008000L
9229 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK                                                     0x00010000L
9230 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK                                                     0x00020000L
9231 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK                                                     0x00040000L
9232 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK                                                     0x00080000L
9233 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK                                                     0x00100000L
9234 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK                                                     0x00200000L
9235 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK                                                     0x00400000L
9236 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK                                                     0x00800000L
9237 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK                                                     0x01000000L
9238 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK                                                     0x02000000L
9239 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK                                                     0x04000000L
9240 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK                                                     0x08000000L
9241 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK                                                     0x10000000L
9242 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK                                                     0x20000000L
9243 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK                                                     0x40000000L
9244 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK                                                     0x80000000L
9245 //VM_L2_BANK_SELECT_RESERVED_CID
9246 #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT                                        0x0
9247 #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT                                       0xa
9248 #define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT                                                         0x14
9249 #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT                               0x18
9250 #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT                            0x19
9251 #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK                                          0x000001FFL
9252 #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK                                         0x0007FC00L
9253 #define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK                                                           0x00100000L
9254 #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK                                 0x01000000L
9255 #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK                              0x02000000L
9256 //VM_L2_BANK_SELECT_RESERVED_CID2
9257 #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT                                       0x0
9258 #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT                                      0xa
9259 #define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT                                                        0x14
9260 #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT                              0x18
9261 #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT                           0x19
9262 #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK                                         0x000001FFL
9263 #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK                                        0x0007FC00L
9264 #define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK                                                          0x00100000L
9265 #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK                                0x01000000L
9266 #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK                             0x02000000L
9267 //VM_L2_CACHE_PARITY_CNTL
9268 #define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT                                 0x0
9269 #define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT                               0x1
9270 #define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT                                    0x2
9271 #define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT                                 0x3
9272 #define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT                               0x4
9273 #define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT                                    0x5
9274 #define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT                                                      0x6
9275 #define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT                                                    0x9
9276 #define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT                                                     0xc
9277 #define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK                                   0x00000001L
9278 #define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK                                 0x00000002L
9279 #define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK                                      0x00000004L
9280 #define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK                                   0x00000008L
9281 #define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK                                 0x00000010L
9282 #define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK                                      0x00000020L
9283 #define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK                                                        0x000001C0L
9284 #define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK                                                      0x00000E00L
9285 #define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK                                                       0x0000F000L
9286 //VM_L2_CGTT_CLK_CTRL
9287 #define VM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                                  0x0
9288 #define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                            0x4
9289 #define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT                                                             0xf
9290 #define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                       0x10
9291 #define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT                                                             0x18
9292 #define VM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                    0x0000000FL
9293 #define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                              0x00000FF0L
9294 #define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK                                                               0x00008000L
9295 #define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                         0x00FF0000L
9296 #define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK                                                               0xFF000000L
9297 //VM_L2_CGTT_BUSY_CTRL
9298 #define VM_L2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT                                                               0x0
9299 #define VM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT                                                              0x4
9300 #define VM_L2_CGTT_BUSY_CTRL__READ_DELAY_MASK                                                                 0x0000000FL
9301 #define VM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK                                                                0x00000010L
9302 //VML2_MEM_ECC_INDEX
9303 #define VML2_MEM_ECC_INDEX__INDEX__SHIFT                                                                      0x0
9304 #define VML2_MEM_ECC_INDEX__INDEX_MASK                                                                        0x000000FFL
9305 //VML2_WALKER_MEM_ECC_INDEX
9306 #define VML2_WALKER_MEM_ECC_INDEX__INDEX__SHIFT                                                               0x0
9307 #define VML2_WALKER_MEM_ECC_INDEX__INDEX_MASK                                                                 0x000000FFL
9308 //UTCL2_MEM_ECC_INDEX
9309 #define UTCL2_MEM_ECC_INDEX__INDEX__SHIFT                                                                     0x0
9310 #define UTCL2_MEM_ECC_INDEX__INDEX_MASK                                                                       0x000000FFL
9311 //VML2_MEM_ECC_CNTL
9312 #define VML2_MEM_ECC_CNTL__INJECT_DELAY__SHIFT                                                                0x0
9313 #define VML2_MEM_ECC_CNTL__DSM_IRRITATOR_DATA__SHIFT                                                          0x6
9314 #define VML2_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE__SHIFT                                                         0x8
9315 #define VML2_MEM_ECC_CNTL__ENABLE_ERROR_INJECT__SHIFT                                                         0x9
9316 #define VML2_MEM_ECC_CNTL__SELECT_INJECT_DELAY__SHIFT                                                         0xb
9317 #define VML2_MEM_ECC_CNTL__SEC_COUNT__SHIFT                                                                   0xc
9318 #define VML2_MEM_ECC_CNTL__DED_COUNT__SHIFT                                                                   0xe
9319 #define VML2_MEM_ECC_CNTL__WRITE_COUNTERS__SHIFT                                                              0x10
9320 #define VML2_MEM_ECC_CNTL__TEST_FUE__SHIFT                                                                    0x11
9321 #define VML2_MEM_ECC_CNTL__INJECT_DELAY_MASK                                                                  0x0000003FL
9322 #define VML2_MEM_ECC_CNTL__DSM_IRRITATOR_DATA_MASK                                                            0x000000C0L
9323 #define VML2_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE_MASK                                                           0x00000100L
9324 #define VML2_MEM_ECC_CNTL__ENABLE_ERROR_INJECT_MASK                                                           0x00000600L
9325 #define VML2_MEM_ECC_CNTL__SELECT_INJECT_DELAY_MASK                                                           0x00000800L
9326 #define VML2_MEM_ECC_CNTL__SEC_COUNT_MASK                                                                     0x00003000L
9327 #define VML2_MEM_ECC_CNTL__DED_COUNT_MASK                                                                     0x0000C000L
9328 #define VML2_MEM_ECC_CNTL__WRITE_COUNTERS_MASK                                                                0x00010000L
9329 #define VML2_MEM_ECC_CNTL__TEST_FUE_MASK                                                                      0x00020000L
9330 //VML2_WALKER_MEM_ECC_CNTL
9331 #define VML2_WALKER_MEM_ECC_CNTL__INJECT_DELAY__SHIFT                                                         0x0
9332 #define VML2_WALKER_MEM_ECC_CNTL__DSM_IRRITATOR_DATA__SHIFT                                                   0x6
9333 #define VML2_WALKER_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE__SHIFT                                                  0x8
9334 #define VML2_WALKER_MEM_ECC_CNTL__ENABLE_ERROR_INJECT__SHIFT                                                  0x9
9335 #define VML2_WALKER_MEM_ECC_CNTL__SELECT_INJECT_DELAY__SHIFT                                                  0xb
9336 #define VML2_WALKER_MEM_ECC_CNTL__SEC_COUNT__SHIFT                                                            0xc
9337 #define VML2_WALKER_MEM_ECC_CNTL__DED_COUNT__SHIFT                                                            0xe
9338 #define VML2_WALKER_MEM_ECC_CNTL__WRITE_COUNTERS__SHIFT                                                       0x10
9339 #define VML2_WALKER_MEM_ECC_CNTL__TEST_FUE__SHIFT                                                             0x11
9340 #define VML2_WALKER_MEM_ECC_CNTL__INJECT_DELAY_MASK                                                           0x0000003FL
9341 #define VML2_WALKER_MEM_ECC_CNTL__DSM_IRRITATOR_DATA_MASK                                                     0x000000C0L
9342 #define VML2_WALKER_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE_MASK                                                    0x00000100L
9343 #define VML2_WALKER_MEM_ECC_CNTL__ENABLE_ERROR_INJECT_MASK                                                    0x00000600L
9344 #define VML2_WALKER_MEM_ECC_CNTL__SELECT_INJECT_DELAY_MASK                                                    0x00000800L
9345 #define VML2_WALKER_MEM_ECC_CNTL__SEC_COUNT_MASK                                                              0x00003000L
9346 #define VML2_WALKER_MEM_ECC_CNTL__DED_COUNT_MASK                                                              0x0000C000L
9347 #define VML2_WALKER_MEM_ECC_CNTL__WRITE_COUNTERS_MASK                                                         0x00010000L
9348 #define VML2_WALKER_MEM_ECC_CNTL__TEST_FUE_MASK                                                               0x00020000L
9349 //UTCL2_MEM_ECC_CNTL
9350 #define UTCL2_MEM_ECC_CNTL__INJECT_DELAY__SHIFT                                                               0x0
9351 #define UTCL2_MEM_ECC_CNTL__DSM_IRRITATOR_DATA__SHIFT                                                         0x6
9352 #define UTCL2_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE__SHIFT                                                        0x8
9353 #define UTCL2_MEM_ECC_CNTL__ENABLE_ERROR_INJECT__SHIFT                                                        0x9
9354 #define UTCL2_MEM_ECC_CNTL__SELECT_INJECT_DELAY__SHIFT                                                        0xb
9355 #define UTCL2_MEM_ECC_CNTL__SEC_COUNT__SHIFT                                                                  0xc
9356 #define UTCL2_MEM_ECC_CNTL__DED_COUNT__SHIFT                                                                  0xe
9357 #define UTCL2_MEM_ECC_CNTL__WRITE_COUNTERS__SHIFT                                                             0x10
9358 #define UTCL2_MEM_ECC_CNTL__TEST_FUE__SHIFT                                                                   0x11
9359 #define UTCL2_MEM_ECC_CNTL__INJECT_DELAY_MASK                                                                 0x0000003FL
9360 #define UTCL2_MEM_ECC_CNTL__DSM_IRRITATOR_DATA_MASK                                                           0x000000C0L
9361 #define UTCL2_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE_MASK                                                          0x00000100L
9362 #define UTCL2_MEM_ECC_CNTL__ENABLE_ERROR_INJECT_MASK                                                          0x00000600L
9363 #define UTCL2_MEM_ECC_CNTL__SELECT_INJECT_DELAY_MASK                                                          0x00000800L
9364 #define UTCL2_MEM_ECC_CNTL__SEC_COUNT_MASK                                                                    0x00003000L
9365 #define UTCL2_MEM_ECC_CNTL__DED_COUNT_MASK                                                                    0x0000C000L
9366 #define UTCL2_MEM_ECC_CNTL__WRITE_COUNTERS_MASK                                                               0x00010000L
9367 #define UTCL2_MEM_ECC_CNTL__TEST_FUE_MASK                                                                     0x00020000L
9368 //VML2_MEM_ECC_STATUS
9369 #define VML2_MEM_ECC_STATUS__UCE__SHIFT                                                                       0x0
9370 #define VML2_MEM_ECC_STATUS__FED__SHIFT                                                                       0x1
9371 #define VML2_MEM_ECC_STATUS__UCE_MASK                                                                         0x00000001L
9372 #define VML2_MEM_ECC_STATUS__FED_MASK                                                                         0x00000002L
9373 //VML2_WALKER_MEM_ECC_STATUS
9374 #define VML2_WALKER_MEM_ECC_STATUS__UCE__SHIFT                                                                0x0
9375 #define VML2_WALKER_MEM_ECC_STATUS__FED__SHIFT                                                                0x1
9376 #define VML2_WALKER_MEM_ECC_STATUS__UCE_MASK                                                                  0x00000001L
9377 #define VML2_WALKER_MEM_ECC_STATUS__FED_MASK                                                                  0x00000002L
9378 //UTCL2_MEM_ECC_STATUS
9379 #define UTCL2_MEM_ECC_STATUS__UCE__SHIFT                                                                      0x0
9380 #define UTCL2_MEM_ECC_STATUS__FED__SHIFT                                                                      0x1
9381 #define UTCL2_MEM_ECC_STATUS__UCE_MASK                                                                        0x00000001L
9382 #define UTCL2_MEM_ECC_STATUS__FED_MASK                                                                        0x00000002L
9383 //UTCL2_EDC_MODE
9384 #define UTCL2_EDC_MODE__FORCE_SEC_ON_DED__SHIFT                                                               0xf
9385 #define UTCL2_EDC_MODE__COUNT_FED_OUT__SHIFT                                                                  0x10
9386 #define UTCL2_EDC_MODE__GATE_FUE__SHIFT                                                                       0x11
9387 #define UTCL2_EDC_MODE__DED_MODE__SHIFT                                                                       0x14
9388 #define UTCL2_EDC_MODE__PROP_FED__SHIFT                                                                       0x1d
9389 #define UTCL2_EDC_MODE__BYPASS__SHIFT                                                                         0x1f
9390 #define UTCL2_EDC_MODE__FORCE_SEC_ON_DED_MASK                                                                 0x00008000L
9391 #define UTCL2_EDC_MODE__COUNT_FED_OUT_MASK                                                                    0x00010000L
9392 #define UTCL2_EDC_MODE__GATE_FUE_MASK                                                                         0x00020000L
9393 #define UTCL2_EDC_MODE__DED_MODE_MASK                                                                         0x00300000L
9394 #define UTCL2_EDC_MODE__PROP_FED_MASK                                                                         0x20000000L
9395 #define UTCL2_EDC_MODE__BYPASS_MASK                                                                           0x80000000L
9396 //UTCL2_EDC_CONFIG
9397 #define UTCL2_EDC_CONFIG__WRITE_DIS__SHIFT                                                                    0x0
9398 #define UTCL2_EDC_CONFIG__DIS_EDC__SHIFT                                                                      0x1
9399 #define UTCL2_EDC_CONFIG__WRITE_DIS_MASK                                                                      0x00000001L
9400 #define UTCL2_EDC_CONFIG__DIS_EDC_MASK                                                                        0x00000002L
9401 //VML2_UE_ERR_STATUS_LO
9402 #define VML2_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT                                                   0x0
9403 #define VML2_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT                                                      0x1
9404 #define VML2_UE_ERR_STATUS_LO__ADDRESS__SHIFT                                                                 0x2
9405 #define VML2_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT                                                               0x18
9406 #define VML2_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK                                                     0x00000001L
9407 #define VML2_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK                                                        0x00000002L
9408 #define VML2_UE_ERR_STATUS_LO__ADDRESS_MASK                                                                   0x00FFFFFCL
9409 #define VML2_UE_ERR_STATUS_LO__MEMORY_ID_MASK                                                                 0xFF000000L
9410 //VML2_WALKER_UE_ERR_STATUS_LO
9411 #define VML2_WALKER_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT                                            0x0
9412 #define VML2_WALKER_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT                                               0x1
9413 #define VML2_WALKER_UE_ERR_STATUS_LO__ADDRESS__SHIFT                                                          0x2
9414 #define VML2_WALKER_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT                                                        0x18
9415 #define VML2_WALKER_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK                                              0x00000001L
9416 #define VML2_WALKER_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK                                                 0x00000002L
9417 #define VML2_WALKER_UE_ERR_STATUS_LO__ADDRESS_MASK                                                            0x00FFFFFCL
9418 #define VML2_WALKER_UE_ERR_STATUS_LO__MEMORY_ID_MASK                                                          0xFF000000L
9419 //UTCL2_UE_ERR_STATUS_LO
9420 #define UTCL2_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT                                                  0x0
9421 #define UTCL2_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT                                                     0x1
9422 #define UTCL2_UE_ERR_STATUS_LO__ADDRESS__SHIFT                                                                0x2
9423 #define UTCL2_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT                                                              0x18
9424 #define UTCL2_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK                                                    0x00000001L
9425 #define UTCL2_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK                                                       0x00000002L
9426 #define UTCL2_UE_ERR_STATUS_LO__ADDRESS_MASK                                                                  0x00FFFFFCL
9427 #define UTCL2_UE_ERR_STATUS_LO__MEMORY_ID_MASK                                                                0xFF000000L
9428 //VML2_UE_ERR_STATUS_HI
9429 #define VML2_UE_ERR_STATUS_HI__ECC__SHIFT                                                                     0x0
9430 #define VML2_UE_ERR_STATUS_HI__PARITY__SHIFT                                                                  0x1
9431 #define VML2_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT                                                     0x2
9432 #define VML2_UE_ERR_STATUS_HI__ERR_INFO__SHIFT                                                                0x3
9433 #define VML2_UE_ERR_STATUS_HI__UE_CNT__SHIFT                                                                  0x17
9434 #define VML2_UE_ERR_STATUS_HI__FED_CNT__SHIFT                                                                 0x1a
9435 #define VML2_UE_ERR_STATUS_HI__RESERVED__SHIFT                                                                0x1d
9436 #define VML2_UE_ERR_STATUS_HI__ECC_MASK                                                                       0x00000001L
9437 #define VML2_UE_ERR_STATUS_HI__PARITY_MASK                                                                    0x00000002L
9438 #define VML2_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK                                                       0x00000004L
9439 #define VML2_UE_ERR_STATUS_HI__ERR_INFO_MASK                                                                  0x007FFFF8L
9440 #define VML2_UE_ERR_STATUS_HI__UE_CNT_MASK                                                                    0x03800000L
9441 #define VML2_UE_ERR_STATUS_HI__FED_CNT_MASK                                                                   0x1C000000L
9442 #define VML2_UE_ERR_STATUS_HI__RESERVED_MASK                                                                  0xE0000000L
9443 //VML2_WALKER_UE_ERR_STATUS_HI
9444 #define VML2_WALKER_UE_ERR_STATUS_HI__ECC__SHIFT                                                              0x0
9445 #define VML2_WALKER_UE_ERR_STATUS_HI__PARITY__SHIFT                                                           0x1
9446 #define VML2_WALKER_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT                                              0x2
9447 #define VML2_WALKER_UE_ERR_STATUS_HI__ERR_INFO__SHIFT                                                         0x3
9448 #define VML2_WALKER_UE_ERR_STATUS_HI__UE_CNT__SHIFT                                                           0x17
9449 #define VML2_WALKER_UE_ERR_STATUS_HI__FED_CNT__SHIFT                                                          0x1a
9450 #define VML2_WALKER_UE_ERR_STATUS_HI__RESERVED__SHIFT                                                         0x1d
9451 #define VML2_WALKER_UE_ERR_STATUS_HI__ECC_MASK                                                                0x00000001L
9452 #define VML2_WALKER_UE_ERR_STATUS_HI__PARITY_MASK                                                             0x00000002L
9453 #define VML2_WALKER_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK                                                0x00000004L
9454 #define VML2_WALKER_UE_ERR_STATUS_HI__ERR_INFO_MASK                                                           0x007FFFF8L
9455 #define VML2_WALKER_UE_ERR_STATUS_HI__UE_CNT_MASK                                                             0x03800000L
9456 #define VML2_WALKER_UE_ERR_STATUS_HI__FED_CNT_MASK                                                            0x1C000000L
9457 #define VML2_WALKER_UE_ERR_STATUS_HI__RESERVED_MASK                                                           0xE0000000L
9458 //UTCL2_UE_ERR_STATUS_HI
9459 #define UTCL2_UE_ERR_STATUS_HI__ECC__SHIFT                                                                    0x0
9460 #define UTCL2_UE_ERR_STATUS_HI__PARITY__SHIFT                                                                 0x1
9461 #define UTCL2_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT                                                    0x2
9462 #define UTCL2_UE_ERR_STATUS_HI__ERR_INFO__SHIFT                                                               0x3
9463 #define UTCL2_UE_ERR_STATUS_HI__UE_CNT__SHIFT                                                                 0x17
9464 #define UTCL2_UE_ERR_STATUS_HI__FED_CNT__SHIFT                                                                0x1a
9465 #define UTCL2_UE_ERR_STATUS_HI__RESERVED__SHIFT                                                               0x1d
9466 #define UTCL2_UE_ERR_STATUS_HI__ECC_MASK                                                                      0x00000001L
9467 #define UTCL2_UE_ERR_STATUS_HI__PARITY_MASK                                                                   0x00000002L
9468 #define UTCL2_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK                                                      0x00000004L
9469 #define UTCL2_UE_ERR_STATUS_HI__ERR_INFO_MASK                                                                 0x007FFFF8L
9470 #define UTCL2_UE_ERR_STATUS_HI__UE_CNT_MASK                                                                   0x03800000L
9471 #define UTCL2_UE_ERR_STATUS_HI__FED_CNT_MASK                                                                  0x1C000000L
9472 #define UTCL2_UE_ERR_STATUS_HI__RESERVED_MASK                                                                 0xE0000000L
9473 //VML2_CE_ERR_STATUS_LO
9474 #define VML2_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT                                                   0x0
9475 #define VML2_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT                                                      0x1
9476 #define VML2_CE_ERR_STATUS_LO__ADDRESS__SHIFT                                                                 0x2
9477 #define VML2_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT                                                               0x18
9478 #define VML2_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK                                                     0x00000001L
9479 #define VML2_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK                                                        0x00000002L
9480 #define VML2_CE_ERR_STATUS_LO__ADDRESS_MASK                                                                   0x00FFFFFCL
9481 #define VML2_CE_ERR_STATUS_LO__MEMORY_ID_MASK                                                                 0xFF000000L
9482 //VML2_WALKER_CE_ERR_STATUS_LO
9483 #define VML2_WALKER_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT                                            0x0
9484 #define VML2_WALKER_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT                                               0x1
9485 #define VML2_WALKER_CE_ERR_STATUS_LO__ADDRESS__SHIFT                                                          0x2
9486 #define VML2_WALKER_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT                                                        0x18
9487 #define VML2_WALKER_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK                                              0x00000001L
9488 #define VML2_WALKER_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK                                                 0x00000002L
9489 #define VML2_WALKER_CE_ERR_STATUS_LO__ADDRESS_MASK                                                            0x00FFFFFCL
9490 #define VML2_WALKER_CE_ERR_STATUS_LO__MEMORY_ID_MASK                                                          0xFF000000L
9491 //UTCL2_CE_ERR_STATUS_LO
9492 #define UTCL2_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT                                                  0x0
9493 #define UTCL2_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT                                                     0x1
9494 #define UTCL2_CE_ERR_STATUS_LO__ADDRESS__SHIFT                                                                0x2
9495 #define UTCL2_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT                                                              0x18
9496 #define UTCL2_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK                                                    0x00000001L
9497 #define UTCL2_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK                                                       0x00000002L
9498 #define UTCL2_CE_ERR_STATUS_LO__ADDRESS_MASK                                                                  0x00FFFFFCL
9499 #define UTCL2_CE_ERR_STATUS_LO__MEMORY_ID_MASK                                                                0xFF000000L
9500 //VML2_CE_ERR_STATUS_HI
9501 #define VML2_CE_ERR_STATUS_HI__ECC__SHIFT                                                                     0x0
9502 #define VML2_CE_ERR_STATUS_HI__OTHER__SHIFT                                                                   0x1
9503 #define VML2_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT                                                     0x2
9504 #define VML2_CE_ERR_STATUS_HI__ERR_INFO__SHIFT                                                                0x3
9505 #define VML2_CE_ERR_STATUS_HI__CE_CNT__SHIFT                                                                  0x17
9506 #define VML2_CE_ERR_STATUS_HI__POISON__SHIFT                                                                  0x1a
9507 #define VML2_CE_ERR_STATUS_HI__RESERVED__SHIFT                                                                0x1b
9508 #define VML2_CE_ERR_STATUS_HI__ECC_MASK                                                                       0x00000001L
9509 #define VML2_CE_ERR_STATUS_HI__OTHER_MASK                                                                     0x00000002L
9510 #define VML2_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK                                                       0x00000004L
9511 #define VML2_CE_ERR_STATUS_HI__ERR_INFO_MASK                                                                  0x007FFFF8L
9512 #define VML2_CE_ERR_STATUS_HI__CE_CNT_MASK                                                                    0x03800000L
9513 #define VML2_CE_ERR_STATUS_HI__POISON_MASK                                                                    0x04000000L
9514 #define VML2_CE_ERR_STATUS_HI__RESERVED_MASK                                                                  0xF8000000L
9515 //VML2_WALKER_CE_ERR_STATUS_HI
9516 #define VML2_WALKER_CE_ERR_STATUS_HI__ECC__SHIFT                                                              0x0
9517 #define VML2_WALKER_CE_ERR_STATUS_HI__OTHER__SHIFT                                                            0x1
9518 #define VML2_WALKER_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT                                              0x2
9519 #define VML2_WALKER_CE_ERR_STATUS_HI__ERR_INFO__SHIFT                                                         0x3
9520 #define VML2_WALKER_CE_ERR_STATUS_HI__CE_CNT__SHIFT                                                           0x17
9521 #define VML2_WALKER_CE_ERR_STATUS_HI__POISON__SHIFT                                                           0x1a
9522 #define VML2_WALKER_CE_ERR_STATUS_HI__RESERVED__SHIFT                                                         0x1b
9523 #define VML2_WALKER_CE_ERR_STATUS_HI__ECC_MASK                                                                0x00000001L
9524 #define VML2_WALKER_CE_ERR_STATUS_HI__OTHER_MASK                                                              0x00000002L
9525 #define VML2_WALKER_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK                                                0x00000004L
9526 #define VML2_WALKER_CE_ERR_STATUS_HI__ERR_INFO_MASK                                                           0x007FFFF8L
9527 #define VML2_WALKER_CE_ERR_STATUS_HI__CE_CNT_MASK                                                             0x03800000L
9528 #define VML2_WALKER_CE_ERR_STATUS_HI__POISON_MASK                                                             0x04000000L
9529 #define VML2_WALKER_CE_ERR_STATUS_HI__RESERVED_MASK                                                           0xF8000000L
9530 //UTCL2_CE_ERR_STATUS_HI
9531 #define UTCL2_CE_ERR_STATUS_HI__ECC__SHIFT                                                                    0x0
9532 #define UTCL2_CE_ERR_STATUS_HI__OTHER__SHIFT                                                                  0x1
9533 #define UTCL2_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT                                                    0x2
9534 #define UTCL2_CE_ERR_STATUS_HI__ERR_INFO__SHIFT                                                               0x3
9535 #define UTCL2_CE_ERR_STATUS_HI__CE_CNT__SHIFT                                                                 0x17
9536 #define UTCL2_CE_ERR_STATUS_HI__POISON__SHIFT                                                                 0x1a
9537 #define UTCL2_CE_ERR_STATUS_HI__RESERVED__SHIFT                                                               0x1b
9538 #define UTCL2_CE_ERR_STATUS_HI__ECC_MASK                                                                      0x00000001L
9539 #define UTCL2_CE_ERR_STATUS_HI__OTHER_MASK                                                                    0x00000002L
9540 #define UTCL2_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK                                                      0x00000004L
9541 #define UTCL2_CE_ERR_STATUS_HI__ERR_INFO_MASK                                                                 0x007FFFF8L
9542 #define UTCL2_CE_ERR_STATUS_HI__CE_CNT_MASK                                                                   0x03800000L
9543 #define UTCL2_CE_ERR_STATUS_HI__POISON_MASK                                                                   0x04000000L
9544 #define UTCL2_CE_ERR_STATUS_HI__RESERVED_MASK                                                                 0xF8000000L
9545 
9546 
9547 // addressBlock: xcd0_gc_utcl2_vml2vcdec
9548 //VM_CONTEXT0_CNTL
9549 #define VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT                                                               0x0
9550 #define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                             0x1
9551 #define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                        0x3
9552 #define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                       0x7
9553 #define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT                                                            0x8
9554 #define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x9
9555 #define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xa
9556 #define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0xb
9557 #define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0xc
9558 #define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0xd
9559 #define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0xe
9560 #define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xf
9561 #define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x10
9562 #define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0x11
9563 #define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0x12
9564 #define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x13
9565 #define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x14
9566 #define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x15
9567 #define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x16
9568 #define VM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x17
9569 #define VM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x18
9570 #define VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK                                                                 0x00000001L
9571 #define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK                                                               0x00000006L
9572 #define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                          0x00000078L
9573 #define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                         0x00000080L
9574 #define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK                                                              0x00000100L
9575 #define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00000200L
9576 #define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00000400L
9577 #define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00000800L
9578 #define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00001000L
9579 #define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00002000L
9580 #define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00004000L
9581 #define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00008000L
9582 #define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00010000L
9583 #define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00020000L
9584 #define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00040000L
9585 #define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00080000L
9586 #define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00100000L
9587 #define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00200000L
9588 #define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00400000L
9589 #define VM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00800000L
9590 #define VM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x01000000L
9591 //VM_CONTEXT1_CNTL
9592 #define VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT                                                               0x0
9593 #define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                             0x1
9594 #define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                        0x3
9595 #define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                       0x7
9596 #define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT                                                            0x8
9597 #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x9
9598 #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xa
9599 #define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0xb
9600 #define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0xc
9601 #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0xd
9602 #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0xe
9603 #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xf
9604 #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x10
9605 #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0x11
9606 #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0x12
9607 #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x13
9608 #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x14
9609 #define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x15
9610 #define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x16
9611 #define VM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x17
9612 #define VM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x18
9613 #define VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK                                                                 0x00000001L
9614 #define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK                                                               0x00000006L
9615 #define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                          0x00000078L
9616 #define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                         0x00000080L
9617 #define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK                                                              0x00000100L
9618 #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00000200L
9619 #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00000400L
9620 #define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00000800L
9621 #define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00001000L
9622 #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00002000L
9623 #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00004000L
9624 #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00008000L
9625 #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00010000L
9626 #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00020000L
9627 #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00040000L
9628 #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00080000L
9629 #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00100000L
9630 #define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00200000L
9631 #define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00400000L
9632 #define VM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00800000L
9633 #define VM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x01000000L
9634 //VM_CONTEXT2_CNTL
9635 #define VM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT                                                               0x0
9636 #define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                             0x1
9637 #define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                        0x3
9638 #define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                       0x7
9639 #define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT                                                            0x8
9640 #define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x9
9641 #define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xa
9642 #define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0xb
9643 #define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0xc
9644 #define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0xd
9645 #define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0xe
9646 #define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xf
9647 #define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x10
9648 #define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0x11
9649 #define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0x12
9650 #define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x13
9651 #define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x14
9652 #define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x15
9653 #define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x16
9654 #define VM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x17
9655 #define VM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x18
9656 #define VM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK                                                                 0x00000001L
9657 #define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK                                                               0x00000006L
9658 #define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                          0x00000078L
9659 #define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                         0x00000080L
9660 #define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK                                                              0x00000100L
9661 #define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00000200L
9662 #define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00000400L
9663 #define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00000800L
9664 #define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00001000L
9665 #define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00002000L
9666 #define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00004000L
9667 #define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00008000L
9668 #define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00010000L
9669 #define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00020000L
9670 #define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00040000L
9671 #define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00080000L
9672 #define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00100000L
9673 #define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00200000L
9674 #define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00400000L
9675 #define VM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00800000L
9676 #define VM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x01000000L
9677 //VM_CONTEXT3_CNTL
9678 #define VM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT                                                               0x0
9679 #define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                             0x1
9680 #define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                        0x3
9681 #define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                       0x7
9682 #define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT                                                            0x8
9683 #define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x9
9684 #define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xa
9685 #define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0xb
9686 #define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0xc
9687 #define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0xd
9688 #define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0xe
9689 #define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xf
9690 #define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x10
9691 #define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0x11
9692 #define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0x12
9693 #define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x13
9694 #define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x14
9695 #define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x15
9696 #define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x16
9697 #define VM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x17
9698 #define VM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x18
9699 #define VM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK                                                                 0x00000001L
9700 #define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK                                                               0x00000006L
9701 #define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                          0x00000078L
9702 #define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                         0x00000080L
9703 #define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK                                                              0x00000100L
9704 #define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00000200L
9705 #define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00000400L
9706 #define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00000800L
9707 #define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00001000L
9708 #define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00002000L
9709 #define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00004000L
9710 #define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00008000L
9711 #define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00010000L
9712 #define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00020000L
9713 #define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00040000L
9714 #define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00080000L
9715 #define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00100000L
9716 #define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00200000L
9717 #define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00400000L
9718 #define VM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00800000L
9719 #define VM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x01000000L
9720 //VM_CONTEXT4_CNTL
9721 #define VM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT                                                               0x0
9722 #define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                             0x1
9723 #define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                        0x3
9724 #define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                       0x7
9725 #define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT                                                            0x8
9726 #define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x9
9727 #define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xa
9728 #define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0xb
9729 #define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0xc
9730 #define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0xd
9731 #define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0xe
9732 #define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xf
9733 #define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x10
9734 #define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0x11
9735 #define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0x12
9736 #define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x13
9737 #define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x14
9738 #define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x15
9739 #define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x16
9740 #define VM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x17
9741 #define VM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x18
9742 #define VM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK                                                                 0x00000001L
9743 #define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK                                                               0x00000006L
9744 #define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                          0x00000078L
9745 #define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                         0x00000080L
9746 #define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK                                                              0x00000100L
9747 #define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00000200L
9748 #define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00000400L
9749 #define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00000800L
9750 #define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00001000L
9751 #define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00002000L
9752 #define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00004000L
9753 #define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00008000L
9754 #define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00010000L
9755 #define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00020000L
9756 #define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00040000L
9757 #define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00080000L
9758 #define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00100000L
9759 #define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00200000L
9760 #define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00400000L
9761 #define VM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00800000L
9762 #define VM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x01000000L
9763 //VM_CONTEXT5_CNTL
9764 #define VM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT                                                               0x0
9765 #define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                             0x1
9766 #define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                        0x3
9767 #define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                       0x7
9768 #define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT                                                            0x8
9769 #define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x9
9770 #define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xa
9771 #define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0xb
9772 #define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0xc
9773 #define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0xd
9774 #define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0xe
9775 #define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xf
9776 #define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x10
9777 #define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0x11
9778 #define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0x12
9779 #define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x13
9780 #define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x14
9781 #define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x15
9782 #define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x16
9783 #define VM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x17
9784 #define VM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x18
9785 #define VM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK                                                                 0x00000001L
9786 #define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK                                                               0x00000006L
9787 #define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                          0x00000078L
9788 #define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                         0x00000080L
9789 #define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK                                                              0x00000100L
9790 #define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00000200L
9791 #define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00000400L
9792 #define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00000800L
9793 #define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00001000L
9794 #define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00002000L
9795 #define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00004000L
9796 #define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00008000L
9797 #define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00010000L
9798 #define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00020000L
9799 #define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00040000L
9800 #define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00080000L
9801 #define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00100000L
9802 #define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00200000L
9803 #define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00400000L
9804 #define VM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00800000L
9805 #define VM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x01000000L
9806 //VM_CONTEXT6_CNTL
9807 #define VM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT                                                               0x0
9808 #define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                             0x1
9809 #define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                        0x3
9810 #define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                       0x7
9811 #define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT                                                            0x8
9812 #define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x9
9813 #define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xa
9814 #define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0xb
9815 #define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0xc
9816 #define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0xd
9817 #define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0xe
9818 #define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xf
9819 #define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x10
9820 #define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0x11
9821 #define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0x12
9822 #define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x13
9823 #define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x14
9824 #define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x15
9825 #define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x16
9826 #define VM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x17
9827 #define VM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x18
9828 #define VM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK                                                                 0x00000001L
9829 #define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK                                                               0x00000006L
9830 #define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                          0x00000078L
9831 #define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                         0x00000080L
9832 #define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK                                                              0x00000100L
9833 #define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00000200L
9834 #define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00000400L
9835 #define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00000800L
9836 #define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00001000L
9837 #define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00002000L
9838 #define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00004000L
9839 #define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00008000L
9840 #define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00010000L
9841 #define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00020000L
9842 #define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00040000L
9843 #define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00080000L
9844 #define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00100000L
9845 #define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00200000L
9846 #define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00400000L
9847 #define VM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00800000L
9848 #define VM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x01000000L
9849 //VM_CONTEXT7_CNTL
9850 #define VM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT                                                               0x0
9851 #define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                             0x1
9852 #define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                        0x3
9853 #define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                       0x7
9854 #define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT                                                            0x8
9855 #define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x9
9856 #define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xa
9857 #define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0xb
9858 #define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0xc
9859 #define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0xd
9860 #define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0xe
9861 #define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xf
9862 #define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x10
9863 #define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0x11
9864 #define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0x12
9865 #define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x13
9866 #define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x14
9867 #define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x15
9868 #define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x16
9869 #define VM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x17
9870 #define VM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x18
9871 #define VM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK                                                                 0x00000001L
9872 #define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK                                                               0x00000006L
9873 #define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                          0x00000078L
9874 #define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                         0x00000080L
9875 #define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK                                                              0x00000100L
9876 #define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00000200L
9877 #define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00000400L
9878 #define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00000800L
9879 #define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00001000L
9880 #define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00002000L
9881 #define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00004000L
9882 #define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00008000L
9883 #define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00010000L
9884 #define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00020000L
9885 #define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00040000L
9886 #define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00080000L
9887 #define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00100000L
9888 #define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00200000L
9889 #define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00400000L
9890 #define VM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00800000L
9891 #define VM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x01000000L
9892 //VM_CONTEXT8_CNTL
9893 #define VM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT                                                               0x0
9894 #define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                             0x1
9895 #define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                        0x3
9896 #define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                       0x7
9897 #define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT                                                            0x8
9898 #define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x9
9899 #define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xa
9900 #define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0xb
9901 #define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0xc
9902 #define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0xd
9903 #define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0xe
9904 #define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xf
9905 #define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x10
9906 #define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0x11
9907 #define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0x12
9908 #define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x13
9909 #define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x14
9910 #define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x15
9911 #define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x16
9912 #define VM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x17
9913 #define VM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x18
9914 #define VM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK                                                                 0x00000001L
9915 #define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK                                                               0x00000006L
9916 #define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                          0x00000078L
9917 #define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                         0x00000080L
9918 #define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK                                                              0x00000100L
9919 #define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00000200L
9920 #define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00000400L
9921 #define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00000800L
9922 #define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00001000L
9923 #define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00002000L
9924 #define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00004000L
9925 #define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00008000L
9926 #define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00010000L
9927 #define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00020000L
9928 #define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00040000L
9929 #define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00080000L
9930 #define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00100000L
9931 #define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00200000L
9932 #define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00400000L
9933 #define VM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00800000L
9934 #define VM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x01000000L
9935 //VM_CONTEXT9_CNTL
9936 #define VM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT                                                               0x0
9937 #define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                             0x1
9938 #define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                        0x3
9939 #define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                       0x7
9940 #define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT                                                            0x8
9941 #define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x9
9942 #define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xa
9943 #define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0xb
9944 #define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0xc
9945 #define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0xd
9946 #define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0xe
9947 #define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xf
9948 #define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x10
9949 #define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0x11
9950 #define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0x12
9951 #define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x13
9952 #define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x14
9953 #define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x15
9954 #define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x16
9955 #define VM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x17
9956 #define VM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x18
9957 #define VM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK                                                                 0x00000001L
9958 #define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK                                                               0x00000006L
9959 #define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                          0x00000078L
9960 #define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                         0x00000080L
9961 #define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK                                                              0x00000100L
9962 #define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00000200L
9963 #define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00000400L
9964 #define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00000800L
9965 #define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00001000L
9966 #define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00002000L
9967 #define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00004000L
9968 #define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00008000L
9969 #define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00010000L
9970 #define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00020000L
9971 #define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00040000L
9972 #define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00080000L
9973 #define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00100000L
9974 #define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00200000L
9975 #define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00400000L
9976 #define VM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00800000L
9977 #define VM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x01000000L
9978 //VM_CONTEXT10_CNTL
9979 #define VM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT                                                              0x0
9980 #define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                            0x1
9981 #define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                       0x3
9982 #define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                      0x7
9983 #define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT                                                           0x8
9984 #define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x9
9985 #define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xa
9986 #define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                0xb
9987 #define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                  0xc
9988 #define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xd
9989 #define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xe
9990 #define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xf
9991 #define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x10
9992 #define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x11
9993 #define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x12
9994 #define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x13
9995 #define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x14
9996 #define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x15
9997 #define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x16
9998 #define VM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x17
9999 #define VM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x18
10000 #define VM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK                                                                0x00000001L
10001 #define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK                                                              0x00000006L
10002 #define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                         0x00000078L
10003 #define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                        0x00000080L
10004 #define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK                                                             0x00000100L
10005 #define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00000200L
10006 #define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00000400L
10007 #define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                  0x00000800L
10008 #define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                    0x00001000L
10009 #define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00002000L
10010 #define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00004000L
10011 #define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00008000L
10012 #define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00010000L
10013 #define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00020000L
10014 #define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00040000L
10015 #define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00080000L
10016 #define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00100000L
10017 #define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00200000L
10018 #define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00400000L
10019 #define VM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00800000L
10020 #define VM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x01000000L
10021 //VM_CONTEXT11_CNTL
10022 #define VM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT                                                              0x0
10023 #define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                            0x1
10024 #define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                       0x3
10025 #define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                      0x7
10026 #define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT                                                           0x8
10027 #define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x9
10028 #define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xa
10029 #define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                0xb
10030 #define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                  0xc
10031 #define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xd
10032 #define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xe
10033 #define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xf
10034 #define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x10
10035 #define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x11
10036 #define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x12
10037 #define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x13
10038 #define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x14
10039 #define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x15
10040 #define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x16
10041 #define VM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x17
10042 #define VM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x18
10043 #define VM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK                                                                0x00000001L
10044 #define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK                                                              0x00000006L
10045 #define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                         0x00000078L
10046 #define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                        0x00000080L
10047 #define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK                                                             0x00000100L
10048 #define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00000200L
10049 #define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00000400L
10050 #define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                  0x00000800L
10051 #define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                    0x00001000L
10052 #define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00002000L
10053 #define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00004000L
10054 #define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00008000L
10055 #define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00010000L
10056 #define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00020000L
10057 #define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00040000L
10058 #define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00080000L
10059 #define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00100000L
10060 #define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00200000L
10061 #define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00400000L
10062 #define VM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00800000L
10063 #define VM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x01000000L
10064 //VM_CONTEXT12_CNTL
10065 #define VM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT                                                              0x0
10066 #define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                            0x1
10067 #define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                       0x3
10068 #define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                      0x7
10069 #define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT                                                           0x8
10070 #define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x9
10071 #define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xa
10072 #define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                0xb
10073 #define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                  0xc
10074 #define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xd
10075 #define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xe
10076 #define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xf
10077 #define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x10
10078 #define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x11
10079 #define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x12
10080 #define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x13
10081 #define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x14
10082 #define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x15
10083 #define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x16
10084 #define VM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x17
10085 #define VM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x18
10086 #define VM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK                                                                0x00000001L
10087 #define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK                                                              0x00000006L
10088 #define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                         0x00000078L
10089 #define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                        0x00000080L
10090 #define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK                                                             0x00000100L
10091 #define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00000200L
10092 #define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00000400L
10093 #define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                  0x00000800L
10094 #define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                    0x00001000L
10095 #define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00002000L
10096 #define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00004000L
10097 #define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00008000L
10098 #define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00010000L
10099 #define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00020000L
10100 #define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00040000L
10101 #define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00080000L
10102 #define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00100000L
10103 #define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00200000L
10104 #define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00400000L
10105 #define VM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00800000L
10106 #define VM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x01000000L
10107 //VM_CONTEXT13_CNTL
10108 #define VM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT                                                              0x0
10109 #define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                            0x1
10110 #define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                       0x3
10111 #define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                      0x7
10112 #define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT                                                           0x8
10113 #define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x9
10114 #define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xa
10115 #define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                0xb
10116 #define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                  0xc
10117 #define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xd
10118 #define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xe
10119 #define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xf
10120 #define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x10
10121 #define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x11
10122 #define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x12
10123 #define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x13
10124 #define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x14
10125 #define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x15
10126 #define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x16
10127 #define VM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x17
10128 #define VM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x18
10129 #define VM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK                                                                0x00000001L
10130 #define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK                                                              0x00000006L
10131 #define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                         0x00000078L
10132 #define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                        0x00000080L
10133 #define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK                                                             0x00000100L
10134 #define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00000200L
10135 #define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00000400L
10136 #define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                  0x00000800L
10137 #define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                    0x00001000L
10138 #define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00002000L
10139 #define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00004000L
10140 #define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00008000L
10141 #define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00010000L
10142 #define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00020000L
10143 #define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00040000L
10144 #define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00080000L
10145 #define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00100000L
10146 #define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00200000L
10147 #define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00400000L
10148 #define VM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00800000L
10149 #define VM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x01000000L
10150 //VM_CONTEXT14_CNTL
10151 #define VM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT                                                              0x0
10152 #define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                            0x1
10153 #define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                       0x3
10154 #define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                      0x7
10155 #define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT                                                           0x8
10156 #define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x9
10157 #define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xa
10158 #define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                0xb
10159 #define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                  0xc
10160 #define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xd
10161 #define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xe
10162 #define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xf
10163 #define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x10
10164 #define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x11
10165 #define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x12
10166 #define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x13
10167 #define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x14
10168 #define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x15
10169 #define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x16
10170 #define VM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x17
10171 #define VM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x18
10172 #define VM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK                                                                0x00000001L
10173 #define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK                                                              0x00000006L
10174 #define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                         0x00000078L
10175 #define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                        0x00000080L
10176 #define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK                                                             0x00000100L
10177 #define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00000200L
10178 #define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00000400L
10179 #define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                  0x00000800L
10180 #define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                    0x00001000L
10181 #define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00002000L
10182 #define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00004000L
10183 #define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00008000L
10184 #define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00010000L
10185 #define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00020000L
10186 #define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00040000L
10187 #define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00080000L
10188 #define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00100000L
10189 #define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00200000L
10190 #define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00400000L
10191 #define VM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00800000L
10192 #define VM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x01000000L
10193 //VM_CONTEXT15_CNTL
10194 #define VM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT                                                              0x0
10195 #define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                            0x1
10196 #define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                       0x3
10197 #define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                      0x7
10198 #define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT                                                           0x8
10199 #define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x9
10200 #define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xa
10201 #define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                0xb
10202 #define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                  0xc
10203 #define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xd
10204 #define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xe
10205 #define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xf
10206 #define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x10
10207 #define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x11
10208 #define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x12
10209 #define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x13
10210 #define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x14
10211 #define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x15
10212 #define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x16
10213 #define VM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x17
10214 #define VM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x18
10215 #define VM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK                                                                0x00000001L
10216 #define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK                                                              0x00000006L
10217 #define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                         0x00000078L
10218 #define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                        0x00000080L
10219 #define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK                                                             0x00000100L
10220 #define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00000200L
10221 #define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00000400L
10222 #define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                  0x00000800L
10223 #define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                    0x00001000L
10224 #define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00002000L
10225 #define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00004000L
10226 #define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00008000L
10227 #define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00010000L
10228 #define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00020000L
10229 #define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00040000L
10230 #define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00080000L
10231 #define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00100000L
10232 #define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00200000L
10233 #define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00400000L
10234 #define VM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00800000L
10235 #define VM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x01000000L
10236 //VM_CONTEXTS_DISABLE
10237 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT                                                         0x0
10238 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT                                                         0x1
10239 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT                                                         0x2
10240 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT                                                         0x3
10241 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT                                                         0x4
10242 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT                                                         0x5
10243 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT                                                         0x6
10244 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT                                                         0x7
10245 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT                                                         0x8
10246 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT                                                         0x9
10247 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT                                                        0xa
10248 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT                                                        0xb
10249 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT                                                        0xc
10250 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT                                                        0xd
10251 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT                                                        0xe
10252 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT                                                        0xf
10253 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK                                                           0x00000001L
10254 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK                                                           0x00000002L
10255 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK                                                           0x00000004L
10256 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK                                                           0x00000008L
10257 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK                                                           0x00000010L
10258 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK                                                           0x00000020L
10259 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK                                                           0x00000040L
10260 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK                                                           0x00000080L
10261 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK                                                           0x00000100L
10262 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK                                                           0x00000200L
10263 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK                                                          0x00000400L
10264 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK                                                          0x00000800L
10265 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK                                                          0x00001000L
10266 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK                                                          0x00002000L
10267 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK                                                          0x00004000L
10268 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK                                                          0x00008000L
10269 //VM_INVALIDATE_ENG0_SEM
10270 #define VM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT                                                              0x0
10271 #define VM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK                                                                0x00000001L
10272 //VM_INVALIDATE_ENG1_SEM
10273 #define VM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT                                                              0x0
10274 #define VM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK                                                                0x00000001L
10275 //VM_INVALIDATE_ENG2_SEM
10276 #define VM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT                                                              0x0
10277 #define VM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK                                                                0x00000001L
10278 //VM_INVALIDATE_ENG3_SEM
10279 #define VM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT                                                              0x0
10280 #define VM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK                                                                0x00000001L
10281 //VM_INVALIDATE_ENG4_SEM
10282 #define VM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT                                                              0x0
10283 #define VM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK                                                                0x00000001L
10284 //VM_INVALIDATE_ENG5_SEM
10285 #define VM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT                                                              0x0
10286 #define VM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK                                                                0x00000001L
10287 //VM_INVALIDATE_ENG6_SEM
10288 #define VM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT                                                              0x0
10289 #define VM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK                                                                0x00000001L
10290 //VM_INVALIDATE_ENG7_SEM
10291 #define VM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT                                                              0x0
10292 #define VM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK                                                                0x00000001L
10293 //VM_INVALIDATE_ENG8_SEM
10294 #define VM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT                                                              0x0
10295 #define VM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK                                                                0x00000001L
10296 //VM_INVALIDATE_ENG9_SEM
10297 #define VM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT                                                              0x0
10298 #define VM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK                                                                0x00000001L
10299 //VM_INVALIDATE_ENG10_SEM
10300 #define VM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT                                                             0x0
10301 #define VM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK                                                               0x00000001L
10302 //VM_INVALIDATE_ENG11_SEM
10303 #define VM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT                                                             0x0
10304 #define VM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK                                                               0x00000001L
10305 //VM_INVALIDATE_ENG12_SEM
10306 #define VM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT                                                             0x0
10307 #define VM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK                                                               0x00000001L
10308 //VM_INVALIDATE_ENG13_SEM
10309 #define VM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT                                                             0x0
10310 #define VM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK                                                               0x00000001L
10311 //VM_INVALIDATE_ENG14_SEM
10312 #define VM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT                                                             0x0
10313 #define VM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK                                                               0x00000001L
10314 //VM_INVALIDATE_ENG15_SEM
10315 #define VM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT                                                             0x0
10316 #define VM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK                                                               0x00000001L
10317 //VM_INVALIDATE_ENG16_SEM
10318 #define VM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT                                                             0x0
10319 #define VM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK                                                               0x00000001L
10320 //VM_INVALIDATE_ENG17_SEM
10321 #define VM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT                                                             0x0
10322 #define VM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK                                                               0x00000001L
10323 //VM_INVALIDATE_ENG0_REQ
10324 #define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                                0x0
10325 #define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT                                                             0x10
10326 #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT                                                     0x12
10327 #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT                                                     0x13
10328 #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT                                                     0x14
10329 #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT                                                     0x15
10330 #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT                                                     0x16
10331 #define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                     0x17
10332 #define VM_INVALIDATE_ENG0_REQ__LOG_REQUEST__SHIFT                                                            0x18
10333 #define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                  0x0000FFFFL
10334 #define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK                                                               0x00030000L
10335 #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK                                                       0x00040000L
10336 #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK                                                       0x00080000L
10337 #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK                                                       0x00100000L
10338 #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK                                                       0x00200000L
10339 #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK                                                       0x00400000L
10340 #define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                       0x00800000L
10341 #define VM_INVALIDATE_ENG0_REQ__LOG_REQUEST_MASK                                                              0x01000000L
10342 //VM_INVALIDATE_ENG1_REQ
10343 #define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                                0x0
10344 #define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT                                                             0x10
10345 #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT                                                     0x12
10346 #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT                                                     0x13
10347 #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT                                                     0x14
10348 #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT                                                     0x15
10349 #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT                                                     0x16
10350 #define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                     0x17
10351 #define VM_INVALIDATE_ENG1_REQ__LOG_REQUEST__SHIFT                                                            0x18
10352 #define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                  0x0000FFFFL
10353 #define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK                                                               0x00030000L
10354 #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK                                                       0x00040000L
10355 #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK                                                       0x00080000L
10356 #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK                                                       0x00100000L
10357 #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK                                                       0x00200000L
10358 #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK                                                       0x00400000L
10359 #define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                       0x00800000L
10360 #define VM_INVALIDATE_ENG1_REQ__LOG_REQUEST_MASK                                                              0x01000000L
10361 //VM_INVALIDATE_ENG2_REQ
10362 #define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                                0x0
10363 #define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT                                                             0x10
10364 #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT                                                     0x12
10365 #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT                                                     0x13
10366 #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT                                                     0x14
10367 #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT                                                     0x15
10368 #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT                                                     0x16
10369 #define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                     0x17
10370 #define VM_INVALIDATE_ENG2_REQ__LOG_REQUEST__SHIFT                                                            0x18
10371 #define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                  0x0000FFFFL
10372 #define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK                                                               0x00030000L
10373 #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK                                                       0x00040000L
10374 #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK                                                       0x00080000L
10375 #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK                                                       0x00100000L
10376 #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK                                                       0x00200000L
10377 #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK                                                       0x00400000L
10378 #define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                       0x00800000L
10379 #define VM_INVALIDATE_ENG2_REQ__LOG_REQUEST_MASK                                                              0x01000000L
10380 //VM_INVALIDATE_ENG3_REQ
10381 #define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                                0x0
10382 #define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT                                                             0x10
10383 #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT                                                     0x12
10384 #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT                                                     0x13
10385 #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT                                                     0x14
10386 #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT                                                     0x15
10387 #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT                                                     0x16
10388 #define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                     0x17
10389 #define VM_INVALIDATE_ENG3_REQ__LOG_REQUEST__SHIFT                                                            0x18
10390 #define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                  0x0000FFFFL
10391 #define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK                                                               0x00030000L
10392 #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK                                                       0x00040000L
10393 #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK                                                       0x00080000L
10394 #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK                                                       0x00100000L
10395 #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK                                                       0x00200000L
10396 #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK                                                       0x00400000L
10397 #define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                       0x00800000L
10398 #define VM_INVALIDATE_ENG3_REQ__LOG_REQUEST_MASK                                                              0x01000000L
10399 //VM_INVALIDATE_ENG4_REQ
10400 #define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                                0x0
10401 #define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT                                                             0x10
10402 #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT                                                     0x12
10403 #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT                                                     0x13
10404 #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT                                                     0x14
10405 #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT                                                     0x15
10406 #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT                                                     0x16
10407 #define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                     0x17
10408 #define VM_INVALIDATE_ENG4_REQ__LOG_REQUEST__SHIFT                                                            0x18
10409 #define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                  0x0000FFFFL
10410 #define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK                                                               0x00030000L
10411 #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK                                                       0x00040000L
10412 #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK                                                       0x00080000L
10413 #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK                                                       0x00100000L
10414 #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK                                                       0x00200000L
10415 #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK                                                       0x00400000L
10416 #define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                       0x00800000L
10417 #define VM_INVALIDATE_ENG4_REQ__LOG_REQUEST_MASK                                                              0x01000000L
10418 //VM_INVALIDATE_ENG5_REQ
10419 #define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                                0x0
10420 #define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT                                                             0x10
10421 #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT                                                     0x12
10422 #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT                                                     0x13
10423 #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT                                                     0x14
10424 #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT                                                     0x15
10425 #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT                                                     0x16
10426 #define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                     0x17
10427 #define VM_INVALIDATE_ENG5_REQ__LOG_REQUEST__SHIFT                                                            0x18
10428 #define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                  0x0000FFFFL
10429 #define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK                                                               0x00030000L
10430 #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK                                                       0x00040000L
10431 #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK                                                       0x00080000L
10432 #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK                                                       0x00100000L
10433 #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK                                                       0x00200000L
10434 #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK                                                       0x00400000L
10435 #define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                       0x00800000L
10436 #define VM_INVALIDATE_ENG5_REQ__LOG_REQUEST_MASK                                                              0x01000000L
10437 //VM_INVALIDATE_ENG6_REQ
10438 #define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                                0x0
10439 #define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT                                                             0x10
10440 #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT                                                     0x12
10441 #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT                                                     0x13
10442 #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT                                                     0x14
10443 #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT                                                     0x15
10444 #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT                                                     0x16
10445 #define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                     0x17
10446 #define VM_INVALIDATE_ENG6_REQ__LOG_REQUEST__SHIFT                                                            0x18
10447 #define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                  0x0000FFFFL
10448 #define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK                                                               0x00030000L
10449 #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK                                                       0x00040000L
10450 #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK                                                       0x00080000L
10451 #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK                                                       0x00100000L
10452 #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK                                                       0x00200000L
10453 #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK                                                       0x00400000L
10454 #define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                       0x00800000L
10455 #define VM_INVALIDATE_ENG6_REQ__LOG_REQUEST_MASK                                                              0x01000000L
10456 //VM_INVALIDATE_ENG7_REQ
10457 #define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                                0x0
10458 #define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT                                                             0x10
10459 #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT                                                     0x12
10460 #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT                                                     0x13
10461 #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT                                                     0x14
10462 #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT                                                     0x15
10463 #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT                                                     0x16
10464 #define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                     0x17
10465 #define VM_INVALIDATE_ENG7_REQ__LOG_REQUEST__SHIFT                                                            0x18
10466 #define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                  0x0000FFFFL
10467 #define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK                                                               0x00030000L
10468 #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK                                                       0x00040000L
10469 #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK                                                       0x00080000L
10470 #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK                                                       0x00100000L
10471 #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK                                                       0x00200000L
10472 #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK                                                       0x00400000L
10473 #define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                       0x00800000L
10474 #define VM_INVALIDATE_ENG7_REQ__LOG_REQUEST_MASK                                                              0x01000000L
10475 //VM_INVALIDATE_ENG8_REQ
10476 #define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                                0x0
10477 #define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT                                                             0x10
10478 #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT                                                     0x12
10479 #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT                                                     0x13
10480 #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT                                                     0x14
10481 #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT                                                     0x15
10482 #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT                                                     0x16
10483 #define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                     0x17
10484 #define VM_INVALIDATE_ENG8_REQ__LOG_REQUEST__SHIFT                                                            0x18
10485 #define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                  0x0000FFFFL
10486 #define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK                                                               0x00030000L
10487 #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK                                                       0x00040000L
10488 #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK                                                       0x00080000L
10489 #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK                                                       0x00100000L
10490 #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK                                                       0x00200000L
10491 #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK                                                       0x00400000L
10492 #define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                       0x00800000L
10493 #define VM_INVALIDATE_ENG8_REQ__LOG_REQUEST_MASK                                                              0x01000000L
10494 //VM_INVALIDATE_ENG9_REQ
10495 #define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                                0x0
10496 #define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT                                                             0x10
10497 #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT                                                     0x12
10498 #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT                                                     0x13
10499 #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT                                                     0x14
10500 #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT                                                     0x15
10501 #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT                                                     0x16
10502 #define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                     0x17
10503 #define VM_INVALIDATE_ENG9_REQ__LOG_REQUEST__SHIFT                                                            0x18
10504 #define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                  0x0000FFFFL
10505 #define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK                                                               0x00030000L
10506 #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK                                                       0x00040000L
10507 #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK                                                       0x00080000L
10508 #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK                                                       0x00100000L
10509 #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK                                                       0x00200000L
10510 #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK                                                       0x00400000L
10511 #define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                       0x00800000L
10512 #define VM_INVALIDATE_ENG9_REQ__LOG_REQUEST_MASK                                                              0x01000000L
10513 //VM_INVALIDATE_ENG10_REQ
10514 #define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                               0x0
10515 #define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT                                                            0x10
10516 #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT                                                    0x12
10517 #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT                                                    0x13
10518 #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT                                                    0x14
10519 #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT                                                    0x15
10520 #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT                                                    0x16
10521 #define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                    0x17
10522 #define VM_INVALIDATE_ENG10_REQ__LOG_REQUEST__SHIFT                                                           0x18
10523 #define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                 0x0000FFFFL
10524 #define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK                                                              0x00030000L
10525 #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK                                                      0x00040000L
10526 #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK                                                      0x00080000L
10527 #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK                                                      0x00100000L
10528 #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK                                                      0x00200000L
10529 #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK                                                      0x00400000L
10530 #define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                      0x00800000L
10531 #define VM_INVALIDATE_ENG10_REQ__LOG_REQUEST_MASK                                                             0x01000000L
10532 //VM_INVALIDATE_ENG11_REQ
10533 #define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                               0x0
10534 #define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT                                                            0x10
10535 #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT                                                    0x12
10536 #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT                                                    0x13
10537 #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT                                                    0x14
10538 #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT                                                    0x15
10539 #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT                                                    0x16
10540 #define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                    0x17
10541 #define VM_INVALIDATE_ENG11_REQ__LOG_REQUEST__SHIFT                                                           0x18
10542 #define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                 0x0000FFFFL
10543 #define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK                                                              0x00030000L
10544 #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK                                                      0x00040000L
10545 #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK                                                      0x00080000L
10546 #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK                                                      0x00100000L
10547 #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK                                                      0x00200000L
10548 #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK                                                      0x00400000L
10549 #define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                      0x00800000L
10550 #define VM_INVALIDATE_ENG11_REQ__LOG_REQUEST_MASK                                                             0x01000000L
10551 //VM_INVALIDATE_ENG12_REQ
10552 #define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                               0x0
10553 #define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT                                                            0x10
10554 #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT                                                    0x12
10555 #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT                                                    0x13
10556 #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT                                                    0x14
10557 #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT                                                    0x15
10558 #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT                                                    0x16
10559 #define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                    0x17
10560 #define VM_INVALIDATE_ENG12_REQ__LOG_REQUEST__SHIFT                                                           0x18
10561 #define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                 0x0000FFFFL
10562 #define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK                                                              0x00030000L
10563 #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK                                                      0x00040000L
10564 #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK                                                      0x00080000L
10565 #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK                                                      0x00100000L
10566 #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK                                                      0x00200000L
10567 #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK                                                      0x00400000L
10568 #define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                      0x00800000L
10569 #define VM_INVALIDATE_ENG12_REQ__LOG_REQUEST_MASK                                                             0x01000000L
10570 //VM_INVALIDATE_ENG13_REQ
10571 #define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                               0x0
10572 #define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT                                                            0x10
10573 #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT                                                    0x12
10574 #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT                                                    0x13
10575 #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT                                                    0x14
10576 #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT                                                    0x15
10577 #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT                                                    0x16
10578 #define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                    0x17
10579 #define VM_INVALIDATE_ENG13_REQ__LOG_REQUEST__SHIFT                                                           0x18
10580 #define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                 0x0000FFFFL
10581 #define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK                                                              0x00030000L
10582 #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK                                                      0x00040000L
10583 #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK                                                      0x00080000L
10584 #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK                                                      0x00100000L
10585 #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK                                                      0x00200000L
10586 #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK                                                      0x00400000L
10587 #define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                      0x00800000L
10588 #define VM_INVALIDATE_ENG13_REQ__LOG_REQUEST_MASK                                                             0x01000000L
10589 //VM_INVALIDATE_ENG14_REQ
10590 #define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                               0x0
10591 #define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT                                                            0x10
10592 #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT                                                    0x12
10593 #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT                                                    0x13
10594 #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT                                                    0x14
10595 #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT                                                    0x15
10596 #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT                                                    0x16
10597 #define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                    0x17
10598 #define VM_INVALIDATE_ENG14_REQ__LOG_REQUEST__SHIFT                                                           0x18
10599 #define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                 0x0000FFFFL
10600 #define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK                                                              0x00030000L
10601 #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK                                                      0x00040000L
10602 #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK                                                      0x00080000L
10603 #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK                                                      0x00100000L
10604 #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK                                                      0x00200000L
10605 #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK                                                      0x00400000L
10606 #define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                      0x00800000L
10607 #define VM_INVALIDATE_ENG14_REQ__LOG_REQUEST_MASK                                                             0x01000000L
10608 //VM_INVALIDATE_ENG15_REQ
10609 #define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                               0x0
10610 #define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT                                                            0x10
10611 #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT                                                    0x12
10612 #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT                                                    0x13
10613 #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT                                                    0x14
10614 #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT                                                    0x15
10615 #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT                                                    0x16
10616 #define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                    0x17
10617 #define VM_INVALIDATE_ENG15_REQ__LOG_REQUEST__SHIFT                                                           0x18
10618 #define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                 0x0000FFFFL
10619 #define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK                                                              0x00030000L
10620 #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK                                                      0x00040000L
10621 #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK                                                      0x00080000L
10622 #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK                                                      0x00100000L
10623 #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK                                                      0x00200000L
10624 #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK                                                      0x00400000L
10625 #define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                      0x00800000L
10626 #define VM_INVALIDATE_ENG15_REQ__LOG_REQUEST_MASK                                                             0x01000000L
10627 //VM_INVALIDATE_ENG16_REQ
10628 #define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                               0x0
10629 #define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT                                                            0x10
10630 #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT                                                    0x12
10631 #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT                                                    0x13
10632 #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT                                                    0x14
10633 #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT                                                    0x15
10634 #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT                                                    0x16
10635 #define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                    0x17
10636 #define VM_INVALIDATE_ENG16_REQ__LOG_REQUEST__SHIFT                                                           0x18
10637 #define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                 0x0000FFFFL
10638 #define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK                                                              0x00030000L
10639 #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK                                                      0x00040000L
10640 #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK                                                      0x00080000L
10641 #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK                                                      0x00100000L
10642 #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK                                                      0x00200000L
10643 #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK                                                      0x00400000L
10644 #define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                      0x00800000L
10645 #define VM_INVALIDATE_ENG16_REQ__LOG_REQUEST_MASK                                                             0x01000000L
10646 //VM_INVALIDATE_ENG17_REQ
10647 #define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                               0x0
10648 #define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT                                                            0x10
10649 #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT                                                    0x12
10650 #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT                                                    0x13
10651 #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT                                                    0x14
10652 #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT                                                    0x15
10653 #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT                                                    0x16
10654 #define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                    0x17
10655 #define VM_INVALIDATE_ENG17_REQ__LOG_REQUEST__SHIFT                                                           0x18
10656 #define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                 0x0000FFFFL
10657 #define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK                                                              0x00030000L
10658 #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK                                                      0x00040000L
10659 #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK                                                      0x00080000L
10660 #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK                                                      0x00100000L
10661 #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK                                                      0x00200000L
10662 #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK                                                      0x00400000L
10663 #define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                      0x00800000L
10664 #define VM_INVALIDATE_ENG17_REQ__LOG_REQUEST_MASK                                                             0x01000000L
10665 //VM_INVALIDATE_ENG0_ACK
10666 #define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                                0x0
10667 #define VM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT                                                              0x10
10668 #define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                  0x0000FFFFL
10669 #define VM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK                                                                0x00010000L
10670 //VM_INVALIDATE_ENG1_ACK
10671 #define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                                0x0
10672 #define VM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT                                                              0x10
10673 #define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                  0x0000FFFFL
10674 #define VM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK                                                                0x00010000L
10675 //VM_INVALIDATE_ENG2_ACK
10676 #define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                                0x0
10677 #define VM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT                                                              0x10
10678 #define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                  0x0000FFFFL
10679 #define VM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK                                                                0x00010000L
10680 //VM_INVALIDATE_ENG3_ACK
10681 #define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                                0x0
10682 #define VM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT                                                              0x10
10683 #define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                  0x0000FFFFL
10684 #define VM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK                                                                0x00010000L
10685 //VM_INVALIDATE_ENG4_ACK
10686 #define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                                0x0
10687 #define VM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT                                                              0x10
10688 #define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                  0x0000FFFFL
10689 #define VM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK                                                                0x00010000L
10690 //VM_INVALIDATE_ENG5_ACK
10691 #define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                                0x0
10692 #define VM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT                                                              0x10
10693 #define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                  0x0000FFFFL
10694 #define VM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK                                                                0x00010000L
10695 //VM_INVALIDATE_ENG6_ACK
10696 #define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                                0x0
10697 #define VM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT                                                              0x10
10698 #define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                  0x0000FFFFL
10699 #define VM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK                                                                0x00010000L
10700 //VM_INVALIDATE_ENG7_ACK
10701 #define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                                0x0
10702 #define VM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT                                                              0x10
10703 #define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                  0x0000FFFFL
10704 #define VM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK                                                                0x00010000L
10705 //VM_INVALIDATE_ENG8_ACK
10706 #define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                                0x0
10707 #define VM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT                                                              0x10
10708 #define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                  0x0000FFFFL
10709 #define VM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK                                                                0x00010000L
10710 //VM_INVALIDATE_ENG9_ACK
10711 #define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                                0x0
10712 #define VM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT                                                              0x10
10713 #define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                  0x0000FFFFL
10714 #define VM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK                                                                0x00010000L
10715 //VM_INVALIDATE_ENG10_ACK
10716 #define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                               0x0
10717 #define VM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT                                                             0x10
10718 #define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                 0x0000FFFFL
10719 #define VM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK                                                               0x00010000L
10720 //VM_INVALIDATE_ENG11_ACK
10721 #define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                               0x0
10722 #define VM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT                                                             0x10
10723 #define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                 0x0000FFFFL
10724 #define VM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK                                                               0x00010000L
10725 //VM_INVALIDATE_ENG12_ACK
10726 #define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                               0x0
10727 #define VM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT                                                             0x10
10728 #define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                 0x0000FFFFL
10729 #define VM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK                                                               0x00010000L
10730 //VM_INVALIDATE_ENG13_ACK
10731 #define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                               0x0
10732 #define VM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT                                                             0x10
10733 #define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                 0x0000FFFFL
10734 #define VM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK                                                               0x00010000L
10735 //VM_INVALIDATE_ENG14_ACK
10736 #define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                               0x0
10737 #define VM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT                                                             0x10
10738 #define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                 0x0000FFFFL
10739 #define VM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK                                                               0x00010000L
10740 //VM_INVALIDATE_ENG15_ACK
10741 #define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                               0x0
10742 #define VM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT                                                             0x10
10743 #define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                 0x0000FFFFL
10744 #define VM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK                                                               0x00010000L
10745 //VM_INVALIDATE_ENG16_ACK
10746 #define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                               0x0
10747 #define VM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT                                                             0x10
10748 #define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                 0x0000FFFFL
10749 #define VM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK                                                               0x00010000L
10750 //VM_INVALIDATE_ENG17_ACK
10751 #define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                               0x0
10752 #define VM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT                                                             0x10
10753 #define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                 0x0000FFFFL
10754 #define VM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK                                                               0x00010000L
10755 //VM_INVALIDATE_ENG0_ADDR_RANGE_LO32
10756 #define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT                                                      0x0
10757 #define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                  0x1
10758 #define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK                                                        0x00000001L
10759 #define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                    0xFFFFFFFEL
10760 //VM_INVALIDATE_ENG0_ADDR_RANGE_HI32
10761 #define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                   0x0
10762 #define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                     0x0000001FL
10763 //VM_INVALIDATE_ENG1_ADDR_RANGE_LO32
10764 #define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT                                                      0x0
10765 #define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                  0x1
10766 #define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK                                                        0x00000001L
10767 #define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                    0xFFFFFFFEL
10768 //VM_INVALIDATE_ENG1_ADDR_RANGE_HI32
10769 #define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                   0x0
10770 #define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                     0x0000001FL
10771 //VM_INVALIDATE_ENG2_ADDR_RANGE_LO32
10772 #define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT                                                      0x0
10773 #define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                  0x1
10774 #define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK                                                        0x00000001L
10775 #define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                    0xFFFFFFFEL
10776 //VM_INVALIDATE_ENG2_ADDR_RANGE_HI32
10777 #define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                   0x0
10778 #define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                     0x0000001FL
10779 //VM_INVALIDATE_ENG3_ADDR_RANGE_LO32
10780 #define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT                                                      0x0
10781 #define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                  0x1
10782 #define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK                                                        0x00000001L
10783 #define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                    0xFFFFFFFEL
10784 //VM_INVALIDATE_ENG3_ADDR_RANGE_HI32
10785 #define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                   0x0
10786 #define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                     0x0000001FL
10787 //VM_INVALIDATE_ENG4_ADDR_RANGE_LO32
10788 #define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT                                                      0x0
10789 #define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                  0x1
10790 #define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK                                                        0x00000001L
10791 #define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                    0xFFFFFFFEL
10792 //VM_INVALIDATE_ENG4_ADDR_RANGE_HI32
10793 #define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                   0x0
10794 #define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                     0x0000001FL
10795 //VM_INVALIDATE_ENG5_ADDR_RANGE_LO32
10796 #define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT                                                      0x0
10797 #define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                  0x1
10798 #define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK                                                        0x00000001L
10799 #define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                    0xFFFFFFFEL
10800 //VM_INVALIDATE_ENG5_ADDR_RANGE_HI32
10801 #define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                   0x0
10802 #define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                     0x0000001FL
10803 //VM_INVALIDATE_ENG6_ADDR_RANGE_LO32
10804 #define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT                                                      0x0
10805 #define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                  0x1
10806 #define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK                                                        0x00000001L
10807 #define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                    0xFFFFFFFEL
10808 //VM_INVALIDATE_ENG6_ADDR_RANGE_HI32
10809 #define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                   0x0
10810 #define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                     0x0000001FL
10811 //VM_INVALIDATE_ENG7_ADDR_RANGE_LO32
10812 #define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT                                                      0x0
10813 #define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                  0x1
10814 #define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK                                                        0x00000001L
10815 #define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                    0xFFFFFFFEL
10816 //VM_INVALIDATE_ENG7_ADDR_RANGE_HI32
10817 #define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                   0x0
10818 #define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                     0x0000001FL
10819 //VM_INVALIDATE_ENG8_ADDR_RANGE_LO32
10820 #define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT                                                      0x0
10821 #define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                  0x1
10822 #define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK                                                        0x00000001L
10823 #define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                    0xFFFFFFFEL
10824 //VM_INVALIDATE_ENG8_ADDR_RANGE_HI32
10825 #define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                   0x0
10826 #define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                     0x0000001FL
10827 //VM_INVALIDATE_ENG9_ADDR_RANGE_LO32
10828 #define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT                                                      0x0
10829 #define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                  0x1
10830 #define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK                                                        0x00000001L
10831 #define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                    0xFFFFFFFEL
10832 //VM_INVALIDATE_ENG9_ADDR_RANGE_HI32
10833 #define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                   0x0
10834 #define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                     0x0000001FL
10835 //VM_INVALIDATE_ENG10_ADDR_RANGE_LO32
10836 #define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT                                                     0x0
10837 #define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                 0x1
10838 #define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK                                                       0x00000001L
10839 #define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                   0xFFFFFFFEL
10840 //VM_INVALIDATE_ENG10_ADDR_RANGE_HI32
10841 #define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                  0x0
10842 #define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                    0x0000001FL
10843 //VM_INVALIDATE_ENG11_ADDR_RANGE_LO32
10844 #define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT                                                     0x0
10845 #define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                 0x1
10846 #define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK                                                       0x00000001L
10847 #define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                   0xFFFFFFFEL
10848 //VM_INVALIDATE_ENG11_ADDR_RANGE_HI32
10849 #define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                  0x0
10850 #define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                    0x0000001FL
10851 //VM_INVALIDATE_ENG12_ADDR_RANGE_LO32
10852 #define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT                                                     0x0
10853 #define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                 0x1
10854 #define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK                                                       0x00000001L
10855 #define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                   0xFFFFFFFEL
10856 //VM_INVALIDATE_ENG12_ADDR_RANGE_HI32
10857 #define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                  0x0
10858 #define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                    0x0000001FL
10859 //VM_INVALIDATE_ENG13_ADDR_RANGE_LO32
10860 #define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT                                                     0x0
10861 #define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                 0x1
10862 #define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK                                                       0x00000001L
10863 #define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                   0xFFFFFFFEL
10864 //VM_INVALIDATE_ENG13_ADDR_RANGE_HI32
10865 #define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                  0x0
10866 #define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                    0x0000001FL
10867 //VM_INVALIDATE_ENG14_ADDR_RANGE_LO32
10868 #define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT                                                     0x0
10869 #define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                 0x1
10870 #define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK                                                       0x00000001L
10871 #define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                   0xFFFFFFFEL
10872 //VM_INVALIDATE_ENG14_ADDR_RANGE_HI32
10873 #define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                  0x0
10874 #define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                    0x0000001FL
10875 //VM_INVALIDATE_ENG15_ADDR_RANGE_LO32
10876 #define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT                                                     0x0
10877 #define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                 0x1
10878 #define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK                                                       0x00000001L
10879 #define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                   0xFFFFFFFEL
10880 //VM_INVALIDATE_ENG15_ADDR_RANGE_HI32
10881 #define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                  0x0
10882 #define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                    0x0000001FL
10883 //VM_INVALIDATE_ENG16_ADDR_RANGE_LO32
10884 #define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT                                                     0x0
10885 #define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                 0x1
10886 #define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK                                                       0x00000001L
10887 #define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                   0xFFFFFFFEL
10888 //VM_INVALIDATE_ENG16_ADDR_RANGE_HI32
10889 #define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                  0x0
10890 #define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                    0x0000001FL
10891 //VM_INVALIDATE_ENG17_ADDR_RANGE_LO32
10892 #define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT                                                     0x0
10893 #define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                 0x1
10894 #define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK                                                       0x00000001L
10895 #define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                   0xFFFFFFFEL
10896 //VM_INVALIDATE_ENG17_ADDR_RANGE_HI32
10897 #define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                  0x0
10898 #define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                    0x0000001FL
10899 //VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32
10900 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                               0x0
10901 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                 0xFFFFFFFFL
10902 //VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32
10903 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                               0x0
10904 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                 0xFFFFFFFFL
10905 //VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32
10906 #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                               0x0
10907 #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                 0xFFFFFFFFL
10908 //VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32
10909 #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                               0x0
10910 #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                 0xFFFFFFFFL
10911 //VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32
10912 #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                               0x0
10913 #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                 0xFFFFFFFFL
10914 //VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32
10915 #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                               0x0
10916 #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                 0xFFFFFFFFL
10917 //VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32
10918 #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                               0x0
10919 #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                 0xFFFFFFFFL
10920 //VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32
10921 #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                               0x0
10922 #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                 0xFFFFFFFFL
10923 //VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32
10924 #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                               0x0
10925 #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                 0xFFFFFFFFL
10926 //VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32
10927 #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                               0x0
10928 #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                 0xFFFFFFFFL
10929 //VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32
10930 #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                               0x0
10931 #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                 0xFFFFFFFFL
10932 //VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32
10933 #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                               0x0
10934 #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                 0xFFFFFFFFL
10935 //VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32
10936 #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                               0x0
10937 #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                 0xFFFFFFFFL
10938 //VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32
10939 #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                               0x0
10940 #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                 0xFFFFFFFFL
10941 //VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32
10942 #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                               0x0
10943 #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                 0xFFFFFFFFL
10944 //VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32
10945 #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                               0x0
10946 #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                 0xFFFFFFFFL
10947 //VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32
10948 #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                               0x0
10949 #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                 0xFFFFFFFFL
10950 //VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32
10951 #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                               0x0
10952 #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                 0xFFFFFFFFL
10953 //VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32
10954 #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                               0x0
10955 #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                 0xFFFFFFFFL
10956 //VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32
10957 #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                               0x0
10958 #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                 0xFFFFFFFFL
10959 //VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32
10960 #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                              0x0
10961 #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                0xFFFFFFFFL
10962 //VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32
10963 #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                              0x0
10964 #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                0xFFFFFFFFL
10965 //VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32
10966 #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                              0x0
10967 #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                0xFFFFFFFFL
10968 //VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32
10969 #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                              0x0
10970 #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                0xFFFFFFFFL
10971 //VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32
10972 #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                              0x0
10973 #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                0xFFFFFFFFL
10974 //VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32
10975 #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                              0x0
10976 #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                0xFFFFFFFFL
10977 //VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32
10978 #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                              0x0
10979 #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                0xFFFFFFFFL
10980 //VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32
10981 #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                              0x0
10982 #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                0xFFFFFFFFL
10983 //VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32
10984 #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                              0x0
10985 #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                0xFFFFFFFFL
10986 //VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32
10987 #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                              0x0
10988 #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                0xFFFFFFFFL
10989 //VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32
10990 #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                              0x0
10991 #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                0xFFFFFFFFL
10992 //VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32
10993 #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                              0x0
10994 #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                0xFFFFFFFFL
10995 //VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32
10996 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
10997 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
10998 //VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32
10999 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
11000 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
11001 //VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32
11002 #define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
11003 #define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
11004 //VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32
11005 #define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
11006 #define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
11007 //VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32
11008 #define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
11009 #define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
11010 //VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32
11011 #define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
11012 #define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
11013 //VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32
11014 #define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
11015 #define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
11016 //VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32
11017 #define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
11018 #define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
11019 //VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32
11020 #define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
11021 #define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
11022 //VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32
11023 #define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
11024 #define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
11025 //VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32
11026 #define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
11027 #define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
11028 //VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32
11029 #define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
11030 #define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
11031 //VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32
11032 #define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
11033 #define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
11034 //VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32
11035 #define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
11036 #define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
11037 //VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32
11038 #define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
11039 #define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
11040 //VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32
11041 #define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
11042 #define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
11043 //VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32
11044 #define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
11045 #define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
11046 //VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32
11047 #define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
11048 #define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
11049 //VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32
11050 #define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
11051 #define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
11052 //VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32
11053 #define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
11054 #define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
11055 //VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32
11056 #define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                              0x0
11057 #define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                0xFFFFFFFFL
11058 //VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32
11059 #define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                               0x0
11060 #define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                 0x0000000FL
11061 //VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32
11062 #define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                              0x0
11063 #define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                0xFFFFFFFFL
11064 //VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32
11065 #define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                               0x0
11066 #define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                 0x0000000FL
11067 //VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32
11068 #define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                              0x0
11069 #define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                0xFFFFFFFFL
11070 //VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32
11071 #define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                               0x0
11072 #define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                 0x0000000FL
11073 //VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32
11074 #define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                              0x0
11075 #define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                0xFFFFFFFFL
11076 //VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32
11077 #define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                               0x0
11078 #define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                 0x0000000FL
11079 //VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32
11080 #define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                              0x0
11081 #define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                0xFFFFFFFFL
11082 //VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32
11083 #define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                               0x0
11084 #define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                 0x0000000FL
11085 //VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32
11086 #define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                              0x0
11087 #define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                0xFFFFFFFFL
11088 //VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32
11089 #define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                               0x0
11090 #define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                 0x0000000FL
11091 //VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32
11092 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                 0x0
11093 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                   0xFFFFFFFFL
11094 //VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32
11095 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                  0x0
11096 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                    0x0000000FL
11097 //VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32
11098 #define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                 0x0
11099 #define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                   0xFFFFFFFFL
11100 //VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32
11101 #define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                  0x0
11102 #define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                    0x0000000FL
11103 //VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32
11104 #define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                 0x0
11105 #define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                   0xFFFFFFFFL
11106 //VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32
11107 #define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                  0x0
11108 #define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                    0x0000000FL
11109 //VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32
11110 #define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                 0x0
11111 #define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                   0xFFFFFFFFL
11112 //VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32
11113 #define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                  0x0
11114 #define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                    0x0000000FL
11115 //VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32
11116 #define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                 0x0
11117 #define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                   0xFFFFFFFFL
11118 //VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32
11119 #define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                  0x0
11120 #define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                    0x0000000FL
11121 //VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32
11122 #define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                 0x0
11123 #define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                   0xFFFFFFFFL
11124 //VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32
11125 #define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                  0x0
11126 #define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                    0x0000000FL
11127 //VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32
11128 #define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                 0x0
11129 #define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                   0xFFFFFFFFL
11130 //VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32
11131 #define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                  0x0
11132 #define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                    0x0000000FL
11133 //VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32
11134 #define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                 0x0
11135 #define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                   0xFFFFFFFFL
11136 //VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32
11137 #define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                  0x0
11138 #define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                    0x0000000FL
11139 //VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32
11140 #define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                 0x0
11141 #define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                   0xFFFFFFFFL
11142 //VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32
11143 #define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                  0x0
11144 #define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                    0x0000000FL
11145 //VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32
11146 #define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                 0x0
11147 #define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                   0xFFFFFFFFL
11148 //VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32
11149 #define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                  0x0
11150 #define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                    0x0000000FL
11151 //VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32
11152 #define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                0x0
11153 #define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                  0xFFFFFFFFL
11154 //VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32
11155 #define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                 0x0
11156 #define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                   0x0000000FL
11157 //VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32
11158 #define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                0x0
11159 #define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                  0xFFFFFFFFL
11160 //VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32
11161 #define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                 0x0
11162 #define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                   0x0000000FL
11163 //VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32
11164 #define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                0x0
11165 #define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                  0xFFFFFFFFL
11166 //VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32
11167 #define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                 0x0
11168 #define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                   0x0000000FL
11169 //VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32
11170 #define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                0x0
11171 #define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                  0xFFFFFFFFL
11172 //VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32
11173 #define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                 0x0
11174 #define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                   0x0000000FL
11175 //VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32
11176 #define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                0x0
11177 #define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                  0xFFFFFFFFL
11178 //VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32
11179 #define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                 0x0
11180 #define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                   0x0000000FL
11181 //VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32
11182 #define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                0x0
11183 #define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                  0xFFFFFFFFL
11184 //VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32
11185 #define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                 0x0
11186 #define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                   0x0000000FL
11187 
11188 
11189 // addressBlock: xcd0_gc_utcl2_vmsharedpfdec
11190 //MC_VM_NB_MMIOBASE
11191 #define MC_VM_NB_MMIOBASE__MMIOBASE__SHIFT                                                                    0x0
11192 #define MC_VM_NB_MMIOBASE__MMIOBASE_MASK                                                                      0xFFFFFFFFL
11193 //MC_VM_NB_MMIOLIMIT
11194 #define MC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT                                                                  0x0
11195 #define MC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK                                                                    0xFFFFFFFFL
11196 //MC_VM_NB_PCI_CTRL
11197 #define MC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT                                                                  0x17
11198 #define MC_VM_NB_PCI_CTRL__MMIOENABLE_MASK                                                                    0x00800000L
11199 //MC_VM_NB_PCI_ARB
11200 #define MC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT                                                                     0x3
11201 #define MC_VM_NB_PCI_ARB__VGA_HOLE_MASK                                                                       0x00000008L
11202 //MC_VM_NB_TOP_OF_DRAM_SLOT1
11203 #define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT                                                        0x17
11204 #define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK                                                          0xFF800000L
11205 //MC_VM_NB_LOWER_TOP_OF_DRAM2
11206 #define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT                                                            0x0
11207 #define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT                                                        0x17
11208 #define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK                                                              0x00000001L
11209 #define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK                                                          0xFF800000L
11210 //MC_VM_NB_UPPER_TOP_OF_DRAM2
11211 #define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT                                                        0x0
11212 #define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK                                                          0x0000FFFFL
11213 //MC_VM_FB_OFFSET
11214 #define MC_VM_FB_OFFSET__FB_OFFSET__SHIFT                                                                     0x0
11215 #define MC_VM_FB_OFFSET__FB_OFFSET_MASK                                                                       0x00FFFFFFL
11216 //MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB
11217 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT                               0x0
11218 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK                                 0xFFFFFFFFL
11219 //MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB
11220 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT                               0x0
11221 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK                                 0x0000000FL
11222 //MC_VM_STEERING
11223 #define MC_VM_STEERING__DEFAULT_STEERING__SHIFT                                                               0x0
11224 #define MC_VM_STEERING__DEFAULT_STEERING_MASK                                                                 0x00000003L
11225 //MC_SHARED_VIRT_RESET_REQ
11226 #define MC_SHARED_VIRT_RESET_REQ__VF__SHIFT                                                                   0x0
11227 #define MC_SHARED_VIRT_RESET_REQ__PF__SHIFT                                                                   0x1f
11228 #define MC_SHARED_VIRT_RESET_REQ__VF_MASK                                                                     0x0000FFFFL
11229 #define MC_SHARED_VIRT_RESET_REQ__PF_MASK                                                                     0x80000000L
11230 //MC_MEM_POWER_LS
11231 #define MC_MEM_POWER_LS__LS_SETUP__SHIFT                                                                      0x0
11232 #define MC_MEM_POWER_LS__LS_HOLD__SHIFT                                                                       0x6
11233 #define MC_MEM_POWER_LS__LS_SETUP_MASK                                                                        0x0000003FL
11234 #define MC_MEM_POWER_LS__LS_HOLD_MASK                                                                         0x00000FC0L
11235 //MC_VM_CACHEABLE_DRAM_ADDRESS_START
11236 #define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT                                                    0x0
11237 #define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK                                                      0x00FFFFFFL
11238 //MC_VM_CACHEABLE_DRAM_ADDRESS_END
11239 #define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT                                                      0x0
11240 #define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK                                                        0x00FFFFFFL
11241 //MC_VM_APT_CNTL
11242 #define MC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT                                                                 0x0
11243 #define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT                                                               0x1
11244 #define MC_VM_APT_CNTL__CHECK_IS_LOCAL__SHIFT                                                                 0x2
11245 #define MC_VM_APT_CNTL__PERMS_GRANTED__SHIFT                                                                  0x3
11246 #define MC_VM_APT_CNTL__LOCAL_SYSMEM_APERTURE_CNTL__SHIFT                                                     0x4
11247 #define MC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK                                                                   0x00000001L
11248 #define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK                                                                 0x00000002L
11249 #define MC_VM_APT_CNTL__CHECK_IS_LOCAL_MASK                                                                   0x00000004L
11250 #define MC_VM_APT_CNTL__PERMS_GRANTED_MASK                                                                    0x00000008L
11251 #define MC_VM_APT_CNTL__LOCAL_SYSMEM_APERTURE_CNTL_MASK                                                       0x00000030L
11252 //MC_VM_LOCAL_HBM_ADDRESS_START
11253 #define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS__SHIFT                                                         0x0
11254 #define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_MASK                                                           0x00FFFFFFL
11255 //MC_VM_LOCAL_HBM_ADDRESS_END
11256 #define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS__SHIFT                                                           0x0
11257 #define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_MASK                                                             0x00FFFFFFL
11258 //MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL
11259 #define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT                                                        0x0
11260 #define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK                                                          0x00000001L
11261 //UTCL2_CGTT_CLK_CTRL
11262 #define UTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                                  0x0
11263 #define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                            0x4
11264 #define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA__SHIFT                                                       0xc
11265 #define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT                                                             0xf
11266 #define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                       0x10
11267 #define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT                                                             0x18
11268 #define UTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                    0x0000000FL
11269 #define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                              0x00000FF0L
11270 #define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA_MASK                                                         0x00007000L
11271 #define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK                                                               0x00008000L
11272 #define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                         0x00FF0000L
11273 #define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK                                                               0xFF000000L
11274 //MC_VM_XGMI_LFB_CNTL
11275 #define MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION__SHIFT                                                             0x0
11276 #define MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION__SHIFT                                                             0x4
11277 #define MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION_MASK                                                               0x0000000FL
11278 #define MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION_MASK                                                               0x000000F0L
11279 //MC_VM_XGMI_LFB_SIZE
11280 #define MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE__SHIFT                                                               0x0
11281 #define MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE_MASK                                                                 0x0001FFFFL
11282 //MC_VM_CACHEABLE_DRAM_CNTL
11283 #define MC_VM_CACHEABLE_DRAM_CNTL__ENABLE_CACHEABLE_DRAM_ADDRESS_APERTURE__SHIFT                              0x0
11284 #define MC_VM_CACHEABLE_DRAM_CNTL__ENABLE_CACHEABLE_DRAM_ADDRESS_APERTURE_MASK                                0x00000001L
11285 //MC_VM_HOST_MAPPING
11286 #define MC_VM_HOST_MAPPING__MODE__SHIFT                                                                       0x0
11287 #define MC_VM_HOST_MAPPING__MODE_MASK                                                                         0x00000001L
11288 
11289 
11290 // addressBlock: xcd0_gc_utcl2_vmsharedvcdec
11291 //MC_VM_FB_LOCATION_BASE
11292 #define MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT                                                                0x0
11293 #define MC_VM_FB_LOCATION_BASE__FB_BASE_MASK                                                                  0x00FFFFFFL
11294 //MC_VM_FB_LOCATION_TOP
11295 #define MC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT                                                                  0x0
11296 #define MC_VM_FB_LOCATION_TOP__FB_TOP_MASK                                                                    0x00FFFFFFL
11297 //MC_VM_AGP_TOP
11298 #define MC_VM_AGP_TOP__AGP_TOP__SHIFT                                                                         0x0
11299 #define MC_VM_AGP_TOP__AGP_TOP_MASK                                                                           0x00FFFFFFL
11300 //MC_VM_AGP_BOT
11301 #define MC_VM_AGP_BOT__AGP_BOT__SHIFT                                                                         0x0
11302 #define MC_VM_AGP_BOT__AGP_BOT_MASK                                                                           0x00FFFFFFL
11303 //MC_VM_AGP_BASE
11304 #define MC_VM_AGP_BASE__AGP_BASE__SHIFT                                                                       0x0
11305 #define MC_VM_AGP_BASE__AGP_BASE_MASK                                                                         0x00FFFFFFL
11306 //MC_VM_SYSTEM_APERTURE_LOW_ADDR
11307 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT                                                   0x0
11308 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK                                                     0x3FFFFFFFL
11309 //MC_VM_SYSTEM_APERTURE_HIGH_ADDR
11310 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT                                                  0x0
11311 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK                                                    0x3FFFFFFFL
11312 //MC_VM_MX_L1_TLB_CNTL
11313 #define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT                                                            0x0
11314 #define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT                                                       0x3
11315 #define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT                                          0x5
11316 #define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT                                             0x6
11317 #define MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT                                                                 0x7
11318 #define MC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT                                                                    0xb
11319 #define MC_VM_MX_L1_TLB_CNTL__ATC_EN__SHIFT                                                                   0xd
11320 #define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK                                                              0x00000001L
11321 #define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK                                                         0x00000018L
11322 #define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK                                            0x00000020L
11323 #define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK                                               0x00000040L
11324 #define MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK                                                                   0x00000780L
11325 #define MC_VM_MX_L1_TLB_CNTL__MTYPE_MASK                                                                      0x00001800L
11326 #define MC_VM_MX_L1_TLB_CNTL__ATC_EN_MASK                                                                     0x00002000L
11327 
11328 
11329 // addressBlock: xcd0_gc_utcl2_l2tlbdec
11330 //L2TLB_TLB0_STATUS
11331 #define L2TLB_TLB0_STATUS__BUSY__SHIFT                                                                        0x0
11332 #define L2TLB_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT                                                         0x1
11333 #define L2TLB_TLB0_STATUS__BUSY_MASK                                                                          0x00000001L
11334 #define L2TLB_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK                                                           0x00000002L
11335 //UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO
11336 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR__SHIFT                                             0x0
11337 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR_MASK                                               0xFFFFFFFFL
11338 //UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI
11339 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR__SHIFT                                             0x0
11340 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID__SHIFT                                             0x4
11341 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID__SHIFT                                             0x9
11342 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF__SHIFT                                               0xd
11343 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA__SHIFT                                              0xe
11344 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM__SHIFT                                          0x10
11345 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM__SHIFT                                          0x11
11346 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM__SHIFT                                          0x12
11347 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID__SHIFT                                        0x13
11348 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ__SHIFT                                              0x1f
11349 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR_MASK                                               0x0000000FL
11350 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID_MASK                                               0x000000F0L
11351 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID_MASK                                               0x00001E00L
11352 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF_MASK                                                 0x00002000L
11353 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA_MASK                                                0x0000C000L
11354 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM_MASK                                            0x00010000L
11355 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM_MASK                                            0x00020000L
11356 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM_MASK                                            0x00040000L
11357 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID_MASK                                          0x0FF80000L
11358 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ_MASK                                                0x80000000L
11359 //UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO
11360 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR__SHIFT                                            0x0
11361 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR_MASK                                              0xFFFFFFFFL
11362 //UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI
11363 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR__SHIFT                                            0x0
11364 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS__SHIFT                                           0x4
11365 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE__SHIFT                                   0x7
11366 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP__SHIFT                                           0xd
11367 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA__SHIFT                                             0xe
11368 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO__SHIFT                                              0xf
11369 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ__SHIFT                                         0x10
11370 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE__SHIFT                                          0x11
11371 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE__SHIFT                                           0x12
11372 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG__SHIFT                                          0x14
11373 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__LLC_NOALLOC__SHIFT                                     0x15
11374 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK__SHIFT                                            0x16
11375 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK__SHIFT                                             0x1f
11376 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR_MASK                                              0x0000000FL
11377 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS_MASK                                             0x00000070L
11378 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE_MASK                                     0x00001F80L
11379 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP_MASK                                             0x00002000L
11380 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA_MASK                                               0x00004000L
11381 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO_MASK                                                0x00008000L
11382 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ_MASK                                           0x00010000L
11383 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE_MASK                                            0x00020000L
11384 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE_MASK                                             0x000C0000L
11385 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG_MASK                                            0x00100000L
11386 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__LLC_NOALLOC_MASK                                       0x00200000L
11387 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK_MASK                                              0x00C00000L
11388 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK_MASK                                               0x80000000L
11389 
11390 
11391 // addressBlock: xcd0_gc_tcdec
11392 //TCP_INVALIDATE
11393 #define TCP_INVALIDATE__START__SHIFT                                                                          0x0
11394 #define TCP_INVALIDATE__START_MASK                                                                            0x00000001L
11395 //TCP_STATUS
11396 #define TCP_STATUS__TCP_BUSY__SHIFT                                                                           0x0
11397 #define TCP_STATUS__INPUT_BUSY__SHIFT                                                                         0x1
11398 #define TCP_STATUS__ADRS_BUSY__SHIFT                                                                          0x2
11399 #define TCP_STATUS__TAGRAMS_BUSY__SHIFT                                                                       0x3
11400 #define TCP_STATUS__CNTRL_BUSY__SHIFT                                                                         0x4
11401 #define TCP_STATUS__LFIFO_BUSY__SHIFT                                                                         0x5
11402 #define TCP_STATUS__READ_BUSY__SHIFT                                                                          0x6
11403 #define TCP_STATUS__FORMAT_BUSY__SHIFT                                                                        0x7
11404 #define TCP_STATUS__VM_BUSY__SHIFT                                                                            0x8
11405 #define TCP_STATUS__TCP_BUSY_MASK                                                                             0x00000001L
11406 #define TCP_STATUS__INPUT_BUSY_MASK                                                                           0x00000002L
11407 #define TCP_STATUS__ADRS_BUSY_MASK                                                                            0x00000004L
11408 #define TCP_STATUS__TAGRAMS_BUSY_MASK                                                                         0x00000008L
11409 #define TCP_STATUS__CNTRL_BUSY_MASK                                                                           0x00000010L
11410 #define TCP_STATUS__LFIFO_BUSY_MASK                                                                           0x00000020L
11411 #define TCP_STATUS__READ_BUSY_MASK                                                                            0x00000040L
11412 #define TCP_STATUS__FORMAT_BUSY_MASK                                                                          0x00000080L
11413 #define TCP_STATUS__VM_BUSY_MASK                                                                              0x00000100L
11414 //TCP_CNTL
11415 #define TCP_CNTL__FORCE_HIT__SHIFT                                                                            0x0
11416 #define TCP_CNTL__FORCE_MISS__SHIFT                                                                           0x1
11417 #define TCP_CNTL__L1_SIZE__SHIFT                                                                              0x2
11418 #define TCP_CNTL__FLAT_BUF_HASH_ENABLE__SHIFT                                                                 0x4
11419 #define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE__SHIFT                                                               0x5
11420 #define TCP_CNTL__FORCE_EOW_TOTAL_CNT__SHIFT                                                                  0xf
11421 #define TCP_CNTL__FORCE_EOW_TAGRAM_CNT__SHIFT                                                                 0x16
11422 #define TCP_CNTL__DISABLE_Z_MAP__SHIFT                                                                        0x1c
11423 #define TCP_CNTL__FORCE_HIT_MASK                                                                              0x00000001L
11424 #define TCP_CNTL__FORCE_MISS_MASK                                                                             0x00000002L
11425 #define TCP_CNTL__L1_SIZE_MASK                                                                                0x0000000CL
11426 #define TCP_CNTL__FLAT_BUF_HASH_ENABLE_MASK                                                                   0x00000010L
11427 #define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE_MASK                                                                 0x00000020L
11428 #define TCP_CNTL__FORCE_EOW_TOTAL_CNT_MASK                                                                    0x001F8000L
11429 #define TCP_CNTL__FORCE_EOW_TAGRAM_CNT_MASK                                                                   0x0FC00000L
11430 #define TCP_CNTL__DISABLE_Z_MAP_MASK                                                                          0x10000000L
11431 //TCP_CHAN_STEER_0
11432 #define TCP_CHAN_STEER_0__CHAN0__SHIFT                                                                        0x0
11433 #define TCP_CHAN_STEER_0__CHAN1__SHIFT                                                                        0x4
11434 #define TCP_CHAN_STEER_0__CHAN2__SHIFT                                                                        0x8
11435 #define TCP_CHAN_STEER_0__CHAN3__SHIFT                                                                        0xc
11436 #define TCP_CHAN_STEER_0__CHAN4__SHIFT                                                                        0x10
11437 #define TCP_CHAN_STEER_0__CHAN5__SHIFT                                                                        0x14
11438 #define TCP_CHAN_STEER_0__CHAN6__SHIFT                                                                        0x18
11439 #define TCP_CHAN_STEER_0__CHAN7__SHIFT                                                                        0x1c
11440 #define TCP_CHAN_STEER_0__CHAN0_MASK                                                                          0x0000000FL
11441 #define TCP_CHAN_STEER_0__CHAN1_MASK                                                                          0x000000F0L
11442 #define TCP_CHAN_STEER_0__CHAN2_MASK                                                                          0x00000F00L
11443 #define TCP_CHAN_STEER_0__CHAN3_MASK                                                                          0x0000F000L
11444 #define TCP_CHAN_STEER_0__CHAN4_MASK                                                                          0x000F0000L
11445 #define TCP_CHAN_STEER_0__CHAN5_MASK                                                                          0x00F00000L
11446 #define TCP_CHAN_STEER_0__CHAN6_MASK                                                                          0x0F000000L
11447 #define TCP_CHAN_STEER_0__CHAN7_MASK                                                                          0xF0000000L
11448 //TCP_CHAN_STEER_1
11449 #define TCP_CHAN_STEER_1__CHAN8__SHIFT                                                                        0x0
11450 #define TCP_CHAN_STEER_1__CHAN9__SHIFT                                                                        0x4
11451 #define TCP_CHAN_STEER_1__CHANA__SHIFT                                                                        0x8
11452 #define TCP_CHAN_STEER_1__CHANB__SHIFT                                                                        0xc
11453 #define TCP_CHAN_STEER_1__CHANC__SHIFT                                                                        0x10
11454 #define TCP_CHAN_STEER_1__CHAND__SHIFT                                                                        0x14
11455 #define TCP_CHAN_STEER_1__CHANE__SHIFT                                                                        0x18
11456 #define TCP_CHAN_STEER_1__CHANF__SHIFT                                                                        0x1c
11457 #define TCP_CHAN_STEER_1__CHAN8_MASK                                                                          0x0000000FL
11458 #define TCP_CHAN_STEER_1__CHAN9_MASK                                                                          0x000000F0L
11459 #define TCP_CHAN_STEER_1__CHANA_MASK                                                                          0x00000F00L
11460 #define TCP_CHAN_STEER_1__CHANB_MASK                                                                          0x0000F000L
11461 #define TCP_CHAN_STEER_1__CHANC_MASK                                                                          0x000F0000L
11462 #define TCP_CHAN_STEER_1__CHAND_MASK                                                                          0x00F00000L
11463 #define TCP_CHAN_STEER_1__CHANE_MASK                                                                          0x0F000000L
11464 #define TCP_CHAN_STEER_1__CHANF_MASK                                                                          0xF0000000L
11465 //TCP_ADDR_CONFIG
11466 #define TCP_ADDR_CONFIG__NUM_TCC_BANKS__SHIFT                                                                 0x0
11467 #define TCP_ADDR_CONFIG__ENABLE64KHASH__SHIFT                                                                 0xb
11468 #define TCP_ADDR_CONFIG__ENABLE2MHASH__SHIFT                                                                  0xc
11469 #define TCP_ADDR_CONFIG__ENABLE1GHASH__SHIFT                                                                  0xd
11470 #define TCP_ADDR_CONFIG__ENABLE1THASH__SHIFT                                                                  0xe
11471 #define TCP_ADDR_CONFIG__ENABLE4KHASH__SHIFT                                                                  0xf
11472 #define TCP_ADDR_CONFIG__NUM_TCC_BANKS_MASK                                                                   0x0000001FL
11473 #define TCP_ADDR_CONFIG__ENABLE64KHASH_MASK                                                                   0x00000800L
11474 #define TCP_ADDR_CONFIG__ENABLE2MHASH_MASK                                                                    0x00001000L
11475 #define TCP_ADDR_CONFIG__ENABLE1GHASH_MASK                                                                    0x00002000L
11476 #define TCP_ADDR_CONFIG__ENABLE1THASH_MASK                                                                    0x00004000L
11477 #define TCP_ADDR_CONFIG__ENABLE4KHASH_MASK                                                                    0x00008000L
11478 //TCP_CREDIT
11479 #define TCP_CREDIT__LFIFO_CREDIT__SHIFT                                                                       0x0
11480 #define TCP_CREDIT__REQ_FIFO_CREDIT__SHIFT                                                                    0x10
11481 #define TCP_CREDIT__TD_CREDIT__SHIFT                                                                          0x1d
11482 #define TCP_CREDIT__LFIFO_CREDIT_MASK                                                                         0x000007FFL
11483 #define TCP_CREDIT__REQ_FIFO_CREDIT_MASK                                                                      0x007F0000L
11484 #define TCP_CREDIT__TD_CREDIT_MASK                                                                            0xE0000000L
11485 //TCP_BUFFER_ADDR_HASH_CNTL
11486 #define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS__SHIFT                                                        0x0
11487 #define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS__SHIFT                                                           0x8
11488 #define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT__SHIFT                                                   0x10
11489 #define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT__SHIFT                                                      0x18
11490 #define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS_MASK                                                          0x00000007L
11491 #define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS_MASK                                                             0x00000700L
11492 #define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT_MASK                                                     0x00070000L
11493 #define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT_MASK                                                        0x07000000L
11494 //TC_CFG_L1_LOAD_POLICY0
11495 #define TC_CFG_L1_LOAD_POLICY0__POLICY_0__SHIFT                                                               0x0
11496 #define TC_CFG_L1_LOAD_POLICY0__POLICY_1__SHIFT                                                               0x2
11497 #define TC_CFG_L1_LOAD_POLICY0__POLICY_2__SHIFT                                                               0x4
11498 #define TC_CFG_L1_LOAD_POLICY0__POLICY_3__SHIFT                                                               0x6
11499 #define TC_CFG_L1_LOAD_POLICY0__POLICY_4__SHIFT                                                               0x8
11500 #define TC_CFG_L1_LOAD_POLICY0__POLICY_5__SHIFT                                                               0xa
11501 #define TC_CFG_L1_LOAD_POLICY0__POLICY_6__SHIFT                                                               0xc
11502 #define TC_CFG_L1_LOAD_POLICY0__POLICY_7__SHIFT                                                               0xe
11503 #define TC_CFG_L1_LOAD_POLICY0__POLICY_8__SHIFT                                                               0x10
11504 #define TC_CFG_L1_LOAD_POLICY0__POLICY_9__SHIFT                                                               0x12
11505 #define TC_CFG_L1_LOAD_POLICY0__POLICY_10__SHIFT                                                              0x14
11506 #define TC_CFG_L1_LOAD_POLICY0__POLICY_11__SHIFT                                                              0x16
11507 #define TC_CFG_L1_LOAD_POLICY0__POLICY_12__SHIFT                                                              0x18
11508 #define TC_CFG_L1_LOAD_POLICY0__POLICY_13__SHIFT                                                              0x1a
11509 #define TC_CFG_L1_LOAD_POLICY0__POLICY_14__SHIFT                                                              0x1c
11510 #define TC_CFG_L1_LOAD_POLICY0__POLICY_15__SHIFT                                                              0x1e
11511 #define TC_CFG_L1_LOAD_POLICY0__POLICY_0_MASK                                                                 0x00000003L
11512 #define TC_CFG_L1_LOAD_POLICY0__POLICY_1_MASK                                                                 0x0000000CL
11513 #define TC_CFG_L1_LOAD_POLICY0__POLICY_2_MASK                                                                 0x00000030L
11514 #define TC_CFG_L1_LOAD_POLICY0__POLICY_3_MASK                                                                 0x000000C0L
11515 #define TC_CFG_L1_LOAD_POLICY0__POLICY_4_MASK                                                                 0x00000300L
11516 #define TC_CFG_L1_LOAD_POLICY0__POLICY_5_MASK                                                                 0x00000C00L
11517 #define TC_CFG_L1_LOAD_POLICY0__POLICY_6_MASK                                                                 0x00003000L
11518 #define TC_CFG_L1_LOAD_POLICY0__POLICY_7_MASK                                                                 0x0000C000L
11519 #define TC_CFG_L1_LOAD_POLICY0__POLICY_8_MASK                                                                 0x00030000L
11520 #define TC_CFG_L1_LOAD_POLICY0__POLICY_9_MASK                                                                 0x000C0000L
11521 #define TC_CFG_L1_LOAD_POLICY0__POLICY_10_MASK                                                                0x00300000L
11522 #define TC_CFG_L1_LOAD_POLICY0__POLICY_11_MASK                                                                0x00C00000L
11523 #define TC_CFG_L1_LOAD_POLICY0__POLICY_12_MASK                                                                0x03000000L
11524 #define TC_CFG_L1_LOAD_POLICY0__POLICY_13_MASK                                                                0x0C000000L
11525 #define TC_CFG_L1_LOAD_POLICY0__POLICY_14_MASK                                                                0x30000000L
11526 #define TC_CFG_L1_LOAD_POLICY0__POLICY_15_MASK                                                                0xC0000000L
11527 //TC_CFG_L1_LOAD_POLICY1
11528 #define TC_CFG_L1_LOAD_POLICY1__POLICY_16__SHIFT                                                              0x0
11529 #define TC_CFG_L1_LOAD_POLICY1__POLICY_17__SHIFT                                                              0x2
11530 #define TC_CFG_L1_LOAD_POLICY1__POLICY_18__SHIFT                                                              0x4
11531 #define TC_CFG_L1_LOAD_POLICY1__POLICY_19__SHIFT                                                              0x6
11532 #define TC_CFG_L1_LOAD_POLICY1__POLICY_20__SHIFT                                                              0x8
11533 #define TC_CFG_L1_LOAD_POLICY1__POLICY_21__SHIFT                                                              0xa
11534 #define TC_CFG_L1_LOAD_POLICY1__POLICY_22__SHIFT                                                              0xc
11535 #define TC_CFG_L1_LOAD_POLICY1__POLICY_23__SHIFT                                                              0xe
11536 #define TC_CFG_L1_LOAD_POLICY1__POLICY_24__SHIFT                                                              0x10
11537 #define TC_CFG_L1_LOAD_POLICY1__POLICY_25__SHIFT                                                              0x12
11538 #define TC_CFG_L1_LOAD_POLICY1__POLICY_26__SHIFT                                                              0x14
11539 #define TC_CFG_L1_LOAD_POLICY1__POLICY_27__SHIFT                                                              0x16
11540 #define TC_CFG_L1_LOAD_POLICY1__POLICY_28__SHIFT                                                              0x18
11541 #define TC_CFG_L1_LOAD_POLICY1__POLICY_29__SHIFT                                                              0x1a
11542 #define TC_CFG_L1_LOAD_POLICY1__POLICY_30__SHIFT                                                              0x1c
11543 #define TC_CFG_L1_LOAD_POLICY1__POLICY_31__SHIFT                                                              0x1e
11544 #define TC_CFG_L1_LOAD_POLICY1__POLICY_16_MASK                                                                0x00000003L
11545 #define TC_CFG_L1_LOAD_POLICY1__POLICY_17_MASK                                                                0x0000000CL
11546 #define TC_CFG_L1_LOAD_POLICY1__POLICY_18_MASK                                                                0x00000030L
11547 #define TC_CFG_L1_LOAD_POLICY1__POLICY_19_MASK                                                                0x000000C0L
11548 #define TC_CFG_L1_LOAD_POLICY1__POLICY_20_MASK                                                                0x00000300L
11549 #define TC_CFG_L1_LOAD_POLICY1__POLICY_21_MASK                                                                0x00000C00L
11550 #define TC_CFG_L1_LOAD_POLICY1__POLICY_22_MASK                                                                0x00003000L
11551 #define TC_CFG_L1_LOAD_POLICY1__POLICY_23_MASK                                                                0x0000C000L
11552 #define TC_CFG_L1_LOAD_POLICY1__POLICY_24_MASK                                                                0x00030000L
11553 #define TC_CFG_L1_LOAD_POLICY1__POLICY_25_MASK                                                                0x000C0000L
11554 #define TC_CFG_L1_LOAD_POLICY1__POLICY_26_MASK                                                                0x00300000L
11555 #define TC_CFG_L1_LOAD_POLICY1__POLICY_27_MASK                                                                0x00C00000L
11556 #define TC_CFG_L1_LOAD_POLICY1__POLICY_28_MASK                                                                0x03000000L
11557 #define TC_CFG_L1_LOAD_POLICY1__POLICY_29_MASK                                                                0x0C000000L
11558 #define TC_CFG_L1_LOAD_POLICY1__POLICY_30_MASK                                                                0x30000000L
11559 #define TC_CFG_L1_LOAD_POLICY1__POLICY_31_MASK                                                                0xC0000000L
11560 //TC_CFG_L1_STORE_POLICY
11561 #define TC_CFG_L1_STORE_POLICY__POLICY_0__SHIFT                                                               0x0
11562 #define TC_CFG_L1_STORE_POLICY__POLICY_1__SHIFT                                                               0x1
11563 #define TC_CFG_L1_STORE_POLICY__POLICY_2__SHIFT                                                               0x2
11564 #define TC_CFG_L1_STORE_POLICY__POLICY_3__SHIFT                                                               0x3
11565 #define TC_CFG_L1_STORE_POLICY__POLICY_4__SHIFT                                                               0x4
11566 #define TC_CFG_L1_STORE_POLICY__POLICY_5__SHIFT                                                               0x5
11567 #define TC_CFG_L1_STORE_POLICY__POLICY_6__SHIFT                                                               0x6
11568 #define TC_CFG_L1_STORE_POLICY__POLICY_7__SHIFT                                                               0x7
11569 #define TC_CFG_L1_STORE_POLICY__POLICY_8__SHIFT                                                               0x8
11570 #define TC_CFG_L1_STORE_POLICY__POLICY_9__SHIFT                                                               0x9
11571 #define TC_CFG_L1_STORE_POLICY__POLICY_10__SHIFT                                                              0xa
11572 #define TC_CFG_L1_STORE_POLICY__POLICY_11__SHIFT                                                              0xb
11573 #define TC_CFG_L1_STORE_POLICY__POLICY_12__SHIFT                                                              0xc
11574 #define TC_CFG_L1_STORE_POLICY__POLICY_13__SHIFT                                                              0xd
11575 #define TC_CFG_L1_STORE_POLICY__POLICY_14__SHIFT                                                              0xe
11576 #define TC_CFG_L1_STORE_POLICY__POLICY_15__SHIFT                                                              0xf
11577 #define TC_CFG_L1_STORE_POLICY__POLICY_16__SHIFT                                                              0x10
11578 #define TC_CFG_L1_STORE_POLICY__POLICY_17__SHIFT                                                              0x11
11579 #define TC_CFG_L1_STORE_POLICY__POLICY_18__SHIFT                                                              0x12
11580 #define TC_CFG_L1_STORE_POLICY__POLICY_19__SHIFT                                                              0x13
11581 #define TC_CFG_L1_STORE_POLICY__POLICY_20__SHIFT                                                              0x14
11582 #define TC_CFG_L1_STORE_POLICY__POLICY_21__SHIFT                                                              0x15
11583 #define TC_CFG_L1_STORE_POLICY__POLICY_22__SHIFT                                                              0x16
11584 #define TC_CFG_L1_STORE_POLICY__POLICY_23__SHIFT                                                              0x17
11585 #define TC_CFG_L1_STORE_POLICY__POLICY_24__SHIFT                                                              0x18
11586 #define TC_CFG_L1_STORE_POLICY__POLICY_25__SHIFT                                                              0x19
11587 #define TC_CFG_L1_STORE_POLICY__POLICY_26__SHIFT                                                              0x1a
11588 #define TC_CFG_L1_STORE_POLICY__POLICY_27__SHIFT                                                              0x1b
11589 #define TC_CFG_L1_STORE_POLICY__POLICY_28__SHIFT                                                              0x1c
11590 #define TC_CFG_L1_STORE_POLICY__POLICY_29__SHIFT                                                              0x1d
11591 #define TC_CFG_L1_STORE_POLICY__POLICY_30__SHIFT                                                              0x1e
11592 #define TC_CFG_L1_STORE_POLICY__POLICY_31__SHIFT                                                              0x1f
11593 #define TC_CFG_L1_STORE_POLICY__POLICY_0_MASK                                                                 0x00000001L
11594 #define TC_CFG_L1_STORE_POLICY__POLICY_1_MASK                                                                 0x00000002L
11595 #define TC_CFG_L1_STORE_POLICY__POLICY_2_MASK                                                                 0x00000004L
11596 #define TC_CFG_L1_STORE_POLICY__POLICY_3_MASK                                                                 0x00000008L
11597 #define TC_CFG_L1_STORE_POLICY__POLICY_4_MASK                                                                 0x00000010L
11598 #define TC_CFG_L1_STORE_POLICY__POLICY_5_MASK                                                                 0x00000020L
11599 #define TC_CFG_L1_STORE_POLICY__POLICY_6_MASK                                                                 0x00000040L
11600 #define TC_CFG_L1_STORE_POLICY__POLICY_7_MASK                                                                 0x00000080L
11601 #define TC_CFG_L1_STORE_POLICY__POLICY_8_MASK                                                                 0x00000100L
11602 #define TC_CFG_L1_STORE_POLICY__POLICY_9_MASK                                                                 0x00000200L
11603 #define TC_CFG_L1_STORE_POLICY__POLICY_10_MASK                                                                0x00000400L
11604 #define TC_CFG_L1_STORE_POLICY__POLICY_11_MASK                                                                0x00000800L
11605 #define TC_CFG_L1_STORE_POLICY__POLICY_12_MASK                                                                0x00001000L
11606 #define TC_CFG_L1_STORE_POLICY__POLICY_13_MASK                                                                0x00002000L
11607 #define TC_CFG_L1_STORE_POLICY__POLICY_14_MASK                                                                0x00004000L
11608 #define TC_CFG_L1_STORE_POLICY__POLICY_15_MASK                                                                0x00008000L
11609 #define TC_CFG_L1_STORE_POLICY__POLICY_16_MASK                                                                0x00010000L
11610 #define TC_CFG_L1_STORE_POLICY__POLICY_17_MASK                                                                0x00020000L
11611 #define TC_CFG_L1_STORE_POLICY__POLICY_18_MASK                                                                0x00040000L
11612 #define TC_CFG_L1_STORE_POLICY__POLICY_19_MASK                                                                0x00080000L
11613 #define TC_CFG_L1_STORE_POLICY__POLICY_20_MASK                                                                0x00100000L
11614 #define TC_CFG_L1_STORE_POLICY__POLICY_21_MASK                                                                0x00200000L
11615 #define TC_CFG_L1_STORE_POLICY__POLICY_22_MASK                                                                0x00400000L
11616 #define TC_CFG_L1_STORE_POLICY__POLICY_23_MASK                                                                0x00800000L
11617 #define TC_CFG_L1_STORE_POLICY__POLICY_24_MASK                                                                0x01000000L
11618 #define TC_CFG_L1_STORE_POLICY__POLICY_25_MASK                                                                0x02000000L
11619 #define TC_CFG_L1_STORE_POLICY__POLICY_26_MASK                                                                0x04000000L
11620 #define TC_CFG_L1_STORE_POLICY__POLICY_27_MASK                                                                0x08000000L
11621 #define TC_CFG_L1_STORE_POLICY__POLICY_28_MASK                                                                0x10000000L
11622 #define TC_CFG_L1_STORE_POLICY__POLICY_29_MASK                                                                0x20000000L
11623 #define TC_CFG_L1_STORE_POLICY__POLICY_30_MASK                                                                0x40000000L
11624 #define TC_CFG_L1_STORE_POLICY__POLICY_31_MASK                                                                0x80000000L
11625 //TC_CFG_L2_LOAD_POLICY0
11626 #define TC_CFG_L2_LOAD_POLICY0__POLICY_0__SHIFT                                                               0x0
11627 #define TC_CFG_L2_LOAD_POLICY0__POLICY_1__SHIFT                                                               0x2
11628 #define TC_CFG_L2_LOAD_POLICY0__POLICY_2__SHIFT                                                               0x4
11629 #define TC_CFG_L2_LOAD_POLICY0__POLICY_3__SHIFT                                                               0x6
11630 #define TC_CFG_L2_LOAD_POLICY0__POLICY_4__SHIFT                                                               0x8
11631 #define TC_CFG_L2_LOAD_POLICY0__POLICY_5__SHIFT                                                               0xa
11632 #define TC_CFG_L2_LOAD_POLICY0__POLICY_6__SHIFT                                                               0xc
11633 #define TC_CFG_L2_LOAD_POLICY0__POLICY_7__SHIFT                                                               0xe
11634 #define TC_CFG_L2_LOAD_POLICY0__POLICY_8__SHIFT                                                               0x10
11635 #define TC_CFG_L2_LOAD_POLICY0__POLICY_9__SHIFT                                                               0x12
11636 #define TC_CFG_L2_LOAD_POLICY0__POLICY_10__SHIFT                                                              0x14
11637 #define TC_CFG_L2_LOAD_POLICY0__POLICY_11__SHIFT                                                              0x16
11638 #define TC_CFG_L2_LOAD_POLICY0__POLICY_12__SHIFT                                                              0x18
11639 #define TC_CFG_L2_LOAD_POLICY0__POLICY_13__SHIFT                                                              0x1a
11640 #define TC_CFG_L2_LOAD_POLICY0__POLICY_14__SHIFT                                                              0x1c
11641 #define TC_CFG_L2_LOAD_POLICY0__POLICY_15__SHIFT                                                              0x1e
11642 #define TC_CFG_L2_LOAD_POLICY0__POLICY_0_MASK                                                                 0x00000003L
11643 #define TC_CFG_L2_LOAD_POLICY0__POLICY_1_MASK                                                                 0x0000000CL
11644 #define TC_CFG_L2_LOAD_POLICY0__POLICY_2_MASK                                                                 0x00000030L
11645 #define TC_CFG_L2_LOAD_POLICY0__POLICY_3_MASK                                                                 0x000000C0L
11646 #define TC_CFG_L2_LOAD_POLICY0__POLICY_4_MASK                                                                 0x00000300L
11647 #define TC_CFG_L2_LOAD_POLICY0__POLICY_5_MASK                                                                 0x00000C00L
11648 #define TC_CFG_L2_LOAD_POLICY0__POLICY_6_MASK                                                                 0x00003000L
11649 #define TC_CFG_L2_LOAD_POLICY0__POLICY_7_MASK                                                                 0x0000C000L
11650 #define TC_CFG_L2_LOAD_POLICY0__POLICY_8_MASK                                                                 0x00030000L
11651 #define TC_CFG_L2_LOAD_POLICY0__POLICY_9_MASK                                                                 0x000C0000L
11652 #define TC_CFG_L2_LOAD_POLICY0__POLICY_10_MASK                                                                0x00300000L
11653 #define TC_CFG_L2_LOAD_POLICY0__POLICY_11_MASK                                                                0x00C00000L
11654 #define TC_CFG_L2_LOAD_POLICY0__POLICY_12_MASK                                                                0x03000000L
11655 #define TC_CFG_L2_LOAD_POLICY0__POLICY_13_MASK                                                                0x0C000000L
11656 #define TC_CFG_L2_LOAD_POLICY0__POLICY_14_MASK                                                                0x30000000L
11657 #define TC_CFG_L2_LOAD_POLICY0__POLICY_15_MASK                                                                0xC0000000L
11658 //TC_CFG_L2_LOAD_POLICY1
11659 #define TC_CFG_L2_LOAD_POLICY1__POLICY_16__SHIFT                                                              0x0
11660 #define TC_CFG_L2_LOAD_POLICY1__POLICY_17__SHIFT                                                              0x2
11661 #define TC_CFG_L2_LOAD_POLICY1__POLICY_18__SHIFT                                                              0x4
11662 #define TC_CFG_L2_LOAD_POLICY1__POLICY_19__SHIFT                                                              0x6
11663 #define TC_CFG_L2_LOAD_POLICY1__POLICY_20__SHIFT                                                              0x8
11664 #define TC_CFG_L2_LOAD_POLICY1__POLICY_21__SHIFT                                                              0xa
11665 #define TC_CFG_L2_LOAD_POLICY1__POLICY_22__SHIFT                                                              0xc
11666 #define TC_CFG_L2_LOAD_POLICY1__POLICY_23__SHIFT                                                              0xe
11667 #define TC_CFG_L2_LOAD_POLICY1__POLICY_24__SHIFT                                                              0x10
11668 #define TC_CFG_L2_LOAD_POLICY1__POLICY_25__SHIFT                                                              0x12
11669 #define TC_CFG_L2_LOAD_POLICY1__POLICY_26__SHIFT                                                              0x14
11670 #define TC_CFG_L2_LOAD_POLICY1__POLICY_27__SHIFT                                                              0x16
11671 #define TC_CFG_L2_LOAD_POLICY1__POLICY_28__SHIFT                                                              0x18
11672 #define TC_CFG_L2_LOAD_POLICY1__POLICY_29__SHIFT                                                              0x1a
11673 #define TC_CFG_L2_LOAD_POLICY1__POLICY_30__SHIFT                                                              0x1c
11674 #define TC_CFG_L2_LOAD_POLICY1__POLICY_31__SHIFT                                                              0x1e
11675 #define TC_CFG_L2_LOAD_POLICY1__POLICY_16_MASK                                                                0x00000003L
11676 #define TC_CFG_L2_LOAD_POLICY1__POLICY_17_MASK                                                                0x0000000CL
11677 #define TC_CFG_L2_LOAD_POLICY1__POLICY_18_MASK                                                                0x00000030L
11678 #define TC_CFG_L2_LOAD_POLICY1__POLICY_19_MASK                                                                0x000000C0L
11679 #define TC_CFG_L2_LOAD_POLICY1__POLICY_20_MASK                                                                0x00000300L
11680 #define TC_CFG_L2_LOAD_POLICY1__POLICY_21_MASK                                                                0x00000C00L
11681 #define TC_CFG_L2_LOAD_POLICY1__POLICY_22_MASK                                                                0x00003000L
11682 #define TC_CFG_L2_LOAD_POLICY1__POLICY_23_MASK                                                                0x0000C000L
11683 #define TC_CFG_L2_LOAD_POLICY1__POLICY_24_MASK                                                                0x00030000L
11684 #define TC_CFG_L2_LOAD_POLICY1__POLICY_25_MASK                                                                0x000C0000L
11685 #define TC_CFG_L2_LOAD_POLICY1__POLICY_26_MASK                                                                0x00300000L
11686 #define TC_CFG_L2_LOAD_POLICY1__POLICY_27_MASK                                                                0x00C00000L
11687 #define TC_CFG_L2_LOAD_POLICY1__POLICY_28_MASK                                                                0x03000000L
11688 #define TC_CFG_L2_LOAD_POLICY1__POLICY_29_MASK                                                                0x0C000000L
11689 #define TC_CFG_L2_LOAD_POLICY1__POLICY_30_MASK                                                                0x30000000L
11690 #define TC_CFG_L2_LOAD_POLICY1__POLICY_31_MASK                                                                0xC0000000L
11691 //TC_CFG_L2_STORE_POLICY0
11692 #define TC_CFG_L2_STORE_POLICY0__POLICY_0__SHIFT                                                              0x0
11693 #define TC_CFG_L2_STORE_POLICY0__POLICY_1__SHIFT                                                              0x2
11694 #define TC_CFG_L2_STORE_POLICY0__POLICY_2__SHIFT                                                              0x4
11695 #define TC_CFG_L2_STORE_POLICY0__POLICY_3__SHIFT                                                              0x6
11696 #define TC_CFG_L2_STORE_POLICY0__POLICY_4__SHIFT                                                              0x8
11697 #define TC_CFG_L2_STORE_POLICY0__POLICY_5__SHIFT                                                              0xa
11698 #define TC_CFG_L2_STORE_POLICY0__POLICY_6__SHIFT                                                              0xc
11699 #define TC_CFG_L2_STORE_POLICY0__POLICY_7__SHIFT                                                              0xe
11700 #define TC_CFG_L2_STORE_POLICY0__POLICY_8__SHIFT                                                              0x10
11701 #define TC_CFG_L2_STORE_POLICY0__POLICY_9__SHIFT                                                              0x12
11702 #define TC_CFG_L2_STORE_POLICY0__POLICY_10__SHIFT                                                             0x14
11703 #define TC_CFG_L2_STORE_POLICY0__POLICY_11__SHIFT                                                             0x16
11704 #define TC_CFG_L2_STORE_POLICY0__POLICY_12__SHIFT                                                             0x18
11705 #define TC_CFG_L2_STORE_POLICY0__POLICY_13__SHIFT                                                             0x1a
11706 #define TC_CFG_L2_STORE_POLICY0__POLICY_14__SHIFT                                                             0x1c
11707 #define TC_CFG_L2_STORE_POLICY0__POLICY_15__SHIFT                                                             0x1e
11708 #define TC_CFG_L2_STORE_POLICY0__POLICY_0_MASK                                                                0x00000003L
11709 #define TC_CFG_L2_STORE_POLICY0__POLICY_1_MASK                                                                0x0000000CL
11710 #define TC_CFG_L2_STORE_POLICY0__POLICY_2_MASK                                                                0x00000030L
11711 #define TC_CFG_L2_STORE_POLICY0__POLICY_3_MASK                                                                0x000000C0L
11712 #define TC_CFG_L2_STORE_POLICY0__POLICY_4_MASK                                                                0x00000300L
11713 #define TC_CFG_L2_STORE_POLICY0__POLICY_5_MASK                                                                0x00000C00L
11714 #define TC_CFG_L2_STORE_POLICY0__POLICY_6_MASK                                                                0x00003000L
11715 #define TC_CFG_L2_STORE_POLICY0__POLICY_7_MASK                                                                0x0000C000L
11716 #define TC_CFG_L2_STORE_POLICY0__POLICY_8_MASK                                                                0x00030000L
11717 #define TC_CFG_L2_STORE_POLICY0__POLICY_9_MASK                                                                0x000C0000L
11718 #define TC_CFG_L2_STORE_POLICY0__POLICY_10_MASK                                                               0x00300000L
11719 #define TC_CFG_L2_STORE_POLICY0__POLICY_11_MASK                                                               0x00C00000L
11720 #define TC_CFG_L2_STORE_POLICY0__POLICY_12_MASK                                                               0x03000000L
11721 #define TC_CFG_L2_STORE_POLICY0__POLICY_13_MASK                                                               0x0C000000L
11722 #define TC_CFG_L2_STORE_POLICY0__POLICY_14_MASK                                                               0x30000000L
11723 #define TC_CFG_L2_STORE_POLICY0__POLICY_15_MASK                                                               0xC0000000L
11724 //TC_CFG_L2_STORE_POLICY1
11725 #define TC_CFG_L2_STORE_POLICY1__POLICY_16__SHIFT                                                             0x0
11726 #define TC_CFG_L2_STORE_POLICY1__POLICY_17__SHIFT                                                             0x2
11727 #define TC_CFG_L2_STORE_POLICY1__POLICY_18__SHIFT                                                             0x4
11728 #define TC_CFG_L2_STORE_POLICY1__POLICY_19__SHIFT                                                             0x6
11729 #define TC_CFG_L2_STORE_POLICY1__POLICY_20__SHIFT                                                             0x8
11730 #define TC_CFG_L2_STORE_POLICY1__POLICY_21__SHIFT                                                             0xa
11731 #define TC_CFG_L2_STORE_POLICY1__POLICY_22__SHIFT                                                             0xc
11732 #define TC_CFG_L2_STORE_POLICY1__POLICY_23__SHIFT                                                             0xe
11733 #define TC_CFG_L2_STORE_POLICY1__POLICY_24__SHIFT                                                             0x10
11734 #define TC_CFG_L2_STORE_POLICY1__POLICY_25__SHIFT                                                             0x12
11735 #define TC_CFG_L2_STORE_POLICY1__POLICY_26__SHIFT                                                             0x14
11736 #define TC_CFG_L2_STORE_POLICY1__POLICY_27__SHIFT                                                             0x16
11737 #define TC_CFG_L2_STORE_POLICY1__POLICY_28__SHIFT                                                             0x18
11738 #define TC_CFG_L2_STORE_POLICY1__POLICY_29__SHIFT                                                             0x1a
11739 #define TC_CFG_L2_STORE_POLICY1__POLICY_30__SHIFT                                                             0x1c
11740 #define TC_CFG_L2_STORE_POLICY1__POLICY_31__SHIFT                                                             0x1e
11741 #define TC_CFG_L2_STORE_POLICY1__POLICY_16_MASK                                                               0x00000003L
11742 #define TC_CFG_L2_STORE_POLICY1__POLICY_17_MASK                                                               0x0000000CL
11743 #define TC_CFG_L2_STORE_POLICY1__POLICY_18_MASK                                                               0x00000030L
11744 #define TC_CFG_L2_STORE_POLICY1__POLICY_19_MASK                                                               0x000000C0L
11745 #define TC_CFG_L2_STORE_POLICY1__POLICY_20_MASK                                                               0x00000300L
11746 #define TC_CFG_L2_STORE_POLICY1__POLICY_21_MASK                                                               0x00000C00L
11747 #define TC_CFG_L2_STORE_POLICY1__POLICY_22_MASK                                                               0x00003000L
11748 #define TC_CFG_L2_STORE_POLICY1__POLICY_23_MASK                                                               0x0000C000L
11749 #define TC_CFG_L2_STORE_POLICY1__POLICY_24_MASK                                                               0x00030000L
11750 #define TC_CFG_L2_STORE_POLICY1__POLICY_25_MASK                                                               0x000C0000L
11751 #define TC_CFG_L2_STORE_POLICY1__POLICY_26_MASK                                                               0x00300000L
11752 #define TC_CFG_L2_STORE_POLICY1__POLICY_27_MASK                                                               0x00C00000L
11753 #define TC_CFG_L2_STORE_POLICY1__POLICY_28_MASK                                                               0x03000000L
11754 #define TC_CFG_L2_STORE_POLICY1__POLICY_29_MASK                                                               0x0C000000L
11755 #define TC_CFG_L2_STORE_POLICY1__POLICY_30_MASK                                                               0x30000000L
11756 #define TC_CFG_L2_STORE_POLICY1__POLICY_31_MASK                                                               0xC0000000L
11757 //TC_CFG_L2_ATOMIC_POLICY
11758 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_0__SHIFT                                                              0x0
11759 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_1__SHIFT                                                              0x2
11760 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_2__SHIFT                                                              0x4
11761 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_3__SHIFT                                                              0x6
11762 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_4__SHIFT                                                              0x8
11763 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_5__SHIFT                                                              0xa
11764 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_6__SHIFT                                                              0xc
11765 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_7__SHIFT                                                              0xe
11766 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_8__SHIFT                                                              0x10
11767 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_9__SHIFT                                                              0x12
11768 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_10__SHIFT                                                             0x14
11769 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_11__SHIFT                                                             0x16
11770 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_12__SHIFT                                                             0x18
11771 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_13__SHIFT                                                             0x1a
11772 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_14__SHIFT                                                             0x1c
11773 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_15__SHIFT                                                             0x1e
11774 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_0_MASK                                                                0x00000003L
11775 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_1_MASK                                                                0x0000000CL
11776 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_2_MASK                                                                0x00000030L
11777 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_3_MASK                                                                0x000000C0L
11778 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_4_MASK                                                                0x00000300L
11779 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_5_MASK                                                                0x00000C00L
11780 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_6_MASK                                                                0x00003000L
11781 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_7_MASK                                                                0x0000C000L
11782 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_8_MASK                                                                0x00030000L
11783 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_9_MASK                                                                0x000C0000L
11784 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_10_MASK                                                               0x00300000L
11785 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_11_MASK                                                               0x00C00000L
11786 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_12_MASK                                                               0x03000000L
11787 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_13_MASK                                                               0x0C000000L
11788 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_14_MASK                                                               0x30000000L
11789 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_15_MASK                                                               0xC0000000L
11790 //TC_CFG_L1_VOLATILE
11791 #define TC_CFG_L1_VOLATILE__VOL__SHIFT                                                                        0x0
11792 #define TC_CFG_L1_VOLATILE__VOL_MASK                                                                          0x0000000FL
11793 //TC_CFG_L2_VOLATILE
11794 #define TC_CFG_L2_VOLATILE__VOL__SHIFT                                                                        0x0
11795 #define TC_CFG_L2_VOLATILE__VOL_MASK                                                                          0x0000000FL
11796 //TCP_UE_EDC_HI_REG
11797 #define TCP_UE_EDC_HI_REG__ECC__SHIFT                                                                         0x0
11798 #define TCP_UE_EDC_HI_REG__PARITY__SHIFT                                                                      0x1
11799 #define TCP_UE_EDC_HI_REG__ERR_INFO_VALID_FLAG__SHIFT                                                         0x2
11800 #define TCP_UE_EDC_HI_REG__ERR_INFO__SHIFT                                                                    0x3
11801 #define TCP_UE_EDC_HI_REG__UE_CNT__SHIFT                                                                      0x17
11802 #define TCP_UE_EDC_HI_REG__FED_CNT__SHIFT                                                                     0x1a
11803 #define TCP_UE_EDC_HI_REG__RESERVED__SHIFT                                                                    0x1d
11804 #define TCP_UE_EDC_HI_REG__ECC_MASK                                                                           0x00000001L
11805 #define TCP_UE_EDC_HI_REG__PARITY_MASK                                                                        0x00000002L
11806 #define TCP_UE_EDC_HI_REG__ERR_INFO_VALID_FLAG_MASK                                                           0x00000004L
11807 #define TCP_UE_EDC_HI_REG__ERR_INFO_MASK                                                                      0x007FFFF8L
11808 #define TCP_UE_EDC_HI_REG__UE_CNT_MASK                                                                        0x03800000L
11809 #define TCP_UE_EDC_HI_REG__FED_CNT_MASK                                                                       0x1C000000L
11810 #define TCP_UE_EDC_HI_REG__RESERVED_MASK                                                                      0xE0000000L
11811 //TCP_UE_EDC_LO_REG
11812 #define TCP_UE_EDC_LO_REG__STATUS_VALID_FLAG__SHIFT                                                           0x0
11813 #define TCP_UE_EDC_LO_REG__ADDRESS_INFO_VALID_FLAG__SHIFT                                                     0x1
11814 #define TCP_UE_EDC_LO_REG__ADDRESS__SHIFT                                                                     0x2
11815 #define TCP_UE_EDC_LO_REG__MEM_ID__SHIFT                                                                      0x18
11816 #define TCP_UE_EDC_LO_REG__STATUS_VALID_FLAG_MASK                                                             0x00000001L
11817 #define TCP_UE_EDC_LO_REG__ADDRESS_INFO_VALID_FLAG_MASK                                                       0x00000002L
11818 #define TCP_UE_EDC_LO_REG__ADDRESS_MASK                                                                       0x00FFFFFCL
11819 #define TCP_UE_EDC_LO_REG__MEM_ID_MASK                                                                        0xFF000000L
11820 //TCP_CE_EDC_HI_REG
11821 #define TCP_CE_EDC_HI_REG__ECC__SHIFT                                                                         0x0
11822 #define TCP_CE_EDC_HI_REG__ERR_INFO_VALID_FLAG__SHIFT                                                         0x2
11823 #define TCP_CE_EDC_HI_REG__ERR_INFO__SHIFT                                                                    0x3
11824 #define TCP_CE_EDC_HI_REG__CE_CNT__SHIFT                                                                      0x17
11825 #define TCP_CE_EDC_HI_REG__POISON__SHIFT                                                                      0x1a
11826 #define TCP_CE_EDC_HI_REG__RESERVED__SHIFT                                                                    0x1b
11827 #define TCP_CE_EDC_HI_REG__ECC_MASK                                                                           0x00000001L
11828 #define TCP_CE_EDC_HI_REG__ERR_INFO_VALID_FLAG_MASK                                                           0x00000004L
11829 #define TCP_CE_EDC_HI_REG__ERR_INFO_MASK                                                                      0x007FFFF8L
11830 #define TCP_CE_EDC_HI_REG__CE_CNT_MASK                                                                        0x03800000L
11831 #define TCP_CE_EDC_HI_REG__POISON_MASK                                                                        0x04000000L
11832 #define TCP_CE_EDC_HI_REG__RESERVED_MASK                                                                      0xF8000000L
11833 //TCP_CE_EDC_LO_REG
11834 #define TCP_CE_EDC_LO_REG__STATUS_VALID_FLAG__SHIFT                                                           0x0
11835 #define TCP_CE_EDC_LO_REG__ADDRESS_INFO_VALID_FLAG__SHIFT                                                     0x1
11836 #define TCP_CE_EDC_LO_REG__ADDRESS__SHIFT                                                                     0x2
11837 #define TCP_CE_EDC_LO_REG__MEM_ID__SHIFT                                                                      0x18
11838 #define TCP_CE_EDC_LO_REG__STATUS_VALID_FLAG_MASK                                                             0x00000001L
11839 #define TCP_CE_EDC_LO_REG__ADDRESS_INFO_VALID_FLAG_MASK                                                       0x00000002L
11840 #define TCP_CE_EDC_LO_REG__ADDRESS_MASK                                                                       0x00FFFFFCL
11841 #define TCP_CE_EDC_LO_REG__MEM_ID_MASK                                                                        0xFF000000L
11842 //TCI_UE_EDC_HI_REG
11843 #define TCI_UE_EDC_HI_REG__ECC__SHIFT                                                                         0x0
11844 #define TCI_UE_EDC_HI_REG__PARITY__SHIFT                                                                      0x1
11845 #define TCI_UE_EDC_HI_REG__ERR_INFO_VALID_FLAG__SHIFT                                                         0x2
11846 #define TCI_UE_EDC_HI_REG__ERR_INFO__SHIFT                                                                    0x3
11847 #define TCI_UE_EDC_HI_REG__UE_CNT__SHIFT                                                                      0x17
11848 #define TCI_UE_EDC_HI_REG__FED_CNT__SHIFT                                                                     0x1a
11849 #define TCI_UE_EDC_HI_REG__RESERVED__SHIFT                                                                    0x1d
11850 #define TCI_UE_EDC_HI_REG__ECC_MASK                                                                           0x00000001L
11851 #define TCI_UE_EDC_HI_REG__PARITY_MASK                                                                        0x00000002L
11852 #define TCI_UE_EDC_HI_REG__ERR_INFO_VALID_FLAG_MASK                                                           0x00000004L
11853 #define TCI_UE_EDC_HI_REG__ERR_INFO_MASK                                                                      0x007FFFF8L
11854 #define TCI_UE_EDC_HI_REG__UE_CNT_MASK                                                                        0x03800000L
11855 #define TCI_UE_EDC_HI_REG__FED_CNT_MASK                                                                       0x1C000000L
11856 #define TCI_UE_EDC_HI_REG__RESERVED_MASK                                                                      0xE0000000L
11857 //TCI_UE_EDC_LO_REG
11858 #define TCI_UE_EDC_LO_REG__STATUS_VALID_FLAG__SHIFT                                                           0x0
11859 #define TCI_UE_EDC_LO_REG__ADDRESS_INFO_VALID_FLAG__SHIFT                                                     0x1
11860 #define TCI_UE_EDC_LO_REG__ADDRESS__SHIFT                                                                     0x2
11861 #define TCI_UE_EDC_LO_REG__MEM_ID__SHIFT                                                                      0x18
11862 #define TCI_UE_EDC_LO_REG__STATUS_VALID_FLAG_MASK                                                             0x00000001L
11863 #define TCI_UE_EDC_LO_REG__ADDRESS_INFO_VALID_FLAG_MASK                                                       0x00000002L
11864 #define TCI_UE_EDC_LO_REG__ADDRESS_MASK                                                                       0x00FFFFFCL
11865 #define TCI_UE_EDC_LO_REG__MEM_ID_MASK                                                                        0xFF000000L
11866 //TCI_CE_EDC_HI_REG
11867 #define TCI_CE_EDC_HI_REG__ECC__SHIFT                                                                         0x0
11868 #define TCI_CE_EDC_HI_REG__ERR_INFO_VALID_FLAG__SHIFT                                                         0x2
11869 #define TCI_CE_EDC_HI_REG__ERR_INFO__SHIFT                                                                    0x3
11870 #define TCI_CE_EDC_HI_REG__CE_CNT__SHIFT                                                                      0x17
11871 #define TCI_CE_EDC_HI_REG__POISON__SHIFT                                                                      0x1a
11872 #define TCI_CE_EDC_HI_REG__RESERVED__SHIFT                                                                    0x1b
11873 #define TCI_CE_EDC_HI_REG__ECC_MASK                                                                           0x00000001L
11874 #define TCI_CE_EDC_HI_REG__ERR_INFO_VALID_FLAG_MASK                                                           0x00000004L
11875 #define TCI_CE_EDC_HI_REG__ERR_INFO_MASK                                                                      0x007FFFF8L
11876 #define TCI_CE_EDC_HI_REG__CE_CNT_MASK                                                                        0x03800000L
11877 #define TCI_CE_EDC_HI_REG__POISON_MASK                                                                        0x04000000L
11878 #define TCI_CE_EDC_HI_REG__RESERVED_MASK                                                                      0xF8000000L
11879 //TCI_CE_EDC_LO_REG
11880 #define TCI_CE_EDC_LO_REG__STATUS_VALID_FLAG__SHIFT                                                           0x0
11881 #define TCI_CE_EDC_LO_REG__ADDRESS_INFO_VALID_FLAG__SHIFT                                                     0x1
11882 #define TCI_CE_EDC_LO_REG__ADDRESS__SHIFT                                                                     0x2
11883 #define TCI_CE_EDC_LO_REG__MEM_ID__SHIFT                                                                      0x18
11884 #define TCI_CE_EDC_LO_REG__STATUS_VALID_FLAG_MASK                                                             0x00000001L
11885 #define TCI_CE_EDC_LO_REG__ADDRESS_INFO_VALID_FLAG_MASK                                                       0x00000002L
11886 #define TCI_CE_EDC_LO_REG__ADDRESS_MASK                                                                       0x00FFFFFCL
11887 #define TCI_CE_EDC_LO_REG__MEM_ID_MASK                                                                        0xFF000000L
11888 //TCI_MISC
11889 #define TCI_MISC__FGCG_REPEATER_DISABLE__SHIFT                                                                0x0
11890 #define TCI_MISC__LEGACY_MGCG_DISABLE__SHIFT                                                                  0x1
11891 #define TCI_MISC__FGCG_REPEATER_DISABLE_MASK                                                                  0x00000001L
11892 #define TCI_MISC__LEGACY_MGCG_DISABLE_MASK                                                                    0x00000002L
11893 //TCI_CNTL_3
11894 #define TCI_CNTL_3__DISABLE_DOUBLING_L2_BANDWIDTH__SHIFT                                                      0x0
11895 #define TCI_CNTL_3__COMBINING_DELAY_WINDOW__SHIFT                                                             0x2
11896 #define TCI_CNTL_3__CHICKEN_BIT_TCR_MGCG__SHIFT                                                               0x4
11897 #define TCI_CNTL_3__TCR_FGCG_REPEATER_DISABLE__SHIFT                                                          0x7
11898 #define TCI_CNTL_3__DISABLE_DOUBLING_L2_BANDWIDTH_MASK                                                        0x00000003L
11899 #define TCI_CNTL_3__COMBINING_DELAY_WINDOW_MASK                                                               0x0000000CL
11900 #define TCI_CNTL_3__CHICKEN_BIT_TCR_MGCG_MASK                                                                 0x00000070L
11901 #define TCI_CNTL_3__TCR_FGCG_REPEATER_DISABLE_MASK                                                            0x00000080L
11902 //TCI_DSM_CNTL
11903 #define TCI_DSM_CNTL__WRITE_RAM_IRRITATOR_DATA_SEL__SHIFT                                                     0x0
11904 #define TCI_DSM_CNTL__WRITE_RAM_IRRITATOR_SINGLE_WRITE__SHIFT                                                 0x2
11905 #define TCI_DSM_CNTL__WRITE_RAM_IRRITATOR_DATA_SEL_MASK                                                       0x00000003L
11906 #define TCI_DSM_CNTL__WRITE_RAM_IRRITATOR_SINGLE_WRITE_MASK                                                   0x00000004L
11907 //TCI_DSM_CNTL2
11908 #define TCI_DSM_CNTL2__WRITE_RAM_ENABLE_ERROR_INJECT__SHIFT                                                   0x0
11909 #define TCI_DSM_CNTL2__WRITE_RAM_SELECT_INJECT_DELAY__SHIFT                                                   0x2
11910 #define TCI_DSM_CNTL2__TCI_INJECT_DELAY__SHIFT                                                                0x1a
11911 #define TCI_DSM_CNTL2__WRITE_RAM_ENABLE_ERROR_INJECT_MASK                                                     0x00000003L
11912 #define TCI_DSM_CNTL2__WRITE_RAM_SELECT_INJECT_DELAY_MASK                                                     0x00000004L
11913 #define TCI_DSM_CNTL2__TCI_INJECT_DELAY_MASK                                                                  0xFC000000L
11914 //TCI_STATUS
11915 #define TCI_STATUS__TCI_BUSY__SHIFT                                                                           0x0
11916 #define TCI_STATUS__TCI_BUSY_MASK                                                                             0x00000001L
11917 //TCI_CNTL_1
11918 #define TCI_CNTL_1__WBINVL1_NUM_CYCLES__SHIFT                                                                 0x0
11919 #define TCI_CNTL_1__REQ_FIFO_DEPTH__SHIFT                                                                     0x10
11920 #define TCI_CNTL_1__WDATA_RAM_DEPTH__SHIFT                                                                    0x18
11921 #define TCI_CNTL_1__WBINVL1_NUM_CYCLES_MASK                                                                   0x0000FFFFL
11922 #define TCI_CNTL_1__REQ_FIFO_DEPTH_MASK                                                                       0x00FF0000L
11923 #define TCI_CNTL_1__WDATA_RAM_DEPTH_MASK                                                                      0xFF000000L
11924 //TCI_CNTL_2
11925 #define TCI_CNTL_2__L1_INVAL_ON_WBINVL2__SHIFT                                                                0x0
11926 #define TCI_CNTL_2__TCA_MAX_CREDIT__SHIFT                                                                     0x1
11927 #define TCI_CNTL_2__L1_INVAL_ON_WBINVL2_MASK                                                                  0x00000001L
11928 #define TCI_CNTL_2__TCA_MAX_CREDIT_MASK                                                                       0x000001FEL
11929 //TCC_CTRL
11930 #define TCC_CTRL__CACHE_SIZE__SHIFT                                                                           0x0
11931 #define TCC_CTRL__RATE__SHIFT                                                                                 0x2
11932 #define TCC_CTRL__WRITEBACK_MARGIN__SHIFT                                                                     0x4
11933 #define TCC_CTRL__SRC_FIFO_SIZE__SHIFT                                                                        0xc
11934 #define TCC_CTRL__LATENCY_FIFO_SIZE__SHIFT                                                                    0x10
11935 #define TCC_CTRL__LINEAR_SET_HASH__SHIFT                                                                      0x15
11936 #define TCC_CTRL__OUTPUT_FIFO_CLK_MODE__SHIFT                                                                 0x16
11937 #define TCC_CTRL__EXECUTE_CLK_MODE__SHIFT                                                                     0x17
11938 #define TCC_CTRL__RETURN_BUFFER_CLK_MODE__SHIFT                                                               0x19
11939 #define TCC_CTRL__SRC_FIFO_CLK_MODE__SHIFT                                                                    0x1a
11940 #define TCC_CTRL__MC_WRITE_CLK_MODE__SHIFT                                                                    0x1b
11941 #define TCC_CTRL__LATENCY_FIFO_CLK_MODE__SHIFT                                                                0x1c
11942 #define TCC_CTRL__DISABLE_SHARED_128B_READ_REQUEST__SHIFT                                                     0x1d
11943 #define TCC_CTRL__CACHE_SIZE_MASK                                                                             0x00000003L
11944 #define TCC_CTRL__RATE_MASK                                                                                   0x0000000CL
11945 #define TCC_CTRL__WRITEBACK_MARGIN_MASK                                                                       0x000000F0L
11946 #define TCC_CTRL__SRC_FIFO_SIZE_MASK                                                                          0x0000F000L
11947 #define TCC_CTRL__LATENCY_FIFO_SIZE_MASK                                                                      0x000F0000L
11948 #define TCC_CTRL__LINEAR_SET_HASH_MASK                                                                        0x00200000L
11949 #define TCC_CTRL__OUTPUT_FIFO_CLK_MODE_MASK                                                                   0x00400000L
11950 #define TCC_CTRL__EXECUTE_CLK_MODE_MASK                                                                       0x01800000L
11951 #define TCC_CTRL__RETURN_BUFFER_CLK_MODE_MASK                                                                 0x02000000L
11952 #define TCC_CTRL__SRC_FIFO_CLK_MODE_MASK                                                                      0x04000000L
11953 #define TCC_CTRL__MC_WRITE_CLK_MODE_MASK                                                                      0x08000000L
11954 #define TCC_CTRL__LATENCY_FIFO_CLK_MODE_MASK                                                                  0x10000000L
11955 #define TCC_CTRL__DISABLE_SHARED_128B_READ_REQUEST_MASK                                                       0x20000000L
11956 //TCC_CTRL2
11957 #define TCC_CTRL2__PROBE_FIFO_SIZE__SHIFT                                                                     0x0
11958 #define TCC_CTRL2__INF_NAN_CLAMP__SHIFT                                                                       0x10
11959 #define TCC_CTRL2__PROBE_FILTER_CTRL__SHIFT                                                                   0x11
11960 #define TCC_CTRL2__WAIT_CLK_STABLE_CNT__SHIFT                                                                 0x12
11961 #define TCC_CTRL2__TCC_TCX_REPEATER_FGCG_DISABLE__SHIFT                                                       0x17
11962 #define TCC_CTRL2__TCC_EA0_RDREQ_FGCG_DISABLE__SHIFT                                                          0x18
11963 #define TCC_CTRL2__TCC_EA0_WRREQ_FGCG_DISABLE__SHIFT                                                          0x19
11964 #define TCC_CTRL2__TCC_TCX_ACK_REPEATER_FGCG_DISABLE__SHIFT                                                   0x1a
11965 #define TCC_CTRL2__TCC_TCA_HOLE_REPEATER_FGCG_DISABLE__SHIFT                                                  0x1b
11966 #define TCC_CTRL2__TCC_TCA_RTN_REPEATER_FGCG_DISABLE__SHIFT                                                   0x1c
11967 #define TCC_CTRL2__USE_EA_EARLYWRRET_ON_WRITEBACK__SHIFT                                                      0x1d
11968 #define TCC_CTRL2__Enable_TCC_64K_2M_1G_1T_hash__SHIFT                                                        0x1e
11969 #define TCC_CTRL2__PROBE_FIFO_SIZE_MASK                                                                       0x0000000FL
11970 #define TCC_CTRL2__INF_NAN_CLAMP_MASK                                                                         0x00010000L
11971 #define TCC_CTRL2__PROBE_FILTER_CTRL_MASK                                                                     0x00020000L
11972 #define TCC_CTRL2__WAIT_CLK_STABLE_CNT_MASK                                                                   0x007C0000L
11973 #define TCC_CTRL2__TCC_TCX_REPEATER_FGCG_DISABLE_MASK                                                         0x00800000L
11974 #define TCC_CTRL2__TCC_EA0_RDREQ_FGCG_DISABLE_MASK                                                            0x01000000L
11975 #define TCC_CTRL2__TCC_EA0_WRREQ_FGCG_DISABLE_MASK                                                            0x02000000L
11976 #define TCC_CTRL2__TCC_TCX_ACK_REPEATER_FGCG_DISABLE_MASK                                                     0x04000000L
11977 #define TCC_CTRL2__TCC_TCA_HOLE_REPEATER_FGCG_DISABLE_MASK                                                    0x08000000L
11978 #define TCC_CTRL2__TCC_TCA_RTN_REPEATER_FGCG_DISABLE_MASK                                                     0x10000000L
11979 #define TCC_CTRL2__USE_EA_EARLYWRRET_ON_WRITEBACK_MASK                                                        0x20000000L
11980 #define TCC_CTRL2__Enable_TCC_64K_2M_1G_1T_hash_MASK                                                          0x40000000L
11981 //TCC_DSM_CNTL
11982 #define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_DATA_SEL__SHIFT                                                    0x0
11983 #define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_SINGLE_WRITE__SHIFT                                                0x2
11984 #define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_DATA_SEL__SHIFT                                           0x3
11985 #define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_SINGLE_WRITE__SHIFT                                       0x5
11986 #define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_DATA_SEL__SHIFT                                           0x6
11987 #define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_SINGLE_WRITE__SHIFT                                       0x8
11988 #define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_DATA_SEL__SHIFT                                           0x9
11989 #define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_SINGLE_WRITE__SHIFT                                       0xb
11990 #define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_DATA_SEL__SHIFT                                            0xc
11991 #define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_SINGLE_WRITE__SHIFT                                        0xe
11992 #define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_DATA_SEL__SHIFT                                            0xf
11993 #define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_SINGLE_WRITE__SHIFT                                        0x11
11994 #define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_DATA_SEL__SHIFT                                                 0x12
11995 #define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_SINGLE_WRITE__SHIFT                                             0x14
11996 #define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_DATA_SEL__SHIFT                                                  0x15
11997 #define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_SINGLE_WRITE__SHIFT                                              0x17
11998 #define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_DATA_SEL__SHIFT                                                    0x18
11999 #define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_SINGLE_WRITE__SHIFT                                                0x1a
12000 #define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_DATA_SEL__SHIFT                                               0x1b
12001 #define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_SINGLE_WRITE__SHIFT                                           0x1d
12002 #define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_DATA_SEL_MASK                                                      0x00000003L
12003 #define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_SINGLE_WRITE_MASK                                                  0x00000004L
12004 #define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_DATA_SEL_MASK                                             0x00000018L
12005 #define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_SINGLE_WRITE_MASK                                         0x00000020L
12006 #define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_DATA_SEL_MASK                                             0x000000C0L
12007 #define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_SINGLE_WRITE_MASK                                         0x00000100L
12008 #define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_DATA_SEL_MASK                                             0x00000600L
12009 #define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_SINGLE_WRITE_MASK                                         0x00000800L
12010 #define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_DATA_SEL_MASK                                              0x00003000L
12011 #define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_SINGLE_WRITE_MASK                                          0x00004000L
12012 #define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_DATA_SEL_MASK                                              0x00018000L
12013 #define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_SINGLE_WRITE_MASK                                          0x00020000L
12014 #define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_DATA_SEL_MASK                                                   0x000C0000L
12015 #define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_SINGLE_WRITE_MASK                                               0x00100000L
12016 #define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_DATA_SEL_MASK                                                    0x00600000L
12017 #define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_SINGLE_WRITE_MASK                                                0x00800000L
12018 #define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_DATA_SEL_MASK                                                      0x03000000L
12019 #define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_SINGLE_WRITE_MASK                                                  0x04000000L
12020 #define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_DATA_SEL_MASK                                                 0x18000000L
12021 #define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_SINGLE_WRITE_MASK                                             0x20000000L
12022 //TCC_DSM_CNTLA
12023 #define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_DATA_SEL__SHIFT                                                     0x0
12024 #define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT                                                 0x2
12025 #define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_DATA_SEL__SHIFT                                               0x3
12026 #define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT                                           0x5
12027 #define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_DATA_SEL__SHIFT                                                 0x6
12028 #define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_SINGLE_WRITE__SHIFT                                             0x8
12029 #define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_DATA_SEL__SHIFT                                             0x9
12030 #define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_SINGLE_WRITE__SHIFT                                         0xb
12031 #define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL__SHIFT                                        0xc
12032 #define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE__SHIFT                                    0xe
12033 #define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_DATA_SEL__SHIFT                                         0xf
12034 #define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT                                     0x11
12035 #define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_DATA_SEL__SHIFT                                                 0x12
12036 #define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT                                             0x14
12037 #define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_DATA_SEL__SHIFT                                                  0x15
12038 #define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_SINGLE_WRITE__SHIFT                                              0x17
12039 #define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_DATA_SEL__SHIFT                                               0x18
12040 #define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_SINGLE_WRITE__SHIFT                                           0x1a
12041 #define TCC_DSM_CNTLA__OUTPUT_FIFOS_IRRITATOR_DATA_SEL__SHIFT                                                 0x1b
12042 #define TCC_DSM_CNTLA__OUTPUT_FIFOS_IRRITATOR_SINGLE_WRITE__SHIFT                                             0x1d
12043 #define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_DATA_SEL_MASK                                                       0x00000003L
12044 #define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_SINGLE_WRITE_MASK                                                   0x00000004L
12045 #define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_DATA_SEL_MASK                                                 0x00000018L
12046 #define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_SINGLE_WRITE_MASK                                             0x00000020L
12047 #define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_DATA_SEL_MASK                                                   0x000000C0L
12048 #define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_SINGLE_WRITE_MASK                                               0x00000100L
12049 #define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_DATA_SEL_MASK                                               0x00000600L
12050 #define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_SINGLE_WRITE_MASK                                           0x00000800L
12051 #define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL_MASK                                          0x00003000L
12052 #define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE_MASK                                      0x00004000L
12053 #define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_DATA_SEL_MASK                                           0x00018000L
12054 #define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_SINGLE_WRITE_MASK                                       0x00020000L
12055 #define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_DATA_SEL_MASK                                                   0x000C0000L
12056 #define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_SINGLE_WRITE_MASK                                               0x00100000L
12057 #define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_DATA_SEL_MASK                                                    0x00600000L
12058 #define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_SINGLE_WRITE_MASK                                                0x00800000L
12059 #define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_DATA_SEL_MASK                                                 0x03000000L
12060 #define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_SINGLE_WRITE_MASK                                             0x04000000L
12061 #define TCC_DSM_CNTLA__OUTPUT_FIFOS_IRRITATOR_DATA_SEL_MASK                                                   0x18000000L
12062 #define TCC_DSM_CNTLA__OUTPUT_FIFOS_IRRITATOR_SINGLE_WRITE_MASK                                               0x20000000L
12063 //TCC_DSM_CNTL2
12064 #define TCC_DSM_CNTL2__CACHE_DATA_ENABLE_ERROR_INJECT__SHIFT                                                  0x0
12065 #define TCC_DSM_CNTL2__CACHE_DATA_SELECT_INJECT_DELAY__SHIFT                                                  0x2
12066 #define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_ENABLE_ERROR_INJECT__SHIFT                                         0x3
12067 #define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_SELECT_INJECT_DELAY__SHIFT                                         0x5
12068 #define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_ENABLE_ERROR_INJECT__SHIFT                                         0x6
12069 #define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_SELECT_INJECT_DELAY__SHIFT                                         0x8
12070 #define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_ENABLE_ERROR_INJECT__SHIFT                                         0x9
12071 #define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_SELECT_INJECT_DELAY__SHIFT                                         0xb
12072 #define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_ENABLE_ERROR_INJECT__SHIFT                                          0xc
12073 #define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_SELECT_INJECT_DELAY__SHIFT                                          0xe
12074 #define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_ENABLE_ERROR_INJECT__SHIFT                                          0xf
12075 #define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_SELECT_INJECT_DELAY__SHIFT                                          0x11
12076 #define TCC_DSM_CNTL2__HIGH_RATE_TAG_ENABLE_ERROR_INJECT__SHIFT                                               0x12
12077 #define TCC_DSM_CNTL2__HIGH_RATE_TAG_SELECT_INJECT_DELAY__SHIFT                                               0x14
12078 #define TCC_DSM_CNTL2__LOW_RATE_TAG_ENABLE_ERROR_INJECT__SHIFT                                                0x15
12079 #define TCC_DSM_CNTL2__LOW_RATE_TAG_SELECT_INJECT_DELAY__SHIFT                                                0x17
12080 #define TCC_DSM_CNTL2__INJECT_DELAY__SHIFT                                                                    0x1a
12081 #define TCC_DSM_CNTL2__CACHE_DATA_ENABLE_ERROR_INJECT_MASK                                                    0x00000003L
12082 #define TCC_DSM_CNTL2__CACHE_DATA_SELECT_INJECT_DELAY_MASK                                                    0x00000004L
12083 #define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_ENABLE_ERROR_INJECT_MASK                                           0x00000018L
12084 #define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_SELECT_INJECT_DELAY_MASK                                           0x00000020L
12085 #define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_ENABLE_ERROR_INJECT_MASK                                           0x000000C0L
12086 #define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_SELECT_INJECT_DELAY_MASK                                           0x00000100L
12087 #define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_ENABLE_ERROR_INJECT_MASK                                           0x00000600L
12088 #define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_SELECT_INJECT_DELAY_MASK                                           0x00000800L
12089 #define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_ENABLE_ERROR_INJECT_MASK                                            0x00003000L
12090 #define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_SELECT_INJECT_DELAY_MASK                                            0x00004000L
12091 #define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_ENABLE_ERROR_INJECT_MASK                                            0x00018000L
12092 #define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_SELECT_INJECT_DELAY_MASK                                            0x00020000L
12093 #define TCC_DSM_CNTL2__HIGH_RATE_TAG_ENABLE_ERROR_INJECT_MASK                                                 0x000C0000L
12094 #define TCC_DSM_CNTL2__HIGH_RATE_TAG_SELECT_INJECT_DELAY_MASK                                                 0x00100000L
12095 #define TCC_DSM_CNTL2__LOW_RATE_TAG_ENABLE_ERROR_INJECT_MASK                                                  0x00600000L
12096 #define TCC_DSM_CNTL2__LOW_RATE_TAG_SELECT_INJECT_DELAY_MASK                                                  0x00800000L
12097 #define TCC_DSM_CNTL2__INJECT_DELAY_MASK                                                                      0xFC000000L
12098 //TCC_DSM_CNTL2A
12099 #define TCC_DSM_CNTL2A__IN_USE_DEC_ENABLE_ERROR_INJECT__SHIFT                                                 0x0
12100 #define TCC_DSM_CNTL2A__IN_USE_DEC_SELECT_INJECT_DELAY__SHIFT                                                 0x2
12101 #define TCC_DSM_CNTL2A__IN_USE_TRANSFER_ENABLE_ERROR_INJECT__SHIFT                                            0x3
12102 #define TCC_DSM_CNTL2A__IN_USE_TRANSFER_SELECT_INJECT_DELAY__SHIFT                                            0x5
12103 #define TCC_DSM_CNTL2A__RETURN_DATA_ENABLE_ERROR_INJECT__SHIFT                                                0x6
12104 #define TCC_DSM_CNTL2A__RETURN_DATA_SELECT_INJECT_DELAY__SHIFT                                                0x8
12105 #define TCC_DSM_CNTL2A__RETURN_CONTROL_ENABLE_ERROR_INJECT__SHIFT                                             0x9
12106 #define TCC_DSM_CNTL2A__RETURN_CONTROL_SELECT_INJECT_DELAY__SHIFT                                             0xb
12107 #define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_ENABLE_ERROR_INJECT__SHIFT                                             0xc
12108 #define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_SELECT_INJECT_DELAY__SHIFT                                             0xe
12109 #define TCC_DSM_CNTL2A__WRITE_RETURN_ENABLE_ERROR_INJECT__SHIFT                                               0xf
12110 #define TCC_DSM_CNTL2A__WRITE_RETURN_SELECT_INJECT_DELAY__SHIFT                                               0x11
12111 #define TCC_DSM_CNTL2A__WRITE_CACHE_READ_ENABLE_ERROR_INJECT__SHIFT                                           0x12
12112 #define TCC_DSM_CNTL2A__WRITE_CACHE_READ_SELECT_INJECT_DELAY__SHIFT                                           0x14
12113 #define TCC_DSM_CNTL2A__SRC_FIFO_ENABLE_ERROR_INJECT__SHIFT                                                   0x15
12114 #define TCC_DSM_CNTL2A__SRC_FIFO_SELECT_INJECT_DELAY__SHIFT                                                   0x17
12115 #define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_ENABLE_ERROR_INJECT__SHIFT                                       0x18
12116 #define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_SELECT_INJECT_DELAY__SHIFT                                       0x1a
12117 #define TCC_DSM_CNTL2A__OUTPUT_FIFOS_ENABLE_ERROR_INJECT__SHIFT                                               0x1b
12118 #define TCC_DSM_CNTL2A__OUTPUT_FIFOS_SELECT_INJECT_DELAY__SHIFT                                               0x1d
12119 #define TCC_DSM_CNTL2A__IN_USE_DEC_ENABLE_ERROR_INJECT_MASK                                                   0x00000003L
12120 #define TCC_DSM_CNTL2A__IN_USE_DEC_SELECT_INJECT_DELAY_MASK                                                   0x00000004L
12121 #define TCC_DSM_CNTL2A__IN_USE_TRANSFER_ENABLE_ERROR_INJECT_MASK                                              0x00000018L
12122 #define TCC_DSM_CNTL2A__IN_USE_TRANSFER_SELECT_INJECT_DELAY_MASK                                              0x00000020L
12123 #define TCC_DSM_CNTL2A__RETURN_DATA_ENABLE_ERROR_INJECT_MASK                                                  0x000000C0L
12124 #define TCC_DSM_CNTL2A__RETURN_DATA_SELECT_INJECT_DELAY_MASK                                                  0x00000100L
12125 #define TCC_DSM_CNTL2A__RETURN_CONTROL_ENABLE_ERROR_INJECT_MASK                                               0x00000600L
12126 #define TCC_DSM_CNTL2A__RETURN_CONTROL_SELECT_INJECT_DELAY_MASK                                               0x00000800L
12127 #define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_ENABLE_ERROR_INJECT_MASK                                               0x00003000L
12128 #define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_SELECT_INJECT_DELAY_MASK                                               0x00004000L
12129 #define TCC_DSM_CNTL2A__WRITE_RETURN_ENABLE_ERROR_INJECT_MASK                                                 0x00018000L
12130 #define TCC_DSM_CNTL2A__WRITE_RETURN_SELECT_INJECT_DELAY_MASK                                                 0x00020000L
12131 #define TCC_DSM_CNTL2A__WRITE_CACHE_READ_ENABLE_ERROR_INJECT_MASK                                             0x000C0000L
12132 #define TCC_DSM_CNTL2A__WRITE_CACHE_READ_SELECT_INJECT_DELAY_MASK                                             0x00100000L
12133 #define TCC_DSM_CNTL2A__SRC_FIFO_ENABLE_ERROR_INJECT_MASK                                                     0x00600000L
12134 #define TCC_DSM_CNTL2A__SRC_FIFO_SELECT_INJECT_DELAY_MASK                                                     0x00800000L
12135 #define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_ENABLE_ERROR_INJECT_MASK                                         0x03000000L
12136 #define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_SELECT_INJECT_DELAY_MASK                                         0x04000000L
12137 #define TCC_DSM_CNTL2A__OUTPUT_FIFOS_ENABLE_ERROR_INJECT_MASK                                                 0x18000000L
12138 #define TCC_DSM_CNTL2A__OUTPUT_FIFOS_SELECT_INJECT_DELAY_MASK                                                 0x20000000L
12139 //TCC_DSM_CNTL2B
12140 #define TCC_DSM_CNTL2B__LATENCY_FIFO_ENABLE_ERROR_INJECT__SHIFT                                               0x0
12141 #define TCC_DSM_CNTL2B__LATENCY_FIFO_SELECT_INJECT_DELAY__SHIFT                                               0x2
12142 #define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT__SHIFT                                      0x3
12143 #define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_SELECT_INJECT_DELAY__SHIFT                                      0x5
12144 #define TCC_DSM_CNTL2B__WRITE_EARLY_RETURN_ENABLE_ERROR_INJECT__SHIFT                                         0xc
12145 #define TCC_DSM_CNTL2B__WRITE_EARLY_RETURN_SELECT_INJECT_DELAY__SHIFT                                         0xe
12146 #define TCC_DSM_CNTL2B__WRITE_EARLY_RETURN_IRRITATOR_DATA_SEL__SHIFT                                          0xf
12147 #define TCC_DSM_CNTL2B__WRITE_EARLY_RETURN_IRRITATOR_SINGLE_WRITE__SHIFT                                      0x11
12148 #define TCC_DSM_CNTL2B__RETURN_BUFFER_LEVEL_BUBBLE_THRESHOLD__SHIFT                                           0x12
12149 #define TCC_DSM_CNTL2B__LATENCY_FIFO_ENABLE_ERROR_INJECT_MASK                                                 0x00000003L
12150 #define TCC_DSM_CNTL2B__LATENCY_FIFO_SELECT_INJECT_DELAY_MASK                                                 0x00000004L
12151 #define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT_MASK                                        0x00000018L
12152 #define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_SELECT_INJECT_DELAY_MASK                                        0x00000020L
12153 #define TCC_DSM_CNTL2B__WRITE_EARLY_RETURN_ENABLE_ERROR_INJECT_MASK                                           0x00003000L
12154 #define TCC_DSM_CNTL2B__WRITE_EARLY_RETURN_SELECT_INJECT_DELAY_MASK                                           0x00004000L
12155 #define TCC_DSM_CNTL2B__WRITE_EARLY_RETURN_IRRITATOR_DATA_SEL_MASK                                            0x00018000L
12156 #define TCC_DSM_CNTL2B__WRITE_EARLY_RETURN_IRRITATOR_SINGLE_WRITE_MASK                                        0x00020000L
12157 #define TCC_DSM_CNTL2B__RETURN_BUFFER_LEVEL_BUBBLE_THRESHOLD_MASK                                             0x00FC0000L
12158 //TCC_WBINVL2
12159 #define TCC_WBINVL2__DONE__SHIFT                                                                              0x4
12160 #define TCC_WBINVL2__DONE_MASK                                                                                0x00000010L
12161 //TCC_SOFT_RESET
12162 #define TCC_SOFT_RESET__HALT_FOR_RESET__SHIFT                                                                 0x0
12163 #define TCC_SOFT_RESET__HALT_FOR_RESET_MASK                                                                   0x00000001L
12164 //TCC_DSM_CNTL3
12165 #define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_2_IRRITATOR_DATA_SEL__SHIFT                                          0x0
12166 #define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_2_IRRITATOR_SINGLE_WRITE__SHIFT                                      0x2
12167 #define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_3_IRRITATOR_DATA_SEL__SHIFT                                          0x3
12168 #define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_3_IRRITATOR_SINGLE_WRITE__SHIFT                                      0x5
12169 #define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_2_IRRITATOR_DATA_SEL__SHIFT                                          0x6
12170 #define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_2_IRRITATOR_SINGLE_WRITE__SHIFT                                      0x8
12171 #define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_3_IRRITATOR_DATA_SEL__SHIFT                                          0x9
12172 #define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_3_IRRITATOR_SINGLE_WRITE__SHIFT                                      0xb
12173 #define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_2_ENABLE_ERROR_INJECT__SHIFT                                         0xc
12174 #define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_2_SELECT_INJECT_DELAY__SHIFT                                         0xe
12175 #define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_3_ENABLE_ERROR_INJECT__SHIFT                                         0xf
12176 #define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_3_SELECT_INJECT_DELAY__SHIFT                                         0x11
12177 #define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_2_ENABLE_ERROR_INJECT__SHIFT                                         0x12
12178 #define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_2_SELECT_INJECT_DELAY__SHIFT                                         0x14
12179 #define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_3_ENABLE_ERROR_INJECT__SHIFT                                         0x15
12180 #define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_3_SELECT_INJECT_DELAY__SHIFT                                         0x17
12181 #define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_2_IRRITATOR_DATA_SEL_MASK                                            0x00000003L
12182 #define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_2_IRRITATOR_SINGLE_WRITE_MASK                                        0x00000004L
12183 #define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_3_IRRITATOR_DATA_SEL_MASK                                            0x00000018L
12184 #define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_3_IRRITATOR_SINGLE_WRITE_MASK                                        0x00000020L
12185 #define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_2_IRRITATOR_DATA_SEL_MASK                                            0x000000C0L
12186 #define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_2_IRRITATOR_SINGLE_WRITE_MASK                                        0x00000100L
12187 #define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_3_IRRITATOR_DATA_SEL_MASK                                            0x00000600L
12188 #define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_3_IRRITATOR_SINGLE_WRITE_MASK                                        0x00000800L
12189 #define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_2_ENABLE_ERROR_INJECT_MASK                                           0x00003000L
12190 #define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_2_SELECT_INJECT_DELAY_MASK                                           0x00004000L
12191 #define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_3_ENABLE_ERROR_INJECT_MASK                                           0x00018000L
12192 #define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_3_SELECT_INJECT_DELAY_MASK                                           0x00020000L
12193 #define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_2_ENABLE_ERROR_INJECT_MASK                                           0x000C0000L
12194 #define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_2_SELECT_INJECT_DELAY_MASK                                           0x00100000L
12195 #define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_3_ENABLE_ERROR_INJECT_MASK                                           0x00600000L
12196 #define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_3_SELECT_INJECT_DELAY_MASK                                           0x00800000L
12197 //TCA_CTRL
12198 #define TCA_CTRL__HOLE_TIMEOUT__SHIFT                                                                         0x0
12199 #define TCA_CTRL__RB_STILL_4_PHASE__SHIFT                                                                     0x4
12200 #define TCA_CTRL__RB_AS_TCI__SHIFT                                                                            0x5
12201 #define TCA_CTRL__DISABLE_UTCL2_PRIORITY__SHIFT                                                               0x6
12202 #define TCA_CTRL__DISABLE_RB_ONLY_TCA_ARBITER__SHIFT                                                          0x7
12203 #define TCA_CTRL__TCA_TCC_FGCG_DISABLE__SHIFT                                                                 0x8
12204 #define TCA_CTRL__TCA_TCA_FGCG_DISABLE__SHIFT                                                                 0x9
12205 #define TCA_CTRL__TCA_TCH_FGCG_DISABLE__SHIFT                                                                 0xa
12206 #define TCA_CTRL__TCA_TCX_FGCG_DISABLE__SHIFT                                                                 0xb
12207 #define TCA_CTRL__TCA_RANDOM_REVERSE_PRIORITY_ENABLE__SHIFT                                                   0xc
12208 #define TCA_CTRL__RTN_CREDIT_THRESHOLD__SHIFT                                                                 0xd
12209 #define TCA_CTRL__ACK_CREDIT_THRESHOLD__SHIFT                                                                 0x10
12210 #define TCA_CTRL__RTN_ARB_MODE__SHIFT                                                                         0x13
12211 #define TCA_CTRL__HOLE_ARB_SHARE_THRESHOLD__SHIFT                                                             0x18
12212 #define TCA_CTRL__HOLE_ARB_LANE_THRESHOLD__SHIFT                                                              0x1c
12213 #define TCA_CTRL__HOLE_TIMEOUT_MASK                                                                           0x0000000FL
12214 #define TCA_CTRL__RB_STILL_4_PHASE_MASK                                                                       0x00000010L
12215 #define TCA_CTRL__RB_AS_TCI_MASK                                                                              0x00000020L
12216 #define TCA_CTRL__DISABLE_UTCL2_PRIORITY_MASK                                                                 0x00000040L
12217 #define TCA_CTRL__DISABLE_RB_ONLY_TCA_ARBITER_MASK                                                            0x00000080L
12218 #define TCA_CTRL__TCA_TCC_FGCG_DISABLE_MASK                                                                   0x00000100L
12219 #define TCA_CTRL__TCA_TCA_FGCG_DISABLE_MASK                                                                   0x00000200L
12220 #define TCA_CTRL__TCA_TCH_FGCG_DISABLE_MASK                                                                   0x00000400L
12221 #define TCA_CTRL__TCA_TCX_FGCG_DISABLE_MASK                                                                   0x00000800L
12222 #define TCA_CTRL__TCA_RANDOM_REVERSE_PRIORITY_ENABLE_MASK                                                     0x00001000L
12223 #define TCA_CTRL__RTN_CREDIT_THRESHOLD_MASK                                                                   0x0000E000L
12224 #define TCA_CTRL__ACK_CREDIT_THRESHOLD_MASK                                                                   0x00070000L
12225 #define TCA_CTRL__RTN_ARB_MODE_MASK                                                                           0x00080000L
12226 #define TCA_CTRL__HOLE_ARB_SHARE_THRESHOLD_MASK                                                               0x07000000L
12227 #define TCA_CTRL__HOLE_ARB_LANE_THRESHOLD_MASK                                                                0x70000000L
12228 //TCA_BURST_MASK
12229 #define TCA_BURST_MASK__ADDR_MASK__SHIFT                                                                      0x0
12230 #define TCA_BURST_MASK__ADDR_MASK_MASK                                                                        0xFFFFFFFFL
12231 //TCA_BURST_CTRL
12232 #define TCA_BURST_CTRL__MAX_BURST__SHIFT                                                                      0x0
12233 #define TCA_BURST_CTRL__TCP_DISABLE__SHIFT                                                                    0x4
12234 #define TCA_BURST_CTRL__SQC_DISABLE__SHIFT                                                                    0x5
12235 #define TCA_BURST_CTRL__CPF_DISABLE__SHIFT                                                                    0x6
12236 #define TCA_BURST_CTRL__CPG_DISABLE__SHIFT                                                                    0x7
12237 #define TCA_BURST_CTRL__SQG_DISABLE__SHIFT                                                                    0xa
12238 #define TCA_BURST_CTRL__UTCL2_DISABLE__SHIFT                                                                  0xb
12239 #define TCA_BURST_CTRL__TPI_DISABLE__SHIFT                                                                    0xc
12240 #define TCA_BURST_CTRL__RLC_DISABLE__SHIFT                                                                    0xd
12241 #define TCA_BURST_CTRL__MAX_BURST_MASK                                                                        0x00000007L
12242 #define TCA_BURST_CTRL__TCP_DISABLE_MASK                                                                      0x00000010L
12243 #define TCA_BURST_CTRL__SQC_DISABLE_MASK                                                                      0x00000020L
12244 #define TCA_BURST_CTRL__CPF_DISABLE_MASK                                                                      0x00000040L
12245 #define TCA_BURST_CTRL__CPG_DISABLE_MASK                                                                      0x00000080L
12246 #define TCA_BURST_CTRL__SQG_DISABLE_MASK                                                                      0x00000400L
12247 #define TCA_BURST_CTRL__UTCL2_DISABLE_MASK                                                                    0x00000800L
12248 #define TCA_BURST_CTRL__TPI_DISABLE_MASK                                                                      0x00001000L
12249 #define TCA_BURST_CTRL__RLC_DISABLE_MASK                                                                      0x00002000L
12250 //TCA_DSM_CNTL
12251 #define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_DATA_SEL__SHIFT                                                 0x0
12252 #define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_SINGLE_WRITE__SHIFT                                             0x2
12253 #define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_DATA_SEL__SHIFT                                                  0x3
12254 #define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_SINGLE_WRITE__SHIFT                                              0x5
12255 #define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_DATA_SEL_MASK                                                   0x00000003L
12256 #define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_SINGLE_WRITE_MASK                                               0x00000004L
12257 #define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_DATA_SEL_MASK                                                    0x00000018L
12258 #define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_SINGLE_WRITE_MASK                                                0x00000020L
12259 //TCA_DSM_CNTL2
12260 #define TCA_DSM_CNTL2__HOLE_FIFO_SED_ENABLE_ERROR_INJECT__SHIFT                                               0x0
12261 #define TCA_DSM_CNTL2__HOLE_FIFO_SED_SELECT_INJECT_DELAY__SHIFT                                               0x2
12262 #define TCA_DSM_CNTL2__REQ_FIFO_SED_ENABLE_ERROR_INJECT__SHIFT                                                0x3
12263 #define TCA_DSM_CNTL2__REQ_FIFO_SED_SELECT_INJECT_DELAY__SHIFT                                                0x5
12264 #define TCA_DSM_CNTL2__INJECT_DELAY__SHIFT                                                                    0x1a
12265 #define TCA_DSM_CNTL2__HOLE_FIFO_SED_ENABLE_ERROR_INJECT_MASK                                                 0x00000003L
12266 #define TCA_DSM_CNTL2__HOLE_FIFO_SED_SELECT_INJECT_DELAY_MASK                                                 0x00000004L
12267 #define TCA_DSM_CNTL2__REQ_FIFO_SED_ENABLE_ERROR_INJECT_MASK                                                  0x00000018L
12268 #define TCA_DSM_CNTL2__REQ_FIFO_SED_SELECT_INJECT_DELAY_MASK                                                  0x00000020L
12269 #define TCA_DSM_CNTL2__INJECT_DELAY_MASK                                                                      0xFC000000L
12270 //TCX_CTRL
12271 #define TCX_CTRL__TCX_TCX_FGCG_DISABLE__SHIFT                                                                 0x0
12272 #define TCX_CTRL__TCX_TCR_FGCG_DISABLE__SHIFT                                                                 0x1
12273 #define TCX_CTRL__TCX_TCC_FGCG_DISABLE__SHIFT                                                                 0x2
12274 #define TCX_CTRL__TCX_TCX_FGCG_DISABLE_MASK                                                                   0x00000001L
12275 #define TCX_CTRL__TCX_TCR_FGCG_DISABLE_MASK                                                                   0x00000002L
12276 #define TCX_CTRL__TCX_TCC_FGCG_DISABLE_MASK                                                                   0x00000004L
12277 //TCX_DSM_CNTL
12278 #define TCX_DSM_CNTL__GROUP0_SED_IRRITATOR_DATA_SEL__SHIFT                                                    0x0
12279 #define TCX_DSM_CNTL__GROUP1_SED_IRRITATOR_DATA_SEL__SHIFT                                                    0x2
12280 #define TCX_DSM_CNTL__GROUP2_SED_IRRITATOR_DATA_SEL__SHIFT                                                    0x4
12281 #define TCX_DSM_CNTL__GROUP4_SED_IRRITATOR_DATA_SEL__SHIFT                                                    0x8
12282 #define TCX_DSM_CNTL__GROUP5_SED_IRRITATOR_DATA_SEL__SHIFT                                                    0xa
12283 #define TCX_DSM_CNTL__GROUP6_SED_IRRITATOR_DATA_SEL__SHIFT                                                    0xc
12284 #define TCX_DSM_CNTL__GROUP8_SED_IRRITATOR_DATA_SEL__SHIFT                                                    0x10
12285 #define TCX_DSM_CNTL__GROUP9_SED_IRRITATOR_DATA_SEL__SHIFT                                                    0x12
12286 #define TCX_DSM_CNTL__GROUP10_SED_IRRITATOR_DATA_SEL__SHIFT                                                   0x14
12287 #define TCX_DSM_CNTL__GROUP13_SED_IRRITATOR_DATA_SEL__SHIFT                                                   0x1a
12288 #define TCX_DSM_CNTL__GROUP14_SED_IRRITATOR_DATA_SEL__SHIFT                                                   0x1c
12289 #define TCX_DSM_CNTL__SED_IRRITATOR_SINGLE_WRITE__SHIFT                                                       0x1e
12290 #define TCX_DSM_CNTL__GROUP0_SED_IRRITATOR_DATA_SEL_MASK                                                      0x00000003L
12291 #define TCX_DSM_CNTL__GROUP1_SED_IRRITATOR_DATA_SEL_MASK                                                      0x0000000CL
12292 #define TCX_DSM_CNTL__GROUP2_SED_IRRITATOR_DATA_SEL_MASK                                                      0x00000030L
12293 #define TCX_DSM_CNTL__GROUP4_SED_IRRITATOR_DATA_SEL_MASK                                                      0x00000300L
12294 #define TCX_DSM_CNTL__GROUP5_SED_IRRITATOR_DATA_SEL_MASK                                                      0x00000C00L
12295 #define TCX_DSM_CNTL__GROUP6_SED_IRRITATOR_DATA_SEL_MASK                                                      0x00003000L
12296 #define TCX_DSM_CNTL__GROUP8_SED_IRRITATOR_DATA_SEL_MASK                                                      0x00030000L
12297 #define TCX_DSM_CNTL__GROUP9_SED_IRRITATOR_DATA_SEL_MASK                                                      0x000C0000L
12298 #define TCX_DSM_CNTL__GROUP10_SED_IRRITATOR_DATA_SEL_MASK                                                     0x00300000L
12299 #define TCX_DSM_CNTL__GROUP13_SED_IRRITATOR_DATA_SEL_MASK                                                     0x0C000000L
12300 #define TCX_DSM_CNTL__GROUP14_SED_IRRITATOR_DATA_SEL_MASK                                                     0x30000000L
12301 #define TCX_DSM_CNTL__SED_IRRITATOR_SINGLE_WRITE_MASK                                                         0x40000000L
12302 //TCX_DSM_CNTL2
12303 #define TCX_DSM_CNTL2__SED_ENABLE_ERROR_INJECT__SHIFT                                                         0x0
12304 #define TCX_DSM_CNTL2__SED_SELECT_INJECT_DELAY__SHIFT                                                         0x2
12305 #define TCX_DSM_CNTL2__INJECT_DELAY__SHIFT                                                                    0x1a
12306 #define TCX_DSM_CNTL2__SED_ENABLE_ERROR_INJECT_MASK                                                           0x00000003L
12307 #define TCX_DSM_CNTL2__SED_SELECT_INJECT_DELAY_MASK                                                           0x00000004L
12308 #define TCX_DSM_CNTL2__INJECT_DELAY_MASK                                                                      0xFC000000L
12309 //TCA_UE_ERR_STATUS_LO
12310 #define TCA_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT                                                    0x0
12311 #define TCA_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT                                                       0x1
12312 #define TCA_UE_ERR_STATUS_LO__ADDRESS__SHIFT                                                                  0x2
12313 #define TCA_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT                                                                0x18
12314 #define TCA_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK                                                      0x00000001L
12315 #define TCA_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK                                                         0x00000002L
12316 #define TCA_UE_ERR_STATUS_LO__ADDRESS_MASK                                                                    0x00FFFFFCL
12317 #define TCA_UE_ERR_STATUS_LO__MEMORY_ID_MASK                                                                  0xFF000000L
12318 //TCA_UE_ERR_STATUS_HI
12319 #define TCA_UE_ERR_STATUS_HI__ECC__SHIFT                                                                      0x0
12320 #define TCA_UE_ERR_STATUS_HI__PARITY__SHIFT                                                                   0x1
12321 #define TCA_UE_ERR_STATUS_HI__ERROR_INFO_VALID_FLAG__SHIFT                                                    0x2
12322 #define TCA_UE_ERR_STATUS_HI__ERROR_INFO__SHIFT                                                               0x3
12323 #define TCA_UE_ERR_STATUS_HI__UE_CNT__SHIFT                                                                   0x17
12324 #define TCA_UE_ERR_STATUS_HI__FED_CNT__SHIFT                                                                  0x1a
12325 #define TCA_UE_ERR_STATUS_HI__ECC_MASK                                                                        0x00000001L
12326 #define TCA_UE_ERR_STATUS_HI__PARITY_MASK                                                                     0x00000002L
12327 #define TCA_UE_ERR_STATUS_HI__ERROR_INFO_VALID_FLAG_MASK                                                      0x00000004L
12328 #define TCA_UE_ERR_STATUS_HI__ERROR_INFO_MASK                                                                 0x007FFFF8L
12329 #define TCA_UE_ERR_STATUS_HI__UE_CNT_MASK                                                                     0x03800000L
12330 #define TCA_UE_ERR_STATUS_HI__FED_CNT_MASK                                                                    0x1C000000L
12331 //TCX_UE_ERR_STATUS_LO
12332 #define TCX_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT                                                    0x0
12333 #define TCX_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT                                                       0x1
12334 #define TCX_UE_ERR_STATUS_LO__ADDRESS__SHIFT                                                                  0x2
12335 #define TCX_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT                                                                0x18
12336 #define TCX_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK                                                      0x00000001L
12337 #define TCX_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK                                                         0x00000002L
12338 #define TCX_UE_ERR_STATUS_LO__ADDRESS_MASK                                                                    0x00FFFFFCL
12339 #define TCX_UE_ERR_STATUS_LO__MEMORY_ID_MASK                                                                  0xFF000000L
12340 //TCX_UE_ERR_STATUS_HI
12341 #define TCX_UE_ERR_STATUS_HI__ECC__SHIFT                                                                      0x0
12342 #define TCX_UE_ERR_STATUS_HI__PARITY__SHIFT                                                                   0x1
12343 #define TCX_UE_ERR_STATUS_HI__ERROR_INFO_VALID_FLAG__SHIFT                                                    0x2
12344 #define TCX_UE_ERR_STATUS_HI__ERROR_INFO__SHIFT                                                               0x3
12345 #define TCX_UE_ERR_STATUS_HI__UE_CNT__SHIFT                                                                   0x17
12346 #define TCX_UE_ERR_STATUS_HI__FED_CNT__SHIFT                                                                  0x1a
12347 #define TCX_UE_ERR_STATUS_HI__ECC_MASK                                                                        0x00000001L
12348 #define TCX_UE_ERR_STATUS_HI__PARITY_MASK                                                                     0x00000002L
12349 #define TCX_UE_ERR_STATUS_HI__ERROR_INFO_VALID_FLAG_MASK                                                      0x00000004L
12350 #define TCX_UE_ERR_STATUS_HI__ERROR_INFO_MASK                                                                 0x007FFFF8L
12351 #define TCX_UE_ERR_STATUS_HI__UE_CNT_MASK                                                                     0x03800000L
12352 #define TCX_UE_ERR_STATUS_HI__FED_CNT_MASK                                                                    0x1C000000L
12353 //TCX_CE_ERR_STATUS_LO
12354 #define TCX_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT                                                    0x0
12355 #define TCX_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT                                                       0x1
12356 #define TCX_CE_ERR_STATUS_LO__ADDRESS__SHIFT                                                                  0x2
12357 #define TCX_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT                                                                0x18
12358 #define TCX_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK                                                      0x00000001L
12359 #define TCX_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK                                                         0x00000002L
12360 #define TCX_CE_ERR_STATUS_LO__ADDRESS_MASK                                                                    0x00FFFFFCL
12361 #define TCX_CE_ERR_STATUS_LO__MEMORY_ID_MASK                                                                  0xFF000000L
12362 //TCX_CE_ERR_STATUS_HI
12363 #define TCX_CE_ERR_STATUS_HI__ECC__SHIFT                                                                      0x0
12364 #define TCX_CE_ERR_STATUS_HI__ERROR_INFO_VALID_FLAG__SHIFT                                                    0x2
12365 #define TCX_CE_ERR_STATUS_HI__ERROR_INFO__SHIFT                                                               0x3
12366 #define TCX_CE_ERR_STATUS_HI__CE_CNT__SHIFT                                                                   0x17
12367 #define TCX_CE_ERR_STATUS_HI__POISON__SHIFT                                                                   0x1a
12368 #define TCX_CE_ERR_STATUS_HI__ECC_MASK                                                                        0x00000001L
12369 #define TCX_CE_ERR_STATUS_HI__ERROR_INFO_VALID_FLAG_MASK                                                      0x00000004L
12370 #define TCX_CE_ERR_STATUS_HI__ERROR_INFO_MASK                                                                 0x007FFFF8L
12371 #define TCX_CE_ERR_STATUS_HI__CE_CNT_MASK                                                                     0x03800000L
12372 #define TCX_CE_ERR_STATUS_HI__POISON_MASK                                                                     0x04000000L
12373 //TCC_UE_ERR_STATUS_LO
12374 #define TCC_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT                                                    0x0
12375 #define TCC_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT                                                       0x1
12376 #define TCC_UE_ERR_STATUS_LO__ADDRESS__SHIFT                                                                  0x2
12377 #define TCC_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT                                                                0x18
12378 #define TCC_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK                                                      0x00000001L
12379 #define TCC_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK                                                         0x00000002L
12380 #define TCC_UE_ERR_STATUS_LO__ADDRESS_MASK                                                                    0x00FFFFFCL
12381 #define TCC_UE_ERR_STATUS_LO__MEMORY_ID_MASK                                                                  0xFF000000L
12382 //TCC_UE_ERR_STATUS_HI
12383 #define TCC_UE_ERR_STATUS_HI__ECC__SHIFT                                                                      0x0
12384 #define TCC_UE_ERR_STATUS_HI__PARITY__SHIFT                                                                   0x1
12385 #define TCC_UE_ERR_STATUS_HI__ERROR_INFO_VALID_FLAG__SHIFT                                                    0x2
12386 #define TCC_UE_ERR_STATUS_HI__ERROR_INFO__SHIFT                                                               0x3
12387 #define TCC_UE_ERR_STATUS_HI__UE_CNT__SHIFT                                                                   0x17
12388 #define TCC_UE_ERR_STATUS_HI__FED_CNT__SHIFT                                                                  0x1a
12389 #define TCC_UE_ERR_STATUS_HI__ECC_MASK                                                                        0x00000001L
12390 #define TCC_UE_ERR_STATUS_HI__PARITY_MASK                                                                     0x00000002L
12391 #define TCC_UE_ERR_STATUS_HI__ERROR_INFO_VALID_FLAG_MASK                                                      0x00000004L
12392 #define TCC_UE_ERR_STATUS_HI__ERROR_INFO_MASK                                                                 0x007FFFF8L
12393 #define TCC_UE_ERR_STATUS_HI__UE_CNT_MASK                                                                     0x03800000L
12394 #define TCC_UE_ERR_STATUS_HI__FED_CNT_MASK                                                                    0x1C000000L
12395 //TCC_CE_ERR_STATUS_LO
12396 #define TCC_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT                                                    0x0
12397 #define TCC_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT                                                       0x1
12398 #define TCC_CE_ERR_STATUS_LO__ADDRESS__SHIFT                                                                  0x2
12399 #define TCC_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT                                                                0x18
12400 #define TCC_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK                                                      0x00000001L
12401 #define TCC_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK                                                         0x00000002L
12402 #define TCC_CE_ERR_STATUS_LO__ADDRESS_MASK                                                                    0x00FFFFFCL
12403 #define TCC_CE_ERR_STATUS_LO__MEMORY_ID_MASK                                                                  0xFF000000L
12404 //TCC_CE_ERR_STATUS_HI
12405 #define TCC_CE_ERR_STATUS_HI__ECC__SHIFT                                                                      0x0
12406 #define TCC_CE_ERR_STATUS_HI__ERROR_INFO_VALID_FLAG__SHIFT                                                    0x2
12407 #define TCC_CE_ERR_STATUS_HI__ERROR_INFO__SHIFT                                                               0x3
12408 #define TCC_CE_ERR_STATUS_HI__CE_CNT__SHIFT                                                                   0x17
12409 #define TCC_CE_ERR_STATUS_HI__POISON__SHIFT                                                                   0x1a
12410 #define TCC_CE_ERR_STATUS_HI__ECC_MASK                                                                        0x00000001L
12411 #define TCC_CE_ERR_STATUS_HI__ERROR_INFO_VALID_FLAG_MASK                                                      0x00000004L
12412 #define TCC_CE_ERR_STATUS_HI__ERROR_INFO_MASK                                                                 0x007FFFF8L
12413 #define TCC_CE_ERR_STATUS_HI__CE_CNT_MASK                                                                     0x03800000L
12414 #define TCC_CE_ERR_STATUS_HI__POISON_MASK                                                                     0x04000000L
12415 
12416 
12417 // addressBlock: xcd0_gc_shdec
12418 //SPI_SHADER_PGM_RSRC3_PS
12419 #define SPI_SHADER_PGM_RSRC3_PS__CU_EN__SHIFT                                                                 0x0
12420 #define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT__SHIFT                                                            0x10
12421 #define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD__SHIFT                                                    0x16
12422 #define SPI_SHADER_PGM_RSRC3_PS__SIMD_DISABLE__SHIFT                                                          0x1a
12423 #define SPI_SHADER_PGM_RSRC3_PS__CU_EN_MASK                                                                   0x0000FFFFL
12424 #define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT_MASK                                                              0x003F0000L
12425 #define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD_MASK                                                      0x03C00000L
12426 #define SPI_SHADER_PGM_RSRC3_PS__SIMD_DISABLE_MASK                                                            0x3C000000L
12427 //SPI_SHADER_PGM_LO_PS
12428 #define SPI_SHADER_PGM_LO_PS__MEM_BASE__SHIFT                                                                 0x0
12429 #define SPI_SHADER_PGM_LO_PS__MEM_BASE_MASK                                                                   0xFFFFFFFFL
12430 //SPI_SHADER_PGM_HI_PS
12431 #define SPI_SHADER_PGM_HI_PS__MEM_BASE__SHIFT                                                                 0x0
12432 #define SPI_SHADER_PGM_HI_PS__MEM_BASE_MASK                                                                   0xFFL
12433 //SPI_SHADER_PGM_RSRC1_PS
12434 #define SPI_SHADER_PGM_RSRC1_PS__VGPRS__SHIFT                                                                 0x0
12435 #define SPI_SHADER_PGM_RSRC1_PS__SGPRS__SHIFT                                                                 0x6
12436 #define SPI_SHADER_PGM_RSRC1_PS__PRIORITY__SHIFT                                                              0xa
12437 #define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE__SHIFT                                                            0xc
12438 #define SPI_SHADER_PGM_RSRC1_PS__PRIV__SHIFT                                                                  0x14
12439 #define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP__SHIFT                                                            0x15
12440 #define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE__SHIFT                                                            0x16
12441 #define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE__SHIFT                                                             0x17
12442 #define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE__SHIFT                                                      0x18
12443 #define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER__SHIFT                                                             0x1c
12444 #define SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL__SHIFT                                                             0x1d
12445 #define SPI_SHADER_PGM_RSRC1_PS__VGPRS_MASK                                                                   0x0000003FL
12446 #define SPI_SHADER_PGM_RSRC1_PS__SGPRS_MASK                                                                   0x000003C0L
12447 #define SPI_SHADER_PGM_RSRC1_PS__PRIORITY_MASK                                                                0x00000C00L
12448 #define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE_MASK                                                              0x000FF000L
12449 #define SPI_SHADER_PGM_RSRC1_PS__PRIV_MASK                                                                    0x00100000L
12450 #define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP_MASK                                                              0x00200000L
12451 #define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE_MASK                                                              0x00400000L
12452 #define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE_MASK                                                               0x00800000L
12453 #define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE_MASK                                                        0x01000000L
12454 #define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER_MASK                                                               0x10000000L
12455 #define SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL_MASK                                                               0x20000000L
12456 //SPI_SHADER_PGM_RSRC2_PS
12457 #define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN__SHIFT                                                            0x0
12458 #define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR__SHIFT                                                             0x1
12459 #define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT__SHIFT                                                          0x6
12460 #define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN__SHIFT                                                           0x7
12461 #define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE__SHIFT                                                        0x8
12462 #define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN__SHIFT                                                               0x10
12463 #define SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID__SHIFT                                                 0x19
12464 #define SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION__SHIFT                                              0x1a
12465 #define SPI_SHADER_PGM_RSRC2_PS__SKIP_USGPR0__SHIFT                                                           0x1b
12466 #define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB__SHIFT                                                         0x1c
12467 #define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN_MASK                                                              0x00000001L
12468 #define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MASK                                                               0x0000003EL
12469 #define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT_MASK                                                            0x00000040L
12470 #define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN_MASK                                                             0x00000080L
12471 #define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE_MASK                                                          0x0000FF00L
12472 #define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN_MASK                                                                 0x01FF0000L
12473 #define SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID_MASK                                                   0x02000000L
12474 #define SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION_MASK                                                0x04000000L
12475 #define SPI_SHADER_PGM_RSRC2_PS__SKIP_USGPR0_MASK                                                             0x08000000L
12476 #define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB_MASK                                                           0x10000000L
12477 //SPI_SHADER_USER_DATA_PS_0
12478 #define SPI_SHADER_USER_DATA_PS_0__DATA__SHIFT                                                                0x0
12479 #define SPI_SHADER_USER_DATA_PS_0__DATA_MASK                                                                  0xFFFFFFFFL
12480 //SPI_SHADER_USER_DATA_PS_1
12481 #define SPI_SHADER_USER_DATA_PS_1__DATA__SHIFT                                                                0x0
12482 #define SPI_SHADER_USER_DATA_PS_1__DATA_MASK                                                                  0xFFFFFFFFL
12483 //SPI_SHADER_USER_DATA_PS_2
12484 #define SPI_SHADER_USER_DATA_PS_2__DATA__SHIFT                                                                0x0
12485 #define SPI_SHADER_USER_DATA_PS_2__DATA_MASK                                                                  0xFFFFFFFFL
12486 //SPI_SHADER_USER_DATA_PS_3
12487 #define SPI_SHADER_USER_DATA_PS_3__DATA__SHIFT                                                                0x0
12488 #define SPI_SHADER_USER_DATA_PS_3__DATA_MASK                                                                  0xFFFFFFFFL
12489 //SPI_SHADER_USER_DATA_PS_4
12490 #define SPI_SHADER_USER_DATA_PS_4__DATA__SHIFT                                                                0x0
12491 #define SPI_SHADER_USER_DATA_PS_4__DATA_MASK                                                                  0xFFFFFFFFL
12492 //SPI_SHADER_USER_DATA_PS_5
12493 #define SPI_SHADER_USER_DATA_PS_5__DATA__SHIFT                                                                0x0
12494 #define SPI_SHADER_USER_DATA_PS_5__DATA_MASK                                                                  0xFFFFFFFFL
12495 //SPI_SHADER_USER_DATA_PS_6
12496 #define SPI_SHADER_USER_DATA_PS_6__DATA__SHIFT                                                                0x0
12497 #define SPI_SHADER_USER_DATA_PS_6__DATA_MASK                                                                  0xFFFFFFFFL
12498 //SPI_SHADER_USER_DATA_PS_7
12499 #define SPI_SHADER_USER_DATA_PS_7__DATA__SHIFT                                                                0x0
12500 #define SPI_SHADER_USER_DATA_PS_7__DATA_MASK                                                                  0xFFFFFFFFL
12501 //SPI_SHADER_USER_DATA_PS_8
12502 #define SPI_SHADER_USER_DATA_PS_8__DATA__SHIFT                                                                0x0
12503 #define SPI_SHADER_USER_DATA_PS_8__DATA_MASK                                                                  0xFFFFFFFFL
12504 //SPI_SHADER_USER_DATA_PS_9
12505 #define SPI_SHADER_USER_DATA_PS_9__DATA__SHIFT                                                                0x0
12506 #define SPI_SHADER_USER_DATA_PS_9__DATA_MASK                                                                  0xFFFFFFFFL
12507 //SPI_SHADER_USER_DATA_PS_10
12508 #define SPI_SHADER_USER_DATA_PS_10__DATA__SHIFT                                                               0x0
12509 #define SPI_SHADER_USER_DATA_PS_10__DATA_MASK                                                                 0xFFFFFFFFL
12510 //SPI_SHADER_USER_DATA_PS_11
12511 #define SPI_SHADER_USER_DATA_PS_11__DATA__SHIFT                                                               0x0
12512 #define SPI_SHADER_USER_DATA_PS_11__DATA_MASK                                                                 0xFFFFFFFFL
12513 //SPI_SHADER_USER_DATA_PS_12
12514 #define SPI_SHADER_USER_DATA_PS_12__DATA__SHIFT                                                               0x0
12515 #define SPI_SHADER_USER_DATA_PS_12__DATA_MASK                                                                 0xFFFFFFFFL
12516 //SPI_SHADER_USER_DATA_PS_13
12517 #define SPI_SHADER_USER_DATA_PS_13__DATA__SHIFT                                                               0x0
12518 #define SPI_SHADER_USER_DATA_PS_13__DATA_MASK                                                                 0xFFFFFFFFL
12519 //SPI_SHADER_USER_DATA_PS_14
12520 #define SPI_SHADER_USER_DATA_PS_14__DATA__SHIFT                                                               0x0
12521 #define SPI_SHADER_USER_DATA_PS_14__DATA_MASK                                                                 0xFFFFFFFFL
12522 //SPI_SHADER_USER_DATA_PS_15
12523 #define SPI_SHADER_USER_DATA_PS_15__DATA__SHIFT                                                               0x0
12524 #define SPI_SHADER_USER_DATA_PS_15__DATA_MASK                                                                 0xFFFFFFFFL
12525 //SPI_SHADER_USER_DATA_PS_16
12526 #define SPI_SHADER_USER_DATA_PS_16__DATA__SHIFT                                                               0x0
12527 #define SPI_SHADER_USER_DATA_PS_16__DATA_MASK                                                                 0xFFFFFFFFL
12528 //SPI_SHADER_USER_DATA_PS_17
12529 #define SPI_SHADER_USER_DATA_PS_17__DATA__SHIFT                                                               0x0
12530 #define SPI_SHADER_USER_DATA_PS_17__DATA_MASK                                                                 0xFFFFFFFFL
12531 //SPI_SHADER_USER_DATA_PS_18
12532 #define SPI_SHADER_USER_DATA_PS_18__DATA__SHIFT                                                               0x0
12533 #define SPI_SHADER_USER_DATA_PS_18__DATA_MASK                                                                 0xFFFFFFFFL
12534 //SPI_SHADER_USER_DATA_PS_19
12535 #define SPI_SHADER_USER_DATA_PS_19__DATA__SHIFT                                                               0x0
12536 #define SPI_SHADER_USER_DATA_PS_19__DATA_MASK                                                                 0xFFFFFFFFL
12537 //SPI_SHADER_USER_DATA_PS_20
12538 #define SPI_SHADER_USER_DATA_PS_20__DATA__SHIFT                                                               0x0
12539 #define SPI_SHADER_USER_DATA_PS_20__DATA_MASK                                                                 0xFFFFFFFFL
12540 //SPI_SHADER_USER_DATA_PS_21
12541 #define SPI_SHADER_USER_DATA_PS_21__DATA__SHIFT                                                               0x0
12542 #define SPI_SHADER_USER_DATA_PS_21__DATA_MASK                                                                 0xFFFFFFFFL
12543 //SPI_SHADER_USER_DATA_PS_22
12544 #define SPI_SHADER_USER_DATA_PS_22__DATA__SHIFT                                                               0x0
12545 #define SPI_SHADER_USER_DATA_PS_22__DATA_MASK                                                                 0xFFFFFFFFL
12546 //SPI_SHADER_USER_DATA_PS_23
12547 #define SPI_SHADER_USER_DATA_PS_23__DATA__SHIFT                                                               0x0
12548 #define SPI_SHADER_USER_DATA_PS_23__DATA_MASK                                                                 0xFFFFFFFFL
12549 //SPI_SHADER_USER_DATA_PS_24
12550 #define SPI_SHADER_USER_DATA_PS_24__DATA__SHIFT                                                               0x0
12551 #define SPI_SHADER_USER_DATA_PS_24__DATA_MASK                                                                 0xFFFFFFFFL
12552 //SPI_SHADER_USER_DATA_PS_25
12553 #define SPI_SHADER_USER_DATA_PS_25__DATA__SHIFT                                                               0x0
12554 #define SPI_SHADER_USER_DATA_PS_25__DATA_MASK                                                                 0xFFFFFFFFL
12555 //SPI_SHADER_USER_DATA_PS_26
12556 #define SPI_SHADER_USER_DATA_PS_26__DATA__SHIFT                                                               0x0
12557 #define SPI_SHADER_USER_DATA_PS_26__DATA_MASK                                                                 0xFFFFFFFFL
12558 //SPI_SHADER_USER_DATA_PS_27
12559 #define SPI_SHADER_USER_DATA_PS_27__DATA__SHIFT                                                               0x0
12560 #define SPI_SHADER_USER_DATA_PS_27__DATA_MASK                                                                 0xFFFFFFFFL
12561 //SPI_SHADER_USER_DATA_PS_28
12562 #define SPI_SHADER_USER_DATA_PS_28__DATA__SHIFT                                                               0x0
12563 #define SPI_SHADER_USER_DATA_PS_28__DATA_MASK                                                                 0xFFFFFFFFL
12564 //SPI_SHADER_USER_DATA_PS_29
12565 #define SPI_SHADER_USER_DATA_PS_29__DATA__SHIFT                                                               0x0
12566 #define SPI_SHADER_USER_DATA_PS_29__DATA_MASK                                                                 0xFFFFFFFFL
12567 //SPI_SHADER_USER_DATA_PS_30
12568 #define SPI_SHADER_USER_DATA_PS_30__DATA__SHIFT                                                               0x0
12569 #define SPI_SHADER_USER_DATA_PS_30__DATA_MASK                                                                 0xFFFFFFFFL
12570 //SPI_SHADER_USER_DATA_PS_31
12571 #define SPI_SHADER_USER_DATA_PS_31__DATA__SHIFT                                                               0x0
12572 #define SPI_SHADER_USER_DATA_PS_31__DATA_MASK                                                                 0xFFFFFFFFL
12573 //SPI_SHADER_PGM_RSRC3_VS
12574 #define SPI_SHADER_PGM_RSRC3_VS__CU_EN__SHIFT                                                                 0x0
12575 #define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT__SHIFT                                                            0x10
12576 #define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD__SHIFT                                                    0x16
12577 #define SPI_SHADER_PGM_RSRC3_VS__SIMD_DISABLE__SHIFT                                                          0x1a
12578 #define SPI_SHADER_PGM_RSRC3_VS__CU_EN_MASK                                                                   0x0000FFFFL
12579 #define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT_MASK                                                              0x003F0000L
12580 #define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD_MASK                                                      0x03C00000L
12581 #define SPI_SHADER_PGM_RSRC3_VS__SIMD_DISABLE_MASK                                                            0x3C000000L
12582 //SPI_SHADER_LATE_ALLOC_VS
12583 #define SPI_SHADER_LATE_ALLOC_VS__LIMIT__SHIFT                                                                0x0
12584 #define SPI_SHADER_LATE_ALLOC_VS__LIMIT_MASK                                                                  0x0000003FL
12585 //SPI_SHADER_PGM_LO_VS
12586 #define SPI_SHADER_PGM_LO_VS__MEM_BASE__SHIFT                                                                 0x0
12587 #define SPI_SHADER_PGM_LO_VS__MEM_BASE_MASK                                                                   0xFFFFFFFFL
12588 //SPI_SHADER_PGM_HI_VS
12589 #define SPI_SHADER_PGM_HI_VS__MEM_BASE__SHIFT                                                                 0x0
12590 #define SPI_SHADER_PGM_HI_VS__MEM_BASE_MASK                                                                   0xFFL
12591 //SPI_SHADER_PGM_RSRC1_VS
12592 #define SPI_SHADER_PGM_RSRC1_VS__VGPRS__SHIFT                                                                 0x0
12593 #define SPI_SHADER_PGM_RSRC1_VS__SGPRS__SHIFT                                                                 0x6
12594 #define SPI_SHADER_PGM_RSRC1_VS__PRIORITY__SHIFT                                                              0xa
12595 #define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE__SHIFT                                                            0xc
12596 #define SPI_SHADER_PGM_RSRC1_VS__PRIV__SHIFT                                                                  0x14
12597 #define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP__SHIFT                                                            0x15
12598 #define SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE__SHIFT                                                            0x16
12599 #define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE__SHIFT                                                             0x17
12600 #define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT__SHIFT                                                         0x18
12601 #define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE__SHIFT                                                       0x1a
12602 #define SPI_SHADER_PGM_RSRC1_VS__CDBG_USER__SHIFT                                                             0x1e
12603 #define SPI_SHADER_PGM_RSRC1_VS__FP16_OVFL__SHIFT                                                             0x1f
12604 #define SPI_SHADER_PGM_RSRC1_VS__VGPRS_MASK                                                                   0x0000003FL
12605 #define SPI_SHADER_PGM_RSRC1_VS__SGPRS_MASK                                                                   0x000003C0L
12606 #define SPI_SHADER_PGM_RSRC1_VS__PRIORITY_MASK                                                                0x00000C00L
12607 #define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE_MASK                                                              0x000FF000L
12608 #define SPI_SHADER_PGM_RSRC1_VS__PRIV_MASK                                                                    0x00100000L
12609 #define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP_MASK                                                              0x00200000L
12610 #define SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE_MASK                                                              0x00400000L
12611 #define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE_MASK                                                               0x00800000L
12612 #define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT_MASK                                                           0x03000000L
12613 #define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE_MASK                                                         0x04000000L
12614 #define SPI_SHADER_PGM_RSRC1_VS__CDBG_USER_MASK                                                               0x40000000L
12615 #define SPI_SHADER_PGM_RSRC1_VS__FP16_OVFL_MASK                                                               0x80000000L
12616 //SPI_SHADER_PGM_RSRC2_VS
12617 #define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN__SHIFT                                                            0x0
12618 #define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR__SHIFT                                                             0x1
12619 #define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT__SHIFT                                                          0x6
12620 #define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN__SHIFT                                                             0x7
12621 #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN__SHIFT                                                           0x8
12622 #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN__SHIFT                                                           0x9
12623 #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN__SHIFT                                                           0xa
12624 #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN__SHIFT                                                           0xb
12625 #define SPI_SHADER_PGM_RSRC2_VS__SO_EN__SHIFT                                                                 0xc
12626 #define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN__SHIFT                                                               0xd
12627 #define SPI_SHADER_PGM_RSRC2_VS__PC_BASE_EN__SHIFT                                                            0x16
12628 #define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN__SHIFT                                                      0x18
12629 #define SPI_SHADER_PGM_RSRC2_VS__SKIP_USGPR0__SHIFT                                                           0x1b
12630 #define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MSB__SHIFT                                                         0x1c
12631 #define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN_MASK                                                              0x00000001L
12632 #define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MASK                                                               0x0000003EL
12633 #define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT_MASK                                                            0x00000040L
12634 #define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN_MASK                                                               0x00000080L
12635 #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN_MASK                                                             0x00000100L
12636 #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN_MASK                                                             0x00000200L
12637 #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN_MASK                                                             0x00000400L
12638 #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN_MASK                                                             0x00000800L
12639 #define SPI_SHADER_PGM_RSRC2_VS__SO_EN_MASK                                                                   0x00001000L
12640 #define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN_MASK                                                                 0x003FE000L
12641 #define SPI_SHADER_PGM_RSRC2_VS__PC_BASE_EN_MASK                                                              0x00400000L
12642 #define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN_MASK                                                        0x01000000L
12643 #define SPI_SHADER_PGM_RSRC2_VS__SKIP_USGPR0_MASK                                                             0x08000000L
12644 #define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MSB_MASK                                                           0x10000000L
12645 //SPI_SHADER_USER_DATA_VS_0
12646 #define SPI_SHADER_USER_DATA_VS_0__DATA__SHIFT                                                                0x0
12647 #define SPI_SHADER_USER_DATA_VS_0__DATA_MASK                                                                  0xFFFFFFFFL
12648 //SPI_SHADER_USER_DATA_VS_1
12649 #define SPI_SHADER_USER_DATA_VS_1__DATA__SHIFT                                                                0x0
12650 #define SPI_SHADER_USER_DATA_VS_1__DATA_MASK                                                                  0xFFFFFFFFL
12651 //SPI_SHADER_USER_DATA_VS_2
12652 #define SPI_SHADER_USER_DATA_VS_2__DATA__SHIFT                                                                0x0
12653 #define SPI_SHADER_USER_DATA_VS_2__DATA_MASK                                                                  0xFFFFFFFFL
12654 //SPI_SHADER_USER_DATA_VS_3
12655 #define SPI_SHADER_USER_DATA_VS_3__DATA__SHIFT                                                                0x0
12656 #define SPI_SHADER_USER_DATA_VS_3__DATA_MASK                                                                  0xFFFFFFFFL
12657 //SPI_SHADER_USER_DATA_VS_4
12658 #define SPI_SHADER_USER_DATA_VS_4__DATA__SHIFT                                                                0x0
12659 #define SPI_SHADER_USER_DATA_VS_4__DATA_MASK                                                                  0xFFFFFFFFL
12660 //SPI_SHADER_USER_DATA_VS_5
12661 #define SPI_SHADER_USER_DATA_VS_5__DATA__SHIFT                                                                0x0
12662 #define SPI_SHADER_USER_DATA_VS_5__DATA_MASK                                                                  0xFFFFFFFFL
12663 //SPI_SHADER_USER_DATA_VS_6
12664 #define SPI_SHADER_USER_DATA_VS_6__DATA__SHIFT                                                                0x0
12665 #define SPI_SHADER_USER_DATA_VS_6__DATA_MASK                                                                  0xFFFFFFFFL
12666 //SPI_SHADER_USER_DATA_VS_7
12667 #define SPI_SHADER_USER_DATA_VS_7__DATA__SHIFT                                                                0x0
12668 #define SPI_SHADER_USER_DATA_VS_7__DATA_MASK                                                                  0xFFFFFFFFL
12669 //SPI_SHADER_USER_DATA_VS_8
12670 #define SPI_SHADER_USER_DATA_VS_8__DATA__SHIFT                                                                0x0
12671 #define SPI_SHADER_USER_DATA_VS_8__DATA_MASK                                                                  0xFFFFFFFFL
12672 //SPI_SHADER_USER_DATA_VS_9
12673 #define SPI_SHADER_USER_DATA_VS_9__DATA__SHIFT                                                                0x0
12674 #define SPI_SHADER_USER_DATA_VS_9__DATA_MASK                                                                  0xFFFFFFFFL
12675 //SPI_SHADER_USER_DATA_VS_10
12676 #define SPI_SHADER_USER_DATA_VS_10__DATA__SHIFT                                                               0x0
12677 #define SPI_SHADER_USER_DATA_VS_10__DATA_MASK                                                                 0xFFFFFFFFL
12678 //SPI_SHADER_USER_DATA_VS_11
12679 #define SPI_SHADER_USER_DATA_VS_11__DATA__SHIFT                                                               0x0
12680 #define SPI_SHADER_USER_DATA_VS_11__DATA_MASK                                                                 0xFFFFFFFFL
12681 //SPI_SHADER_USER_DATA_VS_12
12682 #define SPI_SHADER_USER_DATA_VS_12__DATA__SHIFT                                                               0x0
12683 #define SPI_SHADER_USER_DATA_VS_12__DATA_MASK                                                                 0xFFFFFFFFL
12684 //SPI_SHADER_USER_DATA_VS_13
12685 #define SPI_SHADER_USER_DATA_VS_13__DATA__SHIFT                                                               0x0
12686 #define SPI_SHADER_USER_DATA_VS_13__DATA_MASK                                                                 0xFFFFFFFFL
12687 //SPI_SHADER_USER_DATA_VS_14
12688 #define SPI_SHADER_USER_DATA_VS_14__DATA__SHIFT                                                               0x0
12689 #define SPI_SHADER_USER_DATA_VS_14__DATA_MASK                                                                 0xFFFFFFFFL
12690 //SPI_SHADER_USER_DATA_VS_15
12691 #define SPI_SHADER_USER_DATA_VS_15__DATA__SHIFT                                                               0x0
12692 #define SPI_SHADER_USER_DATA_VS_15__DATA_MASK                                                                 0xFFFFFFFFL
12693 //SPI_SHADER_USER_DATA_VS_16
12694 #define SPI_SHADER_USER_DATA_VS_16__DATA__SHIFT                                                               0x0
12695 #define SPI_SHADER_USER_DATA_VS_16__DATA_MASK                                                                 0xFFFFFFFFL
12696 //SPI_SHADER_USER_DATA_VS_17
12697 #define SPI_SHADER_USER_DATA_VS_17__DATA__SHIFT                                                               0x0
12698 #define SPI_SHADER_USER_DATA_VS_17__DATA_MASK                                                                 0xFFFFFFFFL
12699 //SPI_SHADER_USER_DATA_VS_18
12700 #define SPI_SHADER_USER_DATA_VS_18__DATA__SHIFT                                                               0x0
12701 #define SPI_SHADER_USER_DATA_VS_18__DATA_MASK                                                                 0xFFFFFFFFL
12702 //SPI_SHADER_USER_DATA_VS_19
12703 #define SPI_SHADER_USER_DATA_VS_19__DATA__SHIFT                                                               0x0
12704 #define SPI_SHADER_USER_DATA_VS_19__DATA_MASK                                                                 0xFFFFFFFFL
12705 //SPI_SHADER_USER_DATA_VS_20
12706 #define SPI_SHADER_USER_DATA_VS_20__DATA__SHIFT                                                               0x0
12707 #define SPI_SHADER_USER_DATA_VS_20__DATA_MASK                                                                 0xFFFFFFFFL
12708 //SPI_SHADER_USER_DATA_VS_21
12709 #define SPI_SHADER_USER_DATA_VS_21__DATA__SHIFT                                                               0x0
12710 #define SPI_SHADER_USER_DATA_VS_21__DATA_MASK                                                                 0xFFFFFFFFL
12711 //SPI_SHADER_USER_DATA_VS_22
12712 #define SPI_SHADER_USER_DATA_VS_22__DATA__SHIFT                                                               0x0
12713 #define SPI_SHADER_USER_DATA_VS_22__DATA_MASK                                                                 0xFFFFFFFFL
12714 //SPI_SHADER_USER_DATA_VS_23
12715 #define SPI_SHADER_USER_DATA_VS_23__DATA__SHIFT                                                               0x0
12716 #define SPI_SHADER_USER_DATA_VS_23__DATA_MASK                                                                 0xFFFFFFFFL
12717 //SPI_SHADER_USER_DATA_VS_24
12718 #define SPI_SHADER_USER_DATA_VS_24__DATA__SHIFT                                                               0x0
12719 #define SPI_SHADER_USER_DATA_VS_24__DATA_MASK                                                                 0xFFFFFFFFL
12720 //SPI_SHADER_USER_DATA_VS_25
12721 #define SPI_SHADER_USER_DATA_VS_25__DATA__SHIFT                                                               0x0
12722 #define SPI_SHADER_USER_DATA_VS_25__DATA_MASK                                                                 0xFFFFFFFFL
12723 //SPI_SHADER_USER_DATA_VS_26
12724 #define SPI_SHADER_USER_DATA_VS_26__DATA__SHIFT                                                               0x0
12725 #define SPI_SHADER_USER_DATA_VS_26__DATA_MASK                                                                 0xFFFFFFFFL
12726 //SPI_SHADER_USER_DATA_VS_27
12727 #define SPI_SHADER_USER_DATA_VS_27__DATA__SHIFT                                                               0x0
12728 #define SPI_SHADER_USER_DATA_VS_27__DATA_MASK                                                                 0xFFFFFFFFL
12729 //SPI_SHADER_USER_DATA_VS_28
12730 #define SPI_SHADER_USER_DATA_VS_28__DATA__SHIFT                                                               0x0
12731 #define SPI_SHADER_USER_DATA_VS_28__DATA_MASK                                                                 0xFFFFFFFFL
12732 //SPI_SHADER_USER_DATA_VS_29
12733 #define SPI_SHADER_USER_DATA_VS_29__DATA__SHIFT                                                               0x0
12734 #define SPI_SHADER_USER_DATA_VS_29__DATA_MASK                                                                 0xFFFFFFFFL
12735 //SPI_SHADER_USER_DATA_VS_30
12736 #define SPI_SHADER_USER_DATA_VS_30__DATA__SHIFT                                                               0x0
12737 #define SPI_SHADER_USER_DATA_VS_30__DATA_MASK                                                                 0xFFFFFFFFL
12738 //SPI_SHADER_USER_DATA_VS_31
12739 #define SPI_SHADER_USER_DATA_VS_31__DATA__SHIFT                                                               0x0
12740 #define SPI_SHADER_USER_DATA_VS_31__DATA_MASK                                                                 0xFFFFFFFFL
12741 //SPI_SHADER_PGM_RSRC2_GS_VS
12742 #define SPI_SHADER_PGM_RSRC2_GS_VS__SCRATCH_EN__SHIFT                                                         0x0
12743 #define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR__SHIFT                                                          0x1
12744 #define SPI_SHADER_PGM_RSRC2_GS_VS__TRAP_PRESENT__SHIFT                                                       0x6
12745 #define SPI_SHADER_PGM_RSRC2_GS_VS__EXCP_EN__SHIFT                                                            0x7
12746 #define SPI_SHADER_PGM_RSRC2_GS_VS__VGPR_COMP_CNT__SHIFT                                                      0x10
12747 #define SPI_SHADER_PGM_RSRC2_GS_VS__OC_LDS_EN__SHIFT                                                          0x12
12748 #define SPI_SHADER_PGM_RSRC2_GS_VS__LDS_SIZE__SHIFT                                                           0x13
12749 #define SPI_SHADER_PGM_RSRC2_GS_VS__SKIP_USGPR0__SHIFT                                                        0x1b
12750 #define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MSB__SHIFT                                                      0x1c
12751 #define SPI_SHADER_PGM_RSRC2_GS_VS__SCRATCH_EN_MASK                                                           0x00000001L
12752 #define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MASK                                                            0x0000003EL
12753 #define SPI_SHADER_PGM_RSRC2_GS_VS__TRAP_PRESENT_MASK                                                         0x00000040L
12754 #define SPI_SHADER_PGM_RSRC2_GS_VS__EXCP_EN_MASK                                                              0x0000FF80L
12755 #define SPI_SHADER_PGM_RSRC2_GS_VS__VGPR_COMP_CNT_MASK                                                        0x00030000L
12756 #define SPI_SHADER_PGM_RSRC2_GS_VS__OC_LDS_EN_MASK                                                            0x00040000L
12757 #define SPI_SHADER_PGM_RSRC2_GS_VS__LDS_SIZE_MASK                                                             0x07F80000L
12758 #define SPI_SHADER_PGM_RSRC2_GS_VS__SKIP_USGPR0_MASK                                                          0x08000000L
12759 #define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MSB_MASK                                                        0x10000000L
12760 //SPI_SHADER_PGM_RSRC4_GS
12761 #define SPI_SHADER_PGM_RSRC4_GS__GROUP_FIFO_DEPTH__SHIFT                                                      0x0
12762 #define SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS__SHIFT                                              0x7
12763 #define SPI_SHADER_PGM_RSRC4_GS__GROUP_FIFO_DEPTH_MASK                                                        0x0000007FL
12764 #define SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS_MASK                                                0x00003F80L
12765 //SPI_SHADER_USER_DATA_ADDR_LO_GS
12766 #define SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE__SHIFT                                                      0x0
12767 #define SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE_MASK                                                        0xFFFFFFFFL
12768 //SPI_SHADER_USER_DATA_ADDR_HI_GS
12769 #define SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE__SHIFT                                                      0x0
12770 #define SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE_MASK                                                        0xFFFFFFFFL
12771 //SPI_SHADER_PGM_LO_ES
12772 #define SPI_SHADER_PGM_LO_ES__MEM_BASE__SHIFT                                                                 0x0
12773 #define SPI_SHADER_PGM_LO_ES__MEM_BASE_MASK                                                                   0xFFFFFFFFL
12774 //SPI_SHADER_PGM_HI_ES
12775 #define SPI_SHADER_PGM_HI_ES__MEM_BASE__SHIFT                                                                 0x0
12776 #define SPI_SHADER_PGM_HI_ES__MEM_BASE_MASK                                                                   0xFFL
12777 //SPI_SHADER_PGM_RSRC3_GS
12778 #define SPI_SHADER_PGM_RSRC3_GS__CU_EN__SHIFT                                                                 0x0
12779 #define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT__SHIFT                                                            0x10
12780 #define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD__SHIFT                                                    0x16
12781 #define SPI_SHADER_PGM_RSRC3_GS__SIMD_DISABLE__SHIFT                                                          0x1a
12782 #define SPI_SHADER_PGM_RSRC3_GS__CU_EN_MASK                                                                   0x0000FFFFL
12783 #define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT_MASK                                                              0x003F0000L
12784 #define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD_MASK                                                      0x03C00000L
12785 #define SPI_SHADER_PGM_RSRC3_GS__SIMD_DISABLE_MASK                                                            0x3C000000L
12786 //SPI_SHADER_PGM_LO_GS
12787 #define SPI_SHADER_PGM_LO_GS__MEM_BASE__SHIFT                                                                 0x0
12788 #define SPI_SHADER_PGM_LO_GS__MEM_BASE_MASK                                                                   0xFFFFFFFFL
12789 //SPI_SHADER_PGM_HI_GS
12790 #define SPI_SHADER_PGM_HI_GS__MEM_BASE__SHIFT                                                                 0x0
12791 #define SPI_SHADER_PGM_HI_GS__MEM_BASE_MASK                                                                   0xFFL
12792 //SPI_SHADER_PGM_RSRC1_GS
12793 #define SPI_SHADER_PGM_RSRC1_GS__VGPRS__SHIFT                                                                 0x0
12794 #define SPI_SHADER_PGM_RSRC1_GS__SGPRS__SHIFT                                                                 0x6
12795 #define SPI_SHADER_PGM_RSRC1_GS__PRIORITY__SHIFT                                                              0xa
12796 #define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE__SHIFT                                                            0xc
12797 #define SPI_SHADER_PGM_RSRC1_GS__PRIV__SHIFT                                                                  0x14
12798 #define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP__SHIFT                                                            0x15
12799 #define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE__SHIFT                                                            0x16
12800 #define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE__SHIFT                                                             0x17
12801 #define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE__SHIFT                                                       0x18
12802 #define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER__SHIFT                                                             0x1c
12803 #define SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT__SHIFT                                                      0x1d
12804 #define SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL__SHIFT                                                             0x1f
12805 #define SPI_SHADER_PGM_RSRC1_GS__VGPRS_MASK                                                                   0x0000003FL
12806 #define SPI_SHADER_PGM_RSRC1_GS__SGPRS_MASK                                                                   0x000003C0L
12807 #define SPI_SHADER_PGM_RSRC1_GS__PRIORITY_MASK                                                                0x00000C00L
12808 #define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE_MASK                                                              0x000FF000L
12809 #define SPI_SHADER_PGM_RSRC1_GS__PRIV_MASK                                                                    0x00100000L
12810 #define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP_MASK                                                              0x00200000L
12811 #define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE_MASK                                                              0x00400000L
12812 #define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE_MASK                                                               0x00800000L
12813 #define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE_MASK                                                         0x01000000L
12814 #define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER_MASK                                                               0x10000000L
12815 #define SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT_MASK                                                        0x60000000L
12816 #define SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL_MASK                                                               0x80000000L
12817 //SPI_SHADER_PGM_RSRC2_GS
12818 #define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN__SHIFT                                                            0x0
12819 #define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR__SHIFT                                                             0x1
12820 #define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT__SHIFT                                                          0x6
12821 #define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN__SHIFT                                                               0x7
12822 #define SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT__SHIFT                                                      0x10
12823 #define SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN__SHIFT                                                             0x12
12824 #define SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE__SHIFT                                                              0x13
12825 #define SPI_SHADER_PGM_RSRC2_GS__SKIP_USGPR0__SHIFT                                                           0x1b
12826 #define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB__SHIFT                                                         0x1c
12827 #define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN_MASK                                                              0x00000001L
12828 #define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MASK                                                               0x0000003EL
12829 #define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT_MASK                                                            0x00000040L
12830 #define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN_MASK                                                                 0x0000FF80L
12831 #define SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT_MASK                                                        0x00030000L
12832 #define SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN_MASK                                                               0x00040000L
12833 #define SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE_MASK                                                                0x07F80000L
12834 #define SPI_SHADER_PGM_RSRC2_GS__SKIP_USGPR0_MASK                                                             0x08000000L
12835 #define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB_MASK                                                           0x10000000L
12836 //SPI_SHADER_USER_DATA_ES_0
12837 #define SPI_SHADER_USER_DATA_ES_0__DATA__SHIFT                                                                0x0
12838 #define SPI_SHADER_USER_DATA_ES_0__DATA_MASK                                                                  0xFFFFFFFFL
12839 //SPI_SHADER_USER_DATA_ES_1
12840 #define SPI_SHADER_USER_DATA_ES_1__DATA__SHIFT                                                                0x0
12841 #define SPI_SHADER_USER_DATA_ES_1__DATA_MASK                                                                  0xFFFFFFFFL
12842 //SPI_SHADER_USER_DATA_ES_2
12843 #define SPI_SHADER_USER_DATA_ES_2__DATA__SHIFT                                                                0x0
12844 #define SPI_SHADER_USER_DATA_ES_2__DATA_MASK                                                                  0xFFFFFFFFL
12845 //SPI_SHADER_USER_DATA_ES_3
12846 #define SPI_SHADER_USER_DATA_ES_3__DATA__SHIFT                                                                0x0
12847 #define SPI_SHADER_USER_DATA_ES_3__DATA_MASK                                                                  0xFFFFFFFFL
12848 //SPI_SHADER_USER_DATA_ES_4
12849 #define SPI_SHADER_USER_DATA_ES_4__DATA__SHIFT                                                                0x0
12850 #define SPI_SHADER_USER_DATA_ES_4__DATA_MASK                                                                  0xFFFFFFFFL
12851 //SPI_SHADER_USER_DATA_ES_5
12852 #define SPI_SHADER_USER_DATA_ES_5__DATA__SHIFT                                                                0x0
12853 #define SPI_SHADER_USER_DATA_ES_5__DATA_MASK                                                                  0xFFFFFFFFL
12854 //SPI_SHADER_USER_DATA_ES_6
12855 #define SPI_SHADER_USER_DATA_ES_6__DATA__SHIFT                                                                0x0
12856 #define SPI_SHADER_USER_DATA_ES_6__DATA_MASK                                                                  0xFFFFFFFFL
12857 //SPI_SHADER_USER_DATA_ES_7
12858 #define SPI_SHADER_USER_DATA_ES_7__DATA__SHIFT                                                                0x0
12859 #define SPI_SHADER_USER_DATA_ES_7__DATA_MASK                                                                  0xFFFFFFFFL
12860 //SPI_SHADER_USER_DATA_ES_8
12861 #define SPI_SHADER_USER_DATA_ES_8__DATA__SHIFT                                                                0x0
12862 #define SPI_SHADER_USER_DATA_ES_8__DATA_MASK                                                                  0xFFFFFFFFL
12863 //SPI_SHADER_USER_DATA_ES_9
12864 #define SPI_SHADER_USER_DATA_ES_9__DATA__SHIFT                                                                0x0
12865 #define SPI_SHADER_USER_DATA_ES_9__DATA_MASK                                                                  0xFFFFFFFFL
12866 //SPI_SHADER_USER_DATA_ES_10
12867 #define SPI_SHADER_USER_DATA_ES_10__DATA__SHIFT                                                               0x0
12868 #define SPI_SHADER_USER_DATA_ES_10__DATA_MASK                                                                 0xFFFFFFFFL
12869 //SPI_SHADER_USER_DATA_ES_11
12870 #define SPI_SHADER_USER_DATA_ES_11__DATA__SHIFT                                                               0x0
12871 #define SPI_SHADER_USER_DATA_ES_11__DATA_MASK                                                                 0xFFFFFFFFL
12872 //SPI_SHADER_USER_DATA_ES_12
12873 #define SPI_SHADER_USER_DATA_ES_12__DATA__SHIFT                                                               0x0
12874 #define SPI_SHADER_USER_DATA_ES_12__DATA_MASK                                                                 0xFFFFFFFFL
12875 //SPI_SHADER_USER_DATA_ES_13
12876 #define SPI_SHADER_USER_DATA_ES_13__DATA__SHIFT                                                               0x0
12877 #define SPI_SHADER_USER_DATA_ES_13__DATA_MASK                                                                 0xFFFFFFFFL
12878 //SPI_SHADER_USER_DATA_ES_14
12879 #define SPI_SHADER_USER_DATA_ES_14__DATA__SHIFT                                                               0x0
12880 #define SPI_SHADER_USER_DATA_ES_14__DATA_MASK                                                                 0xFFFFFFFFL
12881 //SPI_SHADER_USER_DATA_ES_15
12882 #define SPI_SHADER_USER_DATA_ES_15__DATA__SHIFT                                                               0x0
12883 #define SPI_SHADER_USER_DATA_ES_15__DATA_MASK                                                                 0xFFFFFFFFL
12884 //SPI_SHADER_USER_DATA_ES_16
12885 #define SPI_SHADER_USER_DATA_ES_16__DATA__SHIFT                                                               0x0
12886 #define SPI_SHADER_USER_DATA_ES_16__DATA_MASK                                                                 0xFFFFFFFFL
12887 //SPI_SHADER_USER_DATA_ES_17
12888 #define SPI_SHADER_USER_DATA_ES_17__DATA__SHIFT                                                               0x0
12889 #define SPI_SHADER_USER_DATA_ES_17__DATA_MASK                                                                 0xFFFFFFFFL
12890 //SPI_SHADER_USER_DATA_ES_18
12891 #define SPI_SHADER_USER_DATA_ES_18__DATA__SHIFT                                                               0x0
12892 #define SPI_SHADER_USER_DATA_ES_18__DATA_MASK                                                                 0xFFFFFFFFL
12893 //SPI_SHADER_USER_DATA_ES_19
12894 #define SPI_SHADER_USER_DATA_ES_19__DATA__SHIFT                                                               0x0
12895 #define SPI_SHADER_USER_DATA_ES_19__DATA_MASK                                                                 0xFFFFFFFFL
12896 //SPI_SHADER_USER_DATA_ES_20
12897 #define SPI_SHADER_USER_DATA_ES_20__DATA__SHIFT                                                               0x0
12898 #define SPI_SHADER_USER_DATA_ES_20__DATA_MASK                                                                 0xFFFFFFFFL
12899 //SPI_SHADER_USER_DATA_ES_21
12900 #define SPI_SHADER_USER_DATA_ES_21__DATA__SHIFT                                                               0x0
12901 #define SPI_SHADER_USER_DATA_ES_21__DATA_MASK                                                                 0xFFFFFFFFL
12902 //SPI_SHADER_USER_DATA_ES_22
12903 #define SPI_SHADER_USER_DATA_ES_22__DATA__SHIFT                                                               0x0
12904 #define SPI_SHADER_USER_DATA_ES_22__DATA_MASK                                                                 0xFFFFFFFFL
12905 //SPI_SHADER_USER_DATA_ES_23
12906 #define SPI_SHADER_USER_DATA_ES_23__DATA__SHIFT                                                               0x0
12907 #define SPI_SHADER_USER_DATA_ES_23__DATA_MASK                                                                 0xFFFFFFFFL
12908 //SPI_SHADER_USER_DATA_ES_24
12909 #define SPI_SHADER_USER_DATA_ES_24__DATA__SHIFT                                                               0x0
12910 #define SPI_SHADER_USER_DATA_ES_24__DATA_MASK                                                                 0xFFFFFFFFL
12911 //SPI_SHADER_USER_DATA_ES_25
12912 #define SPI_SHADER_USER_DATA_ES_25__DATA__SHIFT                                                               0x0
12913 #define SPI_SHADER_USER_DATA_ES_25__DATA_MASK                                                                 0xFFFFFFFFL
12914 //SPI_SHADER_USER_DATA_ES_26
12915 #define SPI_SHADER_USER_DATA_ES_26__DATA__SHIFT                                                               0x0
12916 #define SPI_SHADER_USER_DATA_ES_26__DATA_MASK                                                                 0xFFFFFFFFL
12917 //SPI_SHADER_USER_DATA_ES_27
12918 #define SPI_SHADER_USER_DATA_ES_27__DATA__SHIFT                                                               0x0
12919 #define SPI_SHADER_USER_DATA_ES_27__DATA_MASK                                                                 0xFFFFFFFFL
12920 //SPI_SHADER_USER_DATA_ES_28
12921 #define SPI_SHADER_USER_DATA_ES_28__DATA__SHIFT                                                               0x0
12922 #define SPI_SHADER_USER_DATA_ES_28__DATA_MASK                                                                 0xFFFFFFFFL
12923 //SPI_SHADER_USER_DATA_ES_29
12924 #define SPI_SHADER_USER_DATA_ES_29__DATA__SHIFT                                                               0x0
12925 #define SPI_SHADER_USER_DATA_ES_29__DATA_MASK                                                                 0xFFFFFFFFL
12926 //SPI_SHADER_USER_DATA_ES_30
12927 #define SPI_SHADER_USER_DATA_ES_30__DATA__SHIFT                                                               0x0
12928 #define SPI_SHADER_USER_DATA_ES_30__DATA_MASK                                                                 0xFFFFFFFFL
12929 //SPI_SHADER_USER_DATA_ES_31
12930 #define SPI_SHADER_USER_DATA_ES_31__DATA__SHIFT                                                               0x0
12931 #define SPI_SHADER_USER_DATA_ES_31__DATA_MASK                                                                 0xFFFFFFFFL
12932 //SPI_SHADER_PGM_RSRC4_HS
12933 #define SPI_SHADER_PGM_RSRC4_HS__GROUP_FIFO_DEPTH__SHIFT                                                      0x0
12934 #define SPI_SHADER_PGM_RSRC4_HS__GROUP_FIFO_DEPTH_MASK                                                        0x0000007FL
12935 //SPI_SHADER_USER_DATA_ADDR_LO_HS
12936 #define SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE__SHIFT                                                      0x0
12937 #define SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE_MASK                                                        0xFFFFFFFFL
12938 //SPI_SHADER_USER_DATA_ADDR_HI_HS
12939 #define SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE__SHIFT                                                      0x0
12940 #define SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE_MASK                                                        0xFFFFFFFFL
12941 //SPI_SHADER_PGM_LO_LS
12942 #define SPI_SHADER_PGM_LO_LS__MEM_BASE__SHIFT                                                                 0x0
12943 #define SPI_SHADER_PGM_LO_LS__MEM_BASE_MASK                                                                   0xFFFFFFFFL
12944 //SPI_SHADER_PGM_HI_LS
12945 #define SPI_SHADER_PGM_HI_LS__MEM_BASE__SHIFT                                                                 0x0
12946 #define SPI_SHADER_PGM_HI_LS__MEM_BASE_MASK                                                                   0xFFL
12947 //SPI_SHADER_PGM_RSRC3_HS
12948 #define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT__SHIFT                                                            0x0
12949 #define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD__SHIFT                                                    0x6
12950 #define SPI_SHADER_PGM_RSRC3_HS__SIMD_DISABLE__SHIFT                                                          0xa
12951 #define SPI_SHADER_PGM_RSRC3_HS__CU_EN__SHIFT                                                                 0x10
12952 #define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT_MASK                                                              0x0000003FL
12953 #define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD_MASK                                                      0x000003C0L
12954 #define SPI_SHADER_PGM_RSRC3_HS__SIMD_DISABLE_MASK                                                            0x00003C00L
12955 #define SPI_SHADER_PGM_RSRC3_HS__CU_EN_MASK                                                                   0xFFFF0000L
12956 //SPI_SHADER_PGM_LO_HS
12957 #define SPI_SHADER_PGM_LO_HS__MEM_BASE__SHIFT                                                                 0x0
12958 #define SPI_SHADER_PGM_LO_HS__MEM_BASE_MASK                                                                   0xFFFFFFFFL
12959 //SPI_SHADER_PGM_HI_HS
12960 #define SPI_SHADER_PGM_HI_HS__MEM_BASE__SHIFT                                                                 0x0
12961 #define SPI_SHADER_PGM_HI_HS__MEM_BASE_MASK                                                                   0xFFL
12962 //SPI_SHADER_PGM_RSRC1_HS
12963 #define SPI_SHADER_PGM_RSRC1_HS__VGPRS__SHIFT                                                                 0x0
12964 #define SPI_SHADER_PGM_RSRC1_HS__SGPRS__SHIFT                                                                 0x6
12965 #define SPI_SHADER_PGM_RSRC1_HS__PRIORITY__SHIFT                                                              0xa
12966 #define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE__SHIFT                                                            0xc
12967 #define SPI_SHADER_PGM_RSRC1_HS__PRIV__SHIFT                                                                  0x14
12968 #define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP__SHIFT                                                            0x15
12969 #define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE__SHIFT                                                            0x16
12970 #define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE__SHIFT                                                             0x17
12971 #define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER__SHIFT                                                             0x1b
12972 #define SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT__SHIFT                                                      0x1c
12973 #define SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL__SHIFT                                                             0x1e
12974 #define SPI_SHADER_PGM_RSRC1_HS__VGPRS_MASK                                                                   0x0000003FL
12975 #define SPI_SHADER_PGM_RSRC1_HS__SGPRS_MASK                                                                   0x000003C0L
12976 #define SPI_SHADER_PGM_RSRC1_HS__PRIORITY_MASK                                                                0x00000C00L
12977 #define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE_MASK                                                              0x000FF000L
12978 #define SPI_SHADER_PGM_RSRC1_HS__PRIV_MASK                                                                    0x00100000L
12979 #define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP_MASK                                                              0x00200000L
12980 #define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE_MASK                                                              0x00400000L
12981 #define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE_MASK                                                               0x00800000L
12982 #define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER_MASK                                                               0x08000000L
12983 #define SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT_MASK                                                        0x30000000L
12984 #define SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL_MASK                                                               0x40000000L
12985 //SPI_SHADER_PGM_RSRC2_HS
12986 #define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN__SHIFT                                                            0x0
12987 #define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR__SHIFT                                                             0x1
12988 #define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT__SHIFT                                                          0x6
12989 #define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN__SHIFT                                                               0x7
12990 #define SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE__SHIFT                                                              0x10
12991 #define SPI_SHADER_PGM_RSRC2_HS__SKIP_USGPR0__SHIFT                                                           0x1b
12992 #define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB__SHIFT                                                         0x1c
12993 #define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN_MASK                                                              0x00000001L
12994 #define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MASK                                                               0x0000003EL
12995 #define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT_MASK                                                            0x00000040L
12996 #define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN_MASK                                                                 0x0000FF80L
12997 #define SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE_MASK                                                                0x01FF0000L
12998 #define SPI_SHADER_PGM_RSRC2_HS__SKIP_USGPR0_MASK                                                             0x08000000L
12999 #define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB_MASK                                                           0x10000000L
13000 //SPI_SHADER_USER_DATA_LS_0
13001 #define SPI_SHADER_USER_DATA_LS_0__DATA__SHIFT                                                                0x0
13002 #define SPI_SHADER_USER_DATA_LS_0__DATA_MASK                                                                  0xFFFFFFFFL
13003 //SPI_SHADER_USER_DATA_LS_1
13004 #define SPI_SHADER_USER_DATA_LS_1__DATA__SHIFT                                                                0x0
13005 #define SPI_SHADER_USER_DATA_LS_1__DATA_MASK                                                                  0xFFFFFFFFL
13006 //SPI_SHADER_USER_DATA_LS_2
13007 #define SPI_SHADER_USER_DATA_LS_2__DATA__SHIFT                                                                0x0
13008 #define SPI_SHADER_USER_DATA_LS_2__DATA_MASK                                                                  0xFFFFFFFFL
13009 //SPI_SHADER_USER_DATA_LS_3
13010 #define SPI_SHADER_USER_DATA_LS_3__DATA__SHIFT                                                                0x0
13011 #define SPI_SHADER_USER_DATA_LS_3__DATA_MASK                                                                  0xFFFFFFFFL
13012 //SPI_SHADER_USER_DATA_LS_4
13013 #define SPI_SHADER_USER_DATA_LS_4__DATA__SHIFT                                                                0x0
13014 #define SPI_SHADER_USER_DATA_LS_4__DATA_MASK                                                                  0xFFFFFFFFL
13015 //SPI_SHADER_USER_DATA_LS_5
13016 #define SPI_SHADER_USER_DATA_LS_5__DATA__SHIFT                                                                0x0
13017 #define SPI_SHADER_USER_DATA_LS_5__DATA_MASK                                                                  0xFFFFFFFFL
13018 //SPI_SHADER_USER_DATA_LS_6
13019 #define SPI_SHADER_USER_DATA_LS_6__DATA__SHIFT                                                                0x0
13020 #define SPI_SHADER_USER_DATA_LS_6__DATA_MASK                                                                  0xFFFFFFFFL
13021 //SPI_SHADER_USER_DATA_LS_7
13022 #define SPI_SHADER_USER_DATA_LS_7__DATA__SHIFT                                                                0x0
13023 #define SPI_SHADER_USER_DATA_LS_7__DATA_MASK                                                                  0xFFFFFFFFL
13024 //SPI_SHADER_USER_DATA_LS_8
13025 #define SPI_SHADER_USER_DATA_LS_8__DATA__SHIFT                                                                0x0
13026 #define SPI_SHADER_USER_DATA_LS_8__DATA_MASK                                                                  0xFFFFFFFFL
13027 //SPI_SHADER_USER_DATA_LS_9
13028 #define SPI_SHADER_USER_DATA_LS_9__DATA__SHIFT                                                                0x0
13029 #define SPI_SHADER_USER_DATA_LS_9__DATA_MASK                                                                  0xFFFFFFFFL
13030 //SPI_SHADER_USER_DATA_LS_10
13031 #define SPI_SHADER_USER_DATA_LS_10__DATA__SHIFT                                                               0x0
13032 #define SPI_SHADER_USER_DATA_LS_10__DATA_MASK                                                                 0xFFFFFFFFL
13033 //SPI_SHADER_USER_DATA_LS_11
13034 #define SPI_SHADER_USER_DATA_LS_11__DATA__SHIFT                                                               0x0
13035 #define SPI_SHADER_USER_DATA_LS_11__DATA_MASK                                                                 0xFFFFFFFFL
13036 //SPI_SHADER_USER_DATA_LS_12
13037 #define SPI_SHADER_USER_DATA_LS_12__DATA__SHIFT                                                               0x0
13038 #define SPI_SHADER_USER_DATA_LS_12__DATA_MASK                                                                 0xFFFFFFFFL
13039 //SPI_SHADER_USER_DATA_LS_13
13040 #define SPI_SHADER_USER_DATA_LS_13__DATA__SHIFT                                                               0x0
13041 #define SPI_SHADER_USER_DATA_LS_13__DATA_MASK                                                                 0xFFFFFFFFL
13042 //SPI_SHADER_USER_DATA_LS_14
13043 #define SPI_SHADER_USER_DATA_LS_14__DATA__SHIFT                                                               0x0
13044 #define SPI_SHADER_USER_DATA_LS_14__DATA_MASK                                                                 0xFFFFFFFFL
13045 //SPI_SHADER_USER_DATA_LS_15
13046 #define SPI_SHADER_USER_DATA_LS_15__DATA__SHIFT                                                               0x0
13047 #define SPI_SHADER_USER_DATA_LS_15__DATA_MASK                                                                 0xFFFFFFFFL
13048 //SPI_SHADER_USER_DATA_LS_16
13049 #define SPI_SHADER_USER_DATA_LS_16__DATA__SHIFT                                                               0x0
13050 #define SPI_SHADER_USER_DATA_LS_16__DATA_MASK                                                                 0xFFFFFFFFL
13051 //SPI_SHADER_USER_DATA_LS_17
13052 #define SPI_SHADER_USER_DATA_LS_17__DATA__SHIFT                                                               0x0
13053 #define SPI_SHADER_USER_DATA_LS_17__DATA_MASK                                                                 0xFFFFFFFFL
13054 //SPI_SHADER_USER_DATA_LS_18
13055 #define SPI_SHADER_USER_DATA_LS_18__DATA__SHIFT                                                               0x0
13056 #define SPI_SHADER_USER_DATA_LS_18__DATA_MASK                                                                 0xFFFFFFFFL
13057 //SPI_SHADER_USER_DATA_LS_19
13058 #define SPI_SHADER_USER_DATA_LS_19__DATA__SHIFT                                                               0x0
13059 #define SPI_SHADER_USER_DATA_LS_19__DATA_MASK                                                                 0xFFFFFFFFL
13060 //SPI_SHADER_USER_DATA_LS_20
13061 #define SPI_SHADER_USER_DATA_LS_20__DATA__SHIFT                                                               0x0
13062 #define SPI_SHADER_USER_DATA_LS_20__DATA_MASK                                                                 0xFFFFFFFFL
13063 //SPI_SHADER_USER_DATA_LS_21
13064 #define SPI_SHADER_USER_DATA_LS_21__DATA__SHIFT                                                               0x0
13065 #define SPI_SHADER_USER_DATA_LS_21__DATA_MASK                                                                 0xFFFFFFFFL
13066 //SPI_SHADER_USER_DATA_LS_22
13067 #define SPI_SHADER_USER_DATA_LS_22__DATA__SHIFT                                                               0x0
13068 #define SPI_SHADER_USER_DATA_LS_22__DATA_MASK                                                                 0xFFFFFFFFL
13069 //SPI_SHADER_USER_DATA_LS_23
13070 #define SPI_SHADER_USER_DATA_LS_23__DATA__SHIFT                                                               0x0
13071 #define SPI_SHADER_USER_DATA_LS_23__DATA_MASK                                                                 0xFFFFFFFFL
13072 //SPI_SHADER_USER_DATA_LS_24
13073 #define SPI_SHADER_USER_DATA_LS_24__DATA__SHIFT                                                               0x0
13074 #define SPI_SHADER_USER_DATA_LS_24__DATA_MASK                                                                 0xFFFFFFFFL
13075 //SPI_SHADER_USER_DATA_LS_25
13076 #define SPI_SHADER_USER_DATA_LS_25__DATA__SHIFT                                                               0x0
13077 #define SPI_SHADER_USER_DATA_LS_25__DATA_MASK                                                                 0xFFFFFFFFL
13078 //SPI_SHADER_USER_DATA_LS_26
13079 #define SPI_SHADER_USER_DATA_LS_26__DATA__SHIFT                                                               0x0
13080 #define SPI_SHADER_USER_DATA_LS_26__DATA_MASK                                                                 0xFFFFFFFFL
13081 //SPI_SHADER_USER_DATA_LS_27
13082 #define SPI_SHADER_USER_DATA_LS_27__DATA__SHIFT                                                               0x0
13083 #define SPI_SHADER_USER_DATA_LS_27__DATA_MASK                                                                 0xFFFFFFFFL
13084 //SPI_SHADER_USER_DATA_LS_28
13085 #define SPI_SHADER_USER_DATA_LS_28__DATA__SHIFT                                                               0x0
13086 #define SPI_SHADER_USER_DATA_LS_28__DATA_MASK                                                                 0xFFFFFFFFL
13087 //SPI_SHADER_USER_DATA_LS_29
13088 #define SPI_SHADER_USER_DATA_LS_29__DATA__SHIFT                                                               0x0
13089 #define SPI_SHADER_USER_DATA_LS_29__DATA_MASK                                                                 0xFFFFFFFFL
13090 //SPI_SHADER_USER_DATA_LS_30
13091 #define SPI_SHADER_USER_DATA_LS_30__DATA__SHIFT                                                               0x0
13092 #define SPI_SHADER_USER_DATA_LS_30__DATA_MASK                                                                 0xFFFFFFFFL
13093 //SPI_SHADER_USER_DATA_LS_31
13094 #define SPI_SHADER_USER_DATA_LS_31__DATA__SHIFT                                                               0x0
13095 #define SPI_SHADER_USER_DATA_LS_31__DATA_MASK                                                                 0xFFFFFFFFL
13096 //SPI_SHADER_USER_DATA_COMMON_0
13097 #define SPI_SHADER_USER_DATA_COMMON_0__DATA__SHIFT                                                            0x0
13098 #define SPI_SHADER_USER_DATA_COMMON_0__DATA_MASK                                                              0xFFFFFFFFL
13099 //SPI_SHADER_USER_DATA_COMMON_1
13100 #define SPI_SHADER_USER_DATA_COMMON_1__DATA__SHIFT                                                            0x0
13101 #define SPI_SHADER_USER_DATA_COMMON_1__DATA_MASK                                                              0xFFFFFFFFL
13102 //SPI_SHADER_USER_DATA_COMMON_2
13103 #define SPI_SHADER_USER_DATA_COMMON_2__DATA__SHIFT                                                            0x0
13104 #define SPI_SHADER_USER_DATA_COMMON_2__DATA_MASK                                                              0xFFFFFFFFL
13105 //SPI_SHADER_USER_DATA_COMMON_3
13106 #define SPI_SHADER_USER_DATA_COMMON_3__DATA__SHIFT                                                            0x0
13107 #define SPI_SHADER_USER_DATA_COMMON_3__DATA_MASK                                                              0xFFFFFFFFL
13108 //SPI_SHADER_USER_DATA_COMMON_4
13109 #define SPI_SHADER_USER_DATA_COMMON_4__DATA__SHIFT                                                            0x0
13110 #define SPI_SHADER_USER_DATA_COMMON_4__DATA_MASK                                                              0xFFFFFFFFL
13111 //SPI_SHADER_USER_DATA_COMMON_5
13112 #define SPI_SHADER_USER_DATA_COMMON_5__DATA__SHIFT                                                            0x0
13113 #define SPI_SHADER_USER_DATA_COMMON_5__DATA_MASK                                                              0xFFFFFFFFL
13114 //SPI_SHADER_USER_DATA_COMMON_6
13115 #define SPI_SHADER_USER_DATA_COMMON_6__DATA__SHIFT                                                            0x0
13116 #define SPI_SHADER_USER_DATA_COMMON_6__DATA_MASK                                                              0xFFFFFFFFL
13117 //SPI_SHADER_USER_DATA_COMMON_7
13118 #define SPI_SHADER_USER_DATA_COMMON_7__DATA__SHIFT                                                            0x0
13119 #define SPI_SHADER_USER_DATA_COMMON_7__DATA_MASK                                                              0xFFFFFFFFL
13120 //SPI_SHADER_USER_DATA_COMMON_8
13121 #define SPI_SHADER_USER_DATA_COMMON_8__DATA__SHIFT                                                            0x0
13122 #define SPI_SHADER_USER_DATA_COMMON_8__DATA_MASK                                                              0xFFFFFFFFL
13123 //SPI_SHADER_USER_DATA_COMMON_9
13124 #define SPI_SHADER_USER_DATA_COMMON_9__DATA__SHIFT                                                            0x0
13125 #define SPI_SHADER_USER_DATA_COMMON_9__DATA_MASK                                                              0xFFFFFFFFL
13126 //SPI_SHADER_USER_DATA_COMMON_10
13127 #define SPI_SHADER_USER_DATA_COMMON_10__DATA__SHIFT                                                           0x0
13128 #define SPI_SHADER_USER_DATA_COMMON_10__DATA_MASK                                                             0xFFFFFFFFL
13129 //SPI_SHADER_USER_DATA_COMMON_11
13130 #define SPI_SHADER_USER_DATA_COMMON_11__DATA__SHIFT                                                           0x0
13131 #define SPI_SHADER_USER_DATA_COMMON_11__DATA_MASK                                                             0xFFFFFFFFL
13132 //SPI_SHADER_USER_DATA_COMMON_12
13133 #define SPI_SHADER_USER_DATA_COMMON_12__DATA__SHIFT                                                           0x0
13134 #define SPI_SHADER_USER_DATA_COMMON_12__DATA_MASK                                                             0xFFFFFFFFL
13135 //SPI_SHADER_USER_DATA_COMMON_13
13136 #define SPI_SHADER_USER_DATA_COMMON_13__DATA__SHIFT                                                           0x0
13137 #define SPI_SHADER_USER_DATA_COMMON_13__DATA_MASK                                                             0xFFFFFFFFL
13138 //SPI_SHADER_USER_DATA_COMMON_14
13139 #define SPI_SHADER_USER_DATA_COMMON_14__DATA__SHIFT                                                           0x0
13140 #define SPI_SHADER_USER_DATA_COMMON_14__DATA_MASK                                                             0xFFFFFFFFL
13141 //SPI_SHADER_USER_DATA_COMMON_15
13142 #define SPI_SHADER_USER_DATA_COMMON_15__DATA__SHIFT                                                           0x0
13143 #define SPI_SHADER_USER_DATA_COMMON_15__DATA_MASK                                                             0xFFFFFFFFL
13144 //SPI_SHADER_USER_DATA_COMMON_16
13145 #define SPI_SHADER_USER_DATA_COMMON_16__DATA__SHIFT                                                           0x0
13146 #define SPI_SHADER_USER_DATA_COMMON_16__DATA_MASK                                                             0xFFFFFFFFL
13147 //SPI_SHADER_USER_DATA_COMMON_17
13148 #define SPI_SHADER_USER_DATA_COMMON_17__DATA__SHIFT                                                           0x0
13149 #define SPI_SHADER_USER_DATA_COMMON_17__DATA_MASK                                                             0xFFFFFFFFL
13150 //SPI_SHADER_USER_DATA_COMMON_18
13151 #define SPI_SHADER_USER_DATA_COMMON_18__DATA__SHIFT                                                           0x0
13152 #define SPI_SHADER_USER_DATA_COMMON_18__DATA_MASK                                                             0xFFFFFFFFL
13153 //SPI_SHADER_USER_DATA_COMMON_19
13154 #define SPI_SHADER_USER_DATA_COMMON_19__DATA__SHIFT                                                           0x0
13155 #define SPI_SHADER_USER_DATA_COMMON_19__DATA_MASK                                                             0xFFFFFFFFL
13156 //SPI_SHADER_USER_DATA_COMMON_20
13157 #define SPI_SHADER_USER_DATA_COMMON_20__DATA__SHIFT                                                           0x0
13158 #define SPI_SHADER_USER_DATA_COMMON_20__DATA_MASK                                                             0xFFFFFFFFL
13159 //SPI_SHADER_USER_DATA_COMMON_21
13160 #define SPI_SHADER_USER_DATA_COMMON_21__DATA__SHIFT                                                           0x0
13161 #define SPI_SHADER_USER_DATA_COMMON_21__DATA_MASK                                                             0xFFFFFFFFL
13162 //SPI_SHADER_USER_DATA_COMMON_22
13163 #define SPI_SHADER_USER_DATA_COMMON_22__DATA__SHIFT                                                           0x0
13164 #define SPI_SHADER_USER_DATA_COMMON_22__DATA_MASK                                                             0xFFFFFFFFL
13165 //SPI_SHADER_USER_DATA_COMMON_23
13166 #define SPI_SHADER_USER_DATA_COMMON_23__DATA__SHIFT                                                           0x0
13167 #define SPI_SHADER_USER_DATA_COMMON_23__DATA_MASK                                                             0xFFFFFFFFL
13168 //SPI_SHADER_USER_DATA_COMMON_24
13169 #define SPI_SHADER_USER_DATA_COMMON_24__DATA__SHIFT                                                           0x0
13170 #define SPI_SHADER_USER_DATA_COMMON_24__DATA_MASK                                                             0xFFFFFFFFL
13171 //SPI_SHADER_USER_DATA_COMMON_25
13172 #define SPI_SHADER_USER_DATA_COMMON_25__DATA__SHIFT                                                           0x0
13173 #define SPI_SHADER_USER_DATA_COMMON_25__DATA_MASK                                                             0xFFFFFFFFL
13174 //SPI_SHADER_USER_DATA_COMMON_26
13175 #define SPI_SHADER_USER_DATA_COMMON_26__DATA__SHIFT                                                           0x0
13176 #define SPI_SHADER_USER_DATA_COMMON_26__DATA_MASK                                                             0xFFFFFFFFL
13177 //SPI_SHADER_USER_DATA_COMMON_27
13178 #define SPI_SHADER_USER_DATA_COMMON_27__DATA__SHIFT                                                           0x0
13179 #define SPI_SHADER_USER_DATA_COMMON_27__DATA_MASK                                                             0xFFFFFFFFL
13180 //SPI_SHADER_USER_DATA_COMMON_28
13181 #define SPI_SHADER_USER_DATA_COMMON_28__DATA__SHIFT                                                           0x0
13182 #define SPI_SHADER_USER_DATA_COMMON_28__DATA_MASK                                                             0xFFFFFFFFL
13183 //SPI_SHADER_USER_DATA_COMMON_29
13184 #define SPI_SHADER_USER_DATA_COMMON_29__DATA__SHIFT                                                           0x0
13185 #define SPI_SHADER_USER_DATA_COMMON_29__DATA_MASK                                                             0xFFFFFFFFL
13186 //SPI_SHADER_USER_DATA_COMMON_30
13187 #define SPI_SHADER_USER_DATA_COMMON_30__DATA__SHIFT                                                           0x0
13188 #define SPI_SHADER_USER_DATA_COMMON_30__DATA_MASK                                                             0xFFFFFFFFL
13189 //SPI_SHADER_USER_DATA_COMMON_31
13190 #define SPI_SHADER_USER_DATA_COMMON_31__DATA__SHIFT                                                           0x0
13191 #define SPI_SHADER_USER_DATA_COMMON_31__DATA_MASK                                                             0xFFFFFFFFL
13192 //COMPUTE_DISPATCH_INITIATOR
13193 #define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN__SHIFT                                                  0x0
13194 #define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN__SHIFT                                                      0x1
13195 #define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000__SHIFT                                                 0x2
13196 #define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL__SHIFT                                                0x3
13197 #define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE__SHIFT                                                0x4
13198 #define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS__SHIFT                                              0x5
13199 #define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE__SHIFT                                                         0x6
13200 #define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT                                                  0xa
13201 #define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL__SHIFT                                                  0xb
13202 #define COMPUTE_DISPATCH_INITIATOR__RESERVED__SHIFT                                                           0xc
13203 #define COMPUTE_DISPATCH_INITIATOR__RESTORE__SHIFT                                                            0xe
13204 #define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN_MASK                                                    0x00000001L
13205 #define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN_MASK                                                        0x00000002L
13206 #define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000_MASK                                                   0x00000004L
13207 #define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL_MASK                                                  0x00000008L
13208 #define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE_MASK                                                  0x00000010L
13209 #define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS_MASK                                                0x00000020L
13210 #define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE_MASK                                                           0x00000040L
13211 #define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL_MASK                                                    0x00000400L
13212 #define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL_MASK                                                    0x00000800L
13213 #define COMPUTE_DISPATCH_INITIATOR__RESERVED_MASK                                                             0x00001000L
13214 #define COMPUTE_DISPATCH_INITIATOR__RESTORE_MASK                                                              0x00004000L
13215 //COMPUTE_DIM_X
13216 #define COMPUTE_DIM_X__SIZE__SHIFT                                                                            0x0
13217 #define COMPUTE_DIM_X__SIZE_MASK                                                                              0xFFFFFFFFL
13218 //COMPUTE_DIM_Y
13219 #define COMPUTE_DIM_Y__SIZE__SHIFT                                                                            0x0
13220 #define COMPUTE_DIM_Y__SIZE_MASK                                                                              0xFFFFFFFFL
13221 //COMPUTE_DIM_Z
13222 #define COMPUTE_DIM_Z__SIZE__SHIFT                                                                            0x0
13223 #define COMPUTE_DIM_Z__SIZE_MASK                                                                              0xFFFFFFFFL
13224 //COMPUTE_START_X
13225 #define COMPUTE_START_X__START__SHIFT                                                                         0x0
13226 #define COMPUTE_START_X__START_MASK                                                                           0xFFFFFFFFL
13227 //COMPUTE_START_Y
13228 #define COMPUTE_START_Y__START__SHIFT                                                                         0x0
13229 #define COMPUTE_START_Y__START_MASK                                                                           0xFFFFFFFFL
13230 //COMPUTE_START_Z
13231 #define COMPUTE_START_Z__START__SHIFT                                                                         0x0
13232 #define COMPUTE_START_Z__START_MASK                                                                           0xFFFFFFFFL
13233 //COMPUTE_NUM_THREAD_X
13234 #define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL__SHIFT                                                          0x0
13235 #define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL__SHIFT                                                       0x10
13236 #define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL_MASK                                                            0x0000FFFFL
13237 #define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL_MASK                                                         0xFFFF0000L
13238 //COMPUTE_NUM_THREAD_Y
13239 #define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL__SHIFT                                                          0x0
13240 #define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL__SHIFT                                                       0x10
13241 #define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL_MASK                                                            0x0000FFFFL
13242 #define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL_MASK                                                         0xFFFF0000L
13243 //COMPUTE_NUM_THREAD_Z
13244 #define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL__SHIFT                                                          0x0
13245 #define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL__SHIFT                                                       0x10
13246 #define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL_MASK                                                            0x0000FFFFL
13247 #define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL_MASK                                                         0xFFFF0000L
13248 //COMPUTE_PIPELINESTAT_ENABLE
13249 #define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE__SHIFT                                               0x0
13250 #define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE_MASK                                                 0x00000001L
13251 //COMPUTE_PERFCOUNT_ENABLE
13252 #define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE__SHIFT                                                     0x0
13253 #define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE_MASK                                                       0x00000001L
13254 //COMPUTE_PGM_LO
13255 #define COMPUTE_PGM_LO__DATA__SHIFT                                                                           0x0
13256 #define COMPUTE_PGM_LO__DATA_MASK                                                                             0xFFFFFFFFL
13257 //COMPUTE_PGM_HI
13258 #define COMPUTE_PGM_HI__DATA__SHIFT                                                                           0x0
13259 #define COMPUTE_PGM_HI__DATA_MASK                                                                             0x000000FFL
13260 //COMPUTE_DISPATCH_PKT_ADDR_LO
13261 #define COMPUTE_DISPATCH_PKT_ADDR_LO__DATA__SHIFT                                                             0x0
13262 #define COMPUTE_DISPATCH_PKT_ADDR_LO__DATA_MASK                                                               0xFFFFFFFFL
13263 //COMPUTE_DISPATCH_PKT_ADDR_HI
13264 #define COMPUTE_DISPATCH_PKT_ADDR_HI__DATA__SHIFT                                                             0x0
13265 #define COMPUTE_DISPATCH_PKT_ADDR_HI__DATA_MASK                                                               0x000000FFL
13266 //COMPUTE_DISPATCH_SCRATCH_BASE_LO
13267 #define COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA__SHIFT                                                         0x0
13268 #define COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA_MASK                                                           0xFFFFFFFFL
13269 //COMPUTE_DISPATCH_SCRATCH_BASE_HI
13270 #define COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA__SHIFT                                                         0x0
13271 #define COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA_MASK                                                           0x000000FFL
13272 //COMPUTE_PGM_RSRC1
13273 #define COMPUTE_PGM_RSRC1__VGPRS__SHIFT                                                                       0x0
13274 #define COMPUTE_PGM_RSRC1__SGPRS__SHIFT                                                                       0x6
13275 #define COMPUTE_PGM_RSRC1__PRIORITY__SHIFT                                                                    0xa
13276 #define COMPUTE_PGM_RSRC1__FLOAT_MODE__SHIFT                                                                  0xc
13277 #define COMPUTE_PGM_RSRC1__PRIV__SHIFT                                                                        0x14
13278 #define COMPUTE_PGM_RSRC1__DX10_CLAMP__SHIFT                                                                  0x15
13279 #define COMPUTE_PGM_RSRC1__DEBUG_MODE__SHIFT                                                                  0x16
13280 #define COMPUTE_PGM_RSRC1__IEEE_MODE__SHIFT                                                                   0x17
13281 #define COMPUTE_PGM_RSRC1__BULKY__SHIFT                                                                       0x18
13282 #define COMPUTE_PGM_RSRC1__CDBG_USER__SHIFT                                                                   0x19
13283 #define COMPUTE_PGM_RSRC1__FP16_OVFL__SHIFT                                                                   0x1a
13284 #define COMPUTE_PGM_RSRC1__VGPRS_MASK                                                                         0x0000003FL
13285 #define COMPUTE_PGM_RSRC1__SGPRS_MASK                                                                         0x000003C0L
13286 #define COMPUTE_PGM_RSRC1__PRIORITY_MASK                                                                      0x00000C00L
13287 #define COMPUTE_PGM_RSRC1__FLOAT_MODE_MASK                                                                    0x000FF000L
13288 #define COMPUTE_PGM_RSRC1__PRIV_MASK                                                                          0x00100000L
13289 #define COMPUTE_PGM_RSRC1__DX10_CLAMP_MASK                                                                    0x00200000L
13290 #define COMPUTE_PGM_RSRC1__DEBUG_MODE_MASK                                                                    0x00400000L
13291 #define COMPUTE_PGM_RSRC1__IEEE_MODE_MASK                                                                     0x00800000L
13292 #define COMPUTE_PGM_RSRC1__BULKY_MASK                                                                         0x01000000L
13293 #define COMPUTE_PGM_RSRC1__CDBG_USER_MASK                                                                     0x02000000L
13294 #define COMPUTE_PGM_RSRC1__FP16_OVFL_MASK                                                                     0x04000000L
13295 //COMPUTE_PGM_RSRC2
13296 #define COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT                                                                  0x0
13297 #define COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT                                                                   0x1
13298 #define COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT                                                                0x6
13299 #define COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT                                                                   0x7
13300 #define COMPUTE_PGM_RSRC2__TGID_Y_EN__SHIFT                                                                   0x8
13301 #define COMPUTE_PGM_RSRC2__TGID_Z_EN__SHIFT                                                                   0x9
13302 #define COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT                                                                  0xa
13303 #define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT                                                              0xb
13304 #define COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT                                                                 0xd
13305 #define COMPUTE_PGM_RSRC2__LDS_SIZE__SHIFT                                                                    0xf
13306 #define COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT                                                                     0x18
13307 #define COMPUTE_PGM_RSRC2__SKIP_USGPR0__SHIFT                                                                 0x1f
13308 #define COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK                                                                    0x00000001L
13309 #define COMPUTE_PGM_RSRC2__USER_SGPR_MASK                                                                     0x0000003EL
13310 #define COMPUTE_PGM_RSRC2__TRAP_PRESENT_MASK                                                                  0x00000040L
13311 #define COMPUTE_PGM_RSRC2__TGID_X_EN_MASK                                                                     0x00000080L
13312 #define COMPUTE_PGM_RSRC2__TGID_Y_EN_MASK                                                                     0x00000100L
13313 #define COMPUTE_PGM_RSRC2__TGID_Z_EN_MASK                                                                     0x00000200L
13314 #define COMPUTE_PGM_RSRC2__TG_SIZE_EN_MASK                                                                    0x00000400L
13315 #define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK                                                                0x00001800L
13316 #define COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK                                                                   0x00006000L
13317 #define COMPUTE_PGM_RSRC2__LDS_SIZE_MASK                                                                      0x00FF8000L
13318 #define COMPUTE_PGM_RSRC2__EXCP_EN_MASK                                                                       0x7F000000L
13319 #define COMPUTE_PGM_RSRC2__SKIP_USGPR0_MASK                                                                   0x80000000L
13320 //COMPUTE_VMID
13321 #define COMPUTE_VMID__DATA__SHIFT                                                                             0x0
13322 #define COMPUTE_VMID__DATA_MASK                                                                               0x0000000FL
13323 //COMPUTE_RESOURCE_LIMITS
13324 #define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH__SHIFT                                                          0x0
13325 #define COMPUTE_RESOURCE_LIMITS__TG_PER_CU__SHIFT                                                             0xc
13326 #define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD__SHIFT                                                        0x10
13327 #define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL__SHIFT                                                        0x16
13328 #define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST__SHIFT                                                       0x17
13329 #define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT__SHIFT                                                        0x18
13330 #define COMPUTE_RESOURCE_LIMITS__SIMD_DISABLE__SHIFT                                                          0x1b
13331 #define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH_MASK                                                            0x000003FFL
13332 #define COMPUTE_RESOURCE_LIMITS__TG_PER_CU_MASK                                                               0x0000F000L
13333 #define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD_MASK                                                          0x003F0000L
13334 #define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL_MASK                                                          0x00400000L
13335 #define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK                                                         0x00800000L
13336 #define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT_MASK                                                          0x07000000L
13337 #define COMPUTE_RESOURCE_LIMITS__SIMD_DISABLE_MASK                                                            0x78000000L
13338 //COMPUTE_STATIC_THREAD_MGMT_SE0
13339 #define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN__SHIFT                                                      0x0
13340 #define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN__SHIFT                                                      0x10
13341 #define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN_MASK                                                        0x0000FFFFL
13342 #define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN_MASK                                                        0xFFFF0000L
13343 //COMPUTE_STATIC_THREAD_MGMT_SE1
13344 #define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN__SHIFT                                                      0x0
13345 #define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN__SHIFT                                                      0x10
13346 #define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN_MASK                                                        0x0000FFFFL
13347 #define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN_MASK                                                        0xFFFF0000L
13348 //COMPUTE_TMPRING_SIZE
13349 #define COMPUTE_TMPRING_SIZE__WAVES__SHIFT                                                                    0x0
13350 #define COMPUTE_TMPRING_SIZE__WAVESIZE__SHIFT                                                                 0xc
13351 #define COMPUTE_TMPRING_SIZE__WAVES_MASK                                                                      0x00000FFFL
13352 #define COMPUTE_TMPRING_SIZE__WAVESIZE_MASK                                                                   0x01FFF000L
13353 //COMPUTE_STATIC_THREAD_MGMT_SE2
13354 #define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN__SHIFT                                                      0x0
13355 #define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN__SHIFT                                                      0x10
13356 #define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN_MASK                                                        0x0000FFFFL
13357 #define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN_MASK                                                        0xFFFF0000L
13358 //COMPUTE_STATIC_THREAD_MGMT_SE3
13359 #define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN__SHIFT                                                      0x0
13360 #define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN__SHIFT                                                      0x10
13361 #define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN_MASK                                                        0x0000FFFFL
13362 #define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN_MASK                                                        0xFFFF0000L
13363 //COMPUTE_RESTART_X
13364 #define COMPUTE_RESTART_X__RESTART__SHIFT                                                                     0x0
13365 #define COMPUTE_RESTART_X__RESTART_MASK                                                                       0xFFFFFFFFL
13366 //COMPUTE_RESTART_Y
13367 #define COMPUTE_RESTART_Y__RESTART__SHIFT                                                                     0x0
13368 #define COMPUTE_RESTART_Y__RESTART_MASK                                                                       0xFFFFFFFFL
13369 //COMPUTE_RESTART_Z
13370 #define COMPUTE_RESTART_Z__RESTART__SHIFT                                                                     0x0
13371 #define COMPUTE_RESTART_Z__RESTART_MASK                                                                       0xFFFFFFFFL
13372 //COMPUTE_THREAD_TRACE_ENABLE
13373 #define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE__SHIFT                                               0x0
13374 #define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE_MASK                                                 0x00000001L
13375 //COMPUTE_MISC_RESERVED
13376 #define COMPUTE_MISC_RESERVED__SEND_SEID__SHIFT                                                               0x0
13377 #define COMPUTE_MISC_RESERVED__WAVE_ID_BASE__SHIFT                                                            0x5
13378 #define COMPUTE_MISC_RESERVED__SEND_SEID_MASK                                                                 0x00000003L
13379 #define COMPUTE_MISC_RESERVED__WAVE_ID_BASE_MASK                                                              0x0001FFE0L
13380 //COMPUTE_DISPATCH_ID
13381 #define COMPUTE_DISPATCH_ID__DISPATCH_ID__SHIFT                                                               0x0
13382 #define COMPUTE_DISPATCH_ID__DISPATCH_ID_MASK                                                                 0xFFFFFFFFL
13383 //COMPUTE_THREADGROUP_ID
13384 #define COMPUTE_THREADGROUP_ID__THREADGROUP_ID__SHIFT                                                         0x0
13385 #define COMPUTE_THREADGROUP_ID__THREADGROUP_ID_MASK                                                           0xFFFFFFFFL
13386 //COMPUTE_RELAUNCH
13387 #define COMPUTE_RELAUNCH__PAYLOAD__SHIFT                                                                      0x0
13388 #define COMPUTE_RELAUNCH__IS_EVENT__SHIFT                                                                     0x1e
13389 #define COMPUTE_RELAUNCH__IS_STATE__SHIFT                                                                     0x1f
13390 #define COMPUTE_RELAUNCH__PAYLOAD_MASK                                                                        0x3FFFFFFFL
13391 #define COMPUTE_RELAUNCH__IS_EVENT_MASK                                                                       0x40000000L
13392 #define COMPUTE_RELAUNCH__IS_STATE_MASK                                                                       0x80000000L
13393 //COMPUTE_WAVE_RESTORE_ADDR_LO
13394 #define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR__SHIFT                                                             0x0
13395 #define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR_MASK                                                               0xFFFFFFFFL
13396 //COMPUTE_WAVE_RESTORE_ADDR_HI
13397 #define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR__SHIFT                                                             0x0
13398 #define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR_MASK                                                               0xFFFFL
13399 //COMPUTE_TG_CHUNK_SIZE
13400 #define COMPUTE_TG_CHUNK_SIZE__TG_CHUNK_SIZE__SHIFT                                                           0x0
13401 #define COMPUTE_TG_CHUNK_SIZE__TG_CHUNK_SIZE_MASK                                                             0x0000FFFFL
13402 //COMPUTE_SHADER_CHKSUM
13403 #define COMPUTE_SHADER_CHKSUM__CHECKSUM__SHIFT                                                                0x0
13404 #define COMPUTE_SHADER_CHKSUM__CHECKSUM_MASK                                                                  0xFFFFFFFFL
13405 //COMPUTE_PGM_RSRC3
13406 #define COMPUTE_PGM_RSRC3__ACCUM_OFFSET__SHIFT                                                                0x0
13407 #define COMPUTE_PGM_RSRC3__TRAP_ON_START__SHIFT                                                               0xa
13408 #define COMPUTE_PGM_RSRC3__TRAP_ON_END__SHIFT                                                                 0xb
13409 #define COMPUTE_PGM_RSRC3__TG_SPLIT__SHIFT                                                                    0x10
13410 #define COMPUTE_PGM_RSRC3__ACCUM_OFFSET_MASK                                                                  0x0000003FL
13411 #define COMPUTE_PGM_RSRC3__TRAP_ON_START_MASK                                                                 0x00000400L
13412 #define COMPUTE_PGM_RSRC3__TRAP_ON_END_MASK                                                                   0x00000800L
13413 #define COMPUTE_PGM_RSRC3__TG_SPLIT_MASK                                                                      0x00010000L
13414 //COMPUTE_USER_DATA_0
13415 #define COMPUTE_USER_DATA_0__DATA__SHIFT                                                                      0x0
13416 #define COMPUTE_USER_DATA_0__DATA_MASK                                                                        0xFFFFFFFFL
13417 //COMPUTE_USER_DATA_1
13418 #define COMPUTE_USER_DATA_1__DATA__SHIFT                                                                      0x0
13419 #define COMPUTE_USER_DATA_1__DATA_MASK                                                                        0xFFFFFFFFL
13420 //COMPUTE_USER_DATA_2
13421 #define COMPUTE_USER_DATA_2__DATA__SHIFT                                                                      0x0
13422 #define COMPUTE_USER_DATA_2__DATA_MASK                                                                        0xFFFFFFFFL
13423 //COMPUTE_USER_DATA_3
13424 #define COMPUTE_USER_DATA_3__DATA__SHIFT                                                                      0x0
13425 #define COMPUTE_USER_DATA_3__DATA_MASK                                                                        0xFFFFFFFFL
13426 //COMPUTE_USER_DATA_4
13427 #define COMPUTE_USER_DATA_4__DATA__SHIFT                                                                      0x0
13428 #define COMPUTE_USER_DATA_4__DATA_MASK                                                                        0xFFFFFFFFL
13429 //COMPUTE_USER_DATA_5
13430 #define COMPUTE_USER_DATA_5__DATA__SHIFT                                                                      0x0
13431 #define COMPUTE_USER_DATA_5__DATA_MASK                                                                        0xFFFFFFFFL
13432 //COMPUTE_USER_DATA_6
13433 #define COMPUTE_USER_DATA_6__DATA__SHIFT                                                                      0x0
13434 #define COMPUTE_USER_DATA_6__DATA_MASK                                                                        0xFFFFFFFFL
13435 //COMPUTE_USER_DATA_7
13436 #define COMPUTE_USER_DATA_7__DATA__SHIFT                                                                      0x0
13437 #define COMPUTE_USER_DATA_7__DATA_MASK                                                                        0xFFFFFFFFL
13438 //COMPUTE_USER_DATA_8
13439 #define COMPUTE_USER_DATA_8__DATA__SHIFT                                                                      0x0
13440 #define COMPUTE_USER_DATA_8__DATA_MASK                                                                        0xFFFFFFFFL
13441 //COMPUTE_USER_DATA_9
13442 #define COMPUTE_USER_DATA_9__DATA__SHIFT                                                                      0x0
13443 #define COMPUTE_USER_DATA_9__DATA_MASK                                                                        0xFFFFFFFFL
13444 //COMPUTE_USER_DATA_10
13445 #define COMPUTE_USER_DATA_10__DATA__SHIFT                                                                     0x0
13446 #define COMPUTE_USER_DATA_10__DATA_MASK                                                                       0xFFFFFFFFL
13447 //COMPUTE_USER_DATA_11
13448 #define COMPUTE_USER_DATA_11__DATA__SHIFT                                                                     0x0
13449 #define COMPUTE_USER_DATA_11__DATA_MASK                                                                       0xFFFFFFFFL
13450 //COMPUTE_USER_DATA_12
13451 #define COMPUTE_USER_DATA_12__DATA__SHIFT                                                                     0x0
13452 #define COMPUTE_USER_DATA_12__DATA_MASK                                                                       0xFFFFFFFFL
13453 //COMPUTE_USER_DATA_13
13454 #define COMPUTE_USER_DATA_13__DATA__SHIFT                                                                     0x0
13455 #define COMPUTE_USER_DATA_13__DATA_MASK                                                                       0xFFFFFFFFL
13456 //COMPUTE_USER_DATA_14
13457 #define COMPUTE_USER_DATA_14__DATA__SHIFT                                                                     0x0
13458 #define COMPUTE_USER_DATA_14__DATA_MASK                                                                       0xFFFFFFFFL
13459 //COMPUTE_USER_DATA_15
13460 #define COMPUTE_USER_DATA_15__DATA__SHIFT                                                                     0x0
13461 #define COMPUTE_USER_DATA_15__DATA_MASK                                                                       0xFFFFFFFFL
13462 //COMPUTE_DISPATCH_END
13463 #define COMPUTE_DISPATCH_END__DATA__SHIFT                                                                     0x0
13464 #define COMPUTE_DISPATCH_END__DATA_MASK                                                                       0xFFFFFFFFL
13465 //COMPUTE_NOWHERE
13466 #define COMPUTE_NOWHERE__DATA__SHIFT                                                                          0x0
13467 #define COMPUTE_NOWHERE__DATA_MASK                                                                            0xFFFFFFFFL
13468 
13469 
13470 // addressBlock: xcd0_gc_cppdec
13471 //CP_DFY_CNTL
13472 #define CP_DFY_CNTL__POLICY__SHIFT                                                                            0x0
13473 #define CP_DFY_CNTL__MTYPE__SHIFT                                                                             0x2
13474 #define CP_DFY_CNTL__WRITE_DIS__SHIFT                                                                         0x1b
13475 #define CP_DFY_CNTL__LFSR_RESET__SHIFT                                                                        0x1c
13476 #define CP_DFY_CNTL__MODE__SHIFT                                                                              0x1d
13477 #define CP_DFY_CNTL__ENABLE__SHIFT                                                                            0x1f
13478 #define CP_DFY_CNTL__POLICY_MASK                                                                              0x00000001L
13479 #define CP_DFY_CNTL__MTYPE_MASK                                                                               0x0000000CL
13480 #define CP_DFY_CNTL__WRITE_DIS_MASK                                                                           0x08000000L
13481 #define CP_DFY_CNTL__LFSR_RESET_MASK                                                                          0x10000000L
13482 #define CP_DFY_CNTL__MODE_MASK                                                                                0x60000000L
13483 #define CP_DFY_CNTL__ENABLE_MASK                                                                              0x80000000L
13484 //CP_DFY_STAT
13485 #define CP_DFY_STAT__BURST_COUNT__SHIFT                                                                       0x0
13486 #define CP_DFY_STAT__TAGS_PENDING__SHIFT                                                                      0x10
13487 #define CP_DFY_STAT__BUSY__SHIFT                                                                              0x1f
13488 #define CP_DFY_STAT__BURST_COUNT_MASK                                                                         0x0000FFFFL
13489 #define CP_DFY_STAT__TAGS_PENDING_MASK                                                                        0x07FF0000L
13490 #define CP_DFY_STAT__BUSY_MASK                                                                                0x80000000L
13491 //CP_DFY_ADDR_HI
13492 #define CP_DFY_ADDR_HI__ADDR_HI__SHIFT                                                                        0x0
13493 #define CP_DFY_ADDR_HI__ADDR_HI_MASK                                                                          0xFFFFFFFFL
13494 //CP_DFY_ADDR_LO
13495 #define CP_DFY_ADDR_LO__ADDR_LO__SHIFT                                                                        0x5
13496 #define CP_DFY_ADDR_LO__ADDR_LO_MASK                                                                          0xFFFFFFE0L
13497 //CP_DFY_DATA_0
13498 #define CP_DFY_DATA_0__DATA__SHIFT                                                                            0x0
13499 #define CP_DFY_DATA_0__DATA_MASK                                                                              0xFFFFFFFFL
13500 //CP_DFY_DATA_1
13501 #define CP_DFY_DATA_1__DATA__SHIFT                                                                            0x0
13502 #define CP_DFY_DATA_1__DATA_MASK                                                                              0xFFFFFFFFL
13503 //CP_DFY_DATA_2
13504 #define CP_DFY_DATA_2__DATA__SHIFT                                                                            0x0
13505 #define CP_DFY_DATA_2__DATA_MASK                                                                              0xFFFFFFFFL
13506 //CP_DFY_DATA_3
13507 #define CP_DFY_DATA_3__DATA__SHIFT                                                                            0x0
13508 #define CP_DFY_DATA_3__DATA_MASK                                                                              0xFFFFFFFFL
13509 //CP_DFY_DATA_4
13510 #define CP_DFY_DATA_4__DATA__SHIFT                                                                            0x0
13511 #define CP_DFY_DATA_4__DATA_MASK                                                                              0xFFFFFFFFL
13512 //CP_DFY_DATA_5
13513 #define CP_DFY_DATA_5__DATA__SHIFT                                                                            0x0
13514 #define CP_DFY_DATA_5__DATA_MASK                                                                              0xFFFFFFFFL
13515 //CP_DFY_DATA_6
13516 #define CP_DFY_DATA_6__DATA__SHIFT                                                                            0x0
13517 #define CP_DFY_DATA_6__DATA_MASK                                                                              0xFFFFFFFFL
13518 //CP_DFY_DATA_7
13519 #define CP_DFY_DATA_7__DATA__SHIFT                                                                            0x0
13520 #define CP_DFY_DATA_7__DATA_MASK                                                                              0xFFFFFFFFL
13521 //CP_DFY_DATA_8
13522 #define CP_DFY_DATA_8__DATA__SHIFT                                                                            0x0
13523 #define CP_DFY_DATA_8__DATA_MASK                                                                              0xFFFFFFFFL
13524 //CP_DFY_DATA_9
13525 #define CP_DFY_DATA_9__DATA__SHIFT                                                                            0x0
13526 #define CP_DFY_DATA_9__DATA_MASK                                                                              0xFFFFFFFFL
13527 //CP_DFY_DATA_10
13528 #define CP_DFY_DATA_10__DATA__SHIFT                                                                           0x0
13529 #define CP_DFY_DATA_10__DATA_MASK                                                                             0xFFFFFFFFL
13530 //CP_DFY_DATA_11
13531 #define CP_DFY_DATA_11__DATA__SHIFT                                                                           0x0
13532 #define CP_DFY_DATA_11__DATA_MASK                                                                             0xFFFFFFFFL
13533 //CP_DFY_DATA_12
13534 #define CP_DFY_DATA_12__DATA__SHIFT                                                                           0x0
13535 #define CP_DFY_DATA_12__DATA_MASK                                                                             0xFFFFFFFFL
13536 //CP_DFY_DATA_13
13537 #define CP_DFY_DATA_13__DATA__SHIFT                                                                           0x0
13538 #define CP_DFY_DATA_13__DATA_MASK                                                                             0xFFFFFFFFL
13539 //CP_DFY_DATA_14
13540 #define CP_DFY_DATA_14__DATA__SHIFT                                                                           0x0
13541 #define CP_DFY_DATA_14__DATA_MASK                                                                             0xFFFFFFFFL
13542 //CP_DFY_DATA_15
13543 #define CP_DFY_DATA_15__DATA__SHIFT                                                                           0x0
13544 #define CP_DFY_DATA_15__DATA_MASK                                                                             0xFFFFFFFFL
13545 //CP_DFY_CMD
13546 #define CP_DFY_CMD__OFFSET__SHIFT                                                                             0x0
13547 #define CP_DFY_CMD__SIZE__SHIFT                                                                               0x10
13548 #define CP_DFY_CMD__OFFSET_MASK                                                                               0x000001FFL
13549 #define CP_DFY_CMD__SIZE_MASK                                                                                 0xFFFF0000L
13550 //CP_EOPQ_WAIT_TIME
13551 #define CP_EOPQ_WAIT_TIME__WAIT_TIME__SHIFT                                                                   0x0
13552 #define CP_EOPQ_WAIT_TIME__SCALE_COUNT__SHIFT                                                                 0xa
13553 #define CP_EOPQ_WAIT_TIME__WAIT_TIME_MASK                                                                     0x000003FFL
13554 #define CP_EOPQ_WAIT_TIME__SCALE_COUNT_MASK                                                                   0x0003FC00L
13555 //CP_CPC_MGCG_SYNC_CNTL
13556 #define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD__SHIFT                                                         0x0
13557 #define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD__SHIFT                                                           0x8
13558 #define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD_MASK                                                           0x000000FFL
13559 #define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD_MASK                                                             0x0000FF00L
13560 //CPC_INT_INFO
13561 #define CPC_INT_INFO__ADDR_HI__SHIFT                                                                          0x0
13562 #define CPC_INT_INFO__TYPE__SHIFT                                                                             0x10
13563 #define CPC_INT_INFO__VMID__SHIFT                                                                             0x14
13564 #define CPC_INT_INFO__QUEUE_ID__SHIFT                                                                         0x1c
13565 #define CPC_INT_INFO__ADDR_HI_MASK                                                                            0x0000FFFFL
13566 #define CPC_INT_INFO__TYPE_MASK                                                                               0x00010000L
13567 #define CPC_INT_INFO__VMID_MASK                                                                               0x00F00000L
13568 #define CPC_INT_INFO__QUEUE_ID_MASK                                                                           0x70000000L
13569 //CP_VIRT_STATUS
13570 #define CP_VIRT_STATUS__VIRT_STATUS__SHIFT                                                                    0x0
13571 #define CP_VIRT_STATUS__VIRT_STATUS_MASK                                                                      0xFFFFFFFFL
13572 //CPC_INT_ADDR
13573 #define CPC_INT_ADDR__ADDR__SHIFT                                                                             0x0
13574 #define CPC_INT_ADDR__ADDR_MASK                                                                               0xFFFFFFFFL
13575 //CPC_INT_PASID
13576 #define CPC_INT_PASID__PASID__SHIFT                                                                           0x0
13577 #define CPC_INT_PASID__PASID_MASK                                                                             0x0000FFFFL
13578 //CP_GFX_ERROR
13579 #define CP_GFX_ERROR__EDC_ERROR_ID__SHIFT                                                                     0x0
13580 #define CP_GFX_ERROR__SUA_ERROR__SHIFT                                                                        0x4
13581 #define CP_GFX_ERROR__RSVD1_ERROR__SHIFT                                                                      0x5
13582 #define CP_GFX_ERROR__RSVD2_ERROR__SHIFT                                                                      0x6
13583 #define CP_GFX_ERROR__SEM_UTCL1_ERROR__SHIFT                                                                  0x7
13584 #define CP_GFX_ERROR__QU_STRM_UTCL1_ERROR__SHIFT                                                              0x8
13585 #define CP_GFX_ERROR__QU_EOP_UTCL1_ERROR__SHIFT                                                               0x9
13586 #define CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR__SHIFT                                                              0xa
13587 #define CP_GFX_ERROR__QU_READ_UTCL1_ERROR__SHIFT                                                              0xb
13588 #define CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR__SHIFT                                                           0xc
13589 #define CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR__SHIFT                                                           0xd
13590 #define CP_GFX_ERROR__SHADOW_UTCL1_ERROR__SHIFT                                                               0xe
13591 #define CP_GFX_ERROR__APPEND_UTCL1_ERROR__SHIFT                                                               0xf
13592 #define CP_GFX_ERROR__CE_DMA_UTCL1_ERROR__SHIFT                                                               0x10
13593 #define CP_GFX_ERROR__PFP_VGTDMA_UTCL1_ERROR__SHIFT                                                           0x11
13594 #define CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT                                                              0x12
13595 #define CP_GFX_ERROR__DMA_DST_UTCL1_ERROR__SHIFT                                                              0x13
13596 #define CP_GFX_ERROR__PFP_TC_UTCL1_ERROR__SHIFT                                                               0x14
13597 #define CP_GFX_ERROR__ME_TC_UTCL1_ERROR__SHIFT                                                                0x15
13598 #define CP_GFX_ERROR__CE_TC_UTCL1_ERROR__SHIFT                                                                0x16
13599 #define CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR__SHIFT                                                              0x17
13600 #define CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR__SHIFT                                                            0x18
13601 #define CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR__SHIFT                                                           0x19
13602 #define CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR__SHIFT                                                           0x1a
13603 #define CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR__SHIFT                                                           0x1b
13604 #define CP_GFX_ERROR__C1_FETCHER_UTCL1_ERROR__SHIFT                                                           0x1c
13605 #define CP_GFX_ERROR__C2_FETCHER_UTCL1_ERROR__SHIFT                                                           0x1d
13606 #define CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR__SHIFT                                                           0x1e
13607 #define CP_GFX_ERROR__CE_INIT_UTCL1_ERROR__SHIFT                                                              0x1f
13608 #define CP_GFX_ERROR__EDC_ERROR_ID_MASK                                                                       0x0000000FL
13609 #define CP_GFX_ERROR__SUA_ERROR_MASK                                                                          0x00000010L
13610 #define CP_GFX_ERROR__RSVD1_ERROR_MASK                                                                        0x00000020L
13611 #define CP_GFX_ERROR__RSVD2_ERROR_MASK                                                                        0x00000040L
13612 #define CP_GFX_ERROR__SEM_UTCL1_ERROR_MASK                                                                    0x00000080L
13613 #define CP_GFX_ERROR__QU_STRM_UTCL1_ERROR_MASK                                                                0x00000100L
13614 #define CP_GFX_ERROR__QU_EOP_UTCL1_ERROR_MASK                                                                 0x00000200L
13615 #define CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR_MASK                                                                0x00000400L
13616 #define CP_GFX_ERROR__QU_READ_UTCL1_ERROR_MASK                                                                0x00000800L
13617 #define CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR_MASK                                                             0x00001000L
13618 #define CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR_MASK                                                             0x00002000L
13619 #define CP_GFX_ERROR__SHADOW_UTCL1_ERROR_MASK                                                                 0x00004000L
13620 #define CP_GFX_ERROR__APPEND_UTCL1_ERROR_MASK                                                                 0x00008000L
13621 #define CP_GFX_ERROR__CE_DMA_UTCL1_ERROR_MASK                                                                 0x00010000L
13622 #define CP_GFX_ERROR__PFP_VGTDMA_UTCL1_ERROR_MASK                                                             0x00020000L
13623 #define CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR_MASK                                                                0x00040000L
13624 #define CP_GFX_ERROR__DMA_DST_UTCL1_ERROR_MASK                                                                0x00080000L
13625 #define CP_GFX_ERROR__PFP_TC_UTCL1_ERROR_MASK                                                                 0x00100000L
13626 #define CP_GFX_ERROR__ME_TC_UTCL1_ERROR_MASK                                                                  0x00200000L
13627 #define CP_GFX_ERROR__CE_TC_UTCL1_ERROR_MASK                                                                  0x00400000L
13628 #define CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR_MASK                                                                0x00800000L
13629 #define CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR_MASK                                                              0x01000000L
13630 #define CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR_MASK                                                             0x02000000L
13631 #define CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR_MASK                                                             0x04000000L
13632 #define CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR_MASK                                                             0x08000000L
13633 #define CP_GFX_ERROR__C1_FETCHER_UTCL1_ERROR_MASK                                                             0x10000000L
13634 #define CP_GFX_ERROR__C2_FETCHER_UTCL1_ERROR_MASK                                                             0x20000000L
13635 #define CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR_MASK                                                             0x40000000L
13636 #define CP_GFX_ERROR__CE_INIT_UTCL1_ERROR_MASK                                                                0x80000000L
13637 //CPG_UTCL1_CNTL
13638 #define CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT                                                           0x0
13639 #define CPG_UTCL1_CNTL__VMID_RESET_MODE__SHIFT                                                                0x17
13640 #define CPG_UTCL1_CNTL__DROP_MODE__SHIFT                                                                      0x18
13641 #define CPG_UTCL1_CNTL__INVALIDATE__SHIFT                                                                     0x1a
13642 #define CPG_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT                                                                0x1b
13643 #define CPG_UTCL1_CNTL__FORCE_SNOOP__SHIFT                                                                    0x1c
13644 #define CPG_UTCL1_CNTL__IGNORE_PTE_PERMISSION__SHIFT                                                          0x1d
13645 #define CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT                                                              0x1e
13646 #define CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK                                                             0x000FFFFFL
13647 #define CPG_UTCL1_CNTL__VMID_RESET_MODE_MASK                                                                  0x00800000L
13648 #define CPG_UTCL1_CNTL__DROP_MODE_MASK                                                                        0x01000000L
13649 #define CPG_UTCL1_CNTL__INVALIDATE_MASK                                                                       0x04000000L
13650 #define CPG_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK                                                                  0x08000000L
13651 #define CPG_UTCL1_CNTL__FORCE_SNOOP_MASK                                                                      0x10000000L
13652 #define CPG_UTCL1_CNTL__IGNORE_PTE_PERMISSION_MASK                                                            0x20000000L
13653 #define CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK                                                                0x40000000L
13654 //CPC_UTCL1_CNTL
13655 #define CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT                                                           0x0
13656 #define CPC_UTCL1_CNTL__DROP_MODE__SHIFT                                                                      0x18
13657 #define CPC_UTCL1_CNTL__INVALIDATE__SHIFT                                                                     0x1a
13658 #define CPC_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT                                                                0x1b
13659 #define CPC_UTCL1_CNTL__FORCE_SNOOP__SHIFT                                                                    0x1c
13660 #define CPC_UTCL1_CNTL__IGNORE_PTE_PERMISSION__SHIFT                                                          0x1d
13661 #define CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT                                                              0x1e
13662 #define CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK                                                             0x000FFFFFL
13663 #define CPC_UTCL1_CNTL__DROP_MODE_MASK                                                                        0x01000000L
13664 #define CPC_UTCL1_CNTL__INVALIDATE_MASK                                                                       0x04000000L
13665 #define CPC_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK                                                                  0x08000000L
13666 #define CPC_UTCL1_CNTL__FORCE_SNOOP_MASK                                                                      0x10000000L
13667 #define CPC_UTCL1_CNTL__IGNORE_PTE_PERMISSION_MASK                                                            0x20000000L
13668 #define CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK                                                                0x40000000L
13669 //CPF_UTCL1_CNTL
13670 #define CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT                                                           0x0
13671 #define CPF_UTCL1_CNTL__VMID_RESET_MODE__SHIFT                                                                0x17
13672 #define CPF_UTCL1_CNTL__DROP_MODE__SHIFT                                                                      0x18
13673 #define CPF_UTCL1_CNTL__INVALIDATE__SHIFT                                                                     0x1a
13674 #define CPF_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT                                                                0x1b
13675 #define CPF_UTCL1_CNTL__FORCE_SNOOP__SHIFT                                                                    0x1c
13676 #define CPF_UTCL1_CNTL__IGNORE_PTE_PERMISSION__SHIFT                                                          0x1d
13677 #define CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT                                                              0x1e
13678 #define CPF_UTCL1_CNTL__FORCE_NO_EXE__SHIFT                                                                   0x1f
13679 #define CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK                                                             0x000FFFFFL
13680 #define CPF_UTCL1_CNTL__VMID_RESET_MODE_MASK                                                                  0x00800000L
13681 #define CPF_UTCL1_CNTL__DROP_MODE_MASK                                                                        0x01000000L
13682 #define CPF_UTCL1_CNTL__INVALIDATE_MASK                                                                       0x04000000L
13683 #define CPF_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK                                                                  0x08000000L
13684 #define CPF_UTCL1_CNTL__FORCE_SNOOP_MASK                                                                      0x10000000L
13685 #define CPF_UTCL1_CNTL__IGNORE_PTE_PERMISSION_MASK                                                            0x20000000L
13686 #define CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK                                                                0x40000000L
13687 #define CPF_UTCL1_CNTL__FORCE_NO_EXE_MASK                                                                     0x80000000L
13688 //CP_AQL_SMM_STATUS
13689 #define CP_AQL_SMM_STATUS__AQL_QUEUE_SMM__SHIFT                                                               0x0
13690 #define CP_AQL_SMM_STATUS__AQL_QUEUE_SMM_MASK                                                                 0xFFFFFFFFL
13691 //CP_RB0_BASE
13692 #define CP_RB0_BASE__RB_BASE__SHIFT                                                                           0x0
13693 #define CP_RB0_BASE__RB_BASE_MASK                                                                             0xFFFFFFFFL
13694 //CP_RB_BASE
13695 #define CP_RB_BASE__RB_BASE__SHIFT                                                                            0x0
13696 #define CP_RB_BASE__RB_BASE_MASK                                                                              0xFFFFFFFFL
13697 //CP_RB0_CNTL
13698 #define CP_RB0_CNTL__RB_BUFSZ__SHIFT                                                                          0x0
13699 #define CP_RB0_CNTL__RB_BLKSZ__SHIFT                                                                          0x8
13700 #define CP_RB0_CNTL__BUF_SWAP__SHIFT                                                                          0x11
13701 #define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT                                                                       0x14
13702 #define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT                                                                    0x16
13703 #define CP_RB0_CNTL__CACHE_POLICY__SHIFT                                                                      0x18
13704 #define CP_RB0_CNTL__RB_NO_UPDATE__SHIFT                                                                      0x1b
13705 #define CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT                                                                    0x1f
13706 #define CP_RB0_CNTL__RB_BUFSZ_MASK                                                                            0x0000003FL
13707 #define CP_RB0_CNTL__RB_BLKSZ_MASK                                                                            0x00003F00L
13708 #define CP_RB0_CNTL__BUF_SWAP_MASK                                                                            0x00060000L
13709 #define CP_RB0_CNTL__MIN_AVAILSZ_MASK                                                                         0x00300000L
13710 #define CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK                                                                      0x00C00000L
13711 #define CP_RB0_CNTL__CACHE_POLICY_MASK                                                                        0x01000000L
13712 #define CP_RB0_CNTL__RB_NO_UPDATE_MASK                                                                        0x08000000L
13713 #define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK                                                                      0x80000000L
13714 //CP_RB_CNTL
13715 #define CP_RB_CNTL__RB_BUFSZ__SHIFT                                                                           0x0
13716 #define CP_RB_CNTL__RB_BLKSZ__SHIFT                                                                           0x8
13717 #define CP_RB_CNTL__MIN_AVAILSZ__SHIFT                                                                        0x14
13718 #define CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT                                                                     0x16
13719 #define CP_RB_CNTL__CACHE_POLICY__SHIFT                                                                       0x18
13720 #define CP_RB_CNTL__RB_NO_UPDATE__SHIFT                                                                       0x1b
13721 #define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT                                                                     0x1f
13722 #define CP_RB_CNTL__RB_BUFSZ_MASK                                                                             0x0000003FL
13723 #define CP_RB_CNTL__RB_BLKSZ_MASK                                                                             0x00003F00L
13724 #define CP_RB_CNTL__MIN_AVAILSZ_MASK                                                                          0x00300000L
13725 #define CP_RB_CNTL__MIN_IB_AVAILSZ_MASK                                                                       0x00C00000L
13726 #define CP_RB_CNTL__CACHE_POLICY_MASK                                                                         0x01000000L
13727 #define CP_RB_CNTL__RB_NO_UPDATE_MASK                                                                         0x08000000L
13728 #define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK                                                                       0x80000000L
13729 //CP_RB_RPTR_WR
13730 #define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT                                                                      0x0
13731 #define CP_RB_RPTR_WR__RB_RPTR_WR_MASK                                                                        0x000FFFFFL
13732 //CP_RB0_RPTR_ADDR
13733 #define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT                                                                 0x2
13734 #define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK                                                                   0xFFFFFFFCL
13735 //CP_RB_RPTR_ADDR
13736 #define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT                                                                  0x2
13737 #define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK                                                                    0xFFFFFFFCL
13738 //CP_RB0_RPTR_ADDR_HI
13739 #define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT                                                           0x0
13740 #define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK                                                             0x0000FFFFL
13741 //CP_RB_RPTR_ADDR_HI
13742 #define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT                                                            0x0
13743 #define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK                                                              0x0000FFFFL
13744 //CP_RB0_BUFSZ_MASK
13745 #define CP_RB0_BUFSZ_MASK__DATA__SHIFT                                                                        0x0
13746 #define CP_RB0_BUFSZ_MASK__DATA_MASK                                                                          0x000FFFFFL
13747 //CP_RB_BUFSZ_MASK
13748 #define CP_RB_BUFSZ_MASK__DATA__SHIFT                                                                         0x0
13749 #define CP_RB_BUFSZ_MASK__DATA_MASK                                                                           0x000FFFFFL
13750 //CP_RB_WPTR_POLL_ADDR_LO
13751 #define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO__SHIFT                                                  0x2
13752 #define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO_MASK                                                    0xFFFFFFFCL
13753 //CP_RB_WPTR_POLL_ADDR_HI
13754 #define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI__SHIFT                                                  0x0
13755 #define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI_MASK                                                    0x0000FFFFL
13756 //GC_PRIV_MODE
13757 #define GC_PRIV_MODE__MC_PRIV_MODE__SHIFT                                                                     0x0
13758 #define GC_PRIV_MODE__MC_PRIV_MODE_MASK                                                                       0x00000001L
13759 //CP_INT_CNTL
13760 #define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT                                                      0xb
13761 #define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                           0xe
13762 #define CP_INT_CNTL__GPF_INT_ENABLE__SHIFT                                                                    0x10
13763 #define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                                       0x11
13764 #define CP_INT_CNTL__CMP_BUSY_INT_ENABLE__SHIFT                                                               0x12
13765 #define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT                                                              0x13
13766 #define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT                                                             0x14
13767 #define CP_INT_CNTL__GFX_IDLE_INT_ENABLE__SHIFT                                                               0x15
13768 #define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT                                                             0x16
13769 #define CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT                                                               0x17
13770 #define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT                                                           0x18
13771 #define CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT                                                             0x1a
13772 #define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                                     0x1b
13773 #define CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT                                                               0x1d
13774 #define CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT                                                               0x1e
13775 #define CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT                                                               0x1f
13776 #define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE_MASK                                                        0x00000800L
13777 #define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK                                                             0x00004000L
13778 #define CP_INT_CNTL__GPF_INT_ENABLE_MASK                                                                      0x00010000L
13779 #define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                                         0x00020000L
13780 #define CP_INT_CNTL__CMP_BUSY_INT_ENABLE_MASK                                                                 0x00040000L
13781 #define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK                                                                0x00080000L
13782 #define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK                                                               0x00100000L
13783 #define CP_INT_CNTL__GFX_IDLE_INT_ENABLE_MASK                                                                 0x00200000L
13784 #define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK                                                               0x00400000L
13785 #define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK                                                                 0x00800000L
13786 #define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK                                                             0x01000000L
13787 #define CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK                                                               0x04000000L
13788 #define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                                       0x08000000L
13789 #define CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK                                                                 0x20000000L
13790 #define CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK                                                                 0x40000000L
13791 #define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK                                                                 0x80000000L
13792 //CP_INT_STATUS
13793 #define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT__SHIFT                                                      0xb
13794 #define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT                                                           0xe
13795 #define CP_INT_STATUS__GPF_INT_STAT__SHIFT                                                                    0x10
13796 #define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT                                                       0x11
13797 #define CP_INT_STATUS__CMP_BUSY_INT_STAT__SHIFT                                                               0x12
13798 #define CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT                                                              0x13
13799 #define CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT                                                             0x14
13800 #define CP_INT_STATUS__GFX_IDLE_INT_STAT__SHIFT                                                               0x15
13801 #define CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT                                                             0x16
13802 #define CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT                                                               0x17
13803 #define CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT                                                           0x18
13804 #define CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT                                                             0x1a
13805 #define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT                                                     0x1b
13806 #define CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT                                                               0x1d
13807 #define CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT                                                               0x1e
13808 #define CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT                                                               0x1f
13809 #define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT_MASK                                                        0x00000800L
13810 #define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK                                                             0x00004000L
13811 #define CP_INT_STATUS__GPF_INT_STAT_MASK                                                                      0x00010000L
13812 #define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK                                                         0x00020000L
13813 #define CP_INT_STATUS__CMP_BUSY_INT_STAT_MASK                                                                 0x00040000L
13814 #define CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK                                                                0x00080000L
13815 #define CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK                                                               0x00100000L
13816 #define CP_INT_STATUS__GFX_IDLE_INT_STAT_MASK                                                                 0x00200000L
13817 #define CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK                                                               0x00400000L
13818 #define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK                                                                 0x00800000L
13819 #define CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK                                                             0x01000000L
13820 #define CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK                                                               0x04000000L
13821 #define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK                                                       0x08000000L
13822 #define CP_INT_STATUS__GENERIC2_INT_STAT_MASK                                                                 0x20000000L
13823 #define CP_INT_STATUS__GENERIC1_INT_STAT_MASK                                                                 0x40000000L
13824 #define CP_INT_STATUS__GENERIC0_INT_STAT_MASK                                                                 0x80000000L
13825 //CP_DEVICE_ID
13826 #define CP_DEVICE_ID__DEVICE_ID__SHIFT                                                                        0x0
13827 #define CP_DEVICE_ID__DEVICE_ID_MASK                                                                          0x000000FFL
13828 //CP_ME0_PIPE_PRIORITY_CNTS
13829 #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT                                                       0x0
13830 #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT                                                      0x8
13831 #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT                                                      0x10
13832 #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT                                                       0x18
13833 #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK                                                         0x000000FFL
13834 #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK                                                        0x0000FF00L
13835 #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK                                                        0x00FF0000L
13836 #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK                                                         0xFF000000L
13837 //CP_RING_PRIORITY_CNTS
13838 #define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT                                                           0x0
13839 #define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT                                                          0x8
13840 #define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT                                                          0x10
13841 #define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT                                                           0x18
13842 #define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK                                                             0x000000FFL
13843 #define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK                                                            0x0000FF00L
13844 #define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK                                                            0x00FF0000L
13845 #define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK                                                             0xFF000000L
13846 //CP_ME0_PIPE0_PRIORITY
13847 #define CP_ME0_PIPE0_PRIORITY__PRIORITY__SHIFT                                                                0x0
13848 #define CP_ME0_PIPE0_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
13849 //CP_RING0_PRIORITY
13850 #define CP_RING0_PRIORITY__PRIORITY__SHIFT                                                                    0x0
13851 #define CP_RING0_PRIORITY__PRIORITY_MASK                                                                      0x00000003L
13852 //CP_ME0_PIPE1_PRIORITY
13853 #define CP_ME0_PIPE1_PRIORITY__PRIORITY__SHIFT                                                                0x0
13854 #define CP_ME0_PIPE1_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
13855 //CP_RING1_PRIORITY
13856 #define CP_RING1_PRIORITY__PRIORITY__SHIFT                                                                    0x0
13857 #define CP_RING1_PRIORITY__PRIORITY_MASK                                                                      0x00000003L
13858 //CP_ME0_PIPE2_PRIORITY
13859 #define CP_ME0_PIPE2_PRIORITY__PRIORITY__SHIFT                                                                0x0
13860 #define CP_ME0_PIPE2_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
13861 //CP_RING2_PRIORITY
13862 #define CP_RING2_PRIORITY__PRIORITY__SHIFT                                                                    0x0
13863 #define CP_RING2_PRIORITY__PRIORITY_MASK                                                                      0x00000003L
13864 //CP_FATAL_ERROR
13865 #define CP_FATAL_ERROR__CPF_FATAL_ERROR__SHIFT                                                                0x0
13866 #define CP_FATAL_ERROR__CPG_FATAL_ERROR__SHIFT                                                                0x1
13867 #define CP_FATAL_ERROR__GFX_HALT_PROC__SHIFT                                                                  0x2
13868 #define CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR__SHIFT                                                            0x3
13869 #define CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN__SHIFT                                                         0x4
13870 #define CP_FATAL_ERROR__CPF_FATAL_ERROR_MASK                                                                  0x00000001L
13871 #define CP_FATAL_ERROR__CPG_FATAL_ERROR_MASK                                                                  0x00000002L
13872 #define CP_FATAL_ERROR__GFX_HALT_PROC_MASK                                                                    0x00000004L
13873 #define CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR_MASK                                                              0x00000008L
13874 #define CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN_MASK                                                           0x00000010L
13875 //CP_RB_VMID
13876 #define CP_RB_VMID__RB0_VMID__SHIFT                                                                           0x0
13877 #define CP_RB_VMID__RB1_VMID__SHIFT                                                                           0x8
13878 #define CP_RB_VMID__RB2_VMID__SHIFT                                                                           0x10
13879 #define CP_RB_VMID__RB0_VMID_MASK                                                                             0x0000000FL
13880 #define CP_RB_VMID__RB1_VMID_MASK                                                                             0x00000F00L
13881 #define CP_RB_VMID__RB2_VMID_MASK                                                                             0x000F0000L
13882 //CP_ME0_PIPE0_VMID
13883 #define CP_ME0_PIPE0_VMID__VMID__SHIFT                                                                        0x0
13884 #define CP_ME0_PIPE0_VMID__VMID_MASK                                                                          0x0000000FL
13885 //CP_ME0_PIPE1_VMID
13886 #define CP_ME0_PIPE1_VMID__VMID__SHIFT                                                                        0x0
13887 #define CP_ME0_PIPE1_VMID__VMID_MASK                                                                          0x0000000FL
13888 //CP_RB0_WPTR
13889 #define CP_RB0_WPTR__RB_WPTR__SHIFT                                                                           0x0
13890 #define CP_RB0_WPTR__RB_WPTR_MASK                                                                             0xFFFFFFFFL
13891 //CP_RB_WPTR
13892 #define CP_RB_WPTR__RB_WPTR__SHIFT                                                                            0x0
13893 #define CP_RB_WPTR__RB_WPTR_MASK                                                                              0xFFFFFFFFL
13894 //CP_RB0_WPTR_HI
13895 #define CP_RB0_WPTR_HI__RB_WPTR__SHIFT                                                                        0x0
13896 #define CP_RB0_WPTR_HI__RB_WPTR_MASK                                                                          0xFFFFFFFFL
13897 //CP_RB_WPTR_HI
13898 #define CP_RB_WPTR_HI__RB_WPTR__SHIFT                                                                         0x0
13899 #define CP_RB_WPTR_HI__RB_WPTR_MASK                                                                           0xFFFFFFFFL
13900 //CP_RB1_WPTR
13901 #define CP_RB1_WPTR__RB_WPTR__SHIFT                                                                           0x0
13902 #define CP_RB1_WPTR__RB_WPTR_MASK                                                                             0xFFFFFFFFL
13903 //CP_RB1_WPTR_HI
13904 #define CP_RB1_WPTR_HI__RB_WPTR__SHIFT                                                                        0x0
13905 #define CP_RB1_WPTR_HI__RB_WPTR_MASK                                                                          0xFFFFFFFFL
13906 //CP_RB2_WPTR
13907 #define CP_RB2_WPTR__RB_WPTR__SHIFT                                                                           0x0
13908 #define CP_RB2_WPTR__RB_WPTR_MASK                                                                             0x000FFFFFL
13909 //CP_RB_DOORBELL_CONTROL
13910 #define CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT                                                      0x1
13911 #define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT                                                        0x2
13912 #define CP_RB_DOORBELL_CONTROL__DOORBELL_EN__SHIFT                                                            0x1e
13913 #define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT                                                           0x1f
13914 #define CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK                                                        0x00000002L
13915 #define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK                                                          0x0FFFFFFCL
13916 #define CP_RB_DOORBELL_CONTROL__DOORBELL_EN_MASK                                                              0x40000000L
13917 #define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT_MASK                                                             0x80000000L
13918 //CP_RB_DOORBELL_RANGE_LOWER
13919 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT                                               0x2
13920 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK                                                 0x0FFFFFFCL
13921 //CP_RB_DOORBELL_RANGE_UPPER
13922 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT                                               0x2
13923 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK                                                 0x0FFFFFFCL
13924 //CP_MEC_DOORBELL_RANGE_LOWER
13925 #define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT                                              0x2
13926 #define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK                                                0x0FFFFFFCL
13927 //CP_MEC_DOORBELL_RANGE_UPPER
13928 #define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT                                              0x2
13929 #define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK                                                0x0FFFFFFCL
13930 //CPG_UTCL1_ERROR
13931 #define CPG_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT                                                           0x0
13932 #define CPG_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK                                                             0x00000001L
13933 //CPC_UTCL1_ERROR
13934 #define CPC_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT                                                           0x0
13935 #define CPC_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK                                                             0x00000001L
13936 //CP_RB1_BASE
13937 #define CP_RB1_BASE__RB_BASE__SHIFT                                                                           0x0
13938 #define CP_RB1_BASE__RB_BASE_MASK                                                                             0xFFFFFFFFL
13939 //CP_RB1_CNTL
13940 #define CP_RB1_CNTL__RB_BUFSZ__SHIFT                                                                          0x0
13941 #define CP_RB1_CNTL__RB_BLKSZ__SHIFT                                                                          0x8
13942 #define CP_RB1_CNTL__MIN_AVAILSZ__SHIFT                                                                       0x14
13943 #define CP_RB1_CNTL__MIN_IB_AVAILSZ__SHIFT                                                                    0x16
13944 #define CP_RB1_CNTL__CACHE_POLICY__SHIFT                                                                      0x18
13945 #define CP_RB1_CNTL__RB_NO_UPDATE__SHIFT                                                                      0x1b
13946 #define CP_RB1_CNTL__RB_RPTR_WR_ENA__SHIFT                                                                    0x1f
13947 #define CP_RB1_CNTL__RB_BUFSZ_MASK                                                                            0x0000003FL
13948 #define CP_RB1_CNTL__RB_BLKSZ_MASK                                                                            0x00003F00L
13949 #define CP_RB1_CNTL__MIN_AVAILSZ_MASK                                                                         0x00300000L
13950 #define CP_RB1_CNTL__MIN_IB_AVAILSZ_MASK                                                                      0x00C00000L
13951 #define CP_RB1_CNTL__CACHE_POLICY_MASK                                                                        0x01000000L
13952 #define CP_RB1_CNTL__RB_NO_UPDATE_MASK                                                                        0x08000000L
13953 #define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK                                                                      0x80000000L
13954 //CP_RB1_RPTR_ADDR
13955 #define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR__SHIFT                                                                 0x2
13956 #define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR_MASK                                                                   0xFFFFFFFCL
13957 //CP_RB1_RPTR_ADDR_HI
13958 #define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT                                                           0x0
13959 #define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK                                                             0x0000FFFFL
13960 //CP_RB2_BASE
13961 #define CP_RB2_BASE__RB_BASE__SHIFT                                                                           0x0
13962 #define CP_RB2_BASE__RB_BASE_MASK                                                                             0xFFFFFFFFL
13963 //CP_RB2_CNTL
13964 #define CP_RB2_CNTL__RB_BUFSZ__SHIFT                                                                          0x0
13965 #define CP_RB2_CNTL__RB_BLKSZ__SHIFT                                                                          0x8
13966 #define CP_RB2_CNTL__MIN_AVAILSZ__SHIFT                                                                       0x14
13967 #define CP_RB2_CNTL__MIN_IB_AVAILSZ__SHIFT                                                                    0x16
13968 #define CP_RB2_CNTL__CACHE_POLICY__SHIFT                                                                      0x18
13969 #define CP_RB2_CNTL__RB_NO_UPDATE__SHIFT                                                                      0x1b
13970 #define CP_RB2_CNTL__RB_RPTR_WR_ENA__SHIFT                                                                    0x1f
13971 #define CP_RB2_CNTL__RB_BUFSZ_MASK                                                                            0x0000003FL
13972 #define CP_RB2_CNTL__RB_BLKSZ_MASK                                                                            0x00003F00L
13973 #define CP_RB2_CNTL__MIN_AVAILSZ_MASK                                                                         0x00300000L
13974 #define CP_RB2_CNTL__MIN_IB_AVAILSZ_MASK                                                                      0x00C00000L
13975 #define CP_RB2_CNTL__CACHE_POLICY_MASK                                                                        0x01000000L
13976 #define CP_RB2_CNTL__RB_NO_UPDATE_MASK                                                                        0x08000000L
13977 #define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK                                                                      0x80000000L
13978 //CP_RB2_RPTR_ADDR
13979 #define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR__SHIFT                                                                 0x2
13980 #define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR_MASK                                                                   0xFFFFFFFCL
13981 //CP_RB2_RPTR_ADDR_HI
13982 #define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT                                                           0x0
13983 #define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK                                                             0x0000FFFFL
13984 //CP_RB0_ACTIVE
13985 #define CP_RB0_ACTIVE__ACTIVE__SHIFT                                                                          0x0
13986 #define CP_RB0_ACTIVE__ACTIVE_MASK                                                                            0x00000001L
13987 //CP_RB_ACTIVE
13988 #define CP_RB_ACTIVE__ACTIVE__SHIFT                                                                           0x0
13989 #define CP_RB_ACTIVE__ACTIVE_MASK                                                                             0x00000001L
13990 //CP_INT_CNTL_RING0
13991 #define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT                                                0xb
13992 #define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                     0xe
13993 #define CP_INT_CNTL_RING0__GPF_INT_ENABLE__SHIFT                                                              0x10
13994 #define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                                 0x11
13995 #define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE__SHIFT                                                         0x12
13996 #define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT                                                        0x13
13997 #define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT                                                       0x14
13998 #define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE__SHIFT                                                         0x15
13999 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT                                                       0x16
14000 #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT                                                         0x17
14001 #define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT                                                     0x18
14002 #define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT                                                       0x1a
14003 #define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                               0x1b
14004 #define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT                                                         0x1d
14005 #define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT                                                         0x1e
14006 #define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT                                                         0x1f
14007 #define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE_MASK                                                  0x00000800L
14008 #define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK                                                       0x00004000L
14009 #define CP_INT_CNTL_RING0__GPF_INT_ENABLE_MASK                                                                0x00010000L
14010 #define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                                   0x00020000L
14011 #define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE_MASK                                                           0x00040000L
14012 #define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK                                                          0x00080000L
14013 #define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK                                                         0x00100000L
14014 #define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE_MASK                                                           0x00200000L
14015 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK                                                         0x00400000L
14016 #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK                                                           0x00800000L
14017 #define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK                                                       0x01000000L
14018 #define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK                                                         0x04000000L
14019 #define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                                 0x08000000L
14020 #define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK                                                           0x20000000L
14021 #define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK                                                           0x40000000L
14022 #define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK                                                           0x80000000L
14023 //CP_INT_CNTL_RING1
14024 #define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT                                                0xb
14025 #define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                     0xe
14026 #define CP_INT_CNTL_RING1__GPF_INT_ENABLE__SHIFT                                                              0x10
14027 #define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                                 0x11
14028 #define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE__SHIFT                                                         0x12
14029 #define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE__SHIFT                                                        0x13
14030 #define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE__SHIFT                                                       0x14
14031 #define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE__SHIFT                                                         0x15
14032 #define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT                                                       0x16
14033 #define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE__SHIFT                                                         0x17
14034 #define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE__SHIFT                                                     0x18
14035 #define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE__SHIFT                                                       0x1a
14036 #define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                               0x1b
14037 #define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT                                                         0x1d
14038 #define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE__SHIFT                                                         0x1e
14039 #define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE__SHIFT                                                         0x1f
14040 #define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE_MASK                                                  0x00000800L
14041 #define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE_MASK                                                       0x00004000L
14042 #define CP_INT_CNTL_RING1__GPF_INT_ENABLE_MASK                                                                0x00010000L
14043 #define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                                   0x00020000L
14044 #define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE_MASK                                                           0x00040000L
14045 #define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE_MASK                                                          0x00080000L
14046 #define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK                                                         0x00100000L
14047 #define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE_MASK                                                           0x00200000L
14048 #define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK                                                         0x00400000L
14049 #define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK                                                           0x00800000L
14050 #define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK                                                       0x01000000L
14051 #define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK                                                         0x04000000L
14052 #define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                                 0x08000000L
14053 #define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK                                                           0x20000000L
14054 #define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE_MASK                                                           0x40000000L
14055 #define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE_MASK                                                           0x80000000L
14056 //CP_INT_CNTL_RING2
14057 #define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT                                                0xb
14058 #define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                     0xe
14059 #define CP_INT_CNTL_RING2__GPF_INT_ENABLE__SHIFT                                                              0x10
14060 #define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                                 0x11
14061 #define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE__SHIFT                                                         0x12
14062 #define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE__SHIFT                                                        0x13
14063 #define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE__SHIFT                                                       0x14
14064 #define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE__SHIFT                                                         0x15
14065 #define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE__SHIFT                                                       0x16
14066 #define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE__SHIFT                                                         0x17
14067 #define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE__SHIFT                                                     0x18
14068 #define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE__SHIFT                                                       0x1a
14069 #define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                               0x1b
14070 #define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE__SHIFT                                                         0x1d
14071 #define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE__SHIFT                                                         0x1e
14072 #define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE__SHIFT                                                         0x1f
14073 #define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE_MASK                                                  0x00000800L
14074 #define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE_MASK                                                       0x00004000L
14075 #define CP_INT_CNTL_RING2__GPF_INT_ENABLE_MASK                                                                0x00010000L
14076 #define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                                   0x00020000L
14077 #define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE_MASK                                                           0x00040000L
14078 #define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE_MASK                                                          0x00080000L
14079 #define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE_MASK                                                         0x00100000L
14080 #define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE_MASK                                                           0x00200000L
14081 #define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE_MASK                                                         0x00400000L
14082 #define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK                                                           0x00800000L
14083 #define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK                                                       0x01000000L
14084 #define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK                                                         0x04000000L
14085 #define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                                 0x08000000L
14086 #define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE_MASK                                                           0x20000000L
14087 #define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE_MASK                                                           0x40000000L
14088 #define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE_MASK                                                           0x80000000L
14089 //CP_INT_STATUS_RING0
14090 #define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT__SHIFT                                                0xb
14091 #define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT                                                     0xe
14092 #define CP_INT_STATUS_RING0__GPF_INT_STAT__SHIFT                                                              0x10
14093 #define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT                                                 0x11
14094 #define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT__SHIFT                                                         0x12
14095 #define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT__SHIFT                                                       0x13
14096 #define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT                                                       0x14
14097 #define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT__SHIFT                                                         0x15
14098 #define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT                                                       0x16
14099 #define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT                                                         0x17
14100 #define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT                                                     0x18
14101 #define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT                                                       0x1a
14102 #define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT                                               0x1b
14103 #define CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT                                                         0x1d
14104 #define CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT                                                         0x1e
14105 #define CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT                                                         0x1f
14106 #define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT_MASK                                                  0x00000800L
14107 #define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK                                                       0x00004000L
14108 #define CP_INT_STATUS_RING0__GPF_INT_STAT_MASK                                                                0x00010000L
14109 #define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK                                                   0x00020000L
14110 #define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT_MASK                                                           0x00040000L
14111 #define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT_MASK                                                         0x00080000L
14112 #define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK                                                         0x00100000L
14113 #define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT_MASK                                                           0x00200000L
14114 #define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK                                                         0x00400000L
14115 #define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK                                                           0x00800000L
14116 #define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK                                                       0x01000000L
14117 #define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK                                                         0x04000000L
14118 #define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK                                                 0x08000000L
14119 #define CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK                                                           0x20000000L
14120 #define CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK                                                           0x40000000L
14121 #define CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK                                                           0x80000000L
14122 //CP_INT_STATUS_RING1
14123 #define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT__SHIFT                                                0xb
14124 #define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT__SHIFT                                                     0xe
14125 #define CP_INT_STATUS_RING1__GPF_INT_STAT__SHIFT                                                              0x10
14126 #define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT__SHIFT                                                 0x11
14127 #define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT__SHIFT                                                         0x12
14128 #define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT__SHIFT                                                        0x13
14129 #define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT__SHIFT                                                       0x14
14130 #define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT__SHIFT                                                         0x15
14131 #define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT__SHIFT                                                       0x16
14132 #define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT                                                         0x17
14133 #define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT__SHIFT                                                     0x18
14134 #define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT__SHIFT                                                       0x1a
14135 #define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT__SHIFT                                               0x1b
14136 #define CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT                                                         0x1d
14137 #define CP_INT_STATUS_RING1__GENERIC1_INT_STAT__SHIFT                                                         0x1e
14138 #define CP_INT_STATUS_RING1__GENERIC0_INT_STAT__SHIFT                                                         0x1f
14139 #define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT_MASK                                                  0x00000800L
14140 #define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT_MASK                                                       0x00004000L
14141 #define CP_INT_STATUS_RING1__GPF_INT_STAT_MASK                                                                0x00010000L
14142 #define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT_MASK                                                   0x00020000L
14143 #define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT_MASK                                                           0x00040000L
14144 #define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT_MASK                                                          0x00080000L
14145 #define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT_MASK                                                         0x00100000L
14146 #define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT_MASK                                                           0x00200000L
14147 #define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT_MASK                                                         0x00400000L
14148 #define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT_MASK                                                           0x00800000L
14149 #define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT_MASK                                                       0x01000000L
14150 #define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT_MASK                                                         0x04000000L
14151 #define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT_MASK                                                 0x08000000L
14152 #define CP_INT_STATUS_RING1__GENERIC2_INT_STAT_MASK                                                           0x20000000L
14153 #define CP_INT_STATUS_RING1__GENERIC1_INT_STAT_MASK                                                           0x40000000L
14154 #define CP_INT_STATUS_RING1__GENERIC0_INT_STAT_MASK                                                           0x80000000L
14155 //CP_INT_STATUS_RING2
14156 #define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT__SHIFT                                                0xb
14157 #define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT__SHIFT                                                     0xe
14158 #define CP_INT_STATUS_RING2__GPF_INT_STAT__SHIFT                                                              0x10
14159 #define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT__SHIFT                                                 0x11
14160 #define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT__SHIFT                                                         0x12
14161 #define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT__SHIFT                                                        0x13
14162 #define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT__SHIFT                                                       0x14
14163 #define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT__SHIFT                                                         0x15
14164 #define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT__SHIFT                                                       0x16
14165 #define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT__SHIFT                                                         0x17
14166 #define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT__SHIFT                                                     0x18
14167 #define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT__SHIFT                                                       0x1a
14168 #define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT__SHIFT                                               0x1b
14169 #define CP_INT_STATUS_RING2__GENERIC2_INT_STAT__SHIFT                                                         0x1d
14170 #define CP_INT_STATUS_RING2__GENERIC1_INT_STAT__SHIFT                                                         0x1e
14171 #define CP_INT_STATUS_RING2__GENERIC0_INT_STAT__SHIFT                                                         0x1f
14172 #define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT_MASK                                                  0x00000800L
14173 #define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT_MASK                                                       0x00004000L
14174 #define CP_INT_STATUS_RING2__GPF_INT_STAT_MASK                                                                0x00010000L
14175 #define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT_MASK                                                   0x00020000L
14176 #define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT_MASK                                                           0x00040000L
14177 #define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT_MASK                                                          0x00080000L
14178 #define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT_MASK                                                         0x00100000L
14179 #define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT_MASK                                                           0x00200000L
14180 #define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT_MASK                                                         0x00400000L
14181 #define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT_MASK                                                           0x00800000L
14182 #define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT_MASK                                                       0x01000000L
14183 #define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT_MASK                                                         0x04000000L
14184 #define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT_MASK                                                 0x08000000L
14185 #define CP_INT_STATUS_RING2__GENERIC2_INT_STAT_MASK                                                           0x20000000L
14186 #define CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK                                                           0x40000000L
14187 #define CP_INT_STATUS_RING2__GENERIC0_INT_STAT_MASK                                                           0x80000000L
14188 //CP_ME_F32_INTERRUPT
14189 #define CP_ME_F32_INTERRUPT__ECC_ERROR_INT__SHIFT                                                             0x0
14190 #define CP_ME_F32_INTERRUPT__TIME_STAMP_INT__SHIFT                                                            0x1
14191 #define CP_ME_F32_INTERRUPT__ME_F32_INT_2__SHIFT                                                              0x2
14192 #define CP_ME_F32_INTERRUPT__ME_F32_INT_3__SHIFT                                                              0x3
14193 #define CP_ME_F32_INTERRUPT__ECC_ERROR_INT_MASK                                                               0x00000001L
14194 #define CP_ME_F32_INTERRUPT__TIME_STAMP_INT_MASK                                                              0x00000002L
14195 #define CP_ME_F32_INTERRUPT__ME_F32_INT_2_MASK                                                                0x00000004L
14196 #define CP_ME_F32_INTERRUPT__ME_F32_INT_3_MASK                                                                0x00000008L
14197 //CP_PFP_F32_INTERRUPT
14198 #define CP_PFP_F32_INTERRUPT__ECC_ERROR_INT__SHIFT                                                            0x0
14199 #define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT                                                             0x1
14200 #define CP_PFP_F32_INTERRUPT__RESERVED_BIT_ERR_INT__SHIFT                                                     0x2
14201 #define CP_PFP_F32_INTERRUPT__PFP_F32_INT_3__SHIFT                                                            0x3
14202 #define CP_PFP_F32_INTERRUPT__ECC_ERROR_INT_MASK                                                              0x00000001L
14203 #define CP_PFP_F32_INTERRUPT__PRIV_REG_INT_MASK                                                               0x00000002L
14204 #define CP_PFP_F32_INTERRUPT__RESERVED_BIT_ERR_INT_MASK                                                       0x00000004L
14205 #define CP_PFP_F32_INTERRUPT__PFP_F32_INT_3_MASK                                                              0x00000008L
14206 //CP_CE_F32_INTERRUPT
14207 #define CP_CE_F32_INTERRUPT__ECC_ERROR_INT__SHIFT                                                             0x0
14208 #define CP_CE_F32_INTERRUPT__RESERVED_BIT_ERR_INT__SHIFT                                                      0x1
14209 #define CP_CE_F32_INTERRUPT__CE_F32_INT_2__SHIFT                                                              0x2
14210 #define CP_CE_F32_INTERRUPT__CE_F32_INT_3__SHIFT                                                              0x3
14211 #define CP_CE_F32_INTERRUPT__ECC_ERROR_INT_MASK                                                               0x00000001L
14212 #define CP_CE_F32_INTERRUPT__RESERVED_BIT_ERR_INT_MASK                                                        0x00000002L
14213 #define CP_CE_F32_INTERRUPT__CE_F32_INT_2_MASK                                                                0x00000004L
14214 #define CP_CE_F32_INTERRUPT__CE_F32_INT_3_MASK                                                                0x00000008L
14215 //CP_MEC1_F32_INTERRUPT
14216 #define CP_MEC1_F32_INTERRUPT__EDC_ROQ_FED_INT__SHIFT                                                         0x0
14217 #define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT__SHIFT                                                            0x1
14218 #define CP_MEC1_F32_INTERRUPT__RESERVED_BIT_ERR_INT__SHIFT                                                    0x2
14219 #define CP_MEC1_F32_INTERRUPT__EDC_TC_FED_INT__SHIFT                                                          0x3
14220 #define CP_MEC1_F32_INTERRUPT__EDC_GDS_FED_INT__SHIFT                                                         0x4
14221 #define CP_MEC1_F32_INTERRUPT__EDC_SCRATCH_FED_INT__SHIFT                                                     0x5
14222 #define CP_MEC1_F32_INTERRUPT__WAVE_RESTORE_INT__SHIFT                                                        0x6
14223 #define CP_MEC1_F32_INTERRUPT__SUA_VIOLATION_INT__SHIFT                                                       0x7
14224 #define CP_MEC1_F32_INTERRUPT__EDC_DMA_FED_INT__SHIFT                                                         0x8
14225 #define CP_MEC1_F32_INTERRUPT__IQ_TIMER_INT__SHIFT                                                            0x9
14226 #define CP_MEC1_F32_INTERRUPT__GPF_INT_CPF__SHIFT                                                             0xa
14227 #define CP_MEC1_F32_INTERRUPT__GPF_INT_DMA__SHIFT                                                             0xb
14228 #define CP_MEC1_F32_INTERRUPT__GPF_INT_CPC__SHIFT                                                             0xc
14229 #define CP_MEC1_F32_INTERRUPT__EDC_SR_MEM_FED_INT__SHIFT                                                      0xd
14230 #define CP_MEC1_F32_INTERRUPT__QUEUE_MESSAGE_INT__SHIFT                                                       0xe
14231 #define CP_MEC1_F32_INTERRUPT__FATAL_EDC_ERROR_INT__SHIFT                                                     0xf
14232 #define CP_MEC1_F32_INTERRUPT__EDC_ROQ_FED_INT_MASK                                                           0x00000001L
14233 #define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT_MASK                                                              0x00000002L
14234 #define CP_MEC1_F32_INTERRUPT__RESERVED_BIT_ERR_INT_MASK                                                      0x00000004L
14235 #define CP_MEC1_F32_INTERRUPT__EDC_TC_FED_INT_MASK                                                            0x00000008L
14236 #define CP_MEC1_F32_INTERRUPT__EDC_GDS_FED_INT_MASK                                                           0x00000010L
14237 #define CP_MEC1_F32_INTERRUPT__EDC_SCRATCH_FED_INT_MASK                                                       0x00000020L
14238 #define CP_MEC1_F32_INTERRUPT__WAVE_RESTORE_INT_MASK                                                          0x00000040L
14239 #define CP_MEC1_F32_INTERRUPT__SUA_VIOLATION_INT_MASK                                                         0x00000080L
14240 #define CP_MEC1_F32_INTERRUPT__EDC_DMA_FED_INT_MASK                                                           0x00000100L
14241 #define CP_MEC1_F32_INTERRUPT__IQ_TIMER_INT_MASK                                                              0x00000200L
14242 #define CP_MEC1_F32_INTERRUPT__GPF_INT_CPF_MASK                                                               0x00000400L
14243 #define CP_MEC1_F32_INTERRUPT__GPF_INT_DMA_MASK                                                               0x00000800L
14244 #define CP_MEC1_F32_INTERRUPT__GPF_INT_CPC_MASK                                                               0x00001000L
14245 #define CP_MEC1_F32_INTERRUPT__EDC_SR_MEM_FED_INT_MASK                                                        0x00002000L
14246 #define CP_MEC1_F32_INTERRUPT__QUEUE_MESSAGE_INT_MASK                                                         0x00004000L
14247 #define CP_MEC1_F32_INTERRUPT__FATAL_EDC_ERROR_INT_MASK                                                       0x00008000L
14248 //CP_MEC2_F32_INTERRUPT
14249 #define CP_MEC2_F32_INTERRUPT__EDC_ROQ_FED_INT__SHIFT                                                         0x0
14250 #define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT__SHIFT                                                            0x1
14251 #define CP_MEC2_F32_INTERRUPT__RESERVED_BIT_ERR_INT__SHIFT                                                    0x2
14252 #define CP_MEC2_F32_INTERRUPT__EDC_TC_FED_INT__SHIFT                                                          0x3
14253 #define CP_MEC2_F32_INTERRUPT__EDC_GDS_FED_INT__SHIFT                                                         0x4
14254 #define CP_MEC2_F32_INTERRUPT__EDC_SCRATCH_FED_INT__SHIFT                                                     0x5
14255 #define CP_MEC2_F32_INTERRUPT__WAVE_RESTORE_INT__SHIFT                                                        0x6
14256 #define CP_MEC2_F32_INTERRUPT__SUA_VIOLATION_INT__SHIFT                                                       0x7
14257 #define CP_MEC2_F32_INTERRUPT__EDC_DMA_FED_INT__SHIFT                                                         0x8
14258 #define CP_MEC2_F32_INTERRUPT__IQ_TIMER_INT__SHIFT                                                            0x9
14259 #define CP_MEC2_F32_INTERRUPT__GPF_INT_CPF__SHIFT                                                             0xa
14260 #define CP_MEC2_F32_INTERRUPT__GPF_INT_DMA__SHIFT                                                             0xb
14261 #define CP_MEC2_F32_INTERRUPT__GPF_INT_CPC__SHIFT                                                             0xc
14262 #define CP_MEC2_F32_INTERRUPT__EDC_SR_MEM_FED_INT__SHIFT                                                      0xd
14263 #define CP_MEC2_F32_INTERRUPT__QUEUE_MESSAGE_INT__SHIFT                                                       0xe
14264 #define CP_MEC2_F32_INTERRUPT__FATAL_EDC_ERROR_INT__SHIFT                                                     0xf
14265 #define CP_MEC2_F32_INTERRUPT__EDC_ROQ_FED_INT_MASK                                                           0x00000001L
14266 #define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT_MASK                                                              0x00000002L
14267 #define CP_MEC2_F32_INTERRUPT__RESERVED_BIT_ERR_INT_MASK                                                      0x00000004L
14268 #define CP_MEC2_F32_INTERRUPT__EDC_TC_FED_INT_MASK                                                            0x00000008L
14269 #define CP_MEC2_F32_INTERRUPT__EDC_GDS_FED_INT_MASK                                                           0x00000010L
14270 #define CP_MEC2_F32_INTERRUPT__EDC_SCRATCH_FED_INT_MASK                                                       0x00000020L
14271 #define CP_MEC2_F32_INTERRUPT__WAVE_RESTORE_INT_MASK                                                          0x00000040L
14272 #define CP_MEC2_F32_INTERRUPT__SUA_VIOLATION_INT_MASK                                                         0x00000080L
14273 #define CP_MEC2_F32_INTERRUPT__EDC_DMA_FED_INT_MASK                                                           0x00000100L
14274 #define CP_MEC2_F32_INTERRUPT__IQ_TIMER_INT_MASK                                                              0x00000200L
14275 #define CP_MEC2_F32_INTERRUPT__GPF_INT_CPF_MASK                                                               0x00000400L
14276 #define CP_MEC2_F32_INTERRUPT__GPF_INT_DMA_MASK                                                               0x00000800L
14277 #define CP_MEC2_F32_INTERRUPT__GPF_INT_CPC_MASK                                                               0x00001000L
14278 #define CP_MEC2_F32_INTERRUPT__EDC_SR_MEM_FED_INT_MASK                                                        0x00002000L
14279 #define CP_MEC2_F32_INTERRUPT__QUEUE_MESSAGE_INT_MASK                                                         0x00004000L
14280 #define CP_MEC2_F32_INTERRUPT__FATAL_EDC_ERROR_INT_MASK                                                       0x00008000L
14281 //CP_PWR_CNTL
14282 #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0__SHIFT                                                            0x0
14283 #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1__SHIFT                                                            0x1
14284 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0__SHIFT                                                            0x8
14285 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT                                                            0x9
14286 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2__SHIFT                                                            0xa
14287 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3__SHIFT                                                            0xb
14288 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0__SHIFT                                                            0x10
14289 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1__SHIFT                                                            0x11
14290 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2__SHIFT                                                            0x12
14291 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3__SHIFT                                                            0x13
14292 #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0_MASK                                                              0x00000001L
14293 #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK                                                              0x00000002L
14294 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0_MASK                                                              0x00000100L
14295 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1_MASK                                                              0x00000200L
14296 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2_MASK                                                              0x00000400L
14297 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3_MASK                                                              0x00000800L
14298 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0_MASK                                                              0x00010000L
14299 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1_MASK                                                              0x00020000L
14300 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2_MASK                                                              0x00040000L
14301 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3_MASK                                                              0x00080000L
14302 //CP_MEM_SLP_CNTL
14303 #define CP_MEM_SLP_CNTL__CP_MEM_LS_EN__SHIFT                                                                  0x0
14304 #define CP_MEM_SLP_CNTL__CP_MEM_DS_EN__SHIFT                                                                  0x1
14305 #define CP_MEM_SLP_CNTL__RESERVED__SHIFT                                                                      0x2
14306 #define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE__SHIFT                                                        0x7
14307 #define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY__SHIFT                                                            0x8
14308 #define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY__SHIFT                                                           0x10
14309 #define CP_MEM_SLP_CNTL__RESERVED1__SHIFT                                                                     0x18
14310 #define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK                                                                    0x00000001L
14311 #define CP_MEM_SLP_CNTL__CP_MEM_DS_EN_MASK                                                                    0x00000002L
14312 #define CP_MEM_SLP_CNTL__RESERVED_MASK                                                                        0x0000007CL
14313 #define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE_MASK                                                          0x00000080L
14314 #define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY_MASK                                                              0x0000FF00L
14315 #define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY_MASK                                                             0x00FF0000L
14316 #define CP_MEM_SLP_CNTL__RESERVED1_MASK                                                                       0xFF000000L
14317 //CP_ECC_DMA_FIRST_OCCURRENCE
14318 #define CP_ECC_DMA_FIRST_OCCURRENCE__INTERFACE__SHIFT                                                         0x0
14319 #define CP_ECC_DMA_FIRST_OCCURRENCE__CLIENT__SHIFT                                                            0x4
14320 #define CP_ECC_DMA_FIRST_OCCURRENCE__ME__SHIFT                                                                0x8
14321 #define CP_ECC_DMA_FIRST_OCCURRENCE__PIPE__SHIFT                                                              0xa
14322 #define CP_ECC_DMA_FIRST_OCCURRENCE__VMID__SHIFT                                                              0x10
14323 #define CP_ECC_DMA_FIRST_OCCURRENCE__INTERFACE_MASK                                                           0x00000003L
14324 #define CP_ECC_DMA_FIRST_OCCURRENCE__CLIENT_MASK                                                              0x000000F0L
14325 #define CP_ECC_DMA_FIRST_OCCURRENCE__ME_MASK                                                                  0x00000300L
14326 #define CP_ECC_DMA_FIRST_OCCURRENCE__PIPE_MASK                                                                0x00000C00L
14327 #define CP_ECC_DMA_FIRST_OCCURRENCE__VMID_MASK                                                                0x000F0000L
14328 //CP_ECC_FIRSTOCCURRENCE
14329 #define CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT                                                              0x0
14330 #define CP_ECC_FIRSTOCCURRENCE__CLIENT__SHIFT                                                                 0x4
14331 #define CP_ECC_FIRSTOCCURRENCE__ME__SHIFT                                                                     0x8
14332 #define CP_ECC_FIRSTOCCURRENCE__PIPE__SHIFT                                                                   0xa
14333 #define CP_ECC_FIRSTOCCURRENCE__QUEUE__SHIFT                                                                  0xc
14334 #define CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT                                                                   0x10
14335 #define CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK                                                                0x00000003L
14336 #define CP_ECC_FIRSTOCCURRENCE__CLIENT_MASK                                                                   0x000000F0L
14337 #define CP_ECC_FIRSTOCCURRENCE__ME_MASK                                                                       0x00000300L
14338 #define CP_ECC_FIRSTOCCURRENCE__PIPE_MASK                                                                     0x00000C00L
14339 #define CP_ECC_FIRSTOCCURRENCE__QUEUE_MASK                                                                    0x00007000L
14340 #define CP_ECC_FIRSTOCCURRENCE__VMID_MASK                                                                     0x000F0000L
14341 //CP_ECC_FIRSTOCCURRENCE_RING0
14342 #define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE__SHIFT                                                         0x0
14343 #define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE_MASK                                                           0xFFFFFFFFL
14344 //CP_ECC_FIRSTOCCURRENCE_RING1
14345 #define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE__SHIFT                                                         0x0
14346 #define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE_MASK                                                           0xFFFFFFFFL
14347 //CP_ECC_FIRSTOCCURRENCE_RING2
14348 #define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE__SHIFT                                                         0x0
14349 #define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE_MASK                                                           0xFFFFFFFFL
14350 //GB_EDC_MODE
14351 #define GB_EDC_MODE__FORCE_SEC_ON_DED__SHIFT                                                                  0xf
14352 #define GB_EDC_MODE__COUNT_FED_OUT__SHIFT                                                                     0x10
14353 #define GB_EDC_MODE__GATE_FUE__SHIFT                                                                          0x11
14354 #define GB_EDC_MODE__DED_MODE__SHIFT                                                                          0x14
14355 #define GB_EDC_MODE__PROP_FED__SHIFT                                                                          0x1d
14356 #define GB_EDC_MODE__BYPASS__SHIFT                                                                            0x1f
14357 #define GB_EDC_MODE__FORCE_SEC_ON_DED_MASK                                                                    0x00008000L
14358 #define GB_EDC_MODE__COUNT_FED_OUT_MASK                                                                       0x00010000L
14359 #define GB_EDC_MODE__GATE_FUE_MASK                                                                            0x00020000L
14360 #define GB_EDC_MODE__DED_MODE_MASK                                                                            0x00300000L
14361 #define GB_EDC_MODE__PROP_FED_MASK                                                                            0x20000000L
14362 #define GB_EDC_MODE__BYPASS_MASK                                                                              0x80000000L
14363 //CP_DEBUG
14364 #define CP_DEBUG__CPG_REPEATER_FGCG_OVERRIDE__SHIFT                                                           0x9
14365 #define CP_DEBUG__CPG_RAM_CLK_GATING_DISABLE__SHIFT                                                           0xe
14366 #define CP_DEBUG__DISABLE_GFX_HALT_ON_UTCL1_ERROR__SHIFT                                                      0xf
14367 #define CP_DEBUG__SURFSYNC_CNTX_RDADDR__SHIFT                                                                 0x10
14368 #define CP_DEBUG__BUSY_EXTENDER__SHIFT                                                                        0x13
14369 #define CP_DEBUG__PRIV_REG_INTERRUPT_ENABLE__SHIFT                                                            0x15
14370 #define CP_DEBUG__INTERRUPT_ENABLE__SHIFT                                                                     0x16
14371 #define CP_DEBUG__PREDICATE_DISABLE__SHIFT                                                                    0x17
14372 #define CP_DEBUG__UNDERFLOW_BUSY_DISABLE__SHIFT                                                               0x18
14373 #define CP_DEBUG__OVERFLOW_BUSY_DISABLE__SHIFT                                                                0x19
14374 #define CP_DEBUG__EVENT_FILT_DISABLE__SHIFT                                                                   0x1a
14375 #define CP_DEBUG__CPG_TC_MTYPE_OVERRIDE__SHIFT                                                                0x1b
14376 #define CP_DEBUG__CPG_TC_ONE_CYCLE_WRITE_DISABLE__SHIFT                                                       0x1c
14377 #define CP_DEBUG__CS_STATE_FILT_DISABLE__SHIFT                                                                0x1d
14378 #define CP_DEBUG__CS_PIPELINE_RESET_DISABLE__SHIFT                                                            0x1e
14379 #define CP_DEBUG__IB_PACKET_INJECTOR_DISABLE__SHIFT                                                           0x1f
14380 #define CP_DEBUG__CPG_REPEATER_FGCG_OVERRIDE_MASK                                                             0x00000200L
14381 #define CP_DEBUG__CPG_RAM_CLK_GATING_DISABLE_MASK                                                             0x00004000L
14382 #define CP_DEBUG__DISABLE_GFX_HALT_ON_UTCL1_ERROR_MASK                                                        0x00008000L
14383 #define CP_DEBUG__SURFSYNC_CNTX_RDADDR_MASK                                                                   0x00070000L
14384 #define CP_DEBUG__BUSY_EXTENDER_MASK                                                                          0x00180000L
14385 #define CP_DEBUG__PRIV_REG_INTERRUPT_ENABLE_MASK                                                              0x00200000L
14386 #define CP_DEBUG__INTERRUPT_ENABLE_MASK                                                                       0x00400000L
14387 #define CP_DEBUG__PREDICATE_DISABLE_MASK                                                                      0x00800000L
14388 #define CP_DEBUG__UNDERFLOW_BUSY_DISABLE_MASK                                                                 0x01000000L
14389 #define CP_DEBUG__OVERFLOW_BUSY_DISABLE_MASK                                                                  0x02000000L
14390 #define CP_DEBUG__EVENT_FILT_DISABLE_MASK                                                                     0x04000000L
14391 #define CP_DEBUG__CPG_TC_MTYPE_OVERRIDE_MASK                                                                  0x08000000L
14392 #define CP_DEBUG__CPG_TC_ONE_CYCLE_WRITE_DISABLE_MASK                                                         0x10000000L
14393 #define CP_DEBUG__CS_STATE_FILT_DISABLE_MASK                                                                  0x20000000L
14394 #define CP_DEBUG__CS_PIPELINE_RESET_DISABLE_MASK                                                              0x40000000L
14395 #define CP_DEBUG__IB_PACKET_INJECTOR_DISABLE_MASK                                                             0x80000000L
14396 //CP_CPF_DEBUG
14397 #define CP_CPF_DEBUG__QUE_MANAGER_CLR_DBELLUPD_DIS__SHIFT                                                     0x6
14398 #define CP_CPF_DEBUG__CPF_REPEATER_FGCG_OVERRIDE__SHIFT                                                       0x10
14399 #define CP_CPF_DEBUG__CPF_RAM_CLK_GATING_DISABLE__SHIFT                                                       0x12
14400 #define CP_CPF_DEBUG__BUSY_EXTENDER__SHIFT                                                                    0x13
14401 #define CP_CPF_DEBUG__UNDERFLOW_BUSY_DISABLE__SHIFT                                                           0x18
14402 #define CP_CPF_DEBUG__OVERFLOW_BUSY_DISABLE__SHIFT                                                            0x19
14403 #define CP_CPF_DEBUG__CPF_PRIORITY_YIELD_ACTIVE_DIS__SHIFT                                                    0x1d
14404 #define CP_CPF_DEBUG__CPF_TC_MTYPE_OVERRIDE__SHIFT                                                            0x1e
14405 #define CP_CPF_DEBUG__DBGU_TRIGGER__SHIFT                                                                     0x1f
14406 #define CP_CPF_DEBUG__QUE_MANAGER_CLR_DBELLUPD_DIS_MASK                                                       0x00000040L
14407 #define CP_CPF_DEBUG__CPF_REPEATER_FGCG_OVERRIDE_MASK                                                         0x00010000L
14408 #define CP_CPF_DEBUG__CPF_RAM_CLK_GATING_DISABLE_MASK                                                         0x00040000L
14409 #define CP_CPF_DEBUG__BUSY_EXTENDER_MASK                                                                      0x00180000L
14410 #define CP_CPF_DEBUG__UNDERFLOW_BUSY_DISABLE_MASK                                                             0x01000000L
14411 #define CP_CPF_DEBUG__OVERFLOW_BUSY_DISABLE_MASK                                                              0x02000000L
14412 #define CP_CPF_DEBUG__CPF_PRIORITY_YIELD_ACTIVE_DIS_MASK                                                      0x20000000L
14413 #define CP_CPF_DEBUG__CPF_TC_MTYPE_OVERRIDE_MASK                                                              0x40000000L
14414 #define CP_CPF_DEBUG__DBGU_TRIGGER_MASK                                                                       0x80000000L
14415 //CP_CPC_DEBUG
14416 #define CP_CPC_DEBUG__CPC_PIPE_SEL__SHIFT                                                                     0x0
14417 #define CP_CPC_DEBUG__CPC_ROLLOVER_EVENT_DEBUG_EN__SHIFT                                                      0x3
14418 #define CP_CPC_DEBUG__CPC_HARVESTING_CONTINUE_DISABLE__SHIFT                                                  0xb
14419 #define CP_CPC_DEBUG__CPC_HARVESTING_RELAUNCH_DISABLE__SHIFT                                                  0xc
14420 #define CP_CPC_DEBUG__CPC_HARVEST_AUTO_DISABLE__SHIFT                                                         0xd
14421 #define CP_CPC_DEBUG__CPC_HARVESTING_DISPATCH_DISABLE__SHIFT                                                  0xe
14422 #define CP_CPC_DEBUG__CPC_REPEATER_FGCG_OVERRIDE__SHIFT                                                       0xf
14423 #define CP_CPC_DEBUG__CPC_RAM_CLK_GATING_DISABLE__SHIFT                                                       0x12
14424 #define CP_CPC_DEBUG__BUSY_EXTENDER__SHIFT                                                                    0x13
14425 #define CP_CPC_DEBUG__UCODE_ECC_ERROR_DISABLE__SHIFT                                                          0x15
14426 #define CP_CPC_DEBUG__RESERVED_INTERRUPT_ENABLE__SHIFT                                                        0x16
14427 #define CP_CPC_DEBUG__RESTORE_FIFO_EMPTY_SEL__SHIFT                                                           0x17
14428 #define CP_CPC_DEBUG__UNDERFLOW_BUSY_DISABLE__SHIFT                                                           0x18
14429 #define CP_CPC_DEBUG__OVERFLOW_BUSY_DISABLE__SHIFT                                                            0x19
14430 #define CP_CPC_DEBUG__EVENT_FILT_DISABLE__SHIFT                                                               0x1a
14431 #define CP_CPC_DEBUG__PRIV_REG_INTERRUPT_ENABLE__SHIFT                                                        0x1b
14432 #define CP_CPC_DEBUG__CPC_TC_ONE_CYCLE_WRITE_DISABLE__SHIFT                                                   0x1c
14433 #define CP_CPC_DEBUG__CS_STATE_FILT_DISABLE__SHIFT                                                            0x1d
14434 #define CP_CPC_DEBUG__ME2_UCODE_RAM_ENABLE__SHIFT                                                             0x1f
14435 #define CP_CPC_DEBUG__CPC_PIPE_SEL_MASK                                                                       0x00000003L
14436 #define CP_CPC_DEBUG__CPC_ROLLOVER_EVENT_DEBUG_EN_MASK                                                        0x00000008L
14437 #define CP_CPC_DEBUG__CPC_HARVESTING_CONTINUE_DISABLE_MASK                                                    0x00000800L
14438 #define CP_CPC_DEBUG__CPC_HARVESTING_RELAUNCH_DISABLE_MASK                                                    0x00001000L
14439 #define CP_CPC_DEBUG__CPC_HARVEST_AUTO_DISABLE_MASK                                                           0x00002000L
14440 #define CP_CPC_DEBUG__CPC_HARVESTING_DISPATCH_DISABLE_MASK                                                    0x00004000L
14441 #define CP_CPC_DEBUG__CPC_REPEATER_FGCG_OVERRIDE_MASK                                                         0x00008000L
14442 #define CP_CPC_DEBUG__CPC_RAM_CLK_GATING_DISABLE_MASK                                                         0x00040000L
14443 #define CP_CPC_DEBUG__BUSY_EXTENDER_MASK                                                                      0x00180000L
14444 #define CP_CPC_DEBUG__UCODE_ECC_ERROR_DISABLE_MASK                                                            0x00200000L
14445 #define CP_CPC_DEBUG__RESERVED_INTERRUPT_ENABLE_MASK                                                          0x00400000L
14446 #define CP_CPC_DEBUG__RESTORE_FIFO_EMPTY_SEL_MASK                                                             0x00800000L
14447 #define CP_CPC_DEBUG__UNDERFLOW_BUSY_DISABLE_MASK                                                             0x01000000L
14448 #define CP_CPC_DEBUG__OVERFLOW_BUSY_DISABLE_MASK                                                              0x02000000L
14449 #define CP_CPC_DEBUG__EVENT_FILT_DISABLE_MASK                                                                 0x04000000L
14450 #define CP_CPC_DEBUG__PRIV_REG_INTERRUPT_ENABLE_MASK                                                          0x08000000L
14451 #define CP_CPC_DEBUG__CPC_TC_ONE_CYCLE_WRITE_DISABLE_MASK                                                     0x10000000L
14452 #define CP_CPC_DEBUG__CS_STATE_FILT_DISABLE_MASK                                                              0x20000000L
14453 #define CP_CPC_DEBUG__ME2_UCODE_RAM_ENABLE_MASK                                                               0x80000000L
14454 //CP_CPC_DEBUG_2
14455 #define CP_CPC_DEBUG_2__DC_GD_PIPE3_QSWITCH_CNT__SHIFT                                                        0x0
14456 #define CP_CPC_DEBUG_2__DC_GD_PIPE2_QSWITCH_CNT__SHIFT                                                        0x8
14457 #define CP_CPC_DEBUG_2__DC_GD_PIPE1_QSWITCH_CNT__SHIFT                                                        0x10
14458 #define CP_CPC_DEBUG_2__DC_GD_PIPE0_QSWITCH_CNT__SHIFT                                                        0x18
14459 #define CP_CPC_DEBUG_2__DC_GD_PIPE3_QSWITCH_CNT_MASK                                                          0x000000FFL
14460 #define CP_CPC_DEBUG_2__DC_GD_PIPE2_QSWITCH_CNT_MASK                                                          0x0000FF00L
14461 #define CP_CPC_DEBUG_2__DC_GD_PIPE1_QSWITCH_CNT_MASK                                                          0x00FF0000L
14462 #define CP_CPC_DEBUG_2__DC_GD_PIPE0_QSWITCH_CNT_MASK                                                          0xFF000000L
14463 //CP_PQ_WPTR_POLL_CNTL
14464 #define CP_PQ_WPTR_POLL_CNTL__PERIOD__SHIFT                                                                   0x0
14465 #define CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT__SHIFT                                                0x1d
14466 #define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE__SHIFT                                                              0x1e
14467 #define CP_PQ_WPTR_POLL_CNTL__EN__SHIFT                                                                       0x1f
14468 #define CP_PQ_WPTR_POLL_CNTL__PERIOD_MASK                                                                     0x000000FFL
14469 #define CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT_MASK                                                  0x20000000L
14470 #define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE_MASK                                                                0x40000000L
14471 #define CP_PQ_WPTR_POLL_CNTL__EN_MASK                                                                         0x80000000L
14472 //CP_PQ_WPTR_POLL_CNTL1
14473 #define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK__SHIFT                                                              0x0
14474 #define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK_MASK                                                                0xFFFFFFFFL
14475 //CP_ME1_PIPE0_INT_CNTL
14476 #define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT                                             0xc
14477 #define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT                                              0xd
14478 #define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                 0xe
14479 #define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT                                                0xf
14480 #define CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE__SHIFT                                                          0x10
14481 #define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                             0x11
14482 #define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT                                                     0x17
14483 #define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT                                                 0x18
14484 #define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT                                                   0x1a
14485 #define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                           0x1b
14486 #define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT                                                     0x1d
14487 #define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT                                                     0x1e
14488 #define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT                                                     0x1f
14489 #define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK                                               0x00001000L
14490 #define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK                                                0x00002000L
14491 #define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK                                                   0x00004000L
14492 #define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK                                                  0x00008000L
14493 #define CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE_MASK                                                            0x00010000L
14494 #define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                               0x00020000L
14495 #define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK                                                       0x00800000L
14496 #define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK                                                   0x01000000L
14497 #define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK                                                     0x04000000L
14498 #define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                             0x08000000L
14499 #define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK                                                       0x20000000L
14500 #define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK                                                       0x40000000L
14501 #define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK                                                       0x80000000L
14502 //CP_ME1_PIPE1_INT_CNTL
14503 #define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT                                             0xc
14504 #define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT                                              0xd
14505 #define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                 0xe
14506 #define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT                                                0xf
14507 #define CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE__SHIFT                                                          0x10
14508 #define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                             0x11
14509 #define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT                                                     0x17
14510 #define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT                                                 0x18
14511 #define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT                                                   0x1a
14512 #define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                           0x1b
14513 #define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT                                                     0x1d
14514 #define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT                                                     0x1e
14515 #define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT                                                     0x1f
14516 #define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK                                               0x00001000L
14517 #define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK                                                0x00002000L
14518 #define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK                                                   0x00004000L
14519 #define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK                                                  0x00008000L
14520 #define CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE_MASK                                                            0x00010000L
14521 #define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                               0x00020000L
14522 #define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK                                                       0x00800000L
14523 #define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK                                                   0x01000000L
14524 #define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK                                                     0x04000000L
14525 #define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                             0x08000000L
14526 #define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK                                                       0x20000000L
14527 #define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK                                                       0x40000000L
14528 #define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK                                                       0x80000000L
14529 //CP_ME1_PIPE2_INT_CNTL
14530 #define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT                                             0xc
14531 #define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT                                              0xd
14532 #define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                 0xe
14533 #define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT                                                0xf
14534 #define CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE__SHIFT                                                          0x10
14535 #define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                             0x11
14536 #define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT                                                     0x17
14537 #define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT                                                 0x18
14538 #define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT                                                   0x1a
14539 #define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                           0x1b
14540 #define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT                                                     0x1d
14541 #define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT                                                     0x1e
14542 #define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT                                                     0x1f
14543 #define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK                                               0x00001000L
14544 #define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK                                                0x00002000L
14545 #define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK                                                   0x00004000L
14546 #define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK                                                  0x00008000L
14547 #define CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE_MASK                                                            0x00010000L
14548 #define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                               0x00020000L
14549 #define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK                                                       0x00800000L
14550 #define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK                                                   0x01000000L
14551 #define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK                                                     0x04000000L
14552 #define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                             0x08000000L
14553 #define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK                                                       0x20000000L
14554 #define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK                                                       0x40000000L
14555 #define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK                                                       0x80000000L
14556 //CP_ME1_PIPE3_INT_CNTL
14557 #define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT                                             0xc
14558 #define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT                                              0xd
14559 #define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                 0xe
14560 #define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT                                                0xf
14561 #define CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE__SHIFT                                                          0x10
14562 #define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                             0x11
14563 #define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT                                                     0x17
14564 #define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT                                                 0x18
14565 #define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT                                                   0x1a
14566 #define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                           0x1b
14567 #define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT                                                     0x1d
14568 #define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT                                                     0x1e
14569 #define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT                                                     0x1f
14570 #define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK                                               0x00001000L
14571 #define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK                                                0x00002000L
14572 #define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK                                                   0x00004000L
14573 #define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK                                                  0x00008000L
14574 #define CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE_MASK                                                            0x00010000L
14575 #define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                               0x00020000L
14576 #define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK                                                       0x00800000L
14577 #define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK                                                   0x01000000L
14578 #define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK                                                     0x04000000L
14579 #define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                             0x08000000L
14580 #define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK                                                       0x20000000L
14581 #define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK                                                       0x40000000L
14582 #define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK                                                       0x80000000L
14583 //CP_ME2_PIPE0_INT_CNTL
14584 #define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT                                             0xc
14585 #define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT                                              0xd
14586 #define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                 0xe
14587 #define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT                                                0xf
14588 #define CP_ME2_PIPE0_INT_CNTL__GPF_INT_ENABLE__SHIFT                                                          0x10
14589 #define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                             0x11
14590 #define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT                                                     0x17
14591 #define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT                                                 0x18
14592 #define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT                                                   0x1a
14593 #define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                           0x1b
14594 #define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT                                                     0x1d
14595 #define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT                                                     0x1e
14596 #define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT                                                     0x1f
14597 #define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK                                               0x00001000L
14598 #define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK                                                0x00002000L
14599 #define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK                                                   0x00004000L
14600 #define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK                                                  0x00008000L
14601 #define CP_ME2_PIPE0_INT_CNTL__GPF_INT_ENABLE_MASK                                                            0x00010000L
14602 #define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                               0x00020000L
14603 #define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK                                                       0x00800000L
14604 #define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK                                                   0x01000000L
14605 #define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK                                                     0x04000000L
14606 #define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                             0x08000000L
14607 #define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK                                                       0x20000000L
14608 #define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK                                                       0x40000000L
14609 #define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK                                                       0x80000000L
14610 //CP_ME2_PIPE1_INT_CNTL
14611 #define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT                                             0xc
14612 #define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT                                              0xd
14613 #define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                 0xe
14614 #define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT                                                0xf
14615 #define CP_ME2_PIPE1_INT_CNTL__GPF_INT_ENABLE__SHIFT                                                          0x10
14616 #define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                             0x11
14617 #define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT                                                     0x17
14618 #define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT                                                 0x18
14619 #define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT                                                   0x1a
14620 #define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                           0x1b
14621 #define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT                                                     0x1d
14622 #define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT                                                     0x1e
14623 #define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT                                                     0x1f
14624 #define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK                                               0x00001000L
14625 #define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK                                                0x00002000L
14626 #define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK                                                   0x00004000L
14627 #define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK                                                  0x00008000L
14628 #define CP_ME2_PIPE1_INT_CNTL__GPF_INT_ENABLE_MASK                                                            0x00010000L
14629 #define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                               0x00020000L
14630 #define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK                                                       0x00800000L
14631 #define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK                                                   0x01000000L
14632 #define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK                                                     0x04000000L
14633 #define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                             0x08000000L
14634 #define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK                                                       0x20000000L
14635 #define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK                                                       0x40000000L
14636 #define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK                                                       0x80000000L
14637 //CP_ME2_PIPE2_INT_CNTL
14638 #define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT                                             0xc
14639 #define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT                                              0xd
14640 #define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                 0xe
14641 #define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT                                                0xf
14642 #define CP_ME2_PIPE2_INT_CNTL__GPF_INT_ENABLE__SHIFT                                                          0x10
14643 #define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                             0x11
14644 #define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT                                                     0x17
14645 #define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT                                                 0x18
14646 #define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT                                                   0x1a
14647 #define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                           0x1b
14648 #define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT                                                     0x1d
14649 #define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT                                                     0x1e
14650 #define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT                                                     0x1f
14651 #define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK                                               0x00001000L
14652 #define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK                                                0x00002000L
14653 #define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK                                                   0x00004000L
14654 #define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK                                                  0x00008000L
14655 #define CP_ME2_PIPE2_INT_CNTL__GPF_INT_ENABLE_MASK                                                            0x00010000L
14656 #define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                               0x00020000L
14657 #define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK                                                       0x00800000L
14658 #define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK                                                   0x01000000L
14659 #define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK                                                     0x04000000L
14660 #define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                             0x08000000L
14661 #define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK                                                       0x20000000L
14662 #define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK                                                       0x40000000L
14663 #define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK                                                       0x80000000L
14664 //CP_ME2_PIPE3_INT_CNTL
14665 #define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT                                             0xc
14666 #define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT                                              0xd
14667 #define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                 0xe
14668 #define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT                                                0xf
14669 #define CP_ME2_PIPE3_INT_CNTL__GPF_INT_ENABLE__SHIFT                                                          0x10
14670 #define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                             0x11
14671 #define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT                                                     0x17
14672 #define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT                                                 0x18
14673 #define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT                                                   0x1a
14674 #define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                           0x1b
14675 #define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT                                                     0x1d
14676 #define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT                                                     0x1e
14677 #define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT                                                     0x1f
14678 #define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK                                               0x00001000L
14679 #define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK                                                0x00002000L
14680 #define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK                                                   0x00004000L
14681 #define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK                                                  0x00008000L
14682 #define CP_ME2_PIPE3_INT_CNTL__GPF_INT_ENABLE_MASK                                                            0x00010000L
14683 #define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                               0x00020000L
14684 #define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK                                                       0x00800000L
14685 #define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK                                                   0x01000000L
14686 #define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK                                                     0x04000000L
14687 #define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                             0x08000000L
14688 #define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK                                                       0x20000000L
14689 #define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK                                                       0x40000000L
14690 #define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK                                                       0x80000000L
14691 //CP_ME1_PIPE0_INT_STATUS
14692 #define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT                                           0xc
14693 #define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT                                            0xd
14694 #define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT                                               0xe
14695 #define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT                                              0xf
14696 #define CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS__SHIFT                                                        0x10
14697 #define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT                                           0x11
14698 #define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT                                                   0x17
14699 #define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT                                               0x18
14700 #define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT                                                 0x1a
14701 #define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT                                         0x1b
14702 #define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT                                                   0x1d
14703 #define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT                                                   0x1e
14704 #define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT                                                   0x1f
14705 #define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK                                             0x00001000L
14706 #define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK                                              0x00002000L
14707 #define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK                                                 0x00004000L
14708 #define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK                                                0x00008000L
14709 #define CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS_MASK                                                          0x00010000L
14710 #define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK                                             0x00020000L
14711 #define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK                                                     0x00800000L
14712 #define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK                                                 0x01000000L
14713 #define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK                                                   0x04000000L
14714 #define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK                                           0x08000000L
14715 #define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK                                                     0x20000000L
14716 #define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK                                                     0x40000000L
14717 #define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK                                                     0x80000000L
14718 //CP_ME1_PIPE1_INT_STATUS
14719 #define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT                                           0xc
14720 #define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT                                            0xd
14721 #define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT                                               0xe
14722 #define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT                                              0xf
14723 #define CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS__SHIFT                                                        0x10
14724 #define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT                                           0x11
14725 #define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT                                                   0x17
14726 #define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT                                               0x18
14727 #define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT                                                 0x1a
14728 #define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT                                         0x1b
14729 #define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT                                                   0x1d
14730 #define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT                                                   0x1e
14731 #define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT                                                   0x1f
14732 #define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK                                             0x00001000L
14733 #define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK                                              0x00002000L
14734 #define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK                                                 0x00004000L
14735 #define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK                                                0x00008000L
14736 #define CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS_MASK                                                          0x00010000L
14737 #define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK                                             0x00020000L
14738 #define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK                                                     0x00800000L
14739 #define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK                                                 0x01000000L
14740 #define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK                                                   0x04000000L
14741 #define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK                                           0x08000000L
14742 #define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK                                                     0x20000000L
14743 #define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK                                                     0x40000000L
14744 #define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK                                                     0x80000000L
14745 //CP_ME1_PIPE2_INT_STATUS
14746 #define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT                                           0xc
14747 #define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT                                            0xd
14748 #define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT                                               0xe
14749 #define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT                                              0xf
14750 #define CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS__SHIFT                                                        0x10
14751 #define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT                                           0x11
14752 #define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT                                                   0x17
14753 #define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT                                               0x18
14754 #define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT                                                 0x1a
14755 #define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT                                         0x1b
14756 #define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT                                                   0x1d
14757 #define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT                                                   0x1e
14758 #define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT                                                   0x1f
14759 #define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK                                             0x00001000L
14760 #define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK                                              0x00002000L
14761 #define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK                                                 0x00004000L
14762 #define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK                                                0x00008000L
14763 #define CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS_MASK                                                          0x00010000L
14764 #define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK                                             0x00020000L
14765 #define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK                                                     0x00800000L
14766 #define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK                                                 0x01000000L
14767 #define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK                                                   0x04000000L
14768 #define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK                                           0x08000000L
14769 #define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK                                                     0x20000000L
14770 #define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK                                                     0x40000000L
14771 #define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK                                                     0x80000000L
14772 //CP_ME1_PIPE3_INT_STATUS
14773 #define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT                                           0xc
14774 #define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT                                            0xd
14775 #define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT                                               0xe
14776 #define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT                                              0xf
14777 #define CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS__SHIFT                                                        0x10
14778 #define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT                                           0x11
14779 #define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT                                                   0x17
14780 #define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT                                               0x18
14781 #define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT                                                 0x1a
14782 #define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT                                         0x1b
14783 #define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT                                                   0x1d
14784 #define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT                                                   0x1e
14785 #define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT                                                   0x1f
14786 #define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK                                             0x00001000L
14787 #define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK                                              0x00002000L
14788 #define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK                                                 0x00004000L
14789 #define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK                                                0x00008000L
14790 #define CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS_MASK                                                          0x00010000L
14791 #define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK                                             0x00020000L
14792 #define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK                                                     0x00800000L
14793 #define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK                                                 0x01000000L
14794 #define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK                                                   0x04000000L
14795 #define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK                                           0x08000000L
14796 #define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK                                                     0x20000000L
14797 #define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK                                                     0x40000000L
14798 #define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK                                                     0x80000000L
14799 //CP_ME2_PIPE0_INT_STATUS
14800 #define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT                                           0xc
14801 #define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT                                            0xd
14802 #define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT                                               0xe
14803 #define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT                                              0xf
14804 #define CP_ME2_PIPE0_INT_STATUS__GPF_INT_STATUS__SHIFT                                                        0x10
14805 #define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT                                           0x11
14806 #define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT                                                   0x17
14807 #define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT                                               0x18
14808 #define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT                                                 0x1a
14809 #define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT                                         0x1b
14810 #define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT                                                   0x1d
14811 #define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT                                                   0x1e
14812 #define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT                                                   0x1f
14813 #define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK                                             0x00001000L
14814 #define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK                                              0x00002000L
14815 #define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK                                                 0x00004000L
14816 #define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK                                                0x00008000L
14817 #define CP_ME2_PIPE0_INT_STATUS__GPF_INT_STATUS_MASK                                                          0x00010000L
14818 #define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK                                             0x00020000L
14819 #define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK                                                     0x00800000L
14820 #define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK                                                 0x01000000L
14821 #define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK                                                   0x04000000L
14822 #define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK                                           0x08000000L
14823 #define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK                                                     0x20000000L
14824 #define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK                                                     0x40000000L
14825 #define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK                                                     0x80000000L
14826 //CP_ME2_PIPE1_INT_STATUS
14827 #define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT                                           0xc
14828 #define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT                                            0xd
14829 #define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT                                               0xe
14830 #define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT                                              0xf
14831 #define CP_ME2_PIPE1_INT_STATUS__GPF_INT_STATUS__SHIFT                                                        0x10
14832 #define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT                                           0x11
14833 #define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT                                                   0x17
14834 #define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT                                               0x18
14835 #define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT                                                 0x1a
14836 #define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT                                         0x1b
14837 #define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT                                                   0x1d
14838 #define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT                                                   0x1e
14839 #define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT                                                   0x1f
14840 #define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK                                             0x00001000L
14841 #define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK                                              0x00002000L
14842 #define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK                                                 0x00004000L
14843 #define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK                                                0x00008000L
14844 #define CP_ME2_PIPE1_INT_STATUS__GPF_INT_STATUS_MASK                                                          0x00010000L
14845 #define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK                                             0x00020000L
14846 #define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK                                                     0x00800000L
14847 #define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK                                                 0x01000000L
14848 #define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK                                                   0x04000000L
14849 #define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK                                           0x08000000L
14850 #define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK                                                     0x20000000L
14851 #define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK                                                     0x40000000L
14852 #define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK                                                     0x80000000L
14853 //CP_ME2_PIPE2_INT_STATUS
14854 #define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT                                           0xc
14855 #define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT                                            0xd
14856 #define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT                                               0xe
14857 #define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT                                              0xf
14858 #define CP_ME2_PIPE2_INT_STATUS__GPF_INT_STATUS__SHIFT                                                        0x10
14859 #define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT                                           0x11
14860 #define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT                                                   0x17
14861 #define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT                                               0x18
14862 #define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT                                                 0x1a
14863 #define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT                                         0x1b
14864 #define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT                                                   0x1d
14865 #define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT                                                   0x1e
14866 #define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT                                                   0x1f
14867 #define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK                                             0x00001000L
14868 #define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK                                              0x00002000L
14869 #define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK                                                 0x00004000L
14870 #define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK                                                0x00008000L
14871 #define CP_ME2_PIPE2_INT_STATUS__GPF_INT_STATUS_MASK                                                          0x00010000L
14872 #define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK                                             0x00020000L
14873 #define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK                                                     0x00800000L
14874 #define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK                                                 0x01000000L
14875 #define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK                                                   0x04000000L
14876 #define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK                                           0x08000000L
14877 #define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK                                                     0x20000000L
14878 #define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK                                                     0x40000000L
14879 #define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK                                                     0x80000000L
14880 //CP_ME2_PIPE3_INT_STATUS
14881 #define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT                                           0xc
14882 #define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT                                            0xd
14883 #define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT                                               0xe
14884 #define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT                                              0xf
14885 #define CP_ME2_PIPE3_INT_STATUS__GPF_INT_STATUS__SHIFT                                                        0x10
14886 #define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT                                           0x11
14887 #define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT                                                   0x17
14888 #define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT                                               0x18
14889 #define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT                                                 0x1a
14890 #define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT                                         0x1b
14891 #define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT                                                   0x1d
14892 #define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT                                                   0x1e
14893 #define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT                                                   0x1f
14894 #define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK                                             0x00001000L
14895 #define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK                                              0x00002000L
14896 #define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK                                                 0x00004000L
14897 #define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK                                                0x00008000L
14898 #define CP_ME2_PIPE3_INT_STATUS__GPF_INT_STATUS_MASK                                                          0x00010000L
14899 #define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK                                             0x00020000L
14900 #define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK                                                     0x00800000L
14901 #define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK                                                 0x01000000L
14902 #define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK                                                   0x04000000L
14903 #define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK                                           0x08000000L
14904 #define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK                                                     0x20000000L
14905 #define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK                                                     0x40000000L
14906 #define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK                                                     0x80000000L
14907 //CP_ME1_INT_STAT_DEBUG
14908 #define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT                                           0xc
14909 #define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT                                            0xd
14910 #define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT                                               0xe
14911 #define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT                                                0xf
14912 #define CP_ME1_INT_STAT_DEBUG__GPF_INT_ASSERTED__SHIFT                                                        0x10
14913 #define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT                                           0x11
14914 #define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT                                                   0x17
14915 #define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT                                               0x18
14916 #define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT                                                 0x1a
14917 #define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT                                         0x1b
14918 #define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT                                                   0x1d
14919 #define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT                                                   0x1e
14920 #define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT                                                   0x1f
14921 #define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK                                             0x00001000L
14922 #define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK                                              0x00002000L
14923 #define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK                                                 0x00004000L
14924 #define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK                                                  0x00008000L
14925 #define CP_ME1_INT_STAT_DEBUG__GPF_INT_ASSERTED_MASK                                                          0x00010000L
14926 #define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK                                             0x00020000L
14927 #define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK                                                     0x00800000L
14928 #define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK                                                 0x01000000L
14929 #define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK                                                   0x04000000L
14930 #define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK                                           0x08000000L
14931 #define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK                                                     0x20000000L
14932 #define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK                                                     0x40000000L
14933 #define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK                                                     0x80000000L
14934 //CP_ME2_INT_STAT_DEBUG
14935 #define CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT                                           0xc
14936 #define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT                                            0xd
14937 #define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT                                               0xe
14938 #define CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT                                                0xf
14939 #define CP_ME2_INT_STAT_DEBUG__GPF_INT_ASSERTED__SHIFT                                                        0x10
14940 #define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT                                           0x11
14941 #define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT                                                   0x17
14942 #define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT                                               0x18
14943 #define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT                                                 0x1a
14944 #define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT                                         0x1b
14945 #define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT                                                   0x1d
14946 #define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT                                                   0x1e
14947 #define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT                                                   0x1f
14948 #define CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK                                             0x00001000L
14949 #define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK                                              0x00002000L
14950 #define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK                                                 0x00004000L
14951 #define CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK                                                  0x00008000L
14952 #define CP_ME2_INT_STAT_DEBUG__GPF_INT_ASSERTED_MASK                                                          0x00010000L
14953 #define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK                                             0x00020000L
14954 #define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK                                                     0x00800000L
14955 #define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK                                                 0x01000000L
14956 #define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK                                                   0x04000000L
14957 #define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK                                           0x08000000L
14958 #define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK                                                     0x20000000L
14959 #define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK                                                     0x40000000L
14960 #define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK                                                     0x80000000L
14961 //CC_GC_EDC_CONFIG
14962 #define CC_GC_EDC_CONFIG__WRITE_DIS__SHIFT                                                                    0x0
14963 #define CC_GC_EDC_CONFIG__DIS_EDC__SHIFT                                                                      0x1
14964 #define CC_GC_EDC_CONFIG__ENABLE_IRRITATOR_CLK__SHIFT                                                         0x2
14965 #define CC_GC_EDC_CONFIG__WRITE_DIS_MASK                                                                      0x00000001L
14966 #define CC_GC_EDC_CONFIG__DIS_EDC_MASK                                                                        0x00000002L
14967 #define CC_GC_EDC_CONFIG__ENABLE_IRRITATOR_CLK_MASK                                                           0x00000004L
14968 //CP_ME1_PIPE_PRIORITY_CNTS
14969 #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT                                                       0x0
14970 #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT                                                      0x8
14971 #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT                                                      0x10
14972 #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT                                                       0x18
14973 #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK                                                         0x000000FFL
14974 #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK                                                        0x0000FF00L
14975 #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK                                                        0x00FF0000L
14976 #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK                                                         0xFF000000L
14977 //CP_ME1_PIPE0_PRIORITY
14978 #define CP_ME1_PIPE0_PRIORITY__PRIORITY__SHIFT                                                                0x0
14979 #define CP_ME1_PIPE0_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
14980 //CP_ME1_PIPE1_PRIORITY
14981 #define CP_ME1_PIPE1_PRIORITY__PRIORITY__SHIFT                                                                0x0
14982 #define CP_ME1_PIPE1_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
14983 //CP_ME1_PIPE2_PRIORITY
14984 #define CP_ME1_PIPE2_PRIORITY__PRIORITY__SHIFT                                                                0x0
14985 #define CP_ME1_PIPE2_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
14986 //CP_ME1_PIPE3_PRIORITY
14987 #define CP_ME1_PIPE3_PRIORITY__PRIORITY__SHIFT                                                                0x0
14988 #define CP_ME1_PIPE3_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
14989 //CP_ME2_PIPE_PRIORITY_CNTS
14990 #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT                                                       0x0
14991 #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT                                                      0x8
14992 #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT                                                      0x10
14993 #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT                                                       0x18
14994 #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK                                                         0x000000FFL
14995 #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK                                                        0x0000FF00L
14996 #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK                                                        0x00FF0000L
14997 #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK                                                         0xFF000000L
14998 //CP_ME2_PIPE0_PRIORITY
14999 #define CP_ME2_PIPE0_PRIORITY__PRIORITY__SHIFT                                                                0x0
15000 #define CP_ME2_PIPE0_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
15001 //CP_ME2_PIPE1_PRIORITY
15002 #define CP_ME2_PIPE1_PRIORITY__PRIORITY__SHIFT                                                                0x0
15003 #define CP_ME2_PIPE1_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
15004 //CP_ME2_PIPE2_PRIORITY
15005 #define CP_ME2_PIPE2_PRIORITY__PRIORITY__SHIFT                                                                0x0
15006 #define CP_ME2_PIPE2_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
15007 //CP_ME2_PIPE3_PRIORITY
15008 #define CP_ME2_PIPE3_PRIORITY__PRIORITY__SHIFT                                                                0x0
15009 #define CP_ME2_PIPE3_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
15010 //CP_CE_PRGRM_CNTR_START
15011 #define CP_CE_PRGRM_CNTR_START__IP_START__SHIFT                                                               0x0
15012 #define CP_CE_PRGRM_CNTR_START__IP_START_MASK                                                                 0x000007FFL
15013 //CP_PFP_PRGRM_CNTR_START
15014 #define CP_PFP_PRGRM_CNTR_START__IP_START__SHIFT                                                              0x0
15015 #define CP_PFP_PRGRM_CNTR_START__IP_START_MASK                                                                0x00001FFFL
15016 //CP_ME_PRGRM_CNTR_START
15017 #define CP_ME_PRGRM_CNTR_START__IP_START__SHIFT                                                               0x0
15018 #define CP_ME_PRGRM_CNTR_START__IP_START_MASK                                                                 0x00000FFFL
15019 //CP_MEC1_PRGRM_CNTR_START
15020 #define CP_MEC1_PRGRM_CNTR_START__IP_START__SHIFT                                                             0x0
15021 #define CP_MEC1_PRGRM_CNTR_START__IP_START_MASK                                                               0x0000FFFFL
15022 //CP_MEC2_PRGRM_CNTR_START
15023 #define CP_MEC2_PRGRM_CNTR_START__IP_START__SHIFT                                                             0x0
15024 #define CP_MEC2_PRGRM_CNTR_START__IP_START_MASK                                                               0x0000FFFFL
15025 //CP_CE_INTR_ROUTINE_START
15026 #define CP_CE_INTR_ROUTINE_START__IR_START__SHIFT                                                             0x0
15027 #define CP_CE_INTR_ROUTINE_START__IR_START_MASK                                                               0x000007FFL
15028 //CP_PFP_INTR_ROUTINE_START
15029 #define CP_PFP_INTR_ROUTINE_START__IR_START__SHIFT                                                            0x0
15030 #define CP_PFP_INTR_ROUTINE_START__IR_START_MASK                                                              0x00001FFFL
15031 //CP_ME_INTR_ROUTINE_START
15032 #define CP_ME_INTR_ROUTINE_START__IR_START__SHIFT                                                             0x0
15033 #define CP_ME_INTR_ROUTINE_START__IR_START_MASK                                                               0x00000FFFL
15034 //CP_MEC1_INTR_ROUTINE_START
15035 #define CP_MEC1_INTR_ROUTINE_START__IR_START__SHIFT                                                           0x0
15036 #define CP_MEC1_INTR_ROUTINE_START__IR_START_MASK                                                             0x0000FFFFL
15037 //CP_MEC2_INTR_ROUTINE_START
15038 #define CP_MEC2_INTR_ROUTINE_START__IR_START__SHIFT                                                           0x0
15039 #define CP_MEC2_INTR_ROUTINE_START__IR_START_MASK                                                             0x0000FFFFL
15040 //CP_CONTEXT_CNTL
15041 #define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX__SHIFT                                                          0x0
15042 #define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX__SHIFT                                                        0x4
15043 #define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX__SHIFT                                                          0x10
15044 #define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX__SHIFT                                                        0x14
15045 #define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX_MASK                                                            0x00000007L
15046 #define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX_MASK                                                          0x00000070L
15047 #define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX_MASK                                                            0x00070000L
15048 #define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX_MASK                                                          0x00700000L
15049 //CP_MAX_CONTEXT
15050 #define CP_MAX_CONTEXT__MAX_CONTEXT__SHIFT                                                                    0x0
15051 #define CP_MAX_CONTEXT__MAX_CONTEXT_MASK                                                                      0x00000007L
15052 //CP_IQ_WAIT_TIME1
15053 #define CP_IQ_WAIT_TIME1__IB_OFFLOAD__SHIFT                                                                   0x0
15054 #define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD__SHIFT                                                               0x8
15055 #define CP_IQ_WAIT_TIME1__WRM_OFFLOAD__SHIFT                                                                  0x10
15056 #define CP_IQ_WAIT_TIME1__GWS__SHIFT                                                                          0x18
15057 #define CP_IQ_WAIT_TIME1__IB_OFFLOAD_MASK                                                                     0x000000FFL
15058 #define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD_MASK                                                                 0x0000FF00L
15059 #define CP_IQ_WAIT_TIME1__WRM_OFFLOAD_MASK                                                                    0x00FF0000L
15060 #define CP_IQ_WAIT_TIME1__GWS_MASK                                                                            0xFF000000L
15061 //CP_IQ_WAIT_TIME2
15062 #define CP_IQ_WAIT_TIME2__QUE_SLEEP__SHIFT                                                                    0x0
15063 #define CP_IQ_WAIT_TIME2__SCH_WAVE__SHIFT                                                                     0x8
15064 #define CP_IQ_WAIT_TIME2__SEM_REARM__SHIFT                                                                    0x10
15065 #define CP_IQ_WAIT_TIME2__DEQ_RETRY__SHIFT                                                                    0x18
15066 #define CP_IQ_WAIT_TIME2__QUE_SLEEP_MASK                                                                      0x000000FFL
15067 #define CP_IQ_WAIT_TIME2__SCH_WAVE_MASK                                                                       0x0000FF00L
15068 #define CP_IQ_WAIT_TIME2__SEM_REARM_MASK                                                                      0x00FF0000L
15069 #define CP_IQ_WAIT_TIME2__DEQ_RETRY_MASK                                                                      0xFF000000L
15070 //CP_RB0_BASE_HI
15071 #define CP_RB0_BASE_HI__RB_BASE_HI__SHIFT                                                                     0x0
15072 #define CP_RB0_BASE_HI__RB_BASE_HI_MASK                                                                       0x000000FFL
15073 //CP_RB1_BASE_HI
15074 #define CP_RB1_BASE_HI__RB_BASE_HI__SHIFT                                                                     0x0
15075 #define CP_RB1_BASE_HI__RB_BASE_HI_MASK                                                                       0x000000FFL
15076 //CP_VMID_RESET
15077 #define CP_VMID_RESET__RESET_REQUEST__SHIFT                                                                   0x0
15078 #define CP_VMID_RESET__RESET_REQUEST_MASK                                                                     0x0000FFFFL
15079 //CPC_INT_CNTL
15080 #define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT                                                      0xc
15081 #define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT                                                       0xd
15082 #define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                          0xe
15083 #define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT                                                         0xf
15084 #define CPC_INT_CNTL__GPF_INT_ENABLE__SHIFT                                                                   0x10
15085 #define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                                      0x11
15086 #define CPC_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT                                                              0x17
15087 #define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT                                                          0x18
15088 #define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT                                                            0x1a
15089 #define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                                    0x1b
15090 #define CPC_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT                                                              0x1d
15091 #define CPC_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT                                                              0x1e
15092 #define CPC_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT                                                              0x1f
15093 #define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK                                                        0x00001000L
15094 #define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK                                                         0x00002000L
15095 #define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK                                                            0x00004000L
15096 #define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK                                                           0x00008000L
15097 #define CPC_INT_CNTL__GPF_INT_ENABLE_MASK                                                                     0x00010000L
15098 #define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                                        0x00020000L
15099 #define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK                                                                0x00800000L
15100 #define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK                                                            0x01000000L
15101 #define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK                                                              0x04000000L
15102 #define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                                      0x08000000L
15103 #define CPC_INT_CNTL__GENERIC2_INT_ENABLE_MASK                                                                0x20000000L
15104 #define CPC_INT_CNTL__GENERIC1_INT_ENABLE_MASK                                                                0x40000000L
15105 #define CPC_INT_CNTL__GENERIC0_INT_ENABLE_MASK                                                                0x80000000L
15106 //CPC_INT_STATUS
15107 #define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT                                                    0xc
15108 #define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT                                                     0xd
15109 #define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT                                                        0xe
15110 #define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT                                                       0xf
15111 #define CPC_INT_STATUS__GPF_INT_STATUS__SHIFT                                                                 0x10
15112 #define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT                                                    0x11
15113 #define CPC_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT                                                            0x17
15114 #define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT                                                        0x18
15115 #define CPC_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT                                                          0x1a
15116 #define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT                                                  0x1b
15117 #define CPC_INT_STATUS__GENERIC2_INT_STATUS__SHIFT                                                            0x1d
15118 #define CPC_INT_STATUS__GENERIC1_INT_STATUS__SHIFT                                                            0x1e
15119 #define CPC_INT_STATUS__GENERIC0_INT_STATUS__SHIFT                                                            0x1f
15120 #define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK                                                      0x00001000L
15121 #define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK                                                       0x00002000L
15122 #define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK                                                          0x00004000L
15123 #define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK                                                         0x00008000L
15124 #define CPC_INT_STATUS__GPF_INT_STATUS_MASK                                                                   0x00010000L
15125 #define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK                                                      0x00020000L
15126 #define CPC_INT_STATUS__PRIV_REG_INT_STATUS_MASK                                                              0x00800000L
15127 #define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK                                                          0x01000000L
15128 #define CPC_INT_STATUS__TIME_STAMP_INT_STATUS_MASK                                                            0x04000000L
15129 #define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK                                                    0x08000000L
15130 #define CPC_INT_STATUS__GENERIC2_INT_STATUS_MASK                                                              0x20000000L
15131 #define CPC_INT_STATUS__GENERIC1_INT_STATUS_MASK                                                              0x40000000L
15132 #define CPC_INT_STATUS__GENERIC0_INT_STATUS_MASK                                                              0x80000000L
15133 //CP_VMID_PREEMPT
15134 #define CP_VMID_PREEMPT__PREEMPT_REQUEST__SHIFT                                                               0x0
15135 #define CP_VMID_PREEMPT__VIRT_COMMAND__SHIFT                                                                  0x10
15136 #define CP_VMID_PREEMPT__PREEMPT_REQUEST_MASK                                                                 0x0000FFFFL
15137 #define CP_VMID_PREEMPT__VIRT_COMMAND_MASK                                                                    0x000F0000L
15138 //CPC_INT_CNTX_ID
15139 #define CPC_INT_CNTX_ID__CNTX_ID__SHIFT                                                                       0x0
15140 #define CPC_INT_CNTX_ID__CNTX_ID_MASK                                                                         0xFFFFFFFFL
15141 //CP_PQ_STATUS
15142 #define CP_PQ_STATUS__DOORBELL_UPDATED__SHIFT                                                                 0x0
15143 #define CP_PQ_STATUS__DOORBELL_ENABLE__SHIFT                                                                  0x1
15144 #define CP_PQ_STATUS__DOORBELL_UPDATED_EN__SHIFT                                                              0x2
15145 #define CP_PQ_STATUS__DOORBELL_UPDATED_MASK                                                                   0x00000001L
15146 #define CP_PQ_STATUS__DOORBELL_ENABLE_MASK                                                                    0x00000002L
15147 #define CP_PQ_STATUS__DOORBELL_UPDATED_EN_MASK                                                                0x00000004L
15148 //CP_CPC_IC_BASE_LO
15149 #define CP_CPC_IC_BASE_LO__IC_BASE_LO__SHIFT                                                                  0xc
15150 #define CP_CPC_IC_BASE_LO__IC_BASE_LO_MASK                                                                    0xFFFFF000L
15151 //CP_CPC_IC_BASE_HI
15152 #define CP_CPC_IC_BASE_HI__IC_BASE_HI__SHIFT                                                                  0x0
15153 #define CP_CPC_IC_BASE_HI__IC_BASE_HI_MASK                                                                    0x0000FFFFL
15154 //CP_CPC_IC_BASE_CNTL
15155 #define CP_CPC_IC_BASE_CNTL__VMID__SHIFT                                                                      0x0
15156 #define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT                                                              0x18
15157 #define CP_CPC_IC_BASE_CNTL__VMID_MASK                                                                        0x0000000FL
15158 #define CP_CPC_IC_BASE_CNTL__CACHE_POLICY_MASK                                                                0x01000000L
15159 //CP_CPC_IC_OP_CNTL
15160 #define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT                                                            0x0
15161 #define CP_CPC_IC_OP_CNTL__PRIME_ICACHE__SHIFT                                                                0x4
15162 #define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED__SHIFT                                                               0x5
15163 #define CP_CPC_IC_OP_CNTL__ICACHE_INVALIDATED__SHIFT                                                          0x6
15164 #define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_MASK                                                              0x00000001L
15165 #define CP_CPC_IC_OP_CNTL__PRIME_ICACHE_MASK                                                                  0x00000010L
15166 #define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED_MASK                                                                 0x00000020L
15167 #define CP_CPC_IC_OP_CNTL__ICACHE_INVALIDATED_MASK                                                            0x00000040L
15168 //CP_MEC1_F32_INT_DIS
15169 #define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT                                                           0x0
15170 #define CP_MEC1_F32_INT_DIS__PRIV_REG_INT__SHIFT                                                              0x1
15171 #define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT                                                      0x2
15172 #define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT__SHIFT                                                            0x3
15173 #define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT                                                           0x4
15174 #define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT                                                       0x5
15175 #define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT                                                          0x6
15176 #define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT                                                         0x7
15177 #define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT                                                           0x8
15178 #define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT__SHIFT                                                              0x9
15179 #define CP_MEC1_F32_INT_DIS__GPF_INT_CPF__SHIFT                                                               0xa
15180 #define CP_MEC1_F32_INT_DIS__GPF_INT_DMA__SHIFT                                                               0xb
15181 #define CP_MEC1_F32_INT_DIS__GPF_INT_CPC__SHIFT                                                               0xc
15182 #define CP_MEC1_F32_INT_DIS__EDC_SR_MEM_FED_INT__SHIFT                                                        0xd
15183 #define CP_MEC1_F32_INT_DIS__QUEUE_MESSAGE_INT__SHIFT                                                         0xe
15184 #define CP_MEC1_F32_INT_DIS__FATAL_EDC_ERROR_INT__SHIFT                                                       0xf
15185 #define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT_MASK                                                             0x00000001L
15186 #define CP_MEC1_F32_INT_DIS__PRIV_REG_INT_MASK                                                                0x00000002L
15187 #define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK                                                        0x00000004L
15188 #define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT_MASK                                                              0x00000008L
15189 #define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT_MASK                                                             0x00000010L
15190 #define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK                                                         0x00000020L
15191 #define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT_MASK                                                            0x00000040L
15192 #define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT_MASK                                                           0x00000080L
15193 #define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT_MASK                                                             0x00000100L
15194 #define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT_MASK                                                                0x00000200L
15195 #define CP_MEC1_F32_INT_DIS__GPF_INT_CPF_MASK                                                                 0x00000400L
15196 #define CP_MEC1_F32_INT_DIS__GPF_INT_DMA_MASK                                                                 0x00000800L
15197 #define CP_MEC1_F32_INT_DIS__GPF_INT_CPC_MASK                                                                 0x00001000L
15198 #define CP_MEC1_F32_INT_DIS__EDC_SR_MEM_FED_INT_MASK                                                          0x00002000L
15199 #define CP_MEC1_F32_INT_DIS__QUEUE_MESSAGE_INT_MASK                                                           0x00004000L
15200 #define CP_MEC1_F32_INT_DIS__FATAL_EDC_ERROR_INT_MASK                                                         0x00008000L
15201 //CP_MEC2_F32_INT_DIS
15202 #define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT                                                           0x0
15203 #define CP_MEC2_F32_INT_DIS__PRIV_REG_INT__SHIFT                                                              0x1
15204 #define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT                                                      0x2
15205 #define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT__SHIFT                                                            0x3
15206 #define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT                                                           0x4
15207 #define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT                                                       0x5
15208 #define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT                                                          0x6
15209 #define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT                                                         0x7
15210 #define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT                                                           0x8
15211 #define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT__SHIFT                                                              0x9
15212 #define CP_MEC2_F32_INT_DIS__GPF_INT_CPF__SHIFT                                                               0xa
15213 #define CP_MEC2_F32_INT_DIS__GPF_INT_DMA__SHIFT                                                               0xb
15214 #define CP_MEC2_F32_INT_DIS__GPF_INT_CPC__SHIFT                                                               0xc
15215 #define CP_MEC2_F32_INT_DIS__EDC_SR_MEM_FED_INT__SHIFT                                                        0xd
15216 #define CP_MEC2_F32_INT_DIS__QUEUE_MESSAGE_INT__SHIFT                                                         0xe
15217 #define CP_MEC2_F32_INT_DIS__FATAL_EDC_ERROR_INT__SHIFT                                                       0xf
15218 #define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT_MASK                                                             0x00000001L
15219 #define CP_MEC2_F32_INT_DIS__PRIV_REG_INT_MASK                                                                0x00000002L
15220 #define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK                                                        0x00000004L
15221 #define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT_MASK                                                              0x00000008L
15222 #define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT_MASK                                                             0x00000010L
15223 #define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK                                                         0x00000020L
15224 #define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT_MASK                                                            0x00000040L
15225 #define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT_MASK                                                           0x00000080L
15226 #define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT_MASK                                                             0x00000100L
15227 #define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT_MASK                                                                0x00000200L
15228 #define CP_MEC2_F32_INT_DIS__GPF_INT_CPF_MASK                                                                 0x00000400L
15229 #define CP_MEC2_F32_INT_DIS__GPF_INT_DMA_MASK                                                                 0x00000800L
15230 #define CP_MEC2_F32_INT_DIS__GPF_INT_CPC_MASK                                                                 0x00001000L
15231 #define CP_MEC2_F32_INT_DIS__EDC_SR_MEM_FED_INT_MASK                                                          0x00002000L
15232 #define CP_MEC2_F32_INT_DIS__QUEUE_MESSAGE_INT_MASK                                                           0x00004000L
15233 #define CP_MEC2_F32_INT_DIS__FATAL_EDC_ERROR_INT_MASK                                                         0x00008000L
15234 //CP_VMID_STATUS
15235 #define CP_VMID_STATUS__PREEMPT_DE_STATUS__SHIFT                                                              0x0
15236 #define CP_VMID_STATUS__PREEMPT_CE_STATUS__SHIFT                                                              0x10
15237 #define CP_VMID_STATUS__PREEMPT_DE_STATUS_MASK                                                                0x0000FFFFL
15238 #define CP_VMID_STATUS__PREEMPT_CE_STATUS_MASK                                                                0xFFFF0000L
15239 //CPC_UE_ERR_STATUS_LO
15240 #define CPC_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT                                                    0x0
15241 #define CPC_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT                                                       0x1
15242 #define CPC_UE_ERR_STATUS_LO__ADDRESS__SHIFT                                                                  0x2
15243 #define CPC_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT                                                                0x18
15244 #define CPC_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK                                                      0x00000001L
15245 #define CPC_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK                                                         0x00000002L
15246 #define CPC_UE_ERR_STATUS_LO__ADDRESS_MASK                                                                    0x00FFFFFCL
15247 #define CPC_UE_ERR_STATUS_LO__MEMORY_ID_MASK                                                                  0xFF000000L
15248 //CPC_UE_ERR_STATUS_HI
15249 #define CPC_UE_ERR_STATUS_HI__ECC__SHIFT                                                                      0x0
15250 #define CPC_UE_ERR_STATUS_HI__PARITY__SHIFT                                                                   0x1
15251 #define CPC_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT                                                      0x2
15252 #define CPC_UE_ERR_STATUS_HI__ERR_INFO__SHIFT                                                                 0x3
15253 #define CPC_UE_ERR_STATUS_HI__UE_CNT__SHIFT                                                                   0x17
15254 #define CPC_UE_ERR_STATUS_HI__FED_CNT__SHIFT                                                                  0x1a
15255 #define CPC_UE_ERR_STATUS_HI__RESERVED__SHIFT                                                                 0x1d
15256 #define CPC_UE_ERR_STATUS_HI__ECC_MASK                                                                        0x00000001L
15257 #define CPC_UE_ERR_STATUS_HI__PARITY_MASK                                                                     0x00000002L
15258 #define CPC_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK                                                        0x00000004L
15259 #define CPC_UE_ERR_STATUS_HI__ERR_INFO_MASK                                                                   0x007FFFF8L
15260 #define CPC_UE_ERR_STATUS_HI__UE_CNT_MASK                                                                     0x03800000L
15261 #define CPC_UE_ERR_STATUS_HI__FED_CNT_MASK                                                                    0x1C000000L
15262 #define CPC_UE_ERR_STATUS_HI__RESERVED_MASK                                                                   0xE0000000L
15263 //CPC_CE_ERR_STATUS_LO
15264 #define CPC_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT                                                    0x0
15265 #define CPC_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT                                                       0x1
15266 #define CPC_CE_ERR_STATUS_LO__ADDRESS__SHIFT                                                                  0x2
15267 #define CPC_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT                                                                0x18
15268 #define CPC_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK                                                      0x00000001L
15269 #define CPC_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK                                                         0x00000002L
15270 #define CPC_CE_ERR_STATUS_LO__ADDRESS_MASK                                                                    0x00FFFFFCL
15271 #define CPC_CE_ERR_STATUS_LO__MEMORY_ID_MASK                                                                  0xFF000000L
15272 //CPC_CE_ERR_STATUS_HI
15273 #define CPC_CE_ERR_STATUS_HI__ECC__SHIFT                                                                      0x0
15274 #define CPC_CE_ERR_STATUS_HI__OTHER__SHIFT                                                                    0x1
15275 #define CPC_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT                                                      0x2
15276 #define CPC_CE_ERR_STATUS_HI__ERR_INFO__SHIFT                                                                 0x3
15277 #define CPC_CE_ERR_STATUS_HI__CE_CNT__SHIFT                                                                   0x17
15278 #define CPC_CE_ERR_STATUS_HI__POISON__SHIFT                                                                   0x1a
15279 #define CPC_CE_ERR_STATUS_HI__RESERVED__SHIFT                                                                 0x1b
15280 #define CPC_CE_ERR_STATUS_HI__ECC_MASK                                                                        0x00000001L
15281 #define CPC_CE_ERR_STATUS_HI__OTHER_MASK                                                                      0x00000002L
15282 #define CPC_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK                                                        0x00000004L
15283 #define CPC_CE_ERR_STATUS_HI__ERR_INFO_MASK                                                                   0x007FFFF8L
15284 #define CPC_CE_ERR_STATUS_HI__CE_CNT_MASK                                                                     0x03800000L
15285 #define CPC_CE_ERR_STATUS_HI__POISON_MASK                                                                     0x04000000L
15286 #define CPC_CE_ERR_STATUS_HI__RESERVED_MASK                                                                   0xF8000000L
15287 //CPF_UE_ERR_STATUS_LO
15288 #define CPF_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT                                                    0x0
15289 #define CPF_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT                                                       0x1
15290 #define CPF_UE_ERR_STATUS_LO__ADDRESS__SHIFT                                                                  0x2
15291 #define CPF_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT                                                                0x18
15292 #define CPF_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK                                                      0x00000001L
15293 #define CPF_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK                                                         0x00000002L
15294 #define CPF_UE_ERR_STATUS_LO__ADDRESS_MASK                                                                    0x00FFFFFCL
15295 #define CPF_UE_ERR_STATUS_LO__MEMORY_ID_MASK                                                                  0xFF000000L
15296 //CPF_UE_ERR_STATUS_HI
15297 #define CPF_UE_ERR_STATUS_HI__ECC__SHIFT                                                                      0x0
15298 #define CPF_UE_ERR_STATUS_HI__PARITY__SHIFT                                                                   0x1
15299 #define CPF_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT                                                      0x2
15300 #define CPF_UE_ERR_STATUS_HI__ERR_INFO__SHIFT                                                                 0x3
15301 #define CPF_UE_ERR_STATUS_HI__UE_CNT__SHIFT                                                                   0x17
15302 #define CPF_UE_ERR_STATUS_HI__FED_CNT__SHIFT                                                                  0x1a
15303 #define CPF_UE_ERR_STATUS_HI__RESERVED__SHIFT                                                                 0x1d
15304 #define CPF_UE_ERR_STATUS_HI__ECC_MASK                                                                        0x00000001L
15305 #define CPF_UE_ERR_STATUS_HI__PARITY_MASK                                                                     0x00000002L
15306 #define CPF_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK                                                        0x00000004L
15307 #define CPF_UE_ERR_STATUS_HI__ERR_INFO_MASK                                                                   0x007FFFF8L
15308 #define CPF_UE_ERR_STATUS_HI__UE_CNT_MASK                                                                     0x03800000L
15309 #define CPF_UE_ERR_STATUS_HI__FED_CNT_MASK                                                                    0x1C000000L
15310 #define CPF_UE_ERR_STATUS_HI__RESERVED_MASK                                                                   0xE0000000L
15311 //CPF_CE_ERR_STATUS_LO
15312 #define CPF_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT                                                    0x0
15313 #define CPF_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT                                                       0x1
15314 #define CPF_CE_ERR_STATUS_LO__ADDRESS__SHIFT                                                                  0x2
15315 #define CPF_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT                                                                0x18
15316 #define CPF_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK                                                      0x00000001L
15317 #define CPF_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK                                                         0x00000002L
15318 #define CPF_CE_ERR_STATUS_LO__ADDRESS_MASK                                                                    0x00FFFFFCL
15319 #define CPF_CE_ERR_STATUS_LO__MEMORY_ID_MASK                                                                  0xFF000000L
15320 //CPF_CE_ERR_STATUS_HI
15321 #define CPF_CE_ERR_STATUS_HI__ECC__SHIFT                                                                      0x0
15322 #define CPF_CE_ERR_STATUS_HI__OTHER__SHIFT                                                                    0x1
15323 #define CPF_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT                                                      0x2
15324 #define CPF_CE_ERR_STATUS_HI__ERR_INFO__SHIFT                                                                 0x3
15325 #define CPF_CE_ERR_STATUS_HI__CE_CNT__SHIFT                                                                   0x17
15326 #define CPF_CE_ERR_STATUS_HI__POISON__SHIFT                                                                   0x1a
15327 #define CPF_CE_ERR_STATUS_HI__RESERVED__SHIFT                                                                 0x1b
15328 #define CPF_CE_ERR_STATUS_HI__ECC_MASK                                                                        0x00000001L
15329 #define CPF_CE_ERR_STATUS_HI__OTHER_MASK                                                                      0x00000002L
15330 #define CPF_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK                                                        0x00000004L
15331 #define CPF_CE_ERR_STATUS_HI__ERR_INFO_MASK                                                                   0x007FFFF8L
15332 #define CPF_CE_ERR_STATUS_HI__CE_CNT_MASK                                                                     0x03800000L
15333 #define CPF_CE_ERR_STATUS_HI__POISON_MASK                                                                     0x04000000L
15334 #define CPF_CE_ERR_STATUS_HI__RESERVED_MASK                                                                   0xF8000000L
15335 //CPG_UE_ERR_STATUS_LO
15336 #define CPG_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT                                                    0x0
15337 #define CPG_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT                                                       0x1
15338 #define CPG_UE_ERR_STATUS_LO__ADDRESS__SHIFT                                                                  0x2
15339 #define CPG_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT                                                                0x18
15340 #define CPG_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK                                                      0x00000001L
15341 #define CPG_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK                                                         0x00000002L
15342 #define CPG_UE_ERR_STATUS_LO__ADDRESS_MASK                                                                    0x00FFFFFCL
15343 #define CPG_UE_ERR_STATUS_LO__MEMORY_ID_MASK                                                                  0xFF000000L
15344 //CPG_UE_ERR_STATUS_HI
15345 #define CPG_UE_ERR_STATUS_HI__ECC__SHIFT                                                                      0x0
15346 #define CPG_UE_ERR_STATUS_HI__PARITY__SHIFT                                                                   0x1
15347 #define CPG_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT                                                      0x2
15348 #define CPG_UE_ERR_STATUS_HI__ERR_INFO__SHIFT                                                                 0x3
15349 #define CPG_UE_ERR_STATUS_HI__UE_CNT__SHIFT                                                                   0x17
15350 #define CPG_UE_ERR_STATUS_HI__FED_CNT__SHIFT                                                                  0x1a
15351 #define CPG_UE_ERR_STATUS_HI__RESERVED__SHIFT                                                                 0x1d
15352 #define CPG_UE_ERR_STATUS_HI__ECC_MASK                                                                        0x00000001L
15353 #define CPG_UE_ERR_STATUS_HI__PARITY_MASK                                                                     0x00000002L
15354 #define CPG_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK                                                        0x00000004L
15355 #define CPG_UE_ERR_STATUS_HI__ERR_INFO_MASK                                                                   0x007FFFF8L
15356 #define CPG_UE_ERR_STATUS_HI__UE_CNT_MASK                                                                     0x03800000L
15357 #define CPG_UE_ERR_STATUS_HI__FED_CNT_MASK                                                                    0x1C000000L
15358 #define CPG_UE_ERR_STATUS_HI__RESERVED_MASK                                                                   0xE0000000L
15359 //CPG_CE_ERR_STATUS_LO
15360 #define CPG_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT                                                    0x0
15361 #define CPG_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT                                                       0x1
15362 #define CPG_CE_ERR_STATUS_LO__ADDRESS__SHIFT                                                                  0x2
15363 #define CPG_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT                                                                0x18
15364 #define CPG_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK                                                      0x00000001L
15365 #define CPG_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK                                                         0x00000002L
15366 #define CPG_CE_ERR_STATUS_LO__ADDRESS_MASK                                                                    0x00FFFFFCL
15367 #define CPG_CE_ERR_STATUS_LO__MEMORY_ID_MASK                                                                  0xFF000000L
15368 //CPG_CE_ERR_STATUS_HI
15369 #define CPG_CE_ERR_STATUS_HI__ECC__SHIFT                                                                      0x0
15370 #define CPG_CE_ERR_STATUS_HI__OTHER__SHIFT                                                                    0x1
15371 #define CPG_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT                                                      0x2
15372 #define CPG_CE_ERR_STATUS_HI__ERR_INFO__SHIFT                                                                 0x3
15373 #define CPG_CE_ERR_STATUS_HI__CE_CNT__SHIFT                                                                   0x17
15374 #define CPG_CE_ERR_STATUS_HI__POISON__SHIFT                                                                   0x1a
15375 #define CPG_CE_ERR_STATUS_HI__RESERVED__SHIFT                                                                 0x1b
15376 #define CPG_CE_ERR_STATUS_HI__ECC_MASK                                                                        0x00000001L
15377 #define CPG_CE_ERR_STATUS_HI__OTHER_MASK                                                                      0x00000002L
15378 #define CPG_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK                                                        0x00000004L
15379 #define CPG_CE_ERR_STATUS_HI__ERR_INFO_MASK                                                                   0x007FFFF8L
15380 #define CPG_CE_ERR_STATUS_HI__CE_CNT_MASK                                                                     0x03800000L
15381 #define CPG_CE_ERR_STATUS_HI__POISON_MASK                                                                     0x04000000L
15382 #define CPG_CE_ERR_STATUS_HI__RESERVED_MASK                                                                   0xF8000000L
15383 
15384 
15385 // addressBlock: xcd0_gc_cppdec2
15386 //CP_RB_DOORBELL_CONTROL_SCH_0
15387 #define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_OFFSET__SHIFT                                                  0x2
15388 #define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_EN__SHIFT                                                      0x1e
15389 #define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_HIT__SHIFT                                                     0x1f
15390 #define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_OFFSET_MASK                                                    0x0FFFFFFCL
15391 #define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_EN_MASK                                                        0x40000000L
15392 #define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_HIT_MASK                                                       0x80000000L
15393 //CP_RB_DOORBELL_CONTROL_SCH_1
15394 #define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_OFFSET__SHIFT                                                  0x2
15395 #define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_EN__SHIFT                                                      0x1e
15396 #define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_HIT__SHIFT                                                     0x1f
15397 #define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_OFFSET_MASK                                                    0x0FFFFFFCL
15398 #define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_EN_MASK                                                        0x40000000L
15399 #define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_HIT_MASK                                                       0x80000000L
15400 //CP_RB_DOORBELL_CONTROL_SCH_2
15401 #define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_OFFSET__SHIFT                                                  0x2
15402 #define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_EN__SHIFT                                                      0x1e
15403 #define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_HIT__SHIFT                                                     0x1f
15404 #define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_OFFSET_MASK                                                    0x0FFFFFFCL
15405 #define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_EN_MASK                                                        0x40000000L
15406 #define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_HIT_MASK                                                       0x80000000L
15407 //CP_RB_DOORBELL_CONTROL_SCH_3
15408 #define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_OFFSET__SHIFT                                                  0x2
15409 #define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_EN__SHIFT                                                      0x1e
15410 #define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_HIT__SHIFT                                                     0x1f
15411 #define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_OFFSET_MASK                                                    0x0FFFFFFCL
15412 #define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_EN_MASK                                                        0x40000000L
15413 #define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_HIT_MASK                                                       0x80000000L
15414 //CP_RB_DOORBELL_CONTROL_SCH_4
15415 #define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_OFFSET__SHIFT                                                  0x2
15416 #define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_EN__SHIFT                                                      0x1e
15417 #define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_HIT__SHIFT                                                     0x1f
15418 #define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_OFFSET_MASK                                                    0x0FFFFFFCL
15419 #define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_EN_MASK                                                        0x40000000L
15420 #define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_HIT_MASK                                                       0x80000000L
15421 //CP_RB_DOORBELL_CONTROL_SCH_5
15422 #define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_OFFSET__SHIFT                                                  0x2
15423 #define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_EN__SHIFT                                                      0x1e
15424 #define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_HIT__SHIFT                                                     0x1f
15425 #define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_OFFSET_MASK                                                    0x0FFFFFFCL
15426 #define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_EN_MASK                                                        0x40000000L
15427 #define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_HIT_MASK                                                       0x80000000L
15428 //CP_RB_DOORBELL_CONTROL_SCH_6
15429 #define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_OFFSET__SHIFT                                                  0x2
15430 #define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_EN__SHIFT                                                      0x1e
15431 #define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_HIT__SHIFT                                                     0x1f
15432 #define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_OFFSET_MASK                                                    0x0FFFFFFCL
15433 #define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_EN_MASK                                                        0x40000000L
15434 #define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_HIT_MASK                                                       0x80000000L
15435 //CP_RB_DOORBELL_CONTROL_SCH_7
15436 #define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_OFFSET__SHIFT                                                  0x2
15437 #define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_EN__SHIFT                                                      0x1e
15438 #define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_HIT__SHIFT                                                     0x1f
15439 #define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_OFFSET_MASK                                                    0x0FFFFFFCL
15440 #define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_EN_MASK                                                        0x40000000L
15441 #define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_HIT_MASK                                                       0x80000000L
15442 //CP_RB_DOORBELL_CLEAR
15443 #define CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE__SHIFT                                                             0x0
15444 #define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR__SHIFT                                             0x8
15445 #define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR__SHIFT                                            0x9
15446 #define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR__SHIFT                                                 0xa
15447 #define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR__SHIFT                                                0xb
15448 #define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR__SHIFT                                                 0xc
15449 #define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR__SHIFT                                                0xd
15450 #define CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE_MASK                                                               0x00000007L
15451 #define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR_MASK                                               0x00000100L
15452 #define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR_MASK                                              0x00000200L
15453 #define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR_MASK                                                   0x00000400L
15454 #define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR_MASK                                                  0x00000800L
15455 #define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR_MASK                                                   0x00001000L
15456 #define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR_MASK                                                  0x00002000L
15457 //CP_CPF_DSM_CNTL
15458 #define CP_CPF_DSM_CNTL__CPF0_DSM_IRRITATOR_DATA__SHIFT                                                       0x0
15459 #define CP_CPF_DSM_CNTL__CPF0_ENABLE_SINGLE_WRITE__SHIFT                                                      0x2
15460 #define CP_CPF_DSM_CNTL__CPF1_DSM_IRRITATOR_DATA__SHIFT                                                       0x3
15461 #define CP_CPF_DSM_CNTL__CPF1_ENABLE_SINGLE_WRITE__SHIFT                                                      0x5
15462 #define CP_CPF_DSM_CNTL__CPF2_DSM_IRRITATOR_DATA__SHIFT                                                       0x6
15463 #define CP_CPF_DSM_CNTL__CPF2_ENABLE_SINGLE_WRITE__SHIFT                                                      0x8
15464 #define CP_CPF_DSM_CNTL__CPF0_DSM_IRRITATOR_DATA_MASK                                                         0x00000003L
15465 #define CP_CPF_DSM_CNTL__CPF0_ENABLE_SINGLE_WRITE_MASK                                                        0x00000004L
15466 #define CP_CPF_DSM_CNTL__CPF1_DSM_IRRITATOR_DATA_MASK                                                         0x00000018L
15467 #define CP_CPF_DSM_CNTL__CPF1_ENABLE_SINGLE_WRITE_MASK                                                        0x00000020L
15468 #define CP_CPF_DSM_CNTL__CPF2_DSM_IRRITATOR_DATA_MASK                                                         0x000000C0L
15469 #define CP_CPF_DSM_CNTL__CPF2_ENABLE_SINGLE_WRITE_MASK                                                        0x00000100L
15470 //CP_CPG_DSM_CNTL
15471 #define CP_CPG_DSM_CNTL__CPG0_DSM_IRRITATOR_DATA__SHIFT                                                       0x0
15472 #define CP_CPG_DSM_CNTL__CPG0_ENABLE_SINGLE_WRITE__SHIFT                                                      0x2
15473 #define CP_CPG_DSM_CNTL__CPG1_DSM_IRRITATOR_DATA__SHIFT                                                       0x3
15474 #define CP_CPG_DSM_CNTL__CPG1_ENABLE_SINGLE_WRITE__SHIFT                                                      0x5
15475 #define CP_CPG_DSM_CNTL__CPG2_DSM_IRRITATOR_DATA__SHIFT                                                       0x6
15476 #define CP_CPG_DSM_CNTL__CPG2_ENABLE_SINGLE_WRITE__SHIFT                                                      0x8
15477 #define CP_CPG_DSM_CNTL__CPG0_DSM_IRRITATOR_DATA_MASK                                                         0x00000003L
15478 #define CP_CPG_DSM_CNTL__CPG0_ENABLE_SINGLE_WRITE_MASK                                                        0x00000004L
15479 #define CP_CPG_DSM_CNTL__CPG1_DSM_IRRITATOR_DATA_MASK                                                         0x00000018L
15480 #define CP_CPG_DSM_CNTL__CPG1_ENABLE_SINGLE_WRITE_MASK                                                        0x00000020L
15481 #define CP_CPG_DSM_CNTL__CPG2_DSM_IRRITATOR_DATA_MASK                                                         0x000000C0L
15482 #define CP_CPG_DSM_CNTL__CPG2_ENABLE_SINGLE_WRITE_MASK                                                        0x00000100L
15483 //CP_CPC_DSM_CNTL
15484 #define CP_CPC_DSM_CNTL__CPC0_DSM_IRRITATOR_DATA__SHIFT                                                       0x0
15485 #define CP_CPC_DSM_CNTL__CPC0_ENABLE_SINGLE_WRITE__SHIFT                                                      0x2
15486 #define CP_CPC_DSM_CNTL__CPC1_DSM_IRRITATOR_DATA__SHIFT                                                       0x3
15487 #define CP_CPC_DSM_CNTL__CPC1_ENABLE_SINGLE_WRITE__SHIFT                                                      0x5
15488 #define CP_CPC_DSM_CNTL__CPC2_DSM_IRRITATOR_DATA__SHIFT                                                       0x6
15489 #define CP_CPC_DSM_CNTL__CPC2_ENABLE_SINGLE_WRITE__SHIFT                                                      0x8
15490 #define CP_CPC_DSM_CNTL__CPC3_DSM_IRRITATOR_DATA__SHIFT                                                       0x9
15491 #define CP_CPC_DSM_CNTL__CPC3_ENABLE_SINGLE_WRITE__SHIFT                                                      0xb
15492 #define CP_CPC_DSM_CNTL__CPC4_DSM_IRRITATOR_DATA__SHIFT                                                       0xc
15493 #define CP_CPC_DSM_CNTL__CPC4_ENABLE_SINGLE_WRITE__SHIFT                                                      0xe
15494 #define CP_CPC_DSM_CNTL__CPC5_DSM_IRRITATOR_DATA__SHIFT                                                       0xf
15495 #define CP_CPC_DSM_CNTL__CPC5_ENABLE_SINGLE_WRITE__SHIFT                                                      0x11
15496 #define CP_CPC_DSM_CNTL__CPC6_DSM_IRRITATOR_DATA__SHIFT                                                       0x12
15497 #define CP_CPC_DSM_CNTL__CPC6_ENABLE_SINGLE_WRITE__SHIFT                                                      0x14
15498 #define CP_CPC_DSM_CNTL__CPC7_DSM_IRRITATOR_DATA__SHIFT                                                       0x15
15499 #define CP_CPC_DSM_CNTL__CPC7_ENABLE_SINGLE_WRITE__SHIFT                                                      0x17
15500 #define CP_CPC_DSM_CNTL__CPC8_DSM_IRRITATOR_DATA__SHIFT                                                       0x18
15501 #define CP_CPC_DSM_CNTL__CPC8_ENABLE_SINGLE_WRITE__SHIFT                                                      0x1a
15502 #define CP_CPC_DSM_CNTL__CPC0_DSM_IRRITATOR_DATA_MASK                                                         0x00000003L
15503 #define CP_CPC_DSM_CNTL__CPC0_ENABLE_SINGLE_WRITE_MASK                                                        0x00000004L
15504 #define CP_CPC_DSM_CNTL__CPC1_DSM_IRRITATOR_DATA_MASK                                                         0x00000018L
15505 #define CP_CPC_DSM_CNTL__CPC1_ENABLE_SINGLE_WRITE_MASK                                                        0x00000020L
15506 #define CP_CPC_DSM_CNTL__CPC2_DSM_IRRITATOR_DATA_MASK                                                         0x000000C0L
15507 #define CP_CPC_DSM_CNTL__CPC2_ENABLE_SINGLE_WRITE_MASK                                                        0x00000100L
15508 #define CP_CPC_DSM_CNTL__CPC3_DSM_IRRITATOR_DATA_MASK                                                         0x00000600L
15509 #define CP_CPC_DSM_CNTL__CPC3_ENABLE_SINGLE_WRITE_MASK                                                        0x00000800L
15510 #define CP_CPC_DSM_CNTL__CPC4_DSM_IRRITATOR_DATA_MASK                                                         0x00003000L
15511 #define CP_CPC_DSM_CNTL__CPC4_ENABLE_SINGLE_WRITE_MASK                                                        0x00004000L
15512 #define CP_CPC_DSM_CNTL__CPC5_DSM_IRRITATOR_DATA_MASK                                                         0x00018000L
15513 #define CP_CPC_DSM_CNTL__CPC5_ENABLE_SINGLE_WRITE_MASK                                                        0x00020000L
15514 #define CP_CPC_DSM_CNTL__CPC6_DSM_IRRITATOR_DATA_MASK                                                         0x000C0000L
15515 #define CP_CPC_DSM_CNTL__CPC6_ENABLE_SINGLE_WRITE_MASK                                                        0x00100000L
15516 #define CP_CPC_DSM_CNTL__CPC7_DSM_IRRITATOR_DATA_MASK                                                         0x00600000L
15517 #define CP_CPC_DSM_CNTL__CPC7_ENABLE_SINGLE_WRITE_MASK                                                        0x00800000L
15518 #define CP_CPC_DSM_CNTL__CPC8_DSM_IRRITATOR_DATA_MASK                                                         0x03000000L
15519 #define CP_CPC_DSM_CNTL__CPC8_ENABLE_SINGLE_WRITE_MASK                                                        0x04000000L
15520 //CP_CPF_DSM_CNTL2
15521 #define CP_CPF_DSM_CNTL2__CPF0_ENABLE_ERROR_INJECT__SHIFT                                                     0x0
15522 #define CP_CPF_DSM_CNTL2__CPF0_SELECT_INJECT_DELAY__SHIFT                                                     0x2
15523 #define CP_CPF_DSM_CNTL2__CPF1_ENABLE_ERROR_INJECT__SHIFT                                                     0x3
15524 #define CP_CPF_DSM_CNTL2__CPF1_SELECT_INJECT_DELAY__SHIFT                                                     0x5
15525 #define CP_CPF_DSM_CNTL2__CPF2_ENABLE_ERROR_INJECT__SHIFT                                                     0x6
15526 #define CP_CPF_DSM_CNTL2__CPF2_SELECT_INJECT_DELAY__SHIFT                                                     0x8
15527 #define CP_CPF_DSM_CNTL2__CPF0_ENABLE_ERROR_INJECT_MASK                                                       0x00000003L
15528 #define CP_CPF_DSM_CNTL2__CPF0_SELECT_INJECT_DELAY_MASK                                                       0x00000004L
15529 #define CP_CPF_DSM_CNTL2__CPF1_ENABLE_ERROR_INJECT_MASK                                                       0x00000018L
15530 #define CP_CPF_DSM_CNTL2__CPF1_SELECT_INJECT_DELAY_MASK                                                       0x00000020L
15531 #define CP_CPF_DSM_CNTL2__CPF2_ENABLE_ERROR_INJECT_MASK                                                       0x000000C0L
15532 #define CP_CPF_DSM_CNTL2__CPF2_SELECT_INJECT_DELAY_MASK                                                       0x00000100L
15533 //CP_CPG_DSM_CNTL2
15534 #define CP_CPG_DSM_CNTL2__CPG0_ENABLE_ERROR_INJECT__SHIFT                                                     0x0
15535 #define CP_CPG_DSM_CNTL2__CPG0_SELECT_INJECT_DELAY__SHIFT                                                     0x2
15536 #define CP_CPG_DSM_CNTL2__CPG1_ENABLE_ERROR_INJECT__SHIFT                                                     0x3
15537 #define CP_CPG_DSM_CNTL2__CPG1_SELECT_INJECT_DELAY__SHIFT                                                     0x5
15538 #define CP_CPG_DSM_CNTL2__CPG2_ENABLE_ERROR_INJECT__SHIFT                                                     0x6
15539 #define CP_CPG_DSM_CNTL2__CPG2_SELECT_INJECT_DELAY__SHIFT                                                     0x8
15540 #define CP_CPG_DSM_CNTL2__CPG0_ENABLE_ERROR_INJECT_MASK                                                       0x00000003L
15541 #define CP_CPG_DSM_CNTL2__CPG0_SELECT_INJECT_DELAY_MASK                                                       0x00000004L
15542 #define CP_CPG_DSM_CNTL2__CPG1_ENABLE_ERROR_INJECT_MASK                                                       0x00000018L
15543 #define CP_CPG_DSM_CNTL2__CPG1_SELECT_INJECT_DELAY_MASK                                                       0x00000020L
15544 #define CP_CPG_DSM_CNTL2__CPG2_ENABLE_ERROR_INJECT_MASK                                                       0x000000C0L
15545 #define CP_CPG_DSM_CNTL2__CPG2_SELECT_INJECT_DELAY_MASK                                                       0x00000100L
15546 //CP_CPC_DSM_CNTL2
15547 #define CP_CPC_DSM_CNTL2__CPC0_ENABLE_ERROR_INJECT__SHIFT                                                     0x0
15548 #define CP_CPC_DSM_CNTL2__CPC0_SELECT_INJECT_DELAY__SHIFT                                                     0x2
15549 #define CP_CPC_DSM_CNTL2__CPC1_ENABLE_ERROR_INJECT__SHIFT                                                     0x3
15550 #define CP_CPC_DSM_CNTL2__CPC1_SELECT_INJECT_DELAY__SHIFT                                                     0x5
15551 #define CP_CPC_DSM_CNTL2__CPC2_ENABLE_ERROR_INJECT__SHIFT                                                     0x6
15552 #define CP_CPC_DSM_CNTL2__CPC2_SELECT_INJECT_DELAY__SHIFT                                                     0x8
15553 #define CP_CPC_DSM_CNTL2__CPC3_ENABLE_ERROR_INJECT__SHIFT                                                     0x9
15554 #define CP_CPC_DSM_CNTL2__CPC3_SELECT_INJECT_DELAY__SHIFT                                                     0xb
15555 #define CP_CPC_DSM_CNTL2__CPC4_ENABLE_ERROR_INJECT__SHIFT                                                     0xc
15556 #define CP_CPC_DSM_CNTL2__CPC4_SELECT_INJECT_DELAY__SHIFT                                                     0xe
15557 #define CP_CPC_DSM_CNTL2__CPC5_ENABLE_ERROR_INJECT__SHIFT                                                     0xf
15558 #define CP_CPC_DSM_CNTL2__CPC5_SELECT_INJECT_DELAY__SHIFT                                                     0x11
15559 #define CP_CPC_DSM_CNTL2__CPC6_ENABLE_ERROR_INJECT__SHIFT                                                     0x12
15560 #define CP_CPC_DSM_CNTL2__CPC6_SELECT_INJECT_DELAY__SHIFT                                                     0x14
15561 #define CP_CPC_DSM_CNTL2__CPC7_ENABLE_ERROR_INJECT__SHIFT                                                     0x15
15562 #define CP_CPC_DSM_CNTL2__CPC7_SELECT_INJECT_DELAY__SHIFT                                                     0x17
15563 #define CP_CPC_DSM_CNTL2__CPC8_ENABLE_ERROR_INJECT__SHIFT                                                     0x18
15564 #define CP_CPC_DSM_CNTL2__CPC8_SELECT_INJECT_DELAY__SHIFT                                                     0x1a
15565 #define CP_CPC_DSM_CNTL2__CPC0_ENABLE_ERROR_INJECT_MASK                                                       0x00000003L
15566 #define CP_CPC_DSM_CNTL2__CPC0_SELECT_INJECT_DELAY_MASK                                                       0x00000004L
15567 #define CP_CPC_DSM_CNTL2__CPC1_ENABLE_ERROR_INJECT_MASK                                                       0x00000018L
15568 #define CP_CPC_DSM_CNTL2__CPC1_SELECT_INJECT_DELAY_MASK                                                       0x00000020L
15569 #define CP_CPC_DSM_CNTL2__CPC2_ENABLE_ERROR_INJECT_MASK                                                       0x000000C0L
15570 #define CP_CPC_DSM_CNTL2__CPC2_SELECT_INJECT_DELAY_MASK                                                       0x00000100L
15571 #define CP_CPC_DSM_CNTL2__CPC3_ENABLE_ERROR_INJECT_MASK                                                       0x00000600L
15572 #define CP_CPC_DSM_CNTL2__CPC3_SELECT_INJECT_DELAY_MASK                                                       0x00000800L
15573 #define CP_CPC_DSM_CNTL2__CPC4_ENABLE_ERROR_INJECT_MASK                                                       0x00003000L
15574 #define CP_CPC_DSM_CNTL2__CPC4_SELECT_INJECT_DELAY_MASK                                                       0x00004000L
15575 #define CP_CPC_DSM_CNTL2__CPC5_ENABLE_ERROR_INJECT_MASK                                                       0x00018000L
15576 #define CP_CPC_DSM_CNTL2__CPC5_SELECT_INJECT_DELAY_MASK                                                       0x00020000L
15577 #define CP_CPC_DSM_CNTL2__CPC6_ENABLE_ERROR_INJECT_MASK                                                       0x000C0000L
15578 #define CP_CPC_DSM_CNTL2__CPC6_SELECT_INJECT_DELAY_MASK                                                       0x00100000L
15579 #define CP_CPC_DSM_CNTL2__CPC7_ENABLE_ERROR_INJECT_MASK                                                       0x00600000L
15580 #define CP_CPC_DSM_CNTL2__CPC7_SELECT_INJECT_DELAY_MASK                                                       0x00800000L
15581 #define CP_CPC_DSM_CNTL2__CPC8_ENABLE_ERROR_INJECT_MASK                                                       0x03000000L
15582 #define CP_CPC_DSM_CNTL2__CPC8_SELECT_INJECT_DELAY_MASK                                                       0x04000000L
15583 //CP_CPF_DSM_CNTL2A
15584 #define CP_CPF_DSM_CNTL2A__CPF_INJECT_DELAY__SHIFT                                                            0x0
15585 #define CP_CPF_DSM_CNTL2A__CPF_INJECT_DELAY_MASK                                                              0x0000003FL
15586 //CP_CPG_DSM_CNTL2A
15587 #define CP_CPG_DSM_CNTL2A__CPG_INJECT_DELAY__SHIFT                                                            0x0
15588 #define CP_CPG_DSM_CNTL2A__CPG_INJECT_DELAY_MASK                                                              0x0000003FL
15589 //CP_CPC_DSM_CNTL2A
15590 #define CP_CPC_DSM_CNTL2A__CPC_INJECT_DELAY__SHIFT                                                            0x0
15591 #define CP_CPC_DSM_CNTL2A__CPC_INJECT_DELAY_MASK                                                              0x0000003FL
15592 //CP_EDC_FUE_CNTL
15593 #define CP_EDC_FUE_CNTL__CP_FUE_MASK__SHIFT                                                                   0x0
15594 #define CP_EDC_FUE_CNTL__SPI_FUE_MASK__SHIFT                                                                  0x1
15595 #define CP_EDC_FUE_CNTL__GDS_FUE_MASK__SHIFT                                                                  0x2
15596 #define CP_EDC_FUE_CNTL__TC_RLC_FUE_MASK__SHIFT                                                               0x3
15597 #define CP_EDC_FUE_CNTL__TC_CPG_FUE_MASK__SHIFT                                                               0x4
15598 #define CP_EDC_FUE_CNTL__TCA_FUE_MASK__SHIFT                                                                  0x5
15599 #define CP_EDC_FUE_CNTL__TCC_FUE_MASK__SHIFT                                                                  0x6
15600 #define CP_EDC_FUE_CNTL__UTCL2_FUE_MASK__SHIFT                                                                0x7
15601 #define CP_EDC_FUE_CNTL__CP_FUE_FLAG__SHIFT                                                                   0x10
15602 #define CP_EDC_FUE_CNTL__SPI_FUE_FLAG__SHIFT                                                                  0x11
15603 #define CP_EDC_FUE_CNTL__GDS_FUE_FLAG__SHIFT                                                                  0x12
15604 #define CP_EDC_FUE_CNTL__TC_RLC_FUE_FLAG__SHIFT                                                               0x13
15605 #define CP_EDC_FUE_CNTL__TC_CPG_FUE_FLAG__SHIFT                                                               0x14
15606 #define CP_EDC_FUE_CNTL__TCA_FUE_FLAG__SHIFT                                                                  0x15
15607 #define CP_EDC_FUE_CNTL__TCC_FUE_FLAG__SHIFT                                                                  0x16
15608 #define CP_EDC_FUE_CNTL__UTCL2_FUE_FLAG__SHIFT                                                                0x17
15609 #define CP_EDC_FUE_CNTL__CP_FUE_MASK_MASK                                                                     0x00000001L
15610 #define CP_EDC_FUE_CNTL__SPI_FUE_MASK_MASK                                                                    0x00000002L
15611 #define CP_EDC_FUE_CNTL__GDS_FUE_MASK_MASK                                                                    0x00000004L
15612 #define CP_EDC_FUE_CNTL__TC_RLC_FUE_MASK_MASK                                                                 0x00000008L
15613 #define CP_EDC_FUE_CNTL__TC_CPG_FUE_MASK_MASK                                                                 0x00000010L
15614 #define CP_EDC_FUE_CNTL__TCA_FUE_MASK_MASK                                                                    0x00000020L
15615 #define CP_EDC_FUE_CNTL__TCC_FUE_MASK_MASK                                                                    0x00000040L
15616 #define CP_EDC_FUE_CNTL__UTCL2_FUE_MASK_MASK                                                                  0x00000080L
15617 #define CP_EDC_FUE_CNTL__CP_FUE_FLAG_MASK                                                                     0x00010000L
15618 #define CP_EDC_FUE_CNTL__SPI_FUE_FLAG_MASK                                                                    0x00020000L
15619 #define CP_EDC_FUE_CNTL__GDS_FUE_FLAG_MASK                                                                    0x00040000L
15620 #define CP_EDC_FUE_CNTL__TC_RLC_FUE_FLAG_MASK                                                                 0x00080000L
15621 #define CP_EDC_FUE_CNTL__TC_CPG_FUE_FLAG_MASK                                                                 0x00100000L
15622 #define CP_EDC_FUE_CNTL__TCA_FUE_FLAG_MASK                                                                    0x00200000L
15623 #define CP_EDC_FUE_CNTL__TCC_FUE_FLAG_MASK                                                                    0x00400000L
15624 #define CP_EDC_FUE_CNTL__UTCL2_FUE_FLAG_MASK                                                                  0x00800000L
15625 //CP_GFX_MQD_CONTROL
15626 #define CP_GFX_MQD_CONTROL__VMID__SHIFT                                                                       0x0
15627 #define CP_GFX_MQD_CONTROL__PRIV_STATE__SHIFT                                                                 0x8
15628 #define CP_GFX_MQD_CONTROL__EXE_DISABLE__SHIFT                                                                0x17
15629 #define CP_GFX_MQD_CONTROL__CACHE_POLICY__SHIFT                                                               0x18
15630 #define CP_GFX_MQD_CONTROL__VMID_MASK                                                                         0x0000000FL
15631 #define CP_GFX_MQD_CONTROL__PRIV_STATE_MASK                                                                   0x00000100L
15632 #define CP_GFX_MQD_CONTROL__EXE_DISABLE_MASK                                                                  0x00800000L
15633 #define CP_GFX_MQD_CONTROL__CACHE_POLICY_MASK                                                                 0x01000000L
15634 //CP_GFX_MQD_BASE_ADDR
15635 #define CP_GFX_MQD_BASE_ADDR__BASE_ADDR__SHIFT                                                                0x2
15636 #define CP_GFX_MQD_BASE_ADDR__BASE_ADDR_MASK                                                                  0xFFFFFFFCL
15637 //CP_GFX_MQD_BASE_ADDR_HI
15638 #define CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT                                                          0x0
15639 #define CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK                                                            0x0000FFFFL
15640 //CP_RB_STATUS
15641 #define CP_RB_STATUS__DOORBELL_UPDATED__SHIFT                                                                 0x0
15642 #define CP_RB_STATUS__DOORBELL_ENABLE__SHIFT                                                                  0x1
15643 #define CP_RB_STATUS__DOORBELL_UPDATED_MASK                                                                   0x00000001L
15644 #define CP_RB_STATUS__DOORBELL_ENABLE_MASK                                                                    0x00000002L
15645 //CPG_UTCL1_STATUS
15646 #define CPG_UTCL1_STATUS__FAULT_DETECTED__SHIFT                                                               0x0
15647 #define CPG_UTCL1_STATUS__RETRY_DETECTED__SHIFT                                                               0x1
15648 #define CPG_UTCL1_STATUS__PRT_DETECTED__SHIFT                                                                 0x2
15649 #define CPG_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT                                                                0x8
15650 #define CPG_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT                                                                0x10
15651 #define CPG_UTCL1_STATUS__PRT_UTCL1ID__SHIFT                                                                  0x18
15652 #define CPG_UTCL1_STATUS__FAULT_DETECTED_MASK                                                                 0x00000001L
15653 #define CPG_UTCL1_STATUS__RETRY_DETECTED_MASK                                                                 0x00000002L
15654 #define CPG_UTCL1_STATUS__PRT_DETECTED_MASK                                                                   0x00000004L
15655 #define CPG_UTCL1_STATUS__FAULT_UTCL1ID_MASK                                                                  0x00003F00L
15656 #define CPG_UTCL1_STATUS__RETRY_UTCL1ID_MASK                                                                  0x003F0000L
15657 #define CPG_UTCL1_STATUS__PRT_UTCL1ID_MASK                                                                    0x3F000000L
15658 //CPC_UTCL1_STATUS
15659 #define CPC_UTCL1_STATUS__FAULT_DETECTED__SHIFT                                                               0x0
15660 #define CPC_UTCL1_STATUS__RETRY_DETECTED__SHIFT                                                               0x1
15661 #define CPC_UTCL1_STATUS__PRT_DETECTED__SHIFT                                                                 0x2
15662 #define CPC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT                                                                0x8
15663 #define CPC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT                                                                0x10
15664 #define CPC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT                                                                  0x18
15665 #define CPC_UTCL1_STATUS__FAULT_DETECTED_MASK                                                                 0x00000001L
15666 #define CPC_UTCL1_STATUS__RETRY_DETECTED_MASK                                                                 0x00000002L
15667 #define CPC_UTCL1_STATUS__PRT_DETECTED_MASK                                                                   0x00000004L
15668 #define CPC_UTCL1_STATUS__FAULT_UTCL1ID_MASK                                                                  0x00003F00L
15669 #define CPC_UTCL1_STATUS__RETRY_UTCL1ID_MASK                                                                  0x003F0000L
15670 #define CPC_UTCL1_STATUS__PRT_UTCL1ID_MASK                                                                    0x3F000000L
15671 //CPF_UTCL1_STATUS
15672 #define CPF_UTCL1_STATUS__FAULT_DETECTED__SHIFT                                                               0x0
15673 #define CPF_UTCL1_STATUS__RETRY_DETECTED__SHIFT                                                               0x1
15674 #define CPF_UTCL1_STATUS__PRT_DETECTED__SHIFT                                                                 0x2
15675 #define CPF_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT                                                                0x8
15676 #define CPF_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT                                                                0x10
15677 #define CPF_UTCL1_STATUS__PRT_UTCL1ID__SHIFT                                                                  0x18
15678 #define CPF_UTCL1_STATUS__FAULT_DETECTED_MASK                                                                 0x00000001L
15679 #define CPF_UTCL1_STATUS__RETRY_DETECTED_MASK                                                                 0x00000002L
15680 #define CPF_UTCL1_STATUS__PRT_DETECTED_MASK                                                                   0x00000004L
15681 #define CPF_UTCL1_STATUS__FAULT_UTCL1ID_MASK                                                                  0x00003F00L
15682 #define CPF_UTCL1_STATUS__RETRY_UTCL1ID_MASK                                                                  0x003F0000L
15683 #define CPF_UTCL1_STATUS__PRT_UTCL1ID_MASK                                                                    0x3F000000L
15684 //CP_SD_CNTL
15685 #define CP_SD_CNTL__CPF_EN__SHIFT                                                                             0x0
15686 #define CP_SD_CNTL__CPG_EN__SHIFT                                                                             0x1
15687 #define CP_SD_CNTL__CPC_EN__SHIFT                                                                             0x2
15688 #define CP_SD_CNTL__RLC_EN__SHIFT                                                                             0x3
15689 #define CP_SD_CNTL__SPI_EN__SHIFT                                                                             0x4
15690 #define CP_SD_CNTL__WD_EN__SHIFT                                                                              0x5
15691 #define CP_SD_CNTL__IA_EN__SHIFT                                                                              0x6
15692 #define CP_SD_CNTL__PA_EN__SHIFT                                                                              0x7
15693 #define CP_SD_CNTL__RMI_EN__SHIFT                                                                             0x8
15694 #define CP_SD_CNTL__EA_EN__SHIFT                                                                              0x9
15695 #define CP_SD_CNTL__CPF_EN_MASK                                                                               0x00000001L
15696 #define CP_SD_CNTL__CPG_EN_MASK                                                                               0x00000002L
15697 #define CP_SD_CNTL__CPC_EN_MASK                                                                               0x00000004L
15698 #define CP_SD_CNTL__RLC_EN_MASK                                                                               0x00000008L
15699 #define CP_SD_CNTL__SPI_EN_MASK                                                                               0x00000010L
15700 #define CP_SD_CNTL__WD_EN_MASK                                                                                0x00000020L
15701 #define CP_SD_CNTL__IA_EN_MASK                                                                                0x00000040L
15702 #define CP_SD_CNTL__PA_EN_MASK                                                                                0x00000080L
15703 #define CP_SD_CNTL__RMI_EN_MASK                                                                               0x00000100L
15704 #define CP_SD_CNTL__EA_EN_MASK                                                                                0x00000200L
15705 //CP_SOFT_RESET_CNTL
15706 #define CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET__SHIFT                                                        0x0
15707 #define CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET__SHIFT                                                        0x1
15708 #define CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET__SHIFT                                                          0x2
15709 #define CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET__SHIFT                                                         0x3
15710 #define CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET__SHIFT                                               0x4
15711 #define CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET__SHIFT                                                      0x5
15712 #define CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET__SHIFT                                                         0x6
15713 #define CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET_MASK                                                          0x00000001L
15714 #define CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET_MASK                                                          0x00000002L
15715 #define CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET_MASK                                                            0x00000004L
15716 #define CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET_MASK                                                           0x00000008L
15717 #define CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET_MASK                                                 0x00000010L
15718 #define CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET_MASK                                                        0x00000020L
15719 #define CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET_MASK                                                           0x00000040L
15720 //CP_CPC_GFX_CNTL
15721 #define CP_CPC_GFX_CNTL__QUEUEID__SHIFT                                                                       0x0
15722 #define CP_CPC_GFX_CNTL__PIPEID__SHIFT                                                                        0x3
15723 #define CP_CPC_GFX_CNTL__MEID__SHIFT                                                                          0x5
15724 #define CP_CPC_GFX_CNTL__VALID__SHIFT                                                                         0x7
15725 #define CP_CPC_GFX_CNTL__QUEUEID_MASK                                                                         0x00000007L
15726 #define CP_CPC_GFX_CNTL__PIPEID_MASK                                                                          0x00000018L
15727 #define CP_CPC_GFX_CNTL__MEID_MASK                                                                            0x00000060L
15728 #define CP_CPC_GFX_CNTL__VALID_MASK                                                                           0x00000080L
15729 
15730 
15731 // addressBlock: xcd0_gc_spipdec
15732 //SPI_ARB_PRIORITY
15733 #define SPI_ARB_PRIORITY__PIPE_ORDER_TS0__SHIFT                                                               0x0
15734 #define SPI_ARB_PRIORITY__PIPE_ORDER_TS1__SHIFT                                                               0x3
15735 #define SPI_ARB_PRIORITY__PIPE_ORDER_TS2__SHIFT                                                               0x6
15736 #define SPI_ARB_PRIORITY__PIPE_ORDER_TS3__SHIFT                                                               0x9
15737 #define SPI_ARB_PRIORITY__TS0_DUR_MULT__SHIFT                                                                 0xc
15738 #define SPI_ARB_PRIORITY__TS1_DUR_MULT__SHIFT                                                                 0xe
15739 #define SPI_ARB_PRIORITY__TS2_DUR_MULT__SHIFT                                                                 0x10
15740 #define SPI_ARB_PRIORITY__TS3_DUR_MULT__SHIFT                                                                 0x12
15741 #define SPI_ARB_PRIORITY__PIPE_ORDER_TS0_MASK                                                                 0x00000007L
15742 #define SPI_ARB_PRIORITY__PIPE_ORDER_TS1_MASK                                                                 0x00000038L
15743 #define SPI_ARB_PRIORITY__PIPE_ORDER_TS2_MASK                                                                 0x000001C0L
15744 #define SPI_ARB_PRIORITY__PIPE_ORDER_TS3_MASK                                                                 0x00000E00L
15745 #define SPI_ARB_PRIORITY__TS0_DUR_MULT_MASK                                                                   0x00003000L
15746 #define SPI_ARB_PRIORITY__TS1_DUR_MULT_MASK                                                                   0x0000C000L
15747 #define SPI_ARB_PRIORITY__TS2_DUR_MULT_MASK                                                                   0x00030000L
15748 #define SPI_ARB_PRIORITY__TS3_DUR_MULT_MASK                                                                   0x000C0000L
15749 //SPI_ARB_CYCLES_0
15750 #define SPI_ARB_CYCLES_0__TS0_DURATION__SHIFT                                                                 0x0
15751 #define SPI_ARB_CYCLES_0__TS1_DURATION__SHIFT                                                                 0x10
15752 #define SPI_ARB_CYCLES_0__TS0_DURATION_MASK                                                                   0x0000FFFFL
15753 #define SPI_ARB_CYCLES_0__TS1_DURATION_MASK                                                                   0xFFFF0000L
15754 //SPI_ARB_CYCLES_1
15755 #define SPI_ARB_CYCLES_1__TS2_DURATION__SHIFT                                                                 0x0
15756 #define SPI_ARB_CYCLES_1__TS3_DURATION__SHIFT                                                                 0x10
15757 #define SPI_ARB_CYCLES_1__TS2_DURATION_MASK                                                                   0x0000FFFFL
15758 #define SPI_ARB_CYCLES_1__TS3_DURATION_MASK                                                                   0xFFFF0000L
15759 //SPI_CDBG_SYS_GFX
15760 #define SPI_CDBG_SYS_GFX__PS_EN__SHIFT                                                                        0x0
15761 #define SPI_CDBG_SYS_GFX__VS_EN__SHIFT                                                                        0x1
15762 #define SPI_CDBG_SYS_GFX__GS_EN__SHIFT                                                                        0x2
15763 #define SPI_CDBG_SYS_GFX__ES_EN__SHIFT                                                                        0x3
15764 #define SPI_CDBG_SYS_GFX__HS_EN__SHIFT                                                                        0x4
15765 #define SPI_CDBG_SYS_GFX__LS_EN__SHIFT                                                                        0x5
15766 #define SPI_CDBG_SYS_GFX__CS_EN__SHIFT                                                                        0x6
15767 #define SPI_CDBG_SYS_GFX__PS_EN_MASK                                                                          0x0001L
15768 #define SPI_CDBG_SYS_GFX__VS_EN_MASK                                                                          0x0002L
15769 #define SPI_CDBG_SYS_GFX__GS_EN_MASK                                                                          0x0004L
15770 #define SPI_CDBG_SYS_GFX__ES_EN_MASK                                                                          0x0008L
15771 #define SPI_CDBG_SYS_GFX__HS_EN_MASK                                                                          0x0010L
15772 #define SPI_CDBG_SYS_GFX__LS_EN_MASK                                                                          0x0020L
15773 #define SPI_CDBG_SYS_GFX__CS_EN_MASK                                                                          0x0040L
15774 //SPI_CDBG_SYS_HP3D
15775 #define SPI_CDBG_SYS_HP3D__PS_EN__SHIFT                                                                       0x0
15776 #define SPI_CDBG_SYS_HP3D__VS_EN__SHIFT                                                                       0x1
15777 #define SPI_CDBG_SYS_HP3D__GS_EN__SHIFT                                                                       0x2
15778 #define SPI_CDBG_SYS_HP3D__ES_EN__SHIFT                                                                       0x3
15779 #define SPI_CDBG_SYS_HP3D__HS_EN__SHIFT                                                                       0x4
15780 #define SPI_CDBG_SYS_HP3D__LS_EN__SHIFT                                                                       0x5
15781 #define SPI_CDBG_SYS_HP3D__PS_EN_MASK                                                                         0x0001L
15782 #define SPI_CDBG_SYS_HP3D__VS_EN_MASK                                                                         0x0002L
15783 #define SPI_CDBG_SYS_HP3D__GS_EN_MASK                                                                         0x0004L
15784 #define SPI_CDBG_SYS_HP3D__ES_EN_MASK                                                                         0x0008L
15785 #define SPI_CDBG_SYS_HP3D__HS_EN_MASK                                                                         0x0010L
15786 #define SPI_CDBG_SYS_HP3D__LS_EN_MASK                                                                         0x0020L
15787 //SPI_CDBG_SYS_CS0
15788 #define SPI_CDBG_SYS_CS0__PIPE0__SHIFT                                                                        0x0
15789 #define SPI_CDBG_SYS_CS0__PIPE1__SHIFT                                                                        0x8
15790 #define SPI_CDBG_SYS_CS0__PIPE2__SHIFT                                                                        0x10
15791 #define SPI_CDBG_SYS_CS0__PIPE3__SHIFT                                                                        0x18
15792 #define SPI_CDBG_SYS_CS0__PIPE0_MASK                                                                          0x000000FFL
15793 #define SPI_CDBG_SYS_CS0__PIPE1_MASK                                                                          0x0000FF00L
15794 #define SPI_CDBG_SYS_CS0__PIPE2_MASK                                                                          0x00FF0000L
15795 #define SPI_CDBG_SYS_CS0__PIPE3_MASK                                                                          0xFF000000L
15796 //SPI_CDBG_SYS_CS1
15797 #define SPI_CDBG_SYS_CS1__PIPE0__SHIFT                                                                        0x0
15798 #define SPI_CDBG_SYS_CS1__PIPE1__SHIFT                                                                        0x8
15799 #define SPI_CDBG_SYS_CS1__PIPE2__SHIFT                                                                        0x10
15800 #define SPI_CDBG_SYS_CS1__PIPE3__SHIFT                                                                        0x18
15801 #define SPI_CDBG_SYS_CS1__PIPE0_MASK                                                                          0x000000FFL
15802 #define SPI_CDBG_SYS_CS1__PIPE1_MASK                                                                          0x0000FF00L
15803 #define SPI_CDBG_SYS_CS1__PIPE2_MASK                                                                          0x00FF0000L
15804 #define SPI_CDBG_SYS_CS1__PIPE3_MASK                                                                          0xFF000000L
15805 //SPI_WCL_PIPE_PERCENT_GFX
15806 #define SPI_WCL_PIPE_PERCENT_GFX__VALUE__SHIFT                                                                0x0
15807 #define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE__SHIFT                                                         0x7
15808 #define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE__SHIFT                                                         0xc
15809 #define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE__SHIFT                                                         0x11
15810 #define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE__SHIFT                                                         0x16
15811 #define SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK                                                                  0x0000007FL
15812 #define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE_MASK                                                           0x00000F80L
15813 #define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE_MASK                                                           0x0001F000L
15814 #define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE_MASK                                                           0x003E0000L
15815 #define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE_MASK                                                           0x07C00000L
15816 //SPI_WCL_PIPE_PERCENT_HP3D
15817 #define SPI_WCL_PIPE_PERCENT_HP3D__VALUE__SHIFT                                                               0x0
15818 #define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE__SHIFT                                                        0xc
15819 #define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE__SHIFT                                                        0x16
15820 #define SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK                                                                 0x0000007FL
15821 #define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE_MASK                                                          0x0001F000L
15822 #define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE_MASK                                                          0x07C00000L
15823 //SPI_WCL_PIPE_PERCENT_CS0
15824 #define SPI_WCL_PIPE_PERCENT_CS0__VALUE__SHIFT                                                                0x0
15825 #define SPI_WCL_PIPE_PERCENT_CS0__VALUE_MASK                                                                  0x7FL
15826 //SPI_WCL_PIPE_PERCENT_CS1
15827 #define SPI_WCL_PIPE_PERCENT_CS1__VALUE__SHIFT                                                                0x0
15828 #define SPI_WCL_PIPE_PERCENT_CS1__VALUE_MASK                                                                  0x7FL
15829 //SPI_WCL_PIPE_PERCENT_CS2
15830 #define SPI_WCL_PIPE_PERCENT_CS2__VALUE__SHIFT                                                                0x0
15831 #define SPI_WCL_PIPE_PERCENT_CS2__VALUE_MASK                                                                  0x7FL
15832 //SPI_WCL_PIPE_PERCENT_CS3
15833 #define SPI_WCL_PIPE_PERCENT_CS3__VALUE__SHIFT                                                                0x0
15834 #define SPI_WCL_PIPE_PERCENT_CS3__VALUE_MASK                                                                  0x7FL
15835 //SPI_WCL_PIPE_PERCENT_CS4
15836 #define SPI_WCL_PIPE_PERCENT_CS4__VALUE__SHIFT                                                                0x0
15837 #define SPI_WCL_PIPE_PERCENT_CS4__VALUE_MASK                                                                  0x7FL
15838 //SPI_WCL_PIPE_PERCENT_CS5
15839 #define SPI_WCL_PIPE_PERCENT_CS5__VALUE__SHIFT                                                                0x0
15840 #define SPI_WCL_PIPE_PERCENT_CS5__VALUE_MASK                                                                  0x7FL
15841 //SPI_WCL_PIPE_PERCENT_CS6
15842 #define SPI_WCL_PIPE_PERCENT_CS6__VALUE__SHIFT                                                                0x0
15843 #define SPI_WCL_PIPE_PERCENT_CS6__VALUE_MASK                                                                  0x7FL
15844 //SPI_WCL_PIPE_PERCENT_CS7
15845 #define SPI_WCL_PIPE_PERCENT_CS7__VALUE__SHIFT                                                                0x0
15846 #define SPI_WCL_PIPE_PERCENT_CS7__VALUE_MASK                                                                  0x7FL
15847 //SPI_GDBG_WAVE_CNTL
15848 #define SPI_GDBG_WAVE_CNTL__STALL_RA__SHIFT                                                                   0x0
15849 #define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK                                                                     0x01L
15850 //SPI_GDBG_TRAP_CONFIG
15851 #define SPI_GDBG_TRAP_CONFIG__PIPE0_EN__SHIFT                                                                 0x0
15852 #define SPI_GDBG_TRAP_CONFIG__PIPE1_EN__SHIFT                                                                 0x8
15853 #define SPI_GDBG_TRAP_CONFIG__PIPE2_EN__SHIFT                                                                 0x10
15854 #define SPI_GDBG_TRAP_CONFIG__PIPE3_EN__SHIFT                                                                 0x18
15855 #define SPI_GDBG_TRAP_CONFIG__PIPE0_EN_MASK                                                                   0x000000FFL
15856 #define SPI_GDBG_TRAP_CONFIG__PIPE1_EN_MASK                                                                   0x0000FF00L
15857 #define SPI_GDBG_TRAP_CONFIG__PIPE2_EN_MASK                                                                   0x00FF0000L
15858 #define SPI_GDBG_TRAP_CONFIG__PIPE3_EN_MASK                                                                   0xFF000000L
15859 //SPI_GDBG_PER_VMID_CNTL
15860 #define SPI_GDBG_PER_VMID_CNTL__STALL_VMID__SHIFT                                                             0x0
15861 #define SPI_GDBG_PER_VMID_CNTL__LAUNCH_MODE__SHIFT                                                            0x1
15862 #define SPI_GDBG_PER_VMID_CNTL__TRAP_EN__SHIFT                                                                0x3
15863 #define SPI_GDBG_PER_VMID_CNTL__EXCP_EN__SHIFT                                                                0x4
15864 #define SPI_GDBG_PER_VMID_CNTL__EXCP_REPLACE__SHIFT                                                           0xd
15865 #define SPI_GDBG_PER_VMID_CNTL__TRAP_ON_START__SHIFT                                                          0xe
15866 #define SPI_GDBG_PER_VMID_CNTL__TRAP_ON_END__SHIFT                                                            0xf
15867 #define SPI_GDBG_PER_VMID_CNTL__STALL_VMID_MASK                                                               0x0001L
15868 #define SPI_GDBG_PER_VMID_CNTL__LAUNCH_MODE_MASK                                                              0x0006L
15869 #define SPI_GDBG_PER_VMID_CNTL__TRAP_EN_MASK                                                                  0x0008L
15870 #define SPI_GDBG_PER_VMID_CNTL__EXCP_EN_MASK                                                                  0x1FF0L
15871 #define SPI_GDBG_PER_VMID_CNTL__EXCP_REPLACE_MASK                                                             0x2000L
15872 #define SPI_GDBG_PER_VMID_CNTL__TRAP_ON_START_MASK                                                            0x4000L
15873 #define SPI_GDBG_PER_VMID_CNTL__TRAP_ON_END_MASK                                                              0x8000L
15874 //SPI_GDBG_WAVE_CNTL3
15875 #define SPI_GDBG_WAVE_CNTL3__STALL_PS__SHIFT                                                                  0x0
15876 #define SPI_GDBG_WAVE_CNTL3__STALL_VS__SHIFT                                                                  0x1
15877 #define SPI_GDBG_WAVE_CNTL3__STALL_GS__SHIFT                                                                  0x2
15878 #define SPI_GDBG_WAVE_CNTL3__STALL_HS__SHIFT                                                                  0x3
15879 #define SPI_GDBG_WAVE_CNTL3__STALL_CSG__SHIFT                                                                 0x4
15880 #define SPI_GDBG_WAVE_CNTL3__STALL_CS0__SHIFT                                                                 0x5
15881 #define SPI_GDBG_WAVE_CNTL3__STALL_CS1__SHIFT                                                                 0x6
15882 #define SPI_GDBG_WAVE_CNTL3__STALL_CS2__SHIFT                                                                 0x7
15883 #define SPI_GDBG_WAVE_CNTL3__STALL_CS3__SHIFT                                                                 0x8
15884 #define SPI_GDBG_WAVE_CNTL3__STALL_CS4__SHIFT                                                                 0x9
15885 #define SPI_GDBG_WAVE_CNTL3__STALL_CS5__SHIFT                                                                 0xa
15886 #define SPI_GDBG_WAVE_CNTL3__STALL_CS6__SHIFT                                                                 0xb
15887 #define SPI_GDBG_WAVE_CNTL3__STALL_CS7__SHIFT                                                                 0xc
15888 #define SPI_GDBG_WAVE_CNTL3__STALL_DURATION__SHIFT                                                            0xd
15889 #define SPI_GDBG_WAVE_CNTL3__STALL_MULT__SHIFT                                                                0x1c
15890 #define SPI_GDBG_WAVE_CNTL3__STALL_PS_MASK                                                                    0x00000001L
15891 #define SPI_GDBG_WAVE_CNTL3__STALL_VS_MASK                                                                    0x00000002L
15892 #define SPI_GDBG_WAVE_CNTL3__STALL_GS_MASK                                                                    0x00000004L
15893 #define SPI_GDBG_WAVE_CNTL3__STALL_HS_MASK                                                                    0x00000008L
15894 #define SPI_GDBG_WAVE_CNTL3__STALL_CSG_MASK                                                                   0x00000010L
15895 #define SPI_GDBG_WAVE_CNTL3__STALL_CS0_MASK                                                                   0x00000020L
15896 #define SPI_GDBG_WAVE_CNTL3__STALL_CS1_MASK                                                                   0x00000040L
15897 #define SPI_GDBG_WAVE_CNTL3__STALL_CS2_MASK                                                                   0x00000080L
15898 #define SPI_GDBG_WAVE_CNTL3__STALL_CS3_MASK                                                                   0x00000100L
15899 #define SPI_GDBG_WAVE_CNTL3__STALL_CS4_MASK                                                                   0x00000200L
15900 #define SPI_GDBG_WAVE_CNTL3__STALL_CS5_MASK                                                                   0x00000400L
15901 #define SPI_GDBG_WAVE_CNTL3__STALL_CS6_MASK                                                                   0x00000800L
15902 #define SPI_GDBG_WAVE_CNTL3__STALL_CS7_MASK                                                                   0x00001000L
15903 #define SPI_GDBG_WAVE_CNTL3__STALL_DURATION_MASK                                                              0x0FFFE000L
15904 #define SPI_GDBG_WAVE_CNTL3__STALL_MULT_MASK                                                                  0x10000000L
15905 //SPI_SCRATCH_ADDR_CHECK
15906 #define SPI_SCRATCH_ADDR_CHECK__RESERVED__SHIFT                                                               0x0
15907 #define SPI_SCRATCH_ADDR_CHECK__RESERVED_MASK                                                                 0x0FL
15908 //SPI_SCRATCH_ADDR_STATUS
15909 #define SPI_SCRATCH_ADDR_STATUS__WRITE_DIS__SHIFT                                                             0x0
15910 #define SPI_SCRATCH_ADDR_STATUS__OVERFLOW_DETECTED__SHIFT                                                     0x1
15911 #define SPI_SCRATCH_ADDR_STATUS__ME_ID__SHIFT                                                                 0x2
15912 #define SPI_SCRATCH_ADDR_STATUS__PIPE_ID__SHIFT                                                               0x4
15913 #define SPI_SCRATCH_ADDR_STATUS__WRITE_DIS_MASK                                                               0x01L
15914 #define SPI_SCRATCH_ADDR_STATUS__OVERFLOW_DETECTED_MASK                                                       0x02L
15915 #define SPI_SCRATCH_ADDR_STATUS__ME_ID_MASK                                                                   0x0CL
15916 #define SPI_SCRATCH_ADDR_STATUS__PIPE_ID_MASK                                                                 0x30L
15917 //SPI_RESET_DEBUG
15918 #define SPI_RESET_DEBUG__DISABLE_GFX_RESET__SHIFT                                                             0x0
15919 #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PER_VMID__SHIFT                                                    0x1
15920 #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_ALL_VMID__SHIFT                                                    0x2
15921 #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_RESOURCE__SHIFT                                                    0x3
15922 #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PRIORITY__SHIFT                                                    0x4
15923 #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_MASK                                                               0x01L
15924 #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PER_VMID_MASK                                                      0x02L
15925 #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_ALL_VMID_MASK                                                      0x04L
15926 #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_RESOURCE_MASK                                                      0x08L
15927 #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PRIORITY_MASK                                                      0x10L
15928 //SPI_COMPUTE_QUEUE_RESET
15929 #define SPI_COMPUTE_QUEUE_RESET__RESET__SHIFT                                                                 0x0
15930 #define SPI_COMPUTE_QUEUE_RESET__RESET_MASK                                                                   0x01L
15931 //SPI_RESOURCE_RESERVE_CU_0
15932 #define SPI_RESOURCE_RESERVE_CU_0__VGPR__SHIFT                                                                0x0
15933 #define SPI_RESOURCE_RESERVE_CU_0__SGPR__SHIFT                                                                0x4
15934 #define SPI_RESOURCE_RESERVE_CU_0__LDS__SHIFT                                                                 0x8
15935 #define SPI_RESOURCE_RESERVE_CU_0__WAVES__SHIFT                                                               0xc
15936 #define SPI_RESOURCE_RESERVE_CU_0__BARRIERS__SHIFT                                                            0xf
15937 #define SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK                                                                  0x0000000FL
15938 #define SPI_RESOURCE_RESERVE_CU_0__SGPR_MASK                                                                  0x000000F0L
15939 #define SPI_RESOURCE_RESERVE_CU_0__LDS_MASK                                                                   0x00000F00L
15940 #define SPI_RESOURCE_RESERVE_CU_0__WAVES_MASK                                                                 0x00007000L
15941 #define SPI_RESOURCE_RESERVE_CU_0__BARRIERS_MASK                                                              0x00078000L
15942 //SPI_RESOURCE_RESERVE_CU_1
15943 #define SPI_RESOURCE_RESERVE_CU_1__VGPR__SHIFT                                                                0x0
15944 #define SPI_RESOURCE_RESERVE_CU_1__SGPR__SHIFT                                                                0x4
15945 #define SPI_RESOURCE_RESERVE_CU_1__LDS__SHIFT                                                                 0x8
15946 #define SPI_RESOURCE_RESERVE_CU_1__WAVES__SHIFT                                                               0xc
15947 #define SPI_RESOURCE_RESERVE_CU_1__BARRIERS__SHIFT                                                            0xf
15948 #define SPI_RESOURCE_RESERVE_CU_1__VGPR_MASK                                                                  0x0000000FL
15949 #define SPI_RESOURCE_RESERVE_CU_1__SGPR_MASK                                                                  0x000000F0L
15950 #define SPI_RESOURCE_RESERVE_CU_1__LDS_MASK                                                                   0x00000F00L
15951 #define SPI_RESOURCE_RESERVE_CU_1__WAVES_MASK                                                                 0x00007000L
15952 #define SPI_RESOURCE_RESERVE_CU_1__BARRIERS_MASK                                                              0x00078000L
15953 //SPI_RESOURCE_RESERVE_CU_2
15954 #define SPI_RESOURCE_RESERVE_CU_2__VGPR__SHIFT                                                                0x0
15955 #define SPI_RESOURCE_RESERVE_CU_2__SGPR__SHIFT                                                                0x4
15956 #define SPI_RESOURCE_RESERVE_CU_2__LDS__SHIFT                                                                 0x8
15957 #define SPI_RESOURCE_RESERVE_CU_2__WAVES__SHIFT                                                               0xc
15958 #define SPI_RESOURCE_RESERVE_CU_2__BARRIERS__SHIFT                                                            0xf
15959 #define SPI_RESOURCE_RESERVE_CU_2__VGPR_MASK                                                                  0x0000000FL
15960 #define SPI_RESOURCE_RESERVE_CU_2__SGPR_MASK                                                                  0x000000F0L
15961 #define SPI_RESOURCE_RESERVE_CU_2__LDS_MASK                                                                   0x00000F00L
15962 #define SPI_RESOURCE_RESERVE_CU_2__WAVES_MASK                                                                 0x00007000L
15963 #define SPI_RESOURCE_RESERVE_CU_2__BARRIERS_MASK                                                              0x00078000L
15964 //SPI_RESOURCE_RESERVE_CU_3
15965 #define SPI_RESOURCE_RESERVE_CU_3__VGPR__SHIFT                                                                0x0
15966 #define SPI_RESOURCE_RESERVE_CU_3__SGPR__SHIFT                                                                0x4
15967 #define SPI_RESOURCE_RESERVE_CU_3__LDS__SHIFT                                                                 0x8
15968 #define SPI_RESOURCE_RESERVE_CU_3__WAVES__SHIFT                                                               0xc
15969 #define SPI_RESOURCE_RESERVE_CU_3__BARRIERS__SHIFT                                                            0xf
15970 #define SPI_RESOURCE_RESERVE_CU_3__VGPR_MASK                                                                  0x0000000FL
15971 #define SPI_RESOURCE_RESERVE_CU_3__SGPR_MASK                                                                  0x000000F0L
15972 #define SPI_RESOURCE_RESERVE_CU_3__LDS_MASK                                                                   0x00000F00L
15973 #define SPI_RESOURCE_RESERVE_CU_3__WAVES_MASK                                                                 0x00007000L
15974 #define SPI_RESOURCE_RESERVE_CU_3__BARRIERS_MASK                                                              0x00078000L
15975 //SPI_RESOURCE_RESERVE_CU_4
15976 #define SPI_RESOURCE_RESERVE_CU_4__VGPR__SHIFT                                                                0x0
15977 #define SPI_RESOURCE_RESERVE_CU_4__SGPR__SHIFT                                                                0x4
15978 #define SPI_RESOURCE_RESERVE_CU_4__LDS__SHIFT                                                                 0x8
15979 #define SPI_RESOURCE_RESERVE_CU_4__WAVES__SHIFT                                                               0xc
15980 #define SPI_RESOURCE_RESERVE_CU_4__BARRIERS__SHIFT                                                            0xf
15981 #define SPI_RESOURCE_RESERVE_CU_4__VGPR_MASK                                                                  0x0000000FL
15982 #define SPI_RESOURCE_RESERVE_CU_4__SGPR_MASK                                                                  0x000000F0L
15983 #define SPI_RESOURCE_RESERVE_CU_4__LDS_MASK                                                                   0x00000F00L
15984 #define SPI_RESOURCE_RESERVE_CU_4__WAVES_MASK                                                                 0x00007000L
15985 #define SPI_RESOURCE_RESERVE_CU_4__BARRIERS_MASK                                                              0x00078000L
15986 //SPI_RESOURCE_RESERVE_CU_5
15987 #define SPI_RESOURCE_RESERVE_CU_5__VGPR__SHIFT                                                                0x0
15988 #define SPI_RESOURCE_RESERVE_CU_5__SGPR__SHIFT                                                                0x4
15989 #define SPI_RESOURCE_RESERVE_CU_5__LDS__SHIFT                                                                 0x8
15990 #define SPI_RESOURCE_RESERVE_CU_5__WAVES__SHIFT                                                               0xc
15991 #define SPI_RESOURCE_RESERVE_CU_5__BARRIERS__SHIFT                                                            0xf
15992 #define SPI_RESOURCE_RESERVE_CU_5__VGPR_MASK                                                                  0x0000000FL
15993 #define SPI_RESOURCE_RESERVE_CU_5__SGPR_MASK                                                                  0x000000F0L
15994 #define SPI_RESOURCE_RESERVE_CU_5__LDS_MASK                                                                   0x00000F00L
15995 #define SPI_RESOURCE_RESERVE_CU_5__WAVES_MASK                                                                 0x00007000L
15996 #define SPI_RESOURCE_RESERVE_CU_5__BARRIERS_MASK                                                              0x00078000L
15997 //SPI_RESOURCE_RESERVE_CU_6
15998 #define SPI_RESOURCE_RESERVE_CU_6__VGPR__SHIFT                                                                0x0
15999 #define SPI_RESOURCE_RESERVE_CU_6__SGPR__SHIFT                                                                0x4
16000 #define SPI_RESOURCE_RESERVE_CU_6__LDS__SHIFT                                                                 0x8
16001 #define SPI_RESOURCE_RESERVE_CU_6__WAVES__SHIFT                                                               0xc
16002 #define SPI_RESOURCE_RESERVE_CU_6__BARRIERS__SHIFT                                                            0xf
16003 #define SPI_RESOURCE_RESERVE_CU_6__VGPR_MASK                                                                  0x0000000FL
16004 #define SPI_RESOURCE_RESERVE_CU_6__SGPR_MASK                                                                  0x000000F0L
16005 #define SPI_RESOURCE_RESERVE_CU_6__LDS_MASK                                                                   0x00000F00L
16006 #define SPI_RESOURCE_RESERVE_CU_6__WAVES_MASK                                                                 0x00007000L
16007 #define SPI_RESOURCE_RESERVE_CU_6__BARRIERS_MASK                                                              0x00078000L
16008 //SPI_RESOURCE_RESERVE_CU_7
16009 #define SPI_RESOURCE_RESERVE_CU_7__VGPR__SHIFT                                                                0x0
16010 #define SPI_RESOURCE_RESERVE_CU_7__SGPR__SHIFT                                                                0x4
16011 #define SPI_RESOURCE_RESERVE_CU_7__LDS__SHIFT                                                                 0x8
16012 #define SPI_RESOURCE_RESERVE_CU_7__WAVES__SHIFT                                                               0xc
16013 #define SPI_RESOURCE_RESERVE_CU_7__BARRIERS__SHIFT                                                            0xf
16014 #define SPI_RESOURCE_RESERVE_CU_7__VGPR_MASK                                                                  0x0000000FL
16015 #define SPI_RESOURCE_RESERVE_CU_7__SGPR_MASK                                                                  0x000000F0L
16016 #define SPI_RESOURCE_RESERVE_CU_7__LDS_MASK                                                                   0x00000F00L
16017 #define SPI_RESOURCE_RESERVE_CU_7__WAVES_MASK                                                                 0x00007000L
16018 #define SPI_RESOURCE_RESERVE_CU_7__BARRIERS_MASK                                                              0x00078000L
16019 //SPI_RESOURCE_RESERVE_CU_8
16020 #define SPI_RESOURCE_RESERVE_CU_8__VGPR__SHIFT                                                                0x0
16021 #define SPI_RESOURCE_RESERVE_CU_8__SGPR__SHIFT                                                                0x4
16022 #define SPI_RESOURCE_RESERVE_CU_8__LDS__SHIFT                                                                 0x8
16023 #define SPI_RESOURCE_RESERVE_CU_8__WAVES__SHIFT                                                               0xc
16024 #define SPI_RESOURCE_RESERVE_CU_8__BARRIERS__SHIFT                                                            0xf
16025 #define SPI_RESOURCE_RESERVE_CU_8__VGPR_MASK                                                                  0x0000000FL
16026 #define SPI_RESOURCE_RESERVE_CU_8__SGPR_MASK                                                                  0x000000F0L
16027 #define SPI_RESOURCE_RESERVE_CU_8__LDS_MASK                                                                   0x00000F00L
16028 #define SPI_RESOURCE_RESERVE_CU_8__WAVES_MASK                                                                 0x00007000L
16029 #define SPI_RESOURCE_RESERVE_CU_8__BARRIERS_MASK                                                              0x00078000L
16030 //SPI_RESOURCE_RESERVE_CU_9
16031 #define SPI_RESOURCE_RESERVE_CU_9__VGPR__SHIFT                                                                0x0
16032 #define SPI_RESOURCE_RESERVE_CU_9__SGPR__SHIFT                                                                0x4
16033 #define SPI_RESOURCE_RESERVE_CU_9__LDS__SHIFT                                                                 0x8
16034 #define SPI_RESOURCE_RESERVE_CU_9__WAVES__SHIFT                                                               0xc
16035 #define SPI_RESOURCE_RESERVE_CU_9__BARRIERS__SHIFT                                                            0xf
16036 #define SPI_RESOURCE_RESERVE_CU_9__VGPR_MASK                                                                  0x0000000FL
16037 #define SPI_RESOURCE_RESERVE_CU_9__SGPR_MASK                                                                  0x000000F0L
16038 #define SPI_RESOURCE_RESERVE_CU_9__LDS_MASK                                                                   0x00000F00L
16039 #define SPI_RESOURCE_RESERVE_CU_9__WAVES_MASK                                                                 0x00007000L
16040 #define SPI_RESOURCE_RESERVE_CU_9__BARRIERS_MASK                                                              0x00078000L
16041 //SPI_RESOURCE_RESERVE_EN_CU_0
16042 #define SPI_RESOURCE_RESERVE_EN_CU_0__EN__SHIFT                                                               0x0
16043 #define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK__SHIFT                                                        0x1
16044 #define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK__SHIFT                                                       0x10
16045 #define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY__SHIFT                                               0x18
16046 #define SPI_RESOURCE_RESERVE_EN_CU_0__EN_MASK                                                                 0x00000001L
16047 #define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK_MASK                                                          0x0000FFFEL
16048 #define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK_MASK                                                         0x00FF0000L
16049 #define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY_MASK                                                 0x01000000L
16050 //SPI_RESOURCE_RESERVE_EN_CU_1
16051 #define SPI_RESOURCE_RESERVE_EN_CU_1__EN__SHIFT                                                               0x0
16052 #define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK__SHIFT                                                        0x1
16053 #define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK__SHIFT                                                       0x10
16054 #define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY__SHIFT                                               0x18
16055 #define SPI_RESOURCE_RESERVE_EN_CU_1__EN_MASK                                                                 0x00000001L
16056 #define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK_MASK                                                          0x0000FFFEL
16057 #define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK_MASK                                                         0x00FF0000L
16058 #define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY_MASK                                                 0x01000000L
16059 //SPI_RESOURCE_RESERVE_EN_CU_2
16060 #define SPI_RESOURCE_RESERVE_EN_CU_2__EN__SHIFT                                                               0x0
16061 #define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK__SHIFT                                                        0x1
16062 #define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK__SHIFT                                                       0x10
16063 #define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY__SHIFT                                               0x18
16064 #define SPI_RESOURCE_RESERVE_EN_CU_2__EN_MASK                                                                 0x00000001L
16065 #define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK_MASK                                                          0x0000FFFEL
16066 #define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK_MASK                                                         0x00FF0000L
16067 #define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY_MASK                                                 0x01000000L
16068 //SPI_RESOURCE_RESERVE_EN_CU_3
16069 #define SPI_RESOURCE_RESERVE_EN_CU_3__EN__SHIFT                                                               0x0
16070 #define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK__SHIFT                                                        0x1
16071 #define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK__SHIFT                                                       0x10
16072 #define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY__SHIFT                                               0x18
16073 #define SPI_RESOURCE_RESERVE_EN_CU_3__EN_MASK                                                                 0x00000001L
16074 #define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK_MASK                                                          0x0000FFFEL
16075 #define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK_MASK                                                         0x00FF0000L
16076 #define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY_MASK                                                 0x01000000L
16077 //SPI_RESOURCE_RESERVE_EN_CU_4
16078 #define SPI_RESOURCE_RESERVE_EN_CU_4__EN__SHIFT                                                               0x0
16079 #define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK__SHIFT                                                        0x1
16080 #define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK__SHIFT                                                       0x10
16081 #define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY__SHIFT                                               0x18
16082 #define SPI_RESOURCE_RESERVE_EN_CU_4__EN_MASK                                                                 0x00000001L
16083 #define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK_MASK                                                          0x0000FFFEL
16084 #define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK_MASK                                                         0x00FF0000L
16085 #define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY_MASK                                                 0x01000000L
16086 //SPI_RESOURCE_RESERVE_EN_CU_5
16087 #define SPI_RESOURCE_RESERVE_EN_CU_5__EN__SHIFT                                                               0x0
16088 #define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK__SHIFT                                                        0x1
16089 #define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK__SHIFT                                                       0x10
16090 #define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY__SHIFT                                               0x18
16091 #define SPI_RESOURCE_RESERVE_EN_CU_5__EN_MASK                                                                 0x00000001L
16092 #define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK_MASK                                                          0x0000FFFEL
16093 #define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK_MASK                                                         0x00FF0000L
16094 #define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY_MASK                                                 0x01000000L
16095 //SPI_RESOURCE_RESERVE_EN_CU_6
16096 #define SPI_RESOURCE_RESERVE_EN_CU_6__EN__SHIFT                                                               0x0
16097 #define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK__SHIFT                                                        0x1
16098 #define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK__SHIFT                                                       0x10
16099 #define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY__SHIFT                                               0x18
16100 #define SPI_RESOURCE_RESERVE_EN_CU_6__EN_MASK                                                                 0x00000001L
16101 #define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK_MASK                                                          0x0000FFFEL
16102 #define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK_MASK                                                         0x00FF0000L
16103 #define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY_MASK                                                 0x01000000L
16104 //SPI_RESOURCE_RESERVE_EN_CU_7
16105 #define SPI_RESOURCE_RESERVE_EN_CU_7__EN__SHIFT                                                               0x0
16106 #define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK__SHIFT                                                        0x1
16107 #define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK__SHIFT                                                       0x10
16108 #define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY__SHIFT                                               0x18
16109 #define SPI_RESOURCE_RESERVE_EN_CU_7__EN_MASK                                                                 0x00000001L
16110 #define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK_MASK                                                          0x0000FFFEL
16111 #define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK_MASK                                                         0x00FF0000L
16112 #define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY_MASK                                                 0x01000000L
16113 //SPI_RESOURCE_RESERVE_EN_CU_8
16114 #define SPI_RESOURCE_RESERVE_EN_CU_8__EN__SHIFT                                                               0x0
16115 #define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK__SHIFT                                                        0x1
16116 #define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK__SHIFT                                                       0x10
16117 #define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY__SHIFT                                               0x18
16118 #define SPI_RESOURCE_RESERVE_EN_CU_8__EN_MASK                                                                 0x00000001L
16119 #define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK_MASK                                                          0x0000FFFEL
16120 #define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK_MASK                                                         0x00FF0000L
16121 #define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY_MASK                                                 0x01000000L
16122 //SPI_RESOURCE_RESERVE_EN_CU_9
16123 #define SPI_RESOURCE_RESERVE_EN_CU_9__EN__SHIFT                                                               0x0
16124 #define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK__SHIFT                                                        0x1
16125 #define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK__SHIFT                                                       0x10
16126 #define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY__SHIFT                                               0x18
16127 #define SPI_RESOURCE_RESERVE_EN_CU_9__EN_MASK                                                                 0x00000001L
16128 #define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK_MASK                                                          0x0000FFFEL
16129 #define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK_MASK                                                         0x00FF0000L
16130 #define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY_MASK                                                 0x01000000L
16131 //SPI_RESOURCE_RESERVE_CU_10
16132 #define SPI_RESOURCE_RESERVE_CU_10__VGPR__SHIFT                                                               0x0
16133 #define SPI_RESOURCE_RESERVE_CU_10__SGPR__SHIFT                                                               0x4
16134 #define SPI_RESOURCE_RESERVE_CU_10__LDS__SHIFT                                                                0x8
16135 #define SPI_RESOURCE_RESERVE_CU_10__WAVES__SHIFT                                                              0xc
16136 #define SPI_RESOURCE_RESERVE_CU_10__BARRIERS__SHIFT                                                           0xf
16137 #define SPI_RESOURCE_RESERVE_CU_10__VGPR_MASK                                                                 0x0000000FL
16138 #define SPI_RESOURCE_RESERVE_CU_10__SGPR_MASK                                                                 0x000000F0L
16139 #define SPI_RESOURCE_RESERVE_CU_10__LDS_MASK                                                                  0x00000F00L
16140 #define SPI_RESOURCE_RESERVE_CU_10__WAVES_MASK                                                                0x00007000L
16141 #define SPI_RESOURCE_RESERVE_CU_10__BARRIERS_MASK                                                             0x00078000L
16142 //SPI_RESOURCE_RESERVE_CU_11
16143 #define SPI_RESOURCE_RESERVE_CU_11__VGPR__SHIFT                                                               0x0
16144 #define SPI_RESOURCE_RESERVE_CU_11__SGPR__SHIFT                                                               0x4
16145 #define SPI_RESOURCE_RESERVE_CU_11__LDS__SHIFT                                                                0x8
16146 #define SPI_RESOURCE_RESERVE_CU_11__WAVES__SHIFT                                                              0xc
16147 #define SPI_RESOURCE_RESERVE_CU_11__BARRIERS__SHIFT                                                           0xf
16148 #define SPI_RESOURCE_RESERVE_CU_11__VGPR_MASK                                                                 0x0000000FL
16149 #define SPI_RESOURCE_RESERVE_CU_11__SGPR_MASK                                                                 0x000000F0L
16150 #define SPI_RESOURCE_RESERVE_CU_11__LDS_MASK                                                                  0x00000F00L
16151 #define SPI_RESOURCE_RESERVE_CU_11__WAVES_MASK                                                                0x00007000L
16152 #define SPI_RESOURCE_RESERVE_CU_11__BARRIERS_MASK                                                             0x00078000L
16153 //SPI_RESOURCE_RESERVE_EN_CU_10
16154 #define SPI_RESOURCE_RESERVE_EN_CU_10__EN__SHIFT                                                              0x0
16155 #define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK__SHIFT                                                       0x1
16156 #define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK__SHIFT                                                      0x10
16157 #define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY__SHIFT                                              0x18
16158 #define SPI_RESOURCE_RESERVE_EN_CU_10__EN_MASK                                                                0x00000001L
16159 #define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK_MASK                                                         0x0000FFFEL
16160 #define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK_MASK                                                        0x00FF0000L
16161 #define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY_MASK                                                0x01000000L
16162 //SPI_RESOURCE_RESERVE_EN_CU_11
16163 #define SPI_RESOURCE_RESERVE_EN_CU_11__EN__SHIFT                                                              0x0
16164 #define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK__SHIFT                                                       0x1
16165 #define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK__SHIFT                                                      0x10
16166 #define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY__SHIFT                                              0x18
16167 #define SPI_RESOURCE_RESERVE_EN_CU_11__EN_MASK                                                                0x00000001L
16168 #define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK_MASK                                                         0x0000FFFEL
16169 #define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK_MASK                                                        0x00FF0000L
16170 #define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY_MASK                                                0x01000000L
16171 //SPI_RESOURCE_RESERVE_CU_12
16172 #define SPI_RESOURCE_RESERVE_CU_12__VGPR__SHIFT                                                               0x0
16173 #define SPI_RESOURCE_RESERVE_CU_12__SGPR__SHIFT                                                               0x4
16174 #define SPI_RESOURCE_RESERVE_CU_12__LDS__SHIFT                                                                0x8
16175 #define SPI_RESOURCE_RESERVE_CU_12__WAVES__SHIFT                                                              0xc
16176 #define SPI_RESOURCE_RESERVE_CU_12__BARRIERS__SHIFT                                                           0xf
16177 #define SPI_RESOURCE_RESERVE_CU_12__VGPR_MASK                                                                 0x0000000FL
16178 #define SPI_RESOURCE_RESERVE_CU_12__SGPR_MASK                                                                 0x000000F0L
16179 #define SPI_RESOURCE_RESERVE_CU_12__LDS_MASK                                                                  0x00000F00L
16180 #define SPI_RESOURCE_RESERVE_CU_12__WAVES_MASK                                                                0x00007000L
16181 #define SPI_RESOURCE_RESERVE_CU_12__BARRIERS_MASK                                                             0x00078000L
16182 //SPI_RESOURCE_RESERVE_CU_13
16183 #define SPI_RESOURCE_RESERVE_CU_13__VGPR__SHIFT                                                               0x0
16184 #define SPI_RESOURCE_RESERVE_CU_13__SGPR__SHIFT                                                               0x4
16185 #define SPI_RESOURCE_RESERVE_CU_13__LDS__SHIFT                                                                0x8
16186 #define SPI_RESOURCE_RESERVE_CU_13__WAVES__SHIFT                                                              0xc
16187 #define SPI_RESOURCE_RESERVE_CU_13__BARRIERS__SHIFT                                                           0xf
16188 #define SPI_RESOURCE_RESERVE_CU_13__VGPR_MASK                                                                 0x0000000FL
16189 #define SPI_RESOURCE_RESERVE_CU_13__SGPR_MASK                                                                 0x000000F0L
16190 #define SPI_RESOURCE_RESERVE_CU_13__LDS_MASK                                                                  0x00000F00L
16191 #define SPI_RESOURCE_RESERVE_CU_13__WAVES_MASK                                                                0x00007000L
16192 #define SPI_RESOURCE_RESERVE_CU_13__BARRIERS_MASK                                                             0x00078000L
16193 //SPI_RESOURCE_RESERVE_CU_14
16194 #define SPI_RESOURCE_RESERVE_CU_14__VGPR__SHIFT                                                               0x0
16195 #define SPI_RESOURCE_RESERVE_CU_14__SGPR__SHIFT                                                               0x4
16196 #define SPI_RESOURCE_RESERVE_CU_14__LDS__SHIFT                                                                0x8
16197 #define SPI_RESOURCE_RESERVE_CU_14__WAVES__SHIFT                                                              0xc
16198 #define SPI_RESOURCE_RESERVE_CU_14__BARRIERS__SHIFT                                                           0xf
16199 #define SPI_RESOURCE_RESERVE_CU_14__VGPR_MASK                                                                 0x0000000FL
16200 #define SPI_RESOURCE_RESERVE_CU_14__SGPR_MASK                                                                 0x000000F0L
16201 #define SPI_RESOURCE_RESERVE_CU_14__LDS_MASK                                                                  0x00000F00L
16202 #define SPI_RESOURCE_RESERVE_CU_14__WAVES_MASK                                                                0x00007000L
16203 #define SPI_RESOURCE_RESERVE_CU_14__BARRIERS_MASK                                                             0x00078000L
16204 //SPI_RESOURCE_RESERVE_CU_15
16205 #define SPI_RESOURCE_RESERVE_CU_15__VGPR__SHIFT                                                               0x0
16206 #define SPI_RESOURCE_RESERVE_CU_15__SGPR__SHIFT                                                               0x4
16207 #define SPI_RESOURCE_RESERVE_CU_15__LDS__SHIFT                                                                0x8
16208 #define SPI_RESOURCE_RESERVE_CU_15__WAVES__SHIFT                                                              0xc
16209 #define SPI_RESOURCE_RESERVE_CU_15__BARRIERS__SHIFT                                                           0xf
16210 #define SPI_RESOURCE_RESERVE_CU_15__VGPR_MASK                                                                 0x0000000FL
16211 #define SPI_RESOURCE_RESERVE_CU_15__SGPR_MASK                                                                 0x000000F0L
16212 #define SPI_RESOURCE_RESERVE_CU_15__LDS_MASK                                                                  0x00000F00L
16213 #define SPI_RESOURCE_RESERVE_CU_15__WAVES_MASK                                                                0x00007000L
16214 #define SPI_RESOURCE_RESERVE_CU_15__BARRIERS_MASK                                                             0x00078000L
16215 //SPI_RESOURCE_RESERVE_EN_CU_12
16216 #define SPI_RESOURCE_RESERVE_EN_CU_12__EN__SHIFT                                                              0x0
16217 #define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK__SHIFT                                                       0x1
16218 #define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK__SHIFT                                                      0x10
16219 #define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY__SHIFT                                              0x18
16220 #define SPI_RESOURCE_RESERVE_EN_CU_12__EN_MASK                                                                0x00000001L
16221 #define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK_MASK                                                         0x0000FFFEL
16222 #define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK_MASK                                                        0x00FF0000L
16223 #define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY_MASK                                                0x01000000L
16224 //SPI_RESOURCE_RESERVE_EN_CU_13
16225 #define SPI_RESOURCE_RESERVE_EN_CU_13__EN__SHIFT                                                              0x0
16226 #define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK__SHIFT                                                       0x1
16227 #define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK__SHIFT                                                      0x10
16228 #define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY__SHIFT                                              0x18
16229 #define SPI_RESOURCE_RESERVE_EN_CU_13__EN_MASK                                                                0x00000001L
16230 #define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK_MASK                                                         0x0000FFFEL
16231 #define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK_MASK                                                        0x00FF0000L
16232 #define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY_MASK                                                0x01000000L
16233 //SPI_RESOURCE_RESERVE_EN_CU_14
16234 #define SPI_RESOURCE_RESERVE_EN_CU_14__EN__SHIFT                                                              0x0
16235 #define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK__SHIFT                                                       0x1
16236 #define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK__SHIFT                                                      0x10
16237 #define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY__SHIFT                                              0x18
16238 #define SPI_RESOURCE_RESERVE_EN_CU_14__EN_MASK                                                                0x00000001L
16239 #define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK_MASK                                                         0x0000FFFEL
16240 #define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK_MASK                                                        0x00FF0000L
16241 #define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY_MASK                                                0x01000000L
16242 //SPI_RESOURCE_RESERVE_EN_CU_15
16243 #define SPI_RESOURCE_RESERVE_EN_CU_15__EN__SHIFT                                                              0x0
16244 #define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK__SHIFT                                                       0x1
16245 #define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK__SHIFT                                                      0x10
16246 #define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY__SHIFT                                              0x18
16247 #define SPI_RESOURCE_RESERVE_EN_CU_15__EN_MASK                                                                0x00000001L
16248 #define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK_MASK                                                         0x0000FFFEL
16249 #define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK_MASK                                                        0x00FF0000L
16250 #define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY_MASK                                                0x01000000L
16251 //SPI_COMPUTE_WF_CTX_SAVE
16252 #define SPI_COMPUTE_WF_CTX_SAVE__INITIATE__SHIFT                                                              0x0
16253 #define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN__SHIFT                                                      0x1
16254 #define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN__SHIFT                                                     0x2
16255 #define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY__SHIFT                                                          0x1e
16256 #define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY__SHIFT                                                             0x1f
16257 #define SPI_COMPUTE_WF_CTX_SAVE__INITIATE_MASK                                                                0x00000001L
16258 #define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN_MASK                                                        0x00000002L
16259 #define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN_MASK                                                       0x00000004L
16260 #define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY_MASK                                                            0x40000000L
16261 #define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY_MASK                                                               0x80000000L
16262 //SPI_ARB_CNTL_0
16263 #define SPI_ARB_CNTL_0__EXP_ARB_COL_WT__SHIFT                                                                 0x0
16264 #define SPI_ARB_CNTL_0__EXP_ARB_POS_WT__SHIFT                                                                 0x4
16265 #define SPI_ARB_CNTL_0__EXP_ARB_GDS_WT__SHIFT                                                                 0x8
16266 #define SPI_ARB_CNTL_0__EXP_ARB_COL_WT_MASK                                                                   0x0000000FL
16267 #define SPI_ARB_CNTL_0__EXP_ARB_POS_WT_MASK                                                                   0x000000F0L
16268 #define SPI_ARB_CNTL_0__EXP_ARB_GDS_WT_MASK                                                                   0x00000F00L
16269 
16270 
16271 // addressBlock: xcd0_gc_cpphqddec
16272 //CP_HQD_GFX_CONTROL
16273 #define CP_HQD_GFX_CONTROL__MESSAGE__SHIFT                                                                    0x0
16274 #define CP_HQD_GFX_CONTROL__MISC__SHIFT                                                                       0x4
16275 #define CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT                                                          0xf
16276 #define CP_HQD_GFX_CONTROL__MESSAGE_MASK                                                                      0x0000000FL
16277 #define CP_HQD_GFX_CONTROL__MISC_MASK                                                                         0x00007FF0L
16278 #define CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN_MASK                                                            0x00008000L
16279 //CP_HQD_GFX_STATUS
16280 #define CP_HQD_GFX_STATUS__STATUS__SHIFT                                                                      0x0
16281 #define CP_HQD_GFX_STATUS__STATUS_MASK                                                                        0x0000FFFFL
16282 //CP_HPD_ROQ_OFFSETS
16283 #define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT                                                                  0x0
16284 #define CP_HPD_ROQ_OFFSETS__PQ_OFFSET__SHIFT                                                                  0x8
16285 #define CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT                                                                  0x10
16286 #define CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK                                                                    0x00000007L
16287 #define CP_HPD_ROQ_OFFSETS__PQ_OFFSET_MASK                                                                    0x00003F00L
16288 #define CP_HPD_ROQ_OFFSETS__IB_OFFSET_MASK                                                                    0x003F0000L
16289 //CP_HPD_STATUS0
16290 #define CP_HPD_STATUS0__QUEUE_STATE__SHIFT                                                                    0x0
16291 #define CP_HPD_STATUS0__MAPPED_QUEUE__SHIFT                                                                   0x5
16292 #define CP_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT                                                                0x8
16293 #define CP_HPD_STATUS0__FETCHING_MQD__SHIFT                                                                   0x10
16294 #define CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB__SHIFT                                                           0x11
16295 #define CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ__SHIFT                                                             0x12
16296 #define CP_HPD_STATUS0__FORCE_QUEUE_STATE__SHIFT                                                              0x14
16297 #define CP_HPD_STATUS0__ENABLE_OFFLOAD_CHECK__SHIFT                                                           0x1d
16298 #define CP_HPD_STATUS0__FORCE_QUEUE__SHIFT                                                                    0x1f
16299 #define CP_HPD_STATUS0__QUEUE_STATE_MASK                                                                      0x0000001FL
16300 #define CP_HPD_STATUS0__MAPPED_QUEUE_MASK                                                                     0x000000E0L
16301 #define CP_HPD_STATUS0__QUEUE_AVAILABLE_MASK                                                                  0x0000FF00L
16302 #define CP_HPD_STATUS0__FETCHING_MQD_MASK                                                                     0x00010000L
16303 #define CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB_MASK                                                             0x00020000L
16304 #define CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ_MASK                                                               0x00040000L
16305 #define CP_HPD_STATUS0__FORCE_QUEUE_STATE_MASK                                                                0x01F00000L
16306 #define CP_HPD_STATUS0__ENABLE_OFFLOAD_CHECK_MASK                                                             0x20000000L
16307 #define CP_HPD_STATUS0__FORCE_QUEUE_MASK                                                                      0x80000000L
16308 //CP_HPD_UTCL1_CNTL
16309 #define CP_HPD_UTCL1_CNTL__SELECT__SHIFT                                                                      0x0
16310 #define CP_HPD_UTCL1_CNTL__SELECT_MASK                                                                        0x0000000FL
16311 //CP_HPD_UTCL1_ERROR
16312 #define CP_HPD_UTCL1_ERROR__ADDR_HI__SHIFT                                                                    0x0
16313 #define CP_HPD_UTCL1_ERROR__TYPE__SHIFT                                                                       0x10
16314 #define CP_HPD_UTCL1_ERROR__VMID__SHIFT                                                                       0x14
16315 #define CP_HPD_UTCL1_ERROR__ADDR_HI_MASK                                                                      0x0000FFFFL
16316 #define CP_HPD_UTCL1_ERROR__TYPE_MASK                                                                         0x00010000L
16317 #define CP_HPD_UTCL1_ERROR__VMID_MASK                                                                         0x00F00000L
16318 //CP_HPD_UTCL1_ERROR_ADDR
16319 #define CP_HPD_UTCL1_ERROR_ADDR__ADDR__SHIFT                                                                  0xc
16320 #define CP_HPD_UTCL1_ERROR_ADDR__ADDR_MASK                                                                    0xFFFFF000L
16321 //CP_MQD_BASE_ADDR
16322 #define CP_MQD_BASE_ADDR__BASE_ADDR__SHIFT                                                                    0x2
16323 #define CP_MQD_BASE_ADDR__BASE_ADDR_MASK                                                                      0xFFFFFFFCL
16324 //CP_MQD_BASE_ADDR_HI
16325 #define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT                                                              0x0
16326 #define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK                                                                0x0000FFFFL
16327 //CP_HQD_ACTIVE
16328 #define CP_HQD_ACTIVE__ACTIVE__SHIFT                                                                          0x0
16329 #define CP_HQD_ACTIVE__BUSY_GATE__SHIFT                                                                       0x1
16330 #define CP_HQD_ACTIVE__ACTIVE_MASK                                                                            0x00000001L
16331 #define CP_HQD_ACTIVE__BUSY_GATE_MASK                                                                         0x00000002L
16332 //CP_HQD_VMID
16333 #define CP_HQD_VMID__VMID__SHIFT                                                                              0x0
16334 #define CP_HQD_VMID__IB_VMID__SHIFT                                                                           0x8
16335 #define CP_HQD_VMID__VQID__SHIFT                                                                              0x10
16336 #define CP_HQD_VMID__VMID_MASK                                                                                0x0000000FL
16337 #define CP_HQD_VMID__IB_VMID_MASK                                                                             0x00000F00L
16338 #define CP_HQD_VMID__VQID_MASK                                                                                0x03FF0000L
16339 //CP_HQD_PERSISTENT_STATE
16340 #define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ__SHIFT                                                           0x0
16341 #define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT                                                          0x8
16342 #define CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN__SHIFT                                                     0x15
16343 #define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN__SHIFT                                                      0x16
16344 #define CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN__SHIFT                                                      0x17
16345 #define CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN__SHIFT                                                     0x18
16346 #define CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN__SHIFT                                                      0x19
16347 #define CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN__SHIFT                                                     0x1a
16348 #define CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN__SHIFT                                                  0x1b
16349 #define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE__SHIFT                                                        0x1c
16350 #define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES__SHIFT                                                        0x1d
16351 #define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT                                                          0x1e
16352 #define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE__SHIFT                                                           0x1f
16353 #define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK                                                             0x00000001L
16354 #define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE_MASK                                                            0x0003FF00L
16355 #define CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN_MASK                                                       0x00200000L
16356 #define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN_MASK                                                        0x00400000L
16357 #define CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN_MASK                                                        0x00800000L
16358 #define CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN_MASK                                                       0x01000000L
16359 #define CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN_MASK                                                        0x02000000L
16360 #define CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN_MASK                                                       0x04000000L
16361 #define CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN_MASK                                                    0x08000000L
16362 #define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE_MASK                                                          0x10000000L
16363 #define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES_MASK                                                          0x20000000L
16364 #define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE_MASK                                                            0x40000000L
16365 #define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE_MASK                                                             0x80000000L
16366 //CP_HQD_PIPE_PRIORITY
16367 #define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY__SHIFT                                                            0x0
16368 #define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY_MASK                                                              0x00000003L
16369 //CP_HQD_QUEUE_PRIORITY
16370 #define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT                                                          0x0
16371 #define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK                                                            0x0000000FL
16372 //CP_HQD_QUANTUM
16373 #define CP_HQD_QUANTUM__QUANTUM_EN__SHIFT                                                                     0x0
16374 #define CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT                                                                  0x4
16375 #define CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT                                                               0x8
16376 #define CP_HQD_QUANTUM__QUANTUM_ACTIVE__SHIFT                                                                 0x1f
16377 #define CP_HQD_QUANTUM__QUANTUM_EN_MASK                                                                       0x00000001L
16378 #define CP_HQD_QUANTUM__QUANTUM_SCALE_MASK                                                                    0x00000010L
16379 #define CP_HQD_QUANTUM__QUANTUM_DURATION_MASK                                                                 0x00003F00L
16380 #define CP_HQD_QUANTUM__QUANTUM_ACTIVE_MASK                                                                   0x80000000L
16381 //CP_HQD_PQ_BASE
16382 #define CP_HQD_PQ_BASE__ADDR__SHIFT                                                                           0x0
16383 #define CP_HQD_PQ_BASE__ADDR_MASK                                                                             0xFFFFFFFFL
16384 //CP_HQD_PQ_BASE_HI
16385 #define CP_HQD_PQ_BASE_HI__ADDR_HI__SHIFT                                                                     0x0
16386 #define CP_HQD_PQ_BASE_HI__ADDR_HI_MASK                                                                       0x000000FFL
16387 //CP_HQD_PQ_RPTR
16388 #define CP_HQD_PQ_RPTR__CONSUMED_OFFSET__SHIFT                                                                0x0
16389 #define CP_HQD_PQ_RPTR__CONSUMED_OFFSET_MASK                                                                  0xFFFFFFFFL
16390 //CP_HQD_PQ_RPTR_REPORT_ADDR
16391 #define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR__SHIFT                                                   0x2
16392 #define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR_MASK                                                     0xFFFFFFFCL
16393 //CP_HQD_PQ_RPTR_REPORT_ADDR_HI
16394 #define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI__SHIFT                                             0x0
16395 #define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI_MASK                                               0x0000FFFFL
16396 //CP_HQD_PQ_WPTR_POLL_ADDR
16397 #define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR__SHIFT                                                            0x3
16398 #define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR_MASK                                                              0xFFFFFFF8L
16399 //CP_HQD_PQ_WPTR_POLL_ADDR_HI
16400 #define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI__SHIFT                                                      0x0
16401 #define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK                                                        0x0000FFFFL
16402 //CP_HQD_PQ_DOORBELL_CONTROL
16403 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT                                                      0x0
16404 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT                                                  0x1
16405 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT                                                    0x2
16406 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE__SHIFT                                                    0x1c
16407 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT__SHIFT                                                  0x1d
16408 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN__SHIFT                                                        0x1e
16409 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT                                                       0x1f
16410 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE_MASK                                                        0x00000001L
16411 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK                                                    0x00000002L
16412 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK                                                      0x0FFFFFFCL
16413 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK                                                      0x10000000L
16414 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT_MASK                                                    0x20000000L
16415 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK                                                          0x40000000L
16416 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK                                                         0x80000000L
16417 //CP_HQD_PQ_CONTROL
16418 #define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT                                                                  0x0
16419 #define CP_HQD_PQ_CONTROL__WPTR_CARRY__SHIFT                                                                  0x6
16420 #define CP_HQD_PQ_CONTROL__RPTR_CARRY__SHIFT                                                                  0x7
16421 #define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT                                                             0x8
16422 #define CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT                                                               0xe
16423 #define CP_HQD_PQ_CONTROL__PQ_EMPTY__SHIFT                                                                    0xf
16424 #define CP_HQD_PQ_CONTROL__WPP_CLAMP_EN__SHIFT                                                                0x10
16425 #define CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT                                                                 0x11
16426 #define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE__SHIFT                                                              0x14
16427 #define CP_HQD_PQ_CONTROL__TMZ__SHIFT                                                                         0x16
16428 #define CP_HQD_PQ_CONTROL__EXE_DISABLE__SHIFT                                                                 0x17
16429 #define CP_HQD_PQ_CONTROL__CACHE_POLICY__SHIFT                                                                0x18
16430 #define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT                                                             0x19
16431 #define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR__SHIFT                                                              0x1b
16432 #define CP_HQD_PQ_CONTROL__UNORD_DISPATCH__SHIFT                                                              0x1c
16433 #define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP__SHIFT                                                              0x1d
16434 #define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT                                                                  0x1e
16435 #define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT                                                                   0x1f
16436 #define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK                                                                    0x0000003FL
16437 #define CP_HQD_PQ_CONTROL__WPTR_CARRY_MASK                                                                    0x00000040L
16438 #define CP_HQD_PQ_CONTROL__RPTR_CARRY_MASK                                                                    0x00000080L
16439 #define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK                                                               0x00003F00L
16440 #define CP_HQD_PQ_CONTROL__QUEUE_FULL_EN_MASK                                                                 0x00004000L
16441 #define CP_HQD_PQ_CONTROL__PQ_EMPTY_MASK                                                                      0x00008000L
16442 #define CP_HQD_PQ_CONTROL__WPP_CLAMP_EN_MASK                                                                  0x00010000L
16443 #define CP_HQD_PQ_CONTROL__ENDIAN_SWAP_MASK                                                                   0x00060000L
16444 #define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE_MASK                                                                0x00300000L
16445 #define CP_HQD_PQ_CONTROL__TMZ_MASK                                                                           0x00400000L
16446 #define CP_HQD_PQ_CONTROL__EXE_DISABLE_MASK                                                                   0x00800000L
16447 #define CP_HQD_PQ_CONTROL__CACHE_POLICY_MASK                                                                  0x01000000L
16448 #define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK                                                               0x06000000L
16449 #define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK                                                                0x08000000L
16450 #define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK                                                                0x10000000L
16451 #define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK                                                                0x20000000L
16452 #define CP_HQD_PQ_CONTROL__PRIV_STATE_MASK                                                                    0x40000000L
16453 #define CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK                                                                     0x80000000L
16454 //CP_HQD_IB_BASE_ADDR
16455 #define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR__SHIFT                                                              0x2
16456 #define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR_MASK                                                                0xFFFFFFFCL
16457 //CP_HQD_IB_BASE_ADDR_HI
16458 #define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI__SHIFT                                                        0x0
16459 #define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI_MASK                                                          0x0000FFFFL
16460 //CP_HQD_IB_RPTR
16461 #define CP_HQD_IB_RPTR__CONSUMED_OFFSET__SHIFT                                                                0x0
16462 #define CP_HQD_IB_RPTR__CONSUMED_OFFSET_MASK                                                                  0x000FFFFFL
16463 //CP_HQD_IB_CONTROL
16464 #define CP_HQD_IB_CONTROL__IB_SIZE__SHIFT                                                                     0x0
16465 #define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT                                                           0x14
16466 #define CP_HQD_IB_CONTROL__IB_EXE_DISABLE__SHIFT                                                              0x17
16467 #define CP_HQD_IB_CONTROL__IB_CACHE_POLICY__SHIFT                                                             0x18
16468 #define CP_HQD_IB_CONTROL__IB_PRIV_STATE__SHIFT                                                               0x1e
16469 #define CP_HQD_IB_CONTROL__PROCESSING_IB__SHIFT                                                               0x1f
16470 #define CP_HQD_IB_CONTROL__IB_SIZE_MASK                                                                       0x000FFFFFL
16471 #define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE_MASK                                                             0x00300000L
16472 #define CP_HQD_IB_CONTROL__IB_EXE_DISABLE_MASK                                                                0x00800000L
16473 #define CP_HQD_IB_CONTROL__IB_CACHE_POLICY_MASK                                                               0x01000000L
16474 #define CP_HQD_IB_CONTROL__IB_PRIV_STATE_MASK                                                                 0x40000000L
16475 #define CP_HQD_IB_CONTROL__PROCESSING_IB_MASK                                                                 0x80000000L
16476 //CP_HQD_IQ_TIMER
16477 #define CP_HQD_IQ_TIMER__WAIT_TIME__SHIFT                                                                     0x0
16478 #define CP_HQD_IQ_TIMER__RETRY_TYPE__SHIFT                                                                    0x8
16479 #define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE__SHIFT                                                              0xb
16480 #define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT                                                                0xc
16481 #define CP_HQD_IQ_TIMER__CLOCK_COUNT__SHIFT                                                                   0xe
16482 #define CP_HQD_IQ_TIMER__INTERRUPT_SIZE__SHIFT                                                                0x10
16483 #define CP_HQD_IQ_TIMER__QUANTUM_TIMER__SHIFT                                                                 0x16
16484 #define CP_HQD_IQ_TIMER__EXE_DISABLE__SHIFT                                                                   0x17
16485 #define CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT                                                                  0x18
16486 #define CP_HQD_IQ_TIMER__QUEUE_TYPE__SHIFT                                                                    0x19
16487 #define CP_HQD_IQ_TIMER__REARM_TIMER__SHIFT                                                                   0x1c
16488 #define CP_HQD_IQ_TIMER__PROCESS_IQ_EN__SHIFT                                                                 0x1d
16489 #define CP_HQD_IQ_TIMER__PROCESSING_IQ__SHIFT                                                                 0x1e
16490 #define CP_HQD_IQ_TIMER__ACTIVE__SHIFT                                                                        0x1f
16491 #define CP_HQD_IQ_TIMER__WAIT_TIME_MASK                                                                       0x000000FFL
16492 #define CP_HQD_IQ_TIMER__RETRY_TYPE_MASK                                                                      0x00000700L
16493 #define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE_MASK                                                                0x00000800L
16494 #define CP_HQD_IQ_TIMER__INTERRUPT_TYPE_MASK                                                                  0x00003000L
16495 #define CP_HQD_IQ_TIMER__CLOCK_COUNT_MASK                                                                     0x0000C000L
16496 #define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK                                                                  0x003F0000L
16497 #define CP_HQD_IQ_TIMER__QUANTUM_TIMER_MASK                                                                   0x00400000L
16498 #define CP_HQD_IQ_TIMER__EXE_DISABLE_MASK                                                                     0x00800000L
16499 #define CP_HQD_IQ_TIMER__CACHE_POLICY_MASK                                                                    0x01000000L
16500 #define CP_HQD_IQ_TIMER__QUEUE_TYPE_MASK                                                                      0x02000000L
16501 #define CP_HQD_IQ_TIMER__REARM_TIMER_MASK                                                                     0x10000000L
16502 #define CP_HQD_IQ_TIMER__PROCESS_IQ_EN_MASK                                                                   0x20000000L
16503 #define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK                                                                   0x40000000L
16504 #define CP_HQD_IQ_TIMER__ACTIVE_MASK                                                                          0x80000000L
16505 //CP_HQD_IQ_RPTR
16506 #define CP_HQD_IQ_RPTR__OFFSET__SHIFT                                                                         0x0
16507 #define CP_HQD_IQ_RPTR__OFFSET_MASK                                                                           0x0000003FL
16508 //CP_HQD_DEQUEUE_REQUEST
16509 #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT                                                            0x0
16510 #define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT                                                            0x4
16511 #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT__SHIFT                                                            0x8
16512 #define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN__SHIFT                                                         0x9
16513 #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT                                                         0xa
16514 #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK                                                              0x00000007L
16515 #define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK                                                              0x00000010L
16516 #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT_MASK                                                              0x00000100L
16517 #define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN_MASK                                                           0x00000200L
16518 #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN_MASK                                                           0x00000400L
16519 //CP_HQD_DMA_OFFLOAD
16520 #define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD__SHIFT                                                                0x0
16521 #define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_MASK                                                                  0x00000001L
16522 //CP_HQD_OFFLOAD
16523 #define CP_HQD_OFFLOAD__DMA_OFFLOAD__SHIFT                                                                    0x0
16524 #define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN__SHIFT                                                                 0x1
16525 #define CP_HQD_OFFLOAD__AQL_OFFLOAD__SHIFT                                                                    0x2
16526 #define CP_HQD_OFFLOAD__AQL_OFFLOAD_EN__SHIFT                                                                 0x3
16527 #define CP_HQD_OFFLOAD__EOP_OFFLOAD__SHIFT                                                                    0x4
16528 #define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN__SHIFT                                                                 0x5
16529 #define CP_HQD_OFFLOAD__DMA_OFFLOAD_MASK                                                                      0x00000001L
16530 #define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN_MASK                                                                   0x00000002L
16531 #define CP_HQD_OFFLOAD__AQL_OFFLOAD_MASK                                                                      0x00000004L
16532 #define CP_HQD_OFFLOAD__AQL_OFFLOAD_EN_MASK                                                                   0x00000008L
16533 #define CP_HQD_OFFLOAD__EOP_OFFLOAD_MASK                                                                      0x00000010L
16534 #define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN_MASK                                                                   0x00000020L
16535 //CP_HQD_SEMA_CMD
16536 #define CP_HQD_SEMA_CMD__RETRY__SHIFT                                                                         0x0
16537 #define CP_HQD_SEMA_CMD__RESULT__SHIFT                                                                        0x1
16538 #define CP_HQD_SEMA_CMD__RETRY_MASK                                                                           0x00000001L
16539 #define CP_HQD_SEMA_CMD__RESULT_MASK                                                                          0x00000006L
16540 //CP_HQD_MSG_TYPE
16541 #define CP_HQD_MSG_TYPE__ACTION__SHIFT                                                                        0x0
16542 #define CP_HQD_MSG_TYPE__SAVE_STATE__SHIFT                                                                    0x4
16543 #define CP_HQD_MSG_TYPE__ACTION_MASK                                                                          0x00000007L
16544 #define CP_HQD_MSG_TYPE__SAVE_STATE_MASK                                                                      0x00000070L
16545 //CP_HQD_ATOMIC0_PREOP_LO
16546 #define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO__SHIFT                                                      0x0
16547 #define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO_MASK                                                        0xFFFFFFFFL
16548 //CP_HQD_ATOMIC0_PREOP_HI
16549 #define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI__SHIFT                                                      0x0
16550 #define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI_MASK                                                        0xFFFFFFFFL
16551 //CP_HQD_ATOMIC1_PREOP_LO
16552 #define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO__SHIFT                                                      0x0
16553 #define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO_MASK                                                        0xFFFFFFFFL
16554 //CP_HQD_ATOMIC1_PREOP_HI
16555 #define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI__SHIFT                                                      0x0
16556 #define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI_MASK                                                        0xFFFFFFFFL
16557 //CP_HQD_HQ_SCHEDULER0
16558 #define CP_HQD_HQ_SCHEDULER0__SCHEDULER__SHIFT                                                                0x0
16559 #define CP_HQD_HQ_SCHEDULER0__SCHEDULER_MASK                                                                  0xFFFFFFFFL
16560 //CP_HQD_HQ_STATUS0
16561 #define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS__SHIFT                                                              0x0
16562 #define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT__SHIFT                                                           0x2
16563 #define CP_HQD_HQ_STATUS0__RSV_6_4__SHIFT                                                                     0x4
16564 #define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT__SHIFT                                                            0x7
16565 #define CP_HQD_HQ_STATUS0__TCL2_DIRTY__SHIFT                                                                  0x8
16566 #define CP_HQD_HQ_STATUS0__PG_ACTIVATED__SHIFT                                                                0x9
16567 #define CP_HQD_HQ_STATUS0__RSVR_29_10__SHIFT                                                                  0xa
16568 #define CP_HQD_HQ_STATUS0__QUEUE_IDLE__SHIFT                                                                  0x1e
16569 #define CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN__SHIFT                                                           0x1f
16570 #define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS_MASK                                                                0x00000003L
16571 #define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT_MASK                                                             0x0000000CL
16572 #define CP_HQD_HQ_STATUS0__RSV_6_4_MASK                                                                       0x00000070L
16573 #define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT_MASK                                                              0x00000080L
16574 #define CP_HQD_HQ_STATUS0__TCL2_DIRTY_MASK                                                                    0x00000100L
16575 #define CP_HQD_HQ_STATUS0__PG_ACTIVATED_MASK                                                                  0x00000200L
16576 #define CP_HQD_HQ_STATUS0__RSVR_29_10_MASK                                                                    0x3FFFFC00L
16577 #define CP_HQD_HQ_STATUS0__QUEUE_IDLE_MASK                                                                    0x40000000L
16578 #define CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN_MASK                                                             0x80000000L
16579 //CP_HQD_HQ_CONTROL0
16580 #define CP_HQD_HQ_CONTROL0__CONTROL__SHIFT                                                                    0x0
16581 #define CP_HQD_HQ_CONTROL0__CONTROL_MASK                                                                      0xFFFFFFFFL
16582 //CP_HQD_HQ_SCHEDULER1
16583 #define CP_HQD_HQ_SCHEDULER1__SCHEDULER__SHIFT                                                                0x0
16584 #define CP_HQD_HQ_SCHEDULER1__SCHEDULER_MASK                                                                  0xFFFFFFFFL
16585 //CP_MQD_CONTROL
16586 #define CP_MQD_CONTROL__VMID__SHIFT                                                                           0x0
16587 #define CP_MQD_CONTROL__PRIV_STATE__SHIFT                                                                     0x8
16588 #define CP_MQD_CONTROL__PROCESSING_MQD__SHIFT                                                                 0xc
16589 #define CP_MQD_CONTROL__PROCESSING_MQD_EN__SHIFT                                                              0xd
16590 #define CP_MQD_CONTROL__EXE_DISABLE__SHIFT                                                                    0x17
16591 #define CP_MQD_CONTROL__CACHE_POLICY__SHIFT                                                                   0x18
16592 #define CP_MQD_CONTROL__VMID_MASK                                                                             0x0000000FL
16593 #define CP_MQD_CONTROL__PRIV_STATE_MASK                                                                       0x00000100L
16594 #define CP_MQD_CONTROL__PROCESSING_MQD_MASK                                                                   0x00001000L
16595 #define CP_MQD_CONTROL__PROCESSING_MQD_EN_MASK                                                                0x00002000L
16596 #define CP_MQD_CONTROL__EXE_DISABLE_MASK                                                                      0x00800000L
16597 #define CP_MQD_CONTROL__CACHE_POLICY_MASK                                                                     0x01000000L
16598 //CP_HQD_HQ_STATUS1
16599 #define CP_HQD_HQ_STATUS1__STATUS__SHIFT                                                                      0x0
16600 #define CP_HQD_HQ_STATUS1__STATUS_MASK                                                                        0xFFFFFFFFL
16601 //CP_HQD_HQ_CONTROL1
16602 #define CP_HQD_HQ_CONTROL1__CONTROL__SHIFT                                                                    0x0
16603 #define CP_HQD_HQ_CONTROL1__CONTROL_MASK                                                                      0xFFFFFFFFL
16604 //CP_HQD_EOP_BASE_ADDR
16605 #define CP_HQD_EOP_BASE_ADDR__BASE_ADDR__SHIFT                                                                0x0
16606 #define CP_HQD_EOP_BASE_ADDR__BASE_ADDR_MASK                                                                  0xFFFFFFFFL
16607 //CP_HQD_EOP_BASE_ADDR_HI
16608 #define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT                                                          0x0
16609 #define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI_MASK                                                            0x000000FFL
16610 //CP_HQD_EOP_CONTROL
16611 #define CP_HQD_EOP_CONTROL__EOP_SIZE__SHIFT                                                                   0x0
16612 #define CP_HQD_EOP_CONTROL__PROCESSING_EOP__SHIFT                                                             0x8
16613 #define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN__SHIFT                                                             0xc
16614 #define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB__SHIFT                                                           0xd
16615 #define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN__SHIFT                                                           0xe
16616 #define CP_HQD_EOP_CONTROL__HALT_FETCHER__SHIFT                                                               0x15
16617 #define CP_HQD_EOP_CONTROL__HALT_FETCHER_EN__SHIFT                                                            0x16
16618 #define CP_HQD_EOP_CONTROL__EXE_DISABLE__SHIFT                                                                0x17
16619 #define CP_HQD_EOP_CONTROL__CACHE_POLICY__SHIFT                                                               0x18
16620 #define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT__SHIFT                                                             0x1d
16621 #define CP_HQD_EOP_CONTROL__PEND_SIG_SEM__SHIFT                                                               0x1f
16622 #define CP_HQD_EOP_CONTROL__EOP_SIZE_MASK                                                                     0x0000003FL
16623 #define CP_HQD_EOP_CONTROL__PROCESSING_EOP_MASK                                                               0x00000100L
16624 #define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN_MASK                                                               0x00001000L
16625 #define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB_MASK                                                             0x00002000L
16626 #define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN_MASK                                                             0x00004000L
16627 #define CP_HQD_EOP_CONTROL__HALT_FETCHER_MASK                                                                 0x00200000L
16628 #define CP_HQD_EOP_CONTROL__HALT_FETCHER_EN_MASK                                                              0x00400000L
16629 #define CP_HQD_EOP_CONTROL__EXE_DISABLE_MASK                                                                  0x00800000L
16630 #define CP_HQD_EOP_CONTROL__CACHE_POLICY_MASK                                                                 0x01000000L
16631 #define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT_MASK                                                               0x60000000L
16632 #define CP_HQD_EOP_CONTROL__PEND_SIG_SEM_MASK                                                                 0x80000000L
16633 //CP_HQD_EOP_RPTR
16634 #define CP_HQD_EOP_RPTR__RPTR__SHIFT                                                                          0x0
16635 #define CP_HQD_EOP_RPTR__RESET_FETCHER__SHIFT                                                                 0x1c
16636 #define CP_HQD_EOP_RPTR__DEQUEUE_PEND__SHIFT                                                                  0x1d
16637 #define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR__SHIFT                                                             0x1e
16638 #define CP_HQD_EOP_RPTR__INIT_FETCHER__SHIFT                                                                  0x1f
16639 #define CP_HQD_EOP_RPTR__RPTR_MASK                                                                            0x00001FFFL
16640 #define CP_HQD_EOP_RPTR__RESET_FETCHER_MASK                                                                   0x10000000L
16641 #define CP_HQD_EOP_RPTR__DEQUEUE_PEND_MASK                                                                    0x20000000L
16642 #define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR_MASK                                                               0x40000000L
16643 #define CP_HQD_EOP_RPTR__INIT_FETCHER_MASK                                                                    0x80000000L
16644 //CP_HQD_EOP_WPTR
16645 #define CP_HQD_EOP_WPTR__WPTR__SHIFT                                                                          0x0
16646 #define CP_HQD_EOP_WPTR__EOP_EMPTY__SHIFT                                                                     0xf
16647 #define CP_HQD_EOP_WPTR__EOP_AVAIL__SHIFT                                                                     0x10
16648 #define CP_HQD_EOP_WPTR__WPTR_MASK                                                                            0x00001FFFL
16649 #define CP_HQD_EOP_WPTR__EOP_EMPTY_MASK                                                                       0x00008000L
16650 #define CP_HQD_EOP_WPTR__EOP_AVAIL_MASK                                                                       0x1FFF0000L
16651 //CP_HQD_EOP_EVENTS
16652 #define CP_HQD_EOP_EVENTS__EVENT_COUNT__SHIFT                                                                 0x0
16653 #define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND__SHIFT                                                       0x10
16654 #define CP_HQD_EOP_EVENTS__EVENT_COUNT_MASK                                                                   0x00000FFFL
16655 #define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND_MASK                                                         0x00010000L
16656 //CP_HQD_CTX_SAVE_BASE_ADDR_LO
16657 #define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR__SHIFT                                                             0xc
16658 #define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR_MASK                                                               0xFFFFF000L
16659 //CP_HQD_CTX_SAVE_BASE_ADDR_HI
16660 #define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI__SHIFT                                                          0x0
16661 #define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI_MASK                                                            0x0000FFFFL
16662 //CP_HQD_CTX_SAVE_CONTROL
16663 #define CP_HQD_CTX_SAVE_CONTROL__POLICY__SHIFT                                                                0x3
16664 #define CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE__SHIFT                                                           0x17
16665 #define CP_HQD_CTX_SAVE_CONTROL__POLICY_MASK                                                                  0x00000008L
16666 #define CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE_MASK                                                             0x00800000L
16667 //CP_HQD_CNTL_STACK_OFFSET
16668 #define CP_HQD_CNTL_STACK_OFFSET__OFFSET__SHIFT                                                               0x2
16669 #define CP_HQD_CNTL_STACK_OFFSET__OFFSET_MASK                                                                 0x0000FFFCL
16670 //CP_HQD_CNTL_STACK_SIZE
16671 #define CP_HQD_CNTL_STACK_SIZE__SIZE__SHIFT                                                                   0xc
16672 #define CP_HQD_CNTL_STACK_SIZE__SIZE_MASK                                                                     0x0000F000L
16673 //CP_HQD_WG_STATE_OFFSET
16674 #define CP_HQD_WG_STATE_OFFSET__OFFSET__SHIFT                                                                 0x2
16675 #define CP_HQD_WG_STATE_OFFSET__OFFSET_MASK                                                                   0x07FFFFFCL
16676 //CP_HQD_CTX_SAVE_SIZE
16677 #define CP_HQD_CTX_SAVE_SIZE__SIZE__SHIFT                                                                     0xc
16678 #define CP_HQD_CTX_SAVE_SIZE__SIZE_MASK                                                                       0x07FFF000L
16679 //CP_HQD_GDS_RESOURCE_STATE
16680 #define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED__SHIFT                                                         0x0
16681 #define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED__SHIFT                                                         0x1
16682 #define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE__SHIFT                                                            0x4
16683 #define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR__SHIFT                                                            0xc
16684 #define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED_MASK                                                           0x00000001L
16685 #define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED_MASK                                                           0x00000002L
16686 #define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE_MASK                                                              0x000003F0L
16687 #define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR_MASK                                                              0x0003F000L
16688 //CP_HQD_ERROR
16689 #define CP_HQD_ERROR__EDC_ERROR_ID__SHIFT                                                                     0x0
16690 #define CP_HQD_ERROR__SUA_ERROR__SHIFT                                                                        0x4
16691 #define CP_HQD_ERROR__AQL_ERROR__SHIFT                                                                        0x5
16692 #define CP_HQD_ERROR__PQ_UTCL1_ERROR__SHIFT                                                                   0x8
16693 #define CP_HQD_ERROR__IB_UTCL1_ERROR__SHIFT                                                                   0x9
16694 #define CP_HQD_ERROR__EOP_UTCL1_ERROR__SHIFT                                                                  0xa
16695 #define CP_HQD_ERROR__IQ_UTCL1_ERROR__SHIFT                                                                   0xb
16696 #define CP_HQD_ERROR__RRPT_UTCL1_ERROR__SHIFT                                                                 0xc
16697 #define CP_HQD_ERROR__WPP_UTCL1_ERROR__SHIFT                                                                  0xd
16698 #define CP_HQD_ERROR__SEM_UTCL1_ERROR__SHIFT                                                                  0xe
16699 #define CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT                                                              0xf
16700 #define CP_HQD_ERROR__DMA_DST_UTCL1_ERROR__SHIFT                                                              0x10
16701 #define CP_HQD_ERROR__SR_UTCL1_ERROR__SHIFT                                                                   0x11
16702 #define CP_HQD_ERROR__QU_UTCL1_ERROR__SHIFT                                                                   0x12
16703 #define CP_HQD_ERROR__TC_UTCL1_ERROR__SHIFT                                                                   0x13
16704 #define CP_HQD_ERROR__EDC_ERROR_ID_MASK                                                                       0x0000000FL
16705 #define CP_HQD_ERROR__SUA_ERROR_MASK                                                                          0x00000010L
16706 #define CP_HQD_ERROR__AQL_ERROR_MASK                                                                          0x00000020L
16707 #define CP_HQD_ERROR__PQ_UTCL1_ERROR_MASK                                                                     0x00000100L
16708 #define CP_HQD_ERROR__IB_UTCL1_ERROR_MASK                                                                     0x00000200L
16709 #define CP_HQD_ERROR__EOP_UTCL1_ERROR_MASK                                                                    0x00000400L
16710 #define CP_HQD_ERROR__IQ_UTCL1_ERROR_MASK                                                                     0x00000800L
16711 #define CP_HQD_ERROR__RRPT_UTCL1_ERROR_MASK                                                                   0x00001000L
16712 #define CP_HQD_ERROR__WPP_UTCL1_ERROR_MASK                                                                    0x00002000L
16713 #define CP_HQD_ERROR__SEM_UTCL1_ERROR_MASK                                                                    0x00004000L
16714 #define CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR_MASK                                                                0x00008000L
16715 #define CP_HQD_ERROR__DMA_DST_UTCL1_ERROR_MASK                                                                0x00010000L
16716 #define CP_HQD_ERROR__SR_UTCL1_ERROR_MASK                                                                     0x00020000L
16717 #define CP_HQD_ERROR__QU_UTCL1_ERROR_MASK                                                                     0x00040000L
16718 #define CP_HQD_ERROR__TC_UTCL1_ERROR_MASK                                                                     0x00080000L
16719 //CP_HQD_EOP_WPTR_MEM
16720 #define CP_HQD_EOP_WPTR_MEM__WPTR__SHIFT                                                                      0x0
16721 #define CP_HQD_EOP_WPTR_MEM__WPTR_MASK                                                                        0x00001FFFL
16722 //CP_HQD_AQL_CONTROL
16723 #define CP_HQD_AQL_CONTROL__CONTROL0__SHIFT                                                                   0x0
16724 #define CP_HQD_AQL_CONTROL__CONTROL0_EN__SHIFT                                                                0xf
16725 #define CP_HQD_AQL_CONTROL__CONTROL1__SHIFT                                                                   0x10
16726 #define CP_HQD_AQL_CONTROL__CONTROL1_EN__SHIFT                                                                0x1f
16727 #define CP_HQD_AQL_CONTROL__CONTROL0_MASK                                                                     0x00007FFFL
16728 #define CP_HQD_AQL_CONTROL__CONTROL0_EN_MASK                                                                  0x00008000L
16729 #define CP_HQD_AQL_CONTROL__CONTROL1_MASK                                                                     0x7FFF0000L
16730 #define CP_HQD_AQL_CONTROL__CONTROL1_EN_MASK                                                                  0x80000000L
16731 //CP_HQD_PQ_WPTR_LO
16732 #define CP_HQD_PQ_WPTR_LO__OFFSET__SHIFT                                                                      0x0
16733 #define CP_HQD_PQ_WPTR_LO__OFFSET_MASK                                                                        0xFFFFFFFFL
16734 //CP_HQD_PQ_WPTR_HI
16735 #define CP_HQD_PQ_WPTR_HI__DATA__SHIFT                                                                        0x0
16736 #define CP_HQD_PQ_WPTR_HI__DATA_MASK                                                                          0xFFFFFFFFL
16737 //CP_HQD_AQL_CONTROL_1
16738 #define CP_HQD_AQL_CONTROL_1__RESERVED__SHIFT                                                                 0x0
16739 #define CP_HQD_AQL_CONTROL_1__RESERVED_MASK                                                                   0xFFFFFFFFL
16740 //CP_HQD_AQL_DISPATCH_ID
16741 #define CP_HQD_AQL_DISPATCH_ID__CONSUMED_OFFSET__SHIFT                                                        0x0
16742 #define CP_HQD_AQL_DISPATCH_ID__CONSUMED_OFFSET_MASK                                                          0xFFFFFFFFL
16743 //CP_HQD_AQL_DISPATCH_ID_HI
16744 #define CP_HQD_AQL_DISPATCH_ID_HI__CONSUMED_OFFSET__SHIFT                                                     0x0
16745 #define CP_HQD_AQL_DISPATCH_ID_HI__CONSUMED_OFFSET_MASK                                                       0xFFFFFFFFL
16746 
16747 
16748 // addressBlock: xcd0_gc_tcpdec
16749 //TCP_WATCH0_ADDR_H
16750 #define TCP_WATCH0_ADDR_H__ADDR__SHIFT                                                                        0x0
16751 #define TCP_WATCH0_ADDR_H__ADDR_MASK                                                                          0x0000FFFFL
16752 //TCP_WATCH0_ADDR_L
16753 #define TCP_WATCH0_ADDR_L__ADDR__SHIFT                                                                        0x7
16754 #define TCP_WATCH0_ADDR_L__ADDR_MASK                                                                          0xFFFFFF80L
16755 //TCP_WATCH0_CNTL
16756 #define TCP_WATCH0_CNTL__MASK__SHIFT                                                                          0x0
16757 #define TCP_WATCH0_CNTL__VMID__SHIFT                                                                          0x18
16758 #define TCP_WATCH0_CNTL__ATC__SHIFT                                                                           0x1c
16759 #define TCP_WATCH0_CNTL__MODE__SHIFT                                                                          0x1d
16760 #define TCP_WATCH0_CNTL__VALID__SHIFT                                                                         0x1f
16761 #define TCP_WATCH0_CNTL__MASK_MASK                                                                            0x00FFFFFFL
16762 #define TCP_WATCH0_CNTL__VMID_MASK                                                                            0x0F000000L
16763 #define TCP_WATCH0_CNTL__ATC_MASK                                                                             0x10000000L
16764 #define TCP_WATCH0_CNTL__MODE_MASK                                                                            0x60000000L
16765 #define TCP_WATCH0_CNTL__VALID_MASK                                                                           0x80000000L
16766 //TCP_WATCH1_ADDR_H
16767 #define TCP_WATCH1_ADDR_H__ADDR__SHIFT                                                                        0x0
16768 #define TCP_WATCH1_ADDR_H__ADDR_MASK                                                                          0x0000FFFFL
16769 //TCP_WATCH1_ADDR_L
16770 #define TCP_WATCH1_ADDR_L__ADDR__SHIFT                                                                        0x7
16771 #define TCP_WATCH1_ADDR_L__ADDR_MASK                                                                          0xFFFFFF80L
16772 //TCP_WATCH1_CNTL
16773 #define TCP_WATCH1_CNTL__MASK__SHIFT                                                                          0x0
16774 #define TCP_WATCH1_CNTL__VMID__SHIFT                                                                          0x18
16775 #define TCP_WATCH1_CNTL__ATC__SHIFT                                                                           0x1c
16776 #define TCP_WATCH1_CNTL__MODE__SHIFT                                                                          0x1d
16777 #define TCP_WATCH1_CNTL__VALID__SHIFT                                                                         0x1f
16778 #define TCP_WATCH1_CNTL__MASK_MASK                                                                            0x00FFFFFFL
16779 #define TCP_WATCH1_CNTL__VMID_MASK                                                                            0x0F000000L
16780 #define TCP_WATCH1_CNTL__ATC_MASK                                                                             0x10000000L
16781 #define TCP_WATCH1_CNTL__MODE_MASK                                                                            0x60000000L
16782 #define TCP_WATCH1_CNTL__VALID_MASK                                                                           0x80000000L
16783 //TCP_WATCH2_ADDR_H
16784 #define TCP_WATCH2_ADDR_H__ADDR__SHIFT                                                                        0x0
16785 #define TCP_WATCH2_ADDR_H__ADDR_MASK                                                                          0x0000FFFFL
16786 //TCP_WATCH2_ADDR_L
16787 #define TCP_WATCH2_ADDR_L__ADDR__SHIFT                                                                        0x7
16788 #define TCP_WATCH2_ADDR_L__ADDR_MASK                                                                          0xFFFFFF80L
16789 //TCP_WATCH2_CNTL
16790 #define TCP_WATCH2_CNTL__MASK__SHIFT                                                                          0x0
16791 #define TCP_WATCH2_CNTL__VMID__SHIFT                                                                          0x18
16792 #define TCP_WATCH2_CNTL__ATC__SHIFT                                                                           0x1c
16793 #define TCP_WATCH2_CNTL__MODE__SHIFT                                                                          0x1d
16794 #define TCP_WATCH2_CNTL__VALID__SHIFT                                                                         0x1f
16795 #define TCP_WATCH2_CNTL__MASK_MASK                                                                            0x00FFFFFFL
16796 #define TCP_WATCH2_CNTL__VMID_MASK                                                                            0x0F000000L
16797 #define TCP_WATCH2_CNTL__ATC_MASK                                                                             0x10000000L
16798 #define TCP_WATCH2_CNTL__MODE_MASK                                                                            0x60000000L
16799 #define TCP_WATCH2_CNTL__VALID_MASK                                                                           0x80000000L
16800 //TCP_WATCH3_ADDR_H
16801 #define TCP_WATCH3_ADDR_H__ADDR__SHIFT                                                                        0x0
16802 #define TCP_WATCH3_ADDR_H__ADDR_MASK                                                                          0x0000FFFFL
16803 //TCP_WATCH3_ADDR_L
16804 #define TCP_WATCH3_ADDR_L__ADDR__SHIFT                                                                        0x7
16805 #define TCP_WATCH3_ADDR_L__ADDR_MASK                                                                          0xFFFFFF80L
16806 //TCP_WATCH3_CNTL
16807 #define TCP_WATCH3_CNTL__MASK__SHIFT                                                                          0x0
16808 #define TCP_WATCH3_CNTL__VMID__SHIFT                                                                          0x18
16809 #define TCP_WATCH3_CNTL__ATC__SHIFT                                                                           0x1c
16810 #define TCP_WATCH3_CNTL__MODE__SHIFT                                                                          0x1d
16811 #define TCP_WATCH3_CNTL__VALID__SHIFT                                                                         0x1f
16812 #define TCP_WATCH3_CNTL__MASK_MASK                                                                            0x00FFFFFFL
16813 #define TCP_WATCH3_CNTL__VMID_MASK                                                                            0x0F000000L
16814 #define TCP_WATCH3_CNTL__ATC_MASK                                                                             0x10000000L
16815 #define TCP_WATCH3_CNTL__MODE_MASK                                                                            0x60000000L
16816 #define TCP_WATCH3_CNTL__VALID_MASK                                                                           0x80000000L
16817 //TCP_GATCL1_CNTL
16818 #define TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID__SHIFT                                                           0x19
16819 #define TCP_GATCL1_CNTL__FORCE_MISS__SHIFT                                                                    0x1a
16820 #define TCP_GATCL1_CNTL__FORCE_IN_ORDER__SHIFT                                                                0x1b
16821 #define TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2__SHIFT                                                        0x1c
16822 #define TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2__SHIFT                                                        0x1e
16823 #define TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID_MASK                                                             0x02000000L
16824 #define TCP_GATCL1_CNTL__FORCE_MISS_MASK                                                                      0x04000000L
16825 #define TCP_GATCL1_CNTL__FORCE_IN_ORDER_MASK                                                                  0x08000000L
16826 #define TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2_MASK                                                          0x30000000L
16827 #define TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2_MASK                                                          0xC0000000L
16828 //TCP_ATC_EDC_GATCL1_CNT
16829 #define TCP_ATC_EDC_GATCL1_CNT__DATA_SEC__SHIFT                                                               0x0
16830 #define TCP_ATC_EDC_GATCL1_CNT__DATA_SEC_MASK                                                                 0x000000FFL
16831 //TCP_GATCL1_DSM_CNTL
16832 #define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0__SHIFT                                      0x0
16833 #define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1__SHIFT                                      0x1
16834 #define TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A__SHIFT                                          0x2
16835 #define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0_MASK                                        0x00000001L
16836 #define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1_MASK                                        0x00000002L
16837 #define TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A_MASK                                            0x00000004L
16838 //TCP_DSM_CNTL
16839 #define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL__SHIFT                                                     0x0
16840 #define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE__SHIFT                                                 0x2
16841 #define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_DATA_SEL__SHIFT                                                     0x3
16842 #define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_SINGLE_WRITE__SHIFT                                                 0x5
16843 #define TCP_DSM_CNTL__CMD_FIFO_IRRITATOR_DATA_SEL__SHIFT                                                      0x6
16844 #define TCP_DSM_CNTL__CMD_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT                                                  0x8
16845 #define TCP_DSM_CNTL__VM_FIFO_IRRITATOR_DATA_SEL__SHIFT                                                       0x9
16846 #define TCP_DSM_CNTL__VM_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT                                                   0xb
16847 #define TCP_DSM_CNTL__DB_RAM_IRRITATOR_DATA_SEL__SHIFT                                                        0xc
16848 #define TCP_DSM_CNTL__DB_RAM_IRRITATOR_SINGLE_WRITE__SHIFT                                                    0xe
16849 #define TCP_DSM_CNTL__UTCL1_LFIFO0_IRRITATOR_DATA_SEL__SHIFT                                                  0xf
16850 #define TCP_DSM_CNTL__UTCL1_LFIFO0_IRRITATOR_SINGLE_WRITE__SHIFT                                              0x11
16851 #define TCP_DSM_CNTL__UTCL1_LFIFO1_IRRITATOR_DATA_SEL__SHIFT                                                  0x12
16852 #define TCP_DSM_CNTL__UTCL1_LFIFO1_IRRITATOR_SINGLE_WRITE__SHIFT                                              0x14
16853 #define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL_MASK                                                       0x00000003L
16854 #define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE_MASK                                                   0x00000004L
16855 #define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_DATA_SEL_MASK                                                       0x00000018L
16856 #define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_SINGLE_WRITE_MASK                                                   0x00000020L
16857 #define TCP_DSM_CNTL__CMD_FIFO_IRRITATOR_DATA_SEL_MASK                                                        0x000000C0L
16858 #define TCP_DSM_CNTL__CMD_FIFO_IRRITATOR_SINGLE_WRITE_MASK                                                    0x00000100L
16859 #define TCP_DSM_CNTL__VM_FIFO_IRRITATOR_DATA_SEL_MASK                                                         0x00000600L
16860 #define TCP_DSM_CNTL__VM_FIFO_IRRITATOR_SINGLE_WRITE_MASK                                                     0x00000800L
16861 #define TCP_DSM_CNTL__DB_RAM_IRRITATOR_DATA_SEL_MASK                                                          0x00003000L
16862 #define TCP_DSM_CNTL__DB_RAM_IRRITATOR_SINGLE_WRITE_MASK                                                      0x00004000L
16863 #define TCP_DSM_CNTL__UTCL1_LFIFO0_IRRITATOR_DATA_SEL_MASK                                                    0x00018000L
16864 #define TCP_DSM_CNTL__UTCL1_LFIFO0_IRRITATOR_SINGLE_WRITE_MASK                                                0x00020000L
16865 #define TCP_DSM_CNTL__UTCL1_LFIFO1_IRRITATOR_DATA_SEL_MASK                                                    0x000C0000L
16866 #define TCP_DSM_CNTL__UTCL1_LFIFO1_IRRITATOR_SINGLE_WRITE_MASK                                                0x00100000L
16867 //TCP_CNTL2
16868 #define TCP_CNTL2__LS_DISABLE_CLOCKS__SHIFT                                                                   0x0
16869 #define TCP_CNTL2__TCPF_FMT_MGCG_DISABLE__SHIFT                                                               0x8
16870 #define TCP_CNTL2__TCPI_NEW_MGCG_CTRL_BIT__SHIFT                                                              0xa
16871 #define TCP_CNTL2__MISS_CLK_DISABLE__SHIFT                                                                    0xb
16872 #define TCP_CNTL2__ADRS_CLK_DISABLE__SHIFT                                                                    0xc
16873 #define TCP_CNTL2__VM_CLK_DISABLE__SHIFT                                                                      0xd
16874 #define TCP_CNTL2__TAGRAM_CLK_DISABLE__SHIFT                                                                  0xe
16875 #define TCP_CNTL2__LEGACY_MGCG_DISABLE__SHIFT                                                                 0xf
16876 #define TCP_CNTL2__MEM_MID_GATE_MGCG_DISABLE__SHIFT                                                           0x13
16877 #define TCP_CNTL2__UTCL1_MID_GATE_MGCG_DISABLE__SHIFT                                                         0x14
16878 #define TCP_CNTL2__LS_DISABLE_CLOCKS_MASK                                                                     0x000000FFL
16879 #define TCP_CNTL2__TCPF_FMT_MGCG_DISABLE_MASK                                                                 0x00000100L
16880 #define TCP_CNTL2__TCPI_NEW_MGCG_CTRL_BIT_MASK                                                                0x00000400L
16881 #define TCP_CNTL2__MISS_CLK_DISABLE_MASK                                                                      0x00000800L
16882 #define TCP_CNTL2__ADRS_CLK_DISABLE_MASK                                                                      0x00001000L
16883 #define TCP_CNTL2__VM_CLK_DISABLE_MASK                                                                        0x00002000L
16884 #define TCP_CNTL2__TAGRAM_CLK_DISABLE_MASK                                                                    0x00004000L
16885 #define TCP_CNTL2__LEGACY_MGCG_DISABLE_MASK                                                                   0x00008000L
16886 #define TCP_CNTL2__MEM_MID_GATE_MGCG_DISABLE_MASK                                                             0x00080000L
16887 #define TCP_CNTL2__UTCL1_MID_GATE_MGCG_DISABLE_MASK                                                           0x00100000L
16888 //TCP_UTCL1_CNTL1
16889 #define TCP_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT                                                              0x0
16890 #define TCP_UTCL1_CNTL1__GPUVM_64K_DEFAULT__SHIFT                                                             0x1
16891 #define TCP_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT                                                               0x2
16892 #define TCP_UTCL1_CNTL1__RESP_MODE__SHIFT                                                                     0x3
16893 #define TCP_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT                                                               0x5
16894 #define TCP_UTCL1_CNTL1__CLIENTID__SHIFT                                                                      0x7
16895 #define TCP_UTCL1_CNTL1__UTCL1_FGCG_REPEATER_DISABLE__SHIFT                                                   0x10
16896 #define TCP_UTCL1_CNTL1__REG_INV_VMID__SHIFT                                                                  0x13
16897 #define TCP_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT                                                              0x17
16898 #define TCP_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT                                                                0x18
16899 #define TCP_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT                                                    0x19
16900 #define TCP_UTCL1_CNTL1__FORCE_MISS__SHIFT                                                                    0x1a
16901 #define TCP_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT                                                        0x1c
16902 #define TCP_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT                                                        0x1e
16903 #define TCP_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK                                                                0x00000001L
16904 #define TCP_UTCL1_CNTL1__GPUVM_64K_DEFAULT_MASK                                                               0x00000002L
16905 #define TCP_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK                                                                 0x00000004L
16906 #define TCP_UTCL1_CNTL1__RESP_MODE_MASK                                                                       0x00000018L
16907 #define TCP_UTCL1_CNTL1__RESP_FAULT_MODE_MASK                                                                 0x00000060L
16908 #define TCP_UTCL1_CNTL1__CLIENTID_MASK                                                                        0x0000FF80L
16909 #define TCP_UTCL1_CNTL1__UTCL1_FGCG_REPEATER_DISABLE_MASK                                                     0x00010000L
16910 #define TCP_UTCL1_CNTL1__REG_INV_VMID_MASK                                                                    0x00780000L
16911 #define TCP_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK                                                                0x00800000L
16912 #define TCP_UTCL1_CNTL1__REG_INV_TOGGLE_MASK                                                                  0x01000000L
16913 #define TCP_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK                                                      0x02000000L
16914 #define TCP_UTCL1_CNTL1__FORCE_MISS_MASK                                                                      0x04000000L
16915 #define TCP_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK                                                          0x30000000L
16916 #define TCP_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK                                                          0xC0000000L
16917 //TCP_UTCL1_CNTL2
16918 #define TCP_UTCL1_CNTL2__SPARE__SHIFT                                                                         0x0
16919 #define TCP_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT                                                                0x9
16920 #define TCP_UTCL1_CNTL2__ANY_LINE_VALID__SHIFT                                                                0xa
16921 #define TCP_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT                                                                0xc
16922 #define TCP_UTCL1_CNTL2__FORCE_SNOOP__SHIFT                                                                   0xe
16923 #define TCP_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT                                                           0xf
16924 #define TCP_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT                                                          0x1a
16925 #define TCP_UTCL1_CNTL2__THRASHING_TIMEOUT_PROTECT_ENABLE__SHIFT                                              0x1b
16926 #define TCP_UTCL1_CNTL2__THRASHING_ENABLE__SHIFT                                                              0x1c
16927 #define TCP_UTCL1_CNTL2__SPARE_MASK                                                                           0x000000FFL
16928 #define TCP_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK                                                                  0x00000200L
16929 #define TCP_UTCL1_CNTL2__ANY_LINE_VALID_MASK                                                                  0x00000400L
16930 #define TCP_UTCL1_CNTL2__GPUVM_INV_MODE_MASK                                                                  0x00001000L
16931 #define TCP_UTCL1_CNTL2__FORCE_SNOOP_MASK                                                                     0x00004000L
16932 #define TCP_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK                                                             0x00008000L
16933 #define TCP_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK                                                            0x04000000L
16934 #define TCP_UTCL1_CNTL2__THRASHING_TIMEOUT_PROTECT_ENABLE_MASK                                                0x08000000L
16935 #define TCP_UTCL1_CNTL2__THRASHING_ENABLE_MASK                                                                0x10000000L
16936 //TCP_UTCL1_STATUS
16937 #define TCP_UTCL1_STATUS__FAULT_DETECTED__SHIFT                                                               0x0
16938 #define TCP_UTCL1_STATUS__RETRY_DETECTED__SHIFT                                                               0x1
16939 #define TCP_UTCL1_STATUS__PRT_DETECTED__SHIFT                                                                 0x2
16940 #define TCP_UTCL1_STATUS__TIMEOUT_DETECTED__SHIFT                                                             0x3
16941 #define TCP_UTCL1_STATUS__FAULT_DETECTED_MASK                                                                 0x00000001L
16942 #define TCP_UTCL1_STATUS__RETRY_DETECTED_MASK                                                                 0x00000002L
16943 #define TCP_UTCL1_STATUS__PRT_DETECTED_MASK                                                                   0x00000004L
16944 #define TCP_UTCL1_STATUS__TIMEOUT_DETECTED_MASK                                                               0x00000008L
16945 //TCP_DSM_CNTL2
16946 #define TCP_DSM_CNTL2__CACHE_RAM_ENABLE_ERROR_INJECT__SHIFT                                                   0x0
16947 #define TCP_DSM_CNTL2__CACHE_RAM_SELECT_INJECT_DELAY__SHIFT                                                   0x2
16948 #define TCP_DSM_CNTL2__LFIFO_RAM_ENABLE_ERROR_INJECT__SHIFT                                                   0x3
16949 #define TCP_DSM_CNTL2__LFIFO_RAM_SELECT_INJECT_DELAY__SHIFT                                                   0x5
16950 #define TCP_DSM_CNTL2__CMD_FIFO_ENABLE_ERROR_INJECT__SHIFT                                                    0x6
16951 #define TCP_DSM_CNTL2__CMD_FIFO_SELECT_INJECT_DELAY__SHIFT                                                    0x8
16952 #define TCP_DSM_CNTL2__VM_FIFO_ENABLE_ERROR_INJECT__SHIFT                                                     0x9
16953 #define TCP_DSM_CNTL2__VM_FIFO_SELECT_INJECT_DELAY__SHIFT                                                     0xb
16954 #define TCP_DSM_CNTL2__DB_RAM_ENABLE_ERROR_INJECT__SHIFT                                                      0xc
16955 #define TCP_DSM_CNTL2__DB_RAM_SELECT_INJECT_DELAY__SHIFT                                                      0xe
16956 #define TCP_DSM_CNTL2__UTCL1_LFIFO0_ENABLE_ERROR_INJECT__SHIFT                                                0xf
16957 #define TCP_DSM_CNTL2__UTCL1_LFIFO0_SELECT_INJECT_DELAY__SHIFT                                                0x11
16958 #define TCP_DSM_CNTL2__UTCL1_LFIFO1_ENABLE_ERROR_INJECT__SHIFT                                                0x12
16959 #define TCP_DSM_CNTL2__UTCL1_LFIFO1_SELECT_INJECT_DELAY__SHIFT                                                0x14
16960 #define TCP_DSM_CNTL2__TCP_INJECT_DELAY__SHIFT                                                                0x1a
16961 #define TCP_DSM_CNTL2__CACHE_RAM_ENABLE_ERROR_INJECT_MASK                                                     0x00000003L
16962 #define TCP_DSM_CNTL2__CACHE_RAM_SELECT_INJECT_DELAY_MASK                                                     0x00000004L
16963 #define TCP_DSM_CNTL2__LFIFO_RAM_ENABLE_ERROR_INJECT_MASK                                                     0x00000018L
16964 #define TCP_DSM_CNTL2__LFIFO_RAM_SELECT_INJECT_DELAY_MASK                                                     0x00000020L
16965 #define TCP_DSM_CNTL2__CMD_FIFO_ENABLE_ERROR_INJECT_MASK                                                      0x000000C0L
16966 #define TCP_DSM_CNTL2__CMD_FIFO_SELECT_INJECT_DELAY_MASK                                                      0x00000100L
16967 #define TCP_DSM_CNTL2__VM_FIFO_ENABLE_ERROR_INJECT_MASK                                                       0x00000600L
16968 #define TCP_DSM_CNTL2__VM_FIFO_SELECT_INJECT_DELAY_MASK                                                       0x00000800L
16969 #define TCP_DSM_CNTL2__DB_RAM_ENABLE_ERROR_INJECT_MASK                                                        0x00003000L
16970 #define TCP_DSM_CNTL2__DB_RAM_SELECT_INJECT_DELAY_MASK                                                        0x00004000L
16971 #define TCP_DSM_CNTL2__UTCL1_LFIFO0_ENABLE_ERROR_INJECT_MASK                                                  0x00018000L
16972 #define TCP_DSM_CNTL2__UTCL1_LFIFO0_SELECT_INJECT_DELAY_MASK                                                  0x00020000L
16973 #define TCP_DSM_CNTL2__UTCL1_LFIFO1_ENABLE_ERROR_INJECT_MASK                                                  0x000C0000L
16974 #define TCP_DSM_CNTL2__UTCL1_LFIFO1_SELECT_INJECT_DELAY_MASK                                                  0x00100000L
16975 #define TCP_DSM_CNTL2__TCP_INJECT_DELAY_MASK                                                                  0xFC000000L
16976 //TCP_PERFCOUNTER_FILTER
16977 #define TCP_PERFCOUNTER_FILTER__BUFFER__SHIFT                                                                 0x0
16978 #define TCP_PERFCOUNTER_FILTER__FLAT__SHIFT                                                                   0x1
16979 #define TCP_PERFCOUNTER_FILTER__DIM__SHIFT                                                                    0x2
16980 #define TCP_PERFCOUNTER_FILTER__DATA_FORMAT__SHIFT                                                            0x5
16981 #define TCP_PERFCOUNTER_FILTER__NUM_FORMAT__SHIFT                                                             0xb
16982 #define TCP_PERFCOUNTER_FILTER__SW_MODE__SHIFT                                                                0xf
16983 #define TCP_PERFCOUNTER_FILTER__NUM_SAMPLES__SHIFT                                                            0x14
16984 #define TCP_PERFCOUNTER_FILTER__OPCODE_TYPE__SHIFT                                                            0x16
16985 #define TCP_PERFCOUNTER_FILTER__GLC__SHIFT                                                                    0x19
16986 #define TCP_PERFCOUNTER_FILTER__SLC__SHIFT                                                                    0x1a
16987 #define TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE__SHIFT                                                     0x1b
16988 #define TCP_PERFCOUNTER_FILTER__ADDR_MODE__SHIFT                                                              0x1c
16989 #define TCP_PERFCOUNTER_FILTER__BUFFER_MASK                                                                   0x00000001L
16990 #define TCP_PERFCOUNTER_FILTER__FLAT_MASK                                                                     0x00000002L
16991 #define TCP_PERFCOUNTER_FILTER__DIM_MASK                                                                      0x0000001CL
16992 #define TCP_PERFCOUNTER_FILTER__DATA_FORMAT_MASK                                                              0x000007E0L
16993 #define TCP_PERFCOUNTER_FILTER__NUM_FORMAT_MASK                                                               0x00007800L
16994 #define TCP_PERFCOUNTER_FILTER__SW_MODE_MASK                                                                  0x000F8000L
16995 #define TCP_PERFCOUNTER_FILTER__NUM_SAMPLES_MASK                                                              0x00300000L
16996 #define TCP_PERFCOUNTER_FILTER__OPCODE_TYPE_MASK                                                              0x01C00000L
16997 #define TCP_PERFCOUNTER_FILTER__GLC_MASK                                                                      0x02000000L
16998 #define TCP_PERFCOUNTER_FILTER__SLC_MASK                                                                      0x04000000L
16999 #define TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE_MASK                                                       0x08000000L
17000 #define TCP_PERFCOUNTER_FILTER__ADDR_MODE_MASK                                                                0x70000000L
17001 //TCP_PERFCOUNTER_FILTER_EN
17002 #define TCP_PERFCOUNTER_FILTER_EN__BUFFER__SHIFT                                                              0x0
17003 #define TCP_PERFCOUNTER_FILTER_EN__FLAT__SHIFT                                                                0x1
17004 #define TCP_PERFCOUNTER_FILTER_EN__DIM__SHIFT                                                                 0x2
17005 #define TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT__SHIFT                                                         0x3
17006 #define TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT__SHIFT                                                          0x4
17007 #define TCP_PERFCOUNTER_FILTER_EN__SW_MODE__SHIFT                                                             0x5
17008 #define TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES__SHIFT                                                         0x6
17009 #define TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE__SHIFT                                                         0x7
17010 #define TCP_PERFCOUNTER_FILTER_EN__GLC__SHIFT                                                                 0x8
17011 #define TCP_PERFCOUNTER_FILTER_EN__SLC__SHIFT                                                                 0x9
17012 #define TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE__SHIFT                                                  0xa
17013 #define TCP_PERFCOUNTER_FILTER_EN__ADDR_MODE__SHIFT                                                           0xb
17014 #define TCP_PERFCOUNTER_FILTER_EN__BUFFER_MASK                                                                0x00000001L
17015 #define TCP_PERFCOUNTER_FILTER_EN__FLAT_MASK                                                                  0x00000002L
17016 #define TCP_PERFCOUNTER_FILTER_EN__DIM_MASK                                                                   0x00000004L
17017 #define TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT_MASK                                                           0x00000008L
17018 #define TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT_MASK                                                            0x00000010L
17019 #define TCP_PERFCOUNTER_FILTER_EN__SW_MODE_MASK                                                               0x00000020L
17020 #define TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES_MASK                                                           0x00000040L
17021 #define TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE_MASK                                                           0x00000080L
17022 #define TCP_PERFCOUNTER_FILTER_EN__GLC_MASK                                                                   0x00000100L
17023 #define TCP_PERFCOUNTER_FILTER_EN__SLC_MASK                                                                   0x00000200L
17024 #define TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE_MASK                                                    0x00000400L
17025 #define TCP_PERFCOUNTER_FILTER_EN__ADDR_MODE_MASK                                                             0x00000800L
17026 
17027 
17028 // addressBlock: xcd0_gc_gdspdec
17029 //GDS_VMID0_BASE
17030 #define GDS_VMID0_BASE__BASE__SHIFT                                                                           0x0
17031 #define GDS_VMID0_BASE__BASE_MASK                                                                             0x0000FFFFL
17032 //GDS_VMID0_SIZE
17033 #define GDS_VMID0_SIZE__SIZE__SHIFT                                                                           0x0
17034 #define GDS_VMID0_SIZE__SIZE_MASK                                                                             0x0001FFFFL
17035 //GDS_VMID1_BASE
17036 #define GDS_VMID1_BASE__BASE__SHIFT                                                                           0x0
17037 #define GDS_VMID1_BASE__BASE_MASK                                                                             0x0000FFFFL
17038 //GDS_VMID1_SIZE
17039 #define GDS_VMID1_SIZE__SIZE__SHIFT                                                                           0x0
17040 #define GDS_VMID1_SIZE__SIZE_MASK                                                                             0x0001FFFFL
17041 //GDS_VMID2_BASE
17042 #define GDS_VMID2_BASE__BASE__SHIFT                                                                           0x0
17043 #define GDS_VMID2_BASE__BASE_MASK                                                                             0x0000FFFFL
17044 //GDS_VMID2_SIZE
17045 #define GDS_VMID2_SIZE__SIZE__SHIFT                                                                           0x0
17046 #define GDS_VMID2_SIZE__SIZE_MASK                                                                             0x0001FFFFL
17047 //GDS_VMID3_BASE
17048 #define GDS_VMID3_BASE__BASE__SHIFT                                                                           0x0
17049 #define GDS_VMID3_BASE__BASE_MASK                                                                             0x0000FFFFL
17050 //GDS_VMID3_SIZE
17051 #define GDS_VMID3_SIZE__SIZE__SHIFT                                                                           0x0
17052 #define GDS_VMID3_SIZE__SIZE_MASK                                                                             0x0001FFFFL
17053 //GDS_VMID4_BASE
17054 #define GDS_VMID4_BASE__BASE__SHIFT                                                                           0x0
17055 #define GDS_VMID4_BASE__BASE_MASK                                                                             0x0000FFFFL
17056 //GDS_VMID4_SIZE
17057 #define GDS_VMID4_SIZE__SIZE__SHIFT                                                                           0x0
17058 #define GDS_VMID4_SIZE__SIZE_MASK                                                                             0x0001FFFFL
17059 //GDS_VMID5_BASE
17060 #define GDS_VMID5_BASE__BASE__SHIFT                                                                           0x0
17061 #define GDS_VMID5_BASE__BASE_MASK                                                                             0x0000FFFFL
17062 //GDS_VMID5_SIZE
17063 #define GDS_VMID5_SIZE__SIZE__SHIFT                                                                           0x0
17064 #define GDS_VMID5_SIZE__SIZE_MASK                                                                             0x0001FFFFL
17065 //GDS_VMID6_BASE
17066 #define GDS_VMID6_BASE__BASE__SHIFT                                                                           0x0
17067 #define GDS_VMID6_BASE__BASE_MASK                                                                             0x0000FFFFL
17068 //GDS_VMID6_SIZE
17069 #define GDS_VMID6_SIZE__SIZE__SHIFT                                                                           0x0
17070 #define GDS_VMID6_SIZE__SIZE_MASK                                                                             0x0001FFFFL
17071 //GDS_VMID7_BASE
17072 #define GDS_VMID7_BASE__BASE__SHIFT                                                                           0x0
17073 #define GDS_VMID7_BASE__BASE_MASK                                                                             0x0000FFFFL
17074 //GDS_VMID7_SIZE
17075 #define GDS_VMID7_SIZE__SIZE__SHIFT                                                                           0x0
17076 #define GDS_VMID7_SIZE__SIZE_MASK                                                                             0x0001FFFFL
17077 //GDS_VMID8_BASE
17078 #define GDS_VMID8_BASE__BASE__SHIFT                                                                           0x0
17079 #define GDS_VMID8_BASE__BASE_MASK                                                                             0x0000FFFFL
17080 //GDS_VMID8_SIZE
17081 #define GDS_VMID8_SIZE__SIZE__SHIFT                                                                           0x0
17082 #define GDS_VMID8_SIZE__SIZE_MASK                                                                             0x0001FFFFL
17083 //GDS_VMID9_BASE
17084 #define GDS_VMID9_BASE__BASE__SHIFT                                                                           0x0
17085 #define GDS_VMID9_BASE__BASE_MASK                                                                             0x0000FFFFL
17086 //GDS_VMID9_SIZE
17087 #define GDS_VMID9_SIZE__SIZE__SHIFT                                                                           0x0
17088 #define GDS_VMID9_SIZE__SIZE_MASK                                                                             0x0001FFFFL
17089 //GDS_VMID10_BASE
17090 #define GDS_VMID10_BASE__BASE__SHIFT                                                                          0x0
17091 #define GDS_VMID10_BASE__BASE_MASK                                                                            0x0000FFFFL
17092 //GDS_VMID10_SIZE
17093 #define GDS_VMID10_SIZE__SIZE__SHIFT                                                                          0x0
17094 #define GDS_VMID10_SIZE__SIZE_MASK                                                                            0x0001FFFFL
17095 //GDS_VMID11_BASE
17096 #define GDS_VMID11_BASE__BASE__SHIFT                                                                          0x0
17097 #define GDS_VMID11_BASE__BASE_MASK                                                                            0x0000FFFFL
17098 //GDS_VMID11_SIZE
17099 #define GDS_VMID11_SIZE__SIZE__SHIFT                                                                          0x0
17100 #define GDS_VMID11_SIZE__SIZE_MASK                                                                            0x0001FFFFL
17101 //GDS_VMID12_BASE
17102 #define GDS_VMID12_BASE__BASE__SHIFT                                                                          0x0
17103 #define GDS_VMID12_BASE__BASE_MASK                                                                            0x0000FFFFL
17104 //GDS_VMID12_SIZE
17105 #define GDS_VMID12_SIZE__SIZE__SHIFT                                                                          0x0
17106 #define GDS_VMID12_SIZE__SIZE_MASK                                                                            0x0001FFFFL
17107 //GDS_VMID13_BASE
17108 #define GDS_VMID13_BASE__BASE__SHIFT                                                                          0x0
17109 #define GDS_VMID13_BASE__BASE_MASK                                                                            0x0000FFFFL
17110 //GDS_VMID13_SIZE
17111 #define GDS_VMID13_SIZE__SIZE__SHIFT                                                                          0x0
17112 #define GDS_VMID13_SIZE__SIZE_MASK                                                                            0x0001FFFFL
17113 //GDS_VMID14_BASE
17114 #define GDS_VMID14_BASE__BASE__SHIFT                                                                          0x0
17115 #define GDS_VMID14_BASE__BASE_MASK                                                                            0x0000FFFFL
17116 //GDS_VMID14_SIZE
17117 #define GDS_VMID14_SIZE__SIZE__SHIFT                                                                          0x0
17118 #define GDS_VMID14_SIZE__SIZE_MASK                                                                            0x0001FFFFL
17119 //GDS_VMID15_BASE
17120 #define GDS_VMID15_BASE__BASE__SHIFT                                                                          0x0
17121 #define GDS_VMID15_BASE__BASE_MASK                                                                            0x0000FFFFL
17122 //GDS_VMID15_SIZE
17123 #define GDS_VMID15_SIZE__SIZE__SHIFT                                                                          0x0
17124 #define GDS_VMID15_SIZE__SIZE_MASK                                                                            0x0001FFFFL
17125 //GDS_GWS_VMID0
17126 #define GDS_GWS_VMID0__BASE__SHIFT                                                                            0x0
17127 #define GDS_GWS_VMID0__SIZE__SHIFT                                                                            0x10
17128 #define GDS_GWS_VMID0__BASE_MASK                                                                              0x0000003FL
17129 #define GDS_GWS_VMID0__SIZE_MASK                                                                              0x007F0000L
17130 //GDS_GWS_VMID1
17131 #define GDS_GWS_VMID1__BASE__SHIFT                                                                            0x0
17132 #define GDS_GWS_VMID1__SIZE__SHIFT                                                                            0x10
17133 #define GDS_GWS_VMID1__BASE_MASK                                                                              0x0000003FL
17134 #define GDS_GWS_VMID1__SIZE_MASK                                                                              0x007F0000L
17135 //GDS_GWS_VMID2
17136 #define GDS_GWS_VMID2__BASE__SHIFT                                                                            0x0
17137 #define GDS_GWS_VMID2__SIZE__SHIFT                                                                            0x10
17138 #define GDS_GWS_VMID2__BASE_MASK                                                                              0x0000003FL
17139 #define GDS_GWS_VMID2__SIZE_MASK                                                                              0x007F0000L
17140 //GDS_GWS_VMID3
17141 #define GDS_GWS_VMID3__BASE__SHIFT                                                                            0x0
17142 #define GDS_GWS_VMID3__SIZE__SHIFT                                                                            0x10
17143 #define GDS_GWS_VMID3__BASE_MASK                                                                              0x0000003FL
17144 #define GDS_GWS_VMID3__SIZE_MASK                                                                              0x007F0000L
17145 //GDS_GWS_VMID4
17146 #define GDS_GWS_VMID4__BASE__SHIFT                                                                            0x0
17147 #define GDS_GWS_VMID4__SIZE__SHIFT                                                                            0x10
17148 #define GDS_GWS_VMID4__BASE_MASK                                                                              0x0000003FL
17149 #define GDS_GWS_VMID4__SIZE_MASK                                                                              0x007F0000L
17150 //GDS_GWS_VMID5
17151 #define GDS_GWS_VMID5__BASE__SHIFT                                                                            0x0
17152 #define GDS_GWS_VMID5__SIZE__SHIFT                                                                            0x10
17153 #define GDS_GWS_VMID5__BASE_MASK                                                                              0x0000003FL
17154 #define GDS_GWS_VMID5__SIZE_MASK                                                                              0x007F0000L
17155 //GDS_GWS_VMID6
17156 #define GDS_GWS_VMID6__BASE__SHIFT                                                                            0x0
17157 #define GDS_GWS_VMID6__SIZE__SHIFT                                                                            0x10
17158 #define GDS_GWS_VMID6__BASE_MASK                                                                              0x0000003FL
17159 #define GDS_GWS_VMID6__SIZE_MASK                                                                              0x007F0000L
17160 //GDS_GWS_VMID7
17161 #define GDS_GWS_VMID7__BASE__SHIFT                                                                            0x0
17162 #define GDS_GWS_VMID7__SIZE__SHIFT                                                                            0x10
17163 #define GDS_GWS_VMID7__BASE_MASK                                                                              0x0000003FL
17164 #define GDS_GWS_VMID7__SIZE_MASK                                                                              0x007F0000L
17165 //GDS_GWS_VMID8
17166 #define GDS_GWS_VMID8__BASE__SHIFT                                                                            0x0
17167 #define GDS_GWS_VMID8__SIZE__SHIFT                                                                            0x10
17168 #define GDS_GWS_VMID8__BASE_MASK                                                                              0x0000003FL
17169 #define GDS_GWS_VMID8__SIZE_MASK                                                                              0x007F0000L
17170 //GDS_GWS_VMID9
17171 #define GDS_GWS_VMID9__BASE__SHIFT                                                                            0x0
17172 #define GDS_GWS_VMID9__SIZE__SHIFT                                                                            0x10
17173 #define GDS_GWS_VMID9__BASE_MASK                                                                              0x0000003FL
17174 #define GDS_GWS_VMID9__SIZE_MASK                                                                              0x007F0000L
17175 //GDS_GWS_VMID10
17176 #define GDS_GWS_VMID10__BASE__SHIFT                                                                           0x0
17177 #define GDS_GWS_VMID10__SIZE__SHIFT                                                                           0x10
17178 #define GDS_GWS_VMID10__BASE_MASK                                                                             0x0000003FL
17179 #define GDS_GWS_VMID10__SIZE_MASK                                                                             0x007F0000L
17180 //GDS_GWS_VMID11
17181 #define GDS_GWS_VMID11__BASE__SHIFT                                                                           0x0
17182 #define GDS_GWS_VMID11__SIZE__SHIFT                                                                           0x10
17183 #define GDS_GWS_VMID11__BASE_MASK                                                                             0x0000003FL
17184 #define GDS_GWS_VMID11__SIZE_MASK                                                                             0x007F0000L
17185 //GDS_GWS_VMID12
17186 #define GDS_GWS_VMID12__BASE__SHIFT                                                                           0x0
17187 #define GDS_GWS_VMID12__SIZE__SHIFT                                                                           0x10
17188 #define GDS_GWS_VMID12__BASE_MASK                                                                             0x0000003FL
17189 #define GDS_GWS_VMID12__SIZE_MASK                                                                             0x007F0000L
17190 //GDS_GWS_VMID13
17191 #define GDS_GWS_VMID13__BASE__SHIFT                                                                           0x0
17192 #define GDS_GWS_VMID13__SIZE__SHIFT                                                                           0x10
17193 #define GDS_GWS_VMID13__BASE_MASK                                                                             0x0000003FL
17194 #define GDS_GWS_VMID13__SIZE_MASK                                                                             0x007F0000L
17195 //GDS_GWS_VMID14
17196 #define GDS_GWS_VMID14__BASE__SHIFT                                                                           0x0
17197 #define GDS_GWS_VMID14__SIZE__SHIFT                                                                           0x10
17198 #define GDS_GWS_VMID14__BASE_MASK                                                                             0x0000003FL
17199 #define GDS_GWS_VMID14__SIZE_MASK                                                                             0x007F0000L
17200 //GDS_GWS_VMID15
17201 #define GDS_GWS_VMID15__BASE__SHIFT                                                                           0x0
17202 #define GDS_GWS_VMID15__SIZE__SHIFT                                                                           0x10
17203 #define GDS_GWS_VMID15__BASE_MASK                                                                             0x0000003FL
17204 #define GDS_GWS_VMID15__SIZE_MASK                                                                             0x007F0000L
17205 //GDS_OA_VMID0
17206 #define GDS_OA_VMID0__MASK__SHIFT                                                                             0x0
17207 #define GDS_OA_VMID0__UNUSED__SHIFT                                                                           0x10
17208 #define GDS_OA_VMID0__MASK_MASK                                                                               0x0000FFFFL
17209 #define GDS_OA_VMID0__UNUSED_MASK                                                                             0xFFFF0000L
17210 //GDS_OA_VMID1
17211 #define GDS_OA_VMID1__MASK__SHIFT                                                                             0x0
17212 #define GDS_OA_VMID1__UNUSED__SHIFT                                                                           0x10
17213 #define GDS_OA_VMID1__MASK_MASK                                                                               0x0000FFFFL
17214 #define GDS_OA_VMID1__UNUSED_MASK                                                                             0xFFFF0000L
17215 //GDS_OA_VMID2
17216 #define GDS_OA_VMID2__MASK__SHIFT                                                                             0x0
17217 #define GDS_OA_VMID2__UNUSED__SHIFT                                                                           0x10
17218 #define GDS_OA_VMID2__MASK_MASK                                                                               0x0000FFFFL
17219 #define GDS_OA_VMID2__UNUSED_MASK                                                                             0xFFFF0000L
17220 //GDS_OA_VMID3
17221 #define GDS_OA_VMID3__MASK__SHIFT                                                                             0x0
17222 #define GDS_OA_VMID3__UNUSED__SHIFT                                                                           0x10
17223 #define GDS_OA_VMID3__MASK_MASK                                                                               0x0000FFFFL
17224 #define GDS_OA_VMID3__UNUSED_MASK                                                                             0xFFFF0000L
17225 //GDS_OA_VMID4
17226 #define GDS_OA_VMID4__MASK__SHIFT                                                                             0x0
17227 #define GDS_OA_VMID4__UNUSED__SHIFT                                                                           0x10
17228 #define GDS_OA_VMID4__MASK_MASK                                                                               0x0000FFFFL
17229 #define GDS_OA_VMID4__UNUSED_MASK                                                                             0xFFFF0000L
17230 //GDS_OA_VMID5
17231 #define GDS_OA_VMID5__MASK__SHIFT                                                                             0x0
17232 #define GDS_OA_VMID5__UNUSED__SHIFT                                                                           0x10
17233 #define GDS_OA_VMID5__MASK_MASK                                                                               0x0000FFFFL
17234 #define GDS_OA_VMID5__UNUSED_MASK                                                                             0xFFFF0000L
17235 //GDS_OA_VMID6
17236 #define GDS_OA_VMID6__MASK__SHIFT                                                                             0x0
17237 #define GDS_OA_VMID6__UNUSED__SHIFT                                                                           0x10
17238 #define GDS_OA_VMID6__MASK_MASK                                                                               0x0000FFFFL
17239 #define GDS_OA_VMID6__UNUSED_MASK                                                                             0xFFFF0000L
17240 //GDS_OA_VMID7
17241 #define GDS_OA_VMID7__MASK__SHIFT                                                                             0x0
17242 #define GDS_OA_VMID7__UNUSED__SHIFT                                                                           0x10
17243 #define GDS_OA_VMID7__MASK_MASK                                                                               0x0000FFFFL
17244 #define GDS_OA_VMID7__UNUSED_MASK                                                                             0xFFFF0000L
17245 //GDS_OA_VMID8
17246 #define GDS_OA_VMID8__MASK__SHIFT                                                                             0x0
17247 #define GDS_OA_VMID8__UNUSED__SHIFT                                                                           0x10
17248 #define GDS_OA_VMID8__MASK_MASK                                                                               0x0000FFFFL
17249 #define GDS_OA_VMID8__UNUSED_MASK                                                                             0xFFFF0000L
17250 //GDS_OA_VMID9
17251 #define GDS_OA_VMID9__MASK__SHIFT                                                                             0x0
17252 #define GDS_OA_VMID9__UNUSED__SHIFT                                                                           0x10
17253 #define GDS_OA_VMID9__MASK_MASK                                                                               0x0000FFFFL
17254 #define GDS_OA_VMID9__UNUSED_MASK                                                                             0xFFFF0000L
17255 //GDS_OA_VMID10
17256 #define GDS_OA_VMID10__MASK__SHIFT                                                                            0x0
17257 #define GDS_OA_VMID10__UNUSED__SHIFT                                                                          0x10
17258 #define GDS_OA_VMID10__MASK_MASK                                                                              0x0000FFFFL
17259 #define GDS_OA_VMID10__UNUSED_MASK                                                                            0xFFFF0000L
17260 //GDS_OA_VMID11
17261 #define GDS_OA_VMID11__MASK__SHIFT                                                                            0x0
17262 #define GDS_OA_VMID11__UNUSED__SHIFT                                                                          0x10
17263 #define GDS_OA_VMID11__MASK_MASK                                                                              0x0000FFFFL
17264 #define GDS_OA_VMID11__UNUSED_MASK                                                                            0xFFFF0000L
17265 //GDS_OA_VMID12
17266 #define GDS_OA_VMID12__MASK__SHIFT                                                                            0x0
17267 #define GDS_OA_VMID12__UNUSED__SHIFT                                                                          0x10
17268 #define GDS_OA_VMID12__MASK_MASK                                                                              0x0000FFFFL
17269 #define GDS_OA_VMID12__UNUSED_MASK                                                                            0xFFFF0000L
17270 //GDS_OA_VMID13
17271 #define GDS_OA_VMID13__MASK__SHIFT                                                                            0x0
17272 #define GDS_OA_VMID13__UNUSED__SHIFT                                                                          0x10
17273 #define GDS_OA_VMID13__MASK_MASK                                                                              0x0000FFFFL
17274 #define GDS_OA_VMID13__UNUSED_MASK                                                                            0xFFFF0000L
17275 //GDS_OA_VMID14
17276 #define GDS_OA_VMID14__MASK__SHIFT                                                                            0x0
17277 #define GDS_OA_VMID14__UNUSED__SHIFT                                                                          0x10
17278 #define GDS_OA_VMID14__MASK_MASK                                                                              0x0000FFFFL
17279 #define GDS_OA_VMID14__UNUSED_MASK                                                                            0xFFFF0000L
17280 //GDS_OA_VMID15
17281 #define GDS_OA_VMID15__MASK__SHIFT                                                                            0x0
17282 #define GDS_OA_VMID15__UNUSED__SHIFT                                                                          0x10
17283 #define GDS_OA_VMID15__MASK_MASK                                                                              0x0000FFFFL
17284 #define GDS_OA_VMID15__UNUSED_MASK                                                                            0xFFFF0000L
17285 //GDS_GWS_RESET0
17286 #define GDS_GWS_RESET0__RESOURCE0_RESET__SHIFT                                                                0x0
17287 #define GDS_GWS_RESET0__RESOURCE1_RESET__SHIFT                                                                0x1
17288 #define GDS_GWS_RESET0__RESOURCE2_RESET__SHIFT                                                                0x2
17289 #define GDS_GWS_RESET0__RESOURCE3_RESET__SHIFT                                                                0x3
17290 #define GDS_GWS_RESET0__RESOURCE4_RESET__SHIFT                                                                0x4
17291 #define GDS_GWS_RESET0__RESOURCE5_RESET__SHIFT                                                                0x5
17292 #define GDS_GWS_RESET0__RESOURCE6_RESET__SHIFT                                                                0x6
17293 #define GDS_GWS_RESET0__RESOURCE7_RESET__SHIFT                                                                0x7
17294 #define GDS_GWS_RESET0__RESOURCE8_RESET__SHIFT                                                                0x8
17295 #define GDS_GWS_RESET0__RESOURCE9_RESET__SHIFT                                                                0x9
17296 #define GDS_GWS_RESET0__RESOURCE10_RESET__SHIFT                                                               0xa
17297 #define GDS_GWS_RESET0__RESOURCE11_RESET__SHIFT                                                               0xb
17298 #define GDS_GWS_RESET0__RESOURCE12_RESET__SHIFT                                                               0xc
17299 #define GDS_GWS_RESET0__RESOURCE13_RESET__SHIFT                                                               0xd
17300 #define GDS_GWS_RESET0__RESOURCE14_RESET__SHIFT                                                               0xe
17301 #define GDS_GWS_RESET0__RESOURCE15_RESET__SHIFT                                                               0xf
17302 #define GDS_GWS_RESET0__RESOURCE16_RESET__SHIFT                                                               0x10
17303 #define GDS_GWS_RESET0__RESOURCE17_RESET__SHIFT                                                               0x11
17304 #define GDS_GWS_RESET0__RESOURCE18_RESET__SHIFT                                                               0x12
17305 #define GDS_GWS_RESET0__RESOURCE19_RESET__SHIFT                                                               0x13
17306 #define GDS_GWS_RESET0__RESOURCE20_RESET__SHIFT                                                               0x14
17307 #define GDS_GWS_RESET0__RESOURCE21_RESET__SHIFT                                                               0x15
17308 #define GDS_GWS_RESET0__RESOURCE22_RESET__SHIFT                                                               0x16
17309 #define GDS_GWS_RESET0__RESOURCE23_RESET__SHIFT                                                               0x17
17310 #define GDS_GWS_RESET0__RESOURCE24_RESET__SHIFT                                                               0x18
17311 #define GDS_GWS_RESET0__RESOURCE25_RESET__SHIFT                                                               0x19
17312 #define GDS_GWS_RESET0__RESOURCE26_RESET__SHIFT                                                               0x1a
17313 #define GDS_GWS_RESET0__RESOURCE27_RESET__SHIFT                                                               0x1b
17314 #define GDS_GWS_RESET0__RESOURCE28_RESET__SHIFT                                                               0x1c
17315 #define GDS_GWS_RESET0__RESOURCE29_RESET__SHIFT                                                               0x1d
17316 #define GDS_GWS_RESET0__RESOURCE30_RESET__SHIFT                                                               0x1e
17317 #define GDS_GWS_RESET0__RESOURCE31_RESET__SHIFT                                                               0x1f
17318 #define GDS_GWS_RESET0__RESOURCE0_RESET_MASK                                                                  0x00000001L
17319 #define GDS_GWS_RESET0__RESOURCE1_RESET_MASK                                                                  0x00000002L
17320 #define GDS_GWS_RESET0__RESOURCE2_RESET_MASK                                                                  0x00000004L
17321 #define GDS_GWS_RESET0__RESOURCE3_RESET_MASK                                                                  0x00000008L
17322 #define GDS_GWS_RESET0__RESOURCE4_RESET_MASK                                                                  0x00000010L
17323 #define GDS_GWS_RESET0__RESOURCE5_RESET_MASK                                                                  0x00000020L
17324 #define GDS_GWS_RESET0__RESOURCE6_RESET_MASK                                                                  0x00000040L
17325 #define GDS_GWS_RESET0__RESOURCE7_RESET_MASK                                                                  0x00000080L
17326 #define GDS_GWS_RESET0__RESOURCE8_RESET_MASK                                                                  0x00000100L
17327 #define GDS_GWS_RESET0__RESOURCE9_RESET_MASK                                                                  0x00000200L
17328 #define GDS_GWS_RESET0__RESOURCE10_RESET_MASK                                                                 0x00000400L
17329 #define GDS_GWS_RESET0__RESOURCE11_RESET_MASK                                                                 0x00000800L
17330 #define GDS_GWS_RESET0__RESOURCE12_RESET_MASK                                                                 0x00001000L
17331 #define GDS_GWS_RESET0__RESOURCE13_RESET_MASK                                                                 0x00002000L
17332 #define GDS_GWS_RESET0__RESOURCE14_RESET_MASK                                                                 0x00004000L
17333 #define GDS_GWS_RESET0__RESOURCE15_RESET_MASK                                                                 0x00008000L
17334 #define GDS_GWS_RESET0__RESOURCE16_RESET_MASK                                                                 0x00010000L
17335 #define GDS_GWS_RESET0__RESOURCE17_RESET_MASK                                                                 0x00020000L
17336 #define GDS_GWS_RESET0__RESOURCE18_RESET_MASK                                                                 0x00040000L
17337 #define GDS_GWS_RESET0__RESOURCE19_RESET_MASK                                                                 0x00080000L
17338 #define GDS_GWS_RESET0__RESOURCE20_RESET_MASK                                                                 0x00100000L
17339 #define GDS_GWS_RESET0__RESOURCE21_RESET_MASK                                                                 0x00200000L
17340 #define GDS_GWS_RESET0__RESOURCE22_RESET_MASK                                                                 0x00400000L
17341 #define GDS_GWS_RESET0__RESOURCE23_RESET_MASK                                                                 0x00800000L
17342 #define GDS_GWS_RESET0__RESOURCE24_RESET_MASK                                                                 0x01000000L
17343 #define GDS_GWS_RESET0__RESOURCE25_RESET_MASK                                                                 0x02000000L
17344 #define GDS_GWS_RESET0__RESOURCE26_RESET_MASK                                                                 0x04000000L
17345 #define GDS_GWS_RESET0__RESOURCE27_RESET_MASK                                                                 0x08000000L
17346 #define GDS_GWS_RESET0__RESOURCE28_RESET_MASK                                                                 0x10000000L
17347 #define GDS_GWS_RESET0__RESOURCE29_RESET_MASK                                                                 0x20000000L
17348 #define GDS_GWS_RESET0__RESOURCE30_RESET_MASK                                                                 0x40000000L
17349 #define GDS_GWS_RESET0__RESOURCE31_RESET_MASK                                                                 0x80000000L
17350 //GDS_GWS_RESET1
17351 #define GDS_GWS_RESET1__RESOURCE32_RESET__SHIFT                                                               0x0
17352 #define GDS_GWS_RESET1__RESOURCE33_RESET__SHIFT                                                               0x1
17353 #define GDS_GWS_RESET1__RESOURCE34_RESET__SHIFT                                                               0x2
17354 #define GDS_GWS_RESET1__RESOURCE35_RESET__SHIFT                                                               0x3
17355 #define GDS_GWS_RESET1__RESOURCE36_RESET__SHIFT                                                               0x4
17356 #define GDS_GWS_RESET1__RESOURCE37_RESET__SHIFT                                                               0x5
17357 #define GDS_GWS_RESET1__RESOURCE38_RESET__SHIFT                                                               0x6
17358 #define GDS_GWS_RESET1__RESOURCE39_RESET__SHIFT                                                               0x7
17359 #define GDS_GWS_RESET1__RESOURCE40_RESET__SHIFT                                                               0x8
17360 #define GDS_GWS_RESET1__RESOURCE41_RESET__SHIFT                                                               0x9
17361 #define GDS_GWS_RESET1__RESOURCE42_RESET__SHIFT                                                               0xa
17362 #define GDS_GWS_RESET1__RESOURCE43_RESET__SHIFT                                                               0xb
17363 #define GDS_GWS_RESET1__RESOURCE44_RESET__SHIFT                                                               0xc
17364 #define GDS_GWS_RESET1__RESOURCE45_RESET__SHIFT                                                               0xd
17365 #define GDS_GWS_RESET1__RESOURCE46_RESET__SHIFT                                                               0xe
17366 #define GDS_GWS_RESET1__RESOURCE47_RESET__SHIFT                                                               0xf
17367 #define GDS_GWS_RESET1__RESOURCE48_RESET__SHIFT                                                               0x10
17368 #define GDS_GWS_RESET1__RESOURCE49_RESET__SHIFT                                                               0x11
17369 #define GDS_GWS_RESET1__RESOURCE50_RESET__SHIFT                                                               0x12
17370 #define GDS_GWS_RESET1__RESOURCE51_RESET__SHIFT                                                               0x13
17371 #define GDS_GWS_RESET1__RESOURCE52_RESET__SHIFT                                                               0x14
17372 #define GDS_GWS_RESET1__RESOURCE53_RESET__SHIFT                                                               0x15
17373 #define GDS_GWS_RESET1__RESOURCE54_RESET__SHIFT                                                               0x16
17374 #define GDS_GWS_RESET1__RESOURCE55_RESET__SHIFT                                                               0x17
17375 #define GDS_GWS_RESET1__RESOURCE56_RESET__SHIFT                                                               0x18
17376 #define GDS_GWS_RESET1__RESOURCE57_RESET__SHIFT                                                               0x19
17377 #define GDS_GWS_RESET1__RESOURCE58_RESET__SHIFT                                                               0x1a
17378 #define GDS_GWS_RESET1__RESOURCE59_RESET__SHIFT                                                               0x1b
17379 #define GDS_GWS_RESET1__RESOURCE60_RESET__SHIFT                                                               0x1c
17380 #define GDS_GWS_RESET1__RESOURCE61_RESET__SHIFT                                                               0x1d
17381 #define GDS_GWS_RESET1__RESOURCE62_RESET__SHIFT                                                               0x1e
17382 #define GDS_GWS_RESET1__RESOURCE63_RESET__SHIFT                                                               0x1f
17383 #define GDS_GWS_RESET1__RESOURCE32_RESET_MASK                                                                 0x00000001L
17384 #define GDS_GWS_RESET1__RESOURCE33_RESET_MASK                                                                 0x00000002L
17385 #define GDS_GWS_RESET1__RESOURCE34_RESET_MASK                                                                 0x00000004L
17386 #define GDS_GWS_RESET1__RESOURCE35_RESET_MASK                                                                 0x00000008L
17387 #define GDS_GWS_RESET1__RESOURCE36_RESET_MASK                                                                 0x00000010L
17388 #define GDS_GWS_RESET1__RESOURCE37_RESET_MASK                                                                 0x00000020L
17389 #define GDS_GWS_RESET1__RESOURCE38_RESET_MASK                                                                 0x00000040L
17390 #define GDS_GWS_RESET1__RESOURCE39_RESET_MASK                                                                 0x00000080L
17391 #define GDS_GWS_RESET1__RESOURCE40_RESET_MASK                                                                 0x00000100L
17392 #define GDS_GWS_RESET1__RESOURCE41_RESET_MASK                                                                 0x00000200L
17393 #define GDS_GWS_RESET1__RESOURCE42_RESET_MASK                                                                 0x00000400L
17394 #define GDS_GWS_RESET1__RESOURCE43_RESET_MASK                                                                 0x00000800L
17395 #define GDS_GWS_RESET1__RESOURCE44_RESET_MASK                                                                 0x00001000L
17396 #define GDS_GWS_RESET1__RESOURCE45_RESET_MASK                                                                 0x00002000L
17397 #define GDS_GWS_RESET1__RESOURCE46_RESET_MASK                                                                 0x00004000L
17398 #define GDS_GWS_RESET1__RESOURCE47_RESET_MASK                                                                 0x00008000L
17399 #define GDS_GWS_RESET1__RESOURCE48_RESET_MASK                                                                 0x00010000L
17400 #define GDS_GWS_RESET1__RESOURCE49_RESET_MASK                                                                 0x00020000L
17401 #define GDS_GWS_RESET1__RESOURCE50_RESET_MASK                                                                 0x00040000L
17402 #define GDS_GWS_RESET1__RESOURCE51_RESET_MASK                                                                 0x00080000L
17403 #define GDS_GWS_RESET1__RESOURCE52_RESET_MASK                                                                 0x00100000L
17404 #define GDS_GWS_RESET1__RESOURCE53_RESET_MASK                                                                 0x00200000L
17405 #define GDS_GWS_RESET1__RESOURCE54_RESET_MASK                                                                 0x00400000L
17406 #define GDS_GWS_RESET1__RESOURCE55_RESET_MASK                                                                 0x00800000L
17407 #define GDS_GWS_RESET1__RESOURCE56_RESET_MASK                                                                 0x01000000L
17408 #define GDS_GWS_RESET1__RESOURCE57_RESET_MASK                                                                 0x02000000L
17409 #define GDS_GWS_RESET1__RESOURCE58_RESET_MASK                                                                 0x04000000L
17410 #define GDS_GWS_RESET1__RESOURCE59_RESET_MASK                                                                 0x08000000L
17411 #define GDS_GWS_RESET1__RESOURCE60_RESET_MASK                                                                 0x10000000L
17412 #define GDS_GWS_RESET1__RESOURCE61_RESET_MASK                                                                 0x20000000L
17413 #define GDS_GWS_RESET1__RESOURCE62_RESET_MASK                                                                 0x40000000L
17414 #define GDS_GWS_RESET1__RESOURCE63_RESET_MASK                                                                 0x80000000L
17415 //GDS_GWS_RESOURCE_RESET
17416 #define GDS_GWS_RESOURCE_RESET__RESET__SHIFT                                                                  0x0
17417 #define GDS_GWS_RESOURCE_RESET__RESOURCE_ID__SHIFT                                                            0x8
17418 #define GDS_GWS_RESOURCE_RESET__RESET_MASK                                                                    0x00000001L
17419 #define GDS_GWS_RESOURCE_RESET__RESOURCE_ID_MASK                                                              0x0000FF00L
17420 //GDS_COMPUTE_MAX_WAVE_ID
17421 #define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT                                                           0x0
17422 #define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID_MASK                                                             0x00000FFFL
17423 //GDS_OA_RESET_MASK
17424 #define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET__SHIFT                                                       0x0
17425 #define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET__SHIFT                                                       0x1
17426 #define GDS_OA_RESET_MASK__ME0_CS_RESET__SHIFT                                                                0x2
17427 #define GDS_OA_RESET_MASK__ME0_GFXHP3D_GS_RESET__SHIFT                                                        0x3
17428 #define GDS_OA_RESET_MASK__ME1_PIPE0_RESET__SHIFT                                                             0x4
17429 #define GDS_OA_RESET_MASK__ME1_PIPE1_RESET__SHIFT                                                             0x5
17430 #define GDS_OA_RESET_MASK__ME1_PIPE2_RESET__SHIFT                                                             0x6
17431 #define GDS_OA_RESET_MASK__ME1_PIPE3_RESET__SHIFT                                                             0x7
17432 #define GDS_OA_RESET_MASK__ME2_PIPE0_RESET__SHIFT                                                             0x8
17433 #define GDS_OA_RESET_MASK__ME2_PIPE1_RESET__SHIFT                                                             0x9
17434 #define GDS_OA_RESET_MASK__ME2_PIPE2_RESET__SHIFT                                                             0xa
17435 #define GDS_OA_RESET_MASK__ME2_PIPE3_RESET__SHIFT                                                             0xb
17436 #define GDS_OA_RESET_MASK__UNUSED1__SHIFT                                                                     0xc
17437 #define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET_MASK                                                         0x00000001L
17438 #define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET_MASK                                                         0x00000002L
17439 #define GDS_OA_RESET_MASK__ME0_CS_RESET_MASK                                                                  0x00000004L
17440 #define GDS_OA_RESET_MASK__ME0_GFXHP3D_GS_RESET_MASK                                                          0x00000008L
17441 #define GDS_OA_RESET_MASK__ME1_PIPE0_RESET_MASK                                                               0x00000010L
17442 #define GDS_OA_RESET_MASK__ME1_PIPE1_RESET_MASK                                                               0x00000020L
17443 #define GDS_OA_RESET_MASK__ME1_PIPE2_RESET_MASK                                                               0x00000040L
17444 #define GDS_OA_RESET_MASK__ME1_PIPE3_RESET_MASK                                                               0x00000080L
17445 #define GDS_OA_RESET_MASK__ME2_PIPE0_RESET_MASK                                                               0x00000100L
17446 #define GDS_OA_RESET_MASK__ME2_PIPE1_RESET_MASK                                                               0x00000200L
17447 #define GDS_OA_RESET_MASK__ME2_PIPE2_RESET_MASK                                                               0x00000400L
17448 #define GDS_OA_RESET_MASK__ME2_PIPE3_RESET_MASK                                                               0x00000800L
17449 #define GDS_OA_RESET_MASK__UNUSED1_MASK                                                                       0xFFFFF000L
17450 //GDS_OA_RESET
17451 #define GDS_OA_RESET__RESET__SHIFT                                                                            0x0
17452 #define GDS_OA_RESET__PIPE_ID__SHIFT                                                                          0x8
17453 #define GDS_OA_RESET__RESET_MASK                                                                              0x00000001L
17454 #define GDS_OA_RESET__PIPE_ID_MASK                                                                            0x0000FF00L
17455 //GDS_ENHANCE
17456 #define GDS_ENHANCE__MISC__SHIFT                                                                              0x0
17457 #define GDS_ENHANCE__AUTO_INC_INDEX__SHIFT                                                                    0x10
17458 #define GDS_ENHANCE__CGPG_RESTORE__SHIFT                                                                      0x11
17459 #define GDS_ENHANCE__RD_BUF_TAG_MISS__SHIFT                                                                   0x12
17460 #define GDS_ENHANCE__GDSA_PC_CGTS_DIS__SHIFT                                                                  0x13
17461 #define GDS_ENHANCE__GDSO_PC_CGTS_DIS__SHIFT                                                                  0x14
17462 #define GDS_ENHANCE__WD_GDS_CSB_OVERRIDE__SHIFT                                                               0x15
17463 #define GDS_ENHANCE__GDS_CLK_ENHANCE_DIS__SHIFT                                                               0x16
17464 #define GDS_ENHANCE__DS_MEM_CLK_GATE_DIS__SHIFT                                                               0x17
17465 #define GDS_ENHANCE__UNUSED__SHIFT                                                                            0x18
17466 #define GDS_ENHANCE__MISC_MASK                                                                                0x0000FFFFL
17467 #define GDS_ENHANCE__AUTO_INC_INDEX_MASK                                                                      0x00010000L
17468 #define GDS_ENHANCE__CGPG_RESTORE_MASK                                                                        0x00020000L
17469 #define GDS_ENHANCE__RD_BUF_TAG_MISS_MASK                                                                     0x00040000L
17470 #define GDS_ENHANCE__GDSA_PC_CGTS_DIS_MASK                                                                    0x00080000L
17471 #define GDS_ENHANCE__GDSO_PC_CGTS_DIS_MASK                                                                    0x00100000L
17472 #define GDS_ENHANCE__WD_GDS_CSB_OVERRIDE_MASK                                                                 0x00200000L
17473 #define GDS_ENHANCE__GDS_CLK_ENHANCE_DIS_MASK                                                                 0x00400000L
17474 #define GDS_ENHANCE__DS_MEM_CLK_GATE_DIS_MASK                                                                 0x00800000L
17475 #define GDS_ENHANCE__UNUSED_MASK                                                                              0xFF000000L
17476 //GDS_OA_CGPG_RESTORE
17477 #define GDS_OA_CGPG_RESTORE__VMID__SHIFT                                                                      0x0
17478 #define GDS_OA_CGPG_RESTORE__MEID__SHIFT                                                                      0x8
17479 #define GDS_OA_CGPG_RESTORE__PIPEID__SHIFT                                                                    0xc
17480 #define GDS_OA_CGPG_RESTORE__QUEUEID__SHIFT                                                                   0x10
17481 #define GDS_OA_CGPG_RESTORE__UNUSED__SHIFT                                                                    0x14
17482 #define GDS_OA_CGPG_RESTORE__VMID_MASK                                                                        0x000000FFL
17483 #define GDS_OA_CGPG_RESTORE__MEID_MASK                                                                        0x00000F00L
17484 #define GDS_OA_CGPG_RESTORE__PIPEID_MASK                                                                      0x0000F000L
17485 #define GDS_OA_CGPG_RESTORE__QUEUEID_MASK                                                                     0x000F0000L
17486 #define GDS_OA_CGPG_RESTORE__UNUSED_MASK                                                                      0xFFF00000L
17487 //GDS_CS_CTXSW_STATUS
17488 #define GDS_CS_CTXSW_STATUS__R__SHIFT                                                                         0x0
17489 #define GDS_CS_CTXSW_STATUS__W__SHIFT                                                                         0x1
17490 #define GDS_CS_CTXSW_STATUS__UNUSED__SHIFT                                                                    0x2
17491 #define GDS_CS_CTXSW_STATUS__R_MASK                                                                           0x00000001L
17492 #define GDS_CS_CTXSW_STATUS__W_MASK                                                                           0x00000002L
17493 #define GDS_CS_CTXSW_STATUS__UNUSED_MASK                                                                      0xFFFFFFFCL
17494 //GDS_CS_CTXSW_CNT0
17495 #define GDS_CS_CTXSW_CNT0__UPDN__SHIFT                                                                        0x0
17496 #define GDS_CS_CTXSW_CNT0__PTR__SHIFT                                                                         0x10
17497 #define GDS_CS_CTXSW_CNT0__UPDN_MASK                                                                          0x0000FFFFL
17498 #define GDS_CS_CTXSW_CNT0__PTR_MASK                                                                           0xFFFF0000L
17499 //GDS_CS_CTXSW_CNT1
17500 #define GDS_CS_CTXSW_CNT1__UPDN__SHIFT                                                                        0x0
17501 #define GDS_CS_CTXSW_CNT1__PTR__SHIFT                                                                         0x10
17502 #define GDS_CS_CTXSW_CNT1__UPDN_MASK                                                                          0x0000FFFFL
17503 #define GDS_CS_CTXSW_CNT1__PTR_MASK                                                                           0xFFFF0000L
17504 //GDS_CS_CTXSW_CNT2
17505 #define GDS_CS_CTXSW_CNT2__UPDN__SHIFT                                                                        0x0
17506 #define GDS_CS_CTXSW_CNT2__PTR__SHIFT                                                                         0x10
17507 #define GDS_CS_CTXSW_CNT2__UPDN_MASK                                                                          0x0000FFFFL
17508 #define GDS_CS_CTXSW_CNT2__PTR_MASK                                                                           0xFFFF0000L
17509 //GDS_CS_CTXSW_CNT3
17510 #define GDS_CS_CTXSW_CNT3__UPDN__SHIFT                                                                        0x0
17511 #define GDS_CS_CTXSW_CNT3__PTR__SHIFT                                                                         0x10
17512 #define GDS_CS_CTXSW_CNT3__UPDN_MASK                                                                          0x0000FFFFL
17513 #define GDS_CS_CTXSW_CNT3__PTR_MASK                                                                           0xFFFF0000L
17514 //GDS_GFX_CTXSW_STATUS
17515 #define GDS_GFX_CTXSW_STATUS__R__SHIFT                                                                        0x0
17516 #define GDS_GFX_CTXSW_STATUS__W__SHIFT                                                                        0x1
17517 #define GDS_GFX_CTXSW_STATUS__UNUSED__SHIFT                                                                   0x2
17518 #define GDS_GFX_CTXSW_STATUS__R_MASK                                                                          0x00000001L
17519 #define GDS_GFX_CTXSW_STATUS__W_MASK                                                                          0x00000002L
17520 #define GDS_GFX_CTXSW_STATUS__UNUSED_MASK                                                                     0xFFFFFFFCL
17521 //GDS_VS_CTXSW_CNT0
17522 #define GDS_VS_CTXSW_CNT0__UPDN__SHIFT                                                                        0x0
17523 #define GDS_VS_CTXSW_CNT0__PTR__SHIFT                                                                         0x10
17524 #define GDS_VS_CTXSW_CNT0__UPDN_MASK                                                                          0x0000FFFFL
17525 #define GDS_VS_CTXSW_CNT0__PTR_MASK                                                                           0xFFFF0000L
17526 //GDS_VS_CTXSW_CNT1
17527 #define GDS_VS_CTXSW_CNT1__UPDN__SHIFT                                                                        0x0
17528 #define GDS_VS_CTXSW_CNT1__PTR__SHIFT                                                                         0x10
17529 #define GDS_VS_CTXSW_CNT1__UPDN_MASK                                                                          0x0000FFFFL
17530 #define GDS_VS_CTXSW_CNT1__PTR_MASK                                                                           0xFFFF0000L
17531 //GDS_VS_CTXSW_CNT2
17532 #define GDS_VS_CTXSW_CNT2__UPDN__SHIFT                                                                        0x0
17533 #define GDS_VS_CTXSW_CNT2__PTR__SHIFT                                                                         0x10
17534 #define GDS_VS_CTXSW_CNT2__UPDN_MASK                                                                          0x0000FFFFL
17535 #define GDS_VS_CTXSW_CNT2__PTR_MASK                                                                           0xFFFF0000L
17536 //GDS_VS_CTXSW_CNT3
17537 #define GDS_VS_CTXSW_CNT3__UPDN__SHIFT                                                                        0x0
17538 #define GDS_VS_CTXSW_CNT3__PTR__SHIFT                                                                         0x10
17539 #define GDS_VS_CTXSW_CNT3__UPDN_MASK                                                                          0x0000FFFFL
17540 #define GDS_VS_CTXSW_CNT3__PTR_MASK                                                                           0xFFFF0000L
17541 //GDS_PS0_CTXSW_CNT0
17542 #define GDS_PS0_CTXSW_CNT0__UPDN__SHIFT                                                                       0x0
17543 #define GDS_PS0_CTXSW_CNT0__PTR__SHIFT                                                                        0x10
17544 #define GDS_PS0_CTXSW_CNT0__UPDN_MASK                                                                         0x0000FFFFL
17545 #define GDS_PS0_CTXSW_CNT0__PTR_MASK                                                                          0xFFFF0000L
17546 //GDS_PS0_CTXSW_CNT1
17547 #define GDS_PS0_CTXSW_CNT1__UPDN__SHIFT                                                                       0x0
17548 #define GDS_PS0_CTXSW_CNT1__PTR__SHIFT                                                                        0x10
17549 #define GDS_PS0_CTXSW_CNT1__UPDN_MASK                                                                         0x0000FFFFL
17550 #define GDS_PS0_CTXSW_CNT1__PTR_MASK                                                                          0xFFFF0000L
17551 //GDS_PS0_CTXSW_CNT2
17552 #define GDS_PS0_CTXSW_CNT2__UPDN__SHIFT                                                                       0x0
17553 #define GDS_PS0_CTXSW_CNT2__PTR__SHIFT                                                                        0x10
17554 #define GDS_PS0_CTXSW_CNT2__UPDN_MASK                                                                         0x0000FFFFL
17555 #define GDS_PS0_CTXSW_CNT2__PTR_MASK                                                                          0xFFFF0000L
17556 //GDS_PS0_CTXSW_CNT3
17557 #define GDS_PS0_CTXSW_CNT3__UPDN__SHIFT                                                                       0x0
17558 #define GDS_PS0_CTXSW_CNT3__PTR__SHIFT                                                                        0x10
17559 #define GDS_PS0_CTXSW_CNT3__UPDN_MASK                                                                         0x0000FFFFL
17560 #define GDS_PS0_CTXSW_CNT3__PTR_MASK                                                                          0xFFFF0000L
17561 //GDS_PS1_CTXSW_CNT0
17562 #define GDS_PS1_CTXSW_CNT0__UPDN__SHIFT                                                                       0x0
17563 #define GDS_PS1_CTXSW_CNT0__PTR__SHIFT                                                                        0x10
17564 #define GDS_PS1_CTXSW_CNT0__UPDN_MASK                                                                         0x0000FFFFL
17565 #define GDS_PS1_CTXSW_CNT0__PTR_MASK                                                                          0xFFFF0000L
17566 //GDS_PS1_CTXSW_CNT1
17567 #define GDS_PS1_CTXSW_CNT1__UPDN__SHIFT                                                                       0x0
17568 #define GDS_PS1_CTXSW_CNT1__PTR__SHIFT                                                                        0x10
17569 #define GDS_PS1_CTXSW_CNT1__UPDN_MASK                                                                         0x0000FFFFL
17570 #define GDS_PS1_CTXSW_CNT1__PTR_MASK                                                                          0xFFFF0000L
17571 //GDS_PS1_CTXSW_CNT2
17572 #define GDS_PS1_CTXSW_CNT2__UPDN__SHIFT                                                                       0x0
17573 #define GDS_PS1_CTXSW_CNT2__PTR__SHIFT                                                                        0x10
17574 #define GDS_PS1_CTXSW_CNT2__UPDN_MASK                                                                         0x0000FFFFL
17575 #define GDS_PS1_CTXSW_CNT2__PTR_MASK                                                                          0xFFFF0000L
17576 //GDS_PS1_CTXSW_CNT3
17577 #define GDS_PS1_CTXSW_CNT3__UPDN__SHIFT                                                                       0x0
17578 #define GDS_PS1_CTXSW_CNT3__PTR__SHIFT                                                                        0x10
17579 #define GDS_PS1_CTXSW_CNT3__UPDN_MASK                                                                         0x0000FFFFL
17580 #define GDS_PS1_CTXSW_CNT3__PTR_MASK                                                                          0xFFFF0000L
17581 //GDS_PS2_CTXSW_CNT0
17582 #define GDS_PS2_CTXSW_CNT0__UPDN__SHIFT                                                                       0x0
17583 #define GDS_PS2_CTXSW_CNT0__PTR__SHIFT                                                                        0x10
17584 #define GDS_PS2_CTXSW_CNT0__UPDN_MASK                                                                         0x0000FFFFL
17585 #define GDS_PS2_CTXSW_CNT0__PTR_MASK                                                                          0xFFFF0000L
17586 //GDS_PS2_CTXSW_CNT1
17587 #define GDS_PS2_CTXSW_CNT1__UPDN__SHIFT                                                                       0x0
17588 #define GDS_PS2_CTXSW_CNT1__PTR__SHIFT                                                                        0x10
17589 #define GDS_PS2_CTXSW_CNT1__UPDN_MASK                                                                         0x0000FFFFL
17590 #define GDS_PS2_CTXSW_CNT1__PTR_MASK                                                                          0xFFFF0000L
17591 //GDS_PS2_CTXSW_CNT2
17592 #define GDS_PS2_CTXSW_CNT2__UPDN__SHIFT                                                                       0x0
17593 #define GDS_PS2_CTXSW_CNT2__PTR__SHIFT                                                                        0x10
17594 #define GDS_PS2_CTXSW_CNT2__UPDN_MASK                                                                         0x0000FFFFL
17595 #define GDS_PS2_CTXSW_CNT2__PTR_MASK                                                                          0xFFFF0000L
17596 //GDS_PS2_CTXSW_CNT3
17597 #define GDS_PS2_CTXSW_CNT3__UPDN__SHIFT                                                                       0x0
17598 #define GDS_PS2_CTXSW_CNT3__PTR__SHIFT                                                                        0x10
17599 #define GDS_PS2_CTXSW_CNT3__UPDN_MASK                                                                         0x0000FFFFL
17600 #define GDS_PS2_CTXSW_CNT3__PTR_MASK                                                                          0xFFFF0000L
17601 //GDS_PS3_CTXSW_CNT0
17602 #define GDS_PS3_CTXSW_CNT0__UPDN__SHIFT                                                                       0x0
17603 #define GDS_PS3_CTXSW_CNT0__PTR__SHIFT                                                                        0x10
17604 #define GDS_PS3_CTXSW_CNT0__UPDN_MASK                                                                         0x0000FFFFL
17605 #define GDS_PS3_CTXSW_CNT0__PTR_MASK                                                                          0xFFFF0000L
17606 //GDS_PS3_CTXSW_CNT1
17607 #define GDS_PS3_CTXSW_CNT1__UPDN__SHIFT                                                                       0x0
17608 #define GDS_PS3_CTXSW_CNT1__PTR__SHIFT                                                                        0x10
17609 #define GDS_PS3_CTXSW_CNT1__UPDN_MASK                                                                         0x0000FFFFL
17610 #define GDS_PS3_CTXSW_CNT1__PTR_MASK                                                                          0xFFFF0000L
17611 //GDS_PS3_CTXSW_CNT2
17612 #define GDS_PS3_CTXSW_CNT2__UPDN__SHIFT                                                                       0x0
17613 #define GDS_PS3_CTXSW_CNT2__PTR__SHIFT                                                                        0x10
17614 #define GDS_PS3_CTXSW_CNT2__UPDN_MASK                                                                         0x0000FFFFL
17615 #define GDS_PS3_CTXSW_CNT2__PTR_MASK                                                                          0xFFFF0000L
17616 //GDS_PS3_CTXSW_CNT3
17617 #define GDS_PS3_CTXSW_CNT3__UPDN__SHIFT                                                                       0x0
17618 #define GDS_PS3_CTXSW_CNT3__PTR__SHIFT                                                                        0x10
17619 #define GDS_PS3_CTXSW_CNT3__UPDN_MASK                                                                         0x0000FFFFL
17620 #define GDS_PS3_CTXSW_CNT3__PTR_MASK                                                                          0xFFFF0000L
17621 //GDS_PS4_CTXSW_CNT0
17622 #define GDS_PS4_CTXSW_CNT0__UPDN__SHIFT                                                                       0x0
17623 #define GDS_PS4_CTXSW_CNT0__PTR__SHIFT                                                                        0x10
17624 #define GDS_PS4_CTXSW_CNT0__UPDN_MASK                                                                         0x0000FFFFL
17625 #define GDS_PS4_CTXSW_CNT0__PTR_MASK                                                                          0xFFFF0000L
17626 //GDS_PS4_CTXSW_CNT1
17627 #define GDS_PS4_CTXSW_CNT1__UPDN__SHIFT                                                                       0x0
17628 #define GDS_PS4_CTXSW_CNT1__PTR__SHIFT                                                                        0x10
17629 #define GDS_PS4_CTXSW_CNT1__UPDN_MASK                                                                         0x0000FFFFL
17630 #define GDS_PS4_CTXSW_CNT1__PTR_MASK                                                                          0xFFFF0000L
17631 //GDS_PS4_CTXSW_CNT2
17632 #define GDS_PS4_CTXSW_CNT2__UPDN__SHIFT                                                                       0x0
17633 #define GDS_PS4_CTXSW_CNT2__PTR__SHIFT                                                                        0x10
17634 #define GDS_PS4_CTXSW_CNT2__UPDN_MASK                                                                         0x0000FFFFL
17635 #define GDS_PS4_CTXSW_CNT2__PTR_MASK                                                                          0xFFFF0000L
17636 //GDS_PS4_CTXSW_CNT3
17637 #define GDS_PS4_CTXSW_CNT3__UPDN__SHIFT                                                                       0x0
17638 #define GDS_PS4_CTXSW_CNT3__PTR__SHIFT                                                                        0x10
17639 #define GDS_PS4_CTXSW_CNT3__UPDN_MASK                                                                         0x0000FFFFL
17640 #define GDS_PS4_CTXSW_CNT3__PTR_MASK                                                                          0xFFFF0000L
17641 //GDS_PS5_CTXSW_CNT0
17642 #define GDS_PS5_CTXSW_CNT0__UPDN__SHIFT                                                                       0x0
17643 #define GDS_PS5_CTXSW_CNT0__PTR__SHIFT                                                                        0x10
17644 #define GDS_PS5_CTXSW_CNT0__UPDN_MASK                                                                         0x0000FFFFL
17645 #define GDS_PS5_CTXSW_CNT0__PTR_MASK                                                                          0xFFFF0000L
17646 //GDS_PS5_CTXSW_CNT1
17647 #define GDS_PS5_CTXSW_CNT1__UPDN__SHIFT                                                                       0x0
17648 #define GDS_PS5_CTXSW_CNT1__PTR__SHIFT                                                                        0x10
17649 #define GDS_PS5_CTXSW_CNT1__UPDN_MASK                                                                         0x0000FFFFL
17650 #define GDS_PS5_CTXSW_CNT1__PTR_MASK                                                                          0xFFFF0000L
17651 //GDS_PS5_CTXSW_CNT2
17652 #define GDS_PS5_CTXSW_CNT2__UPDN__SHIFT                                                                       0x0
17653 #define GDS_PS5_CTXSW_CNT2__PTR__SHIFT                                                                        0x10
17654 #define GDS_PS5_CTXSW_CNT2__UPDN_MASK                                                                         0x0000FFFFL
17655 #define GDS_PS5_CTXSW_CNT2__PTR_MASK                                                                          0xFFFF0000L
17656 //GDS_PS5_CTXSW_CNT3
17657 #define GDS_PS5_CTXSW_CNT3__UPDN__SHIFT                                                                       0x0
17658 #define GDS_PS5_CTXSW_CNT3__PTR__SHIFT                                                                        0x10
17659 #define GDS_PS5_CTXSW_CNT3__UPDN_MASK                                                                         0x0000FFFFL
17660 #define GDS_PS5_CTXSW_CNT3__PTR_MASK                                                                          0xFFFF0000L
17661 //GDS_PS6_CTXSW_CNT0
17662 #define GDS_PS6_CTXSW_CNT0__UPDN__SHIFT                                                                       0x0
17663 #define GDS_PS6_CTXSW_CNT0__PTR__SHIFT                                                                        0x10
17664 #define GDS_PS6_CTXSW_CNT0__UPDN_MASK                                                                         0x0000FFFFL
17665 #define GDS_PS6_CTXSW_CNT0__PTR_MASK                                                                          0xFFFF0000L
17666 //GDS_PS6_CTXSW_CNT1
17667 #define GDS_PS6_CTXSW_CNT1__UPDN__SHIFT                                                                       0x0
17668 #define GDS_PS6_CTXSW_CNT1__PTR__SHIFT                                                                        0x10
17669 #define GDS_PS6_CTXSW_CNT1__UPDN_MASK                                                                         0x0000FFFFL
17670 #define GDS_PS6_CTXSW_CNT1__PTR_MASK                                                                          0xFFFF0000L
17671 //GDS_PS6_CTXSW_CNT2
17672 #define GDS_PS6_CTXSW_CNT2__UPDN__SHIFT                                                                       0x0
17673 #define GDS_PS6_CTXSW_CNT2__PTR__SHIFT                                                                        0x10
17674 #define GDS_PS6_CTXSW_CNT2__UPDN_MASK                                                                         0x0000FFFFL
17675 #define GDS_PS6_CTXSW_CNT2__PTR_MASK                                                                          0xFFFF0000L
17676 //GDS_PS6_CTXSW_CNT3
17677 #define GDS_PS6_CTXSW_CNT3__UPDN__SHIFT                                                                       0x0
17678 #define GDS_PS6_CTXSW_CNT3__PTR__SHIFT                                                                        0x10
17679 #define GDS_PS6_CTXSW_CNT3__UPDN_MASK                                                                         0x0000FFFFL
17680 #define GDS_PS6_CTXSW_CNT3__PTR_MASK                                                                          0xFFFF0000L
17681 //GDS_PS7_CTXSW_CNT0
17682 #define GDS_PS7_CTXSW_CNT0__UPDN__SHIFT                                                                       0x0
17683 #define GDS_PS7_CTXSW_CNT0__PTR__SHIFT                                                                        0x10
17684 #define GDS_PS7_CTXSW_CNT0__UPDN_MASK                                                                         0x0000FFFFL
17685 #define GDS_PS7_CTXSW_CNT0__PTR_MASK                                                                          0xFFFF0000L
17686 //GDS_PS7_CTXSW_CNT1
17687 #define GDS_PS7_CTXSW_CNT1__UPDN__SHIFT                                                                       0x0
17688 #define GDS_PS7_CTXSW_CNT1__PTR__SHIFT                                                                        0x10
17689 #define GDS_PS7_CTXSW_CNT1__UPDN_MASK                                                                         0x0000FFFFL
17690 #define GDS_PS7_CTXSW_CNT1__PTR_MASK                                                                          0xFFFF0000L
17691 //GDS_PS7_CTXSW_CNT2
17692 #define GDS_PS7_CTXSW_CNT2__UPDN__SHIFT                                                                       0x0
17693 #define GDS_PS7_CTXSW_CNT2__PTR__SHIFT                                                                        0x10
17694 #define GDS_PS7_CTXSW_CNT2__UPDN_MASK                                                                         0x0000FFFFL
17695 #define GDS_PS7_CTXSW_CNT2__PTR_MASK                                                                          0xFFFF0000L
17696 //GDS_PS7_CTXSW_CNT3
17697 #define GDS_PS7_CTXSW_CNT3__UPDN__SHIFT                                                                       0x0
17698 #define GDS_PS7_CTXSW_CNT3__PTR__SHIFT                                                                        0x10
17699 #define GDS_PS7_CTXSW_CNT3__UPDN_MASK                                                                         0x0000FFFFL
17700 #define GDS_PS7_CTXSW_CNT3__PTR_MASK                                                                          0xFFFF0000L
17701 //GDS_GS_CTXSW_CNT0
17702 #define GDS_GS_CTXSW_CNT0__UPDN__SHIFT                                                                        0x0
17703 #define GDS_GS_CTXSW_CNT0__PTR__SHIFT                                                                         0x10
17704 #define GDS_GS_CTXSW_CNT0__UPDN_MASK                                                                          0x0000FFFFL
17705 #define GDS_GS_CTXSW_CNT0__PTR_MASK                                                                           0xFFFF0000L
17706 //GDS_GS_CTXSW_CNT1
17707 #define GDS_GS_CTXSW_CNT1__UPDN__SHIFT                                                                        0x0
17708 #define GDS_GS_CTXSW_CNT1__PTR__SHIFT                                                                         0x10
17709 #define GDS_GS_CTXSW_CNT1__UPDN_MASK                                                                          0x0000FFFFL
17710 #define GDS_GS_CTXSW_CNT1__PTR_MASK                                                                           0xFFFF0000L
17711 //GDS_GS_CTXSW_CNT2
17712 #define GDS_GS_CTXSW_CNT2__UPDN__SHIFT                                                                        0x0
17713 #define GDS_GS_CTXSW_CNT2__PTR__SHIFT                                                                         0x10
17714 #define GDS_GS_CTXSW_CNT2__UPDN_MASK                                                                          0x0000FFFFL
17715 #define GDS_GS_CTXSW_CNT2__PTR_MASK                                                                           0xFFFF0000L
17716 //GDS_GS_CTXSW_CNT3
17717 #define GDS_GS_CTXSW_CNT3__UPDN__SHIFT                                                                        0x0
17718 #define GDS_GS_CTXSW_CNT3__PTR__SHIFT                                                                         0x10
17719 #define GDS_GS_CTXSW_CNT3__UPDN_MASK                                                                          0x0000FFFFL
17720 #define GDS_GS_CTXSW_CNT3__PTR_MASK                                                                           0xFFFF0000L
17721 
17722 
17723 // addressBlock: xcd0_gc_rasdec
17724 //RAS_SIGNATURE_CONTROL
17725 #define RAS_SIGNATURE_CONTROL__ENABLE__SHIFT                                                                  0x0
17726 #define RAS_SIGNATURE_CONTROL__ENABLE_MASK                                                                    0x00000001L
17727 //RAS_SIGNATURE_MASK
17728 #define RAS_SIGNATURE_MASK__INPUT_BUS_MASK__SHIFT                                                             0x0
17729 #define RAS_SIGNATURE_MASK__INPUT_BUS_MASK_MASK                                                               0xFFFFFFFFL
17730 //RAS_SX_SIGNATURE0
17731 #define RAS_SX_SIGNATURE0__SIGNATURE__SHIFT                                                                   0x0
17732 #define RAS_SX_SIGNATURE0__SIGNATURE_MASK                                                                     0xFFFFFFFFL
17733 //RAS_SX_SIGNATURE1
17734 #define RAS_SX_SIGNATURE1__SIGNATURE__SHIFT                                                                   0x0
17735 #define RAS_SX_SIGNATURE1__SIGNATURE_MASK                                                                     0xFFFFFFFFL
17736 //RAS_SX_SIGNATURE2
17737 #define RAS_SX_SIGNATURE2__SIGNATURE__SHIFT                                                                   0x0
17738 #define RAS_SX_SIGNATURE2__SIGNATURE_MASK                                                                     0xFFFFFFFFL
17739 //RAS_SX_SIGNATURE3
17740 #define RAS_SX_SIGNATURE3__SIGNATURE__SHIFT                                                                   0x0
17741 #define RAS_SX_SIGNATURE3__SIGNATURE_MASK                                                                     0xFFFFFFFFL
17742 //RAS_DB_SIGNATURE0
17743 #define RAS_DB_SIGNATURE0__SIGNATURE__SHIFT                                                                   0x0
17744 #define RAS_DB_SIGNATURE0__SIGNATURE_MASK                                                                     0xFFFFFFFFL
17745 //RAS_PA_SIGNATURE0
17746 #define RAS_PA_SIGNATURE0__SIGNATURE__SHIFT                                                                   0x0
17747 #define RAS_PA_SIGNATURE0__SIGNATURE_MASK                                                                     0xFFFFFFFFL
17748 //RAS_VGT_SIGNATURE0
17749 #define RAS_VGT_SIGNATURE0__SIGNATURE__SHIFT                                                                  0x0
17750 #define RAS_VGT_SIGNATURE0__SIGNATURE_MASK                                                                    0xFFFFFFFFL
17751 //RAS_SQ_SIGNATURE0
17752 #define RAS_SQ_SIGNATURE0__SIGNATURE__SHIFT                                                                   0x0
17753 #define RAS_SQ_SIGNATURE0__SIGNATURE_MASK                                                                     0xFFFFFFFFL
17754 //RAS_SC_SIGNATURE0
17755 #define RAS_SC_SIGNATURE0__SIGNATURE__SHIFT                                                                   0x0
17756 #define RAS_SC_SIGNATURE0__SIGNATURE_MASK                                                                     0xFFFFFFFFL
17757 //RAS_SC_SIGNATURE1
17758 #define RAS_SC_SIGNATURE1__SIGNATURE__SHIFT                                                                   0x0
17759 #define RAS_SC_SIGNATURE1__SIGNATURE_MASK                                                                     0xFFFFFFFFL
17760 //RAS_SC_SIGNATURE2
17761 #define RAS_SC_SIGNATURE2__SIGNATURE__SHIFT                                                                   0x0
17762 #define RAS_SC_SIGNATURE2__SIGNATURE_MASK                                                                     0xFFFFFFFFL
17763 //RAS_SC_SIGNATURE3
17764 #define RAS_SC_SIGNATURE3__SIGNATURE__SHIFT                                                                   0x0
17765 #define RAS_SC_SIGNATURE3__SIGNATURE_MASK                                                                     0xFFFFFFFFL
17766 //RAS_SC_SIGNATURE4
17767 #define RAS_SC_SIGNATURE4__SIGNATURE__SHIFT                                                                   0x0
17768 #define RAS_SC_SIGNATURE4__SIGNATURE_MASK                                                                     0xFFFFFFFFL
17769 //RAS_SC_SIGNATURE5
17770 #define RAS_SC_SIGNATURE5__SIGNATURE__SHIFT                                                                   0x0
17771 #define RAS_SC_SIGNATURE5__SIGNATURE_MASK                                                                     0xFFFFFFFFL
17772 //RAS_SC_SIGNATURE6
17773 #define RAS_SC_SIGNATURE6__SIGNATURE__SHIFT                                                                   0x0
17774 #define RAS_SC_SIGNATURE6__SIGNATURE_MASK                                                                     0xFFFFFFFFL
17775 //RAS_SC_SIGNATURE7
17776 #define RAS_SC_SIGNATURE7__SIGNATURE__SHIFT                                                                   0x0
17777 #define RAS_SC_SIGNATURE7__SIGNATURE_MASK                                                                     0xFFFFFFFFL
17778 //RAS_IA_SIGNATURE0
17779 #define RAS_IA_SIGNATURE0__SIGNATURE__SHIFT                                                                   0x0
17780 #define RAS_IA_SIGNATURE0__SIGNATURE_MASK                                                                     0xFFFFFFFFL
17781 //RAS_IA_SIGNATURE1
17782 #define RAS_IA_SIGNATURE1__SIGNATURE__SHIFT                                                                   0x0
17783 #define RAS_IA_SIGNATURE1__SIGNATURE_MASK                                                                     0xFFFFFFFFL
17784 //RAS_SPI_SIGNATURE0
17785 #define RAS_SPI_SIGNATURE0__SIGNATURE__SHIFT                                                                  0x0
17786 #define RAS_SPI_SIGNATURE0__SIGNATURE_MASK                                                                    0xFFFFFFFFL
17787 //RAS_SPI_SIGNATURE1
17788 #define RAS_SPI_SIGNATURE1__SIGNATURE__SHIFT                                                                  0x0
17789 #define RAS_SPI_SIGNATURE1__SIGNATURE_MASK                                                                    0xFFFFFFFFL
17790 //RAS_TA_SIGNATURE0
17791 #define RAS_TA_SIGNATURE0__SIGNATURE__SHIFT                                                                   0x0
17792 #define RAS_TA_SIGNATURE0__SIGNATURE_MASK                                                                     0xFFFFFFFFL
17793 //RAS_TD_SIGNATURE0
17794 #define RAS_TD_SIGNATURE0__SIGNATURE__SHIFT                                                                   0x0
17795 #define RAS_TD_SIGNATURE0__SIGNATURE_MASK                                                                     0xFFFFFFFFL
17796 //RAS_CB_SIGNATURE0
17797 #define RAS_CB_SIGNATURE0__SIGNATURE__SHIFT                                                                   0x0
17798 #define RAS_CB_SIGNATURE0__SIGNATURE_MASK                                                                     0xFFFFFFFFL
17799 //RAS_BCI_SIGNATURE0
17800 #define RAS_BCI_SIGNATURE0__SIGNATURE__SHIFT                                                                  0x0
17801 #define RAS_BCI_SIGNATURE0__SIGNATURE_MASK                                                                    0xFFFFFFFFL
17802 //RAS_BCI_SIGNATURE1
17803 #define RAS_BCI_SIGNATURE1__SIGNATURE__SHIFT                                                                  0x0
17804 #define RAS_BCI_SIGNATURE1__SIGNATURE_MASK                                                                    0xFFFFFFFFL
17805 //RAS_TA_SIGNATURE1
17806 #define RAS_TA_SIGNATURE1__SIGNATURE__SHIFT                                                                   0x0
17807 #define RAS_TA_SIGNATURE1__SIGNATURE_MASK                                                                     0xFFFFFFFFL
17808 
17809 
17810 // addressBlock: xcd0_gc_gfxdec0
17811 //DB_RENDER_CONTROL
17812 #define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT                                                          0x0
17813 #define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE__SHIFT                                                        0x1
17814 #define DB_RENDER_CONTROL__DEPTH_COPY__SHIFT                                                                  0x2
17815 #define DB_RENDER_CONTROL__STENCIL_COPY__SHIFT                                                                0x3
17816 #define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE__SHIFT                                                          0x4
17817 #define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE__SHIFT                                                    0x5
17818 #define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE__SHIFT                                                      0x6
17819 #define DB_RENDER_CONTROL__COPY_CENTROID__SHIFT                                                               0x7
17820 #define DB_RENDER_CONTROL__COPY_SAMPLE__SHIFT                                                                 0x8
17821 #define DB_RENDER_CONTROL__DECOMPRESS_ENABLE__SHIFT                                                           0xc
17822 #define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE_MASK                                                            0x00000001L
17823 #define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE_MASK                                                          0x00000002L
17824 #define DB_RENDER_CONTROL__DEPTH_COPY_MASK                                                                    0x00000004L
17825 #define DB_RENDER_CONTROL__STENCIL_COPY_MASK                                                                  0x00000008L
17826 #define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE_MASK                                                            0x00000010L
17827 #define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE_MASK                                                      0x00000020L
17828 #define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE_MASK                                                        0x00000040L
17829 #define DB_RENDER_CONTROL__COPY_CENTROID_MASK                                                                 0x00000080L
17830 #define DB_RENDER_CONTROL__COPY_SAMPLE_MASK                                                                   0x00000F00L
17831 #define DB_RENDER_CONTROL__DECOMPRESS_ENABLE_MASK                                                             0x00001000L
17832 //DB_COUNT_CONTROL
17833 #define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE__SHIFT                                                      0x0
17834 #define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS__SHIFT                                                         0x1
17835 #define DB_COUNT_CONTROL__SAMPLE_RATE__SHIFT                                                                  0x4
17836 #define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT                                                                 0x8
17837 #define DB_COUNT_CONTROL__ZFAIL_ENABLE__SHIFT                                                                 0xc
17838 #define DB_COUNT_CONTROL__SFAIL_ENABLE__SHIFT                                                                 0x10
17839 #define DB_COUNT_CONTROL__DBFAIL_ENABLE__SHIFT                                                                0x14
17840 #define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE__SHIFT                                                            0x18
17841 #define DB_COUNT_CONTROL__SLICE_ODD_ENABLE__SHIFT                                                             0x1c
17842 #define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE_MASK                                                        0x00000001L
17843 #define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_MASK                                                           0x00000002L
17844 #define DB_COUNT_CONTROL__SAMPLE_RATE_MASK                                                                    0x00000070L
17845 #define DB_COUNT_CONTROL__ZPASS_ENABLE_MASK                                                                   0x00000F00L
17846 #define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK                                                                   0x0000F000L
17847 #define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK                                                                   0x000F0000L
17848 #define DB_COUNT_CONTROL__DBFAIL_ENABLE_MASK                                                                  0x00F00000L
17849 #define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE_MASK                                                              0x0F000000L
17850 #define DB_COUNT_CONTROL__SLICE_ODD_ENABLE_MASK                                                               0xF0000000L
17851 //DB_DEPTH_VIEW
17852 #define DB_DEPTH_VIEW__SLICE_START__SHIFT                                                                     0x0
17853 #define DB_DEPTH_VIEW__SLICE_MAX__SHIFT                                                                       0xd
17854 #define DB_DEPTH_VIEW__Z_READ_ONLY__SHIFT                                                                     0x18
17855 #define DB_DEPTH_VIEW__STENCIL_READ_ONLY__SHIFT                                                               0x19
17856 #define DB_DEPTH_VIEW__MIPID__SHIFT                                                                           0x1a
17857 #define DB_DEPTH_VIEW__SLICE_START_MASK                                                                       0x000007FFL
17858 #define DB_DEPTH_VIEW__SLICE_MAX_MASK                                                                         0x00FFE000L
17859 #define DB_DEPTH_VIEW__Z_READ_ONLY_MASK                                                                       0x01000000L
17860 #define DB_DEPTH_VIEW__STENCIL_READ_ONLY_MASK                                                                 0x02000000L
17861 #define DB_DEPTH_VIEW__MIPID_MASK                                                                             0x3C000000L
17862 //DB_RENDER_OVERRIDE
17863 #define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT                                                           0x0
17864 #define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0__SHIFT                                                          0x2
17865 #define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1__SHIFT                                                          0x4
17866 #define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER__SHIFT                                                       0x6
17867 #define DB_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT                                                             0x7
17868 #define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT                                                       0x8
17869 #define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE__SHIFT                                                          0x9
17870 #define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT                                                           0xa
17871 #define DB_RENDER_OVERRIDE__FORCE_Z_READ__SHIFT                                                               0xb
17872 #define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ__SHIFT                                                         0xc
17873 #define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT                                                         0xd
17874 #define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT__SHIFT                                                    0xf
17875 #define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP__SHIFT                                                     0x10
17876 #define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE__SHIFT                                                           0x11
17877 #define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED__SHIFT                                                      0x12
17878 #define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM__SHIFT                                                         0x13
17879 #define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT__SHIFT                                                           0x15
17880 #define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT                                                    0x1a
17881 #define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY__SHIFT                                                              0x1b
17882 #define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY__SHIFT                                                        0x1c
17883 #define DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT                                                              0x1d
17884 #define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID__SHIFT                                                        0x1e
17885 #define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION__SHIFT                                                       0x1f
17886 #define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK                                                             0x00000003L
17887 #define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0_MASK                                                            0x0000000CL
17888 #define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1_MASK                                                            0x00000030L
17889 #define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER_MASK                                                         0x00000040L
17890 #define DB_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK                                                               0x00000080L
17891 #define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK                                                         0x00000100L
17892 #define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE_MASK                                                            0x00000200L
17893 #define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL_MASK                                                             0x00000400L
17894 #define DB_RENDER_OVERRIDE__FORCE_Z_READ_MASK                                                                 0x00000800L
17895 #define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ_MASK                                                           0x00001000L
17896 #define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK                                                           0x00006000L
17897 #define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT_MASK                                                      0x00008000L
17898 #define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP_MASK                                                       0x00010000L
17899 #define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE_MASK                                                             0x00020000L
17900 #define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED_MASK                                                        0x00040000L
17901 #define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM_MASK                                                           0x00180000L
17902 #define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT_MASK                                                             0x03E00000L
17903 #define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK                                                      0x04000000L
17904 #define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY_MASK                                                                0x08000000L
17905 #define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY_MASK                                                          0x10000000L
17906 #define DB_RENDER_OVERRIDE__FORCE_Z_VALID_MASK                                                                0x20000000L
17907 #define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID_MASK                                                          0x40000000L
17908 #define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION_MASK                                                         0x80000000L
17909 //DB_RENDER_OVERRIDE2
17910 #define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL__SHIFT                                              0x0
17911 #define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN__SHIFT                                            0x2
17912 #define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION__SHIFT                                       0x5
17913 #define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION__SHIFT                                        0x6
17914 #define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION__SHIFT                                               0x7
17915 #define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH__SHIFT                                                     0x8
17916 #define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP__SHIFT                                                         0x9
17917 #define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT                                           0xa
17918 #define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE__SHIFT                                                 0xb
17919 #define DB_RENDER_OVERRIDE2__HIZ_ZFUNC__SHIFT                                                                 0xc
17920 #define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF__SHIFT                                                              0xf
17921 #define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF__SHIFT                                                              0x12
17922 #define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE__SHIFT                                                           0x15
17923 #define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS__SHIFT                                                         0x16
17924 #define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS__SHIFT                                                         0x17
17925 #define DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL__SHIFT                                               0x19
17926 #define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL_MASK                                                0x00000003L
17927 #define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN_MASK                                              0x0000001CL
17928 #define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION_MASK                                         0x00000020L
17929 #define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION_MASK                                          0x00000040L
17930 #define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION_MASK                                                 0x00000080L
17931 #define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH_MASK                                                       0x00000100L
17932 #define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP_MASK                                                           0x00000200L
17933 #define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK                                             0x00000400L
17934 #define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE_MASK                                                   0x00000800L
17935 #define DB_RENDER_OVERRIDE2__HIZ_ZFUNC_MASK                                                                   0x00007000L
17936 #define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF_MASK                                                                0x00038000L
17937 #define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF_MASK                                                                0x001C0000L
17938 #define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE_MASK                                                             0x00200000L
17939 #define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS_MASK                                                           0x00400000L
17940 #define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS_MASK                                                           0x00800000L
17941 #define DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL_MASK                                                 0x02000000L
17942 //DB_HTILE_DATA_BASE
17943 #define DB_HTILE_DATA_BASE__BASE_256B__SHIFT                                                                  0x0
17944 #define DB_HTILE_DATA_BASE__BASE_256B_MASK                                                                    0xFFFFFFFFL
17945 //DB_HTILE_DATA_BASE_HI
17946 #define DB_HTILE_DATA_BASE_HI__BASE_HI__SHIFT                                                                 0x0
17947 #define DB_HTILE_DATA_BASE_HI__BASE_HI_MASK                                                                   0x000000FFL
17948 //DB_DEPTH_SIZE
17949 #define DB_DEPTH_SIZE__X_MAX__SHIFT                                                                           0x0
17950 #define DB_DEPTH_SIZE__Y_MAX__SHIFT                                                                           0x10
17951 #define DB_DEPTH_SIZE__X_MAX_MASK                                                                             0x00003FFFL
17952 #define DB_DEPTH_SIZE__Y_MAX_MASK                                                                             0x3FFF0000L
17953 //DB_DEPTH_BOUNDS_MIN
17954 #define DB_DEPTH_BOUNDS_MIN__MIN__SHIFT                                                                       0x0
17955 #define DB_DEPTH_BOUNDS_MIN__MIN_MASK                                                                         0xFFFFFFFFL
17956 //DB_DEPTH_BOUNDS_MAX
17957 #define DB_DEPTH_BOUNDS_MAX__MAX__SHIFT                                                                       0x0
17958 #define DB_DEPTH_BOUNDS_MAX__MAX_MASK                                                                         0xFFFFFFFFL
17959 //DB_STENCIL_CLEAR
17960 #define DB_STENCIL_CLEAR__CLEAR__SHIFT                                                                        0x0
17961 #define DB_STENCIL_CLEAR__CLEAR_MASK                                                                          0x000000FFL
17962 //DB_DEPTH_CLEAR
17963 #define DB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT                                                                    0x0
17964 #define DB_DEPTH_CLEAR__DEPTH_CLEAR_MASK                                                                      0xFFFFFFFFL
17965 //PA_SC_SCREEN_SCISSOR_TL
17966 #define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT                                                                  0x0
17967 #define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT                                                                  0x10
17968 #define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK                                                                    0x0000FFFFL
17969 #define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK                                                                    0xFFFF0000L
17970 //PA_SC_SCREEN_SCISSOR_BR
17971 #define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT                                                                  0x0
17972 #define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT                                                                  0x10
17973 #define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK                                                                    0x0000FFFFL
17974 #define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK                                                                    0xFFFF0000L
17975 //DB_Z_INFO
17976 #define DB_Z_INFO__FORMAT__SHIFT                                                                              0x0
17977 #define DB_Z_INFO__NUM_SAMPLES__SHIFT                                                                         0x2
17978 #define DB_Z_INFO__SW_MODE__SHIFT                                                                             0x4
17979 #define DB_Z_INFO__PARTIALLY_RESIDENT__SHIFT                                                                  0xc
17980 #define DB_Z_INFO__FAULT_BEHAVIOR__SHIFT                                                                      0xd
17981 #define DB_Z_INFO__ITERATE_FLUSH__SHIFT                                                                       0xf
17982 #define DB_Z_INFO__MAXMIP__SHIFT                                                                              0x10
17983 #define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES__SHIFT                                                             0x17
17984 #define DB_Z_INFO__ALLOW_EXPCLEAR__SHIFT                                                                      0x1b
17985 #define DB_Z_INFO__READ_SIZE__SHIFT                                                                           0x1c
17986 #define DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT                                                                 0x1d
17987 #define DB_Z_INFO__CLEAR_DISALLOWED__SHIFT                                                                    0x1e
17988 #define DB_Z_INFO__ZRANGE_PRECISION__SHIFT                                                                    0x1f
17989 #define DB_Z_INFO__FORMAT_MASK                                                                                0x00000003L
17990 #define DB_Z_INFO__NUM_SAMPLES_MASK                                                                           0x0000000CL
17991 #define DB_Z_INFO__SW_MODE_MASK                                                                               0x000001F0L
17992 #define DB_Z_INFO__PARTIALLY_RESIDENT_MASK                                                                    0x00001000L
17993 #define DB_Z_INFO__FAULT_BEHAVIOR_MASK                                                                        0x00006000L
17994 #define DB_Z_INFO__ITERATE_FLUSH_MASK                                                                         0x00008000L
17995 #define DB_Z_INFO__MAXMIP_MASK                                                                                0x000F0000L
17996 #define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES_MASK                                                               0x07800000L
17997 #define DB_Z_INFO__ALLOW_EXPCLEAR_MASK                                                                        0x08000000L
17998 #define DB_Z_INFO__READ_SIZE_MASK                                                                             0x10000000L
17999 #define DB_Z_INFO__TILE_SURFACE_ENABLE_MASK                                                                   0x20000000L
18000 #define DB_Z_INFO__CLEAR_DISALLOWED_MASK                                                                      0x40000000L
18001 #define DB_Z_INFO__ZRANGE_PRECISION_MASK                                                                      0x80000000L
18002 //DB_STENCIL_INFO
18003 #define DB_STENCIL_INFO__FORMAT__SHIFT                                                                        0x0
18004 #define DB_STENCIL_INFO__SW_MODE__SHIFT                                                                       0x4
18005 #define DB_STENCIL_INFO__PARTIALLY_RESIDENT__SHIFT                                                            0xc
18006 #define DB_STENCIL_INFO__FAULT_BEHAVIOR__SHIFT                                                                0xd
18007 #define DB_STENCIL_INFO__ITERATE_FLUSH__SHIFT                                                                 0xf
18008 #define DB_STENCIL_INFO__ALLOW_EXPCLEAR__SHIFT                                                                0x1b
18009 #define DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT                                                          0x1d
18010 #define DB_STENCIL_INFO__CLEAR_DISALLOWED__SHIFT                                                              0x1e
18011 #define DB_STENCIL_INFO__FORMAT_MASK                                                                          0x00000001L
18012 #define DB_STENCIL_INFO__SW_MODE_MASK                                                                         0x000001F0L
18013 #define DB_STENCIL_INFO__PARTIALLY_RESIDENT_MASK                                                              0x00001000L
18014 #define DB_STENCIL_INFO__FAULT_BEHAVIOR_MASK                                                                  0x00006000L
18015 #define DB_STENCIL_INFO__ITERATE_FLUSH_MASK                                                                   0x00008000L
18016 #define DB_STENCIL_INFO__ALLOW_EXPCLEAR_MASK                                                                  0x08000000L
18017 #define DB_STENCIL_INFO__TILE_STENCIL_DISABLE_MASK                                                            0x20000000L
18018 #define DB_STENCIL_INFO__CLEAR_DISALLOWED_MASK                                                                0x40000000L
18019 //DB_Z_READ_BASE
18020 #define DB_Z_READ_BASE__BASE_256B__SHIFT                                                                      0x0
18021 #define DB_Z_READ_BASE__BASE_256B_MASK                                                                        0xFFFFFFFFL
18022 //DB_Z_READ_BASE_HI
18023 #define DB_Z_READ_BASE_HI__BASE_HI__SHIFT                                                                     0x0
18024 #define DB_Z_READ_BASE_HI__BASE_HI_MASK                                                                       0x000000FFL
18025 //DB_STENCIL_READ_BASE
18026 #define DB_STENCIL_READ_BASE__BASE_256B__SHIFT                                                                0x0
18027 #define DB_STENCIL_READ_BASE__BASE_256B_MASK                                                                  0xFFFFFFFFL
18028 //DB_STENCIL_READ_BASE_HI
18029 #define DB_STENCIL_READ_BASE_HI__BASE_HI__SHIFT                                                               0x0
18030 #define DB_STENCIL_READ_BASE_HI__BASE_HI_MASK                                                                 0x000000FFL
18031 //DB_Z_WRITE_BASE
18032 #define DB_Z_WRITE_BASE__BASE_256B__SHIFT                                                                     0x0
18033 #define DB_Z_WRITE_BASE__BASE_256B_MASK                                                                       0xFFFFFFFFL
18034 //DB_Z_WRITE_BASE_HI
18035 #define DB_Z_WRITE_BASE_HI__BASE_HI__SHIFT                                                                    0x0
18036 #define DB_Z_WRITE_BASE_HI__BASE_HI_MASK                                                                      0x000000FFL
18037 //DB_STENCIL_WRITE_BASE
18038 #define DB_STENCIL_WRITE_BASE__BASE_256B__SHIFT                                                               0x0
18039 #define DB_STENCIL_WRITE_BASE__BASE_256B_MASK                                                                 0xFFFFFFFFL
18040 //DB_STENCIL_WRITE_BASE_HI
18041 #define DB_STENCIL_WRITE_BASE_HI__BASE_HI__SHIFT                                                              0x0
18042 #define DB_STENCIL_WRITE_BASE_HI__BASE_HI_MASK                                                                0x000000FFL
18043 //DB_DFSM_CONTROL
18044 #define DB_DFSM_CONTROL__PUNCHOUT_MODE__SHIFT                                                                 0x0
18045 #define DB_DFSM_CONTROL__POPS_DRAIN_PS_ON_OVERLAP__SHIFT                                                      0x2
18046 #define DB_DFSM_CONTROL__DISALLOW_OVERFLOW__SHIFT                                                             0x3
18047 #define DB_DFSM_CONTROL__PUNCHOUT_MODE_MASK                                                                   0x00000003L
18048 #define DB_DFSM_CONTROL__POPS_DRAIN_PS_ON_OVERLAP_MASK                                                        0x00000004L
18049 #define DB_DFSM_CONTROL__DISALLOW_OVERFLOW_MASK                                                               0x00000008L
18050 //DB_Z_INFO2
18051 #define DB_Z_INFO2__EPITCH__SHIFT                                                                             0x0
18052 #define DB_Z_INFO2__EPITCH_MASK                                                                               0x0000FFFFL
18053 //DB_STENCIL_INFO2
18054 #define DB_STENCIL_INFO2__EPITCH__SHIFT                                                                       0x0
18055 #define DB_STENCIL_INFO2__EPITCH_MASK                                                                         0x0000FFFFL
18056 //COHER_DEST_BASE_HI_0
18057 #define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B__SHIFT                                                        0x0
18058 #define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B_MASK                                                          0x000000FFL
18059 //COHER_DEST_BASE_HI_1
18060 #define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B__SHIFT                                                        0x0
18061 #define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B_MASK                                                          0x000000FFL
18062 //COHER_DEST_BASE_HI_2
18063 #define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B__SHIFT                                                        0x0
18064 #define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B_MASK                                                          0x000000FFL
18065 //COHER_DEST_BASE_HI_3
18066 #define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B__SHIFT                                                        0x0
18067 #define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B_MASK                                                          0x000000FFL
18068 //COHER_DEST_BASE_2
18069 #define COHER_DEST_BASE_2__DEST_BASE_256B__SHIFT                                                              0x0
18070 #define COHER_DEST_BASE_2__DEST_BASE_256B_MASK                                                                0xFFFFFFFFL
18071 //COHER_DEST_BASE_3
18072 #define COHER_DEST_BASE_3__DEST_BASE_256B__SHIFT                                                              0x0
18073 #define COHER_DEST_BASE_3__DEST_BASE_256B_MASK                                                                0xFFFFFFFFL
18074 //PA_SC_WINDOW_OFFSET
18075 #define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT                                                           0x0
18076 #define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT                                                           0x10
18077 #define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK                                                             0x0000FFFFL
18078 #define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK                                                             0xFFFF0000L
18079 //PA_SC_WINDOW_SCISSOR_TL
18080 #define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT                                                                  0x0
18081 #define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT                                                                  0x10
18082 #define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT                                                 0x1f
18083 #define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK                                                                    0x00007FFFL
18084 #define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK                                                                    0x7FFF0000L
18085 #define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK                                                   0x80000000L
18086 //PA_SC_WINDOW_SCISSOR_BR
18087 #define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT                                                                  0x0
18088 #define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT                                                                  0x10
18089 #define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK                                                                    0x00007FFFL
18090 #define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK                                                                    0x7FFF0000L
18091 //PA_SC_CLIPRECT_RULE
18092 #define PA_SC_CLIPRECT_RULE__CLIP_RULE__SHIFT                                                                 0x0
18093 #define PA_SC_CLIPRECT_RULE__CLIP_RULE_MASK                                                                   0x0000FFFFL
18094 //PA_SC_CLIPRECT_0_TL
18095 #define PA_SC_CLIPRECT_0_TL__TL_X__SHIFT                                                                      0x0
18096 #define PA_SC_CLIPRECT_0_TL__TL_Y__SHIFT                                                                      0x10
18097 #define PA_SC_CLIPRECT_0_TL__TL_X_MASK                                                                        0x00007FFFL
18098 #define PA_SC_CLIPRECT_0_TL__TL_Y_MASK                                                                        0x7FFF0000L
18099 //PA_SC_CLIPRECT_0_BR
18100 #define PA_SC_CLIPRECT_0_BR__BR_X__SHIFT                                                                      0x0
18101 #define PA_SC_CLIPRECT_0_BR__BR_Y__SHIFT                                                                      0x10
18102 #define PA_SC_CLIPRECT_0_BR__BR_X_MASK                                                                        0x00007FFFL
18103 #define PA_SC_CLIPRECT_0_BR__BR_Y_MASK                                                                        0x7FFF0000L
18104 //PA_SC_CLIPRECT_1_TL
18105 #define PA_SC_CLIPRECT_1_TL__TL_X__SHIFT                                                                      0x0
18106 #define PA_SC_CLIPRECT_1_TL__TL_Y__SHIFT                                                                      0x10
18107 #define PA_SC_CLIPRECT_1_TL__TL_X_MASK                                                                        0x00007FFFL
18108 #define PA_SC_CLIPRECT_1_TL__TL_Y_MASK                                                                        0x7FFF0000L
18109 //PA_SC_CLIPRECT_1_BR
18110 #define PA_SC_CLIPRECT_1_BR__BR_X__SHIFT                                                                      0x0
18111 #define PA_SC_CLIPRECT_1_BR__BR_Y__SHIFT                                                                      0x10
18112 #define PA_SC_CLIPRECT_1_BR__BR_X_MASK                                                                        0x00007FFFL
18113 #define PA_SC_CLIPRECT_1_BR__BR_Y_MASK                                                                        0x7FFF0000L
18114 //PA_SC_CLIPRECT_2_TL
18115 #define PA_SC_CLIPRECT_2_TL__TL_X__SHIFT                                                                      0x0
18116 #define PA_SC_CLIPRECT_2_TL__TL_Y__SHIFT                                                                      0x10
18117 #define PA_SC_CLIPRECT_2_TL__TL_X_MASK                                                                        0x00007FFFL
18118 #define PA_SC_CLIPRECT_2_TL__TL_Y_MASK                                                                        0x7FFF0000L
18119 //PA_SC_CLIPRECT_2_BR
18120 #define PA_SC_CLIPRECT_2_BR__BR_X__SHIFT                                                                      0x0
18121 #define PA_SC_CLIPRECT_2_BR__BR_Y__SHIFT                                                                      0x10
18122 #define PA_SC_CLIPRECT_2_BR__BR_X_MASK                                                                        0x00007FFFL
18123 #define PA_SC_CLIPRECT_2_BR__BR_Y_MASK                                                                        0x7FFF0000L
18124 //PA_SC_CLIPRECT_3_TL
18125 #define PA_SC_CLIPRECT_3_TL__TL_X__SHIFT                                                                      0x0
18126 #define PA_SC_CLIPRECT_3_TL__TL_Y__SHIFT                                                                      0x10
18127 #define PA_SC_CLIPRECT_3_TL__TL_X_MASK                                                                        0x00007FFFL
18128 #define PA_SC_CLIPRECT_3_TL__TL_Y_MASK                                                                        0x7FFF0000L
18129 //PA_SC_CLIPRECT_3_BR
18130 #define PA_SC_CLIPRECT_3_BR__BR_X__SHIFT                                                                      0x0
18131 #define PA_SC_CLIPRECT_3_BR__BR_Y__SHIFT                                                                      0x10
18132 #define PA_SC_CLIPRECT_3_BR__BR_X_MASK                                                                        0x00007FFFL
18133 #define PA_SC_CLIPRECT_3_BR__BR_Y_MASK                                                                        0x7FFF0000L
18134 //PA_SC_EDGERULE
18135 #define PA_SC_EDGERULE__ER_TRI__SHIFT                                                                         0x0
18136 #define PA_SC_EDGERULE__ER_POINT__SHIFT                                                                       0x4
18137 #define PA_SC_EDGERULE__ER_RECT__SHIFT                                                                        0x8
18138 #define PA_SC_EDGERULE__ER_LINE_LR__SHIFT                                                                     0xc
18139 #define PA_SC_EDGERULE__ER_LINE_RL__SHIFT                                                                     0x12
18140 #define PA_SC_EDGERULE__ER_LINE_TB__SHIFT                                                                     0x18
18141 #define PA_SC_EDGERULE__ER_LINE_BT__SHIFT                                                                     0x1c
18142 #define PA_SC_EDGERULE__ER_TRI_MASK                                                                           0x0000000FL
18143 #define PA_SC_EDGERULE__ER_POINT_MASK                                                                         0x000000F0L
18144 #define PA_SC_EDGERULE__ER_RECT_MASK                                                                          0x00000F00L
18145 #define PA_SC_EDGERULE__ER_LINE_LR_MASK                                                                       0x0003F000L
18146 #define PA_SC_EDGERULE__ER_LINE_RL_MASK                                                                       0x00FC0000L
18147 #define PA_SC_EDGERULE__ER_LINE_TB_MASK                                                                       0x0F000000L
18148 #define PA_SC_EDGERULE__ER_LINE_BT_MASK                                                                       0xF0000000L
18149 //PA_SU_HARDWARE_SCREEN_OFFSET
18150 #define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X__SHIFT                                               0x0
18151 #define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y__SHIFT                                               0x10
18152 #define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X_MASK                                                 0x000001FFL
18153 #define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y_MASK                                                 0x01FF0000L
18154 //CB_TARGET_MASK
18155 #define CB_TARGET_MASK__TARGET0_ENABLE__SHIFT                                                                 0x0
18156 #define CB_TARGET_MASK__TARGET1_ENABLE__SHIFT                                                                 0x4
18157 #define CB_TARGET_MASK__TARGET2_ENABLE__SHIFT                                                                 0x8
18158 #define CB_TARGET_MASK__TARGET3_ENABLE__SHIFT                                                                 0xc
18159 #define CB_TARGET_MASK__TARGET4_ENABLE__SHIFT                                                                 0x10
18160 #define CB_TARGET_MASK__TARGET5_ENABLE__SHIFT                                                                 0x14
18161 #define CB_TARGET_MASK__TARGET6_ENABLE__SHIFT                                                                 0x18
18162 #define CB_TARGET_MASK__TARGET7_ENABLE__SHIFT                                                                 0x1c
18163 #define CB_TARGET_MASK__TARGET0_ENABLE_MASK                                                                   0x0000000FL
18164 #define CB_TARGET_MASK__TARGET1_ENABLE_MASK                                                                   0x000000F0L
18165 #define CB_TARGET_MASK__TARGET2_ENABLE_MASK                                                                   0x00000F00L
18166 #define CB_TARGET_MASK__TARGET3_ENABLE_MASK                                                                   0x0000F000L
18167 #define CB_TARGET_MASK__TARGET4_ENABLE_MASK                                                                   0x000F0000L
18168 #define CB_TARGET_MASK__TARGET5_ENABLE_MASK                                                                   0x00F00000L
18169 #define CB_TARGET_MASK__TARGET6_ENABLE_MASK                                                                   0x0F000000L
18170 #define CB_TARGET_MASK__TARGET7_ENABLE_MASK                                                                   0xF0000000L
18171 //CB_SHADER_MASK
18172 #define CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT                                                                 0x0
18173 #define CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT                                                                 0x4
18174 #define CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT                                                                 0x8
18175 #define CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT                                                                 0xc
18176 #define CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT                                                                 0x10
18177 #define CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT                                                                 0x14
18178 #define CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT                                                                 0x18
18179 #define CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT                                                                 0x1c
18180 #define CB_SHADER_MASK__OUTPUT0_ENABLE_MASK                                                                   0x0000000FL
18181 #define CB_SHADER_MASK__OUTPUT1_ENABLE_MASK                                                                   0x000000F0L
18182 #define CB_SHADER_MASK__OUTPUT2_ENABLE_MASK                                                                   0x00000F00L
18183 #define CB_SHADER_MASK__OUTPUT3_ENABLE_MASK                                                                   0x0000F000L
18184 #define CB_SHADER_MASK__OUTPUT4_ENABLE_MASK                                                                   0x000F0000L
18185 #define CB_SHADER_MASK__OUTPUT5_ENABLE_MASK                                                                   0x00F00000L
18186 #define CB_SHADER_MASK__OUTPUT6_ENABLE_MASK                                                                   0x0F000000L
18187 #define CB_SHADER_MASK__OUTPUT7_ENABLE_MASK                                                                   0xF0000000L
18188 //PA_SC_GENERIC_SCISSOR_TL
18189 #define PA_SC_GENERIC_SCISSOR_TL__TL_X__SHIFT                                                                 0x0
18190 #define PA_SC_GENERIC_SCISSOR_TL__TL_Y__SHIFT                                                                 0x10
18191 #define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT                                                0x1f
18192 #define PA_SC_GENERIC_SCISSOR_TL__TL_X_MASK                                                                   0x00007FFFL
18193 #define PA_SC_GENERIC_SCISSOR_TL__TL_Y_MASK                                                                   0x7FFF0000L
18194 #define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK                                                  0x80000000L
18195 //PA_SC_GENERIC_SCISSOR_BR
18196 #define PA_SC_GENERIC_SCISSOR_BR__BR_X__SHIFT                                                                 0x0
18197 #define PA_SC_GENERIC_SCISSOR_BR__BR_Y__SHIFT                                                                 0x10
18198 #define PA_SC_GENERIC_SCISSOR_BR__BR_X_MASK                                                                   0x00007FFFL
18199 #define PA_SC_GENERIC_SCISSOR_BR__BR_Y_MASK                                                                   0x7FFF0000L
18200 //COHER_DEST_BASE_0
18201 #define COHER_DEST_BASE_0__DEST_BASE_256B__SHIFT                                                              0x0
18202 #define COHER_DEST_BASE_0__DEST_BASE_256B_MASK                                                                0xFFFFFFFFL
18203 //COHER_DEST_BASE_1
18204 #define COHER_DEST_BASE_1__DEST_BASE_256B__SHIFT                                                              0x0
18205 #define COHER_DEST_BASE_1__DEST_BASE_256B_MASK                                                                0xFFFFFFFFL
18206 //PA_SC_VPORT_SCISSOR_0_TL
18207 #define PA_SC_VPORT_SCISSOR_0_TL__TL_X__SHIFT                                                                 0x0
18208 #define PA_SC_VPORT_SCISSOR_0_TL__TL_Y__SHIFT                                                                 0x10
18209 #define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE__SHIFT                                                0x1f
18210 #define PA_SC_VPORT_SCISSOR_0_TL__TL_X_MASK                                                                   0x00007FFFL
18211 #define PA_SC_VPORT_SCISSOR_0_TL__TL_Y_MASK                                                                   0x7FFF0000L
18212 #define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE_MASK                                                  0x80000000L
18213 //PA_SC_VPORT_SCISSOR_0_BR
18214 #define PA_SC_VPORT_SCISSOR_0_BR__BR_X__SHIFT                                                                 0x0
18215 #define PA_SC_VPORT_SCISSOR_0_BR__BR_Y__SHIFT                                                                 0x10
18216 #define PA_SC_VPORT_SCISSOR_0_BR__BR_X_MASK                                                                   0x00007FFFL
18217 #define PA_SC_VPORT_SCISSOR_0_BR__BR_Y_MASK                                                                   0x7FFF0000L
18218 //PA_SC_VPORT_SCISSOR_1_TL
18219 #define PA_SC_VPORT_SCISSOR_1_TL__TL_X__SHIFT                                                                 0x0
18220 #define PA_SC_VPORT_SCISSOR_1_TL__TL_Y__SHIFT                                                                 0x10
18221 #define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE__SHIFT                                                0x1f
18222 #define PA_SC_VPORT_SCISSOR_1_TL__TL_X_MASK                                                                   0x00007FFFL
18223 #define PA_SC_VPORT_SCISSOR_1_TL__TL_Y_MASK                                                                   0x7FFF0000L
18224 #define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE_MASK                                                  0x80000000L
18225 //PA_SC_VPORT_SCISSOR_1_BR
18226 #define PA_SC_VPORT_SCISSOR_1_BR__BR_X__SHIFT                                                                 0x0
18227 #define PA_SC_VPORT_SCISSOR_1_BR__BR_Y__SHIFT                                                                 0x10
18228 #define PA_SC_VPORT_SCISSOR_1_BR__BR_X_MASK                                                                   0x00007FFFL
18229 #define PA_SC_VPORT_SCISSOR_1_BR__BR_Y_MASK                                                                   0x7FFF0000L
18230 //PA_SC_VPORT_SCISSOR_2_TL
18231 #define PA_SC_VPORT_SCISSOR_2_TL__TL_X__SHIFT                                                                 0x0
18232 #define PA_SC_VPORT_SCISSOR_2_TL__TL_Y__SHIFT                                                                 0x10
18233 #define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE__SHIFT                                                0x1f
18234 #define PA_SC_VPORT_SCISSOR_2_TL__TL_X_MASK                                                                   0x00007FFFL
18235 #define PA_SC_VPORT_SCISSOR_2_TL__TL_Y_MASK                                                                   0x7FFF0000L
18236 #define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE_MASK                                                  0x80000000L
18237 //PA_SC_VPORT_SCISSOR_2_BR
18238 #define PA_SC_VPORT_SCISSOR_2_BR__BR_X__SHIFT                                                                 0x0
18239 #define PA_SC_VPORT_SCISSOR_2_BR__BR_Y__SHIFT                                                                 0x10
18240 #define PA_SC_VPORT_SCISSOR_2_BR__BR_X_MASK                                                                   0x00007FFFL
18241 #define PA_SC_VPORT_SCISSOR_2_BR__BR_Y_MASK                                                                   0x7FFF0000L
18242 //PA_SC_VPORT_SCISSOR_3_TL
18243 #define PA_SC_VPORT_SCISSOR_3_TL__TL_X__SHIFT                                                                 0x0
18244 #define PA_SC_VPORT_SCISSOR_3_TL__TL_Y__SHIFT                                                                 0x10
18245 #define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE__SHIFT                                                0x1f
18246 #define PA_SC_VPORT_SCISSOR_3_TL__TL_X_MASK                                                                   0x00007FFFL
18247 #define PA_SC_VPORT_SCISSOR_3_TL__TL_Y_MASK                                                                   0x7FFF0000L
18248 #define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE_MASK                                                  0x80000000L
18249 //PA_SC_VPORT_SCISSOR_3_BR
18250 #define PA_SC_VPORT_SCISSOR_3_BR__BR_X__SHIFT                                                                 0x0
18251 #define PA_SC_VPORT_SCISSOR_3_BR__BR_Y__SHIFT                                                                 0x10
18252 #define PA_SC_VPORT_SCISSOR_3_BR__BR_X_MASK                                                                   0x00007FFFL
18253 #define PA_SC_VPORT_SCISSOR_3_BR__BR_Y_MASK                                                                   0x7FFF0000L
18254 //PA_SC_VPORT_SCISSOR_4_TL
18255 #define PA_SC_VPORT_SCISSOR_4_TL__TL_X__SHIFT                                                                 0x0
18256 #define PA_SC_VPORT_SCISSOR_4_TL__TL_Y__SHIFT                                                                 0x10
18257 #define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE__SHIFT                                                0x1f
18258 #define PA_SC_VPORT_SCISSOR_4_TL__TL_X_MASK                                                                   0x00007FFFL
18259 #define PA_SC_VPORT_SCISSOR_4_TL__TL_Y_MASK                                                                   0x7FFF0000L
18260 #define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE_MASK                                                  0x80000000L
18261 //PA_SC_VPORT_SCISSOR_4_BR
18262 #define PA_SC_VPORT_SCISSOR_4_BR__BR_X__SHIFT                                                                 0x0
18263 #define PA_SC_VPORT_SCISSOR_4_BR__BR_Y__SHIFT                                                                 0x10
18264 #define PA_SC_VPORT_SCISSOR_4_BR__BR_X_MASK                                                                   0x00007FFFL
18265 #define PA_SC_VPORT_SCISSOR_4_BR__BR_Y_MASK                                                                   0x7FFF0000L
18266 //PA_SC_VPORT_SCISSOR_5_TL
18267 #define PA_SC_VPORT_SCISSOR_5_TL__TL_X__SHIFT                                                                 0x0
18268 #define PA_SC_VPORT_SCISSOR_5_TL__TL_Y__SHIFT                                                                 0x10
18269 #define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE__SHIFT                                                0x1f
18270 #define PA_SC_VPORT_SCISSOR_5_TL__TL_X_MASK                                                                   0x00007FFFL
18271 #define PA_SC_VPORT_SCISSOR_5_TL__TL_Y_MASK                                                                   0x7FFF0000L
18272 #define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE_MASK                                                  0x80000000L
18273 //PA_SC_VPORT_SCISSOR_5_BR
18274 #define PA_SC_VPORT_SCISSOR_5_BR__BR_X__SHIFT                                                                 0x0
18275 #define PA_SC_VPORT_SCISSOR_5_BR__BR_Y__SHIFT                                                                 0x10
18276 #define PA_SC_VPORT_SCISSOR_5_BR__BR_X_MASK                                                                   0x00007FFFL
18277 #define PA_SC_VPORT_SCISSOR_5_BR__BR_Y_MASK                                                                   0x7FFF0000L
18278 //PA_SC_VPORT_SCISSOR_6_TL
18279 #define PA_SC_VPORT_SCISSOR_6_TL__TL_X__SHIFT                                                                 0x0
18280 #define PA_SC_VPORT_SCISSOR_6_TL__TL_Y__SHIFT                                                                 0x10
18281 #define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE__SHIFT                                                0x1f
18282 #define PA_SC_VPORT_SCISSOR_6_TL__TL_X_MASK                                                                   0x00007FFFL
18283 #define PA_SC_VPORT_SCISSOR_6_TL__TL_Y_MASK                                                                   0x7FFF0000L
18284 #define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE_MASK                                                  0x80000000L
18285 //PA_SC_VPORT_SCISSOR_6_BR
18286 #define PA_SC_VPORT_SCISSOR_6_BR__BR_X__SHIFT                                                                 0x0
18287 #define PA_SC_VPORT_SCISSOR_6_BR__BR_Y__SHIFT                                                                 0x10
18288 #define PA_SC_VPORT_SCISSOR_6_BR__BR_X_MASK                                                                   0x00007FFFL
18289 #define PA_SC_VPORT_SCISSOR_6_BR__BR_Y_MASK                                                                   0x7FFF0000L
18290 //PA_SC_VPORT_SCISSOR_7_TL
18291 #define PA_SC_VPORT_SCISSOR_7_TL__TL_X__SHIFT                                                                 0x0
18292 #define PA_SC_VPORT_SCISSOR_7_TL__TL_Y__SHIFT                                                                 0x10
18293 #define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE__SHIFT                                                0x1f
18294 #define PA_SC_VPORT_SCISSOR_7_TL__TL_X_MASK                                                                   0x00007FFFL
18295 #define PA_SC_VPORT_SCISSOR_7_TL__TL_Y_MASK                                                                   0x7FFF0000L
18296 #define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE_MASK                                                  0x80000000L
18297 //PA_SC_VPORT_SCISSOR_7_BR
18298 #define PA_SC_VPORT_SCISSOR_7_BR__BR_X__SHIFT                                                                 0x0
18299 #define PA_SC_VPORT_SCISSOR_7_BR__BR_Y__SHIFT                                                                 0x10
18300 #define PA_SC_VPORT_SCISSOR_7_BR__BR_X_MASK                                                                   0x00007FFFL
18301 #define PA_SC_VPORT_SCISSOR_7_BR__BR_Y_MASK                                                                   0x7FFF0000L
18302 //PA_SC_VPORT_SCISSOR_8_TL
18303 #define PA_SC_VPORT_SCISSOR_8_TL__TL_X__SHIFT                                                                 0x0
18304 #define PA_SC_VPORT_SCISSOR_8_TL__TL_Y__SHIFT                                                                 0x10
18305 #define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE__SHIFT                                                0x1f
18306 #define PA_SC_VPORT_SCISSOR_8_TL__TL_X_MASK                                                                   0x00007FFFL
18307 #define PA_SC_VPORT_SCISSOR_8_TL__TL_Y_MASK                                                                   0x7FFF0000L
18308 #define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE_MASK                                                  0x80000000L
18309 //PA_SC_VPORT_SCISSOR_8_BR
18310 #define PA_SC_VPORT_SCISSOR_8_BR__BR_X__SHIFT                                                                 0x0
18311 #define PA_SC_VPORT_SCISSOR_8_BR__BR_Y__SHIFT                                                                 0x10
18312 #define PA_SC_VPORT_SCISSOR_8_BR__BR_X_MASK                                                                   0x00007FFFL
18313 #define PA_SC_VPORT_SCISSOR_8_BR__BR_Y_MASK                                                                   0x7FFF0000L
18314 //PA_SC_VPORT_SCISSOR_9_TL
18315 #define PA_SC_VPORT_SCISSOR_9_TL__TL_X__SHIFT                                                                 0x0
18316 #define PA_SC_VPORT_SCISSOR_9_TL__TL_Y__SHIFT                                                                 0x10
18317 #define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE__SHIFT                                                0x1f
18318 #define PA_SC_VPORT_SCISSOR_9_TL__TL_X_MASK                                                                   0x00007FFFL
18319 #define PA_SC_VPORT_SCISSOR_9_TL__TL_Y_MASK                                                                   0x7FFF0000L
18320 #define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE_MASK                                                  0x80000000L
18321 //PA_SC_VPORT_SCISSOR_9_BR
18322 #define PA_SC_VPORT_SCISSOR_9_BR__BR_X__SHIFT                                                                 0x0
18323 #define PA_SC_VPORT_SCISSOR_9_BR__BR_Y__SHIFT                                                                 0x10
18324 #define PA_SC_VPORT_SCISSOR_9_BR__BR_X_MASK                                                                   0x00007FFFL
18325 #define PA_SC_VPORT_SCISSOR_9_BR__BR_Y_MASK                                                                   0x7FFF0000L
18326 //PA_SC_VPORT_SCISSOR_10_TL
18327 #define PA_SC_VPORT_SCISSOR_10_TL__TL_X__SHIFT                                                                0x0
18328 #define PA_SC_VPORT_SCISSOR_10_TL__TL_Y__SHIFT                                                                0x10
18329 #define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE__SHIFT                                               0x1f
18330 #define PA_SC_VPORT_SCISSOR_10_TL__TL_X_MASK                                                                  0x00007FFFL
18331 #define PA_SC_VPORT_SCISSOR_10_TL__TL_Y_MASK                                                                  0x7FFF0000L
18332 #define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE_MASK                                                 0x80000000L
18333 //PA_SC_VPORT_SCISSOR_10_BR
18334 #define PA_SC_VPORT_SCISSOR_10_BR__BR_X__SHIFT                                                                0x0
18335 #define PA_SC_VPORT_SCISSOR_10_BR__BR_Y__SHIFT                                                                0x10
18336 #define PA_SC_VPORT_SCISSOR_10_BR__BR_X_MASK                                                                  0x00007FFFL
18337 #define PA_SC_VPORT_SCISSOR_10_BR__BR_Y_MASK                                                                  0x7FFF0000L
18338 //PA_SC_VPORT_SCISSOR_11_TL
18339 #define PA_SC_VPORT_SCISSOR_11_TL__TL_X__SHIFT                                                                0x0
18340 #define PA_SC_VPORT_SCISSOR_11_TL__TL_Y__SHIFT                                                                0x10
18341 #define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE__SHIFT                                               0x1f
18342 #define PA_SC_VPORT_SCISSOR_11_TL__TL_X_MASK                                                                  0x00007FFFL
18343 #define PA_SC_VPORT_SCISSOR_11_TL__TL_Y_MASK                                                                  0x7FFF0000L
18344 #define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE_MASK                                                 0x80000000L
18345 //PA_SC_VPORT_SCISSOR_11_BR
18346 #define PA_SC_VPORT_SCISSOR_11_BR__BR_X__SHIFT                                                                0x0
18347 #define PA_SC_VPORT_SCISSOR_11_BR__BR_Y__SHIFT                                                                0x10
18348 #define PA_SC_VPORT_SCISSOR_11_BR__BR_X_MASK                                                                  0x00007FFFL
18349 #define PA_SC_VPORT_SCISSOR_11_BR__BR_Y_MASK                                                                  0x7FFF0000L
18350 //PA_SC_VPORT_SCISSOR_12_TL
18351 #define PA_SC_VPORT_SCISSOR_12_TL__TL_X__SHIFT                                                                0x0
18352 #define PA_SC_VPORT_SCISSOR_12_TL__TL_Y__SHIFT                                                                0x10
18353 #define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE__SHIFT                                               0x1f
18354 #define PA_SC_VPORT_SCISSOR_12_TL__TL_X_MASK                                                                  0x00007FFFL
18355 #define PA_SC_VPORT_SCISSOR_12_TL__TL_Y_MASK                                                                  0x7FFF0000L
18356 #define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE_MASK                                                 0x80000000L
18357 //PA_SC_VPORT_SCISSOR_12_BR
18358 #define PA_SC_VPORT_SCISSOR_12_BR__BR_X__SHIFT                                                                0x0
18359 #define PA_SC_VPORT_SCISSOR_12_BR__BR_Y__SHIFT                                                                0x10
18360 #define PA_SC_VPORT_SCISSOR_12_BR__BR_X_MASK                                                                  0x00007FFFL
18361 #define PA_SC_VPORT_SCISSOR_12_BR__BR_Y_MASK                                                                  0x7FFF0000L
18362 //PA_SC_VPORT_SCISSOR_13_TL
18363 #define PA_SC_VPORT_SCISSOR_13_TL__TL_X__SHIFT                                                                0x0
18364 #define PA_SC_VPORT_SCISSOR_13_TL__TL_Y__SHIFT                                                                0x10
18365 #define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE__SHIFT                                               0x1f
18366 #define PA_SC_VPORT_SCISSOR_13_TL__TL_X_MASK                                                                  0x00007FFFL
18367 #define PA_SC_VPORT_SCISSOR_13_TL__TL_Y_MASK                                                                  0x7FFF0000L
18368 #define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE_MASK                                                 0x80000000L
18369 //PA_SC_VPORT_SCISSOR_13_BR
18370 #define PA_SC_VPORT_SCISSOR_13_BR__BR_X__SHIFT                                                                0x0
18371 #define PA_SC_VPORT_SCISSOR_13_BR__BR_Y__SHIFT                                                                0x10
18372 #define PA_SC_VPORT_SCISSOR_13_BR__BR_X_MASK                                                                  0x00007FFFL
18373 #define PA_SC_VPORT_SCISSOR_13_BR__BR_Y_MASK                                                                  0x7FFF0000L
18374 //PA_SC_VPORT_SCISSOR_14_TL
18375 #define PA_SC_VPORT_SCISSOR_14_TL__TL_X__SHIFT                                                                0x0
18376 #define PA_SC_VPORT_SCISSOR_14_TL__TL_Y__SHIFT                                                                0x10
18377 #define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE__SHIFT                                               0x1f
18378 #define PA_SC_VPORT_SCISSOR_14_TL__TL_X_MASK                                                                  0x00007FFFL
18379 #define PA_SC_VPORT_SCISSOR_14_TL__TL_Y_MASK                                                                  0x7FFF0000L
18380 #define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE_MASK                                                 0x80000000L
18381 //PA_SC_VPORT_SCISSOR_14_BR
18382 #define PA_SC_VPORT_SCISSOR_14_BR__BR_X__SHIFT                                                                0x0
18383 #define PA_SC_VPORT_SCISSOR_14_BR__BR_Y__SHIFT                                                                0x10
18384 #define PA_SC_VPORT_SCISSOR_14_BR__BR_X_MASK                                                                  0x00007FFFL
18385 #define PA_SC_VPORT_SCISSOR_14_BR__BR_Y_MASK                                                                  0x7FFF0000L
18386 //PA_SC_VPORT_SCISSOR_15_TL
18387 #define PA_SC_VPORT_SCISSOR_15_TL__TL_X__SHIFT                                                                0x0
18388 #define PA_SC_VPORT_SCISSOR_15_TL__TL_Y__SHIFT                                                                0x10
18389 #define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE__SHIFT                                               0x1f
18390 #define PA_SC_VPORT_SCISSOR_15_TL__TL_X_MASK                                                                  0x00007FFFL
18391 #define PA_SC_VPORT_SCISSOR_15_TL__TL_Y_MASK                                                                  0x7FFF0000L
18392 #define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE_MASK                                                 0x80000000L
18393 //PA_SC_VPORT_SCISSOR_15_BR
18394 #define PA_SC_VPORT_SCISSOR_15_BR__BR_X__SHIFT                                                                0x0
18395 #define PA_SC_VPORT_SCISSOR_15_BR__BR_Y__SHIFT                                                                0x10
18396 #define PA_SC_VPORT_SCISSOR_15_BR__BR_X_MASK                                                                  0x00007FFFL
18397 #define PA_SC_VPORT_SCISSOR_15_BR__BR_Y_MASK                                                                  0x7FFF0000L
18398 //PA_SC_VPORT_ZMIN_0
18399 #define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN__SHIFT                                                                 0x0
18400 #define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN_MASK                                                                   0xFFFFFFFFL
18401 //PA_SC_VPORT_ZMAX_0
18402 #define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX__SHIFT                                                                 0x0
18403 #define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX_MASK                                                                   0xFFFFFFFFL
18404 //PA_SC_VPORT_ZMIN_1
18405 #define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN__SHIFT                                                                 0x0
18406 #define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN_MASK                                                                   0xFFFFFFFFL
18407 //PA_SC_VPORT_ZMAX_1
18408 #define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX__SHIFT                                                                 0x0
18409 #define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX_MASK                                                                   0xFFFFFFFFL
18410 //PA_SC_VPORT_ZMIN_2
18411 #define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN__SHIFT                                                                 0x0
18412 #define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN_MASK                                                                   0xFFFFFFFFL
18413 //PA_SC_VPORT_ZMAX_2
18414 #define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX__SHIFT                                                                 0x0
18415 #define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX_MASK                                                                   0xFFFFFFFFL
18416 //PA_SC_VPORT_ZMIN_3
18417 #define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN__SHIFT                                                                 0x0
18418 #define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN_MASK                                                                   0xFFFFFFFFL
18419 //PA_SC_VPORT_ZMAX_3
18420 #define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX__SHIFT                                                                 0x0
18421 #define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX_MASK                                                                   0xFFFFFFFFL
18422 //PA_SC_VPORT_ZMIN_4
18423 #define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN__SHIFT                                                                 0x0
18424 #define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN_MASK                                                                   0xFFFFFFFFL
18425 //PA_SC_VPORT_ZMAX_4
18426 #define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX__SHIFT                                                                 0x0
18427 #define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX_MASK                                                                   0xFFFFFFFFL
18428 //PA_SC_VPORT_ZMIN_5
18429 #define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN__SHIFT                                                                 0x0
18430 #define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN_MASK                                                                   0xFFFFFFFFL
18431 //PA_SC_VPORT_ZMAX_5
18432 #define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX__SHIFT                                                                 0x0
18433 #define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX_MASK                                                                   0xFFFFFFFFL
18434 //PA_SC_VPORT_ZMIN_6
18435 #define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN__SHIFT                                                                 0x0
18436 #define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN_MASK                                                                   0xFFFFFFFFL
18437 //PA_SC_VPORT_ZMAX_6
18438 #define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX__SHIFT                                                                 0x0
18439 #define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX_MASK                                                                   0xFFFFFFFFL
18440 //PA_SC_VPORT_ZMIN_7
18441 #define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN__SHIFT                                                                 0x0
18442 #define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN_MASK                                                                   0xFFFFFFFFL
18443 //PA_SC_VPORT_ZMAX_7
18444 #define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX__SHIFT                                                                 0x0
18445 #define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX_MASK                                                                   0xFFFFFFFFL
18446 //PA_SC_VPORT_ZMIN_8
18447 #define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN__SHIFT                                                                 0x0
18448 #define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN_MASK                                                                   0xFFFFFFFFL
18449 //PA_SC_VPORT_ZMAX_8
18450 #define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX__SHIFT                                                                 0x0
18451 #define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX_MASK                                                                   0xFFFFFFFFL
18452 //PA_SC_VPORT_ZMIN_9
18453 #define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN__SHIFT                                                                 0x0
18454 #define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN_MASK                                                                   0xFFFFFFFFL
18455 //PA_SC_VPORT_ZMAX_9
18456 #define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX__SHIFT                                                                 0x0
18457 #define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX_MASK                                                                   0xFFFFFFFFL
18458 //PA_SC_VPORT_ZMIN_10
18459 #define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN__SHIFT                                                                0x0
18460 #define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN_MASK                                                                  0xFFFFFFFFL
18461 //PA_SC_VPORT_ZMAX_10
18462 #define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX__SHIFT                                                                0x0
18463 #define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX_MASK                                                                  0xFFFFFFFFL
18464 //PA_SC_VPORT_ZMIN_11
18465 #define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN__SHIFT                                                                0x0
18466 #define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN_MASK                                                                  0xFFFFFFFFL
18467 //PA_SC_VPORT_ZMAX_11
18468 #define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX__SHIFT                                                                0x0
18469 #define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX_MASK                                                                  0xFFFFFFFFL
18470 //PA_SC_VPORT_ZMIN_12
18471 #define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN__SHIFT                                                                0x0
18472 #define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN_MASK                                                                  0xFFFFFFFFL
18473 //PA_SC_VPORT_ZMAX_12
18474 #define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX__SHIFT                                                                0x0
18475 #define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX_MASK                                                                  0xFFFFFFFFL
18476 //PA_SC_VPORT_ZMIN_13
18477 #define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN__SHIFT                                                                0x0
18478 #define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN_MASK                                                                  0xFFFFFFFFL
18479 //PA_SC_VPORT_ZMAX_13
18480 #define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX__SHIFT                                                                0x0
18481 #define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX_MASK                                                                  0xFFFFFFFFL
18482 //PA_SC_VPORT_ZMIN_14
18483 #define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN__SHIFT                                                                0x0
18484 #define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN_MASK                                                                  0xFFFFFFFFL
18485 //PA_SC_VPORT_ZMAX_14
18486 #define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX__SHIFT                                                                0x0
18487 #define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX_MASK                                                                  0xFFFFFFFFL
18488 //PA_SC_VPORT_ZMIN_15
18489 #define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN__SHIFT                                                                0x0
18490 #define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN_MASK                                                                  0xFFFFFFFFL
18491 //PA_SC_VPORT_ZMAX_15
18492 #define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX__SHIFT                                                                0x0
18493 #define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX_MASK                                                                  0xFFFFFFFFL
18494 //PA_SC_RASTER_CONFIG
18495 #define PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT                                                               0x0
18496 #define PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT                                                               0x2
18497 #define PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT                                                                  0x4
18498 #define PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT                                                                   0x6
18499 #define PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT                                                                   0x7
18500 #define PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT                                                                   0x8
18501 #define PA_SC_RASTER_CONFIG__PKR_XSEL__SHIFT                                                                  0xa
18502 #define PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT                                                                  0xc
18503 #define PA_SC_RASTER_CONFIG__PKR_XSEL2__SHIFT                                                                 0xe
18504 #define PA_SC_RASTER_CONFIG__SC_MAP__SHIFT                                                                    0x10
18505 #define PA_SC_RASTER_CONFIG__SC_XSEL__SHIFT                                                                   0x12
18506 #define PA_SC_RASTER_CONFIG__SC_YSEL__SHIFT                                                                   0x14
18507 #define PA_SC_RASTER_CONFIG__SE_MAP__SHIFT                                                                    0x18
18508 #define PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT                                                                   0x1a
18509 #define PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT                                                                   0x1d
18510 #define PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK                                                                 0x00000003L
18511 #define PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK                                                                 0x0000000CL
18512 #define PA_SC_RASTER_CONFIG__RB_XSEL2_MASK                                                                    0x00000030L
18513 #define PA_SC_RASTER_CONFIG__RB_XSEL_MASK                                                                     0x00000040L
18514 #define PA_SC_RASTER_CONFIG__RB_YSEL_MASK                                                                     0x00000080L
18515 #define PA_SC_RASTER_CONFIG__PKR_MAP_MASK                                                                     0x00000300L
18516 #define PA_SC_RASTER_CONFIG__PKR_XSEL_MASK                                                                    0x00000C00L
18517 #define PA_SC_RASTER_CONFIG__PKR_YSEL_MASK                                                                    0x00003000L
18518 #define PA_SC_RASTER_CONFIG__PKR_XSEL2_MASK                                                                   0x0000C000L
18519 #define PA_SC_RASTER_CONFIG__SC_MAP_MASK                                                                      0x00030000L
18520 #define PA_SC_RASTER_CONFIG__SC_XSEL_MASK                                                                     0x000C0000L
18521 #define PA_SC_RASTER_CONFIG__SC_YSEL_MASK                                                                     0x00300000L
18522 #define PA_SC_RASTER_CONFIG__SE_MAP_MASK                                                                      0x03000000L
18523 #define PA_SC_RASTER_CONFIG__SE_XSEL_MASK                                                                     0x1C000000L
18524 #define PA_SC_RASTER_CONFIG__SE_YSEL_MASK                                                                     0xE0000000L
18525 //PA_SC_RASTER_CONFIG_1
18526 #define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP__SHIFT                                                             0x0
18527 #define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL__SHIFT                                                            0x2
18528 #define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL__SHIFT                                                            0x5
18529 #define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP_MASK                                                               0x00000003L
18530 #define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL_MASK                                                              0x0000001CL
18531 #define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL_MASK                                                              0x000000E0L
18532 //PA_SC_SCREEN_EXTENT_CONTROL
18533 #define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE__SHIFT                                                 0x0
18534 #define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE__SHIFT                                                  0x2
18535 #define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE_MASK                                                   0x00000003L
18536 #define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE_MASK                                                    0x0000000CL
18537 //PA_SC_TILE_STEERING_OVERRIDE
18538 #define PA_SC_TILE_STEERING_OVERRIDE__ENABLE__SHIFT                                                           0x0
18539 #define PA_SC_TILE_STEERING_OVERRIDE__NUM_SE__SHIFT                                                           0x1
18540 #define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE__SHIFT                                                    0x5
18541 #define PA_SC_TILE_STEERING_OVERRIDE__DISABLE_SRBSL_DB_OPTIMIZED_PACKING__SHIFT                               0x8
18542 #define PA_SC_TILE_STEERING_OVERRIDE__ENABLE_MASK                                                             0x00000001L
18543 #define PA_SC_TILE_STEERING_OVERRIDE__NUM_SE_MASK                                                             0x00000006L
18544 #define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE_MASK                                                      0x00000060L
18545 #define PA_SC_TILE_STEERING_OVERRIDE__DISABLE_SRBSL_DB_OPTIMIZED_PACKING_MASK                                 0x00000100L
18546 //CP_PERFMON_CNTX_CNTL
18547 #define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT                                                           0x1f
18548 #define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK                                                             0x80000000L
18549 //CP_PIPEID
18550 #define CP_PIPEID__PIPE_ID__SHIFT                                                                             0x0
18551 #define CP_PIPEID__PIPE_ID_MASK                                                                               0x00000003L
18552 //CP_RINGID
18553 #define CP_RINGID__RINGID__SHIFT                                                                              0x0
18554 #define CP_RINGID__RINGID_MASK                                                                                0x00000003L
18555 //CP_VMID
18556 #define CP_VMID__VMID__SHIFT                                                                                  0x0
18557 #define CP_VMID__VMID_MASK                                                                                    0x0000000FL
18558 //PA_SC_RIGHT_VERT_GRID
18559 #define PA_SC_RIGHT_VERT_GRID__LEFT_QTR__SHIFT                                                                0x0
18560 #define PA_SC_RIGHT_VERT_GRID__LEFT_HALF__SHIFT                                                               0x8
18561 #define PA_SC_RIGHT_VERT_GRID__RIGHT_HALF__SHIFT                                                              0x10
18562 #define PA_SC_RIGHT_VERT_GRID__RIGHT_QTR__SHIFT                                                               0x18
18563 #define PA_SC_RIGHT_VERT_GRID__LEFT_QTR_MASK                                                                  0x000000FFL
18564 #define PA_SC_RIGHT_VERT_GRID__LEFT_HALF_MASK                                                                 0x0000FF00L
18565 #define PA_SC_RIGHT_VERT_GRID__RIGHT_HALF_MASK                                                                0x00FF0000L
18566 #define PA_SC_RIGHT_VERT_GRID__RIGHT_QTR_MASK                                                                 0xFF000000L
18567 //PA_SC_LEFT_VERT_GRID
18568 #define PA_SC_LEFT_VERT_GRID__LEFT_QTR__SHIFT                                                                 0x0
18569 #define PA_SC_LEFT_VERT_GRID__LEFT_HALF__SHIFT                                                                0x8
18570 #define PA_SC_LEFT_VERT_GRID__RIGHT_HALF__SHIFT                                                               0x10
18571 #define PA_SC_LEFT_VERT_GRID__RIGHT_QTR__SHIFT                                                                0x18
18572 #define PA_SC_LEFT_VERT_GRID__LEFT_QTR_MASK                                                                   0x000000FFL
18573 #define PA_SC_LEFT_VERT_GRID__LEFT_HALF_MASK                                                                  0x0000FF00L
18574 #define PA_SC_LEFT_VERT_GRID__RIGHT_HALF_MASK                                                                 0x00FF0000L
18575 #define PA_SC_LEFT_VERT_GRID__RIGHT_QTR_MASK                                                                  0xFF000000L
18576 //PA_SC_HORIZ_GRID
18577 #define PA_SC_HORIZ_GRID__TOP_QTR__SHIFT                                                                      0x0
18578 #define PA_SC_HORIZ_GRID__TOP_HALF__SHIFT                                                                     0x8
18579 #define PA_SC_HORIZ_GRID__BOT_HALF__SHIFT                                                                     0x10
18580 #define PA_SC_HORIZ_GRID__BOT_QTR__SHIFT                                                                      0x18
18581 #define PA_SC_HORIZ_GRID__TOP_QTR_MASK                                                                        0x000000FFL
18582 #define PA_SC_HORIZ_GRID__TOP_HALF_MASK                                                                       0x0000FF00L
18583 #define PA_SC_HORIZ_GRID__BOT_HALF_MASK                                                                       0x00FF0000L
18584 #define PA_SC_HORIZ_GRID__BOT_QTR_MASK                                                                        0xFF000000L
18585 //VGT_MULTI_PRIM_IB_RESET_INDX
18586 #define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT                                                       0x0
18587 #define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK                                                         0xFFFFFFFFL
18588 //CB_BLEND_RED
18589 #define CB_BLEND_RED__BLEND_RED__SHIFT                                                                        0x0
18590 #define CB_BLEND_RED__BLEND_RED_MASK                                                                          0xFFFFFFFFL
18591 //CB_BLEND_GREEN
18592 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT                                                                    0x0
18593 #define CB_BLEND_GREEN__BLEND_GREEN_MASK                                                                      0xFFFFFFFFL
18594 //CB_BLEND_BLUE
18595 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT                                                                      0x0
18596 #define CB_BLEND_BLUE__BLEND_BLUE_MASK                                                                        0xFFFFFFFFL
18597 //CB_BLEND_ALPHA
18598 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT                                                                    0x0
18599 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK                                                                      0xFFFFFFFFL
18600 //CB_DCC_CONTROL
18601 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT                                                     0x0
18602 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE__SHIFT                                         0x1
18603 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK__SHIFT                                                   0x2
18604 #define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_AC01__SHIFT                                                   0x8
18605 #define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_SINGLE__SHIFT                                                 0x9
18606 #define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT                                                    0xa
18607 #define CB_DCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_AC01__SHIFT                                                    0xc
18608 #define CB_DCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_SINGLE__SHIFT                                                  0xd
18609 #define CB_DCC_CONTROL__ENABLE_ELIMFC_SKIP_OF_REG__SHIFT                                                      0xe
18610 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK                                                       0x00000001L
18611 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE_MASK                                           0x00000002L
18612 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK_MASK                                                     0x0000007CL
18613 #define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_AC01_MASK                                                     0x00000100L
18614 #define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_SINGLE_MASK                                                   0x00000200L
18615 #define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK                                                      0x00000400L
18616 #define CB_DCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_AC01_MASK                                                      0x00001000L
18617 #define CB_DCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_SINGLE_MASK                                                    0x00002000L
18618 #define CB_DCC_CONTROL__ENABLE_ELIMFC_SKIP_OF_REG_MASK                                                        0x00004000L
18619 //DB_STENCIL_CONTROL
18620 #define DB_STENCIL_CONTROL__STENCILFAIL__SHIFT                                                                0x0
18621 #define DB_STENCIL_CONTROL__STENCILZPASS__SHIFT                                                               0x4
18622 #define DB_STENCIL_CONTROL__STENCILZFAIL__SHIFT                                                               0x8
18623 #define DB_STENCIL_CONTROL__STENCILFAIL_BF__SHIFT                                                             0xc
18624 #define DB_STENCIL_CONTROL__STENCILZPASS_BF__SHIFT                                                            0x10
18625 #define DB_STENCIL_CONTROL__STENCILZFAIL_BF__SHIFT                                                            0x14
18626 #define DB_STENCIL_CONTROL__STENCILFAIL_MASK                                                                  0x0000000FL
18627 #define DB_STENCIL_CONTROL__STENCILZPASS_MASK                                                                 0x000000F0L
18628 #define DB_STENCIL_CONTROL__STENCILZFAIL_MASK                                                                 0x00000F00L
18629 #define DB_STENCIL_CONTROL__STENCILFAIL_BF_MASK                                                               0x0000F000L
18630 #define DB_STENCIL_CONTROL__STENCILZPASS_BF_MASK                                                              0x000F0000L
18631 #define DB_STENCIL_CONTROL__STENCILZFAIL_BF_MASK                                                              0x00F00000L
18632 //DB_STENCILREFMASK
18633 #define DB_STENCILREFMASK__STENCILTESTVAL__SHIFT                                                              0x0
18634 #define DB_STENCILREFMASK__STENCILMASK__SHIFT                                                                 0x8
18635 #define DB_STENCILREFMASK__STENCILWRITEMASK__SHIFT                                                            0x10
18636 #define DB_STENCILREFMASK__STENCILOPVAL__SHIFT                                                                0x18
18637 #define DB_STENCILREFMASK__STENCILTESTVAL_MASK                                                                0x000000FFL
18638 #define DB_STENCILREFMASK__STENCILMASK_MASK                                                                   0x0000FF00L
18639 #define DB_STENCILREFMASK__STENCILWRITEMASK_MASK                                                              0x00FF0000L
18640 #define DB_STENCILREFMASK__STENCILOPVAL_MASK                                                                  0xFF000000L
18641 //DB_STENCILREFMASK_BF
18642 #define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF__SHIFT                                                        0x0
18643 #define DB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT                                                           0x8
18644 #define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT                                                      0x10
18645 #define DB_STENCILREFMASK_BF__STENCILOPVAL_BF__SHIFT                                                          0x18
18646 #define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF_MASK                                                          0x000000FFL
18647 #define DB_STENCILREFMASK_BF__STENCILMASK_BF_MASK                                                             0x0000FF00L
18648 #define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK                                                        0x00FF0000L
18649 #define DB_STENCILREFMASK_BF__STENCILOPVAL_BF_MASK                                                            0xFF000000L
18650 //PA_CL_VPORT_XSCALE
18651 #define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT                                                               0x0
18652 #define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK                                                                 0xFFFFFFFFL
18653 //PA_CL_VPORT_XOFFSET
18654 #define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT                                                             0x0
18655 #define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK                                                               0xFFFFFFFFL
18656 //PA_CL_VPORT_YSCALE
18657 #define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT                                                               0x0
18658 #define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK                                                                 0xFFFFFFFFL
18659 //PA_CL_VPORT_YOFFSET
18660 #define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT                                                             0x0
18661 #define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK                                                               0xFFFFFFFFL
18662 //PA_CL_VPORT_ZSCALE
18663 #define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT                                                               0x0
18664 #define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK                                                                 0xFFFFFFFFL
18665 //PA_CL_VPORT_ZOFFSET
18666 #define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT                                                             0x0
18667 #define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK                                                               0xFFFFFFFFL
18668 //PA_CL_VPORT_XSCALE_1
18669 #define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE__SHIFT                                                             0x0
18670 #define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE_MASK                                                               0xFFFFFFFFL
18671 //PA_CL_VPORT_XOFFSET_1
18672 #define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET__SHIFT                                                           0x0
18673 #define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET_MASK                                                             0xFFFFFFFFL
18674 //PA_CL_VPORT_YSCALE_1
18675 #define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE__SHIFT                                                             0x0
18676 #define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE_MASK                                                               0xFFFFFFFFL
18677 //PA_CL_VPORT_YOFFSET_1
18678 #define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET__SHIFT                                                           0x0
18679 #define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET_MASK                                                             0xFFFFFFFFL
18680 //PA_CL_VPORT_ZSCALE_1
18681 #define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE__SHIFT                                                             0x0
18682 #define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE_MASK                                                               0xFFFFFFFFL
18683 //PA_CL_VPORT_ZOFFSET_1
18684 #define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET__SHIFT                                                           0x0
18685 #define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET_MASK                                                             0xFFFFFFFFL
18686 //PA_CL_VPORT_XSCALE_2
18687 #define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE__SHIFT                                                             0x0
18688 #define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE_MASK                                                               0xFFFFFFFFL
18689 //PA_CL_VPORT_XOFFSET_2
18690 #define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET__SHIFT                                                           0x0
18691 #define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET_MASK                                                             0xFFFFFFFFL
18692 //PA_CL_VPORT_YSCALE_2
18693 #define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE__SHIFT                                                             0x0
18694 #define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE_MASK                                                               0xFFFFFFFFL
18695 //PA_CL_VPORT_YOFFSET_2
18696 #define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET__SHIFT                                                           0x0
18697 #define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET_MASK                                                             0xFFFFFFFFL
18698 //PA_CL_VPORT_ZSCALE_2
18699 #define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE__SHIFT                                                             0x0
18700 #define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE_MASK                                                               0xFFFFFFFFL
18701 //PA_CL_VPORT_ZOFFSET_2
18702 #define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET__SHIFT                                                           0x0
18703 #define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET_MASK                                                             0xFFFFFFFFL
18704 //PA_CL_VPORT_XSCALE_3
18705 #define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE__SHIFT                                                             0x0
18706 #define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE_MASK                                                               0xFFFFFFFFL
18707 //PA_CL_VPORT_XOFFSET_3
18708 #define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET__SHIFT                                                           0x0
18709 #define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET_MASK                                                             0xFFFFFFFFL
18710 //PA_CL_VPORT_YSCALE_3
18711 #define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE__SHIFT                                                             0x0
18712 #define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE_MASK                                                               0xFFFFFFFFL
18713 //PA_CL_VPORT_YOFFSET_3
18714 #define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET__SHIFT                                                           0x0
18715 #define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET_MASK                                                             0xFFFFFFFFL
18716 //PA_CL_VPORT_ZSCALE_3
18717 #define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE__SHIFT                                                             0x0
18718 #define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE_MASK                                                               0xFFFFFFFFL
18719 //PA_CL_VPORT_ZOFFSET_3
18720 #define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET__SHIFT                                                           0x0
18721 #define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET_MASK                                                             0xFFFFFFFFL
18722 //PA_CL_VPORT_XSCALE_4
18723 #define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE__SHIFT                                                             0x0
18724 #define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE_MASK                                                               0xFFFFFFFFL
18725 //PA_CL_VPORT_XOFFSET_4
18726 #define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET__SHIFT                                                           0x0
18727 #define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET_MASK                                                             0xFFFFFFFFL
18728 //PA_CL_VPORT_YSCALE_4
18729 #define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE__SHIFT                                                             0x0
18730 #define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE_MASK                                                               0xFFFFFFFFL
18731 //PA_CL_VPORT_YOFFSET_4
18732 #define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET__SHIFT                                                           0x0
18733 #define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET_MASK                                                             0xFFFFFFFFL
18734 //PA_CL_VPORT_ZSCALE_4
18735 #define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE__SHIFT                                                             0x0
18736 #define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE_MASK                                                               0xFFFFFFFFL
18737 //PA_CL_VPORT_ZOFFSET_4
18738 #define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET__SHIFT                                                           0x0
18739 #define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET_MASK                                                             0xFFFFFFFFL
18740 //PA_CL_VPORT_XSCALE_5
18741 #define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE__SHIFT                                                             0x0
18742 #define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE_MASK                                                               0xFFFFFFFFL
18743 //PA_CL_VPORT_XOFFSET_5
18744 #define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET__SHIFT                                                           0x0
18745 #define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET_MASK                                                             0xFFFFFFFFL
18746 //PA_CL_VPORT_YSCALE_5
18747 #define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE__SHIFT                                                             0x0
18748 #define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE_MASK                                                               0xFFFFFFFFL
18749 //PA_CL_VPORT_YOFFSET_5
18750 #define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET__SHIFT                                                           0x0
18751 #define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET_MASK                                                             0xFFFFFFFFL
18752 //PA_CL_VPORT_ZSCALE_5
18753 #define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE__SHIFT                                                             0x0
18754 #define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE_MASK                                                               0xFFFFFFFFL
18755 //PA_CL_VPORT_ZOFFSET_5
18756 #define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET__SHIFT                                                           0x0
18757 #define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET_MASK                                                             0xFFFFFFFFL
18758 //PA_CL_VPORT_XSCALE_6
18759 #define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE__SHIFT                                                             0x0
18760 #define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE_MASK                                                               0xFFFFFFFFL
18761 //PA_CL_VPORT_XOFFSET_6
18762 #define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET__SHIFT                                                           0x0
18763 #define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET_MASK                                                             0xFFFFFFFFL
18764 //PA_CL_VPORT_YSCALE_6
18765 #define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE__SHIFT                                                             0x0
18766 #define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE_MASK                                                               0xFFFFFFFFL
18767 //PA_CL_VPORT_YOFFSET_6
18768 #define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET__SHIFT                                                           0x0
18769 #define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET_MASK                                                             0xFFFFFFFFL
18770 //PA_CL_VPORT_ZSCALE_6
18771 #define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE__SHIFT                                                             0x0
18772 #define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE_MASK                                                               0xFFFFFFFFL
18773 //PA_CL_VPORT_ZOFFSET_6
18774 #define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET__SHIFT                                                           0x0
18775 #define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET_MASK                                                             0xFFFFFFFFL
18776 //PA_CL_VPORT_XSCALE_7
18777 #define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE__SHIFT                                                             0x0
18778 #define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE_MASK                                                               0xFFFFFFFFL
18779 //PA_CL_VPORT_XOFFSET_7
18780 #define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET__SHIFT                                                           0x0
18781 #define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET_MASK                                                             0xFFFFFFFFL
18782 //PA_CL_VPORT_YSCALE_7
18783 #define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE__SHIFT                                                             0x0
18784 #define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE_MASK                                                               0xFFFFFFFFL
18785 //PA_CL_VPORT_YOFFSET_7
18786 #define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET__SHIFT                                                           0x0
18787 #define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET_MASK                                                             0xFFFFFFFFL
18788 //PA_CL_VPORT_ZSCALE_7
18789 #define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE__SHIFT                                                             0x0
18790 #define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE_MASK                                                               0xFFFFFFFFL
18791 //PA_CL_VPORT_ZOFFSET_7
18792 #define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET__SHIFT                                                           0x0
18793 #define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET_MASK                                                             0xFFFFFFFFL
18794 //PA_CL_VPORT_XSCALE_8
18795 #define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE__SHIFT                                                             0x0
18796 #define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE_MASK                                                               0xFFFFFFFFL
18797 //PA_CL_VPORT_XOFFSET_8
18798 #define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET__SHIFT                                                           0x0
18799 #define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET_MASK                                                             0xFFFFFFFFL
18800 //PA_CL_VPORT_YSCALE_8
18801 #define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE__SHIFT                                                             0x0
18802 #define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE_MASK                                                               0xFFFFFFFFL
18803 //PA_CL_VPORT_YOFFSET_8
18804 #define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET__SHIFT                                                           0x0
18805 #define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET_MASK                                                             0xFFFFFFFFL
18806 //PA_CL_VPORT_ZSCALE_8
18807 #define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE__SHIFT                                                             0x0
18808 #define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE_MASK                                                               0xFFFFFFFFL
18809 //PA_CL_VPORT_ZOFFSET_8
18810 #define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET__SHIFT                                                           0x0
18811 #define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET_MASK                                                             0xFFFFFFFFL
18812 //PA_CL_VPORT_XSCALE_9
18813 #define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE__SHIFT                                                             0x0
18814 #define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE_MASK                                                               0xFFFFFFFFL
18815 //PA_CL_VPORT_XOFFSET_9
18816 #define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET__SHIFT                                                           0x0
18817 #define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET_MASK                                                             0xFFFFFFFFL
18818 //PA_CL_VPORT_YSCALE_9
18819 #define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE__SHIFT                                                             0x0
18820 #define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE_MASK                                                               0xFFFFFFFFL
18821 //PA_CL_VPORT_YOFFSET_9
18822 #define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET__SHIFT                                                           0x0
18823 #define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET_MASK                                                             0xFFFFFFFFL
18824 //PA_CL_VPORT_ZSCALE_9
18825 #define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE__SHIFT                                                             0x0
18826 #define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE_MASK                                                               0xFFFFFFFFL
18827 //PA_CL_VPORT_ZOFFSET_9
18828 #define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET__SHIFT                                                           0x0
18829 #define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET_MASK                                                             0xFFFFFFFFL
18830 //PA_CL_VPORT_XSCALE_10
18831 #define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE__SHIFT                                                            0x0
18832 #define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE_MASK                                                              0xFFFFFFFFL
18833 //PA_CL_VPORT_XOFFSET_10
18834 #define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET__SHIFT                                                          0x0
18835 #define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET_MASK                                                            0xFFFFFFFFL
18836 //PA_CL_VPORT_YSCALE_10
18837 #define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE__SHIFT                                                            0x0
18838 #define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE_MASK                                                              0xFFFFFFFFL
18839 //PA_CL_VPORT_YOFFSET_10
18840 #define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET__SHIFT                                                          0x0
18841 #define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET_MASK                                                            0xFFFFFFFFL
18842 //PA_CL_VPORT_ZSCALE_10
18843 #define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE__SHIFT                                                            0x0
18844 #define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE_MASK                                                              0xFFFFFFFFL
18845 //PA_CL_VPORT_ZOFFSET_10
18846 #define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET__SHIFT                                                          0x0
18847 #define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET_MASK                                                            0xFFFFFFFFL
18848 //PA_CL_VPORT_XSCALE_11
18849 #define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE__SHIFT                                                            0x0
18850 #define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE_MASK                                                              0xFFFFFFFFL
18851 //PA_CL_VPORT_XOFFSET_11
18852 #define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET__SHIFT                                                          0x0
18853 #define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET_MASK                                                            0xFFFFFFFFL
18854 //PA_CL_VPORT_YSCALE_11
18855 #define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE__SHIFT                                                            0x0
18856 #define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE_MASK                                                              0xFFFFFFFFL
18857 //PA_CL_VPORT_YOFFSET_11
18858 #define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET__SHIFT                                                          0x0
18859 #define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET_MASK                                                            0xFFFFFFFFL
18860 //PA_CL_VPORT_ZSCALE_11
18861 #define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE__SHIFT                                                            0x0
18862 #define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE_MASK                                                              0xFFFFFFFFL
18863 //PA_CL_VPORT_ZOFFSET_11
18864 #define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET__SHIFT                                                          0x0
18865 #define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET_MASK                                                            0xFFFFFFFFL
18866 //PA_CL_VPORT_XSCALE_12
18867 #define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE__SHIFT                                                            0x0
18868 #define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE_MASK                                                              0xFFFFFFFFL
18869 //PA_CL_VPORT_XOFFSET_12
18870 #define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET__SHIFT                                                          0x0
18871 #define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET_MASK                                                            0xFFFFFFFFL
18872 //PA_CL_VPORT_YSCALE_12
18873 #define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE__SHIFT                                                            0x0
18874 #define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE_MASK                                                              0xFFFFFFFFL
18875 //PA_CL_VPORT_YOFFSET_12
18876 #define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET__SHIFT                                                          0x0
18877 #define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET_MASK                                                            0xFFFFFFFFL
18878 //PA_CL_VPORT_ZSCALE_12
18879 #define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE__SHIFT                                                            0x0
18880 #define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE_MASK                                                              0xFFFFFFFFL
18881 //PA_CL_VPORT_ZOFFSET_12
18882 #define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET__SHIFT                                                          0x0
18883 #define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET_MASK                                                            0xFFFFFFFFL
18884 //PA_CL_VPORT_XSCALE_13
18885 #define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE__SHIFT                                                            0x0
18886 #define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE_MASK                                                              0xFFFFFFFFL
18887 //PA_CL_VPORT_XOFFSET_13
18888 #define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET__SHIFT                                                          0x0
18889 #define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET_MASK                                                            0xFFFFFFFFL
18890 //PA_CL_VPORT_YSCALE_13
18891 #define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE__SHIFT                                                            0x0
18892 #define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE_MASK                                                              0xFFFFFFFFL
18893 //PA_CL_VPORT_YOFFSET_13
18894 #define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET__SHIFT                                                          0x0
18895 #define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET_MASK                                                            0xFFFFFFFFL
18896 //PA_CL_VPORT_ZSCALE_13
18897 #define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE__SHIFT                                                            0x0
18898 #define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE_MASK                                                              0xFFFFFFFFL
18899 //PA_CL_VPORT_ZOFFSET_13
18900 #define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET__SHIFT                                                          0x0
18901 #define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET_MASK                                                            0xFFFFFFFFL
18902 //PA_CL_VPORT_XSCALE_14
18903 #define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE__SHIFT                                                            0x0
18904 #define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE_MASK                                                              0xFFFFFFFFL
18905 //PA_CL_VPORT_XOFFSET_14
18906 #define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET__SHIFT                                                          0x0
18907 #define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET_MASK                                                            0xFFFFFFFFL
18908 //PA_CL_VPORT_YSCALE_14
18909 #define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE__SHIFT                                                            0x0
18910 #define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE_MASK                                                              0xFFFFFFFFL
18911 //PA_CL_VPORT_YOFFSET_14
18912 #define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET__SHIFT                                                          0x0
18913 #define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET_MASK                                                            0xFFFFFFFFL
18914 //PA_CL_VPORT_ZSCALE_14
18915 #define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE__SHIFT                                                            0x0
18916 #define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE_MASK                                                              0xFFFFFFFFL
18917 //PA_CL_VPORT_ZOFFSET_14
18918 #define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET__SHIFT                                                          0x0
18919 #define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET_MASK                                                            0xFFFFFFFFL
18920 //PA_CL_VPORT_XSCALE_15
18921 #define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE__SHIFT                                                            0x0
18922 #define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE_MASK                                                              0xFFFFFFFFL
18923 //PA_CL_VPORT_XOFFSET_15
18924 #define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET__SHIFT                                                          0x0
18925 #define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET_MASK                                                            0xFFFFFFFFL
18926 //PA_CL_VPORT_YSCALE_15
18927 #define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE__SHIFT                                                            0x0
18928 #define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE_MASK                                                              0xFFFFFFFFL
18929 //PA_CL_VPORT_YOFFSET_15
18930 #define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET__SHIFT                                                          0x0
18931 #define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET_MASK                                                            0xFFFFFFFFL
18932 //PA_CL_VPORT_ZSCALE_15
18933 #define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE__SHIFT                                                            0x0
18934 #define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE_MASK                                                              0xFFFFFFFFL
18935 //PA_CL_VPORT_ZOFFSET_15
18936 #define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET__SHIFT                                                          0x0
18937 #define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET_MASK                                                            0xFFFFFFFFL
18938 //PA_CL_UCP_0_X
18939 #define PA_CL_UCP_0_X__DATA_REGISTER__SHIFT                                                                   0x0
18940 #define PA_CL_UCP_0_X__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
18941 //PA_CL_UCP_0_Y
18942 #define PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT                                                                   0x0
18943 #define PA_CL_UCP_0_Y__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
18944 //PA_CL_UCP_0_Z
18945 #define PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT                                                                   0x0
18946 #define PA_CL_UCP_0_Z__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
18947 //PA_CL_UCP_0_W
18948 #define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT                                                                   0x0
18949 #define PA_CL_UCP_0_W__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
18950 //PA_CL_UCP_1_X
18951 #define PA_CL_UCP_1_X__DATA_REGISTER__SHIFT                                                                   0x0
18952 #define PA_CL_UCP_1_X__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
18953 //PA_CL_UCP_1_Y
18954 #define PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT                                                                   0x0
18955 #define PA_CL_UCP_1_Y__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
18956 //PA_CL_UCP_1_Z
18957 #define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT                                                                   0x0
18958 #define PA_CL_UCP_1_Z__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
18959 //PA_CL_UCP_1_W
18960 #define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT                                                                   0x0
18961 #define PA_CL_UCP_1_W__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
18962 //PA_CL_UCP_2_X
18963 #define PA_CL_UCP_2_X__DATA_REGISTER__SHIFT                                                                   0x0
18964 #define PA_CL_UCP_2_X__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
18965 //PA_CL_UCP_2_Y
18966 #define PA_CL_UCP_2_Y__DATA_REGISTER__SHIFT                                                                   0x0
18967 #define PA_CL_UCP_2_Y__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
18968 //PA_CL_UCP_2_Z
18969 #define PA_CL_UCP_2_Z__DATA_REGISTER__SHIFT                                                                   0x0
18970 #define PA_CL_UCP_2_Z__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
18971 //PA_CL_UCP_2_W
18972 #define PA_CL_UCP_2_W__DATA_REGISTER__SHIFT                                                                   0x0
18973 #define PA_CL_UCP_2_W__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
18974 //PA_CL_UCP_3_X
18975 #define PA_CL_UCP_3_X__DATA_REGISTER__SHIFT                                                                   0x0
18976 #define PA_CL_UCP_3_X__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
18977 //PA_CL_UCP_3_Y
18978 #define PA_CL_UCP_3_Y__DATA_REGISTER__SHIFT                                                                   0x0
18979 #define PA_CL_UCP_3_Y__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
18980 //PA_CL_UCP_3_Z
18981 #define PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT                                                                   0x0
18982 #define PA_CL_UCP_3_Z__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
18983 //PA_CL_UCP_3_W
18984 #define PA_CL_UCP_3_W__DATA_REGISTER__SHIFT                                                                   0x0
18985 #define PA_CL_UCP_3_W__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
18986 //PA_CL_UCP_4_X
18987 #define PA_CL_UCP_4_X__DATA_REGISTER__SHIFT                                                                   0x0
18988 #define PA_CL_UCP_4_X__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
18989 //PA_CL_UCP_4_Y
18990 #define PA_CL_UCP_4_Y__DATA_REGISTER__SHIFT                                                                   0x0
18991 #define PA_CL_UCP_4_Y__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
18992 //PA_CL_UCP_4_Z
18993 #define PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT                                                                   0x0
18994 #define PA_CL_UCP_4_Z__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
18995 //PA_CL_UCP_4_W
18996 #define PA_CL_UCP_4_W__DATA_REGISTER__SHIFT                                                                   0x0
18997 #define PA_CL_UCP_4_W__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
18998 //PA_CL_UCP_5_X
18999 #define PA_CL_UCP_5_X__DATA_REGISTER__SHIFT                                                                   0x0
19000 #define PA_CL_UCP_5_X__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
19001 //PA_CL_UCP_5_Y
19002 #define PA_CL_UCP_5_Y__DATA_REGISTER__SHIFT                                                                   0x0
19003 #define PA_CL_UCP_5_Y__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
19004 //PA_CL_UCP_5_Z
19005 #define PA_CL_UCP_5_Z__DATA_REGISTER__SHIFT                                                                   0x0
19006 #define PA_CL_UCP_5_Z__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
19007 //PA_CL_UCP_5_W
19008 #define PA_CL_UCP_5_W__DATA_REGISTER__SHIFT                                                                   0x0
19009 #define PA_CL_UCP_5_W__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
19010 //PA_CL_PROG_NEAR_CLIP_Z
19011 #define PA_CL_PROG_NEAR_CLIP_Z__DATA_REGISTER__SHIFT                                                          0x0
19012 #define PA_CL_PROG_NEAR_CLIP_Z__DATA_REGISTER_MASK                                                            0xFFFFFFFFL
19013 //SPI_PS_INPUT_CNTL_0
19014 #define SPI_PS_INPUT_CNTL_0__OFFSET__SHIFT                                                                    0x0
19015 #define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL__SHIFT                                                               0x8
19016 #define SPI_PS_INPUT_CNTL_0__FLAT_SHADE__SHIFT                                                                0xa
19017 #define SPI_PS_INPUT_CNTL_0__CYL_WRAP__SHIFT                                                                  0xd
19018 #define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX__SHIFT                                                             0x11
19019 #define SPI_PS_INPUT_CNTL_0__DUP__SHIFT                                                                       0x12
19020 #define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE__SHIFT                                                          0x13
19021 #define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1__SHIFT                                                         0x14
19022 #define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1__SHIFT                                                         0x15
19023 #define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1__SHIFT                                                       0x17
19024 #define SPI_PS_INPUT_CNTL_0__ATTR0_VALID__SHIFT                                                               0x18
19025 #define SPI_PS_INPUT_CNTL_0__ATTR1_VALID__SHIFT                                                               0x19
19026 #define SPI_PS_INPUT_CNTL_0__OFFSET_MASK                                                                      0x0000003FL
19027 #define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK                                                                 0x00000300L
19028 #define SPI_PS_INPUT_CNTL_0__FLAT_SHADE_MASK                                                                  0x00000400L
19029 #define SPI_PS_INPUT_CNTL_0__CYL_WRAP_MASK                                                                    0x0001E000L
19030 #define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_MASK                                                               0x00020000L
19031 #define SPI_PS_INPUT_CNTL_0__DUP_MASK                                                                         0x00040000L
19032 #define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE_MASK                                                            0x00080000L
19033 #define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1_MASK                                                           0x00100000L
19034 #define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1_MASK                                                           0x00600000L
19035 #define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1_MASK                                                         0x00800000L
19036 #define SPI_PS_INPUT_CNTL_0__ATTR0_VALID_MASK                                                                 0x01000000L
19037 #define SPI_PS_INPUT_CNTL_0__ATTR1_VALID_MASK                                                                 0x02000000L
19038 //SPI_PS_INPUT_CNTL_1
19039 #define SPI_PS_INPUT_CNTL_1__OFFSET__SHIFT                                                                    0x0
19040 #define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL__SHIFT                                                               0x8
19041 #define SPI_PS_INPUT_CNTL_1__FLAT_SHADE__SHIFT                                                                0xa
19042 #define SPI_PS_INPUT_CNTL_1__CYL_WRAP__SHIFT                                                                  0xd
19043 #define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX__SHIFT                                                             0x11
19044 #define SPI_PS_INPUT_CNTL_1__DUP__SHIFT                                                                       0x12
19045 #define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE__SHIFT                                                          0x13
19046 #define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1__SHIFT                                                         0x14
19047 #define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1__SHIFT                                                         0x15
19048 #define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1__SHIFT                                                       0x17
19049 #define SPI_PS_INPUT_CNTL_1__ATTR0_VALID__SHIFT                                                               0x18
19050 #define SPI_PS_INPUT_CNTL_1__ATTR1_VALID__SHIFT                                                               0x19
19051 #define SPI_PS_INPUT_CNTL_1__OFFSET_MASK                                                                      0x0000003FL
19052 #define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_MASK                                                                 0x00000300L
19053 #define SPI_PS_INPUT_CNTL_1__FLAT_SHADE_MASK                                                                  0x00000400L
19054 #define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK                                                                    0x0001E000L
19055 #define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_MASK                                                               0x00020000L
19056 #define SPI_PS_INPUT_CNTL_1__DUP_MASK                                                                         0x00040000L
19057 #define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE_MASK                                                            0x00080000L
19058 #define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1_MASK                                                           0x00100000L
19059 #define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1_MASK                                                           0x00600000L
19060 #define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1_MASK                                                         0x00800000L
19061 #define SPI_PS_INPUT_CNTL_1__ATTR0_VALID_MASK                                                                 0x01000000L
19062 #define SPI_PS_INPUT_CNTL_1__ATTR1_VALID_MASK                                                                 0x02000000L
19063 //SPI_PS_INPUT_CNTL_2
19064 #define SPI_PS_INPUT_CNTL_2__OFFSET__SHIFT                                                                    0x0
19065 #define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL__SHIFT                                                               0x8
19066 #define SPI_PS_INPUT_CNTL_2__FLAT_SHADE__SHIFT                                                                0xa
19067 #define SPI_PS_INPUT_CNTL_2__CYL_WRAP__SHIFT                                                                  0xd
19068 #define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX__SHIFT                                                             0x11
19069 #define SPI_PS_INPUT_CNTL_2__DUP__SHIFT                                                                       0x12
19070 #define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE__SHIFT                                                          0x13
19071 #define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1__SHIFT                                                         0x14
19072 #define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1__SHIFT                                                         0x15
19073 #define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1__SHIFT                                                       0x17
19074 #define SPI_PS_INPUT_CNTL_2__ATTR0_VALID__SHIFT                                                               0x18
19075 #define SPI_PS_INPUT_CNTL_2__ATTR1_VALID__SHIFT                                                               0x19
19076 #define SPI_PS_INPUT_CNTL_2__OFFSET_MASK                                                                      0x0000003FL
19077 #define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_MASK                                                                 0x00000300L
19078 #define SPI_PS_INPUT_CNTL_2__FLAT_SHADE_MASK                                                                  0x00000400L
19079 #define SPI_PS_INPUT_CNTL_2__CYL_WRAP_MASK                                                                    0x0001E000L
19080 #define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_MASK                                                               0x00020000L
19081 #define SPI_PS_INPUT_CNTL_2__DUP_MASK                                                                         0x00040000L
19082 #define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE_MASK                                                            0x00080000L
19083 #define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1_MASK                                                           0x00100000L
19084 #define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1_MASK                                                           0x00600000L
19085 #define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1_MASK                                                         0x00800000L
19086 #define SPI_PS_INPUT_CNTL_2__ATTR0_VALID_MASK                                                                 0x01000000L
19087 #define SPI_PS_INPUT_CNTL_2__ATTR1_VALID_MASK                                                                 0x02000000L
19088 //SPI_PS_INPUT_CNTL_3
19089 #define SPI_PS_INPUT_CNTL_3__OFFSET__SHIFT                                                                    0x0
19090 #define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL__SHIFT                                                               0x8
19091 #define SPI_PS_INPUT_CNTL_3__FLAT_SHADE__SHIFT                                                                0xa
19092 #define SPI_PS_INPUT_CNTL_3__CYL_WRAP__SHIFT                                                                  0xd
19093 #define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX__SHIFT                                                             0x11
19094 #define SPI_PS_INPUT_CNTL_3__DUP__SHIFT                                                                       0x12
19095 #define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE__SHIFT                                                          0x13
19096 #define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1__SHIFT                                                         0x14
19097 #define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1__SHIFT                                                         0x15
19098 #define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1__SHIFT                                                       0x17
19099 #define SPI_PS_INPUT_CNTL_3__ATTR0_VALID__SHIFT                                                               0x18
19100 #define SPI_PS_INPUT_CNTL_3__ATTR1_VALID__SHIFT                                                               0x19
19101 #define SPI_PS_INPUT_CNTL_3__OFFSET_MASK                                                                      0x0000003FL
19102 #define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_MASK                                                                 0x00000300L
19103 #define SPI_PS_INPUT_CNTL_3__FLAT_SHADE_MASK                                                                  0x00000400L
19104 #define SPI_PS_INPUT_CNTL_3__CYL_WRAP_MASK                                                                    0x0001E000L
19105 #define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_MASK                                                               0x00020000L
19106 #define SPI_PS_INPUT_CNTL_3__DUP_MASK                                                                         0x00040000L
19107 #define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE_MASK                                                            0x00080000L
19108 #define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1_MASK                                                           0x00100000L
19109 #define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1_MASK                                                           0x00600000L
19110 #define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1_MASK                                                         0x00800000L
19111 #define SPI_PS_INPUT_CNTL_3__ATTR0_VALID_MASK                                                                 0x01000000L
19112 #define SPI_PS_INPUT_CNTL_3__ATTR1_VALID_MASK                                                                 0x02000000L
19113 //SPI_PS_INPUT_CNTL_4
19114 #define SPI_PS_INPUT_CNTL_4__OFFSET__SHIFT                                                                    0x0
19115 #define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL__SHIFT                                                               0x8
19116 #define SPI_PS_INPUT_CNTL_4__FLAT_SHADE__SHIFT                                                                0xa
19117 #define SPI_PS_INPUT_CNTL_4__CYL_WRAP__SHIFT                                                                  0xd
19118 #define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX__SHIFT                                                             0x11
19119 #define SPI_PS_INPUT_CNTL_4__DUP__SHIFT                                                                       0x12
19120 #define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE__SHIFT                                                          0x13
19121 #define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1__SHIFT                                                         0x14
19122 #define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1__SHIFT                                                         0x15
19123 #define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1__SHIFT                                                       0x17
19124 #define SPI_PS_INPUT_CNTL_4__ATTR0_VALID__SHIFT                                                               0x18
19125 #define SPI_PS_INPUT_CNTL_4__ATTR1_VALID__SHIFT                                                               0x19
19126 #define SPI_PS_INPUT_CNTL_4__OFFSET_MASK                                                                      0x0000003FL
19127 #define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK                                                                 0x00000300L
19128 #define SPI_PS_INPUT_CNTL_4__FLAT_SHADE_MASK                                                                  0x00000400L
19129 #define SPI_PS_INPUT_CNTL_4__CYL_WRAP_MASK                                                                    0x0001E000L
19130 #define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_MASK                                                               0x00020000L
19131 #define SPI_PS_INPUT_CNTL_4__DUP_MASK                                                                         0x00040000L
19132 #define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE_MASK                                                            0x00080000L
19133 #define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1_MASK                                                           0x00100000L
19134 #define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1_MASK                                                           0x00600000L
19135 #define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1_MASK                                                         0x00800000L
19136 #define SPI_PS_INPUT_CNTL_4__ATTR0_VALID_MASK                                                                 0x01000000L
19137 #define SPI_PS_INPUT_CNTL_4__ATTR1_VALID_MASK                                                                 0x02000000L
19138 //SPI_PS_INPUT_CNTL_5
19139 #define SPI_PS_INPUT_CNTL_5__OFFSET__SHIFT                                                                    0x0
19140 #define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL__SHIFT                                                               0x8
19141 #define SPI_PS_INPUT_CNTL_5__FLAT_SHADE__SHIFT                                                                0xa
19142 #define SPI_PS_INPUT_CNTL_5__CYL_WRAP__SHIFT                                                                  0xd
19143 #define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX__SHIFT                                                             0x11
19144 #define SPI_PS_INPUT_CNTL_5__DUP__SHIFT                                                                       0x12
19145 #define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE__SHIFT                                                          0x13
19146 #define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1__SHIFT                                                         0x14
19147 #define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1__SHIFT                                                         0x15
19148 #define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1__SHIFT                                                       0x17
19149 #define SPI_PS_INPUT_CNTL_5__ATTR0_VALID__SHIFT                                                               0x18
19150 #define SPI_PS_INPUT_CNTL_5__ATTR1_VALID__SHIFT                                                               0x19
19151 #define SPI_PS_INPUT_CNTL_5__OFFSET_MASK                                                                      0x0000003FL
19152 #define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_MASK                                                                 0x00000300L
19153 #define SPI_PS_INPUT_CNTL_5__FLAT_SHADE_MASK                                                                  0x00000400L
19154 #define SPI_PS_INPUT_CNTL_5__CYL_WRAP_MASK                                                                    0x0001E000L
19155 #define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_MASK                                                               0x00020000L
19156 #define SPI_PS_INPUT_CNTL_5__DUP_MASK                                                                         0x00040000L
19157 #define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE_MASK                                                            0x00080000L
19158 #define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1_MASK                                                           0x00100000L
19159 #define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1_MASK                                                           0x00600000L
19160 #define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1_MASK                                                         0x00800000L
19161 #define SPI_PS_INPUT_CNTL_5__ATTR0_VALID_MASK                                                                 0x01000000L
19162 #define SPI_PS_INPUT_CNTL_5__ATTR1_VALID_MASK                                                                 0x02000000L
19163 //SPI_PS_INPUT_CNTL_6
19164 #define SPI_PS_INPUT_CNTL_6__OFFSET__SHIFT                                                                    0x0
19165 #define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL__SHIFT                                                               0x8
19166 #define SPI_PS_INPUT_CNTL_6__FLAT_SHADE__SHIFT                                                                0xa
19167 #define SPI_PS_INPUT_CNTL_6__CYL_WRAP__SHIFT                                                                  0xd
19168 #define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX__SHIFT                                                             0x11
19169 #define SPI_PS_INPUT_CNTL_6__DUP__SHIFT                                                                       0x12
19170 #define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE__SHIFT                                                          0x13
19171 #define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1__SHIFT                                                         0x14
19172 #define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1__SHIFT                                                         0x15
19173 #define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1__SHIFT                                                       0x17
19174 #define SPI_PS_INPUT_CNTL_6__ATTR0_VALID__SHIFT                                                               0x18
19175 #define SPI_PS_INPUT_CNTL_6__ATTR1_VALID__SHIFT                                                               0x19
19176 #define SPI_PS_INPUT_CNTL_6__OFFSET_MASK                                                                      0x0000003FL
19177 #define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_MASK                                                                 0x00000300L
19178 #define SPI_PS_INPUT_CNTL_6__FLAT_SHADE_MASK                                                                  0x00000400L
19179 #define SPI_PS_INPUT_CNTL_6__CYL_WRAP_MASK                                                                    0x0001E000L
19180 #define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_MASK                                                               0x00020000L
19181 #define SPI_PS_INPUT_CNTL_6__DUP_MASK                                                                         0x00040000L
19182 #define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE_MASK                                                            0x00080000L
19183 #define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1_MASK                                                           0x00100000L
19184 #define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1_MASK                                                           0x00600000L
19185 #define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1_MASK                                                         0x00800000L
19186 #define SPI_PS_INPUT_CNTL_6__ATTR0_VALID_MASK                                                                 0x01000000L
19187 #define SPI_PS_INPUT_CNTL_6__ATTR1_VALID_MASK                                                                 0x02000000L
19188 //SPI_PS_INPUT_CNTL_7
19189 #define SPI_PS_INPUT_CNTL_7__OFFSET__SHIFT                                                                    0x0
19190 #define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL__SHIFT                                                               0x8
19191 #define SPI_PS_INPUT_CNTL_7__FLAT_SHADE__SHIFT                                                                0xa
19192 #define SPI_PS_INPUT_CNTL_7__CYL_WRAP__SHIFT                                                                  0xd
19193 #define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX__SHIFT                                                             0x11
19194 #define SPI_PS_INPUT_CNTL_7__DUP__SHIFT                                                                       0x12
19195 #define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE__SHIFT                                                          0x13
19196 #define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1__SHIFT                                                         0x14
19197 #define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1__SHIFT                                                         0x15
19198 #define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1__SHIFT                                                       0x17
19199 #define SPI_PS_INPUT_CNTL_7__ATTR0_VALID__SHIFT                                                               0x18
19200 #define SPI_PS_INPUT_CNTL_7__ATTR1_VALID__SHIFT                                                               0x19
19201 #define SPI_PS_INPUT_CNTL_7__OFFSET_MASK                                                                      0x0000003FL
19202 #define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_MASK                                                                 0x00000300L
19203 #define SPI_PS_INPUT_CNTL_7__FLAT_SHADE_MASK                                                                  0x00000400L
19204 #define SPI_PS_INPUT_CNTL_7__CYL_WRAP_MASK                                                                    0x0001E000L
19205 #define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_MASK                                                               0x00020000L
19206 #define SPI_PS_INPUT_CNTL_7__DUP_MASK                                                                         0x00040000L
19207 #define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE_MASK                                                            0x00080000L
19208 #define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1_MASK                                                           0x00100000L
19209 #define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1_MASK                                                           0x00600000L
19210 #define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1_MASK                                                         0x00800000L
19211 #define SPI_PS_INPUT_CNTL_7__ATTR0_VALID_MASK                                                                 0x01000000L
19212 #define SPI_PS_INPUT_CNTL_7__ATTR1_VALID_MASK                                                                 0x02000000L
19213 //SPI_PS_INPUT_CNTL_8
19214 #define SPI_PS_INPUT_CNTL_8__OFFSET__SHIFT                                                                    0x0
19215 #define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL__SHIFT                                                               0x8
19216 #define SPI_PS_INPUT_CNTL_8__FLAT_SHADE__SHIFT                                                                0xa
19217 #define SPI_PS_INPUT_CNTL_8__CYL_WRAP__SHIFT                                                                  0xd
19218 #define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX__SHIFT                                                             0x11
19219 #define SPI_PS_INPUT_CNTL_8__DUP__SHIFT                                                                       0x12
19220 #define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE__SHIFT                                                          0x13
19221 #define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1__SHIFT                                                         0x14
19222 #define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1__SHIFT                                                         0x15
19223 #define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1__SHIFT                                                       0x17
19224 #define SPI_PS_INPUT_CNTL_8__ATTR0_VALID__SHIFT                                                               0x18
19225 #define SPI_PS_INPUT_CNTL_8__ATTR1_VALID__SHIFT                                                               0x19
19226 #define SPI_PS_INPUT_CNTL_8__OFFSET_MASK                                                                      0x0000003FL
19227 #define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_MASK                                                                 0x00000300L
19228 #define SPI_PS_INPUT_CNTL_8__FLAT_SHADE_MASK                                                                  0x00000400L
19229 #define SPI_PS_INPUT_CNTL_8__CYL_WRAP_MASK                                                                    0x0001E000L
19230 #define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_MASK                                                               0x00020000L
19231 #define SPI_PS_INPUT_CNTL_8__DUP_MASK                                                                         0x00040000L
19232 #define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE_MASK                                                            0x00080000L
19233 #define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1_MASK                                                           0x00100000L
19234 #define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1_MASK                                                           0x00600000L
19235 #define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1_MASK                                                         0x00800000L
19236 #define SPI_PS_INPUT_CNTL_8__ATTR0_VALID_MASK                                                                 0x01000000L
19237 #define SPI_PS_INPUT_CNTL_8__ATTR1_VALID_MASK                                                                 0x02000000L
19238 //SPI_PS_INPUT_CNTL_9
19239 #define SPI_PS_INPUT_CNTL_9__OFFSET__SHIFT                                                                    0x0
19240 #define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL__SHIFT                                                               0x8
19241 #define SPI_PS_INPUT_CNTL_9__FLAT_SHADE__SHIFT                                                                0xa
19242 #define SPI_PS_INPUT_CNTL_9__CYL_WRAP__SHIFT                                                                  0xd
19243 #define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX__SHIFT                                                             0x11
19244 #define SPI_PS_INPUT_CNTL_9__DUP__SHIFT                                                                       0x12
19245 #define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE__SHIFT                                                          0x13
19246 #define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1__SHIFT                                                         0x14
19247 #define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1__SHIFT                                                         0x15
19248 #define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1__SHIFT                                                       0x17
19249 #define SPI_PS_INPUT_CNTL_9__ATTR0_VALID__SHIFT                                                               0x18
19250 #define SPI_PS_INPUT_CNTL_9__ATTR1_VALID__SHIFT                                                               0x19
19251 #define SPI_PS_INPUT_CNTL_9__OFFSET_MASK                                                                      0x0000003FL
19252 #define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_MASK                                                                 0x00000300L
19253 #define SPI_PS_INPUT_CNTL_9__FLAT_SHADE_MASK                                                                  0x00000400L
19254 #define SPI_PS_INPUT_CNTL_9__CYL_WRAP_MASK                                                                    0x0001E000L
19255 #define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_MASK                                                               0x00020000L
19256 #define SPI_PS_INPUT_CNTL_9__DUP_MASK                                                                         0x00040000L
19257 #define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE_MASK                                                            0x00080000L
19258 #define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1_MASK                                                           0x00100000L
19259 #define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1_MASK                                                           0x00600000L
19260 #define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1_MASK                                                         0x00800000L
19261 #define SPI_PS_INPUT_CNTL_9__ATTR0_VALID_MASK                                                                 0x01000000L
19262 #define SPI_PS_INPUT_CNTL_9__ATTR1_VALID_MASK                                                                 0x02000000L
19263 //SPI_PS_INPUT_CNTL_10
19264 #define SPI_PS_INPUT_CNTL_10__OFFSET__SHIFT                                                                   0x0
19265 #define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL__SHIFT                                                              0x8
19266 #define SPI_PS_INPUT_CNTL_10__FLAT_SHADE__SHIFT                                                               0xa
19267 #define SPI_PS_INPUT_CNTL_10__CYL_WRAP__SHIFT                                                                 0xd
19268 #define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX__SHIFT                                                            0x11
19269 #define SPI_PS_INPUT_CNTL_10__DUP__SHIFT                                                                      0x12
19270 #define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE__SHIFT                                                         0x13
19271 #define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
19272 #define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
19273 #define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1__SHIFT                                                      0x17
19274 #define SPI_PS_INPUT_CNTL_10__ATTR0_VALID__SHIFT                                                              0x18
19275 #define SPI_PS_INPUT_CNTL_10__ATTR1_VALID__SHIFT                                                              0x19
19276 #define SPI_PS_INPUT_CNTL_10__OFFSET_MASK                                                                     0x0000003FL
19277 #define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_MASK                                                                0x00000300L
19278 #define SPI_PS_INPUT_CNTL_10__FLAT_SHADE_MASK                                                                 0x00000400L
19279 #define SPI_PS_INPUT_CNTL_10__CYL_WRAP_MASK                                                                   0x0001E000L
19280 #define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_MASK                                                              0x00020000L
19281 #define SPI_PS_INPUT_CNTL_10__DUP_MASK                                                                        0x00040000L
19282 #define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE_MASK                                                           0x00080000L
19283 #define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
19284 #define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
19285 #define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1_MASK                                                        0x00800000L
19286 #define SPI_PS_INPUT_CNTL_10__ATTR0_VALID_MASK                                                                0x01000000L
19287 #define SPI_PS_INPUT_CNTL_10__ATTR1_VALID_MASK                                                                0x02000000L
19288 //SPI_PS_INPUT_CNTL_11
19289 #define SPI_PS_INPUT_CNTL_11__OFFSET__SHIFT                                                                   0x0
19290 #define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL__SHIFT                                                              0x8
19291 #define SPI_PS_INPUT_CNTL_11__FLAT_SHADE__SHIFT                                                               0xa
19292 #define SPI_PS_INPUT_CNTL_11__CYL_WRAP__SHIFT                                                                 0xd
19293 #define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX__SHIFT                                                            0x11
19294 #define SPI_PS_INPUT_CNTL_11__DUP__SHIFT                                                                      0x12
19295 #define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE__SHIFT                                                         0x13
19296 #define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
19297 #define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
19298 #define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1__SHIFT                                                      0x17
19299 #define SPI_PS_INPUT_CNTL_11__ATTR0_VALID__SHIFT                                                              0x18
19300 #define SPI_PS_INPUT_CNTL_11__ATTR1_VALID__SHIFT                                                              0x19
19301 #define SPI_PS_INPUT_CNTL_11__OFFSET_MASK                                                                     0x0000003FL
19302 #define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_MASK                                                                0x00000300L
19303 #define SPI_PS_INPUT_CNTL_11__FLAT_SHADE_MASK                                                                 0x00000400L
19304 #define SPI_PS_INPUT_CNTL_11__CYL_WRAP_MASK                                                                   0x0001E000L
19305 #define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_MASK                                                              0x00020000L
19306 #define SPI_PS_INPUT_CNTL_11__DUP_MASK                                                                        0x00040000L
19307 #define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE_MASK                                                           0x00080000L
19308 #define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
19309 #define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
19310 #define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1_MASK                                                        0x00800000L
19311 #define SPI_PS_INPUT_CNTL_11__ATTR0_VALID_MASK                                                                0x01000000L
19312 #define SPI_PS_INPUT_CNTL_11__ATTR1_VALID_MASK                                                                0x02000000L
19313 //SPI_PS_INPUT_CNTL_12
19314 #define SPI_PS_INPUT_CNTL_12__OFFSET__SHIFT                                                                   0x0
19315 #define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL__SHIFT                                                              0x8
19316 #define SPI_PS_INPUT_CNTL_12__FLAT_SHADE__SHIFT                                                               0xa
19317 #define SPI_PS_INPUT_CNTL_12__CYL_WRAP__SHIFT                                                                 0xd
19318 #define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX__SHIFT                                                            0x11
19319 #define SPI_PS_INPUT_CNTL_12__DUP__SHIFT                                                                      0x12
19320 #define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE__SHIFT                                                         0x13
19321 #define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
19322 #define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
19323 #define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1__SHIFT                                                      0x17
19324 #define SPI_PS_INPUT_CNTL_12__ATTR0_VALID__SHIFT                                                              0x18
19325 #define SPI_PS_INPUT_CNTL_12__ATTR1_VALID__SHIFT                                                              0x19
19326 #define SPI_PS_INPUT_CNTL_12__OFFSET_MASK                                                                     0x0000003FL
19327 #define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_MASK                                                                0x00000300L
19328 #define SPI_PS_INPUT_CNTL_12__FLAT_SHADE_MASK                                                                 0x00000400L
19329 #define SPI_PS_INPUT_CNTL_12__CYL_WRAP_MASK                                                                   0x0001E000L
19330 #define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_MASK                                                              0x00020000L
19331 #define SPI_PS_INPUT_CNTL_12__DUP_MASK                                                                        0x00040000L
19332 #define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE_MASK                                                           0x00080000L
19333 #define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
19334 #define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
19335 #define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1_MASK                                                        0x00800000L
19336 #define SPI_PS_INPUT_CNTL_12__ATTR0_VALID_MASK                                                                0x01000000L
19337 #define SPI_PS_INPUT_CNTL_12__ATTR1_VALID_MASK                                                                0x02000000L
19338 //SPI_PS_INPUT_CNTL_13
19339 #define SPI_PS_INPUT_CNTL_13__OFFSET__SHIFT                                                                   0x0
19340 #define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL__SHIFT                                                              0x8
19341 #define SPI_PS_INPUT_CNTL_13__FLAT_SHADE__SHIFT                                                               0xa
19342 #define SPI_PS_INPUT_CNTL_13__CYL_WRAP__SHIFT                                                                 0xd
19343 #define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX__SHIFT                                                            0x11
19344 #define SPI_PS_INPUT_CNTL_13__DUP__SHIFT                                                                      0x12
19345 #define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE__SHIFT                                                         0x13
19346 #define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
19347 #define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
19348 #define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1__SHIFT                                                      0x17
19349 #define SPI_PS_INPUT_CNTL_13__ATTR0_VALID__SHIFT                                                              0x18
19350 #define SPI_PS_INPUT_CNTL_13__ATTR1_VALID__SHIFT                                                              0x19
19351 #define SPI_PS_INPUT_CNTL_13__OFFSET_MASK                                                                     0x0000003FL
19352 #define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_MASK                                                                0x00000300L
19353 #define SPI_PS_INPUT_CNTL_13__FLAT_SHADE_MASK                                                                 0x00000400L
19354 #define SPI_PS_INPUT_CNTL_13__CYL_WRAP_MASK                                                                   0x0001E000L
19355 #define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_MASK                                                              0x00020000L
19356 #define SPI_PS_INPUT_CNTL_13__DUP_MASK                                                                        0x00040000L
19357 #define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE_MASK                                                           0x00080000L
19358 #define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
19359 #define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
19360 #define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1_MASK                                                        0x00800000L
19361 #define SPI_PS_INPUT_CNTL_13__ATTR0_VALID_MASK                                                                0x01000000L
19362 #define SPI_PS_INPUT_CNTL_13__ATTR1_VALID_MASK                                                                0x02000000L
19363 //SPI_PS_INPUT_CNTL_14
19364 #define SPI_PS_INPUT_CNTL_14__OFFSET__SHIFT                                                                   0x0
19365 #define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL__SHIFT                                                              0x8
19366 #define SPI_PS_INPUT_CNTL_14__FLAT_SHADE__SHIFT                                                               0xa
19367 #define SPI_PS_INPUT_CNTL_14__CYL_WRAP__SHIFT                                                                 0xd
19368 #define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX__SHIFT                                                            0x11
19369 #define SPI_PS_INPUT_CNTL_14__DUP__SHIFT                                                                      0x12
19370 #define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE__SHIFT                                                         0x13
19371 #define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
19372 #define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
19373 #define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1__SHIFT                                                      0x17
19374 #define SPI_PS_INPUT_CNTL_14__ATTR0_VALID__SHIFT                                                              0x18
19375 #define SPI_PS_INPUT_CNTL_14__ATTR1_VALID__SHIFT                                                              0x19
19376 #define SPI_PS_INPUT_CNTL_14__OFFSET_MASK                                                                     0x0000003FL
19377 #define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_MASK                                                                0x00000300L
19378 #define SPI_PS_INPUT_CNTL_14__FLAT_SHADE_MASK                                                                 0x00000400L
19379 #define SPI_PS_INPUT_CNTL_14__CYL_WRAP_MASK                                                                   0x0001E000L
19380 #define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_MASK                                                              0x00020000L
19381 #define SPI_PS_INPUT_CNTL_14__DUP_MASK                                                                        0x00040000L
19382 #define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE_MASK                                                           0x00080000L
19383 #define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
19384 #define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
19385 #define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1_MASK                                                        0x00800000L
19386 #define SPI_PS_INPUT_CNTL_14__ATTR0_VALID_MASK                                                                0x01000000L
19387 #define SPI_PS_INPUT_CNTL_14__ATTR1_VALID_MASK                                                                0x02000000L
19388 //SPI_PS_INPUT_CNTL_15
19389 #define SPI_PS_INPUT_CNTL_15__OFFSET__SHIFT                                                                   0x0
19390 #define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL__SHIFT                                                              0x8
19391 #define SPI_PS_INPUT_CNTL_15__FLAT_SHADE__SHIFT                                                               0xa
19392 #define SPI_PS_INPUT_CNTL_15__CYL_WRAP__SHIFT                                                                 0xd
19393 #define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX__SHIFT                                                            0x11
19394 #define SPI_PS_INPUT_CNTL_15__DUP__SHIFT                                                                      0x12
19395 #define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE__SHIFT                                                         0x13
19396 #define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
19397 #define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
19398 #define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1__SHIFT                                                      0x17
19399 #define SPI_PS_INPUT_CNTL_15__ATTR0_VALID__SHIFT                                                              0x18
19400 #define SPI_PS_INPUT_CNTL_15__ATTR1_VALID__SHIFT                                                              0x19
19401 #define SPI_PS_INPUT_CNTL_15__OFFSET_MASK                                                                     0x0000003FL
19402 #define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_MASK                                                                0x00000300L
19403 #define SPI_PS_INPUT_CNTL_15__FLAT_SHADE_MASK                                                                 0x00000400L
19404 #define SPI_PS_INPUT_CNTL_15__CYL_WRAP_MASK                                                                   0x0001E000L
19405 #define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_MASK                                                              0x00020000L
19406 #define SPI_PS_INPUT_CNTL_15__DUP_MASK                                                                        0x00040000L
19407 #define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE_MASK                                                           0x00080000L
19408 #define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
19409 #define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
19410 #define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1_MASK                                                        0x00800000L
19411 #define SPI_PS_INPUT_CNTL_15__ATTR0_VALID_MASK                                                                0x01000000L
19412 #define SPI_PS_INPUT_CNTL_15__ATTR1_VALID_MASK                                                                0x02000000L
19413 //SPI_PS_INPUT_CNTL_16
19414 #define SPI_PS_INPUT_CNTL_16__OFFSET__SHIFT                                                                   0x0
19415 #define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL__SHIFT                                                              0x8
19416 #define SPI_PS_INPUT_CNTL_16__FLAT_SHADE__SHIFT                                                               0xa
19417 #define SPI_PS_INPUT_CNTL_16__CYL_WRAP__SHIFT                                                                 0xd
19418 #define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX__SHIFT                                                            0x11
19419 #define SPI_PS_INPUT_CNTL_16__DUP__SHIFT                                                                      0x12
19420 #define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE__SHIFT                                                         0x13
19421 #define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
19422 #define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
19423 #define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1__SHIFT                                                      0x17
19424 #define SPI_PS_INPUT_CNTL_16__ATTR0_VALID__SHIFT                                                              0x18
19425 #define SPI_PS_INPUT_CNTL_16__ATTR1_VALID__SHIFT                                                              0x19
19426 #define SPI_PS_INPUT_CNTL_16__OFFSET_MASK                                                                     0x0000003FL
19427 #define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_MASK                                                                0x00000300L
19428 #define SPI_PS_INPUT_CNTL_16__FLAT_SHADE_MASK                                                                 0x00000400L
19429 #define SPI_PS_INPUT_CNTL_16__CYL_WRAP_MASK                                                                   0x0001E000L
19430 #define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_MASK                                                              0x00020000L
19431 #define SPI_PS_INPUT_CNTL_16__DUP_MASK                                                                        0x00040000L
19432 #define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE_MASK                                                           0x00080000L
19433 #define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
19434 #define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
19435 #define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1_MASK                                                        0x00800000L
19436 #define SPI_PS_INPUT_CNTL_16__ATTR0_VALID_MASK                                                                0x01000000L
19437 #define SPI_PS_INPUT_CNTL_16__ATTR1_VALID_MASK                                                                0x02000000L
19438 //SPI_PS_INPUT_CNTL_17
19439 #define SPI_PS_INPUT_CNTL_17__OFFSET__SHIFT                                                                   0x0
19440 #define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL__SHIFT                                                              0x8
19441 #define SPI_PS_INPUT_CNTL_17__FLAT_SHADE__SHIFT                                                               0xa
19442 #define SPI_PS_INPUT_CNTL_17__CYL_WRAP__SHIFT                                                                 0xd
19443 #define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX__SHIFT                                                            0x11
19444 #define SPI_PS_INPUT_CNTL_17__DUP__SHIFT                                                                      0x12
19445 #define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE__SHIFT                                                         0x13
19446 #define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
19447 #define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
19448 #define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1__SHIFT                                                      0x17
19449 #define SPI_PS_INPUT_CNTL_17__ATTR0_VALID__SHIFT                                                              0x18
19450 #define SPI_PS_INPUT_CNTL_17__ATTR1_VALID__SHIFT                                                              0x19
19451 #define SPI_PS_INPUT_CNTL_17__OFFSET_MASK                                                                     0x0000003FL
19452 #define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_MASK                                                                0x00000300L
19453 #define SPI_PS_INPUT_CNTL_17__FLAT_SHADE_MASK                                                                 0x00000400L
19454 #define SPI_PS_INPUT_CNTL_17__CYL_WRAP_MASK                                                                   0x0001E000L
19455 #define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_MASK                                                              0x00020000L
19456 #define SPI_PS_INPUT_CNTL_17__DUP_MASK                                                                        0x00040000L
19457 #define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE_MASK                                                           0x00080000L
19458 #define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
19459 #define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
19460 #define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1_MASK                                                        0x00800000L
19461 #define SPI_PS_INPUT_CNTL_17__ATTR0_VALID_MASK                                                                0x01000000L
19462 #define SPI_PS_INPUT_CNTL_17__ATTR1_VALID_MASK                                                                0x02000000L
19463 //SPI_PS_INPUT_CNTL_18
19464 #define SPI_PS_INPUT_CNTL_18__OFFSET__SHIFT                                                                   0x0
19465 #define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL__SHIFT                                                              0x8
19466 #define SPI_PS_INPUT_CNTL_18__FLAT_SHADE__SHIFT                                                               0xa
19467 #define SPI_PS_INPUT_CNTL_18__CYL_WRAP__SHIFT                                                                 0xd
19468 #define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX__SHIFT                                                            0x11
19469 #define SPI_PS_INPUT_CNTL_18__DUP__SHIFT                                                                      0x12
19470 #define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE__SHIFT                                                         0x13
19471 #define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
19472 #define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
19473 #define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1__SHIFT                                                      0x17
19474 #define SPI_PS_INPUT_CNTL_18__ATTR0_VALID__SHIFT                                                              0x18
19475 #define SPI_PS_INPUT_CNTL_18__ATTR1_VALID__SHIFT                                                              0x19
19476 #define SPI_PS_INPUT_CNTL_18__OFFSET_MASK                                                                     0x0000003FL
19477 #define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_MASK                                                                0x00000300L
19478 #define SPI_PS_INPUT_CNTL_18__FLAT_SHADE_MASK                                                                 0x00000400L
19479 #define SPI_PS_INPUT_CNTL_18__CYL_WRAP_MASK                                                                   0x0001E000L
19480 #define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_MASK                                                              0x00020000L
19481 #define SPI_PS_INPUT_CNTL_18__DUP_MASK                                                                        0x00040000L
19482 #define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE_MASK                                                           0x00080000L
19483 #define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
19484 #define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
19485 #define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1_MASK                                                        0x00800000L
19486 #define SPI_PS_INPUT_CNTL_18__ATTR0_VALID_MASK                                                                0x01000000L
19487 #define SPI_PS_INPUT_CNTL_18__ATTR1_VALID_MASK                                                                0x02000000L
19488 //SPI_PS_INPUT_CNTL_19
19489 #define SPI_PS_INPUT_CNTL_19__OFFSET__SHIFT                                                                   0x0
19490 #define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL__SHIFT                                                              0x8
19491 #define SPI_PS_INPUT_CNTL_19__FLAT_SHADE__SHIFT                                                               0xa
19492 #define SPI_PS_INPUT_CNTL_19__CYL_WRAP__SHIFT                                                                 0xd
19493 #define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX__SHIFT                                                            0x11
19494 #define SPI_PS_INPUT_CNTL_19__DUP__SHIFT                                                                      0x12
19495 #define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE__SHIFT                                                         0x13
19496 #define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
19497 #define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
19498 #define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1__SHIFT                                                      0x17
19499 #define SPI_PS_INPUT_CNTL_19__ATTR0_VALID__SHIFT                                                              0x18
19500 #define SPI_PS_INPUT_CNTL_19__ATTR1_VALID__SHIFT                                                              0x19
19501 #define SPI_PS_INPUT_CNTL_19__OFFSET_MASK                                                                     0x0000003FL
19502 #define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_MASK                                                                0x00000300L
19503 #define SPI_PS_INPUT_CNTL_19__FLAT_SHADE_MASK                                                                 0x00000400L
19504 #define SPI_PS_INPUT_CNTL_19__CYL_WRAP_MASK                                                                   0x0001E000L
19505 #define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_MASK                                                              0x00020000L
19506 #define SPI_PS_INPUT_CNTL_19__DUP_MASK                                                                        0x00040000L
19507 #define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE_MASK                                                           0x00080000L
19508 #define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
19509 #define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
19510 #define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1_MASK                                                        0x00800000L
19511 #define SPI_PS_INPUT_CNTL_19__ATTR0_VALID_MASK                                                                0x01000000L
19512 #define SPI_PS_INPUT_CNTL_19__ATTR1_VALID_MASK                                                                0x02000000L
19513 //SPI_PS_INPUT_CNTL_20
19514 #define SPI_PS_INPUT_CNTL_20__OFFSET__SHIFT                                                                   0x0
19515 #define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL__SHIFT                                                              0x8
19516 #define SPI_PS_INPUT_CNTL_20__FLAT_SHADE__SHIFT                                                               0xa
19517 #define SPI_PS_INPUT_CNTL_20__DUP__SHIFT                                                                      0x12
19518 #define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE__SHIFT                                                         0x13
19519 #define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
19520 #define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
19521 #define SPI_PS_INPUT_CNTL_20__ATTR0_VALID__SHIFT                                                              0x18
19522 #define SPI_PS_INPUT_CNTL_20__ATTR1_VALID__SHIFT                                                              0x19
19523 #define SPI_PS_INPUT_CNTL_20__OFFSET_MASK                                                                     0x0000003FL
19524 #define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_MASK                                                                0x00000300L
19525 #define SPI_PS_INPUT_CNTL_20__FLAT_SHADE_MASK                                                                 0x00000400L
19526 #define SPI_PS_INPUT_CNTL_20__DUP_MASK                                                                        0x00040000L
19527 #define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE_MASK                                                           0x00080000L
19528 #define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
19529 #define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
19530 #define SPI_PS_INPUT_CNTL_20__ATTR0_VALID_MASK                                                                0x01000000L
19531 #define SPI_PS_INPUT_CNTL_20__ATTR1_VALID_MASK                                                                0x02000000L
19532 //SPI_PS_INPUT_CNTL_21
19533 #define SPI_PS_INPUT_CNTL_21__OFFSET__SHIFT                                                                   0x0
19534 #define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL__SHIFT                                                              0x8
19535 #define SPI_PS_INPUT_CNTL_21__FLAT_SHADE__SHIFT                                                               0xa
19536 #define SPI_PS_INPUT_CNTL_21__DUP__SHIFT                                                                      0x12
19537 #define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE__SHIFT                                                         0x13
19538 #define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
19539 #define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
19540 #define SPI_PS_INPUT_CNTL_21__ATTR0_VALID__SHIFT                                                              0x18
19541 #define SPI_PS_INPUT_CNTL_21__ATTR1_VALID__SHIFT                                                              0x19
19542 #define SPI_PS_INPUT_CNTL_21__OFFSET_MASK                                                                     0x0000003FL
19543 #define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_MASK                                                                0x00000300L
19544 #define SPI_PS_INPUT_CNTL_21__FLAT_SHADE_MASK                                                                 0x00000400L
19545 #define SPI_PS_INPUT_CNTL_21__DUP_MASK                                                                        0x00040000L
19546 #define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE_MASK                                                           0x00080000L
19547 #define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
19548 #define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
19549 #define SPI_PS_INPUT_CNTL_21__ATTR0_VALID_MASK                                                                0x01000000L
19550 #define SPI_PS_INPUT_CNTL_21__ATTR1_VALID_MASK                                                                0x02000000L
19551 //SPI_PS_INPUT_CNTL_22
19552 #define SPI_PS_INPUT_CNTL_22__OFFSET__SHIFT                                                                   0x0
19553 #define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL__SHIFT                                                              0x8
19554 #define SPI_PS_INPUT_CNTL_22__FLAT_SHADE__SHIFT                                                               0xa
19555 #define SPI_PS_INPUT_CNTL_22__DUP__SHIFT                                                                      0x12
19556 #define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE__SHIFT                                                         0x13
19557 #define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
19558 #define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
19559 #define SPI_PS_INPUT_CNTL_22__ATTR0_VALID__SHIFT                                                              0x18
19560 #define SPI_PS_INPUT_CNTL_22__ATTR1_VALID__SHIFT                                                              0x19
19561 #define SPI_PS_INPUT_CNTL_22__OFFSET_MASK                                                                     0x0000003FL
19562 #define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_MASK                                                                0x00000300L
19563 #define SPI_PS_INPUT_CNTL_22__FLAT_SHADE_MASK                                                                 0x00000400L
19564 #define SPI_PS_INPUT_CNTL_22__DUP_MASK                                                                        0x00040000L
19565 #define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE_MASK                                                           0x00080000L
19566 #define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
19567 #define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
19568 #define SPI_PS_INPUT_CNTL_22__ATTR0_VALID_MASK                                                                0x01000000L
19569 #define SPI_PS_INPUT_CNTL_22__ATTR1_VALID_MASK                                                                0x02000000L
19570 //SPI_PS_INPUT_CNTL_23
19571 #define SPI_PS_INPUT_CNTL_23__OFFSET__SHIFT                                                                   0x0
19572 #define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL__SHIFT                                                              0x8
19573 #define SPI_PS_INPUT_CNTL_23__FLAT_SHADE__SHIFT                                                               0xa
19574 #define SPI_PS_INPUT_CNTL_23__DUP__SHIFT                                                                      0x12
19575 #define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE__SHIFT                                                         0x13
19576 #define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
19577 #define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
19578 #define SPI_PS_INPUT_CNTL_23__ATTR0_VALID__SHIFT                                                              0x18
19579 #define SPI_PS_INPUT_CNTL_23__ATTR1_VALID__SHIFT                                                              0x19
19580 #define SPI_PS_INPUT_CNTL_23__OFFSET_MASK                                                                     0x0000003FL
19581 #define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_MASK                                                                0x00000300L
19582 #define SPI_PS_INPUT_CNTL_23__FLAT_SHADE_MASK                                                                 0x00000400L
19583 #define SPI_PS_INPUT_CNTL_23__DUP_MASK                                                                        0x00040000L
19584 #define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE_MASK                                                           0x00080000L
19585 #define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
19586 #define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
19587 #define SPI_PS_INPUT_CNTL_23__ATTR0_VALID_MASK                                                                0x01000000L
19588 #define SPI_PS_INPUT_CNTL_23__ATTR1_VALID_MASK                                                                0x02000000L
19589 //SPI_PS_INPUT_CNTL_24
19590 #define SPI_PS_INPUT_CNTL_24__OFFSET__SHIFT                                                                   0x0
19591 #define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL__SHIFT                                                              0x8
19592 #define SPI_PS_INPUT_CNTL_24__FLAT_SHADE__SHIFT                                                               0xa
19593 #define SPI_PS_INPUT_CNTL_24__DUP__SHIFT                                                                      0x12
19594 #define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE__SHIFT                                                         0x13
19595 #define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
19596 #define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
19597 #define SPI_PS_INPUT_CNTL_24__ATTR0_VALID__SHIFT                                                              0x18
19598 #define SPI_PS_INPUT_CNTL_24__ATTR1_VALID__SHIFT                                                              0x19
19599 #define SPI_PS_INPUT_CNTL_24__OFFSET_MASK                                                                     0x0000003FL
19600 #define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_MASK                                                                0x00000300L
19601 #define SPI_PS_INPUT_CNTL_24__FLAT_SHADE_MASK                                                                 0x00000400L
19602 #define SPI_PS_INPUT_CNTL_24__DUP_MASK                                                                        0x00040000L
19603 #define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE_MASK                                                           0x00080000L
19604 #define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
19605 #define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
19606 #define SPI_PS_INPUT_CNTL_24__ATTR0_VALID_MASK                                                                0x01000000L
19607 #define SPI_PS_INPUT_CNTL_24__ATTR1_VALID_MASK                                                                0x02000000L
19608 //SPI_PS_INPUT_CNTL_25
19609 #define SPI_PS_INPUT_CNTL_25__OFFSET__SHIFT                                                                   0x0
19610 #define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL__SHIFT                                                              0x8
19611 #define SPI_PS_INPUT_CNTL_25__FLAT_SHADE__SHIFT                                                               0xa
19612 #define SPI_PS_INPUT_CNTL_25__DUP__SHIFT                                                                      0x12
19613 #define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE__SHIFT                                                         0x13
19614 #define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
19615 #define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
19616 #define SPI_PS_INPUT_CNTL_25__ATTR0_VALID__SHIFT                                                              0x18
19617 #define SPI_PS_INPUT_CNTL_25__ATTR1_VALID__SHIFT                                                              0x19
19618 #define SPI_PS_INPUT_CNTL_25__OFFSET_MASK                                                                     0x0000003FL
19619 #define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_MASK                                                                0x00000300L
19620 #define SPI_PS_INPUT_CNTL_25__FLAT_SHADE_MASK                                                                 0x00000400L
19621 #define SPI_PS_INPUT_CNTL_25__DUP_MASK                                                                        0x00040000L
19622 #define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE_MASK                                                           0x00080000L
19623 #define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
19624 #define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
19625 #define SPI_PS_INPUT_CNTL_25__ATTR0_VALID_MASK                                                                0x01000000L
19626 #define SPI_PS_INPUT_CNTL_25__ATTR1_VALID_MASK                                                                0x02000000L
19627 //SPI_PS_INPUT_CNTL_26
19628 #define SPI_PS_INPUT_CNTL_26__OFFSET__SHIFT                                                                   0x0
19629 #define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL__SHIFT                                                              0x8
19630 #define SPI_PS_INPUT_CNTL_26__FLAT_SHADE__SHIFT                                                               0xa
19631 #define SPI_PS_INPUT_CNTL_26__DUP__SHIFT                                                                      0x12
19632 #define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE__SHIFT                                                         0x13
19633 #define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
19634 #define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
19635 #define SPI_PS_INPUT_CNTL_26__ATTR0_VALID__SHIFT                                                              0x18
19636 #define SPI_PS_INPUT_CNTL_26__ATTR1_VALID__SHIFT                                                              0x19
19637 #define SPI_PS_INPUT_CNTL_26__OFFSET_MASK                                                                     0x0000003FL
19638 #define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_MASK                                                                0x00000300L
19639 #define SPI_PS_INPUT_CNTL_26__FLAT_SHADE_MASK                                                                 0x00000400L
19640 #define SPI_PS_INPUT_CNTL_26__DUP_MASK                                                                        0x00040000L
19641 #define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE_MASK                                                           0x00080000L
19642 #define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
19643 #define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
19644 #define SPI_PS_INPUT_CNTL_26__ATTR0_VALID_MASK                                                                0x01000000L
19645 #define SPI_PS_INPUT_CNTL_26__ATTR1_VALID_MASK                                                                0x02000000L
19646 //SPI_PS_INPUT_CNTL_27
19647 #define SPI_PS_INPUT_CNTL_27__OFFSET__SHIFT                                                                   0x0
19648 #define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL__SHIFT                                                              0x8
19649 #define SPI_PS_INPUT_CNTL_27__FLAT_SHADE__SHIFT                                                               0xa
19650 #define SPI_PS_INPUT_CNTL_27__DUP__SHIFT                                                                      0x12
19651 #define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE__SHIFT                                                         0x13
19652 #define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
19653 #define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
19654 #define SPI_PS_INPUT_CNTL_27__ATTR0_VALID__SHIFT                                                              0x18
19655 #define SPI_PS_INPUT_CNTL_27__ATTR1_VALID__SHIFT                                                              0x19
19656 #define SPI_PS_INPUT_CNTL_27__OFFSET_MASK                                                                     0x0000003FL
19657 #define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_MASK                                                                0x00000300L
19658 #define SPI_PS_INPUT_CNTL_27__FLAT_SHADE_MASK                                                                 0x00000400L
19659 #define SPI_PS_INPUT_CNTL_27__DUP_MASK                                                                        0x00040000L
19660 #define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE_MASK                                                           0x00080000L
19661 #define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
19662 #define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
19663 #define SPI_PS_INPUT_CNTL_27__ATTR0_VALID_MASK                                                                0x01000000L
19664 #define SPI_PS_INPUT_CNTL_27__ATTR1_VALID_MASK                                                                0x02000000L
19665 //SPI_PS_INPUT_CNTL_28
19666 #define SPI_PS_INPUT_CNTL_28__OFFSET__SHIFT                                                                   0x0
19667 #define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL__SHIFT                                                              0x8
19668 #define SPI_PS_INPUT_CNTL_28__FLAT_SHADE__SHIFT                                                               0xa
19669 #define SPI_PS_INPUT_CNTL_28__DUP__SHIFT                                                                      0x12
19670 #define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE__SHIFT                                                         0x13
19671 #define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
19672 #define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
19673 #define SPI_PS_INPUT_CNTL_28__ATTR0_VALID__SHIFT                                                              0x18
19674 #define SPI_PS_INPUT_CNTL_28__ATTR1_VALID__SHIFT                                                              0x19
19675 #define SPI_PS_INPUT_CNTL_28__OFFSET_MASK                                                                     0x0000003FL
19676 #define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_MASK                                                                0x00000300L
19677 #define SPI_PS_INPUT_CNTL_28__FLAT_SHADE_MASK                                                                 0x00000400L
19678 #define SPI_PS_INPUT_CNTL_28__DUP_MASK                                                                        0x00040000L
19679 #define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE_MASK                                                           0x00080000L
19680 #define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
19681 #define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
19682 #define SPI_PS_INPUT_CNTL_28__ATTR0_VALID_MASK                                                                0x01000000L
19683 #define SPI_PS_INPUT_CNTL_28__ATTR1_VALID_MASK                                                                0x02000000L
19684 //SPI_PS_INPUT_CNTL_29
19685 #define SPI_PS_INPUT_CNTL_29__OFFSET__SHIFT                                                                   0x0
19686 #define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL__SHIFT                                                              0x8
19687 #define SPI_PS_INPUT_CNTL_29__FLAT_SHADE__SHIFT                                                               0xa
19688 #define SPI_PS_INPUT_CNTL_29__DUP__SHIFT                                                                      0x12
19689 #define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE__SHIFT                                                         0x13
19690 #define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
19691 #define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
19692 #define SPI_PS_INPUT_CNTL_29__ATTR0_VALID__SHIFT                                                              0x18
19693 #define SPI_PS_INPUT_CNTL_29__ATTR1_VALID__SHIFT                                                              0x19
19694 #define SPI_PS_INPUT_CNTL_29__OFFSET_MASK                                                                     0x0000003FL
19695 #define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_MASK                                                                0x00000300L
19696 #define SPI_PS_INPUT_CNTL_29__FLAT_SHADE_MASK                                                                 0x00000400L
19697 #define SPI_PS_INPUT_CNTL_29__DUP_MASK                                                                        0x00040000L
19698 #define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE_MASK                                                           0x00080000L
19699 #define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
19700 #define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
19701 #define SPI_PS_INPUT_CNTL_29__ATTR0_VALID_MASK                                                                0x01000000L
19702 #define SPI_PS_INPUT_CNTL_29__ATTR1_VALID_MASK                                                                0x02000000L
19703 //SPI_PS_INPUT_CNTL_30
19704 #define SPI_PS_INPUT_CNTL_30__OFFSET__SHIFT                                                                   0x0
19705 #define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL__SHIFT                                                              0x8
19706 #define SPI_PS_INPUT_CNTL_30__FLAT_SHADE__SHIFT                                                               0xa
19707 #define SPI_PS_INPUT_CNTL_30__DUP__SHIFT                                                                      0x12
19708 #define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE__SHIFT                                                         0x13
19709 #define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
19710 #define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
19711 #define SPI_PS_INPUT_CNTL_30__ATTR0_VALID__SHIFT                                                              0x18
19712 #define SPI_PS_INPUT_CNTL_30__ATTR1_VALID__SHIFT                                                              0x19
19713 #define SPI_PS_INPUT_CNTL_30__OFFSET_MASK                                                                     0x0000003FL
19714 #define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_MASK                                                                0x00000300L
19715 #define SPI_PS_INPUT_CNTL_30__FLAT_SHADE_MASK                                                                 0x00000400L
19716 #define SPI_PS_INPUT_CNTL_30__DUP_MASK                                                                        0x00040000L
19717 #define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE_MASK                                                           0x00080000L
19718 #define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
19719 #define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
19720 #define SPI_PS_INPUT_CNTL_30__ATTR0_VALID_MASK                                                                0x01000000L
19721 #define SPI_PS_INPUT_CNTL_30__ATTR1_VALID_MASK                                                                0x02000000L
19722 //SPI_PS_INPUT_CNTL_31
19723 #define SPI_PS_INPUT_CNTL_31__OFFSET__SHIFT                                                                   0x0
19724 #define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL__SHIFT                                                              0x8
19725 #define SPI_PS_INPUT_CNTL_31__FLAT_SHADE__SHIFT                                                               0xa
19726 #define SPI_PS_INPUT_CNTL_31__DUP__SHIFT                                                                      0x12
19727 #define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE__SHIFT                                                         0x13
19728 #define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
19729 #define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
19730 #define SPI_PS_INPUT_CNTL_31__ATTR0_VALID__SHIFT                                                              0x18
19731 #define SPI_PS_INPUT_CNTL_31__ATTR1_VALID__SHIFT                                                              0x19
19732 #define SPI_PS_INPUT_CNTL_31__OFFSET_MASK                                                                     0x0000003FL
19733 #define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_MASK                                                                0x00000300L
19734 #define SPI_PS_INPUT_CNTL_31__FLAT_SHADE_MASK                                                                 0x00000400L
19735 #define SPI_PS_INPUT_CNTL_31__DUP_MASK                                                                        0x00040000L
19736 #define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE_MASK                                                           0x00080000L
19737 #define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
19738 #define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
19739 #define SPI_PS_INPUT_CNTL_31__ATTR0_VALID_MASK                                                                0x01000000L
19740 #define SPI_PS_INPUT_CNTL_31__ATTR1_VALID_MASK                                                                0x02000000L
19741 //SPI_VS_OUT_CONFIG
19742 #define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT__SHIFT                                                             0x1
19743 #define SPI_VS_OUT_CONFIG__VS_HALF_PACK__SHIFT                                                                0x6
19744 #define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT_MASK                                                               0x0000003EL
19745 #define SPI_VS_OUT_CONFIG__VS_HALF_PACK_MASK                                                                  0x00000040L
19746 //SPI_PS_INPUT_ENA
19747 #define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA__SHIFT                                                             0x0
19748 #define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA__SHIFT                                                             0x1
19749 #define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA__SHIFT                                                           0x2
19750 #define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA__SHIFT                                                         0x3
19751 #define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA__SHIFT                                                            0x4
19752 #define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA__SHIFT                                                            0x5
19753 #define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA__SHIFT                                                          0x6
19754 #define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA__SHIFT                                                         0x7
19755 #define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA__SHIFT                                                              0x8
19756 #define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA__SHIFT                                                              0x9
19757 #define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA__SHIFT                                                              0xa
19758 #define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA__SHIFT                                                              0xb
19759 #define SPI_PS_INPUT_ENA__FRONT_FACE_ENA__SHIFT                                                               0xc
19760 #define SPI_PS_INPUT_ENA__ANCILLARY_ENA__SHIFT                                                                0xd
19761 #define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA__SHIFT                                                          0xe
19762 #define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA__SHIFT                                                             0xf
19763 #define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA_MASK                                                               0x00000001L
19764 #define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA_MASK                                                               0x00000002L
19765 #define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA_MASK                                                             0x00000004L
19766 #define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA_MASK                                                           0x00000008L
19767 #define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA_MASK                                                              0x00000010L
19768 #define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA_MASK                                                              0x00000020L
19769 #define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA_MASK                                                            0x00000040L
19770 #define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA_MASK                                                           0x00000080L
19771 #define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA_MASK                                                                0x00000100L
19772 #define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA_MASK                                                                0x00000200L
19773 #define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA_MASK                                                                0x00000400L
19774 #define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA_MASK                                                                0x00000800L
19775 #define SPI_PS_INPUT_ENA__FRONT_FACE_ENA_MASK                                                                 0x00001000L
19776 #define SPI_PS_INPUT_ENA__ANCILLARY_ENA_MASK                                                                  0x00002000L
19777 #define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA_MASK                                                            0x00004000L
19778 #define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA_MASK                                                               0x00008000L
19779 //SPI_PS_INPUT_ADDR
19780 #define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA__SHIFT                                                            0x0
19781 #define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA__SHIFT                                                            0x1
19782 #define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA__SHIFT                                                          0x2
19783 #define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA__SHIFT                                                        0x3
19784 #define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA__SHIFT                                                           0x4
19785 #define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA__SHIFT                                                           0x5
19786 #define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA__SHIFT                                                         0x6
19787 #define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA__SHIFT                                                        0x7
19788 #define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA__SHIFT                                                             0x8
19789 #define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA__SHIFT                                                             0x9
19790 #define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA__SHIFT                                                             0xa
19791 #define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA__SHIFT                                                             0xb
19792 #define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA__SHIFT                                                              0xc
19793 #define SPI_PS_INPUT_ADDR__ANCILLARY_ENA__SHIFT                                                               0xd
19794 #define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA__SHIFT                                                         0xe
19795 #define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA__SHIFT                                                            0xf
19796 #define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA_MASK                                                              0x00000001L
19797 #define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA_MASK                                                              0x00000002L
19798 #define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA_MASK                                                            0x00000004L
19799 #define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA_MASK                                                          0x00000008L
19800 #define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA_MASK                                                             0x00000010L
19801 #define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA_MASK                                                             0x00000020L
19802 #define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA_MASK                                                           0x00000040L
19803 #define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA_MASK                                                          0x00000080L
19804 #define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA_MASK                                                               0x00000100L
19805 #define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA_MASK                                                               0x00000200L
19806 #define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA_MASK                                                               0x00000400L
19807 #define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA_MASK                                                               0x00000800L
19808 #define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA_MASK                                                                0x00001000L
19809 #define SPI_PS_INPUT_ADDR__ANCILLARY_ENA_MASK                                                                 0x00002000L
19810 #define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA_MASK                                                           0x00004000L
19811 #define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA_MASK                                                              0x00008000L
19812 //SPI_INTERP_CONTROL_0
19813 #define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT                                                           0x0
19814 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA__SHIFT                                                           0x1
19815 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X__SHIFT                                                        0x2
19816 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y__SHIFT                                                        0x5
19817 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z__SHIFT                                                        0x8
19818 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W__SHIFT                                                        0xb
19819 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1__SHIFT                                                         0xe
19820 #define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA_MASK                                                             0x00000001L
19821 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA_MASK                                                             0x00000002L
19822 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X_MASK                                                          0x0000001CL
19823 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y_MASK                                                          0x000000E0L
19824 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z_MASK                                                          0x00000700L
19825 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W_MASK                                                          0x00003800L
19826 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1_MASK                                                           0x00004000L
19827 //SPI_PS_IN_CONTROL
19828 #define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT                                                                  0x0
19829 #define SPI_PS_IN_CONTROL__PARAM_GEN__SHIFT                                                                   0x6
19830 #define SPI_PS_IN_CONTROL__OFFCHIP_PARAM_EN__SHIFT                                                            0x7
19831 #define SPI_PS_IN_CONTROL__LATE_PC_DEALLOC__SHIFT                                                             0x8
19832 #define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE__SHIFT                                                         0xe
19833 #define SPI_PS_IN_CONTROL__NUM_INTERP_MASK                                                                    0x0000003FL
19834 #define SPI_PS_IN_CONTROL__PARAM_GEN_MASK                                                                     0x00000040L
19835 #define SPI_PS_IN_CONTROL__OFFCHIP_PARAM_EN_MASK                                                              0x00000080L
19836 #define SPI_PS_IN_CONTROL__LATE_PC_DEALLOC_MASK                                                               0x00000100L
19837 #define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE_MASK                                                           0x00004000L
19838 //SPI_BARYC_CNTL
19839 #define SPI_BARYC_CNTL__PERSP_CENTER_CNTL__SHIFT                                                              0x0
19840 #define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL__SHIFT                                                            0x4
19841 #define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL__SHIFT                                                             0x8
19842 #define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL__SHIFT                                                           0xc
19843 #define SPI_BARYC_CNTL__POS_FLOAT_LOCATION__SHIFT                                                             0x10
19844 #define SPI_BARYC_CNTL__POS_FLOAT_ULC__SHIFT                                                                  0x14
19845 #define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS__SHIFT                                                            0x18
19846 #define SPI_BARYC_CNTL__PERSP_CENTER_CNTL_MASK                                                                0x00000001L
19847 #define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL_MASK                                                              0x00000010L
19848 #define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL_MASK                                                               0x00000100L
19849 #define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL_MASK                                                             0x00001000L
19850 #define SPI_BARYC_CNTL__POS_FLOAT_LOCATION_MASK                                                               0x00030000L
19851 #define SPI_BARYC_CNTL__POS_FLOAT_ULC_MASK                                                                    0x00100000L
19852 #define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS_MASK                                                              0x01000000L
19853 //SPI_TMPRING_SIZE
19854 #define SPI_TMPRING_SIZE__WAVES__SHIFT                                                                        0x0
19855 #define SPI_TMPRING_SIZE__WAVESIZE__SHIFT                                                                     0xc
19856 #define SPI_TMPRING_SIZE__WAVES_MASK                                                                          0x00000FFFL
19857 #define SPI_TMPRING_SIZE__WAVESIZE_MASK                                                                       0x01FFF000L
19858 //SPI_SHADER_POS_FORMAT
19859 #define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT__SHIFT                                                      0x0
19860 #define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT__SHIFT                                                      0x4
19861 #define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT__SHIFT                                                      0x8
19862 #define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT__SHIFT                                                      0xc
19863 #define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT_MASK                                                        0x0000000FL
19864 #define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT_MASK                                                        0x000000F0L
19865 #define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT_MASK                                                        0x00000F00L
19866 #define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT_MASK                                                        0x0000F000L
19867 //SPI_SHADER_Z_FORMAT
19868 #define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT__SHIFT                                                           0x0
19869 #define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT_MASK                                                             0x0000000FL
19870 //SPI_SHADER_COL_FORMAT
19871 #define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT__SHIFT                                                      0x0
19872 #define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT__SHIFT                                                      0x4
19873 #define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT__SHIFT                                                      0x8
19874 #define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT__SHIFT                                                      0xc
19875 #define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT__SHIFT                                                      0x10
19876 #define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT__SHIFT                                                      0x14
19877 #define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT__SHIFT                                                      0x18
19878 #define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT__SHIFT                                                      0x1c
19879 #define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT_MASK                                                        0x0000000FL
19880 #define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT_MASK                                                        0x000000F0L
19881 #define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT_MASK                                                        0x00000F00L
19882 #define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT_MASK                                                        0x0000F000L
19883 #define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT_MASK                                                        0x000F0000L
19884 #define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT_MASK                                                        0x00F00000L
19885 #define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT_MASK                                                        0x0F000000L
19886 #define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT_MASK                                                        0xF0000000L
19887 //CB_BLEND0_CONTROL
19888 #define CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT                                                              0x0
19889 #define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT                                                              0x5
19890 #define CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT                                                             0x8
19891 #define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT                                                              0x10
19892 #define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT                                                              0x15
19893 #define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT                                                             0x18
19894 #define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT                                                        0x1d
19895 #define CB_BLEND0_CONTROL__ENABLE__SHIFT                                                                      0x1e
19896 #define CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT                                                                0x1f
19897 #define CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK                                                                0x0000001FL
19898 #define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK                                                                0x000000E0L
19899 #define CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK                                                               0x00001F00L
19900 #define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK                                                                0x001F0000L
19901 #define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK                                                                0x00E00000L
19902 #define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK                                                               0x1F000000L
19903 #define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK                                                          0x20000000L
19904 #define CB_BLEND0_CONTROL__ENABLE_MASK                                                                        0x40000000L
19905 #define CB_BLEND0_CONTROL__DISABLE_ROP3_MASK                                                                  0x80000000L
19906 //CB_BLEND1_CONTROL
19907 #define CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT                                                              0x0
19908 #define CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT                                                              0x5
19909 #define CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT                                                             0x8
19910 #define CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT                                                              0x10
19911 #define CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT                                                              0x15
19912 #define CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT                                                             0x18
19913 #define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT                                                        0x1d
19914 #define CB_BLEND1_CONTROL__ENABLE__SHIFT                                                                      0x1e
19915 #define CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT                                                                0x1f
19916 #define CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK                                                                0x0000001FL
19917 #define CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK                                                                0x000000E0L
19918 #define CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK                                                               0x00001F00L
19919 #define CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK                                                                0x001F0000L
19920 #define CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK                                                                0x00E00000L
19921 #define CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK                                                               0x1F000000L
19922 #define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK                                                          0x20000000L
19923 #define CB_BLEND1_CONTROL__ENABLE_MASK                                                                        0x40000000L
19924 #define CB_BLEND1_CONTROL__DISABLE_ROP3_MASK                                                                  0x80000000L
19925 //CB_BLEND2_CONTROL
19926 #define CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT                                                              0x0
19927 #define CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT                                                              0x5
19928 #define CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT                                                             0x8
19929 #define CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT                                                              0x10
19930 #define CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT                                                              0x15
19931 #define CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT                                                             0x18
19932 #define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT                                                        0x1d
19933 #define CB_BLEND2_CONTROL__ENABLE__SHIFT                                                                      0x1e
19934 #define CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT                                                                0x1f
19935 #define CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK                                                                0x0000001FL
19936 #define CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK                                                                0x000000E0L
19937 #define CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK                                                               0x00001F00L
19938 #define CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK                                                                0x001F0000L
19939 #define CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK                                                                0x00E00000L
19940 #define CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK                                                               0x1F000000L
19941 #define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK                                                          0x20000000L
19942 #define CB_BLEND2_CONTROL__ENABLE_MASK                                                                        0x40000000L
19943 #define CB_BLEND2_CONTROL__DISABLE_ROP3_MASK                                                                  0x80000000L
19944 //CB_BLEND3_CONTROL
19945 #define CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT                                                              0x0
19946 #define CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT                                                              0x5
19947 #define CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT                                                             0x8
19948 #define CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT                                                              0x10
19949 #define CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT                                                              0x15
19950 #define CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT                                                             0x18
19951 #define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT                                                        0x1d
19952 #define CB_BLEND3_CONTROL__ENABLE__SHIFT                                                                      0x1e
19953 #define CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT                                                                0x1f
19954 #define CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK                                                                0x0000001FL
19955 #define CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK                                                                0x000000E0L
19956 #define CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK                                                               0x00001F00L
19957 #define CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK                                                                0x001F0000L
19958 #define CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK                                                                0x00E00000L
19959 #define CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK                                                               0x1F000000L
19960 #define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK                                                          0x20000000L
19961 #define CB_BLEND3_CONTROL__ENABLE_MASK                                                                        0x40000000L
19962 #define CB_BLEND3_CONTROL__DISABLE_ROP3_MASK                                                                  0x80000000L
19963 //CB_BLEND4_CONTROL
19964 #define CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT                                                              0x0
19965 #define CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT                                                              0x5
19966 #define CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT                                                             0x8
19967 #define CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT                                                              0x10
19968 #define CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT                                                              0x15
19969 #define CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT                                                             0x18
19970 #define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT                                                        0x1d
19971 #define CB_BLEND4_CONTROL__ENABLE__SHIFT                                                                      0x1e
19972 #define CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT                                                                0x1f
19973 #define CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK                                                                0x0000001FL
19974 #define CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK                                                                0x000000E0L
19975 #define CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK                                                               0x00001F00L
19976 #define CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK                                                                0x001F0000L
19977 #define CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK                                                                0x00E00000L
19978 #define CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK                                                               0x1F000000L
19979 #define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK                                                          0x20000000L
19980 #define CB_BLEND4_CONTROL__ENABLE_MASK                                                                        0x40000000L
19981 #define CB_BLEND4_CONTROL__DISABLE_ROP3_MASK                                                                  0x80000000L
19982 //CB_BLEND5_CONTROL
19983 #define CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT                                                              0x0
19984 #define CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT                                                              0x5
19985 #define CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT                                                             0x8
19986 #define CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT                                                              0x10
19987 #define CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT                                                              0x15
19988 #define CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT                                                             0x18
19989 #define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT                                                        0x1d
19990 #define CB_BLEND5_CONTROL__ENABLE__SHIFT                                                                      0x1e
19991 #define CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT                                                                0x1f
19992 #define CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK                                                                0x0000001FL
19993 #define CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK                                                                0x000000E0L
19994 #define CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK                                                               0x00001F00L
19995 #define CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK                                                                0x001F0000L
19996 #define CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK                                                                0x00E00000L
19997 #define CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK                                                               0x1F000000L
19998 #define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK                                                          0x20000000L
19999 #define CB_BLEND5_CONTROL__ENABLE_MASK                                                                        0x40000000L
20000 #define CB_BLEND5_CONTROL__DISABLE_ROP3_MASK                                                                  0x80000000L
20001 //CB_BLEND6_CONTROL
20002 #define CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT                                                              0x0
20003 #define CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT                                                              0x5
20004 #define CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT                                                             0x8
20005 #define CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT                                                              0x10
20006 #define CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT                                                              0x15
20007 #define CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT                                                             0x18
20008 #define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT                                                        0x1d
20009 #define CB_BLEND6_CONTROL__ENABLE__SHIFT                                                                      0x1e
20010 #define CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT                                                                0x1f
20011 #define CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK                                                                0x0000001FL
20012 #define CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK                                                                0x000000E0L
20013 #define CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK                                                               0x00001F00L
20014 #define CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK                                                                0x001F0000L
20015 #define CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK                                                                0x00E00000L
20016 #define CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK                                                               0x1F000000L
20017 #define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK                                                          0x20000000L
20018 #define CB_BLEND6_CONTROL__ENABLE_MASK                                                                        0x40000000L
20019 #define CB_BLEND6_CONTROL__DISABLE_ROP3_MASK                                                                  0x80000000L
20020 //CB_BLEND7_CONTROL
20021 #define CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT                                                              0x0
20022 #define CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT                                                              0x5
20023 #define CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT                                                             0x8
20024 #define CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT                                                              0x10
20025 #define CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT                                                              0x15
20026 #define CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT                                                             0x18
20027 #define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT                                                        0x1d
20028 #define CB_BLEND7_CONTROL__ENABLE__SHIFT                                                                      0x1e
20029 #define CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT                                                                0x1f
20030 #define CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK                                                                0x0000001FL
20031 #define CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK                                                                0x000000E0L
20032 #define CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK                                                               0x00001F00L
20033 #define CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK                                                                0x001F0000L
20034 #define CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK                                                                0x00E00000L
20035 #define CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK                                                               0x1F000000L
20036 #define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK                                                          0x20000000L
20037 #define CB_BLEND7_CONTROL__ENABLE_MASK                                                                        0x40000000L
20038 #define CB_BLEND7_CONTROL__DISABLE_ROP3_MASK                                                                  0x80000000L
20039 //CB_MRT0_EPITCH
20040 #define CB_MRT0_EPITCH__EPITCH__SHIFT                                                                         0x0
20041 #define CB_MRT0_EPITCH__EPITCH_MASK                                                                           0x0000FFFFL
20042 //CB_MRT1_EPITCH
20043 #define CB_MRT1_EPITCH__EPITCH__SHIFT                                                                         0x0
20044 #define CB_MRT1_EPITCH__EPITCH_MASK                                                                           0x0000FFFFL
20045 //CB_MRT2_EPITCH
20046 #define CB_MRT2_EPITCH__EPITCH__SHIFT                                                                         0x0
20047 #define CB_MRT2_EPITCH__EPITCH_MASK                                                                           0x0000FFFFL
20048 //CB_MRT3_EPITCH
20049 #define CB_MRT3_EPITCH__EPITCH__SHIFT                                                                         0x0
20050 #define CB_MRT3_EPITCH__EPITCH_MASK                                                                           0x0000FFFFL
20051 //CB_MRT4_EPITCH
20052 #define CB_MRT4_EPITCH__EPITCH__SHIFT                                                                         0x0
20053 #define CB_MRT4_EPITCH__EPITCH_MASK                                                                           0x0000FFFFL
20054 //CB_MRT5_EPITCH
20055 #define CB_MRT5_EPITCH__EPITCH__SHIFT                                                                         0x0
20056 #define CB_MRT5_EPITCH__EPITCH_MASK                                                                           0x0000FFFFL
20057 //CB_MRT6_EPITCH
20058 #define CB_MRT6_EPITCH__EPITCH__SHIFT                                                                         0x0
20059 #define CB_MRT6_EPITCH__EPITCH_MASK                                                                           0x0000FFFFL
20060 //CB_MRT7_EPITCH
20061 #define CB_MRT7_EPITCH__EPITCH__SHIFT                                                                         0x0
20062 #define CB_MRT7_EPITCH__EPITCH_MASK                                                                           0x0000FFFFL
20063 //CS_COPY_STATE
20064 #define CS_COPY_STATE__SRC_STATE_ID__SHIFT                                                                    0x0
20065 #define CS_COPY_STATE__SRC_STATE_ID_MASK                                                                      0x00000007L
20066 //GFX_COPY_STATE
20067 #define GFX_COPY_STATE__SRC_STATE_ID__SHIFT                                                                   0x0
20068 #define GFX_COPY_STATE__SRC_STATE_ID_MASK                                                                     0x00000007L
20069 //PA_CL_POINT_X_RAD
20070 #define PA_CL_POINT_X_RAD__DATA_REGISTER__SHIFT                                                               0x0
20071 #define PA_CL_POINT_X_RAD__DATA_REGISTER_MASK                                                                 0xFFFFFFFFL
20072 //PA_CL_POINT_Y_RAD
20073 #define PA_CL_POINT_Y_RAD__DATA_REGISTER__SHIFT                                                               0x0
20074 #define PA_CL_POINT_Y_RAD__DATA_REGISTER_MASK                                                                 0xFFFFFFFFL
20075 //PA_CL_POINT_SIZE
20076 #define PA_CL_POINT_SIZE__DATA_REGISTER__SHIFT                                                                0x0
20077 #define PA_CL_POINT_SIZE__DATA_REGISTER_MASK                                                                  0xFFFFFFFFL
20078 //PA_CL_POINT_CULL_RAD
20079 #define PA_CL_POINT_CULL_RAD__DATA_REGISTER__SHIFT                                                            0x0
20080 #define PA_CL_POINT_CULL_RAD__DATA_REGISTER_MASK                                                              0xFFFFFFFFL
20081 //VGT_DMA_BASE_HI
20082 #define VGT_DMA_BASE_HI__BASE_ADDR__SHIFT                                                                     0x0
20083 #define VGT_DMA_BASE_HI__BASE_ADDR_MASK                                                                       0x0000FFFFL
20084 //VGT_DMA_BASE
20085 #define VGT_DMA_BASE__BASE_ADDR__SHIFT                                                                        0x0
20086 #define VGT_DMA_BASE__BASE_ADDR_MASK                                                                          0xFFFFFFFFL
20087 //VGT_DRAW_INITIATOR
20088 #define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT                                                              0x0
20089 #define VGT_DRAW_INITIATOR__MAJOR_MODE__SHIFT                                                                 0x2
20090 #define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX__SHIFT                                                             0x4
20091 #define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT                                                                    0x5
20092 #define VGT_DRAW_INITIATOR__USE_OPAQUE__SHIFT                                                                 0x6
20093 #define VGT_DRAW_INITIATOR__UNROLLED_INST__SHIFT                                                              0x7
20094 #define VGT_DRAW_INITIATOR__GRBM_SKEW_NO_DEC__SHIFT                                                           0x8
20095 #define VGT_DRAW_INITIATOR__REG_RT_INDEX__SHIFT                                                               0x1d
20096 #define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK                                                                0x00000003L
20097 #define VGT_DRAW_INITIATOR__MAJOR_MODE_MASK                                                                   0x0000000CL
20098 #define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX_MASK                                                               0x00000010L
20099 #define VGT_DRAW_INITIATOR__NOT_EOP_MASK                                                                      0x00000020L
20100 #define VGT_DRAW_INITIATOR__USE_OPAQUE_MASK                                                                   0x00000040L
20101 #define VGT_DRAW_INITIATOR__UNROLLED_INST_MASK                                                                0x00000080L
20102 #define VGT_DRAW_INITIATOR__GRBM_SKEW_NO_DEC_MASK                                                             0x00000100L
20103 #define VGT_DRAW_INITIATOR__REG_RT_INDEX_MASK                                                                 0xE0000000L
20104 //VGT_IMMED_DATA
20105 #define VGT_IMMED_DATA__DATA__SHIFT                                                                           0x0
20106 #define VGT_IMMED_DATA__DATA_MASK                                                                             0xFFFFFFFFL
20107 //VGT_EVENT_ADDRESS_REG
20108 #define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW__SHIFT                                                             0x0
20109 #define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW_MASK                                                               0x0FFFFFFFL
20110 //DB_DEPTH_CONTROL
20111 #define DB_DEPTH_CONTROL__STENCIL_ENABLE__SHIFT                                                               0x0
20112 #define DB_DEPTH_CONTROL__Z_ENABLE__SHIFT                                                                     0x1
20113 #define DB_DEPTH_CONTROL__Z_WRITE_ENABLE__SHIFT                                                               0x2
20114 #define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE__SHIFT                                                          0x3
20115 #define DB_DEPTH_CONTROL__ZFUNC__SHIFT                                                                        0x4
20116 #define DB_DEPTH_CONTROL__BACKFACE_ENABLE__SHIFT                                                              0x7
20117 #define DB_DEPTH_CONTROL__STENCILFUNC__SHIFT                                                                  0x8
20118 #define DB_DEPTH_CONTROL__STENCILFUNC_BF__SHIFT                                                               0x14
20119 #define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL__SHIFT                                            0x1e
20120 #define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS__SHIFT                                           0x1f
20121 #define DB_DEPTH_CONTROL__STENCIL_ENABLE_MASK                                                                 0x00000001L
20122 #define DB_DEPTH_CONTROL__Z_ENABLE_MASK                                                                       0x00000002L
20123 #define DB_DEPTH_CONTROL__Z_WRITE_ENABLE_MASK                                                                 0x00000004L
20124 #define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE_MASK                                                            0x00000008L
20125 #define DB_DEPTH_CONTROL__ZFUNC_MASK                                                                          0x00000070L
20126 #define DB_DEPTH_CONTROL__BACKFACE_ENABLE_MASK                                                                0x00000080L
20127 #define DB_DEPTH_CONTROL__STENCILFUNC_MASK                                                                    0x00000700L
20128 #define DB_DEPTH_CONTROL__STENCILFUNC_BF_MASK                                                                 0x00700000L
20129 #define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK                                              0x40000000L
20130 #define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK                                             0x80000000L
20131 //DB_EQAA
20132 #define DB_EQAA__MAX_ANCHOR_SAMPLES__SHIFT                                                                    0x0
20133 #define DB_EQAA__PS_ITER_SAMPLES__SHIFT                                                                       0x4
20134 #define DB_EQAA__MASK_EXPORT_NUM_SAMPLES__SHIFT                                                               0x8
20135 #define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES__SHIFT                                                             0xc
20136 #define DB_EQAA__HIGH_QUALITY_INTERSECTIONS__SHIFT                                                            0x10
20137 #define DB_EQAA__INCOHERENT_EQAA_READS__SHIFT                                                                 0x11
20138 #define DB_EQAA__INTERPOLATE_COMP_Z__SHIFT                                                                    0x12
20139 #define DB_EQAA__INTERPOLATE_SRC_Z__SHIFT                                                                     0x13
20140 #define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS__SHIFT                                                            0x14
20141 #define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE__SHIFT                                                            0x15
20142 #define DB_EQAA__OVERRASTERIZATION_AMOUNT__SHIFT                                                              0x18
20143 #define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION__SHIFT                                                        0x1b
20144 #define DB_EQAA__MAX_ANCHOR_SAMPLES_MASK                                                                      0x00000007L
20145 #define DB_EQAA__PS_ITER_SAMPLES_MASK                                                                         0x00000070L
20146 #define DB_EQAA__MASK_EXPORT_NUM_SAMPLES_MASK                                                                 0x00000700L
20147 #define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES_MASK                                                               0x00007000L
20148 #define DB_EQAA__HIGH_QUALITY_INTERSECTIONS_MASK                                                              0x00010000L
20149 #define DB_EQAA__INCOHERENT_EQAA_READS_MASK                                                                   0x00020000L
20150 #define DB_EQAA__INTERPOLATE_COMP_Z_MASK                                                                      0x00040000L
20151 #define DB_EQAA__INTERPOLATE_SRC_Z_MASK                                                                       0x00080000L
20152 #define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS_MASK                                                              0x00100000L
20153 #define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE_MASK                                                              0x00200000L
20154 #define DB_EQAA__OVERRASTERIZATION_AMOUNT_MASK                                                                0x07000000L
20155 #define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION_MASK                                                          0x08000000L
20156 //CB_COLOR_CONTROL
20157 #define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD__SHIFT                                                            0x0
20158 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT                                                               0x3
20159 #define CB_COLOR_CONTROL__MODE__SHIFT                                                                         0x4
20160 #define CB_COLOR_CONTROL__ROP3__SHIFT                                                                         0x10
20161 #define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD_MASK                                                              0x00000001L
20162 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK                                                                 0x00000008L
20163 #define CB_COLOR_CONTROL__MODE_MASK                                                                           0x00000070L
20164 #define CB_COLOR_CONTROL__ROP3_MASK                                                                           0x00FF0000L
20165 //DB_SHADER_CONTROL
20166 #define DB_SHADER_CONTROL__Z_EXPORT_ENABLE__SHIFT                                                             0x0
20167 #define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE__SHIFT                                              0x1
20168 #define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE__SHIFT                                                0x2
20169 #define DB_SHADER_CONTROL__Z_ORDER__SHIFT                                                                     0x4
20170 #define DB_SHADER_CONTROL__KILL_ENABLE__SHIFT                                                                 0x6
20171 #define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE__SHIFT                                                     0x7
20172 #define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE__SHIFT                                                          0x8
20173 #define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL__SHIFT                                                           0x9
20174 #define DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT                                                                0xa
20175 #define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE__SHIFT                                                       0xb
20176 #define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER__SHIFT                                                         0xc
20177 #define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT                                                       0xd
20178 #define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE__SHIFT                                                           0xf
20179 #define DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER__SHIFT                                              0x10
20180 #define DB_SHADER_CONTROL__EXEC_IF_OVERLAPPED__SHIFT                                                          0x11
20181 #define DB_SHADER_CONTROL__POPS_OVERLAP_NUM_SAMPLES__SHIFT                                                    0x14
20182 #define DB_SHADER_CONTROL__Z_EXPORT_ENABLE_MASK                                                               0x00000001L
20183 #define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE_MASK                                                0x00000002L
20184 #define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE_MASK                                                  0x00000004L
20185 #define DB_SHADER_CONTROL__Z_ORDER_MASK                                                                       0x00000030L
20186 #define DB_SHADER_CONTROL__KILL_ENABLE_MASK                                                                   0x00000040L
20187 #define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE_MASK                                                       0x00000080L
20188 #define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE_MASK                                                            0x00000100L
20189 #define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL_MASK                                                             0x00000200L
20190 #define DB_SHADER_CONTROL__EXEC_ON_NOOP_MASK                                                                  0x00000400L
20191 #define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE_MASK                                                         0x00000800L
20192 #define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER_MASK                                                           0x00001000L
20193 #define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT_MASK                                                         0x00006000L
20194 #define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE_MASK                                                             0x00008000L
20195 #define DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER_MASK                                                0x00010000L
20196 #define DB_SHADER_CONTROL__EXEC_IF_OVERLAPPED_MASK                                                            0x00020000L
20197 #define DB_SHADER_CONTROL__POPS_OVERLAP_NUM_SAMPLES_MASK                                                      0x00700000L
20198 //PA_CL_CLIP_CNTL
20199 #define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT                                                                     0x0
20200 #define PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT                                                                     0x1
20201 #define PA_CL_CLIP_CNTL__UCP_ENA_2__SHIFT                                                                     0x2
20202 #define PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT                                                                     0x3
20203 #define PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT                                                                     0x4
20204 #define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT                                                                     0x5
20205 #define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG__SHIFT                                                            0xd
20206 #define PA_CL_CLIP_CNTL__PS_UCP_MODE__SHIFT                                                                   0xe
20207 #define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT                                                                  0x10
20208 #define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA__SHIFT                                                             0x11
20209 #define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT                                                        0x12
20210 #define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT                                                             0x13
20211 #define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT                                                           0x14
20212 #define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT                                                                   0x15
20213 #define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL__SHIFT                                                         0x16
20214 #define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA__SHIFT                                                       0x18
20215 #define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE__SHIFT                                                     0x19
20216 #define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE__SHIFT                                                            0x1a
20217 #define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE__SHIFT                                                             0x1b
20218 #define PA_CL_CLIP_CNTL__ZCLIP_PROG_NEAR_ENA__SHIFT                                                           0x1c
20219 #define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK                                                                       0x00000001L
20220 #define PA_CL_CLIP_CNTL__UCP_ENA_1_MASK                                                                       0x00000002L
20221 #define PA_CL_CLIP_CNTL__UCP_ENA_2_MASK                                                                       0x00000004L
20222 #define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK                                                                       0x00000008L
20223 #define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK                                                                       0x00000010L
20224 #define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK                                                                       0x00000020L
20225 #define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG_MASK                                                              0x00002000L
20226 #define PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK                                                                     0x0000C000L
20227 #define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK                                                                    0x00010000L
20228 #define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK                                                               0x00020000L
20229 #define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK                                                          0x00040000L
20230 #define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK                                                               0x00080000L
20231 #define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK                                                             0x00100000L
20232 #define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK                                                                     0x00200000L
20233 #define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL_MASK                                                           0x00400000L
20234 #define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA_MASK                                                         0x01000000L
20235 #define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE_MASK                                                       0x02000000L
20236 #define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE_MASK                                                              0x04000000L
20237 #define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE_MASK                                                               0x08000000L
20238 #define PA_CL_CLIP_CNTL__ZCLIP_PROG_NEAR_ENA_MASK                                                             0x10000000L
20239 //PA_SU_SC_MODE_CNTL
20240 #define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT                                                                 0x0
20241 #define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT                                                                  0x1
20242 #define PA_SU_SC_MODE_CNTL__FACE__SHIFT                                                                       0x2
20243 #define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT                                                                  0x3
20244 #define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT                                                       0x5
20245 #define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT                                                        0x8
20246 #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT                                                   0xb
20247 #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT                                                    0xc
20248 #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT                                                    0xd
20249 #define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT                                                   0x10
20250 #define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT                                                         0x13
20251 #define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT                                                             0x14
20252 #define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT                                                          0x15
20253 #define PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF__SHIFT                                      0x16
20254 #define PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION__SHIFT                                                     0x17
20255 #define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK                                                                   0x00000001L
20256 #define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK                                                                    0x00000002L
20257 #define PA_SU_SC_MODE_CNTL__FACE_MASK                                                                         0x00000004L
20258 #define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK                                                                    0x00000018L
20259 #define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK                                                         0x000000E0L
20260 #define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK                                                          0x00000700L
20261 #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK                                                     0x00000800L
20262 #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK                                                      0x00001000L
20263 #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK                                                      0x00002000L
20264 #define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK                                                     0x00010000L
20265 #define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK                                                           0x00080000L
20266 #define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK                                                               0x00100000L
20267 #define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK                                                            0x00200000L
20268 #define PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF_MASK                                        0x00400000L
20269 #define PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION_MASK                                                       0x00800000L
20270 //PA_CL_VTE_CNTL
20271 #define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT                                                              0x0
20272 #define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT                                                             0x1
20273 #define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT                                                              0x2
20274 #define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT                                                             0x3
20275 #define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT                                                              0x4
20276 #define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT                                                             0x5
20277 #define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT                                                                     0x8
20278 #define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT                                                                      0x9
20279 #define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT                                                                     0xa
20280 #define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT                                                                0xb
20281 #define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK                                                                0x00000001L
20282 #define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK                                                               0x00000002L
20283 #define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK                                                                0x00000004L
20284 #define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK                                                               0x00000008L
20285 #define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK                                                                0x00000010L
20286 #define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK                                                               0x00000020L
20287 #define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK                                                                       0x00000100L
20288 #define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK                                                                        0x00000200L
20289 #define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK                                                                       0x00000400L
20290 #define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK                                                                  0x00000800L
20291 //PA_CL_VS_OUT_CNTL
20292 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0__SHIFT                                                             0x0
20293 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1__SHIFT                                                             0x1
20294 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2__SHIFT                                                             0x2
20295 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3__SHIFT                                                             0x3
20296 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4__SHIFT                                                             0x4
20297 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5__SHIFT                                                             0x5
20298 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6__SHIFT                                                             0x6
20299 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7__SHIFT                                                             0x7
20300 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0__SHIFT                                                             0x8
20301 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1__SHIFT                                                             0x9
20302 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2__SHIFT                                                             0xa
20303 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3__SHIFT                                                             0xb
20304 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4__SHIFT                                                             0xc
20305 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5__SHIFT                                                             0xd
20306 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6__SHIFT                                                             0xe
20307 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7__SHIFT                                                             0xf
20308 #define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE__SHIFT                                                          0x10
20309 #define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG__SHIFT                                                           0x11
20310 #define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX__SHIFT                                                  0x12
20311 #define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX__SHIFT                                                       0x13
20312 #define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG__SHIFT                                                           0x14
20313 #define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA__SHIFT                                                         0x15
20314 #define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA__SHIFT                                                      0x16
20315 #define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA__SHIFT                                                      0x17
20316 #define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA__SHIFT                                                    0x18
20317 #define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG__SHIFT                                                         0x19
20318 #define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH__SHIFT                                                          0x1a
20319 #define PA_CL_VS_OUT_CNTL__USE_VTX_SHD_OBJPRIM_ID__SHIFT                                                      0x1b
20320 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0_MASK                                                               0x00000001L
20321 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1_MASK                                                               0x00000002L
20322 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2_MASK                                                               0x00000004L
20323 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3_MASK                                                               0x00000008L
20324 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4_MASK                                                               0x00000010L
20325 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5_MASK                                                               0x00000020L
20326 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6_MASK                                                               0x00000040L
20327 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7_MASK                                                               0x00000080L
20328 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0_MASK                                                               0x00000100L
20329 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1_MASK                                                               0x00000200L
20330 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2_MASK                                                               0x00000400L
20331 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3_MASK                                                               0x00000800L
20332 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4_MASK                                                               0x00001000L
20333 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5_MASK                                                               0x00002000L
20334 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6_MASK                                                               0x00004000L
20335 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7_MASK                                                               0x00008000L
20336 #define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE_MASK                                                            0x00010000L
20337 #define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG_MASK                                                             0x00020000L
20338 #define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX_MASK                                                    0x00040000L
20339 #define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX_MASK                                                         0x00080000L
20340 #define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG_MASK                                                             0x00100000L
20341 #define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA_MASK                                                           0x00200000L
20342 #define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA_MASK                                                        0x00400000L
20343 #define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA_MASK                                                        0x00800000L
20344 #define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA_MASK                                                      0x01000000L
20345 #define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG_MASK                                                           0x02000000L
20346 #define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH_MASK                                                            0x04000000L
20347 #define PA_CL_VS_OUT_CNTL__USE_VTX_SHD_OBJPRIM_ID_MASK                                                        0x08000000L
20348 //PA_CL_NANINF_CNTL
20349 #define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT                                                          0x0
20350 #define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT                                                           0x1
20351 #define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT                                                           0x2
20352 #define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0__SHIFT                                                           0x3
20353 #define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN__SHIFT                                                           0x4
20354 #define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN__SHIFT                                                            0x5
20355 #define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN__SHIFT                                                            0x6
20356 #define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0__SHIFT                                                        0x7
20357 #define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF__SHIFT                                                            0x8
20358 #define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN__SHIFT                                                            0x9
20359 #define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF__SHIFT                                                             0xa
20360 #define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN__SHIFT                                                             0xb
20361 #define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF__SHIFT                                                             0xc
20362 #define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN__SHIFT                                                             0xd
20363 #define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD__SHIFT                                                    0xe
20364 #define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0__SHIFT                                                         0x14
20365 #define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD_MASK                                                            0x00000001L
20366 #define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD_MASK                                                             0x00000002L
20367 #define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD_MASK                                                             0x00000004L
20368 #define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0_MASK                                                             0x00000008L
20369 #define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN_MASK                                                             0x00000010L
20370 #define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN_MASK                                                              0x00000020L
20371 #define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN_MASK                                                              0x00000040L
20372 #define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0_MASK                                                          0x00000080L
20373 #define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF_MASK                                                              0x00000100L
20374 #define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN_MASK                                                              0x00000200L
20375 #define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF_MASK                                                               0x00000400L
20376 #define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN_MASK                                                               0x00000800L
20377 #define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF_MASK                                                               0x00001000L
20378 #define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN_MASK                                                               0x00002000L
20379 #define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD_MASK                                                      0x00004000L
20380 #define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0_MASK                                                           0x00100000L
20381 //PA_SU_LINE_STIPPLE_CNTL
20382 #define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET__SHIFT                                                    0x0
20383 #define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH__SHIFT                                                    0x2
20384 #define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM__SHIFT                                                      0x3
20385 #define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST__SHIFT                                                        0x4
20386 #define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET_MASK                                                      0x00000003L
20387 #define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH_MASK                                                      0x00000004L
20388 #define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM_MASK                                                        0x00000008L
20389 #define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST_MASK                                                          0x00000010L
20390 //PA_SU_LINE_STIPPLE_SCALE
20391 #define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE__SHIFT                                                   0x0
20392 #define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE_MASK                                                     0xFFFFFFFFL
20393 //PA_SU_PRIM_FILTER_CNTL
20394 #define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT                                                0x0
20395 #define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT                                                    0x1
20396 #define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT                                                   0x2
20397 #define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT                                               0x3
20398 #define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA__SHIFT                                                    0x4
20399 #define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA__SHIFT                                                        0x5
20400 #define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA__SHIFT                                                       0x6
20401 #define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA__SHIFT                                                   0x7
20402 #define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT__SHIFT                                                   0x8
20403 #define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION__SHIFT                                                   0x1e
20404 #define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION__SHIFT                                                  0x1f
20405 #define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK                                                  0x00000001L
20406 #define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK                                                      0x00000002L
20407 #define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK                                                     0x00000004L
20408 #define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK                                                 0x00000008L
20409 #define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA_MASK                                                      0x00000010L
20410 #define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA_MASK                                                          0x00000020L
20411 #define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA_MASK                                                         0x00000040L
20412 #define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA_MASK                                                     0x00000080L
20413 #define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT_MASK                                                     0x0000FF00L
20414 #define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION_MASK                                                     0x40000000L
20415 #define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION_MASK                                                    0x80000000L
20416 //PA_SU_SMALL_PRIM_FILTER_CNTL
20417 #define PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE__SHIFT                                         0x0
20418 #define PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT                                          0x1
20419 #define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT                                              0x2
20420 #define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT                                             0x3
20421 #define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT                                         0x4
20422 #define PA_SU_SMALL_PRIM_FILTER_CNTL__SRBSL_ENABLE__SHIFT                                                     0x5
20423 #define PA_SU_SMALL_PRIM_FILTER_CNTL__SC_1XMSAA_COMPATIBLE_DISABLE__SHIFT                                     0x6
20424 #define PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE_MASK                                           0x00000001L
20425 #define PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK                                            0x00000002L
20426 #define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK                                                0x00000004L
20427 #define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK                                               0x00000008L
20428 #define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK                                           0x00000010L
20429 #define PA_SU_SMALL_PRIM_FILTER_CNTL__SRBSL_ENABLE_MASK                                                       0x00000020L
20430 #define PA_SU_SMALL_PRIM_FILTER_CNTL__SC_1XMSAA_COMPATIBLE_DISABLE_MASK                                       0x00000040L
20431 //PA_CL_OBJPRIM_ID_CNTL
20432 #define PA_CL_OBJPRIM_ID_CNTL__OBJ_ID_SEL__SHIFT                                                              0x0
20433 #define PA_CL_OBJPRIM_ID_CNTL__ADD_PIPED_PRIM_ID__SHIFT                                                       0x1
20434 #define PA_CL_OBJPRIM_ID_CNTL__EN_32BIT_OBJPRIMID__SHIFT                                                      0x2
20435 #define PA_CL_OBJPRIM_ID_CNTL__OBJ_ID_SEL_MASK                                                                0x00000001L
20436 #define PA_CL_OBJPRIM_ID_CNTL__ADD_PIPED_PRIM_ID_MASK                                                         0x00000002L
20437 #define PA_CL_OBJPRIM_ID_CNTL__EN_32BIT_OBJPRIMID_MASK                                                        0x00000004L
20438 //PA_CL_NGG_CNTL
20439 #define PA_CL_NGG_CNTL__VERTEX_REUSE_OFF__SHIFT                                                               0x0
20440 #define PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA__SHIFT                                                        0x1
20441 #define PA_CL_NGG_CNTL__VERTEX_REUSE_OFF_MASK                                                                 0x00000001L
20442 #define PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA_MASK                                                          0x00000002L
20443 //PA_SU_OVER_RASTERIZATION_CNTL
20444 #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES__SHIFT                                        0x0
20445 #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES__SHIFT                                            0x1
20446 #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS__SHIFT                                           0x2
20447 #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES__SHIFT                                       0x3
20448 #define PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW__SHIFT                                                0x4
20449 #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES_MASK                                          0x00000001L
20450 #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES_MASK                                              0x00000002L
20451 #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS_MASK                                             0x00000004L
20452 #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES_MASK                                         0x00000008L
20453 #define PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW_MASK                                                  0x00000010L
20454 //PA_STEREO_CNTL
20455 #define PA_STEREO_CNTL__EN_STEREO__SHIFT                                                                      0x0
20456 #define PA_STEREO_CNTL__STEREO_MODE__SHIFT                                                                    0x1
20457 #define PA_STEREO_CNTL__RT_SLICE_MODE__SHIFT                                                                  0x5
20458 #define PA_STEREO_CNTL__RT_SLICE_OFFSET__SHIFT                                                                0x8
20459 #define PA_STEREO_CNTL__VP_ID_MODE__SHIFT                                                                     0xa
20460 #define PA_STEREO_CNTL__VP_ID_OFFSET__SHIFT                                                                   0xd
20461 #define PA_STEREO_CNTL__EN_STEREO_MASK                                                                        0x00000001L
20462 #define PA_STEREO_CNTL__STEREO_MODE_MASK                                                                      0x0000001EL
20463 #define PA_STEREO_CNTL__RT_SLICE_MODE_MASK                                                                    0x000000E0L
20464 #define PA_STEREO_CNTL__RT_SLICE_OFFSET_MASK                                                                  0x00000300L
20465 #define PA_STEREO_CNTL__VP_ID_MODE_MASK                                                                       0x00001C00L
20466 #define PA_STEREO_CNTL__VP_ID_OFFSET_MASK                                                                     0x0001E000L
20467 //PA_SU_POINT_SIZE
20468 #define PA_SU_POINT_SIZE__HEIGHT__SHIFT                                                                       0x0
20469 #define PA_SU_POINT_SIZE__WIDTH__SHIFT                                                                        0x10
20470 #define PA_SU_POINT_SIZE__HEIGHT_MASK                                                                         0x0000FFFFL
20471 #define PA_SU_POINT_SIZE__WIDTH_MASK                                                                          0xFFFF0000L
20472 //PA_SU_POINT_MINMAX
20473 #define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT                                                                   0x0
20474 #define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT                                                                   0x10
20475 #define PA_SU_POINT_MINMAX__MIN_SIZE_MASK                                                                     0x0000FFFFL
20476 #define PA_SU_POINT_MINMAX__MAX_SIZE_MASK                                                                     0xFFFF0000L
20477 //PA_SU_LINE_CNTL
20478 #define PA_SU_LINE_CNTL__WIDTH__SHIFT                                                                         0x0
20479 #define PA_SU_LINE_CNTL__WIDTH_MASK                                                                           0x0000FFFFL
20480 //PA_SC_LINE_STIPPLE
20481 #define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT                                                               0x0
20482 #define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT                                                               0x10
20483 #define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT                                                          0x1c
20484 #define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT                                                            0x1d
20485 #define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK                                                                 0x0000FFFFL
20486 #define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK                                                                 0x00FF0000L
20487 #define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK                                                            0x10000000L
20488 #define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK                                                              0x60000000L
20489 //VGT_OUTPUT_PATH_CNTL
20490 #define VGT_OUTPUT_PATH_CNTL__PATH_SELECT__SHIFT                                                              0x0
20491 #define VGT_OUTPUT_PATH_CNTL__PATH_SELECT_MASK                                                                0x00000007L
20492 //VGT_HOS_CNTL
20493 #define VGT_HOS_CNTL__TESS_MODE__SHIFT                                                                        0x0
20494 #define VGT_HOS_CNTL__TESS_MODE_MASK                                                                          0x00000003L
20495 //VGT_HOS_MAX_TESS_LEVEL
20496 #define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS__SHIFT                                                               0x0
20497 #define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS_MASK                                                                 0xFFFFFFFFL
20498 //VGT_HOS_MIN_TESS_LEVEL
20499 #define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS__SHIFT                                                               0x0
20500 #define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS_MASK                                                                 0xFFFFFFFFL
20501 //VGT_HOS_REUSE_DEPTH
20502 #define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH__SHIFT                                                               0x0
20503 #define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH_MASK                                                                 0x000000FFL
20504 //VGT_GROUP_PRIM_TYPE
20505 #define VGT_GROUP_PRIM_TYPE__PRIM_TYPE__SHIFT                                                                 0x0
20506 #define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER__SHIFT                                                              0xe
20507 #define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS__SHIFT                                                              0xf
20508 #define VGT_GROUP_PRIM_TYPE__PRIM_ORDER__SHIFT                                                                0x10
20509 #define VGT_GROUP_PRIM_TYPE__PRIM_TYPE_MASK                                                                   0x0000001FL
20510 #define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER_MASK                                                                0x00004000L
20511 #define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS_MASK                                                                0x00008000L
20512 #define VGT_GROUP_PRIM_TYPE__PRIM_ORDER_MASK                                                                  0x00070000L
20513 //VGT_GROUP_FIRST_DECR
20514 #define VGT_GROUP_FIRST_DECR__FIRST_DECR__SHIFT                                                               0x0
20515 #define VGT_GROUP_FIRST_DECR__FIRST_DECR_MASK                                                                 0x0000000FL
20516 //VGT_GROUP_DECR
20517 #define VGT_GROUP_DECR__DECR__SHIFT                                                                           0x0
20518 #define VGT_GROUP_DECR__DECR_MASK                                                                             0x0000000FL
20519 //VGT_GROUP_VECT_0_CNTL
20520 #define VGT_GROUP_VECT_0_CNTL__COMP_X_EN__SHIFT                                                               0x0
20521 #define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN__SHIFT                                                               0x1
20522 #define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN__SHIFT                                                               0x2
20523 #define VGT_GROUP_VECT_0_CNTL__COMP_W_EN__SHIFT                                                               0x3
20524 #define VGT_GROUP_VECT_0_CNTL__STRIDE__SHIFT                                                                  0x8
20525 #define VGT_GROUP_VECT_0_CNTL__SHIFT__SHIFT                                                                   0x10
20526 #define VGT_GROUP_VECT_0_CNTL__COMP_X_EN_MASK                                                                 0x00000001L
20527 #define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN_MASK                                                                 0x00000002L
20528 #define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN_MASK                                                                 0x00000004L
20529 #define VGT_GROUP_VECT_0_CNTL__COMP_W_EN_MASK                                                                 0x00000008L
20530 #define VGT_GROUP_VECT_0_CNTL__STRIDE_MASK                                                                    0x0000FF00L
20531 #define VGT_GROUP_VECT_0_CNTL__SHIFT_MASK                                                                     0x00FF0000L
20532 //VGT_GROUP_VECT_1_CNTL
20533 #define VGT_GROUP_VECT_1_CNTL__COMP_X_EN__SHIFT                                                               0x0
20534 #define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN__SHIFT                                                               0x1
20535 #define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN__SHIFT                                                               0x2
20536 #define VGT_GROUP_VECT_1_CNTL__COMP_W_EN__SHIFT                                                               0x3
20537 #define VGT_GROUP_VECT_1_CNTL__STRIDE__SHIFT                                                                  0x8
20538 #define VGT_GROUP_VECT_1_CNTL__SHIFT__SHIFT                                                                   0x10
20539 #define VGT_GROUP_VECT_1_CNTL__COMP_X_EN_MASK                                                                 0x00000001L
20540 #define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN_MASK                                                                 0x00000002L
20541 #define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN_MASK                                                                 0x00000004L
20542 #define VGT_GROUP_VECT_1_CNTL__COMP_W_EN_MASK                                                                 0x00000008L
20543 #define VGT_GROUP_VECT_1_CNTL__STRIDE_MASK                                                                    0x0000FF00L
20544 #define VGT_GROUP_VECT_1_CNTL__SHIFT_MASK                                                                     0x00FF0000L
20545 //VGT_GROUP_VECT_0_FMT_CNTL
20546 #define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV__SHIFT                                                              0x0
20547 #define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET__SHIFT                                                            0x4
20548 #define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV__SHIFT                                                              0x8
20549 #define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET__SHIFT                                                            0xc
20550 #define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV__SHIFT                                                              0x10
20551 #define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET__SHIFT                                                            0x14
20552 #define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV__SHIFT                                                              0x18
20553 #define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET__SHIFT                                                            0x1c
20554 #define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV_MASK                                                                0x0000000FL
20555 #define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET_MASK                                                              0x000000F0L
20556 #define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV_MASK                                                                0x00000F00L
20557 #define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET_MASK                                                              0x0000F000L
20558 #define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV_MASK                                                                0x000F0000L
20559 #define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET_MASK                                                              0x00F00000L
20560 #define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV_MASK                                                                0x0F000000L
20561 #define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET_MASK                                                              0xF0000000L
20562 //VGT_GROUP_VECT_1_FMT_CNTL
20563 #define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV__SHIFT                                                              0x0
20564 #define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET__SHIFT                                                            0x4
20565 #define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV__SHIFT                                                              0x8
20566 #define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET__SHIFT                                                            0xc
20567 #define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV__SHIFT                                                              0x10
20568 #define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET__SHIFT                                                            0x14
20569 #define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV__SHIFT                                                              0x18
20570 #define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET__SHIFT                                                            0x1c
20571 #define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV_MASK                                                                0x0000000FL
20572 #define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET_MASK                                                              0x000000F0L
20573 #define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV_MASK                                                                0x00000F00L
20574 #define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET_MASK                                                              0x0000F000L
20575 #define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV_MASK                                                                0x000F0000L
20576 #define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET_MASK                                                              0x00F00000L
20577 #define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV_MASK                                                                0x0F000000L
20578 #define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET_MASK                                                              0xF0000000L
20579 //VGT_GS_MODE
20580 #define VGT_GS_MODE__MODE__SHIFT                                                                              0x0
20581 #define VGT_GS_MODE__RESERVED_0__SHIFT                                                                        0x3
20582 #define VGT_GS_MODE__CUT_MODE__SHIFT                                                                          0x4
20583 #define VGT_GS_MODE__RESERVED_1__SHIFT                                                                        0x6
20584 #define VGT_GS_MODE__GS_C_PACK_EN__SHIFT                                                                      0xb
20585 #define VGT_GS_MODE__RESERVED_2__SHIFT                                                                        0xc
20586 #define VGT_GS_MODE__ES_PASSTHRU__SHIFT                                                                       0xd
20587 #define VGT_GS_MODE__RESERVED_3__SHIFT                                                                        0xe
20588 #define VGT_GS_MODE__RESERVED_4__SHIFT                                                                        0xf
20589 #define VGT_GS_MODE__RESERVED_5__SHIFT                                                                        0x10
20590 #define VGT_GS_MODE__PARTIAL_THD_AT_EOI__SHIFT                                                                0x11
20591 #define VGT_GS_MODE__SUPPRESS_CUTS__SHIFT                                                                     0x12
20592 #define VGT_GS_MODE__ES_WRITE_OPTIMIZE__SHIFT                                                                 0x13
20593 #define VGT_GS_MODE__GS_WRITE_OPTIMIZE__SHIFT                                                                 0x14
20594 #define VGT_GS_MODE__ONCHIP__SHIFT                                                                            0x15
20595 #define VGT_GS_MODE__MODE_MASK                                                                                0x00000007L
20596 #define VGT_GS_MODE__RESERVED_0_MASK                                                                          0x00000008L
20597 #define VGT_GS_MODE__CUT_MODE_MASK                                                                            0x00000030L
20598 #define VGT_GS_MODE__RESERVED_1_MASK                                                                          0x000007C0L
20599 #define VGT_GS_MODE__GS_C_PACK_EN_MASK                                                                        0x00000800L
20600 #define VGT_GS_MODE__RESERVED_2_MASK                                                                          0x00001000L
20601 #define VGT_GS_MODE__ES_PASSTHRU_MASK                                                                         0x00002000L
20602 #define VGT_GS_MODE__RESERVED_3_MASK                                                                          0x00004000L
20603 #define VGT_GS_MODE__RESERVED_4_MASK                                                                          0x00008000L
20604 #define VGT_GS_MODE__RESERVED_5_MASK                                                                          0x00010000L
20605 #define VGT_GS_MODE__PARTIAL_THD_AT_EOI_MASK                                                                  0x00020000L
20606 #define VGT_GS_MODE__SUPPRESS_CUTS_MASK                                                                       0x00040000L
20607 #define VGT_GS_MODE__ES_WRITE_OPTIMIZE_MASK                                                                   0x00080000L
20608 #define VGT_GS_MODE__GS_WRITE_OPTIMIZE_MASK                                                                   0x00100000L
20609 #define VGT_GS_MODE__ONCHIP_MASK                                                                              0x00600000L
20610 //VGT_GS_ONCHIP_CNTL
20611 #define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP__SHIFT                                                        0x0
20612 #define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP__SHIFT                                                        0xb
20613 #define VGT_GS_ONCHIP_CNTL__GS_INST_PRIMS_IN_SUBGRP__SHIFT                                                    0x16
20614 #define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP_MASK                                                          0x000007FFL
20615 #define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP_MASK                                                          0x003FF800L
20616 #define VGT_GS_ONCHIP_CNTL__GS_INST_PRIMS_IN_SUBGRP_MASK                                                      0xFFC00000L
20617 //PA_SC_MODE_CNTL_0
20618 #define PA_SC_MODE_CNTL_0__MSAA_ENABLE__SHIFT                                                                 0x0
20619 #define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE__SHIFT                                                        0x1
20620 #define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE__SHIFT                                                         0x2
20621 #define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR__SHIFT                                                    0x3
20622 #define PA_SC_MODE_CNTL_0__SCALE_LINE_WIDTH_PAD__SHIFT                                                        0x4
20623 #define PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE__SHIFT                                                      0x5
20624 #define PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB__SHIFT                                               0x6
20625 #define PA_SC_MODE_CNTL_0__MSAA_ENABLE_MASK                                                                   0x00000001L
20626 #define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE_MASK                                                          0x00000002L
20627 #define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE_MASK                                                           0x00000004L
20628 #define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR_MASK                                                      0x00000008L
20629 #define PA_SC_MODE_CNTL_0__SCALE_LINE_WIDTH_PAD_MASK                                                          0x00000010L
20630 #define PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE_MASK                                                        0x00000020L
20631 #define PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB_MASK                                                 0x00000040L
20632 //PA_SC_MODE_CNTL_1
20633 #define PA_SC_MODE_CNTL_1__WALK_SIZE__SHIFT                                                                   0x0
20634 #define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT__SHIFT                                                              0x1
20635 #define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST__SHIFT                                                    0x2
20636 #define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE__SHIFT                                                           0x3
20637 #define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE__SHIFT                                                             0x4
20638 #define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE__SHIFT                                                 0x7
20639 #define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE__SHIFT                                                      0x8
20640 #define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE__SHIFT                                                          0x9
20641 #define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR__SHIFT                                                       0xa
20642 #define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT__SHIFT                                                             0xb
20643 #define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET__SHIFT                                                             0xc
20644 #define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT__SHIFT                                                             0xd
20645 #define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z__SHIFT                                                          0xe
20646 #define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK__SHIFT                                                   0xf
20647 #define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE__SHIFT                                                              0x10
20648 #define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE__SHIFT                                     0x11
20649 #define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE__SHIFT                                                  0x12
20650 #define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE__SHIFT                                                      0x13
20651 #define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE__SHIFT                                                             0x14
20652 #define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE__SHIFT                                               0x18
20653 #define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE__SHIFT                                                     0x19
20654 #define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE__SHIFT                                                        0x1a
20655 #define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE__SHIFT                                               0x1b
20656 #define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK__SHIFT                                                     0x1c
20657 #define PA_SC_MODE_CNTL_1__WALK_SIZE_MASK                                                                     0x00000001L
20658 #define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT_MASK                                                                0x00000002L
20659 #define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST_MASK                                                      0x00000004L
20660 #define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE_MASK                                                             0x00000008L
20661 #define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE_MASK                                                               0x00000070L
20662 #define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE_MASK                                                   0x00000080L
20663 #define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE_MASK                                                        0x00000100L
20664 #define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE_MASK                                                            0x00000200L
20665 #define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR_MASK                                                         0x00000400L
20666 #define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT_MASK                                                               0x00000800L
20667 #define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET_MASK                                                               0x00001000L
20668 #define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT_MASK                                                               0x00002000L
20669 #define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z_MASK                                                            0x00004000L
20670 #define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK_MASK                                                     0x00008000L
20671 #define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE_MASK                                                                0x00010000L
20672 #define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE_MASK                                       0x00020000L
20673 #define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE_MASK                                                    0x00040000L
20674 #define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE_MASK                                                        0x00080000L
20675 #define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_MASK                                                               0x00F00000L
20676 #define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE_MASK                                                 0x01000000L
20677 #define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE_MASK                                                       0x02000000L
20678 #define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK                                                          0x04000000L
20679 #define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE_MASK                                                 0x08000000L
20680 #define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK_MASK                                                       0x70000000L
20681 //VGT_ENHANCE
20682 #define VGT_ENHANCE__MISC__SHIFT                                                                              0x0
20683 #define VGT_ENHANCE__MISC_MASK                                                                                0xFFFFFFFFL
20684 //VGT_GS_PER_ES
20685 #define VGT_GS_PER_ES__GS_PER_ES__SHIFT                                                                       0x0
20686 #define VGT_GS_PER_ES__GS_PER_ES_MASK                                                                         0x000007FFL
20687 //VGT_ES_PER_GS
20688 #define VGT_ES_PER_GS__ES_PER_GS__SHIFT                                                                       0x0
20689 #define VGT_ES_PER_GS__ES_PER_GS_MASK                                                                         0x000007FFL
20690 //VGT_GS_PER_VS
20691 #define VGT_GS_PER_VS__GS_PER_VS__SHIFT                                                                       0x0
20692 #define VGT_GS_PER_VS__GS_PER_VS_MASK                                                                         0x0000000FL
20693 //VGT_GSVS_RING_OFFSET_1
20694 #define VGT_GSVS_RING_OFFSET_1__OFFSET__SHIFT                                                                 0x0
20695 #define VGT_GSVS_RING_OFFSET_1__OFFSET_MASK                                                                   0x00007FFFL
20696 //VGT_GSVS_RING_OFFSET_2
20697 #define VGT_GSVS_RING_OFFSET_2__OFFSET__SHIFT                                                                 0x0
20698 #define VGT_GSVS_RING_OFFSET_2__OFFSET_MASK                                                                   0x00007FFFL
20699 //VGT_GSVS_RING_OFFSET_3
20700 #define VGT_GSVS_RING_OFFSET_3__OFFSET__SHIFT                                                                 0x0
20701 #define VGT_GSVS_RING_OFFSET_3__OFFSET_MASK                                                                   0x00007FFFL
20702 //VGT_GS_OUT_PRIM_TYPE
20703 #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE__SHIFT                                                             0x0
20704 #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1__SHIFT                                                           0x8
20705 #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2__SHIFT                                                           0x10
20706 #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3__SHIFT                                                           0x16
20707 #define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM__SHIFT                                                   0x1f
20708 #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_MASK                                                               0x0000003FL
20709 #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1_MASK                                                             0x00003F00L
20710 #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2_MASK                                                             0x003F0000L
20711 #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3_MASK                                                             0x0FC00000L
20712 #define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM_MASK                                                     0x80000000L
20713 //IA_ENHANCE
20714 #define IA_ENHANCE__MISC__SHIFT                                                                               0x0
20715 #define IA_ENHANCE__MISC_MASK                                                                                 0xFFFFFFFFL
20716 //VGT_DMA_SIZE
20717 #define VGT_DMA_SIZE__NUM_INDICES__SHIFT                                                                      0x0
20718 #define VGT_DMA_SIZE__NUM_INDICES_MASK                                                                        0xFFFFFFFFL
20719 //VGT_DMA_MAX_SIZE
20720 #define VGT_DMA_MAX_SIZE__MAX_SIZE__SHIFT                                                                     0x0
20721 #define VGT_DMA_MAX_SIZE__MAX_SIZE_MASK                                                                       0xFFFFFFFFL
20722 //VGT_DMA_INDEX_TYPE
20723 #define VGT_DMA_INDEX_TYPE__INDEX_TYPE__SHIFT                                                                 0x0
20724 #define VGT_DMA_INDEX_TYPE__SWAP_MODE__SHIFT                                                                  0x2
20725 #define VGT_DMA_INDEX_TYPE__BUF_TYPE__SHIFT                                                                   0x4
20726 #define VGT_DMA_INDEX_TYPE__RDREQ_POLICY__SHIFT                                                               0x6
20727 #define VGT_DMA_INDEX_TYPE__PRIMGEN_EN__SHIFT                                                                 0x8
20728 #define VGT_DMA_INDEX_TYPE__NOT_EOP__SHIFT                                                                    0x9
20729 #define VGT_DMA_INDEX_TYPE__REQ_PATH__SHIFT                                                                   0xa
20730 #define VGT_DMA_INDEX_TYPE__INDEX_TYPE_MASK                                                                   0x00000003L
20731 #define VGT_DMA_INDEX_TYPE__SWAP_MODE_MASK                                                                    0x0000000CL
20732 #define VGT_DMA_INDEX_TYPE__BUF_TYPE_MASK                                                                     0x00000030L
20733 #define VGT_DMA_INDEX_TYPE__RDREQ_POLICY_MASK                                                                 0x00000040L
20734 #define VGT_DMA_INDEX_TYPE__PRIMGEN_EN_MASK                                                                   0x00000100L
20735 #define VGT_DMA_INDEX_TYPE__NOT_EOP_MASK                                                                      0x00000200L
20736 #define VGT_DMA_INDEX_TYPE__REQ_PATH_MASK                                                                     0x00000400L
20737 //WD_ENHANCE
20738 #define WD_ENHANCE__MISC__SHIFT                                                                               0x0
20739 #define WD_ENHANCE__MISC_MASK                                                                                 0xFFFFFFFFL
20740 //VGT_PRIMITIVEID_EN
20741 #define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN__SHIFT                                                             0x0
20742 #define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI__SHIFT                                                       0x1
20743 #define VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE__SHIFT                                                   0x2
20744 #define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN_MASK                                                               0x00000001L
20745 #define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI_MASK                                                         0x00000002L
20746 #define VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE_MASK                                                     0x00000004L
20747 //VGT_DMA_NUM_INSTANCES
20748 #define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES__SHIFT                                                           0x0
20749 #define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES_MASK                                                             0xFFFFFFFFL
20750 //VGT_PRIMITIVEID_RESET
20751 #define VGT_PRIMITIVEID_RESET__VALUE__SHIFT                                                                   0x0
20752 #define VGT_PRIMITIVEID_RESET__VALUE_MASK                                                                     0xFFFFFFFFL
20753 //VGT_EVENT_INITIATOR
20754 #define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT                                                                0x0
20755 #define VGT_EVENT_INITIATOR__ADDRESS_HI__SHIFT                                                                0xa
20756 #define VGT_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT                                                            0x1b
20757 #define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK                                                                  0x0000003FL
20758 #define VGT_EVENT_INITIATOR__ADDRESS_HI_MASK                                                                  0x07FFFC00L
20759 #define VGT_EVENT_INITIATOR__EXTENDED_EVENT_MASK                                                              0x08000000L
20760 //VGT_GS_MAX_PRIMS_PER_SUBGROUP
20761 #define VGT_GS_MAX_PRIMS_PER_SUBGROUP__MAX_PRIMS_PER_SUBGROUP__SHIFT                                          0x0
20762 #define VGT_GS_MAX_PRIMS_PER_SUBGROUP__MAX_PRIMS_PER_SUBGROUP_MASK                                            0x0000FFFFL
20763 //VGT_DRAW_PAYLOAD_CNTL
20764 #define VGT_DRAW_PAYLOAD_CNTL__OBJPRIM_ID_EN__SHIFT                                                           0x0
20765 #define VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX__SHIFT                                                         0x1
20766 #define VGT_DRAW_PAYLOAD_CNTL__EN_PIPELINE_PRIMID__SHIFT                                                      0x2
20767 #define VGT_DRAW_PAYLOAD_CNTL__OBJECT_ID_INST_EN__SHIFT                                                       0x3
20768 #define VGT_DRAW_PAYLOAD_CNTL__OBJPRIM_ID_EN_MASK                                                             0x00000001L
20769 #define VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX_MASK                                                           0x00000002L
20770 #define VGT_DRAW_PAYLOAD_CNTL__EN_PIPELINE_PRIMID_MASK                                                        0x00000004L
20771 #define VGT_DRAW_PAYLOAD_CNTL__OBJECT_ID_INST_EN_MASK                                                         0x00000008L
20772 //VGT_INSTANCE_STEP_RATE_0
20773 #define VGT_INSTANCE_STEP_RATE_0__STEP_RATE__SHIFT                                                            0x0
20774 #define VGT_INSTANCE_STEP_RATE_0__STEP_RATE_MASK                                                              0xFFFFFFFFL
20775 //VGT_INSTANCE_STEP_RATE_1
20776 #define VGT_INSTANCE_STEP_RATE_1__STEP_RATE__SHIFT                                                            0x0
20777 #define VGT_INSTANCE_STEP_RATE_1__STEP_RATE_MASK                                                              0xFFFFFFFFL
20778 //IA_MULTI_VGT_PARAM_BC
20779 //VGT_ESGS_RING_ITEMSIZE
20780 #define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE__SHIFT                                                               0x0
20781 #define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE_MASK                                                                 0x00007FFFL
20782 //VGT_GSVS_RING_ITEMSIZE
20783 #define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE__SHIFT                                                               0x0
20784 #define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE_MASK                                                                 0x00007FFFL
20785 //VGT_REUSE_OFF
20786 #define VGT_REUSE_OFF__REUSE_OFF__SHIFT                                                                       0x0
20787 #define VGT_REUSE_OFF__REUSE_OFF_MASK                                                                         0x00000001L
20788 //VGT_VTX_CNT_EN
20789 #define VGT_VTX_CNT_EN__VTX_CNT_EN__SHIFT                                                                     0x0
20790 #define VGT_VTX_CNT_EN__VTX_CNT_EN_MASK                                                                       0x00000001L
20791 //DB_HTILE_SURFACE
20792 #define DB_HTILE_SURFACE__FULL_CACHE__SHIFT                                                                   0x1
20793 #define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN__SHIFT                                                       0x2
20794 #define DB_HTILE_SURFACE__PRELOAD__SHIFT                                                                      0x3
20795 #define DB_HTILE_SURFACE__PREFETCH_WIDTH__SHIFT                                                               0x4
20796 #define DB_HTILE_SURFACE__PREFETCH_HEIGHT__SHIFT                                                              0xa
20797 #define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE__SHIFT                                                      0x10
20798 #define DB_HTILE_SURFACE__PIPE_ALIGNED__SHIFT                                                                 0x12
20799 #define DB_HTILE_SURFACE__RB_ALIGNED__SHIFT                                                                   0x13
20800 #define DB_HTILE_SURFACE__FULL_CACHE_MASK                                                                     0x00000002L
20801 #define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN_MASK                                                         0x00000004L
20802 #define DB_HTILE_SURFACE__PRELOAD_MASK                                                                        0x00000008L
20803 #define DB_HTILE_SURFACE__PREFETCH_WIDTH_MASK                                                                 0x000003F0L
20804 #define DB_HTILE_SURFACE__PREFETCH_HEIGHT_MASK                                                                0x0000FC00L
20805 #define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE_MASK                                                        0x00010000L
20806 #define DB_HTILE_SURFACE__PIPE_ALIGNED_MASK                                                                   0x00040000L
20807 #define DB_HTILE_SURFACE__RB_ALIGNED_MASK                                                                     0x00080000L
20808 //DB_SRESULTS_COMPARE_STATE0
20809 #define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0__SHIFT                                                       0x0
20810 #define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0__SHIFT                                                      0x4
20811 #define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0__SHIFT                                                       0xc
20812 #define DB_SRESULTS_COMPARE_STATE0__ENABLE0__SHIFT                                                            0x18
20813 #define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0_MASK                                                         0x00000007L
20814 #define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0_MASK                                                        0x00000FF0L
20815 #define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0_MASK                                                         0x000FF000L
20816 #define DB_SRESULTS_COMPARE_STATE0__ENABLE0_MASK                                                              0x01000000L
20817 //DB_SRESULTS_COMPARE_STATE1
20818 #define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1__SHIFT                                                       0x0
20819 #define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1__SHIFT                                                      0x4
20820 #define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1__SHIFT                                                       0xc
20821 #define DB_SRESULTS_COMPARE_STATE1__ENABLE1__SHIFT                                                            0x18
20822 #define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1_MASK                                                         0x00000007L
20823 #define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1_MASK                                                        0x00000FF0L
20824 #define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1_MASK                                                         0x000FF000L
20825 #define DB_SRESULTS_COMPARE_STATE1__ENABLE1_MASK                                                              0x01000000L
20826 //DB_PRELOAD_CONTROL
20827 #define DB_PRELOAD_CONTROL__START_X__SHIFT                                                                    0x0
20828 #define DB_PRELOAD_CONTROL__START_Y__SHIFT                                                                    0x8
20829 #define DB_PRELOAD_CONTROL__MAX_X__SHIFT                                                                      0x10
20830 #define DB_PRELOAD_CONTROL__MAX_Y__SHIFT                                                                      0x18
20831 #define DB_PRELOAD_CONTROL__START_X_MASK                                                                      0x000000FFL
20832 #define DB_PRELOAD_CONTROL__START_Y_MASK                                                                      0x0000FF00L
20833 #define DB_PRELOAD_CONTROL__MAX_X_MASK                                                                        0x00FF0000L
20834 #define DB_PRELOAD_CONTROL__MAX_Y_MASK                                                                        0xFF000000L
20835 //VGT_STRMOUT_BUFFER_SIZE_0
20836 #define VGT_STRMOUT_BUFFER_SIZE_0__SIZE__SHIFT                                                                0x0
20837 #define VGT_STRMOUT_BUFFER_SIZE_0__SIZE_MASK                                                                  0xFFFFFFFFL
20838 //VGT_STRMOUT_VTX_STRIDE_0
20839 #define VGT_STRMOUT_VTX_STRIDE_0__STRIDE__SHIFT                                                               0x0
20840 #define VGT_STRMOUT_VTX_STRIDE_0__STRIDE_MASK                                                                 0x000003FFL
20841 //VGT_STRMOUT_BUFFER_OFFSET_0
20842 #define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET__SHIFT                                                            0x0
20843 #define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET_MASK                                                              0xFFFFFFFFL
20844 //VGT_STRMOUT_BUFFER_SIZE_1
20845 #define VGT_STRMOUT_BUFFER_SIZE_1__SIZE__SHIFT                                                                0x0
20846 #define VGT_STRMOUT_BUFFER_SIZE_1__SIZE_MASK                                                                  0xFFFFFFFFL
20847 //VGT_STRMOUT_VTX_STRIDE_1
20848 #define VGT_STRMOUT_VTX_STRIDE_1__STRIDE__SHIFT                                                               0x0
20849 #define VGT_STRMOUT_VTX_STRIDE_1__STRIDE_MASK                                                                 0x000003FFL
20850 //VGT_STRMOUT_BUFFER_OFFSET_1
20851 #define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET__SHIFT                                                            0x0
20852 #define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET_MASK                                                              0xFFFFFFFFL
20853 //VGT_STRMOUT_BUFFER_SIZE_2
20854 #define VGT_STRMOUT_BUFFER_SIZE_2__SIZE__SHIFT                                                                0x0
20855 #define VGT_STRMOUT_BUFFER_SIZE_2__SIZE_MASK                                                                  0xFFFFFFFFL
20856 //VGT_STRMOUT_VTX_STRIDE_2
20857 #define VGT_STRMOUT_VTX_STRIDE_2__STRIDE__SHIFT                                                               0x0
20858 #define VGT_STRMOUT_VTX_STRIDE_2__STRIDE_MASK                                                                 0x000003FFL
20859 //VGT_STRMOUT_BUFFER_OFFSET_2
20860 #define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET__SHIFT                                                            0x0
20861 #define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET_MASK                                                              0xFFFFFFFFL
20862 //VGT_STRMOUT_BUFFER_SIZE_3
20863 #define VGT_STRMOUT_BUFFER_SIZE_3__SIZE__SHIFT                                                                0x0
20864 #define VGT_STRMOUT_BUFFER_SIZE_3__SIZE_MASK                                                                  0xFFFFFFFFL
20865 //VGT_STRMOUT_VTX_STRIDE_3
20866 #define VGT_STRMOUT_VTX_STRIDE_3__STRIDE__SHIFT                                                               0x0
20867 #define VGT_STRMOUT_VTX_STRIDE_3__STRIDE_MASK                                                                 0x000003FFL
20868 //VGT_STRMOUT_BUFFER_OFFSET_3
20869 #define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET__SHIFT                                                            0x0
20870 #define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET_MASK                                                              0xFFFFFFFFL
20871 //VGT_STRMOUT_DRAW_OPAQUE_OFFSET
20872 #define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET__SHIFT                                                         0x0
20873 #define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET_MASK                                                           0xFFFFFFFFL
20874 //VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
20875 #define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE__SHIFT                                               0x0
20876 #define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE_MASK                                                 0xFFFFFFFFL
20877 //VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
20878 #define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE__SHIFT                                           0x0
20879 #define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE_MASK                                             0x000001FFL
20880 //VGT_GS_MAX_VERT_OUT
20881 #define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT__SHIFT                                                              0x0
20882 #define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT_MASK                                                                0x000007FFL
20883 //VGT_TESS_DISTRIBUTION
20884 #define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE__SHIFT                                                           0x0
20885 #define VGT_TESS_DISTRIBUTION__ACCUM_TRI__SHIFT                                                               0x8
20886 #define VGT_TESS_DISTRIBUTION__ACCUM_QUAD__SHIFT                                                              0x10
20887 #define VGT_TESS_DISTRIBUTION__DONUT_SPLIT__SHIFT                                                             0x18
20888 #define VGT_TESS_DISTRIBUTION__TRAP_SPLIT__SHIFT                                                              0x1d
20889 #define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE_MASK                                                             0x000000FFL
20890 #define VGT_TESS_DISTRIBUTION__ACCUM_TRI_MASK                                                                 0x0000FF00L
20891 #define VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK                                                                0x00FF0000L
20892 #define VGT_TESS_DISTRIBUTION__DONUT_SPLIT_MASK                                                               0x1F000000L
20893 #define VGT_TESS_DISTRIBUTION__TRAP_SPLIT_MASK                                                                0xE0000000L
20894 //VGT_SHADER_STAGES_EN
20895 #define VGT_SHADER_STAGES_EN__LS_EN__SHIFT                                                                    0x0
20896 #define VGT_SHADER_STAGES_EN__HS_EN__SHIFT                                                                    0x2
20897 #define VGT_SHADER_STAGES_EN__ES_EN__SHIFT                                                                    0x3
20898 #define VGT_SHADER_STAGES_EN__GS_EN__SHIFT                                                                    0x5
20899 #define VGT_SHADER_STAGES_EN__VS_EN__SHIFT                                                                    0x6
20900 #define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN__SHIFT                                                         0x9
20901 #define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0__SHIFT                                                      0xa
20902 #define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1__SHIFT                                                      0xb
20903 #define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN__SHIFT                                                            0xc
20904 #define VGT_SHADER_STAGES_EN__PRIMGEN_EN__SHIFT                                                               0xd
20905 #define VGT_SHADER_STAGES_EN__ORDERED_ID_MODE__SHIFT                                                          0xe
20906 #define VGT_SHADER_STAGES_EN__MAX_PRIMGRP_IN_WAVE__SHIFT                                                      0xf
20907 #define VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH__SHIFT                                                           0x13
20908 #define VGT_SHADER_STAGES_EN__LS_EN_MASK                                                                      0x00000003L
20909 #define VGT_SHADER_STAGES_EN__HS_EN_MASK                                                                      0x00000004L
20910 #define VGT_SHADER_STAGES_EN__ES_EN_MASK                                                                      0x00000018L
20911 #define VGT_SHADER_STAGES_EN__GS_EN_MASK                                                                      0x00000020L
20912 #define VGT_SHADER_STAGES_EN__VS_EN_MASK                                                                      0x000000C0L
20913 #define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN_MASK                                                           0x00000200L
20914 #define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0_MASK                                                        0x00000400L
20915 #define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1_MASK                                                        0x00000800L
20916 #define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN_MASK                                                              0x00001000L
20917 #define VGT_SHADER_STAGES_EN__PRIMGEN_EN_MASK                                                                 0x00002000L
20918 #define VGT_SHADER_STAGES_EN__ORDERED_ID_MODE_MASK                                                            0x00004000L
20919 #define VGT_SHADER_STAGES_EN__MAX_PRIMGRP_IN_WAVE_MASK                                                        0x00078000L
20920 #define VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH_MASK                                                             0x00180000L
20921 //VGT_LS_HS_CONFIG
20922 #define VGT_LS_HS_CONFIG__NUM_PATCHES__SHIFT                                                                  0x0
20923 #define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT                                                              0x8
20924 #define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP__SHIFT                                                             0xe
20925 #define VGT_LS_HS_CONFIG__NUM_PATCHES_MASK                                                                    0x000000FFL
20926 #define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK                                                                0x00003F00L
20927 #define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP_MASK                                                               0x000FC000L
20928 //VGT_GS_VERT_ITEMSIZE
20929 #define VGT_GS_VERT_ITEMSIZE__ITEMSIZE__SHIFT                                                                 0x0
20930 #define VGT_GS_VERT_ITEMSIZE__ITEMSIZE_MASK                                                                   0x00007FFFL
20931 //VGT_GS_VERT_ITEMSIZE_1
20932 #define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE__SHIFT                                                               0x0
20933 #define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE_MASK                                                                 0x00007FFFL
20934 //VGT_GS_VERT_ITEMSIZE_2
20935 #define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE__SHIFT                                                               0x0
20936 #define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE_MASK                                                                 0x00007FFFL
20937 //VGT_GS_VERT_ITEMSIZE_3
20938 #define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE__SHIFT                                                               0x0
20939 #define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE_MASK                                                                 0x00007FFFL
20940 //VGT_TF_PARAM
20941 #define VGT_TF_PARAM__TYPE__SHIFT                                                                             0x0
20942 #define VGT_TF_PARAM__PARTITIONING__SHIFT                                                                     0x2
20943 #define VGT_TF_PARAM__TOPOLOGY__SHIFT                                                                         0x5
20944 #define VGT_TF_PARAM__RESERVED_REDUC_AXIS__SHIFT                                                              0x8
20945 #define VGT_TF_PARAM__DEPRECATED__SHIFT                                                                       0x9
20946 #define VGT_TF_PARAM__DISABLE_DONUTS__SHIFT                                                                   0xe
20947 #define VGT_TF_PARAM__RDREQ_POLICY__SHIFT                                                                     0xf
20948 #define VGT_TF_PARAM__DISTRIBUTION_MODE__SHIFT                                                                0x11
20949 #define VGT_TF_PARAM__TYPE_MASK                                                                               0x00000003L
20950 #define VGT_TF_PARAM__PARTITIONING_MASK                                                                       0x0000001CL
20951 #define VGT_TF_PARAM__TOPOLOGY_MASK                                                                           0x000000E0L
20952 #define VGT_TF_PARAM__RESERVED_REDUC_AXIS_MASK                                                                0x00000100L
20953 #define VGT_TF_PARAM__DEPRECATED_MASK                                                                         0x00000200L
20954 #define VGT_TF_PARAM__DISABLE_DONUTS_MASK                                                                     0x00004000L
20955 #define VGT_TF_PARAM__RDREQ_POLICY_MASK                                                                       0x00008000L
20956 #define VGT_TF_PARAM__DISTRIBUTION_MODE_MASK                                                                  0x00060000L
20957 //DB_ALPHA_TO_MASK
20958 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE__SHIFT                                                         0x0
20959 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0__SHIFT                                                        0x8
20960 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT                                                        0xa
20961 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2__SHIFT                                                        0xc
20962 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3__SHIFT                                                        0xe
20963 #define DB_ALPHA_TO_MASK__OFFSET_ROUND__SHIFT                                                                 0x10
20964 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE_MASK                                                           0x00000001L
20965 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0_MASK                                                          0x00000300L
20966 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1_MASK                                                          0x00000C00L
20967 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2_MASK                                                          0x00003000L
20968 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3_MASK                                                          0x0000C000L
20969 #define DB_ALPHA_TO_MASK__OFFSET_ROUND_MASK                                                                   0x00010000L
20970 //VGT_DISPATCH_DRAW_INDEX
20971 #define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX__SHIFT                                                           0x0
20972 #define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX_MASK                                                             0xFFFFFFFFL
20973 //PA_SU_POLY_OFFSET_DB_FMT_CNTL
20974 #define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS__SHIFT                                     0x0
20975 #define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT__SHIFT                                     0x8
20976 #define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS_MASK                                       0x000000FFL
20977 #define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT_MASK                                       0x00000100L
20978 //PA_SU_POLY_OFFSET_CLAMP
20979 #define PA_SU_POLY_OFFSET_CLAMP__CLAMP__SHIFT                                                                 0x0
20980 #define PA_SU_POLY_OFFSET_CLAMP__CLAMP_MASK                                                                   0xFFFFFFFFL
20981 //PA_SU_POLY_OFFSET_FRONT_SCALE
20982 #define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT                                                           0x0
20983 #define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK                                                             0xFFFFFFFFL
20984 //PA_SU_POLY_OFFSET_FRONT_OFFSET
20985 #define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT                                                         0x0
20986 #define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK                                                           0xFFFFFFFFL
20987 //PA_SU_POLY_OFFSET_BACK_SCALE
20988 #define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT                                                            0x0
20989 #define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK                                                              0xFFFFFFFFL
20990 //PA_SU_POLY_OFFSET_BACK_OFFSET
20991 #define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT                                                          0x0
20992 #define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK                                                            0xFFFFFFFFL
20993 //VGT_GS_INSTANCE_CNT
20994 #define VGT_GS_INSTANCE_CNT__ENABLE__SHIFT                                                                    0x0
20995 #define VGT_GS_INSTANCE_CNT__CNT__SHIFT                                                                       0x2
20996 #define VGT_GS_INSTANCE_CNT__ENABLE_MASK                                                                      0x00000001L
20997 #define VGT_GS_INSTANCE_CNT__CNT_MASK                                                                         0x000001FCL
20998 //VGT_STRMOUT_CONFIG
20999 #define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN__SHIFT                                                             0x0
21000 #define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN__SHIFT                                                             0x1
21001 #define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN__SHIFT                                                             0x2
21002 #define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN__SHIFT                                                             0x3
21003 #define VGT_STRMOUT_CONFIG__RAST_STREAM__SHIFT                                                                0x4
21004 #define VGT_STRMOUT_CONFIG__EN_PRIMS_NEEDED_CNT__SHIFT                                                        0x7
21005 #define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK__SHIFT                                                           0x8
21006 #define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK__SHIFT                                                       0x1f
21007 #define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN_MASK                                                               0x00000001L
21008 #define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN_MASK                                                               0x00000002L
21009 #define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN_MASK                                                               0x00000004L
21010 #define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN_MASK                                                               0x00000008L
21011 #define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK                                                                  0x00000070L
21012 #define VGT_STRMOUT_CONFIG__EN_PRIMS_NEEDED_CNT_MASK                                                          0x00000080L
21013 #define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK_MASK                                                             0x00000F00L
21014 #define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK_MASK                                                         0x80000000L
21015 //VGT_STRMOUT_BUFFER_CONFIG
21016 #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN__SHIFT                                                  0x0
21017 #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN__SHIFT                                                  0x4
21018 #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN__SHIFT                                                  0x8
21019 #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN__SHIFT                                                  0xc
21020 #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN_MASK                                                    0x0000000FL
21021 #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN_MASK                                                    0x000000F0L
21022 #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN_MASK                                                    0x00000F00L
21023 #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN_MASK                                                    0x0000F000L
21024 //VGT_DMA_EVENT_INITIATOR
21025 #define VGT_DMA_EVENT_INITIATOR__EVENT_TYPE__SHIFT                                                            0x0
21026 #define VGT_DMA_EVENT_INITIATOR__ADDRESS_HI__SHIFT                                                            0xa
21027 #define VGT_DMA_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT                                                        0x1b
21028 #define VGT_DMA_EVENT_INITIATOR__EVENT_TYPE_MASK                                                              0x0000003FL
21029 #define VGT_DMA_EVENT_INITIATOR__ADDRESS_HI_MASK                                                              0x07FFFC00L
21030 #define VGT_DMA_EVENT_INITIATOR__EXTENDED_EVENT_MASK                                                          0x08000000L
21031 //PA_SC_CENTROID_PRIORITY_0
21032 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0__SHIFT                                                          0x0
21033 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1__SHIFT                                                          0x4
21034 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2__SHIFT                                                          0x8
21035 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3__SHIFT                                                          0xc
21036 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4__SHIFT                                                          0x10
21037 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5__SHIFT                                                          0x14
21038 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6__SHIFT                                                          0x18
21039 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7__SHIFT                                                          0x1c
21040 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0_MASK                                                            0x0000000FL
21041 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1_MASK                                                            0x000000F0L
21042 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2_MASK                                                            0x00000F00L
21043 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3_MASK                                                            0x0000F000L
21044 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4_MASK                                                            0x000F0000L
21045 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5_MASK                                                            0x00F00000L
21046 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6_MASK                                                            0x0F000000L
21047 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7_MASK                                                            0xF0000000L
21048 //PA_SC_CENTROID_PRIORITY_1
21049 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8__SHIFT                                                          0x0
21050 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9__SHIFT                                                          0x4
21051 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10__SHIFT                                                         0x8
21052 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11__SHIFT                                                         0xc
21053 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12__SHIFT                                                         0x10
21054 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13__SHIFT                                                         0x14
21055 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14__SHIFT                                                         0x18
21056 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15__SHIFT                                                         0x1c
21057 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8_MASK                                                            0x0000000FL
21058 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9_MASK                                                            0x000000F0L
21059 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10_MASK                                                           0x00000F00L
21060 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11_MASK                                                           0x0000F000L
21061 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12_MASK                                                           0x000F0000L
21062 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13_MASK                                                           0x00F00000L
21063 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14_MASK                                                           0x0F000000L
21064 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15_MASK                                                           0xF0000000L
21065 //PA_SC_LINE_CNTL
21066 #define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT                                                             0x9
21067 #define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT                                                                    0xa
21068 #define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA__SHIFT                                                      0xb
21069 #define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA__SHIFT                                                         0xc
21070 #define PA_SC_LINE_CNTL__EXTRA_DX_DY_PRECISION__SHIFT                                                         0xd
21071 #define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK                                                               0x00000200L
21072 #define PA_SC_LINE_CNTL__LAST_PIXEL_MASK                                                                      0x00000400L
21073 #define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA_MASK                                                        0x00000800L
21074 #define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA_MASK                                                           0x00001000L
21075 #define PA_SC_LINE_CNTL__EXTRA_DX_DY_PRECISION_MASK                                                           0x00002000L
21076 //PA_SC_AA_CONFIG
21077 #define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT                                                              0x0
21078 #define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN__SHIFT                                                         0x4
21079 #define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT                                                               0xd
21080 #define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES__SHIFT                                                          0x14
21081 #define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE__SHIFT                                                        0x18
21082 #define PA_SC_AA_CONFIG__COVERAGE_TO_SHADER_SELECT__SHIFT                                                     0x1a
21083 #define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK                                                                0x00000007L
21084 #define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN_MASK                                                           0x00000010L
21085 #define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK                                                                 0x0001E000L
21086 #define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES_MASK                                                            0x00700000L
21087 #define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE_MASK                                                          0x03000000L
21088 #define PA_SC_AA_CONFIG__COVERAGE_TO_SHADER_SELECT_MASK                                                       0x0C000000L
21089 //PA_SU_VTX_CNTL
21090 #define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT                                                                     0x0
21091 #define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT                                                                     0x1
21092 #define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT                                                                     0x3
21093 #define PA_SU_VTX_CNTL__PIX_CENTER_MASK                                                                       0x00000001L
21094 #define PA_SU_VTX_CNTL__ROUND_MODE_MASK                                                                       0x00000006L
21095 #define PA_SU_VTX_CNTL__QUANT_MODE_MASK                                                                       0x00000038L
21096 //PA_CL_GB_VERT_CLIP_ADJ
21097 #define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT                                                          0x0
21098 #define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK                                                            0xFFFFFFFFL
21099 //PA_CL_GB_VERT_DISC_ADJ
21100 #define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT                                                          0x0
21101 #define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK                                                            0xFFFFFFFFL
21102 //PA_CL_GB_HORZ_CLIP_ADJ
21103 #define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT                                                          0x0
21104 #define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK                                                            0xFFFFFFFFL
21105 //PA_CL_GB_HORZ_DISC_ADJ
21106 #define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT                                                          0x0
21107 #define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK                                                            0xFFFFFFFFL
21108 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
21109 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X__SHIFT                                                        0x0
21110 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y__SHIFT                                                        0x4
21111 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X__SHIFT                                                        0x8
21112 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y__SHIFT                                                        0xc
21113 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X__SHIFT                                                        0x10
21114 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y__SHIFT                                                        0x14
21115 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X__SHIFT                                                        0x18
21116 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y__SHIFT                                                        0x1c
21117 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X_MASK                                                          0x0000000FL
21118 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y_MASK                                                          0x000000F0L
21119 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X_MASK                                                          0x00000F00L
21120 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y_MASK                                                          0x0000F000L
21121 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X_MASK                                                          0x000F0000L
21122 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y_MASK                                                          0x00F00000L
21123 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X_MASK                                                          0x0F000000L
21124 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y_MASK                                                          0xF0000000L
21125 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1
21126 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X__SHIFT                                                        0x0
21127 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y__SHIFT                                                        0x4
21128 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X__SHIFT                                                        0x8
21129 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y__SHIFT                                                        0xc
21130 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X__SHIFT                                                        0x10
21131 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y__SHIFT                                                        0x14
21132 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X__SHIFT                                                        0x18
21133 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y__SHIFT                                                        0x1c
21134 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X_MASK                                                          0x0000000FL
21135 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y_MASK                                                          0x000000F0L
21136 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X_MASK                                                          0x00000F00L
21137 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y_MASK                                                          0x0000F000L
21138 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X_MASK                                                          0x000F0000L
21139 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y_MASK                                                          0x00F00000L
21140 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X_MASK                                                          0x0F000000L
21141 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y_MASK                                                          0xF0000000L
21142 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2
21143 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X__SHIFT                                                        0x0
21144 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y__SHIFT                                                        0x4
21145 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X__SHIFT                                                        0x8
21146 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y__SHIFT                                                        0xc
21147 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X__SHIFT                                                       0x10
21148 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y__SHIFT                                                       0x14
21149 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X__SHIFT                                                       0x18
21150 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y__SHIFT                                                       0x1c
21151 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X_MASK                                                          0x0000000FL
21152 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y_MASK                                                          0x000000F0L
21153 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X_MASK                                                          0x00000F00L
21154 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y_MASK                                                          0x0000F000L
21155 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X_MASK                                                         0x000F0000L
21156 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y_MASK                                                         0x00F00000L
21157 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X_MASK                                                         0x0F000000L
21158 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y_MASK                                                         0xF0000000L
21159 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3
21160 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X__SHIFT                                                       0x0
21161 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y__SHIFT                                                       0x4
21162 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X__SHIFT                                                       0x8
21163 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y__SHIFT                                                       0xc
21164 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X__SHIFT                                                       0x10
21165 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y__SHIFT                                                       0x14
21166 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X__SHIFT                                                       0x18
21167 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y__SHIFT                                                       0x1c
21168 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X_MASK                                                         0x0000000FL
21169 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y_MASK                                                         0x000000F0L
21170 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X_MASK                                                         0x00000F00L
21171 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y_MASK                                                         0x0000F000L
21172 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X_MASK                                                         0x000F0000L
21173 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y_MASK                                                         0x00F00000L
21174 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X_MASK                                                         0x0F000000L
21175 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y_MASK                                                         0xF0000000L
21176 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
21177 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X__SHIFT                                                        0x0
21178 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y__SHIFT                                                        0x4
21179 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X__SHIFT                                                        0x8
21180 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y__SHIFT                                                        0xc
21181 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X__SHIFT                                                        0x10
21182 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y__SHIFT                                                        0x14
21183 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X__SHIFT                                                        0x18
21184 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y__SHIFT                                                        0x1c
21185 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X_MASK                                                          0x0000000FL
21186 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y_MASK                                                          0x000000F0L
21187 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X_MASK                                                          0x00000F00L
21188 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y_MASK                                                          0x0000F000L
21189 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X_MASK                                                          0x000F0000L
21190 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y_MASK                                                          0x00F00000L
21191 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X_MASK                                                          0x0F000000L
21192 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y_MASK                                                          0xF0000000L
21193 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1
21194 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X__SHIFT                                                        0x0
21195 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y__SHIFT                                                        0x4
21196 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X__SHIFT                                                        0x8
21197 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y__SHIFT                                                        0xc
21198 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X__SHIFT                                                        0x10
21199 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y__SHIFT                                                        0x14
21200 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X__SHIFT                                                        0x18
21201 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y__SHIFT                                                        0x1c
21202 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X_MASK                                                          0x0000000FL
21203 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y_MASK                                                          0x000000F0L
21204 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X_MASK                                                          0x00000F00L
21205 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y_MASK                                                          0x0000F000L
21206 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X_MASK                                                          0x000F0000L
21207 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y_MASK                                                          0x00F00000L
21208 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X_MASK                                                          0x0F000000L
21209 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y_MASK                                                          0xF0000000L
21210 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2
21211 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X__SHIFT                                                        0x0
21212 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y__SHIFT                                                        0x4
21213 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X__SHIFT                                                        0x8
21214 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y__SHIFT                                                        0xc
21215 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X__SHIFT                                                       0x10
21216 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y__SHIFT                                                       0x14
21217 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X__SHIFT                                                       0x18
21218 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y__SHIFT                                                       0x1c
21219 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X_MASK                                                          0x0000000FL
21220 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y_MASK                                                          0x000000F0L
21221 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X_MASK                                                          0x00000F00L
21222 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y_MASK                                                          0x0000F000L
21223 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X_MASK                                                         0x000F0000L
21224 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y_MASK                                                         0x00F00000L
21225 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X_MASK                                                         0x0F000000L
21226 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y_MASK                                                         0xF0000000L
21227 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3
21228 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X__SHIFT                                                       0x0
21229 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y__SHIFT                                                       0x4
21230 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X__SHIFT                                                       0x8
21231 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y__SHIFT                                                       0xc
21232 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X__SHIFT                                                       0x10
21233 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y__SHIFT                                                       0x14
21234 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X__SHIFT                                                       0x18
21235 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y__SHIFT                                                       0x1c
21236 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X_MASK                                                         0x0000000FL
21237 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y_MASK                                                         0x000000F0L
21238 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X_MASK                                                         0x00000F00L
21239 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y_MASK                                                         0x0000F000L
21240 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X_MASK                                                         0x000F0000L
21241 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y_MASK                                                         0x00F00000L
21242 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X_MASK                                                         0x0F000000L
21243 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y_MASK                                                         0xF0000000L
21244 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
21245 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X__SHIFT                                                        0x0
21246 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y__SHIFT                                                        0x4
21247 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X__SHIFT                                                        0x8
21248 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y__SHIFT                                                        0xc
21249 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X__SHIFT                                                        0x10
21250 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y__SHIFT                                                        0x14
21251 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X__SHIFT                                                        0x18
21252 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y__SHIFT                                                        0x1c
21253 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X_MASK                                                          0x0000000FL
21254 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y_MASK                                                          0x000000F0L
21255 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X_MASK                                                          0x00000F00L
21256 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y_MASK                                                          0x0000F000L
21257 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X_MASK                                                          0x000F0000L
21258 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y_MASK                                                          0x00F00000L
21259 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X_MASK                                                          0x0F000000L
21260 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y_MASK                                                          0xF0000000L
21261 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1
21262 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X__SHIFT                                                        0x0
21263 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y__SHIFT                                                        0x4
21264 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X__SHIFT                                                        0x8
21265 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y__SHIFT                                                        0xc
21266 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X__SHIFT                                                        0x10
21267 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y__SHIFT                                                        0x14
21268 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X__SHIFT                                                        0x18
21269 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y__SHIFT                                                        0x1c
21270 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X_MASK                                                          0x0000000FL
21271 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y_MASK                                                          0x000000F0L
21272 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X_MASK                                                          0x00000F00L
21273 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y_MASK                                                          0x0000F000L
21274 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X_MASK                                                          0x000F0000L
21275 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y_MASK                                                          0x00F00000L
21276 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X_MASK                                                          0x0F000000L
21277 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y_MASK                                                          0xF0000000L
21278 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2
21279 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X__SHIFT                                                        0x0
21280 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y__SHIFT                                                        0x4
21281 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X__SHIFT                                                        0x8
21282 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y__SHIFT                                                        0xc
21283 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X__SHIFT                                                       0x10
21284 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y__SHIFT                                                       0x14
21285 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X__SHIFT                                                       0x18
21286 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y__SHIFT                                                       0x1c
21287 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X_MASK                                                          0x0000000FL
21288 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y_MASK                                                          0x000000F0L
21289 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X_MASK                                                          0x00000F00L
21290 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y_MASK                                                          0x0000F000L
21291 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X_MASK                                                         0x000F0000L
21292 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y_MASK                                                         0x00F00000L
21293 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X_MASK                                                         0x0F000000L
21294 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y_MASK                                                         0xF0000000L
21295 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3
21296 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X__SHIFT                                                       0x0
21297 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y__SHIFT                                                       0x4
21298 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X__SHIFT                                                       0x8
21299 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y__SHIFT                                                       0xc
21300 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X__SHIFT                                                       0x10
21301 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y__SHIFT                                                       0x14
21302 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X__SHIFT                                                       0x18
21303 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y__SHIFT                                                       0x1c
21304 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X_MASK                                                         0x0000000FL
21305 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y_MASK                                                         0x000000F0L
21306 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X_MASK                                                         0x00000F00L
21307 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y_MASK                                                         0x0000F000L
21308 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X_MASK                                                         0x000F0000L
21309 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y_MASK                                                         0x00F00000L
21310 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X_MASK                                                         0x0F000000L
21311 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y_MASK                                                         0xF0000000L
21312 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
21313 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X__SHIFT                                                        0x0
21314 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y__SHIFT                                                        0x4
21315 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X__SHIFT                                                        0x8
21316 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y__SHIFT                                                        0xc
21317 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X__SHIFT                                                        0x10
21318 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y__SHIFT                                                        0x14
21319 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X__SHIFT                                                        0x18
21320 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y__SHIFT                                                        0x1c
21321 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X_MASK                                                          0x0000000FL
21322 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y_MASK                                                          0x000000F0L
21323 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X_MASK                                                          0x00000F00L
21324 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y_MASK                                                          0x0000F000L
21325 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X_MASK                                                          0x000F0000L
21326 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y_MASK                                                          0x00F00000L
21327 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X_MASK                                                          0x0F000000L
21328 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y_MASK                                                          0xF0000000L
21329 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1
21330 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X__SHIFT                                                        0x0
21331 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y__SHIFT                                                        0x4
21332 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X__SHIFT                                                        0x8
21333 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y__SHIFT                                                        0xc
21334 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X__SHIFT                                                        0x10
21335 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y__SHIFT                                                        0x14
21336 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X__SHIFT                                                        0x18
21337 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y__SHIFT                                                        0x1c
21338 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X_MASK                                                          0x0000000FL
21339 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y_MASK                                                          0x000000F0L
21340 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X_MASK                                                          0x00000F00L
21341 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y_MASK                                                          0x0000F000L
21342 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X_MASK                                                          0x000F0000L
21343 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y_MASK                                                          0x00F00000L
21344 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X_MASK                                                          0x0F000000L
21345 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y_MASK                                                          0xF0000000L
21346 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2
21347 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X__SHIFT                                                        0x0
21348 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y__SHIFT                                                        0x4
21349 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X__SHIFT                                                        0x8
21350 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y__SHIFT                                                        0xc
21351 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X__SHIFT                                                       0x10
21352 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y__SHIFT                                                       0x14
21353 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X__SHIFT                                                       0x18
21354 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y__SHIFT                                                       0x1c
21355 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X_MASK                                                          0x0000000FL
21356 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y_MASK                                                          0x000000F0L
21357 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X_MASK                                                          0x00000F00L
21358 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y_MASK                                                          0x0000F000L
21359 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X_MASK                                                         0x000F0000L
21360 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y_MASK                                                         0x00F00000L
21361 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X_MASK                                                         0x0F000000L
21362 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y_MASK                                                         0xF0000000L
21363 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3
21364 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X__SHIFT                                                       0x0
21365 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y__SHIFT                                                       0x4
21366 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X__SHIFT                                                       0x8
21367 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y__SHIFT                                                       0xc
21368 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X__SHIFT                                                       0x10
21369 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y__SHIFT                                                       0x14
21370 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X__SHIFT                                                       0x18
21371 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y__SHIFT                                                       0x1c
21372 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X_MASK                                                         0x0000000FL
21373 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y_MASK                                                         0x000000F0L
21374 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X_MASK                                                         0x00000F00L
21375 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y_MASK                                                         0x0000F000L
21376 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X_MASK                                                         0x000F0000L
21377 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y_MASK                                                         0x00F00000L
21378 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X_MASK                                                         0x0F000000L
21379 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y_MASK                                                         0xF0000000L
21380 //PA_SC_AA_MASK_X0Y0_X1Y0
21381 #define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0__SHIFT                                                          0x0
21382 #define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0__SHIFT                                                          0x10
21383 #define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0_MASK                                                            0x0000FFFFL
21384 #define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0_MASK                                                            0xFFFF0000L
21385 //PA_SC_AA_MASK_X0Y1_X1Y1
21386 #define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1__SHIFT                                                          0x0
21387 #define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1__SHIFT                                                          0x10
21388 #define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1_MASK                                                            0x0000FFFFL
21389 #define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1_MASK                                                            0xFFFF0000L
21390 //PA_SC_SHADER_CONTROL
21391 #define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES__SHIFT                                             0x0
21392 #define PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID__SHIFT                                                    0x2
21393 #define PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION__SHIFT                                                 0x3
21394 #define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES_MASK                                               0x00000003L
21395 #define PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID_MASK                                                      0x00000004L
21396 #define PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION_MASK                                                   0x00000008L
21397 //PA_SC_BINNER_CNTL_0
21398 #define PA_SC_BINNER_CNTL_0__BINNING_MODE__SHIFT                                                              0x0
21399 #define PA_SC_BINNER_CNTL_0__BIN_SIZE_X__SHIFT                                                                0x2
21400 #define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y__SHIFT                                                                0x3
21401 #define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND__SHIFT                                                         0x4
21402 #define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND__SHIFT                                                         0x7
21403 #define PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN__SHIFT                                                    0xa
21404 #define PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN__SHIFT                                                 0xd
21405 #define PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM__SHIFT                                                     0x12
21406 #define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH__SHIFT                                                           0x13
21407 #define PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION__SHIFT                                                     0x1b
21408 #define PA_SC_BINNER_CNTL_0__FLUSH_ON_BINNING_TRANSITION__SHIFT                                               0x1c
21409 #define PA_SC_BINNER_CNTL_0__BINNING_MODE_MASK                                                                0x00000003L
21410 #define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_MASK                                                                  0x00000004L
21411 #define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_MASK                                                                  0x00000008L
21412 #define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND_MASK                                                           0x00000070L
21413 #define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND_MASK                                                           0x00000380L
21414 #define PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN_MASK                                                      0x00001C00L
21415 #define PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN_MASK                                                   0x0003E000L
21416 #define PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM_MASK                                                       0x00040000L
21417 #define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH_MASK                                                             0x07F80000L
21418 #define PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION_MASK                                                       0x08000000L
21419 #define PA_SC_BINNER_CNTL_0__FLUSH_ON_BINNING_TRANSITION_MASK                                                 0x10000000L
21420 //PA_SC_BINNER_CNTL_1
21421 #define PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT__SHIFT                                                           0x0
21422 #define PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH__SHIFT                                                        0x10
21423 #define PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT_MASK                                                             0x0000FFFFL
21424 #define PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH_MASK                                                          0xFFFF0000L
21425 //PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
21426 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE__SHIFT                                        0x0
21427 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT__SHIFT                                 0x1
21428 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE__SHIFT                                       0x5
21429 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT__SHIFT                                0x6
21430 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE__SHIFT                           0xa
21431 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT__SHIFT                                          0xb
21432 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET__SHIFT                                          0xc
21433 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL__SHIFT                      0xd
21434 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL__SHIFT                     0xe
21435 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE__SHIFT             0xf
21436 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE__SHIFT                                 0x10
21437 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT                     0x12
21438 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT                     0x13
21439 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE__SHIFT                               0x14
21440 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE__SHIFT                                 0x15
21441 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE__SHIFT                                     0x16
21442 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE__SHIFT                                    0x17
21443 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE__SHIFT                                0x18
21444 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE_MASK                                          0x00000001L
21445 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT_MASK                                   0x0000001EL
21446 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE_MASK                                         0x00000020L
21447 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT_MASK                                  0x000003C0L
21448 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE_MASK                             0x00000400L
21449 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT_MASK                                            0x00000800L
21450 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET_MASK                                            0x00001000L
21451 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL_MASK                        0x00002000L
21452 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL_MASK                       0x00004000L
21453 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE_MASK               0x00008000L
21454 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE_MASK                                   0x00030000L
21455 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK                       0x00040000L
21456 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK                       0x00080000L
21457 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE_MASK                                 0x00100000L
21458 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE_MASK                                   0x00200000L
21459 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE_MASK                                       0x00400000L
21460 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE_MASK                                      0x00800000L
21461 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE_MASK                                  0x01000000L
21462 //PA_SC_NGG_MODE_CNTL
21463 #define PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE__SHIFT                                                      0x0
21464 #define PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE_MASK                                                        0x000007FFL
21465 //VGT_VERTEX_REUSE_BLOCK_CNTL
21466 #define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT                                                   0x0
21467 #define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK                                                     0x000000FFL
21468 //VGT_OUT_DEALLOC_CNTL
21469 #define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT                                                             0x0
21470 #define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK                                                               0x0000007FL
21471 //CB_COLOR0_BASE
21472 #define CB_COLOR0_BASE__BASE_256B__SHIFT                                                                      0x0
21473 #define CB_COLOR0_BASE__BASE_256B_MASK                                                                        0xFFFFFFFFL
21474 //CB_COLOR0_BASE_EXT
21475 #define CB_COLOR0_BASE_EXT__BASE_256B__SHIFT                                                                  0x0
21476 #define CB_COLOR0_BASE_EXT__BASE_256B_MASK                                                                    0x000000FFL
21477 //CB_COLOR0_ATTRIB2
21478 #define CB_COLOR0_ATTRIB2__MIP0_HEIGHT__SHIFT                                                                 0x0
21479 #define CB_COLOR0_ATTRIB2__MIP0_WIDTH__SHIFT                                                                  0xe
21480 #define CB_COLOR0_ATTRIB2__MAX_MIP__SHIFT                                                                     0x1c
21481 #define CB_COLOR0_ATTRIB2__MIP0_HEIGHT_MASK                                                                   0x00003FFFL
21482 #define CB_COLOR0_ATTRIB2__MIP0_WIDTH_MASK                                                                    0x0FFFC000L
21483 #define CB_COLOR0_ATTRIB2__MAX_MIP_MASK                                                                       0xF0000000L
21484 //CB_COLOR0_VIEW
21485 #define CB_COLOR0_VIEW__SLICE_START__SHIFT                                                                    0x0
21486 #define CB_COLOR0_VIEW__SLICE_MAX__SHIFT                                                                      0xd
21487 #define CB_COLOR0_VIEW__MIP_LEVEL__SHIFT                                                                      0x18
21488 #define CB_COLOR0_VIEW__SLICE_START_MASK                                                                      0x000007FFL
21489 #define CB_COLOR0_VIEW__SLICE_MAX_MASK                                                                        0x00FFE000L
21490 #define CB_COLOR0_VIEW__MIP_LEVEL_MASK                                                                        0x0F000000L
21491 //CB_COLOR0_INFO
21492 #define CB_COLOR0_INFO__ENDIAN__SHIFT                                                                         0x0
21493 #define CB_COLOR0_INFO__FORMAT__SHIFT                                                                         0x2
21494 #define CB_COLOR0_INFO__NUMBER_TYPE__SHIFT                                                                    0x8
21495 #define CB_COLOR0_INFO__COMP_SWAP__SHIFT                                                                      0xb
21496 #define CB_COLOR0_INFO__FAST_CLEAR__SHIFT                                                                     0xd
21497 #define CB_COLOR0_INFO__COMPRESSION__SHIFT                                                                    0xe
21498 #define CB_COLOR0_INFO__BLEND_CLAMP__SHIFT                                                                    0xf
21499 #define CB_COLOR0_INFO__BLEND_BYPASS__SHIFT                                                                   0x10
21500 #define CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT                                                                   0x11
21501 #define CB_COLOR0_INFO__ROUND_MODE__SHIFT                                                                     0x12
21502 #define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST__SHIFT                                                          0x14
21503 #define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT                                                        0x17
21504 #define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE__SHIFT                                                      0x1a
21505 #define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT                                                      0x1b
21506 #define CB_COLOR0_INFO__DCC_ENABLE__SHIFT                                                                     0x1c
21507 #define CB_COLOR0_INFO__CMASK_ADDR_TYPE__SHIFT                                                                0x1d
21508 #define CB_COLOR0_INFO__ENDIAN_MASK                                                                           0x00000003L
21509 #define CB_COLOR0_INFO__FORMAT_MASK                                                                           0x0000007CL
21510 #define CB_COLOR0_INFO__NUMBER_TYPE_MASK                                                                      0x00000700L
21511 #define CB_COLOR0_INFO__COMP_SWAP_MASK                                                                        0x00001800L
21512 #define CB_COLOR0_INFO__FAST_CLEAR_MASK                                                                       0x00002000L
21513 #define CB_COLOR0_INFO__COMPRESSION_MASK                                                                      0x00004000L
21514 #define CB_COLOR0_INFO__BLEND_CLAMP_MASK                                                                      0x00008000L
21515 #define CB_COLOR0_INFO__BLEND_BYPASS_MASK                                                                     0x00010000L
21516 #define CB_COLOR0_INFO__SIMPLE_FLOAT_MASK                                                                     0x00020000L
21517 #define CB_COLOR0_INFO__ROUND_MODE_MASK                                                                       0x00040000L
21518 #define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST_MASK                                                            0x00700000L
21519 #define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL_MASK                                                          0x03800000L
21520 #define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE_MASK                                                        0x04000000L
21521 #define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK                                                        0x08000000L
21522 #define CB_COLOR0_INFO__DCC_ENABLE_MASK                                                                       0x10000000L
21523 #define CB_COLOR0_INFO__CMASK_ADDR_TYPE_MASK                                                                  0x60000000L
21524 //CB_COLOR0_ATTRIB
21525 #define CB_COLOR0_ATTRIB__MIP0_DEPTH__SHIFT                                                                   0x0
21526 #define CB_COLOR0_ATTRIB__META_LINEAR__SHIFT                                                                  0xb
21527 #define CB_COLOR0_ATTRIB__NUM_SAMPLES__SHIFT                                                                  0xc
21528 #define CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT                                                                0xf
21529 #define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT                                                            0x11
21530 #define CB_COLOR0_ATTRIB__COLOR_SW_MODE__SHIFT                                                                0x12
21531 #define CB_COLOR0_ATTRIB__FMASK_SW_MODE__SHIFT                                                                0x17
21532 #define CB_COLOR0_ATTRIB__RESOURCE_TYPE__SHIFT                                                                0x1c
21533 #define CB_COLOR0_ATTRIB__RB_ALIGNED__SHIFT                                                                   0x1e
21534 #define CB_COLOR0_ATTRIB__PIPE_ALIGNED__SHIFT                                                                 0x1f
21535 #define CB_COLOR0_ATTRIB__MIP0_DEPTH_MASK                                                                     0x000007FFL
21536 #define CB_COLOR0_ATTRIB__META_LINEAR_MASK                                                                    0x00000800L
21537 #define CB_COLOR0_ATTRIB__NUM_SAMPLES_MASK                                                                    0x00007000L
21538 #define CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK                                                                  0x00018000L
21539 #define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK                                                              0x00020000L
21540 #define CB_COLOR0_ATTRIB__COLOR_SW_MODE_MASK                                                                  0x007C0000L
21541 #define CB_COLOR0_ATTRIB__FMASK_SW_MODE_MASK                                                                  0x0F800000L
21542 #define CB_COLOR0_ATTRIB__RESOURCE_TYPE_MASK                                                                  0x30000000L
21543 #define CB_COLOR0_ATTRIB__RB_ALIGNED_MASK                                                                     0x40000000L
21544 #define CB_COLOR0_ATTRIB__PIPE_ALIGNED_MASK                                                                   0x80000000L
21545 //CB_COLOR0_DCC_CONTROL
21546 #define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT                                              0x0
21547 #define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT                                                        0x1
21548 #define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT                                             0x2
21549 #define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x4
21550 #define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x5
21551 #define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM__SHIFT                                                         0x7
21552 #define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT                                                  0x9
21553 #define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT                                                     0xa
21554 #define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT                                                   0xe
21555 #define CB_COLOR0_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT                                             0x12
21556 #define CB_COLOR0_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT                                        0x13
21557 #define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK                                                0x00000001L
21558 #define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK                                                          0x00000002L
21559 #define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK                                               0x0000000CL
21560 #define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000010L
21561 #define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000060L
21562 #define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM_MASK                                                           0x00000180L
21563 #define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK                                                    0x00000200L
21564 #define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK                                                       0x00003C00L
21565 #define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK                                                     0x0003C000L
21566 #define CB_COLOR0_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK                                               0x00040000L
21567 #define CB_COLOR0_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK                                          0x00080000L
21568 //CB_COLOR0_CMASK
21569 #define CB_COLOR0_CMASK__BASE_256B__SHIFT                                                                     0x0
21570 #define CB_COLOR0_CMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
21571 //CB_COLOR0_CMASK_BASE_EXT
21572 #define CB_COLOR0_CMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
21573 #define CB_COLOR0_CMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
21574 //CB_COLOR0_FMASK
21575 #define CB_COLOR0_FMASK__BASE_256B__SHIFT                                                                     0x0
21576 #define CB_COLOR0_FMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
21577 //CB_COLOR0_FMASK_BASE_EXT
21578 #define CB_COLOR0_FMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
21579 #define CB_COLOR0_FMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
21580 //CB_COLOR0_CLEAR_WORD0
21581 #define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0__SHIFT                                                             0x0
21582 #define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0_MASK                                                               0xFFFFFFFFL
21583 //CB_COLOR0_CLEAR_WORD1
21584 #define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1__SHIFT                                                             0x0
21585 #define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1_MASK                                                               0xFFFFFFFFL
21586 //CB_COLOR0_DCC_BASE
21587 #define CB_COLOR0_DCC_BASE__BASE_256B__SHIFT                                                                  0x0
21588 #define CB_COLOR0_DCC_BASE__BASE_256B_MASK                                                                    0xFFFFFFFFL
21589 //CB_COLOR0_DCC_BASE_EXT
21590 #define CB_COLOR0_DCC_BASE_EXT__BASE_256B__SHIFT                                                              0x0
21591 #define CB_COLOR0_DCC_BASE_EXT__BASE_256B_MASK                                                                0x000000FFL
21592 //CB_COLOR1_BASE
21593 #define CB_COLOR1_BASE__BASE_256B__SHIFT                                                                      0x0
21594 #define CB_COLOR1_BASE__BASE_256B_MASK                                                                        0xFFFFFFFFL
21595 //CB_COLOR1_BASE_EXT
21596 #define CB_COLOR1_BASE_EXT__BASE_256B__SHIFT                                                                  0x0
21597 #define CB_COLOR1_BASE_EXT__BASE_256B_MASK                                                                    0x000000FFL
21598 //CB_COLOR1_ATTRIB2
21599 #define CB_COLOR1_ATTRIB2__MIP0_HEIGHT__SHIFT                                                                 0x0
21600 #define CB_COLOR1_ATTRIB2__MIP0_WIDTH__SHIFT                                                                  0xe
21601 #define CB_COLOR1_ATTRIB2__MAX_MIP__SHIFT                                                                     0x1c
21602 #define CB_COLOR1_ATTRIB2__MIP0_HEIGHT_MASK                                                                   0x00003FFFL
21603 #define CB_COLOR1_ATTRIB2__MIP0_WIDTH_MASK                                                                    0x0FFFC000L
21604 #define CB_COLOR1_ATTRIB2__MAX_MIP_MASK                                                                       0xF0000000L
21605 //CB_COLOR1_VIEW
21606 #define CB_COLOR1_VIEW__SLICE_START__SHIFT                                                                    0x0
21607 #define CB_COLOR1_VIEW__SLICE_MAX__SHIFT                                                                      0xd
21608 #define CB_COLOR1_VIEW__MIP_LEVEL__SHIFT                                                                      0x18
21609 #define CB_COLOR1_VIEW__SLICE_START_MASK                                                                      0x000007FFL
21610 #define CB_COLOR1_VIEW__SLICE_MAX_MASK                                                                        0x00FFE000L
21611 #define CB_COLOR1_VIEW__MIP_LEVEL_MASK                                                                        0x0F000000L
21612 //CB_COLOR1_INFO
21613 #define CB_COLOR1_INFO__ENDIAN__SHIFT                                                                         0x0
21614 #define CB_COLOR1_INFO__FORMAT__SHIFT                                                                         0x2
21615 #define CB_COLOR1_INFO__NUMBER_TYPE__SHIFT                                                                    0x8
21616 #define CB_COLOR1_INFO__COMP_SWAP__SHIFT                                                                      0xb
21617 #define CB_COLOR1_INFO__FAST_CLEAR__SHIFT                                                                     0xd
21618 #define CB_COLOR1_INFO__COMPRESSION__SHIFT                                                                    0xe
21619 #define CB_COLOR1_INFO__BLEND_CLAMP__SHIFT                                                                    0xf
21620 #define CB_COLOR1_INFO__BLEND_BYPASS__SHIFT                                                                   0x10
21621 #define CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT                                                                   0x11
21622 #define CB_COLOR1_INFO__ROUND_MODE__SHIFT                                                                     0x12
21623 #define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST__SHIFT                                                          0x14
21624 #define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT                                                        0x17
21625 #define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE__SHIFT                                                      0x1a
21626 #define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT                                                      0x1b
21627 #define CB_COLOR1_INFO__DCC_ENABLE__SHIFT                                                                     0x1c
21628 #define CB_COLOR1_INFO__CMASK_ADDR_TYPE__SHIFT                                                                0x1d
21629 #define CB_COLOR1_INFO__ENDIAN_MASK                                                                           0x00000003L
21630 #define CB_COLOR1_INFO__FORMAT_MASK                                                                           0x0000007CL
21631 #define CB_COLOR1_INFO__NUMBER_TYPE_MASK                                                                      0x00000700L
21632 #define CB_COLOR1_INFO__COMP_SWAP_MASK                                                                        0x00001800L
21633 #define CB_COLOR1_INFO__FAST_CLEAR_MASK                                                                       0x00002000L
21634 #define CB_COLOR1_INFO__COMPRESSION_MASK                                                                      0x00004000L
21635 #define CB_COLOR1_INFO__BLEND_CLAMP_MASK                                                                      0x00008000L
21636 #define CB_COLOR1_INFO__BLEND_BYPASS_MASK                                                                     0x00010000L
21637 #define CB_COLOR1_INFO__SIMPLE_FLOAT_MASK                                                                     0x00020000L
21638 #define CB_COLOR1_INFO__ROUND_MODE_MASK                                                                       0x00040000L
21639 #define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST_MASK                                                            0x00700000L
21640 #define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL_MASK                                                          0x03800000L
21641 #define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE_MASK                                                        0x04000000L
21642 #define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK                                                        0x08000000L
21643 #define CB_COLOR1_INFO__DCC_ENABLE_MASK                                                                       0x10000000L
21644 #define CB_COLOR1_INFO__CMASK_ADDR_TYPE_MASK                                                                  0x60000000L
21645 //CB_COLOR1_ATTRIB
21646 #define CB_COLOR1_ATTRIB__MIP0_DEPTH__SHIFT                                                                   0x0
21647 #define CB_COLOR1_ATTRIB__META_LINEAR__SHIFT                                                                  0xb
21648 #define CB_COLOR1_ATTRIB__NUM_SAMPLES__SHIFT                                                                  0xc
21649 #define CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT                                                                0xf
21650 #define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT                                                            0x11
21651 #define CB_COLOR1_ATTRIB__COLOR_SW_MODE__SHIFT                                                                0x12
21652 #define CB_COLOR1_ATTRIB__FMASK_SW_MODE__SHIFT                                                                0x17
21653 #define CB_COLOR1_ATTRIB__RESOURCE_TYPE__SHIFT                                                                0x1c
21654 #define CB_COLOR1_ATTRIB__RB_ALIGNED__SHIFT                                                                   0x1e
21655 #define CB_COLOR1_ATTRIB__PIPE_ALIGNED__SHIFT                                                                 0x1f
21656 #define CB_COLOR1_ATTRIB__MIP0_DEPTH_MASK                                                                     0x000007FFL
21657 #define CB_COLOR1_ATTRIB__META_LINEAR_MASK                                                                    0x00000800L
21658 #define CB_COLOR1_ATTRIB__NUM_SAMPLES_MASK                                                                    0x00007000L
21659 #define CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK                                                                  0x00018000L
21660 #define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK                                                              0x00020000L
21661 #define CB_COLOR1_ATTRIB__COLOR_SW_MODE_MASK                                                                  0x007C0000L
21662 #define CB_COLOR1_ATTRIB__FMASK_SW_MODE_MASK                                                                  0x0F800000L
21663 #define CB_COLOR1_ATTRIB__RESOURCE_TYPE_MASK                                                                  0x30000000L
21664 #define CB_COLOR1_ATTRIB__RB_ALIGNED_MASK                                                                     0x40000000L
21665 #define CB_COLOR1_ATTRIB__PIPE_ALIGNED_MASK                                                                   0x80000000L
21666 //CB_COLOR1_DCC_CONTROL
21667 #define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT                                              0x0
21668 #define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT                                                        0x1
21669 #define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT                                             0x2
21670 #define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x4
21671 #define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x5
21672 #define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM__SHIFT                                                         0x7
21673 #define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT                                                  0x9
21674 #define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT                                                     0xa
21675 #define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT                                                   0xe
21676 #define CB_COLOR1_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT                                             0x12
21677 #define CB_COLOR1_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT                                        0x13
21678 #define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK                                                0x00000001L
21679 #define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK                                                          0x00000002L
21680 #define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK                                               0x0000000CL
21681 #define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000010L
21682 #define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000060L
21683 #define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM_MASK                                                           0x00000180L
21684 #define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK                                                    0x00000200L
21685 #define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK                                                       0x00003C00L
21686 #define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK                                                     0x0003C000L
21687 #define CB_COLOR1_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK                                               0x00040000L
21688 #define CB_COLOR1_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK                                          0x00080000L
21689 //CB_COLOR1_CMASK
21690 #define CB_COLOR1_CMASK__BASE_256B__SHIFT                                                                     0x0
21691 #define CB_COLOR1_CMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
21692 //CB_COLOR1_CMASK_BASE_EXT
21693 #define CB_COLOR1_CMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
21694 #define CB_COLOR1_CMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
21695 //CB_COLOR1_FMASK
21696 #define CB_COLOR1_FMASK__BASE_256B__SHIFT                                                                     0x0
21697 #define CB_COLOR1_FMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
21698 //CB_COLOR1_FMASK_BASE_EXT
21699 #define CB_COLOR1_FMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
21700 #define CB_COLOR1_FMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
21701 //CB_COLOR1_CLEAR_WORD0
21702 #define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0__SHIFT                                                             0x0
21703 #define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0_MASK                                                               0xFFFFFFFFL
21704 //CB_COLOR1_CLEAR_WORD1
21705 #define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1__SHIFT                                                             0x0
21706 #define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1_MASK                                                               0xFFFFFFFFL
21707 //CB_COLOR1_DCC_BASE
21708 #define CB_COLOR1_DCC_BASE__BASE_256B__SHIFT                                                                  0x0
21709 #define CB_COLOR1_DCC_BASE__BASE_256B_MASK                                                                    0xFFFFFFFFL
21710 //CB_COLOR1_DCC_BASE_EXT
21711 #define CB_COLOR1_DCC_BASE_EXT__BASE_256B__SHIFT                                                              0x0
21712 #define CB_COLOR1_DCC_BASE_EXT__BASE_256B_MASK                                                                0x000000FFL
21713 //CB_COLOR2_BASE
21714 #define CB_COLOR2_BASE__BASE_256B__SHIFT                                                                      0x0
21715 #define CB_COLOR2_BASE__BASE_256B_MASK                                                                        0xFFFFFFFFL
21716 //CB_COLOR2_BASE_EXT
21717 #define CB_COLOR2_BASE_EXT__BASE_256B__SHIFT                                                                  0x0
21718 #define CB_COLOR2_BASE_EXT__BASE_256B_MASK                                                                    0x000000FFL
21719 //CB_COLOR2_ATTRIB2
21720 #define CB_COLOR2_ATTRIB2__MIP0_HEIGHT__SHIFT                                                                 0x0
21721 #define CB_COLOR2_ATTRIB2__MIP0_WIDTH__SHIFT                                                                  0xe
21722 #define CB_COLOR2_ATTRIB2__MAX_MIP__SHIFT                                                                     0x1c
21723 #define CB_COLOR2_ATTRIB2__MIP0_HEIGHT_MASK                                                                   0x00003FFFL
21724 #define CB_COLOR2_ATTRIB2__MIP0_WIDTH_MASK                                                                    0x0FFFC000L
21725 #define CB_COLOR2_ATTRIB2__MAX_MIP_MASK                                                                       0xF0000000L
21726 //CB_COLOR2_VIEW
21727 #define CB_COLOR2_VIEW__SLICE_START__SHIFT                                                                    0x0
21728 #define CB_COLOR2_VIEW__SLICE_MAX__SHIFT                                                                      0xd
21729 #define CB_COLOR2_VIEW__MIP_LEVEL__SHIFT                                                                      0x18
21730 #define CB_COLOR2_VIEW__SLICE_START_MASK                                                                      0x000007FFL
21731 #define CB_COLOR2_VIEW__SLICE_MAX_MASK                                                                        0x00FFE000L
21732 #define CB_COLOR2_VIEW__MIP_LEVEL_MASK                                                                        0x0F000000L
21733 //CB_COLOR2_INFO
21734 #define CB_COLOR2_INFO__ENDIAN__SHIFT                                                                         0x0
21735 #define CB_COLOR2_INFO__FORMAT__SHIFT                                                                         0x2
21736 #define CB_COLOR2_INFO__NUMBER_TYPE__SHIFT                                                                    0x8
21737 #define CB_COLOR2_INFO__COMP_SWAP__SHIFT                                                                      0xb
21738 #define CB_COLOR2_INFO__FAST_CLEAR__SHIFT                                                                     0xd
21739 #define CB_COLOR2_INFO__COMPRESSION__SHIFT                                                                    0xe
21740 #define CB_COLOR2_INFO__BLEND_CLAMP__SHIFT                                                                    0xf
21741 #define CB_COLOR2_INFO__BLEND_BYPASS__SHIFT                                                                   0x10
21742 #define CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT                                                                   0x11
21743 #define CB_COLOR2_INFO__ROUND_MODE__SHIFT                                                                     0x12
21744 #define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST__SHIFT                                                          0x14
21745 #define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT                                                        0x17
21746 #define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE__SHIFT                                                      0x1a
21747 #define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT                                                      0x1b
21748 #define CB_COLOR2_INFO__DCC_ENABLE__SHIFT                                                                     0x1c
21749 #define CB_COLOR2_INFO__CMASK_ADDR_TYPE__SHIFT                                                                0x1d
21750 #define CB_COLOR2_INFO__ENDIAN_MASK                                                                           0x00000003L
21751 #define CB_COLOR2_INFO__FORMAT_MASK                                                                           0x0000007CL
21752 #define CB_COLOR2_INFO__NUMBER_TYPE_MASK                                                                      0x00000700L
21753 #define CB_COLOR2_INFO__COMP_SWAP_MASK                                                                        0x00001800L
21754 #define CB_COLOR2_INFO__FAST_CLEAR_MASK                                                                       0x00002000L
21755 #define CB_COLOR2_INFO__COMPRESSION_MASK                                                                      0x00004000L
21756 #define CB_COLOR2_INFO__BLEND_CLAMP_MASK                                                                      0x00008000L
21757 #define CB_COLOR2_INFO__BLEND_BYPASS_MASK                                                                     0x00010000L
21758 #define CB_COLOR2_INFO__SIMPLE_FLOAT_MASK                                                                     0x00020000L
21759 #define CB_COLOR2_INFO__ROUND_MODE_MASK                                                                       0x00040000L
21760 #define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST_MASK                                                            0x00700000L
21761 #define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL_MASK                                                          0x03800000L
21762 #define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE_MASK                                                        0x04000000L
21763 #define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK                                                        0x08000000L
21764 #define CB_COLOR2_INFO__DCC_ENABLE_MASK                                                                       0x10000000L
21765 #define CB_COLOR2_INFO__CMASK_ADDR_TYPE_MASK                                                                  0x60000000L
21766 //CB_COLOR2_ATTRIB
21767 #define CB_COLOR2_ATTRIB__MIP0_DEPTH__SHIFT                                                                   0x0
21768 #define CB_COLOR2_ATTRIB__META_LINEAR__SHIFT                                                                  0xb
21769 #define CB_COLOR2_ATTRIB__NUM_SAMPLES__SHIFT                                                                  0xc
21770 #define CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT                                                                0xf
21771 #define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT                                                            0x11
21772 #define CB_COLOR2_ATTRIB__COLOR_SW_MODE__SHIFT                                                                0x12
21773 #define CB_COLOR2_ATTRIB__FMASK_SW_MODE__SHIFT                                                                0x17
21774 #define CB_COLOR2_ATTRIB__RESOURCE_TYPE__SHIFT                                                                0x1c
21775 #define CB_COLOR2_ATTRIB__RB_ALIGNED__SHIFT                                                                   0x1e
21776 #define CB_COLOR2_ATTRIB__PIPE_ALIGNED__SHIFT                                                                 0x1f
21777 #define CB_COLOR2_ATTRIB__MIP0_DEPTH_MASK                                                                     0x000007FFL
21778 #define CB_COLOR2_ATTRIB__META_LINEAR_MASK                                                                    0x00000800L
21779 #define CB_COLOR2_ATTRIB__NUM_SAMPLES_MASK                                                                    0x00007000L
21780 #define CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK                                                                  0x00018000L
21781 #define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK                                                              0x00020000L
21782 #define CB_COLOR2_ATTRIB__COLOR_SW_MODE_MASK                                                                  0x007C0000L
21783 #define CB_COLOR2_ATTRIB__FMASK_SW_MODE_MASK                                                                  0x0F800000L
21784 #define CB_COLOR2_ATTRIB__RESOURCE_TYPE_MASK                                                                  0x30000000L
21785 #define CB_COLOR2_ATTRIB__RB_ALIGNED_MASK                                                                     0x40000000L
21786 #define CB_COLOR2_ATTRIB__PIPE_ALIGNED_MASK                                                                   0x80000000L
21787 //CB_COLOR2_DCC_CONTROL
21788 #define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT                                              0x0
21789 #define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT                                                        0x1
21790 #define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT                                             0x2
21791 #define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x4
21792 #define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x5
21793 #define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM__SHIFT                                                         0x7
21794 #define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT                                                  0x9
21795 #define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT                                                     0xa
21796 #define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT                                                   0xe
21797 #define CB_COLOR2_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT                                             0x12
21798 #define CB_COLOR2_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT                                        0x13
21799 #define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK                                                0x00000001L
21800 #define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK                                                          0x00000002L
21801 #define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK                                               0x0000000CL
21802 #define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000010L
21803 #define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000060L
21804 #define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM_MASK                                                           0x00000180L
21805 #define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK                                                    0x00000200L
21806 #define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK                                                       0x00003C00L
21807 #define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK                                                     0x0003C000L
21808 #define CB_COLOR2_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK                                               0x00040000L
21809 #define CB_COLOR2_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK                                          0x00080000L
21810 //CB_COLOR2_CMASK
21811 #define CB_COLOR2_CMASK__BASE_256B__SHIFT                                                                     0x0
21812 #define CB_COLOR2_CMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
21813 //CB_COLOR2_CMASK_BASE_EXT
21814 #define CB_COLOR2_CMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
21815 #define CB_COLOR2_CMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
21816 //CB_COLOR2_FMASK
21817 #define CB_COLOR2_FMASK__BASE_256B__SHIFT                                                                     0x0
21818 #define CB_COLOR2_FMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
21819 //CB_COLOR2_FMASK_BASE_EXT
21820 #define CB_COLOR2_FMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
21821 #define CB_COLOR2_FMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
21822 //CB_COLOR2_CLEAR_WORD0
21823 #define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0__SHIFT                                                             0x0
21824 #define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0_MASK                                                               0xFFFFFFFFL
21825 //CB_COLOR2_CLEAR_WORD1
21826 #define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1__SHIFT                                                             0x0
21827 #define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1_MASK                                                               0xFFFFFFFFL
21828 //CB_COLOR2_DCC_BASE
21829 #define CB_COLOR2_DCC_BASE__BASE_256B__SHIFT                                                                  0x0
21830 #define CB_COLOR2_DCC_BASE__BASE_256B_MASK                                                                    0xFFFFFFFFL
21831 //CB_COLOR2_DCC_BASE_EXT
21832 #define CB_COLOR2_DCC_BASE_EXT__BASE_256B__SHIFT                                                              0x0
21833 #define CB_COLOR2_DCC_BASE_EXT__BASE_256B_MASK                                                                0x000000FFL
21834 //CB_COLOR3_BASE
21835 #define CB_COLOR3_BASE__BASE_256B__SHIFT                                                                      0x0
21836 #define CB_COLOR3_BASE__BASE_256B_MASK                                                                        0xFFFFFFFFL
21837 //CB_COLOR3_BASE_EXT
21838 #define CB_COLOR3_BASE_EXT__BASE_256B__SHIFT                                                                  0x0
21839 #define CB_COLOR3_BASE_EXT__BASE_256B_MASK                                                                    0x000000FFL
21840 //CB_COLOR3_ATTRIB2
21841 #define CB_COLOR3_ATTRIB2__MIP0_HEIGHT__SHIFT                                                                 0x0
21842 #define CB_COLOR3_ATTRIB2__MIP0_WIDTH__SHIFT                                                                  0xe
21843 #define CB_COLOR3_ATTRIB2__MAX_MIP__SHIFT                                                                     0x1c
21844 #define CB_COLOR3_ATTRIB2__MIP0_HEIGHT_MASK                                                                   0x00003FFFL
21845 #define CB_COLOR3_ATTRIB2__MIP0_WIDTH_MASK                                                                    0x0FFFC000L
21846 #define CB_COLOR3_ATTRIB2__MAX_MIP_MASK                                                                       0xF0000000L
21847 //CB_COLOR3_VIEW
21848 #define CB_COLOR3_VIEW__SLICE_START__SHIFT                                                                    0x0
21849 #define CB_COLOR3_VIEW__SLICE_MAX__SHIFT                                                                      0xd
21850 #define CB_COLOR3_VIEW__MIP_LEVEL__SHIFT                                                                      0x18
21851 #define CB_COLOR3_VIEW__SLICE_START_MASK                                                                      0x000007FFL
21852 #define CB_COLOR3_VIEW__SLICE_MAX_MASK                                                                        0x00FFE000L
21853 #define CB_COLOR3_VIEW__MIP_LEVEL_MASK                                                                        0x0F000000L
21854 //CB_COLOR3_INFO
21855 #define CB_COLOR3_INFO__ENDIAN__SHIFT                                                                         0x0
21856 #define CB_COLOR3_INFO__FORMAT__SHIFT                                                                         0x2
21857 #define CB_COLOR3_INFO__NUMBER_TYPE__SHIFT                                                                    0x8
21858 #define CB_COLOR3_INFO__COMP_SWAP__SHIFT                                                                      0xb
21859 #define CB_COLOR3_INFO__FAST_CLEAR__SHIFT                                                                     0xd
21860 #define CB_COLOR3_INFO__COMPRESSION__SHIFT                                                                    0xe
21861 #define CB_COLOR3_INFO__BLEND_CLAMP__SHIFT                                                                    0xf
21862 #define CB_COLOR3_INFO__BLEND_BYPASS__SHIFT                                                                   0x10
21863 #define CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT                                                                   0x11
21864 #define CB_COLOR3_INFO__ROUND_MODE__SHIFT                                                                     0x12
21865 #define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST__SHIFT                                                          0x14
21866 #define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT                                                        0x17
21867 #define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE__SHIFT                                                      0x1a
21868 #define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT                                                      0x1b
21869 #define CB_COLOR3_INFO__DCC_ENABLE__SHIFT                                                                     0x1c
21870 #define CB_COLOR3_INFO__CMASK_ADDR_TYPE__SHIFT                                                                0x1d
21871 #define CB_COLOR3_INFO__ENDIAN_MASK                                                                           0x00000003L
21872 #define CB_COLOR3_INFO__FORMAT_MASK                                                                           0x0000007CL
21873 #define CB_COLOR3_INFO__NUMBER_TYPE_MASK                                                                      0x00000700L
21874 #define CB_COLOR3_INFO__COMP_SWAP_MASK                                                                        0x00001800L
21875 #define CB_COLOR3_INFO__FAST_CLEAR_MASK                                                                       0x00002000L
21876 #define CB_COLOR3_INFO__COMPRESSION_MASK                                                                      0x00004000L
21877 #define CB_COLOR3_INFO__BLEND_CLAMP_MASK                                                                      0x00008000L
21878 #define CB_COLOR3_INFO__BLEND_BYPASS_MASK                                                                     0x00010000L
21879 #define CB_COLOR3_INFO__SIMPLE_FLOAT_MASK                                                                     0x00020000L
21880 #define CB_COLOR3_INFO__ROUND_MODE_MASK                                                                       0x00040000L
21881 #define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST_MASK                                                            0x00700000L
21882 #define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL_MASK                                                          0x03800000L
21883 #define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE_MASK                                                        0x04000000L
21884 #define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK                                                        0x08000000L
21885 #define CB_COLOR3_INFO__DCC_ENABLE_MASK                                                                       0x10000000L
21886 #define CB_COLOR3_INFO__CMASK_ADDR_TYPE_MASK                                                                  0x60000000L
21887 //CB_COLOR3_ATTRIB
21888 #define CB_COLOR3_ATTRIB__MIP0_DEPTH__SHIFT                                                                   0x0
21889 #define CB_COLOR3_ATTRIB__META_LINEAR__SHIFT                                                                  0xb
21890 #define CB_COLOR3_ATTRIB__NUM_SAMPLES__SHIFT                                                                  0xc
21891 #define CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT                                                                0xf
21892 #define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT                                                            0x11
21893 #define CB_COLOR3_ATTRIB__COLOR_SW_MODE__SHIFT                                                                0x12
21894 #define CB_COLOR3_ATTRIB__FMASK_SW_MODE__SHIFT                                                                0x17
21895 #define CB_COLOR3_ATTRIB__RESOURCE_TYPE__SHIFT                                                                0x1c
21896 #define CB_COLOR3_ATTRIB__RB_ALIGNED__SHIFT                                                                   0x1e
21897 #define CB_COLOR3_ATTRIB__PIPE_ALIGNED__SHIFT                                                                 0x1f
21898 #define CB_COLOR3_ATTRIB__MIP0_DEPTH_MASK                                                                     0x000007FFL
21899 #define CB_COLOR3_ATTRIB__META_LINEAR_MASK                                                                    0x00000800L
21900 #define CB_COLOR3_ATTRIB__NUM_SAMPLES_MASK                                                                    0x00007000L
21901 #define CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK                                                                  0x00018000L
21902 #define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK                                                              0x00020000L
21903 #define CB_COLOR3_ATTRIB__COLOR_SW_MODE_MASK                                                                  0x007C0000L
21904 #define CB_COLOR3_ATTRIB__FMASK_SW_MODE_MASK                                                                  0x0F800000L
21905 #define CB_COLOR3_ATTRIB__RESOURCE_TYPE_MASK                                                                  0x30000000L
21906 #define CB_COLOR3_ATTRIB__RB_ALIGNED_MASK                                                                     0x40000000L
21907 #define CB_COLOR3_ATTRIB__PIPE_ALIGNED_MASK                                                                   0x80000000L
21908 //CB_COLOR3_DCC_CONTROL
21909 #define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT                                              0x0
21910 #define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT                                                        0x1
21911 #define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT                                             0x2
21912 #define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x4
21913 #define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x5
21914 #define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM__SHIFT                                                         0x7
21915 #define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT                                                  0x9
21916 #define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT                                                     0xa
21917 #define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT                                                   0xe
21918 #define CB_COLOR3_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT                                             0x12
21919 #define CB_COLOR3_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT                                        0x13
21920 #define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK                                                0x00000001L
21921 #define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK                                                          0x00000002L
21922 #define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK                                               0x0000000CL
21923 #define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000010L
21924 #define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000060L
21925 #define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM_MASK                                                           0x00000180L
21926 #define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK                                                    0x00000200L
21927 #define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK                                                       0x00003C00L
21928 #define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK                                                     0x0003C000L
21929 #define CB_COLOR3_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK                                               0x00040000L
21930 #define CB_COLOR3_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK                                          0x00080000L
21931 //CB_COLOR3_CMASK
21932 #define CB_COLOR3_CMASK__BASE_256B__SHIFT                                                                     0x0
21933 #define CB_COLOR3_CMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
21934 //CB_COLOR3_CMASK_BASE_EXT
21935 #define CB_COLOR3_CMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
21936 #define CB_COLOR3_CMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
21937 //CB_COLOR3_FMASK
21938 #define CB_COLOR3_FMASK__BASE_256B__SHIFT                                                                     0x0
21939 #define CB_COLOR3_FMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
21940 //CB_COLOR3_FMASK_BASE_EXT
21941 #define CB_COLOR3_FMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
21942 #define CB_COLOR3_FMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
21943 //CB_COLOR3_CLEAR_WORD0
21944 #define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0__SHIFT                                                             0x0
21945 #define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0_MASK                                                               0xFFFFFFFFL
21946 //CB_COLOR3_CLEAR_WORD1
21947 #define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1__SHIFT                                                             0x0
21948 #define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1_MASK                                                               0xFFFFFFFFL
21949 //CB_COLOR3_DCC_BASE
21950 #define CB_COLOR3_DCC_BASE__BASE_256B__SHIFT                                                                  0x0
21951 #define CB_COLOR3_DCC_BASE__BASE_256B_MASK                                                                    0xFFFFFFFFL
21952 //CB_COLOR3_DCC_BASE_EXT
21953 #define CB_COLOR3_DCC_BASE_EXT__BASE_256B__SHIFT                                                              0x0
21954 #define CB_COLOR3_DCC_BASE_EXT__BASE_256B_MASK                                                                0x000000FFL
21955 //CB_COLOR4_BASE
21956 #define CB_COLOR4_BASE__BASE_256B__SHIFT                                                                      0x0
21957 #define CB_COLOR4_BASE__BASE_256B_MASK                                                                        0xFFFFFFFFL
21958 //CB_COLOR4_BASE_EXT
21959 #define CB_COLOR4_BASE_EXT__BASE_256B__SHIFT                                                                  0x0
21960 #define CB_COLOR4_BASE_EXT__BASE_256B_MASK                                                                    0x000000FFL
21961 //CB_COLOR4_ATTRIB2
21962 #define CB_COLOR4_ATTRIB2__MIP0_HEIGHT__SHIFT                                                                 0x0
21963 #define CB_COLOR4_ATTRIB2__MIP0_WIDTH__SHIFT                                                                  0xe
21964 #define CB_COLOR4_ATTRIB2__MAX_MIP__SHIFT                                                                     0x1c
21965 #define CB_COLOR4_ATTRIB2__MIP0_HEIGHT_MASK                                                                   0x00003FFFL
21966 #define CB_COLOR4_ATTRIB2__MIP0_WIDTH_MASK                                                                    0x0FFFC000L
21967 #define CB_COLOR4_ATTRIB2__MAX_MIP_MASK                                                                       0xF0000000L
21968 //CB_COLOR4_VIEW
21969 #define CB_COLOR4_VIEW__SLICE_START__SHIFT                                                                    0x0
21970 #define CB_COLOR4_VIEW__SLICE_MAX__SHIFT                                                                      0xd
21971 #define CB_COLOR4_VIEW__MIP_LEVEL__SHIFT                                                                      0x18
21972 #define CB_COLOR4_VIEW__SLICE_START_MASK                                                                      0x000007FFL
21973 #define CB_COLOR4_VIEW__SLICE_MAX_MASK                                                                        0x00FFE000L
21974 #define CB_COLOR4_VIEW__MIP_LEVEL_MASK                                                                        0x0F000000L
21975 //CB_COLOR4_INFO
21976 #define CB_COLOR4_INFO__ENDIAN__SHIFT                                                                         0x0
21977 #define CB_COLOR4_INFO__FORMAT__SHIFT                                                                         0x2
21978 #define CB_COLOR4_INFO__NUMBER_TYPE__SHIFT                                                                    0x8
21979 #define CB_COLOR4_INFO__COMP_SWAP__SHIFT                                                                      0xb
21980 #define CB_COLOR4_INFO__FAST_CLEAR__SHIFT                                                                     0xd
21981 #define CB_COLOR4_INFO__COMPRESSION__SHIFT                                                                    0xe
21982 #define CB_COLOR4_INFO__BLEND_CLAMP__SHIFT                                                                    0xf
21983 #define CB_COLOR4_INFO__BLEND_BYPASS__SHIFT                                                                   0x10
21984 #define CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT                                                                   0x11
21985 #define CB_COLOR4_INFO__ROUND_MODE__SHIFT                                                                     0x12
21986 #define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST__SHIFT                                                          0x14
21987 #define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT                                                        0x17
21988 #define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE__SHIFT                                                      0x1a
21989 #define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT                                                      0x1b
21990 #define CB_COLOR4_INFO__DCC_ENABLE__SHIFT                                                                     0x1c
21991 #define CB_COLOR4_INFO__CMASK_ADDR_TYPE__SHIFT                                                                0x1d
21992 #define CB_COLOR4_INFO__ENDIAN_MASK                                                                           0x00000003L
21993 #define CB_COLOR4_INFO__FORMAT_MASK                                                                           0x0000007CL
21994 #define CB_COLOR4_INFO__NUMBER_TYPE_MASK                                                                      0x00000700L
21995 #define CB_COLOR4_INFO__COMP_SWAP_MASK                                                                        0x00001800L
21996 #define CB_COLOR4_INFO__FAST_CLEAR_MASK                                                                       0x00002000L
21997 #define CB_COLOR4_INFO__COMPRESSION_MASK                                                                      0x00004000L
21998 #define CB_COLOR4_INFO__BLEND_CLAMP_MASK                                                                      0x00008000L
21999 #define CB_COLOR4_INFO__BLEND_BYPASS_MASK                                                                     0x00010000L
22000 #define CB_COLOR4_INFO__SIMPLE_FLOAT_MASK                                                                     0x00020000L
22001 #define CB_COLOR4_INFO__ROUND_MODE_MASK                                                                       0x00040000L
22002 #define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST_MASK                                                            0x00700000L
22003 #define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL_MASK                                                          0x03800000L
22004 #define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE_MASK                                                        0x04000000L
22005 #define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK                                                        0x08000000L
22006 #define CB_COLOR4_INFO__DCC_ENABLE_MASK                                                                       0x10000000L
22007 #define CB_COLOR4_INFO__CMASK_ADDR_TYPE_MASK                                                                  0x60000000L
22008 //CB_COLOR4_ATTRIB
22009 #define CB_COLOR4_ATTRIB__MIP0_DEPTH__SHIFT                                                                   0x0
22010 #define CB_COLOR4_ATTRIB__META_LINEAR__SHIFT                                                                  0xb
22011 #define CB_COLOR4_ATTRIB__NUM_SAMPLES__SHIFT                                                                  0xc
22012 #define CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT                                                                0xf
22013 #define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT                                                            0x11
22014 #define CB_COLOR4_ATTRIB__COLOR_SW_MODE__SHIFT                                                                0x12
22015 #define CB_COLOR4_ATTRIB__FMASK_SW_MODE__SHIFT                                                                0x17
22016 #define CB_COLOR4_ATTRIB__RESOURCE_TYPE__SHIFT                                                                0x1c
22017 #define CB_COLOR4_ATTRIB__RB_ALIGNED__SHIFT                                                                   0x1e
22018 #define CB_COLOR4_ATTRIB__PIPE_ALIGNED__SHIFT                                                                 0x1f
22019 #define CB_COLOR4_ATTRIB__MIP0_DEPTH_MASK                                                                     0x000007FFL
22020 #define CB_COLOR4_ATTRIB__META_LINEAR_MASK                                                                    0x00000800L
22021 #define CB_COLOR4_ATTRIB__NUM_SAMPLES_MASK                                                                    0x00007000L
22022 #define CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK                                                                  0x00018000L
22023 #define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK                                                              0x00020000L
22024 #define CB_COLOR4_ATTRIB__COLOR_SW_MODE_MASK                                                                  0x007C0000L
22025 #define CB_COLOR4_ATTRIB__FMASK_SW_MODE_MASK                                                                  0x0F800000L
22026 #define CB_COLOR4_ATTRIB__RESOURCE_TYPE_MASK                                                                  0x30000000L
22027 #define CB_COLOR4_ATTRIB__RB_ALIGNED_MASK                                                                     0x40000000L
22028 #define CB_COLOR4_ATTRIB__PIPE_ALIGNED_MASK                                                                   0x80000000L
22029 //CB_COLOR4_DCC_CONTROL
22030 #define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT                                              0x0
22031 #define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT                                                        0x1
22032 #define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT                                             0x2
22033 #define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x4
22034 #define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x5
22035 #define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM__SHIFT                                                         0x7
22036 #define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT                                                  0x9
22037 #define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT                                                     0xa
22038 #define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT                                                   0xe
22039 #define CB_COLOR4_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT                                             0x12
22040 #define CB_COLOR4_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT                                        0x13
22041 #define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK                                                0x00000001L
22042 #define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK                                                          0x00000002L
22043 #define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK                                               0x0000000CL
22044 #define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000010L
22045 #define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000060L
22046 #define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM_MASK                                                           0x00000180L
22047 #define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK                                                    0x00000200L
22048 #define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK                                                       0x00003C00L
22049 #define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK                                                     0x0003C000L
22050 #define CB_COLOR4_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK                                               0x00040000L
22051 #define CB_COLOR4_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK                                          0x00080000L
22052 //CB_COLOR4_CMASK
22053 #define CB_COLOR4_CMASK__BASE_256B__SHIFT                                                                     0x0
22054 #define CB_COLOR4_CMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
22055 //CB_COLOR4_CMASK_BASE_EXT
22056 #define CB_COLOR4_CMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
22057 #define CB_COLOR4_CMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
22058 //CB_COLOR4_FMASK
22059 #define CB_COLOR4_FMASK__BASE_256B__SHIFT                                                                     0x0
22060 #define CB_COLOR4_FMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
22061 //CB_COLOR4_FMASK_BASE_EXT
22062 #define CB_COLOR4_FMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
22063 #define CB_COLOR4_FMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
22064 //CB_COLOR4_CLEAR_WORD0
22065 #define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0__SHIFT                                                             0x0
22066 #define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0_MASK                                                               0xFFFFFFFFL
22067 //CB_COLOR4_CLEAR_WORD1
22068 #define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1__SHIFT                                                             0x0
22069 #define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1_MASK                                                               0xFFFFFFFFL
22070 //CB_COLOR4_DCC_BASE
22071 #define CB_COLOR4_DCC_BASE__BASE_256B__SHIFT                                                                  0x0
22072 #define CB_COLOR4_DCC_BASE__BASE_256B_MASK                                                                    0xFFFFFFFFL
22073 //CB_COLOR4_DCC_BASE_EXT
22074 #define CB_COLOR4_DCC_BASE_EXT__BASE_256B__SHIFT                                                              0x0
22075 #define CB_COLOR4_DCC_BASE_EXT__BASE_256B_MASK                                                                0x000000FFL
22076 //CB_COLOR5_BASE
22077 #define CB_COLOR5_BASE__BASE_256B__SHIFT                                                                      0x0
22078 #define CB_COLOR5_BASE__BASE_256B_MASK                                                                        0xFFFFFFFFL
22079 //CB_COLOR5_BASE_EXT
22080 #define CB_COLOR5_BASE_EXT__BASE_256B__SHIFT                                                                  0x0
22081 #define CB_COLOR5_BASE_EXT__BASE_256B_MASK                                                                    0x000000FFL
22082 //CB_COLOR5_ATTRIB2
22083 #define CB_COLOR5_ATTRIB2__MIP0_HEIGHT__SHIFT                                                                 0x0
22084 #define CB_COLOR5_ATTRIB2__MIP0_WIDTH__SHIFT                                                                  0xe
22085 #define CB_COLOR5_ATTRIB2__MAX_MIP__SHIFT                                                                     0x1c
22086 #define CB_COLOR5_ATTRIB2__MIP0_HEIGHT_MASK                                                                   0x00003FFFL
22087 #define CB_COLOR5_ATTRIB2__MIP0_WIDTH_MASK                                                                    0x0FFFC000L
22088 #define CB_COLOR5_ATTRIB2__MAX_MIP_MASK                                                                       0xF0000000L
22089 //CB_COLOR5_VIEW
22090 #define CB_COLOR5_VIEW__SLICE_START__SHIFT                                                                    0x0
22091 #define CB_COLOR5_VIEW__SLICE_MAX__SHIFT                                                                      0xd
22092 #define CB_COLOR5_VIEW__MIP_LEVEL__SHIFT                                                                      0x18
22093 #define CB_COLOR5_VIEW__SLICE_START_MASK                                                                      0x000007FFL
22094 #define CB_COLOR5_VIEW__SLICE_MAX_MASK                                                                        0x00FFE000L
22095 #define CB_COLOR5_VIEW__MIP_LEVEL_MASK                                                                        0x0F000000L
22096 //CB_COLOR5_INFO
22097 #define CB_COLOR5_INFO__ENDIAN__SHIFT                                                                         0x0
22098 #define CB_COLOR5_INFO__FORMAT__SHIFT                                                                         0x2
22099 #define CB_COLOR5_INFO__NUMBER_TYPE__SHIFT                                                                    0x8
22100 #define CB_COLOR5_INFO__COMP_SWAP__SHIFT                                                                      0xb
22101 #define CB_COLOR5_INFO__FAST_CLEAR__SHIFT                                                                     0xd
22102 #define CB_COLOR5_INFO__COMPRESSION__SHIFT                                                                    0xe
22103 #define CB_COLOR5_INFO__BLEND_CLAMP__SHIFT                                                                    0xf
22104 #define CB_COLOR5_INFO__BLEND_BYPASS__SHIFT                                                                   0x10
22105 #define CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT                                                                   0x11
22106 #define CB_COLOR5_INFO__ROUND_MODE__SHIFT                                                                     0x12
22107 #define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST__SHIFT                                                          0x14
22108 #define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT                                                        0x17
22109 #define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE__SHIFT                                                      0x1a
22110 #define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT                                                      0x1b
22111 #define CB_COLOR5_INFO__DCC_ENABLE__SHIFT                                                                     0x1c
22112 #define CB_COLOR5_INFO__CMASK_ADDR_TYPE__SHIFT                                                                0x1d
22113 #define CB_COLOR5_INFO__ENDIAN_MASK                                                                           0x00000003L
22114 #define CB_COLOR5_INFO__FORMAT_MASK                                                                           0x0000007CL
22115 #define CB_COLOR5_INFO__NUMBER_TYPE_MASK                                                                      0x00000700L
22116 #define CB_COLOR5_INFO__COMP_SWAP_MASK                                                                        0x00001800L
22117 #define CB_COLOR5_INFO__FAST_CLEAR_MASK                                                                       0x00002000L
22118 #define CB_COLOR5_INFO__COMPRESSION_MASK                                                                      0x00004000L
22119 #define CB_COLOR5_INFO__BLEND_CLAMP_MASK                                                                      0x00008000L
22120 #define CB_COLOR5_INFO__BLEND_BYPASS_MASK                                                                     0x00010000L
22121 #define CB_COLOR5_INFO__SIMPLE_FLOAT_MASK                                                                     0x00020000L
22122 #define CB_COLOR5_INFO__ROUND_MODE_MASK                                                                       0x00040000L
22123 #define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST_MASK                                                            0x00700000L
22124 #define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL_MASK                                                          0x03800000L
22125 #define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE_MASK                                                        0x04000000L
22126 #define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK                                                        0x08000000L
22127 #define CB_COLOR5_INFO__DCC_ENABLE_MASK                                                                       0x10000000L
22128 #define CB_COLOR5_INFO__CMASK_ADDR_TYPE_MASK                                                                  0x60000000L
22129 //CB_COLOR5_ATTRIB
22130 #define CB_COLOR5_ATTRIB__MIP0_DEPTH__SHIFT                                                                   0x0
22131 #define CB_COLOR5_ATTRIB__META_LINEAR__SHIFT                                                                  0xb
22132 #define CB_COLOR5_ATTRIB__NUM_SAMPLES__SHIFT                                                                  0xc
22133 #define CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT                                                                0xf
22134 #define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT                                                            0x11
22135 #define CB_COLOR5_ATTRIB__COLOR_SW_MODE__SHIFT                                                                0x12
22136 #define CB_COLOR5_ATTRIB__FMASK_SW_MODE__SHIFT                                                                0x17
22137 #define CB_COLOR5_ATTRIB__RESOURCE_TYPE__SHIFT                                                                0x1c
22138 #define CB_COLOR5_ATTRIB__RB_ALIGNED__SHIFT                                                                   0x1e
22139 #define CB_COLOR5_ATTRIB__PIPE_ALIGNED__SHIFT                                                                 0x1f
22140 #define CB_COLOR5_ATTRIB__MIP0_DEPTH_MASK                                                                     0x000007FFL
22141 #define CB_COLOR5_ATTRIB__META_LINEAR_MASK                                                                    0x00000800L
22142 #define CB_COLOR5_ATTRIB__NUM_SAMPLES_MASK                                                                    0x00007000L
22143 #define CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK                                                                  0x00018000L
22144 #define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK                                                              0x00020000L
22145 #define CB_COLOR5_ATTRIB__COLOR_SW_MODE_MASK                                                                  0x007C0000L
22146 #define CB_COLOR5_ATTRIB__FMASK_SW_MODE_MASK                                                                  0x0F800000L
22147 #define CB_COLOR5_ATTRIB__RESOURCE_TYPE_MASK                                                                  0x30000000L
22148 #define CB_COLOR5_ATTRIB__RB_ALIGNED_MASK                                                                     0x40000000L
22149 #define CB_COLOR5_ATTRIB__PIPE_ALIGNED_MASK                                                                   0x80000000L
22150 //CB_COLOR5_DCC_CONTROL
22151 #define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT                                              0x0
22152 #define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT                                                        0x1
22153 #define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT                                             0x2
22154 #define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x4
22155 #define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x5
22156 #define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM__SHIFT                                                         0x7
22157 #define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT                                                  0x9
22158 #define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT                                                     0xa
22159 #define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT                                                   0xe
22160 #define CB_COLOR5_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT                                             0x12
22161 #define CB_COLOR5_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT                                        0x13
22162 #define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK                                                0x00000001L
22163 #define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK                                                          0x00000002L
22164 #define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK                                               0x0000000CL
22165 #define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000010L
22166 #define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000060L
22167 #define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM_MASK                                                           0x00000180L
22168 #define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK                                                    0x00000200L
22169 #define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK                                                       0x00003C00L
22170 #define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK                                                     0x0003C000L
22171 #define CB_COLOR5_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK                                               0x00040000L
22172 #define CB_COLOR5_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK                                          0x00080000L
22173 //CB_COLOR5_CMASK
22174 #define CB_COLOR5_CMASK__BASE_256B__SHIFT                                                                     0x0
22175 #define CB_COLOR5_CMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
22176 //CB_COLOR5_CMASK_BASE_EXT
22177 #define CB_COLOR5_CMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
22178 #define CB_COLOR5_CMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
22179 //CB_COLOR5_FMASK
22180 #define CB_COLOR5_FMASK__BASE_256B__SHIFT                                                                     0x0
22181 #define CB_COLOR5_FMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
22182 //CB_COLOR5_FMASK_BASE_EXT
22183 #define CB_COLOR5_FMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
22184 #define CB_COLOR5_FMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
22185 //CB_COLOR5_CLEAR_WORD0
22186 #define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0__SHIFT                                                             0x0
22187 #define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0_MASK                                                               0xFFFFFFFFL
22188 //CB_COLOR5_CLEAR_WORD1
22189 #define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1__SHIFT                                                             0x0
22190 #define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1_MASK                                                               0xFFFFFFFFL
22191 //CB_COLOR5_DCC_BASE
22192 #define CB_COLOR5_DCC_BASE__BASE_256B__SHIFT                                                                  0x0
22193 #define CB_COLOR5_DCC_BASE__BASE_256B_MASK                                                                    0xFFFFFFFFL
22194 //CB_COLOR5_DCC_BASE_EXT
22195 #define CB_COLOR5_DCC_BASE_EXT__BASE_256B__SHIFT                                                              0x0
22196 #define CB_COLOR5_DCC_BASE_EXT__BASE_256B_MASK                                                                0x000000FFL
22197 //CB_COLOR6_BASE
22198 #define CB_COLOR6_BASE__BASE_256B__SHIFT                                                                      0x0
22199 #define CB_COLOR6_BASE__BASE_256B_MASK                                                                        0xFFFFFFFFL
22200 //CB_COLOR6_BASE_EXT
22201 #define CB_COLOR6_BASE_EXT__BASE_256B__SHIFT                                                                  0x0
22202 #define CB_COLOR6_BASE_EXT__BASE_256B_MASK                                                                    0x000000FFL
22203 //CB_COLOR6_ATTRIB2
22204 #define CB_COLOR6_ATTRIB2__MIP0_HEIGHT__SHIFT                                                                 0x0
22205 #define CB_COLOR6_ATTRIB2__MIP0_WIDTH__SHIFT                                                                  0xe
22206 #define CB_COLOR6_ATTRIB2__MAX_MIP__SHIFT                                                                     0x1c
22207 #define CB_COLOR6_ATTRIB2__MIP0_HEIGHT_MASK                                                                   0x00003FFFL
22208 #define CB_COLOR6_ATTRIB2__MIP0_WIDTH_MASK                                                                    0x0FFFC000L
22209 #define CB_COLOR6_ATTRIB2__MAX_MIP_MASK                                                                       0xF0000000L
22210 //CB_COLOR6_VIEW
22211 #define CB_COLOR6_VIEW__SLICE_START__SHIFT                                                                    0x0
22212 #define CB_COLOR6_VIEW__SLICE_MAX__SHIFT                                                                      0xd
22213 #define CB_COLOR6_VIEW__MIP_LEVEL__SHIFT                                                                      0x18
22214 #define CB_COLOR6_VIEW__SLICE_START_MASK                                                                      0x000007FFL
22215 #define CB_COLOR6_VIEW__SLICE_MAX_MASK                                                                        0x00FFE000L
22216 #define CB_COLOR6_VIEW__MIP_LEVEL_MASK                                                                        0x0F000000L
22217 //CB_COLOR6_INFO
22218 #define CB_COLOR6_INFO__ENDIAN__SHIFT                                                                         0x0
22219 #define CB_COLOR6_INFO__FORMAT__SHIFT                                                                         0x2
22220 #define CB_COLOR6_INFO__NUMBER_TYPE__SHIFT                                                                    0x8
22221 #define CB_COLOR6_INFO__COMP_SWAP__SHIFT                                                                      0xb
22222 #define CB_COLOR6_INFO__FAST_CLEAR__SHIFT                                                                     0xd
22223 #define CB_COLOR6_INFO__COMPRESSION__SHIFT                                                                    0xe
22224 #define CB_COLOR6_INFO__BLEND_CLAMP__SHIFT                                                                    0xf
22225 #define CB_COLOR6_INFO__BLEND_BYPASS__SHIFT                                                                   0x10
22226 #define CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT                                                                   0x11
22227 #define CB_COLOR6_INFO__ROUND_MODE__SHIFT                                                                     0x12
22228 #define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST__SHIFT                                                          0x14
22229 #define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT                                                        0x17
22230 #define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE__SHIFT                                                      0x1a
22231 #define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT                                                      0x1b
22232 #define CB_COLOR6_INFO__DCC_ENABLE__SHIFT                                                                     0x1c
22233 #define CB_COLOR6_INFO__CMASK_ADDR_TYPE__SHIFT                                                                0x1d
22234 #define CB_COLOR6_INFO__ENDIAN_MASK                                                                           0x00000003L
22235 #define CB_COLOR6_INFO__FORMAT_MASK                                                                           0x0000007CL
22236 #define CB_COLOR6_INFO__NUMBER_TYPE_MASK                                                                      0x00000700L
22237 #define CB_COLOR6_INFO__COMP_SWAP_MASK                                                                        0x00001800L
22238 #define CB_COLOR6_INFO__FAST_CLEAR_MASK                                                                       0x00002000L
22239 #define CB_COLOR6_INFO__COMPRESSION_MASK                                                                      0x00004000L
22240 #define CB_COLOR6_INFO__BLEND_CLAMP_MASK                                                                      0x00008000L
22241 #define CB_COLOR6_INFO__BLEND_BYPASS_MASK                                                                     0x00010000L
22242 #define CB_COLOR6_INFO__SIMPLE_FLOAT_MASK                                                                     0x00020000L
22243 #define CB_COLOR6_INFO__ROUND_MODE_MASK                                                                       0x00040000L
22244 #define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST_MASK                                                            0x00700000L
22245 #define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL_MASK                                                          0x03800000L
22246 #define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE_MASK                                                        0x04000000L
22247 #define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK                                                        0x08000000L
22248 #define CB_COLOR6_INFO__DCC_ENABLE_MASK                                                                       0x10000000L
22249 #define CB_COLOR6_INFO__CMASK_ADDR_TYPE_MASK                                                                  0x60000000L
22250 //CB_COLOR6_ATTRIB
22251 #define CB_COLOR6_ATTRIB__MIP0_DEPTH__SHIFT                                                                   0x0
22252 #define CB_COLOR6_ATTRIB__META_LINEAR__SHIFT                                                                  0xb
22253 #define CB_COLOR6_ATTRIB__NUM_SAMPLES__SHIFT                                                                  0xc
22254 #define CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT                                                                0xf
22255 #define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT                                                            0x11
22256 #define CB_COLOR6_ATTRIB__COLOR_SW_MODE__SHIFT                                                                0x12
22257 #define CB_COLOR6_ATTRIB__FMASK_SW_MODE__SHIFT                                                                0x17
22258 #define CB_COLOR6_ATTRIB__RESOURCE_TYPE__SHIFT                                                                0x1c
22259 #define CB_COLOR6_ATTRIB__RB_ALIGNED__SHIFT                                                                   0x1e
22260 #define CB_COLOR6_ATTRIB__PIPE_ALIGNED__SHIFT                                                                 0x1f
22261 #define CB_COLOR6_ATTRIB__MIP0_DEPTH_MASK                                                                     0x000007FFL
22262 #define CB_COLOR6_ATTRIB__META_LINEAR_MASK                                                                    0x00000800L
22263 #define CB_COLOR6_ATTRIB__NUM_SAMPLES_MASK                                                                    0x00007000L
22264 #define CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK                                                                  0x00018000L
22265 #define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK                                                              0x00020000L
22266 #define CB_COLOR6_ATTRIB__COLOR_SW_MODE_MASK                                                                  0x007C0000L
22267 #define CB_COLOR6_ATTRIB__FMASK_SW_MODE_MASK                                                                  0x0F800000L
22268 #define CB_COLOR6_ATTRIB__RESOURCE_TYPE_MASK                                                                  0x30000000L
22269 #define CB_COLOR6_ATTRIB__RB_ALIGNED_MASK                                                                     0x40000000L
22270 #define CB_COLOR6_ATTRIB__PIPE_ALIGNED_MASK                                                                   0x80000000L
22271 //CB_COLOR6_DCC_CONTROL
22272 #define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT                                              0x0
22273 #define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT                                                        0x1
22274 #define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT                                             0x2
22275 #define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x4
22276 #define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x5
22277 #define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM__SHIFT                                                         0x7
22278 #define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT                                                  0x9
22279 #define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT                                                     0xa
22280 #define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT                                                   0xe
22281 #define CB_COLOR6_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT                                             0x12
22282 #define CB_COLOR6_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT                                        0x13
22283 #define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK                                                0x00000001L
22284 #define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK                                                          0x00000002L
22285 #define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK                                               0x0000000CL
22286 #define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000010L
22287 #define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000060L
22288 #define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM_MASK                                                           0x00000180L
22289 #define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK                                                    0x00000200L
22290 #define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK                                                       0x00003C00L
22291 #define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK                                                     0x0003C000L
22292 #define CB_COLOR6_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK                                               0x00040000L
22293 #define CB_COLOR6_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK                                          0x00080000L
22294 //CB_COLOR6_CMASK
22295 #define CB_COLOR6_CMASK__BASE_256B__SHIFT                                                                     0x0
22296 #define CB_COLOR6_CMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
22297 //CB_COLOR6_CMASK_BASE_EXT
22298 #define CB_COLOR6_CMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
22299 #define CB_COLOR6_CMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
22300 //CB_COLOR6_FMASK
22301 #define CB_COLOR6_FMASK__BASE_256B__SHIFT                                                                     0x0
22302 #define CB_COLOR6_FMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
22303 //CB_COLOR6_FMASK_BASE_EXT
22304 #define CB_COLOR6_FMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
22305 #define CB_COLOR6_FMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
22306 //CB_COLOR6_CLEAR_WORD0
22307 #define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0__SHIFT                                                             0x0
22308 #define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0_MASK                                                               0xFFFFFFFFL
22309 //CB_COLOR6_CLEAR_WORD1
22310 #define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1__SHIFT                                                             0x0
22311 #define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1_MASK                                                               0xFFFFFFFFL
22312 //CB_COLOR6_DCC_BASE
22313 #define CB_COLOR6_DCC_BASE__BASE_256B__SHIFT                                                                  0x0
22314 #define CB_COLOR6_DCC_BASE__BASE_256B_MASK                                                                    0xFFFFFFFFL
22315 //CB_COLOR6_DCC_BASE_EXT
22316 #define CB_COLOR6_DCC_BASE_EXT__BASE_256B__SHIFT                                                              0x0
22317 #define CB_COLOR6_DCC_BASE_EXT__BASE_256B_MASK                                                                0x000000FFL
22318 //CB_COLOR7_BASE
22319 #define CB_COLOR7_BASE__BASE_256B__SHIFT                                                                      0x0
22320 #define CB_COLOR7_BASE__BASE_256B_MASK                                                                        0xFFFFFFFFL
22321 //CB_COLOR7_BASE_EXT
22322 #define CB_COLOR7_BASE_EXT__BASE_256B__SHIFT                                                                  0x0
22323 #define CB_COLOR7_BASE_EXT__BASE_256B_MASK                                                                    0x000000FFL
22324 //CB_COLOR7_ATTRIB2
22325 #define CB_COLOR7_ATTRIB2__MIP0_HEIGHT__SHIFT                                                                 0x0
22326 #define CB_COLOR7_ATTRIB2__MIP0_WIDTH__SHIFT                                                                  0xe
22327 #define CB_COLOR7_ATTRIB2__MAX_MIP__SHIFT                                                                     0x1c
22328 #define CB_COLOR7_ATTRIB2__MIP0_HEIGHT_MASK                                                                   0x00003FFFL
22329 #define CB_COLOR7_ATTRIB2__MIP0_WIDTH_MASK                                                                    0x0FFFC000L
22330 #define CB_COLOR7_ATTRIB2__MAX_MIP_MASK                                                                       0xF0000000L
22331 //CB_COLOR7_VIEW
22332 #define CB_COLOR7_VIEW__SLICE_START__SHIFT                                                                    0x0
22333 #define CB_COLOR7_VIEW__SLICE_MAX__SHIFT                                                                      0xd
22334 #define CB_COLOR7_VIEW__MIP_LEVEL__SHIFT                                                                      0x18
22335 #define CB_COLOR7_VIEW__SLICE_START_MASK                                                                      0x000007FFL
22336 #define CB_COLOR7_VIEW__SLICE_MAX_MASK                                                                        0x00FFE000L
22337 #define CB_COLOR7_VIEW__MIP_LEVEL_MASK                                                                        0x0F000000L
22338 //CB_COLOR7_INFO
22339 #define CB_COLOR7_INFO__ENDIAN__SHIFT                                                                         0x0
22340 #define CB_COLOR7_INFO__FORMAT__SHIFT                                                                         0x2
22341 #define CB_COLOR7_INFO__NUMBER_TYPE__SHIFT                                                                    0x8
22342 #define CB_COLOR7_INFO__COMP_SWAP__SHIFT                                                                      0xb
22343 #define CB_COLOR7_INFO__FAST_CLEAR__SHIFT                                                                     0xd
22344 #define CB_COLOR7_INFO__COMPRESSION__SHIFT                                                                    0xe
22345 #define CB_COLOR7_INFO__BLEND_CLAMP__SHIFT                                                                    0xf
22346 #define CB_COLOR7_INFO__BLEND_BYPASS__SHIFT                                                                   0x10
22347 #define CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT                                                                   0x11
22348 #define CB_COLOR7_INFO__ROUND_MODE__SHIFT                                                                     0x12
22349 #define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST__SHIFT                                                          0x14
22350 #define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT                                                        0x17
22351 #define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE__SHIFT                                                      0x1a
22352 #define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT                                                      0x1b
22353 #define CB_COLOR7_INFO__DCC_ENABLE__SHIFT                                                                     0x1c
22354 #define CB_COLOR7_INFO__CMASK_ADDR_TYPE__SHIFT                                                                0x1d
22355 #define CB_COLOR7_INFO__ENDIAN_MASK                                                                           0x00000003L
22356 #define CB_COLOR7_INFO__FORMAT_MASK                                                                           0x0000007CL
22357 #define CB_COLOR7_INFO__NUMBER_TYPE_MASK                                                                      0x00000700L
22358 #define CB_COLOR7_INFO__COMP_SWAP_MASK                                                                        0x00001800L
22359 #define CB_COLOR7_INFO__FAST_CLEAR_MASK                                                                       0x00002000L
22360 #define CB_COLOR7_INFO__COMPRESSION_MASK                                                                      0x00004000L
22361 #define CB_COLOR7_INFO__BLEND_CLAMP_MASK                                                                      0x00008000L
22362 #define CB_COLOR7_INFO__BLEND_BYPASS_MASK                                                                     0x00010000L
22363 #define CB_COLOR7_INFO__SIMPLE_FLOAT_MASK                                                                     0x00020000L
22364 #define CB_COLOR7_INFO__ROUND_MODE_MASK                                                                       0x00040000L
22365 #define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST_MASK                                                            0x00700000L
22366 #define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL_MASK                                                          0x03800000L
22367 #define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE_MASK                                                        0x04000000L
22368 #define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK                                                        0x08000000L
22369 #define CB_COLOR7_INFO__DCC_ENABLE_MASK                                                                       0x10000000L
22370 #define CB_COLOR7_INFO__CMASK_ADDR_TYPE_MASK                                                                  0x60000000L
22371 //CB_COLOR7_ATTRIB
22372 #define CB_COLOR7_ATTRIB__MIP0_DEPTH__SHIFT                                                                   0x0
22373 #define CB_COLOR7_ATTRIB__META_LINEAR__SHIFT                                                                  0xb
22374 #define CB_COLOR7_ATTRIB__NUM_SAMPLES__SHIFT                                                                  0xc
22375 #define CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT                                                                0xf
22376 #define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT                                                            0x11
22377 #define CB_COLOR7_ATTRIB__COLOR_SW_MODE__SHIFT                                                                0x12
22378 #define CB_COLOR7_ATTRIB__FMASK_SW_MODE__SHIFT                                                                0x17
22379 #define CB_COLOR7_ATTRIB__RESOURCE_TYPE__SHIFT                                                                0x1c
22380 #define CB_COLOR7_ATTRIB__RB_ALIGNED__SHIFT                                                                   0x1e
22381 #define CB_COLOR7_ATTRIB__PIPE_ALIGNED__SHIFT                                                                 0x1f
22382 #define CB_COLOR7_ATTRIB__MIP0_DEPTH_MASK                                                                     0x000007FFL
22383 #define CB_COLOR7_ATTRIB__META_LINEAR_MASK                                                                    0x00000800L
22384 #define CB_COLOR7_ATTRIB__NUM_SAMPLES_MASK                                                                    0x00007000L
22385 #define CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK                                                                  0x00018000L
22386 #define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK                                                              0x00020000L
22387 #define CB_COLOR7_ATTRIB__COLOR_SW_MODE_MASK                                                                  0x007C0000L
22388 #define CB_COLOR7_ATTRIB__FMASK_SW_MODE_MASK                                                                  0x0F800000L
22389 #define CB_COLOR7_ATTRIB__RESOURCE_TYPE_MASK                                                                  0x30000000L
22390 #define CB_COLOR7_ATTRIB__RB_ALIGNED_MASK                                                                     0x40000000L
22391 #define CB_COLOR7_ATTRIB__PIPE_ALIGNED_MASK                                                                   0x80000000L
22392 //CB_COLOR7_DCC_CONTROL
22393 #define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT                                              0x0
22394 #define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT                                                        0x1
22395 #define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT                                             0x2
22396 #define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x4
22397 #define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x5
22398 #define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM__SHIFT                                                         0x7
22399 #define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT                                                  0x9
22400 #define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT                                                     0xa
22401 #define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT                                                   0xe
22402 #define CB_COLOR7_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT                                             0x12
22403 #define CB_COLOR7_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT                                        0x13
22404 #define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK                                                0x00000001L
22405 #define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK                                                          0x00000002L
22406 #define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK                                               0x0000000CL
22407 #define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000010L
22408 #define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000060L
22409 #define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM_MASK                                                           0x00000180L
22410 #define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK                                                    0x00000200L
22411 #define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK                                                       0x00003C00L
22412 #define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK                                                     0x0003C000L
22413 #define CB_COLOR7_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK                                               0x00040000L
22414 #define CB_COLOR7_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK                                          0x00080000L
22415 //CB_COLOR7_CMASK
22416 #define CB_COLOR7_CMASK__BASE_256B__SHIFT                                                                     0x0
22417 #define CB_COLOR7_CMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
22418 //CB_COLOR7_CMASK_BASE_EXT
22419 #define CB_COLOR7_CMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
22420 #define CB_COLOR7_CMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
22421 //CB_COLOR7_FMASK
22422 #define CB_COLOR7_FMASK__BASE_256B__SHIFT                                                                     0x0
22423 #define CB_COLOR7_FMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
22424 //CB_COLOR7_FMASK_BASE_EXT
22425 #define CB_COLOR7_FMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
22426 #define CB_COLOR7_FMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
22427 //CB_COLOR7_CLEAR_WORD0
22428 #define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0__SHIFT                                                             0x0
22429 #define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0_MASK                                                               0xFFFFFFFFL
22430 //CB_COLOR7_CLEAR_WORD1
22431 #define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1__SHIFT                                                             0x0
22432 #define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1_MASK                                                               0xFFFFFFFFL
22433 //CB_COLOR7_DCC_BASE
22434 #define CB_COLOR7_DCC_BASE__BASE_256B__SHIFT                                                                  0x0
22435 #define CB_COLOR7_DCC_BASE__BASE_256B_MASK                                                                    0xFFFFFFFFL
22436 //CB_COLOR7_DCC_BASE_EXT
22437 #define CB_COLOR7_DCC_BASE_EXT__BASE_256B__SHIFT                                                              0x0
22438 #define CB_COLOR7_DCC_BASE_EXT__BASE_256B_MASK                                                                0x000000FFL
22439 
22440 
22441 // addressBlock: xcd0_gc_gfxudec
22442 //CP_EOP_DONE_ADDR_LO
22443 #define CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT                                                                   0x2
22444 #define CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK                                                                     0xFFFFFFFCL
22445 //CP_EOP_DONE_ADDR_HI
22446 #define CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT                                                                   0x0
22447 #define CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK                                                                     0x0000FFFFL
22448 //CP_EOP_DONE_DATA_LO
22449 #define CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT                                                                   0x0
22450 #define CP_EOP_DONE_DATA_LO__DATA_LO_MASK                                                                     0xFFFFFFFFL
22451 //CP_EOP_DONE_DATA_HI
22452 #define CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT                                                                   0x0
22453 #define CP_EOP_DONE_DATA_HI__DATA_HI_MASK                                                                     0xFFFFFFFFL
22454 //CP_EOP_LAST_FENCE_LO
22455 #define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT                                                            0x0
22456 #define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK                                                              0xFFFFFFFFL
22457 //CP_EOP_LAST_FENCE_HI
22458 #define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT                                                            0x0
22459 #define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK                                                              0xFFFFFFFFL
22460 //CP_STREAM_OUT_ADDR_LO
22461 #define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO__SHIFT                                                      0x2
22462 #define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO_MASK                                                        0xFFFFFFFCL
22463 //CP_STREAM_OUT_ADDR_HI
22464 #define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI__SHIFT                                                      0x0
22465 #define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI_MASK                                                        0x0000FFFFL
22466 //CP_NUM_PRIM_WRITTEN_COUNT0_LO
22467 #define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO__SHIFT                                        0x0
22468 #define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO_MASK                                          0xFFFFFFFFL
22469 //CP_NUM_PRIM_WRITTEN_COUNT0_HI
22470 #define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI__SHIFT                                        0x0
22471 #define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI_MASK                                          0xFFFFFFFFL
22472 //CP_NUM_PRIM_NEEDED_COUNT0_LO
22473 #define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO__SHIFT                                          0x0
22474 #define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO_MASK                                            0xFFFFFFFFL
22475 //CP_NUM_PRIM_NEEDED_COUNT0_HI
22476 #define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI__SHIFT                                          0x0
22477 #define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI_MASK                                            0xFFFFFFFFL
22478 //CP_NUM_PRIM_WRITTEN_COUNT1_LO
22479 #define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO__SHIFT                                        0x0
22480 #define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO_MASK                                          0xFFFFFFFFL
22481 //CP_NUM_PRIM_WRITTEN_COUNT1_HI
22482 #define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI__SHIFT                                        0x0
22483 #define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI_MASK                                          0xFFFFFFFFL
22484 //CP_NUM_PRIM_NEEDED_COUNT1_LO
22485 #define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO__SHIFT                                          0x0
22486 #define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO_MASK                                            0xFFFFFFFFL
22487 //CP_NUM_PRIM_NEEDED_COUNT1_HI
22488 #define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI__SHIFT                                          0x0
22489 #define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI_MASK                                            0xFFFFFFFFL
22490 //CP_NUM_PRIM_WRITTEN_COUNT2_LO
22491 #define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO__SHIFT                                        0x0
22492 #define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO_MASK                                          0xFFFFFFFFL
22493 //CP_NUM_PRIM_WRITTEN_COUNT2_HI
22494 #define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI__SHIFT                                        0x0
22495 #define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI_MASK                                          0xFFFFFFFFL
22496 //CP_NUM_PRIM_NEEDED_COUNT2_LO
22497 #define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO__SHIFT                                          0x0
22498 #define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO_MASK                                            0xFFFFFFFFL
22499 //CP_NUM_PRIM_NEEDED_COUNT2_HI
22500 #define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI__SHIFT                                          0x0
22501 #define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI_MASK                                            0xFFFFFFFFL
22502 //CP_NUM_PRIM_WRITTEN_COUNT3_LO
22503 #define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO__SHIFT                                        0x0
22504 #define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO_MASK                                          0xFFFFFFFFL
22505 //CP_NUM_PRIM_WRITTEN_COUNT3_HI
22506 #define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI__SHIFT                                        0x0
22507 #define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI_MASK                                          0xFFFFFFFFL
22508 //CP_NUM_PRIM_NEEDED_COUNT3_LO
22509 #define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO__SHIFT                                          0x0
22510 #define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO_MASK                                            0xFFFFFFFFL
22511 //CP_NUM_PRIM_NEEDED_COUNT3_HI
22512 #define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI__SHIFT                                          0x0
22513 #define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI_MASK                                            0xFFFFFFFFL
22514 //CP_PIPE_STATS_ADDR_LO
22515 #define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO__SHIFT                                                      0x2
22516 #define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO_MASK                                                        0xFFFFFFFCL
22517 //CP_PIPE_STATS_ADDR_HI
22518 #define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI__SHIFT                                                      0x0
22519 #define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK                                                        0x0000FFFFL
22520 //CP_VGT_IAVERT_COUNT_LO
22521 #define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO__SHIFT                                                        0x0
22522 #define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO_MASK                                                          0xFFFFFFFFL
22523 //CP_VGT_IAVERT_COUNT_HI
22524 #define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI__SHIFT                                                        0x0
22525 #define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI_MASK                                                          0xFFFFFFFFL
22526 //CP_VGT_IAPRIM_COUNT_LO
22527 #define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO__SHIFT                                                        0x0
22528 #define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO_MASK                                                          0xFFFFFFFFL
22529 //CP_VGT_IAPRIM_COUNT_HI
22530 #define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI__SHIFT                                                        0x0
22531 #define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI_MASK                                                          0xFFFFFFFFL
22532 //CP_VGT_GSPRIM_COUNT_LO
22533 #define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO__SHIFT                                                        0x0
22534 #define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO_MASK                                                          0xFFFFFFFFL
22535 //CP_VGT_GSPRIM_COUNT_HI
22536 #define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI__SHIFT                                                        0x0
22537 #define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI_MASK                                                          0xFFFFFFFFL
22538 //CP_VGT_VSINVOC_COUNT_LO
22539 #define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO__SHIFT                                                      0x0
22540 #define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO_MASK                                                        0xFFFFFFFFL
22541 //CP_VGT_VSINVOC_COUNT_HI
22542 #define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI__SHIFT                                                      0x0
22543 #define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI_MASK                                                        0xFFFFFFFFL
22544 //CP_VGT_GSINVOC_COUNT_LO
22545 #define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO__SHIFT                                                      0x0
22546 #define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO_MASK                                                        0xFFFFFFFFL
22547 //CP_VGT_GSINVOC_COUNT_HI
22548 #define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI__SHIFT                                                      0x0
22549 #define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI_MASK                                                        0xFFFFFFFFL
22550 //CP_VGT_HSINVOC_COUNT_LO
22551 #define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO__SHIFT                                                      0x0
22552 #define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO_MASK                                                        0xFFFFFFFFL
22553 //CP_VGT_HSINVOC_COUNT_HI
22554 #define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI__SHIFT                                                      0x0
22555 #define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI_MASK                                                        0xFFFFFFFFL
22556 //CP_VGT_DSINVOC_COUNT_LO
22557 #define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO__SHIFT                                                      0x0
22558 #define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO_MASK                                                        0xFFFFFFFFL
22559 //CP_VGT_DSINVOC_COUNT_HI
22560 #define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI__SHIFT                                                      0x0
22561 #define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI_MASK                                                        0xFFFFFFFFL
22562 //CP_PA_CINVOC_COUNT_LO
22563 #define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO__SHIFT                                                         0x0
22564 #define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO_MASK                                                           0xFFFFFFFFL
22565 //CP_PA_CINVOC_COUNT_HI
22566 #define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI__SHIFT                                                         0x0
22567 #define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI_MASK                                                           0xFFFFFFFFL
22568 //CP_PA_CPRIM_COUNT_LO
22569 #define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO__SHIFT                                                           0x0
22570 #define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO_MASK                                                             0xFFFFFFFFL
22571 //CP_PA_CPRIM_COUNT_HI
22572 #define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI__SHIFT                                                           0x0
22573 #define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI_MASK                                                             0xFFFFFFFFL
22574 //CP_SC_PSINVOC_COUNT0_LO
22575 #define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO__SHIFT                                                     0x0
22576 #define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO_MASK                                                       0xFFFFFFFFL
22577 //CP_SC_PSINVOC_COUNT0_HI
22578 #define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT                                                     0x0
22579 #define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI_MASK                                                       0xFFFFFFFFL
22580 //CP_SC_PSINVOC_COUNT1_LO
22581 #define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE__SHIFT                                                              0x0
22582 #define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE_MASK                                                                0xFFFFFFFFL
22583 //CP_SC_PSINVOC_COUNT1_HI
22584 #define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE__SHIFT                                                              0x0
22585 #define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE_MASK                                                                0xFFFFFFFFL
22586 //CP_VGT_CSINVOC_COUNT_LO
22587 #define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO__SHIFT                                                      0x0
22588 #define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO_MASK                                                        0xFFFFFFFFL
22589 //CP_VGT_CSINVOC_COUNT_HI
22590 #define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI__SHIFT                                                      0x0
22591 #define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI_MASK                                                        0xFFFFFFFFL
22592 //CP_PIPE_STATS_CONTROL
22593 #define CP_PIPE_STATS_CONTROL__CACHE_POLICY__SHIFT                                                            0x19
22594 #define CP_PIPE_STATS_CONTROL__CACHE_POLICY_MASK                                                              0x02000000L
22595 //CP_STREAM_OUT_CONTROL
22596 #define CP_STREAM_OUT_CONTROL__CACHE_POLICY__SHIFT                                                            0x19
22597 #define CP_STREAM_OUT_CONTROL__CACHE_POLICY_MASK                                                              0x02000000L
22598 //CP_STRMOUT_CNTL
22599 #define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE__SHIFT                                                            0x0
22600 #define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE_MASK                                                              0x00000001L
22601 //SCRATCH_REG0
22602 #define SCRATCH_REG0__SCRATCH_REG0__SHIFT                                                                     0x0
22603 #define SCRATCH_REG0__SCRATCH_REG0_MASK                                                                       0xFFFFFFFFL
22604 //SCRATCH_REG1
22605 #define SCRATCH_REG1__SCRATCH_REG1__SHIFT                                                                     0x0
22606 #define SCRATCH_REG1__SCRATCH_REG1_MASK                                                                       0xFFFFFFFFL
22607 //SCRATCH_REG2
22608 #define SCRATCH_REG2__SCRATCH_REG2__SHIFT                                                                     0x0
22609 #define SCRATCH_REG2__SCRATCH_REG2_MASK                                                                       0xFFFFFFFFL
22610 //SCRATCH_REG3
22611 #define SCRATCH_REG3__SCRATCH_REG3__SHIFT                                                                     0x0
22612 #define SCRATCH_REG3__SCRATCH_REG3_MASK                                                                       0xFFFFFFFFL
22613 //SCRATCH_REG4
22614 #define SCRATCH_REG4__SCRATCH_REG4__SHIFT                                                                     0x0
22615 #define SCRATCH_REG4__SCRATCH_REG4_MASK                                                                       0xFFFFFFFFL
22616 //SCRATCH_REG5
22617 #define SCRATCH_REG5__SCRATCH_REG5__SHIFT                                                                     0x0
22618 #define SCRATCH_REG5__SCRATCH_REG5_MASK                                                                       0xFFFFFFFFL
22619 //SCRATCH_REG6
22620 #define SCRATCH_REG6__SCRATCH_REG6__SHIFT                                                                     0x0
22621 #define SCRATCH_REG6__SCRATCH_REG6_MASK                                                                       0xFFFFFFFFL
22622 //SCRATCH_REG7
22623 #define SCRATCH_REG7__SCRATCH_REG7__SHIFT                                                                     0x0
22624 #define SCRATCH_REG7__SCRATCH_REG7_MASK                                                                       0xFFFFFFFFL
22625 //CP_APPEND_DATA_HI
22626 #define CP_APPEND_DATA_HI__DATA__SHIFT                                                                        0x0
22627 #define CP_APPEND_DATA_HI__DATA_MASK                                                                          0xFFFFFFFFL
22628 //CP_APPEND_LAST_CS_FENCE_HI
22629 #define CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE__SHIFT                                                         0x0
22630 #define CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE_MASK                                                           0xFFFFFFFFL
22631 //CP_APPEND_LAST_PS_FENCE_HI
22632 #define CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE__SHIFT                                                         0x0
22633 #define CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE_MASK                                                           0xFFFFFFFFL
22634 //SCRATCH_UMSK
22635 #define SCRATCH_UMSK__OBSOLETE_UMSK__SHIFT                                                                    0x0
22636 #define SCRATCH_UMSK__OBSOLETE_SWAP__SHIFT                                                                    0x10
22637 #define SCRATCH_UMSK__OBSOLETE_UMSK_MASK                                                                      0x000000FFL
22638 #define SCRATCH_UMSK__OBSOLETE_SWAP_MASK                                                                      0x00030000L
22639 //SCRATCH_ADDR
22640 #define SCRATCH_ADDR__OBSOLETE_ADDR__SHIFT                                                                    0x0
22641 #define SCRATCH_ADDR__OBSOLETE_ADDR_MASK                                                                      0xFFFFFFFFL
22642 //CP_PFP_ATOMIC_PREOP_LO
22643 #define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT                                                        0x0
22644 #define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK                                                          0xFFFFFFFFL
22645 //CP_PFP_ATOMIC_PREOP_HI
22646 #define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT                                                        0x0
22647 #define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK                                                          0xFFFFFFFFL
22648 //CP_PFP_GDS_ATOMIC0_PREOP_LO
22649 #define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT                                              0x0
22650 #define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK                                                0xFFFFFFFFL
22651 //CP_PFP_GDS_ATOMIC0_PREOP_HI
22652 #define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT                                              0x0
22653 #define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK                                                0xFFFFFFFFL
22654 //CP_PFP_GDS_ATOMIC1_PREOP_LO
22655 #define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT                                              0x0
22656 #define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK                                                0xFFFFFFFFL
22657 //CP_PFP_GDS_ATOMIC1_PREOP_HI
22658 #define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT                                              0x0
22659 #define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK                                                0xFFFFFFFFL
22660 //CP_APPEND_ADDR_LO
22661 #define CP_APPEND_ADDR_LO__MEM_ADDR_LO__SHIFT                                                                 0x2
22662 #define CP_APPEND_ADDR_LO__MEM_ADDR_LO_MASK                                                                   0xFFFFFFFCL
22663 //CP_APPEND_ADDR_HI
22664 #define CP_APPEND_ADDR_HI__MEM_ADDR_HI__SHIFT                                                                 0x0
22665 #define CP_APPEND_ADDR_HI__CS_PS_SEL__SHIFT                                                                   0x10
22666 #define CP_APPEND_ADDR_HI__CACHE_POLICY__SHIFT                                                                0x19
22667 #define CP_APPEND_ADDR_HI__COMMAND__SHIFT                                                                     0x1d
22668 #define CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK                                                                   0x0000FFFFL
22669 #define CP_APPEND_ADDR_HI__CS_PS_SEL_MASK                                                                     0x00010000L
22670 #define CP_APPEND_ADDR_HI__CACHE_POLICY_MASK                                                                  0x02000000L
22671 #define CP_APPEND_ADDR_HI__COMMAND_MASK                                                                       0xE0000000L
22672 //CP_APPEND_DATA_LO
22673 #define CP_APPEND_DATA_LO__DATA__SHIFT                                                                        0x0
22674 #define CP_APPEND_DATA_LO__DATA_MASK                                                                          0xFFFFFFFFL
22675 //CP_APPEND_LAST_CS_FENCE_LO
22676 #define CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE__SHIFT                                                         0x0
22677 #define CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE_MASK                                                           0xFFFFFFFFL
22678 //CP_APPEND_LAST_PS_FENCE_LO
22679 #define CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE__SHIFT                                                         0x0
22680 #define CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE_MASK                                                           0xFFFFFFFFL
22681 //CP_ATOMIC_PREOP_LO
22682 #define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT                                                            0x0
22683 #define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK                                                              0xFFFFFFFFL
22684 //CP_ME_ATOMIC_PREOP_LO
22685 #define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT                                                         0x0
22686 #define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK                                                           0xFFFFFFFFL
22687 //CP_ATOMIC_PREOP_HI
22688 #define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT                                                            0x0
22689 #define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK                                                              0xFFFFFFFFL
22690 //CP_ME_ATOMIC_PREOP_HI
22691 #define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT                                                         0x0
22692 #define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK                                                           0xFFFFFFFFL
22693 //CP_GDS_ATOMIC0_PREOP_LO
22694 #define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT                                                  0x0
22695 #define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK                                                    0xFFFFFFFFL
22696 //CP_ME_GDS_ATOMIC0_PREOP_LO
22697 #define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT                                               0x0
22698 #define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK                                                 0xFFFFFFFFL
22699 //CP_GDS_ATOMIC0_PREOP_HI
22700 #define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT                                                  0x0
22701 #define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK                                                    0xFFFFFFFFL
22702 //CP_ME_GDS_ATOMIC0_PREOP_HI
22703 #define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT                                               0x0
22704 #define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK                                                 0xFFFFFFFFL
22705 //CP_GDS_ATOMIC1_PREOP_LO
22706 #define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT                                                  0x0
22707 #define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK                                                    0xFFFFFFFFL
22708 //CP_ME_GDS_ATOMIC1_PREOP_LO
22709 #define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT                                               0x0
22710 #define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK                                                 0xFFFFFFFFL
22711 //CP_GDS_ATOMIC1_PREOP_HI
22712 #define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT                                                  0x0
22713 #define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK                                                    0xFFFFFFFFL
22714 //CP_ME_GDS_ATOMIC1_PREOP_HI
22715 #define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT                                               0x0
22716 #define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK                                                 0xFFFFFFFFL
22717 //CP_ME_MC_WADDR_LO
22718 #define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO__SHIFT                                                              0x2
22719 #define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO_MASK                                                                0xFFFFFFFCL
22720 //CP_ME_MC_WADDR_HI
22721 #define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI__SHIFT                                                              0x0
22722 #define CP_ME_MC_WADDR_HI__CACHE_POLICY__SHIFT                                                                0x16
22723 #define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK                                                                0x0000FFFFL
22724 #define CP_ME_MC_WADDR_HI__CACHE_POLICY_MASK                                                                  0x00400000L
22725 //CP_ME_MC_WDATA_LO
22726 #define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO__SHIFT                                                              0x0
22727 #define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO_MASK                                                                0xFFFFFFFFL
22728 //CP_ME_MC_WDATA_HI
22729 #define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI__SHIFT                                                              0x0
22730 #define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI_MASK                                                                0xFFFFFFFFL
22731 //CP_ME_MC_RADDR_LO
22732 #define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO__SHIFT                                                              0x2
22733 #define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO_MASK                                                                0xFFFFFFFCL
22734 //CP_ME_MC_RADDR_HI
22735 #define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI__SHIFT                                                              0x0
22736 #define CP_ME_MC_RADDR_HI__CACHE_POLICY__SHIFT                                                                0x16
22737 #define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK                                                                0x0000FFFFL
22738 #define CP_ME_MC_RADDR_HI__CACHE_POLICY_MASK                                                                  0x00400000L
22739 //CP_SEM_WAIT_TIMER
22740 #define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER__SHIFT                                                              0x0
22741 #define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER_MASK                                                                0xFFFFFFFFL
22742 //CP_SIG_SEM_ADDR_LO
22743 #define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT                                                              0x0
22744 #define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT                                                                0x3
22745 #define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK                                                                0x00000003L
22746 #define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO_MASK                                                                  0xFFFFFFF8L
22747 //CP_SIG_SEM_ADDR_HI
22748 #define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT                                                                0x0
22749 #define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT                                                            0x10
22750 #define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT                                                            0x14
22751 #define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT                                                            0x18
22752 #define CP_SIG_SEM_ADDR_HI__SEM_SELECT__SHIFT                                                                 0x1d
22753 #define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI_MASK                                                                  0x0000FFFFL
22754 #define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK                                                              0x00010000L
22755 #define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK                                                              0x00100000L
22756 #define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK                                                              0x03000000L
22757 #define CP_SIG_SEM_ADDR_HI__SEM_SELECT_MASK                                                                   0xE0000000L
22758 //CP_WAIT_REG_MEM_TIMEOUT
22759 #define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT__SHIFT                                                  0x0
22760 #define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT_MASK                                                    0xFFFFFFFFL
22761 //CP_WAIT_SEM_ADDR_LO
22762 #define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT                                                             0x0
22763 #define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT                                                               0x3
22764 #define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK                                                               0x00000003L
22765 #define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO_MASK                                                                 0xFFFFFFF8L
22766 //CP_WAIT_SEM_ADDR_HI
22767 #define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT                                                               0x0
22768 #define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT                                                           0x10
22769 #define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT                                                           0x14
22770 #define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT                                                           0x18
22771 #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT                                                                0x1d
22772 #define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI_MASK                                                                 0x0000FFFFL
22773 #define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK                                                             0x00010000L
22774 #define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK                                                             0x00100000L
22775 #define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK                                                             0x03000000L
22776 #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK                                                                  0xE0000000L
22777 //CP_DMA_PFP_CONTROL
22778 #define CP_DMA_PFP_CONTROL__MEMLOG_CLEAR__SHIFT                                                               0xa
22779 #define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY__SHIFT                                                           0xd
22780 #define CP_DMA_PFP_CONTROL__DST_SELECT__SHIFT                                                                 0x14
22781 #define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY__SHIFT                                                           0x19
22782 #define CP_DMA_PFP_CONTROL__SRC_SELECT__SHIFT                                                                 0x1d
22783 #define CP_DMA_PFP_CONTROL__MEMLOG_CLEAR_MASK                                                                 0x00000400L
22784 #define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY_MASK                                                             0x00002000L
22785 #define CP_DMA_PFP_CONTROL__DST_SELECT_MASK                                                                   0x00300000L
22786 #define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY_MASK                                                             0x02000000L
22787 #define CP_DMA_PFP_CONTROL__SRC_SELECT_MASK                                                                   0x60000000L
22788 //CP_DMA_ME_CONTROL
22789 #define CP_DMA_ME_CONTROL__MEMLOG_CLEAR__SHIFT                                                                0xa
22790 #define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT                                                            0xd
22791 #define CP_DMA_ME_CONTROL__DST_SELECT__SHIFT                                                                  0x14
22792 #define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT                                                            0x19
22793 #define CP_DMA_ME_CONTROL__SRC_SELECT__SHIFT                                                                  0x1d
22794 #define CP_DMA_ME_CONTROL__MEMLOG_CLEAR_MASK                                                                  0x00000400L
22795 #define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK                                                              0x00002000L
22796 #define CP_DMA_ME_CONTROL__DST_SELECT_MASK                                                                    0x00300000L
22797 #define CP_DMA_ME_CONTROL__DST_CACHE_POLICY_MASK                                                              0x02000000L
22798 #define CP_DMA_ME_CONTROL__SRC_SELECT_MASK                                                                    0x60000000L
22799 //CP_COHER_BASE_HI
22800 #define CP_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT                                                           0x0
22801 #define CP_COHER_BASE_HI__COHER_BASE_HI_256B_MASK                                                             0x000000FFL
22802 //CP_COHER_START_DELAY
22803 #define CP_COHER_START_DELAY__START_DELAY_COUNT__SHIFT                                                        0x0
22804 #define CP_COHER_START_DELAY__START_DELAY_COUNT_MASK                                                          0x0000003FL
22805 //CP_COHER_CNTL
22806 #define CP_COHER_CNTL__TC_NC_ACTION_ENA__SHIFT                                                                0x3
22807 #define CP_COHER_CNTL__TC_WC_ACTION_ENA__SHIFT                                                                0x4
22808 #define CP_COHER_CNTL__TC_INV_METADATA_ACTION_ENA__SHIFT                                                      0x5
22809 #define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA__SHIFT                                                             0xf
22810 #define CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT                                                                0x12
22811 #define CP_COHER_CNTL__TCL1_ACTION_ENA__SHIFT                                                                 0x16
22812 #define CP_COHER_CNTL__TC_ACTION_ENA__SHIFT                                                                   0x17
22813 #define CP_COHER_CNTL__CB_ACTION_ENA__SHIFT                                                                   0x19
22814 #define CP_COHER_CNTL__DB_ACTION_ENA__SHIFT                                                                   0x1a
22815 #define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA__SHIFT                                                            0x1b
22816 #define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA__SHIFT                                                        0x1c
22817 #define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA__SHIFT                                                            0x1d
22818 #define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA__SHIFT                                                         0x1e
22819 #define CP_COHER_CNTL__TC_NC_ACTION_ENA_MASK                                                                  0x00000008L
22820 #define CP_COHER_CNTL__TC_WC_ACTION_ENA_MASK                                                                  0x00000010L
22821 #define CP_COHER_CNTL__TC_INV_METADATA_ACTION_ENA_MASK                                                        0x00000020L
22822 #define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA_MASK                                                               0x00008000L
22823 #define CP_COHER_CNTL__TC_WB_ACTION_ENA_MASK                                                                  0x00040000L
22824 #define CP_COHER_CNTL__TCL1_ACTION_ENA_MASK                                                                   0x00400000L
22825 #define CP_COHER_CNTL__TC_ACTION_ENA_MASK                                                                     0x00800000L
22826 #define CP_COHER_CNTL__CB_ACTION_ENA_MASK                                                                     0x02000000L
22827 #define CP_COHER_CNTL__DB_ACTION_ENA_MASK                                                                     0x04000000L
22828 #define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA_MASK                                                              0x08000000L
22829 #define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA_MASK                                                          0x10000000L
22830 #define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA_MASK                                                              0x20000000L
22831 #define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA_MASK                                                           0x40000000L
22832 //CP_COHER_SIZE
22833 #define CP_COHER_SIZE__COHER_SIZE_256B__SHIFT                                                                 0x0
22834 #define CP_COHER_SIZE__COHER_SIZE_256B_MASK                                                                   0xFFFFFFFFL
22835 //CP_COHER_BASE
22836 #define CP_COHER_BASE__COHER_BASE_256B__SHIFT                                                                 0x0
22837 #define CP_COHER_BASE__COHER_BASE_256B_MASK                                                                   0xFFFFFFFFL
22838 //CP_COHER_STATUS
22839 #define CP_COHER_STATUS__MEID__SHIFT                                                                          0x18
22840 #define CP_COHER_STATUS__STATUS__SHIFT                                                                        0x1f
22841 #define CP_COHER_STATUS__MEID_MASK                                                                            0x03000000L
22842 #define CP_COHER_STATUS__STATUS_MASK                                                                          0x80000000L
22843 //CP_DMA_ME_SRC_ADDR
22844 #define CP_DMA_ME_SRC_ADDR__SRC_ADDR__SHIFT                                                                   0x0
22845 #define CP_DMA_ME_SRC_ADDR__SRC_ADDR_MASK                                                                     0xFFFFFFFFL
22846 //CP_DMA_ME_SRC_ADDR_HI
22847 #define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT                                                             0x0
22848 #define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK                                                               0x0000FFFFL
22849 //CP_DMA_ME_DST_ADDR
22850 #define CP_DMA_ME_DST_ADDR__DST_ADDR__SHIFT                                                                   0x0
22851 #define CP_DMA_ME_DST_ADDR__DST_ADDR_MASK                                                                     0xFFFFFFFFL
22852 //CP_DMA_ME_DST_ADDR_HI
22853 #define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI__SHIFT                                                             0x0
22854 #define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK                                                               0x0000FFFFL
22855 //CP_DMA_ME_COMMAND
22856 #define CP_DMA_ME_COMMAND__BYTE_COUNT__SHIFT                                                                  0x0
22857 #define CP_DMA_ME_COMMAND__SAS__SHIFT                                                                         0x1a
22858 #define CP_DMA_ME_COMMAND__DAS__SHIFT                                                                         0x1b
22859 #define CP_DMA_ME_COMMAND__SAIC__SHIFT                                                                        0x1c
22860 #define CP_DMA_ME_COMMAND__DAIC__SHIFT                                                                        0x1d
22861 #define CP_DMA_ME_COMMAND__RAW_WAIT__SHIFT                                                                    0x1e
22862 #define CP_DMA_ME_COMMAND__DIS_WC__SHIFT                                                                      0x1f
22863 #define CP_DMA_ME_COMMAND__BYTE_COUNT_MASK                                                                    0x03FFFFFFL
22864 #define CP_DMA_ME_COMMAND__SAS_MASK                                                                           0x04000000L
22865 #define CP_DMA_ME_COMMAND__DAS_MASK                                                                           0x08000000L
22866 #define CP_DMA_ME_COMMAND__SAIC_MASK                                                                          0x10000000L
22867 #define CP_DMA_ME_COMMAND__DAIC_MASK                                                                          0x20000000L
22868 #define CP_DMA_ME_COMMAND__RAW_WAIT_MASK                                                                      0x40000000L
22869 #define CP_DMA_ME_COMMAND__DIS_WC_MASK                                                                        0x80000000L
22870 //CP_DMA_PFP_SRC_ADDR
22871 #define CP_DMA_PFP_SRC_ADDR__SRC_ADDR__SHIFT                                                                  0x0
22872 #define CP_DMA_PFP_SRC_ADDR__SRC_ADDR_MASK                                                                    0xFFFFFFFFL
22873 //CP_DMA_PFP_SRC_ADDR_HI
22874 #define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT                                                            0x0
22875 #define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK                                                              0x0000FFFFL
22876 //CP_DMA_PFP_DST_ADDR
22877 #define CP_DMA_PFP_DST_ADDR__DST_ADDR__SHIFT                                                                  0x0
22878 #define CP_DMA_PFP_DST_ADDR__DST_ADDR_MASK                                                                    0xFFFFFFFFL
22879 //CP_DMA_PFP_DST_ADDR_HI
22880 #define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI__SHIFT                                                            0x0
22881 #define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK                                                              0x0000FFFFL
22882 //CP_DMA_PFP_COMMAND
22883 #define CP_DMA_PFP_COMMAND__BYTE_COUNT__SHIFT                                                                 0x0
22884 #define CP_DMA_PFP_COMMAND__SAS__SHIFT                                                                        0x1a
22885 #define CP_DMA_PFP_COMMAND__DAS__SHIFT                                                                        0x1b
22886 #define CP_DMA_PFP_COMMAND__SAIC__SHIFT                                                                       0x1c
22887 #define CP_DMA_PFP_COMMAND__DAIC__SHIFT                                                                       0x1d
22888 #define CP_DMA_PFP_COMMAND__RAW_WAIT__SHIFT                                                                   0x1e
22889 #define CP_DMA_PFP_COMMAND__DIS_WC__SHIFT                                                                     0x1f
22890 #define CP_DMA_PFP_COMMAND__BYTE_COUNT_MASK                                                                   0x03FFFFFFL
22891 #define CP_DMA_PFP_COMMAND__SAS_MASK                                                                          0x04000000L
22892 #define CP_DMA_PFP_COMMAND__DAS_MASK                                                                          0x08000000L
22893 #define CP_DMA_PFP_COMMAND__SAIC_MASK                                                                         0x10000000L
22894 #define CP_DMA_PFP_COMMAND__DAIC_MASK                                                                         0x20000000L
22895 #define CP_DMA_PFP_COMMAND__RAW_WAIT_MASK                                                                     0x40000000L
22896 #define CP_DMA_PFP_COMMAND__DIS_WC_MASK                                                                       0x80000000L
22897 //CP_DMA_CNTL
22898 #define CP_DMA_CNTL__UTCL1_FAULT_CONTROL__SHIFT                                                               0x0
22899 #define CP_DMA_CNTL__MIN_AVAILSZ__SHIFT                                                                       0x4
22900 #define CP_DMA_CNTL__BUFFER_DEPTH__SHIFT                                                                      0x10
22901 #define CP_DMA_CNTL__PIO_FIFO_EMPTY__SHIFT                                                                    0x1c
22902 #define CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT                                                                     0x1d
22903 #define CP_DMA_CNTL__PIO_COUNT__SHIFT                                                                         0x1e
22904 #define CP_DMA_CNTL__UTCL1_FAULT_CONTROL_MASK                                                                 0x00000001L
22905 #define CP_DMA_CNTL__MIN_AVAILSZ_MASK                                                                         0x00000030L
22906 #define CP_DMA_CNTL__BUFFER_DEPTH_MASK                                                                        0x000F0000L
22907 #define CP_DMA_CNTL__PIO_FIFO_EMPTY_MASK                                                                      0x10000000L
22908 #define CP_DMA_CNTL__PIO_FIFO_FULL_MASK                                                                       0x20000000L
22909 #define CP_DMA_CNTL__PIO_COUNT_MASK                                                                           0xC0000000L
22910 //CP_DMA_READ_TAGS
22911 #define CP_DMA_READ_TAGS__DMA_READ_TAG__SHIFT                                                                 0x0
22912 #define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID__SHIFT                                                           0x1c
22913 #define CP_DMA_READ_TAGS__DMA_READ_TAG_MASK                                                                   0x03FFFFFFL
22914 #define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID_MASK                                                             0x10000000L
22915 //CP_COHER_SIZE_HI
22916 #define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT                                                           0x0
22917 #define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK                                                             0x000000FFL
22918 //CP_PFP_IB_CONTROL
22919 #define CP_PFP_IB_CONTROL__IB_EN__SHIFT                                                                       0x0
22920 #define CP_PFP_IB_CONTROL__IB_EN_MASK                                                                         0x000000FFL
22921 //CP_PFP_LOAD_CONTROL
22922 #define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN__SHIFT                                                             0x0
22923 #define CP_PFP_LOAD_CONTROL__CNTX_REG_EN__SHIFT                                                               0x1
22924 #define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT                                                             0x10
22925 #define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN__SHIFT                                                              0x18
22926 #define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN_MASK                                                               0x00000001L
22927 #define CP_PFP_LOAD_CONTROL__CNTX_REG_EN_MASK                                                                 0x00000002L
22928 #define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN_MASK                                                               0x00010000L
22929 #define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN_MASK                                                                0x01000000L
22930 //CP_SCRATCH_INDEX
22931 #define CP_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT                                                                0x0
22932 #define CP_SCRATCH_INDEX__SCRATCH_INDEX_MASK                                                                  0x000000FFL
22933 //CP_SCRATCH_DATA
22934 #define CP_SCRATCH_DATA__SCRATCH_DATA__SHIFT                                                                  0x0
22935 #define CP_SCRATCH_DATA__SCRATCH_DATA_MASK                                                                    0xFFFFFFFFL
22936 //CP_RB_OFFSET
22937 #define CP_RB_OFFSET__RB_OFFSET__SHIFT                                                                        0x0
22938 #define CP_RB_OFFSET__RB_OFFSET_MASK                                                                          0x000FFFFFL
22939 //CP_IB1_OFFSET
22940 #define CP_IB1_OFFSET__IB1_OFFSET__SHIFT                                                                      0x0
22941 #define CP_IB1_OFFSET__IB1_OFFSET_MASK                                                                        0x000FFFFFL
22942 //CP_IB2_OFFSET
22943 #define CP_IB2_OFFSET__IB2_OFFSET__SHIFT                                                                      0x0
22944 #define CP_IB2_OFFSET__IB2_OFFSET_MASK                                                                        0x000FFFFFL
22945 //CP_IB1_PREAMBLE_BEGIN
22946 #define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN__SHIFT                                                      0x0
22947 #define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN_MASK                                                        0x000FFFFFL
22948 //CP_IB1_PREAMBLE_END
22949 #define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END__SHIFT                                                          0x0
22950 #define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END_MASK                                                            0x000FFFFFL
22951 //CP_IB2_PREAMBLE_BEGIN
22952 #define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN__SHIFT                                                      0x0
22953 #define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN_MASK                                                        0x000FFFFFL
22954 //CP_IB2_PREAMBLE_END
22955 #define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END__SHIFT                                                          0x0
22956 #define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END_MASK                                                            0x000FFFFFL
22957 //CP_CE_IB1_OFFSET
22958 #define CP_CE_IB1_OFFSET__IB1_OFFSET__SHIFT                                                                   0x0
22959 #define CP_CE_IB1_OFFSET__IB1_OFFSET_MASK                                                                     0x000FFFFFL
22960 //CP_CE_IB2_OFFSET
22961 #define CP_CE_IB2_OFFSET__IB2_OFFSET__SHIFT                                                                   0x0
22962 #define CP_CE_IB2_OFFSET__IB2_OFFSET_MASK                                                                     0x000FFFFFL
22963 //CP_CE_COUNTER
22964 #define CP_CE_COUNTER__CONST_ENGINE_COUNT__SHIFT                                                              0x0
22965 #define CP_CE_COUNTER__CONST_ENGINE_COUNT_MASK                                                                0xFFFFFFFFL
22966 //CP_CE_RB_OFFSET
22967 #define CP_CE_RB_OFFSET__RB_OFFSET__SHIFT                                                                     0x0
22968 #define CP_CE_RB_OFFSET__RB_OFFSET_MASK                                                                       0x000FFFFFL
22969 //CP_CE_INIT_CMD_BUFSZ
22970 #define CP_CE_INIT_CMD_BUFSZ__INIT_CMD_REQSZ__SHIFT                                                           0x0
22971 #define CP_CE_INIT_CMD_BUFSZ__INIT_CMD_REQSZ_MASK                                                             0x00000FFFL
22972 //CP_CE_IB1_CMD_BUFSZ
22973 #define CP_CE_IB1_CMD_BUFSZ__IB1_CMD_REQSZ__SHIFT                                                             0x0
22974 #define CP_CE_IB1_CMD_BUFSZ__IB1_CMD_REQSZ_MASK                                                               0x000FFFFFL
22975 //CP_CE_IB2_CMD_BUFSZ
22976 #define CP_CE_IB2_CMD_BUFSZ__IB2_CMD_REQSZ__SHIFT                                                             0x0
22977 #define CP_CE_IB2_CMD_BUFSZ__IB2_CMD_REQSZ_MASK                                                               0x000FFFFFL
22978 //CP_IB1_CMD_BUFSZ
22979 #define CP_IB1_CMD_BUFSZ__IB1_CMD_REQSZ__SHIFT                                                                0x0
22980 #define CP_IB1_CMD_BUFSZ__IB1_CMD_REQSZ_MASK                                                                  0x000FFFFFL
22981 //CP_IB2_CMD_BUFSZ
22982 #define CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ__SHIFT                                                                0x0
22983 #define CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ_MASK                                                                  0x000FFFFFL
22984 //CP_ST_CMD_BUFSZ
22985 #define CP_ST_CMD_BUFSZ__ST_CMD_REQSZ__SHIFT                                                                  0x0
22986 #define CP_ST_CMD_BUFSZ__ST_CMD_REQSZ_MASK                                                                    0x000FFFFFL
22987 //CP_CE_INIT_BASE_LO
22988 #define CP_CE_INIT_BASE_LO__INIT_BASE_LO__SHIFT                                                               0x5
22989 #define CP_CE_INIT_BASE_LO__INIT_BASE_LO_MASK                                                                 0xFFFFFFE0L
22990 //CP_CE_INIT_BASE_HI
22991 #define CP_CE_INIT_BASE_HI__INIT_BASE_HI__SHIFT                                                               0x0
22992 #define CP_CE_INIT_BASE_HI__INIT_BASE_HI_MASK                                                                 0x0000FFFFL
22993 //CP_CE_INIT_BUFSZ
22994 #define CP_CE_INIT_BUFSZ__INIT_BUFSZ__SHIFT                                                                   0x0
22995 #define CP_CE_INIT_BUFSZ__INIT_BUFSZ_MASK                                                                     0x00000FFFL
22996 //CP_CE_IB1_BASE_LO
22997 #define CP_CE_IB1_BASE_LO__IB1_BASE_LO__SHIFT                                                                 0x2
22998 #define CP_CE_IB1_BASE_LO__IB1_BASE_LO_MASK                                                                   0xFFFFFFFCL
22999 //CP_CE_IB1_BASE_HI
23000 #define CP_CE_IB1_BASE_HI__IB1_BASE_HI__SHIFT                                                                 0x0
23001 #define CP_CE_IB1_BASE_HI__IB1_BASE_HI_MASK                                                                   0x0000FFFFL
23002 //CP_CE_IB1_BUFSZ
23003 #define CP_CE_IB1_BUFSZ__IB1_BUFSZ__SHIFT                                                                     0x0
23004 #define CP_CE_IB1_BUFSZ__IB1_BUFSZ_MASK                                                                       0x000FFFFFL
23005 //CP_CE_IB2_BASE_LO
23006 #define CP_CE_IB2_BASE_LO__IB2_BASE_LO__SHIFT                                                                 0x2
23007 #define CP_CE_IB2_BASE_LO__IB2_BASE_LO_MASK                                                                   0xFFFFFFFCL
23008 //CP_CE_IB2_BASE_HI
23009 #define CP_CE_IB2_BASE_HI__IB2_BASE_HI__SHIFT                                                                 0x0
23010 #define CP_CE_IB2_BASE_HI__IB2_BASE_HI_MASK                                                                   0x0000FFFFL
23011 //CP_CE_IB2_BUFSZ
23012 #define CP_CE_IB2_BUFSZ__IB2_BUFSZ__SHIFT                                                                     0x0
23013 #define CP_CE_IB2_BUFSZ__IB2_BUFSZ_MASK                                                                       0x000FFFFFL
23014 //CP_IB1_BASE_LO
23015 #define CP_IB1_BASE_LO__IB1_BASE_LO__SHIFT                                                                    0x2
23016 #define CP_IB1_BASE_LO__IB1_BASE_LO_MASK                                                                      0xFFFFFFFCL
23017 //CP_IB1_BASE_HI
23018 #define CP_IB1_BASE_HI__IB1_BASE_HI__SHIFT                                                                    0x0
23019 #define CP_IB1_BASE_HI__IB1_BASE_HI_MASK                                                                      0x0000FFFFL
23020 //CP_IB1_BUFSZ
23021 #define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT                                                                        0x0
23022 #define CP_IB1_BUFSZ__IB1_BUFSZ_MASK                                                                          0x000FFFFFL
23023 //CP_IB2_BASE_LO
23024 #define CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT                                                                    0x2
23025 #define CP_IB2_BASE_LO__IB2_BASE_LO_MASK                                                                      0xFFFFFFFCL
23026 //CP_IB2_BASE_HI
23027 #define CP_IB2_BASE_HI__IB2_BASE_HI__SHIFT                                                                    0x0
23028 #define CP_IB2_BASE_HI__IB2_BASE_HI_MASK                                                                      0x0000FFFFL
23029 //CP_IB2_BUFSZ
23030 #define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT                                                                        0x0
23031 #define CP_IB2_BUFSZ__IB2_BUFSZ_MASK                                                                          0x000FFFFFL
23032 //CP_ST_BASE_LO
23033 #define CP_ST_BASE_LO__ST_BASE_LO__SHIFT                                                                      0x2
23034 #define CP_ST_BASE_LO__ST_BASE_LO_MASK                                                                        0xFFFFFFFCL
23035 //CP_ST_BASE_HI
23036 #define CP_ST_BASE_HI__ST_BASE_HI__SHIFT                                                                      0x0
23037 #define CP_ST_BASE_HI__ST_BASE_HI_MASK                                                                        0x0000FFFFL
23038 //CP_ST_BUFSZ
23039 #define CP_ST_BUFSZ__ST_BUFSZ__SHIFT                                                                          0x0
23040 #define CP_ST_BUFSZ__ST_BUFSZ_MASK                                                                            0x000FFFFFL
23041 //CP_EOP_DONE_EVENT_CNTL
23042 #define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP__SHIFT                                                            0x0
23043 #define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA__SHIFT                                                       0xc
23044 #define CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY__SHIFT                                                           0x19
23045 #define CP_EOP_DONE_EVENT_CNTL__EXECUTE__SHIFT                                                                0x1c
23046 #define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP_MASK                                                              0x0000007FL
23047 #define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA_MASK                                                         0x0003F000L
23048 #define CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY_MASK                                                             0x02000000L
23049 #define CP_EOP_DONE_EVENT_CNTL__EXECUTE_MASK                                                                  0x10000000L
23050 //CP_EOP_DONE_DATA_CNTL
23051 #define CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT                                                                 0x10
23052 #define CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT                                                                 0x18
23053 #define CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT                                                                0x1d
23054 #define CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK                                                                   0x00030000L
23055 #define CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK                                                                   0x07000000L
23056 #define CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK                                                                  0xE0000000L
23057 //CP_EOP_DONE_CNTX_ID
23058 #define CP_EOP_DONE_CNTX_ID__CNTX_ID__SHIFT                                                                   0x0
23059 #define CP_EOP_DONE_CNTX_ID__CNTX_ID_MASK                                                                     0xFFFFFFFFL
23060 //CP_PFP_COMPLETION_STATUS
23061 #define CP_PFP_COMPLETION_STATUS__STATUS__SHIFT                                                               0x0
23062 #define CP_PFP_COMPLETION_STATUS__STATUS_MASK                                                                 0x00000003L
23063 //CP_CE_COMPLETION_STATUS
23064 #define CP_CE_COMPLETION_STATUS__STATUS__SHIFT                                                                0x0
23065 #define CP_CE_COMPLETION_STATUS__STATUS_MASK                                                                  0x00000003L
23066 //CP_PRED_NOT_VISIBLE
23067 #define CP_PRED_NOT_VISIBLE__NOT_VISIBLE__SHIFT                                                               0x0
23068 #define CP_PRED_NOT_VISIBLE__NOT_VISIBLE_MASK                                                                 0x00000001L
23069 //CP_PFP_METADATA_BASE_ADDR
23070 #define CP_PFP_METADATA_BASE_ADDR__ADDR_LO__SHIFT                                                             0x0
23071 #define CP_PFP_METADATA_BASE_ADDR__ADDR_LO_MASK                                                               0xFFFFFFFFL
23072 //CP_PFP_METADATA_BASE_ADDR_HI
23073 #define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT                                                          0x0
23074 #define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI_MASK                                                            0x0000FFFFL
23075 //CP_CE_METADATA_BASE_ADDR
23076 #define CP_CE_METADATA_BASE_ADDR__ADDR_LO__SHIFT                                                              0x0
23077 #define CP_CE_METADATA_BASE_ADDR__ADDR_LO_MASK                                                                0xFFFFFFFFL
23078 //CP_CE_METADATA_BASE_ADDR_HI
23079 #define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT                                                           0x0
23080 #define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI_MASK                                                             0x0000FFFFL
23081 //CP_DRAW_INDX_INDR_ADDR
23082 #define CP_DRAW_INDX_INDR_ADDR__ADDR_LO__SHIFT                                                                0x0
23083 #define CP_DRAW_INDX_INDR_ADDR__ADDR_LO_MASK                                                                  0xFFFFFFFFL
23084 //CP_DRAW_INDX_INDR_ADDR_HI
23085 #define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI__SHIFT                                                             0x0
23086 #define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI_MASK                                                               0x0000FFFFL
23087 //CP_DISPATCH_INDR_ADDR
23088 #define CP_DISPATCH_INDR_ADDR__ADDR_LO__SHIFT                                                                 0x0
23089 #define CP_DISPATCH_INDR_ADDR__ADDR_LO_MASK                                                                   0xFFFFFFFFL
23090 //CP_DISPATCH_INDR_ADDR_HI
23091 #define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI__SHIFT                                                              0x0
23092 #define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI_MASK                                                                0x0000FFFFL
23093 //CP_INDEX_BASE_ADDR
23094 #define CP_INDEX_BASE_ADDR__ADDR_LO__SHIFT                                                                    0x0
23095 #define CP_INDEX_BASE_ADDR__ADDR_LO_MASK                                                                      0xFFFFFFFFL
23096 //CP_INDEX_BASE_ADDR_HI
23097 #define CP_INDEX_BASE_ADDR_HI__ADDR_HI__SHIFT                                                                 0x0
23098 #define CP_INDEX_BASE_ADDR_HI__ADDR_HI_MASK                                                                   0x0000FFFFL
23099 //CP_INDEX_TYPE
23100 #define CP_INDEX_TYPE__INDEX_TYPE__SHIFT                                                                      0x0
23101 #define CP_INDEX_TYPE__INDEX_TYPE_MASK                                                                        0x00000003L
23102 //CP_GDS_BKUP_ADDR
23103 #define CP_GDS_BKUP_ADDR__ADDR_LO__SHIFT                                                                      0x0
23104 #define CP_GDS_BKUP_ADDR__ADDR_LO_MASK                                                                        0xFFFFFFFFL
23105 //CP_GDS_BKUP_ADDR_HI
23106 #define CP_GDS_BKUP_ADDR_HI__ADDR_HI__SHIFT                                                                   0x0
23107 #define CP_GDS_BKUP_ADDR_HI__ADDR_HI_MASK                                                                     0x0000FFFFL
23108 //CP_SAMPLE_STATUS
23109 #define CP_SAMPLE_STATUS__Z_PASS_ACITVE__SHIFT                                                                0x0
23110 #define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE__SHIFT                                                             0x1
23111 #define CP_SAMPLE_STATUS__PIPELINE_ACTIVE__SHIFT                                                              0x2
23112 #define CP_SAMPLE_STATUS__STIPPLE_ACTIVE__SHIFT                                                               0x3
23113 #define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE__SHIFT                                                           0x4
23114 #define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE__SHIFT                                                            0x5
23115 #define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE__SHIFT                                                         0x6
23116 #define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE__SHIFT                                                         0x7
23117 #define CP_SAMPLE_STATUS__Z_PASS_ACITVE_MASK                                                                  0x00000001L
23118 #define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE_MASK                                                               0x00000002L
23119 #define CP_SAMPLE_STATUS__PIPELINE_ACTIVE_MASK                                                                0x00000004L
23120 #define CP_SAMPLE_STATUS__STIPPLE_ACTIVE_MASK                                                                 0x00000008L
23121 #define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE_MASK                                                             0x00000010L
23122 #define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE_MASK                                                              0x00000020L
23123 #define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE_MASK                                                           0x00000040L
23124 #define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE_MASK                                                           0x00000080L
23125 //CP_ME_COHER_CNTL
23126 #define CP_ME_COHER_CNTL__DEST_BASE_0_ENA__SHIFT                                                              0x0
23127 #define CP_ME_COHER_CNTL__DEST_BASE_1_ENA__SHIFT                                                              0x1
23128 #define CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA__SHIFT                                                            0x6
23129 #define CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA__SHIFT                                                            0x7
23130 #define CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA__SHIFT                                                            0x8
23131 #define CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA__SHIFT                                                            0x9
23132 #define CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT                                                            0xa
23133 #define CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA__SHIFT                                                            0xb
23134 #define CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA__SHIFT                                                            0xc
23135 #define CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA__SHIFT                                                            0xd
23136 #define CP_ME_COHER_CNTL__DB_DEST_BASE_ENA__SHIFT                                                             0xe
23137 #define CP_ME_COHER_CNTL__DEST_BASE_2_ENA__SHIFT                                                              0x13
23138 #define CP_ME_COHER_CNTL__DEST_BASE_3_ENA__SHIFT                                                              0x15
23139 #define CP_ME_COHER_CNTL__DEST_BASE_0_ENA_MASK                                                                0x00000001L
23140 #define CP_ME_COHER_CNTL__DEST_BASE_1_ENA_MASK                                                                0x00000002L
23141 #define CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA_MASK                                                              0x00000040L
23142 #define CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA_MASK                                                              0x00000080L
23143 #define CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA_MASK                                                              0x00000100L
23144 #define CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA_MASK                                                              0x00000200L
23145 #define CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA_MASK                                                              0x00000400L
23146 #define CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA_MASK                                                              0x00000800L
23147 #define CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA_MASK                                                              0x00001000L
23148 #define CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA_MASK                                                              0x00002000L
23149 #define CP_ME_COHER_CNTL__DB_DEST_BASE_ENA_MASK                                                               0x00004000L
23150 #define CP_ME_COHER_CNTL__DEST_BASE_2_ENA_MASK                                                                0x00080000L
23151 #define CP_ME_COHER_CNTL__DEST_BASE_3_ENA_MASK                                                                0x00200000L
23152 //CP_ME_COHER_SIZE
23153 #define CP_ME_COHER_SIZE__COHER_SIZE_256B__SHIFT                                                              0x0
23154 #define CP_ME_COHER_SIZE__COHER_SIZE_256B_MASK                                                                0xFFFFFFFFL
23155 //CP_ME_COHER_SIZE_HI
23156 #define CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT                                                        0x0
23157 #define CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK                                                          0x000000FFL
23158 //CP_ME_COHER_BASE
23159 #define CP_ME_COHER_BASE__COHER_BASE_256B__SHIFT                                                              0x0
23160 #define CP_ME_COHER_BASE__COHER_BASE_256B_MASK                                                                0xFFFFFFFFL
23161 //CP_ME_COHER_BASE_HI
23162 #define CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT                                                        0x0
23163 #define CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B_MASK                                                          0x000000FFL
23164 //CP_ME_COHER_STATUS
23165 #define CP_ME_COHER_STATUS__MATCHING_GFX_CNTX__SHIFT                                                          0x0
23166 #define CP_ME_COHER_STATUS__STATUS__SHIFT                                                                     0x1f
23167 #define CP_ME_COHER_STATUS__MATCHING_GFX_CNTX_MASK                                                            0x000000FFL
23168 #define CP_ME_COHER_STATUS__STATUS_MASK                                                                       0x80000000L
23169 //RLC_GPM_PERF_COUNT_0
23170 #define RLC_GPM_PERF_COUNT_0__FEATURE_SEL__SHIFT                                                              0x0
23171 #define RLC_GPM_PERF_COUNT_0__SE_INDEX__SHIFT                                                                 0x4
23172 #define RLC_GPM_PERF_COUNT_0__SH_INDEX__SHIFT                                                                 0x8
23173 #define RLC_GPM_PERF_COUNT_0__CU_INDEX__SHIFT                                                                 0xc
23174 #define RLC_GPM_PERF_COUNT_0__EVENT_SEL__SHIFT                                                                0x10
23175 #define RLC_GPM_PERF_COUNT_0__UNUSED__SHIFT                                                                   0x12
23176 #define RLC_GPM_PERF_COUNT_0__ENABLE__SHIFT                                                                   0x14
23177 #define RLC_GPM_PERF_COUNT_0__RESERVED__SHIFT                                                                 0x15
23178 #define RLC_GPM_PERF_COUNT_0__FEATURE_SEL_MASK                                                                0x0000000FL
23179 #define RLC_GPM_PERF_COUNT_0__SE_INDEX_MASK                                                                   0x000000F0L
23180 #define RLC_GPM_PERF_COUNT_0__SH_INDEX_MASK                                                                   0x00000F00L
23181 #define RLC_GPM_PERF_COUNT_0__CU_INDEX_MASK                                                                   0x0000F000L
23182 #define RLC_GPM_PERF_COUNT_0__EVENT_SEL_MASK                                                                  0x00030000L
23183 #define RLC_GPM_PERF_COUNT_0__UNUSED_MASK                                                                     0x000C0000L
23184 #define RLC_GPM_PERF_COUNT_0__ENABLE_MASK                                                                     0x00100000L
23185 #define RLC_GPM_PERF_COUNT_0__RESERVED_MASK                                                                   0xFFE00000L
23186 //RLC_GPM_PERF_COUNT_1
23187 #define RLC_GPM_PERF_COUNT_1__FEATURE_SEL__SHIFT                                                              0x0
23188 #define RLC_GPM_PERF_COUNT_1__SE_INDEX__SHIFT                                                                 0x4
23189 #define RLC_GPM_PERF_COUNT_1__SH_INDEX__SHIFT                                                                 0x8
23190 #define RLC_GPM_PERF_COUNT_1__CU_INDEX__SHIFT                                                                 0xc
23191 #define RLC_GPM_PERF_COUNT_1__EVENT_SEL__SHIFT                                                                0x10
23192 #define RLC_GPM_PERF_COUNT_1__UNUSED__SHIFT                                                                   0x12
23193 #define RLC_GPM_PERF_COUNT_1__ENABLE__SHIFT                                                                   0x14
23194 #define RLC_GPM_PERF_COUNT_1__RESERVED__SHIFT                                                                 0x15
23195 #define RLC_GPM_PERF_COUNT_1__FEATURE_SEL_MASK                                                                0x0000000FL
23196 #define RLC_GPM_PERF_COUNT_1__SE_INDEX_MASK                                                                   0x000000F0L
23197 #define RLC_GPM_PERF_COUNT_1__SH_INDEX_MASK                                                                   0x00000F00L
23198 #define RLC_GPM_PERF_COUNT_1__CU_INDEX_MASK                                                                   0x0000F000L
23199 #define RLC_GPM_PERF_COUNT_1__EVENT_SEL_MASK                                                                  0x00030000L
23200 #define RLC_GPM_PERF_COUNT_1__UNUSED_MASK                                                                     0x000C0000L
23201 #define RLC_GPM_PERF_COUNT_1__ENABLE_MASK                                                                     0x00100000L
23202 #define RLC_GPM_PERF_COUNT_1__RESERVED_MASK                                                                   0xFFE00000L
23203 //GRBM_GFX_INDEX
23204 #define GRBM_GFX_INDEX__INSTANCE_INDEX__SHIFT                                                                 0x0
23205 #define GRBM_GFX_INDEX__SH_INDEX__SHIFT                                                                       0x8
23206 #define GRBM_GFX_INDEX__SE_INDEX__SHIFT                                                                       0x10
23207 #define GRBM_GFX_INDEX__SH_BROADCAST_WRITES__SHIFT                                                            0x1d
23208 #define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT                                                      0x1e
23209 #define GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT                                                            0x1f
23210 #define GRBM_GFX_INDEX__INSTANCE_INDEX_MASK                                                                   0x000000FFL
23211 #define GRBM_GFX_INDEX__SH_INDEX_MASK                                                                         0x0000FF00L
23212 #define GRBM_GFX_INDEX__SE_INDEX_MASK                                                                         0x00FF0000L
23213 #define GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK                                                              0x20000000L
23214 #define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK                                                        0x40000000L
23215 #define GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK                                                              0x80000000L
23216 //VGT_GSVS_RING_SIZE
23217 #define VGT_GSVS_RING_SIZE__MEM_SIZE__SHIFT                                                                   0x0
23218 #define VGT_GSVS_RING_SIZE__MEM_SIZE_MASK                                                                     0xFFFFFFFFL
23219 //VGT_PRIMITIVE_TYPE
23220 #define VGT_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT                                                                  0x0
23221 #define VGT_PRIMITIVE_TYPE__PRIM_TYPE_MASK                                                                    0x0000003FL
23222 //VGT_INDEX_TYPE
23223 #define VGT_INDEX_TYPE__INDEX_TYPE__SHIFT                                                                     0x0
23224 #define VGT_INDEX_TYPE__PRIMGEN_EN__SHIFT                                                                     0x8
23225 #define VGT_INDEX_TYPE__INDEX_TYPE_MASK                                                                       0x00000003L
23226 #define VGT_INDEX_TYPE__PRIMGEN_EN_MASK                                                                       0x00000100L
23227 //VGT_STRMOUT_BUFFER_FILLED_SIZE_0
23228 #define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE__SHIFT                                                         0x0
23229 #define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE_MASK                                                           0xFFFFFFFFL
23230 //VGT_STRMOUT_BUFFER_FILLED_SIZE_1
23231 #define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE__SHIFT                                                         0x0
23232 #define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE_MASK                                                           0xFFFFFFFFL
23233 //VGT_STRMOUT_BUFFER_FILLED_SIZE_2
23234 #define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE__SHIFT                                                         0x0
23235 #define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE_MASK                                                           0xFFFFFFFFL
23236 //VGT_STRMOUT_BUFFER_FILLED_SIZE_3
23237 #define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE__SHIFT                                                         0x0
23238 #define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE_MASK                                                           0xFFFFFFFFL
23239 //VGT_MAX_VTX_INDX
23240 #define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT                                                                     0x0
23241 #define VGT_MAX_VTX_INDX__MAX_INDX_MASK                                                                       0xFFFFFFFFL
23242 //VGT_MIN_VTX_INDX
23243 #define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT                                                                     0x0
23244 #define VGT_MIN_VTX_INDX__MIN_INDX_MASK                                                                       0xFFFFFFFFL
23245 //VGT_INDX_OFFSET
23246 #define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT                                                                   0x0
23247 #define VGT_INDX_OFFSET__INDX_OFFSET_MASK                                                                     0xFFFFFFFFL
23248 //VGT_MULTI_PRIM_IB_RESET_EN
23249 #define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN__SHIFT                                                           0x0
23250 #define VGT_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS__SHIFT                                                     0x1
23251 #define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN_MASK                                                             0x00000001L
23252 #define VGT_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS_MASK                                                       0x00000002L
23253 //VGT_NUM_INDICES
23254 #define VGT_NUM_INDICES__NUM_INDICES__SHIFT                                                                   0x0
23255 #define VGT_NUM_INDICES__NUM_INDICES_MASK                                                                     0xFFFFFFFFL
23256 //VGT_NUM_INSTANCES
23257 #define VGT_NUM_INSTANCES__NUM_INSTANCES__SHIFT                                                               0x0
23258 #define VGT_NUM_INSTANCES__NUM_INSTANCES_MASK                                                                 0xFFFFFFFFL
23259 //VGT_TF_RING_SIZE
23260 #define VGT_TF_RING_SIZE__SIZE__SHIFT                                                                         0x0
23261 #define VGT_TF_RING_SIZE__SIZE_MASK                                                                           0x0000FFFFL
23262 //VGT_HS_OFFCHIP_PARAM
23263 #define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING__SHIFT                                                        0x0
23264 #define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY__SHIFT                                                      0x9
23265 #define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING_MASK                                                          0x000001FFL
23266 #define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY_MASK                                                        0x00000600L
23267 //VGT_TF_MEMORY_BASE
23268 #define VGT_TF_MEMORY_BASE__BASE__SHIFT                                                                       0x0
23269 #define VGT_TF_MEMORY_BASE__BASE_MASK                                                                         0xFFFFFFFFL
23270 //VGT_TF_MEMORY_BASE_HI
23271 #define VGT_TF_MEMORY_BASE_HI__BASE_HI__SHIFT                                                                 0x0
23272 #define VGT_TF_MEMORY_BASE_HI__BASE_HI_MASK                                                                   0x000000FFL
23273 //WD_POS_BUF_BASE
23274 #define WD_POS_BUF_BASE__BASE__SHIFT                                                                          0x0
23275 #define WD_POS_BUF_BASE__BASE_MASK                                                                            0xFFFFFFFFL
23276 //WD_POS_BUF_BASE_HI
23277 #define WD_POS_BUF_BASE_HI__BASE_HI__SHIFT                                                                    0x0
23278 #define WD_POS_BUF_BASE_HI__BASE_HI_MASK                                                                      0x000000FFL
23279 //WD_CNTL_SB_BUF_BASE
23280 #define WD_CNTL_SB_BUF_BASE__BASE__SHIFT                                                                      0x0
23281 #define WD_CNTL_SB_BUF_BASE__BASE_MASK                                                                        0xFFFFFFFFL
23282 //WD_CNTL_SB_BUF_BASE_HI
23283 #define WD_CNTL_SB_BUF_BASE_HI__BASE_HI__SHIFT                                                                0x0
23284 #define WD_CNTL_SB_BUF_BASE_HI__BASE_HI_MASK                                                                  0x000000FFL
23285 //WD_INDEX_BUF_BASE
23286 #define WD_INDEX_BUF_BASE__BASE__SHIFT                                                                        0x0
23287 #define WD_INDEX_BUF_BASE__BASE_MASK                                                                          0xFFFFFFFFL
23288 //WD_INDEX_BUF_BASE_HI
23289 #define WD_INDEX_BUF_BASE_HI__BASE_HI__SHIFT                                                                  0x0
23290 #define WD_INDEX_BUF_BASE_HI__BASE_HI_MASK                                                                    0x000000FFL
23291 //IA_MULTI_VGT_PARAM
23292 #define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE__SHIFT                                                             0x0
23293 #define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON__SHIFT                                                         0x10
23294 #define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP__SHIFT                                                              0x11
23295 #define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON__SHIFT                                                         0x12
23296 #define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI__SHIFT                                                              0x13
23297 #define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP__SHIFT                                                           0x14
23298 #define IA_MULTI_VGT_PARAM__EN_INST_OPT_BASIC__SHIFT                                                          0x15
23299 #define IA_MULTI_VGT_PARAM__EN_INST_OPT_ADV__SHIFT                                                            0x16
23300 #define IA_MULTI_VGT_PARAM__HW_USE_ONLY__SHIFT                                                                0x17
23301 #define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE_MASK                                                               0x0000FFFFL
23302 #define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON_MASK                                                           0x00010000L
23303 #define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP_MASK                                                                0x00020000L
23304 #define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON_MASK                                                           0x00040000L
23305 #define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI_MASK                                                                0x00080000L
23306 #define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP_MASK                                                             0x00100000L
23307 #define IA_MULTI_VGT_PARAM__EN_INST_OPT_BASIC_MASK                                                            0x00200000L
23308 #define IA_MULTI_VGT_PARAM__EN_INST_OPT_ADV_MASK                                                              0x00400000L
23309 #define IA_MULTI_VGT_PARAM__HW_USE_ONLY_MASK                                                                  0x00800000L
23310 //VGT_INSTANCE_BASE_ID
23311 #define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID__SHIFT                                                         0x0
23312 #define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID_MASK                                                           0xFFFFFFFFL
23313 //PA_SU_LINE_STIPPLE_VALUE
23314 #define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE__SHIFT                                                   0x0
23315 #define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE_MASK                                                     0x00FFFFFFL
23316 //PA_SC_LINE_STIPPLE_STATE
23317 #define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT                                                          0x0
23318 #define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT                                                        0x8
23319 #define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK                                                            0x0000000FL
23320 #define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK                                                          0x0000FF00L
23321 //PA_SC_SCREEN_EXTENT_MIN_0
23322 #define PA_SC_SCREEN_EXTENT_MIN_0__X__SHIFT                                                                   0x0
23323 #define PA_SC_SCREEN_EXTENT_MIN_0__Y__SHIFT                                                                   0x10
23324 #define PA_SC_SCREEN_EXTENT_MIN_0__X_MASK                                                                     0x0000FFFFL
23325 #define PA_SC_SCREEN_EXTENT_MIN_0__Y_MASK                                                                     0xFFFF0000L
23326 //PA_SC_SCREEN_EXTENT_MAX_0
23327 #define PA_SC_SCREEN_EXTENT_MAX_0__X__SHIFT                                                                   0x0
23328 #define PA_SC_SCREEN_EXTENT_MAX_0__Y__SHIFT                                                                   0x10
23329 #define PA_SC_SCREEN_EXTENT_MAX_0__X_MASK                                                                     0x0000FFFFL
23330 #define PA_SC_SCREEN_EXTENT_MAX_0__Y_MASK                                                                     0xFFFF0000L
23331 //PA_SC_SCREEN_EXTENT_MIN_1
23332 #define PA_SC_SCREEN_EXTENT_MIN_1__X__SHIFT                                                                   0x0
23333 #define PA_SC_SCREEN_EXTENT_MIN_1__Y__SHIFT                                                                   0x10
23334 #define PA_SC_SCREEN_EXTENT_MIN_1__X_MASK                                                                     0x0000FFFFL
23335 #define PA_SC_SCREEN_EXTENT_MIN_1__Y_MASK                                                                     0xFFFF0000L
23336 //PA_SC_SCREEN_EXTENT_MAX_1
23337 #define PA_SC_SCREEN_EXTENT_MAX_1__X__SHIFT                                                                   0x0
23338 #define PA_SC_SCREEN_EXTENT_MAX_1__Y__SHIFT                                                                   0x10
23339 #define PA_SC_SCREEN_EXTENT_MAX_1__X_MASK                                                                     0x0000FFFFL
23340 #define PA_SC_SCREEN_EXTENT_MAX_1__Y_MASK                                                                     0xFFFF0000L
23341 //PA_SC_P3D_TRAP_SCREEN_HV_EN
23342 #define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT                                              0x0
23343 #define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT                                       0x1
23344 #define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK                                                0x00000001L
23345 #define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK                                         0x00000002L
23346 //PA_SC_P3D_TRAP_SCREEN_H
23347 #define PA_SC_P3D_TRAP_SCREEN_H__X_COORD__SHIFT                                                               0x0
23348 #define PA_SC_P3D_TRAP_SCREEN_H__X_COORD_MASK                                                                 0x00003FFFL
23349 //PA_SC_P3D_TRAP_SCREEN_V
23350 #define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD__SHIFT                                                               0x0
23351 #define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD_MASK                                                                 0x00003FFFL
23352 //PA_SC_P3D_TRAP_SCREEN_OCCURRENCE
23353 #define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT                                                        0x0
23354 #define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK                                                          0x0000FFFFL
23355 //PA_SC_P3D_TRAP_SCREEN_COUNT
23356 #define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT__SHIFT                                                             0x0
23357 #define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT_MASK                                                               0x0000FFFFL
23358 //PA_SC_HP3D_TRAP_SCREEN_HV_EN
23359 #define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT                                             0x0
23360 #define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT                                      0x1
23361 #define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK                                               0x00000001L
23362 #define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK                                        0x00000002L
23363 //PA_SC_HP3D_TRAP_SCREEN_H
23364 #define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD__SHIFT                                                              0x0
23365 #define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD_MASK                                                                0x00003FFFL
23366 //PA_SC_HP3D_TRAP_SCREEN_V
23367 #define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD__SHIFT                                                              0x0
23368 #define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD_MASK                                                                0x00003FFFL
23369 //PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE
23370 #define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT                                                       0x0
23371 #define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK                                                         0x0000FFFFL
23372 //PA_SC_HP3D_TRAP_SCREEN_COUNT
23373 #define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT__SHIFT                                                            0x0
23374 #define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT_MASK                                                              0x0000FFFFL
23375 //PA_SC_TRAP_SCREEN_HV_EN
23376 #define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT                                                  0x0
23377 #define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT                                           0x1
23378 #define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK                                                    0x00000001L
23379 #define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK                                             0x00000002L
23380 //PA_SC_TRAP_SCREEN_H
23381 #define PA_SC_TRAP_SCREEN_H__X_COORD__SHIFT                                                                   0x0
23382 #define PA_SC_TRAP_SCREEN_H__X_COORD_MASK                                                                     0x00003FFFL
23383 //PA_SC_TRAP_SCREEN_V
23384 #define PA_SC_TRAP_SCREEN_V__Y_COORD__SHIFT                                                                   0x0
23385 #define PA_SC_TRAP_SCREEN_V__Y_COORD_MASK                                                                     0x00003FFFL
23386 //PA_SC_TRAP_SCREEN_OCCURRENCE
23387 #define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT                                                            0x0
23388 #define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT_MASK                                                              0x0000FFFFL
23389 //PA_SC_TRAP_SCREEN_COUNT
23390 #define PA_SC_TRAP_SCREEN_COUNT__COUNT__SHIFT                                                                 0x0
23391 #define PA_SC_TRAP_SCREEN_COUNT__COUNT_MASK                                                                   0x0000FFFFL
23392 //PA_STATE_STEREO_X
23393 #define PA_STATE_STEREO_X__STEREO_X_OFFSET__SHIFT                                                             0x0
23394 #define PA_STATE_STEREO_X__STEREO_X_OFFSET_MASK                                                               0xFFFFFFFFL
23395 //SQ_THREAD_TRACE_BASE
23396 #define SQ_THREAD_TRACE_BASE__ADDR__SHIFT                                                                     0x0
23397 #define SQ_THREAD_TRACE_BASE__ADDR_MASK                                                                       0xFFFFFFFFL
23398 //SQ_THREAD_TRACE_SIZE
23399 #define SQ_THREAD_TRACE_SIZE__SIZE__SHIFT                                                                     0x0
23400 #define SQ_THREAD_TRACE_SIZE__SIZE_MASK                                                                       0x003FFFFFL
23401 //SQ_THREAD_TRACE_MASK
23402 #define SQ_THREAD_TRACE_MASK__CU_SEL__SHIFT                                                                   0x0
23403 #define SQ_THREAD_TRACE_MASK__SH_SEL__SHIFT                                                                   0x5
23404 #define SQ_THREAD_TRACE_MASK__REG_STALL_EN__SHIFT                                                             0x7
23405 #define SQ_THREAD_TRACE_MASK__SIMD_EN__SHIFT                                                                  0x8
23406 #define SQ_THREAD_TRACE_MASK__VM_ID_MASK__SHIFT                                                               0xc
23407 #define SQ_THREAD_TRACE_MASK__SPI_STALL_EN__SHIFT                                                             0xe
23408 #define SQ_THREAD_TRACE_MASK__SQ_STALL_EN__SHIFT                                                              0xf
23409 #define SQ_THREAD_TRACE_MASK__CU_SEL_MASK                                                                     0x0000001FL
23410 #define SQ_THREAD_TRACE_MASK__SH_SEL_MASK                                                                     0x00000020L
23411 #define SQ_THREAD_TRACE_MASK__REG_STALL_EN_MASK                                                               0x00000080L
23412 #define SQ_THREAD_TRACE_MASK__SIMD_EN_MASK                                                                    0x00000F00L
23413 #define SQ_THREAD_TRACE_MASK__VM_ID_MASK_MASK                                                                 0x00003000L
23414 #define SQ_THREAD_TRACE_MASK__SPI_STALL_EN_MASK                                                               0x00004000L
23415 #define SQ_THREAD_TRACE_MASK__SQ_STALL_EN_MASK                                                                0x00008000L
23416 //SQ_THREAD_TRACE_TOKEN_MASK
23417 #define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK__SHIFT                                                         0x0
23418 #define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK__SHIFT                                                           0x10
23419 #define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL__SHIFT                                                  0x18
23420 #define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK_MASK                                                           0x0000FFFFL
23421 #define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK_MASK                                                             0x00FF0000L
23422 #define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL_MASK                                                    0x01000000L
23423 //SQ_THREAD_TRACE_PERF_MASK
23424 #define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK__SHIFT                                                            0x0
23425 #define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK__SHIFT                                                            0x10
23426 #define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK_MASK                                                              0x0000FFFFL
23427 #define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK_MASK                                                              0xFFFF0000L
23428 //SQ_THREAD_TRACE_CTRL
23429 #define SQ_THREAD_TRACE_CTRL__RESET_BUFFER__SHIFT                                                             0x1f
23430 #define SQ_THREAD_TRACE_CTRL__RESET_BUFFER_MASK                                                               0x80000000L
23431 //SQ_THREAD_TRACE_MODE
23432 #define SQ_THREAD_TRACE_MODE__MASK_PS__SHIFT                                                                  0x0
23433 #define SQ_THREAD_TRACE_MODE__MASK_VS__SHIFT                                                                  0x3
23434 #define SQ_THREAD_TRACE_MODE__MASK_GS__SHIFT                                                                  0x6
23435 #define SQ_THREAD_TRACE_MODE__MASK_ES__SHIFT                                                                  0x9
23436 #define SQ_THREAD_TRACE_MODE__MASK_HS__SHIFT                                                                  0xc
23437 #define SQ_THREAD_TRACE_MODE__MASK_LS__SHIFT                                                                  0xf
23438 #define SQ_THREAD_TRACE_MODE__MASK_CS__SHIFT                                                                  0x12
23439 #define SQ_THREAD_TRACE_MODE__MODE__SHIFT                                                                     0x15
23440 #define SQ_THREAD_TRACE_MODE__CAPTURE_MODE__SHIFT                                                             0x17
23441 #define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN__SHIFT                                                             0x19
23442 #define SQ_THREAD_TRACE_MODE__TC_PERF_EN__SHIFT                                                               0x1a
23443 #define SQ_THREAD_TRACE_MODE__ISSUE_MASK__SHIFT                                                               0x1b
23444 #define SQ_THREAD_TRACE_MODE__TEST_MODE__SHIFT                                                                0x1d
23445 #define SQ_THREAD_TRACE_MODE__INTERRUPT_EN__SHIFT                                                             0x1e
23446 #define SQ_THREAD_TRACE_MODE__WRAP__SHIFT                                                                     0x1f
23447 #define SQ_THREAD_TRACE_MODE__MASK_PS_MASK                                                                    0x00000007L
23448 #define SQ_THREAD_TRACE_MODE__MASK_VS_MASK                                                                    0x00000038L
23449 #define SQ_THREAD_TRACE_MODE__MASK_GS_MASK                                                                    0x000001C0L
23450 #define SQ_THREAD_TRACE_MODE__MASK_ES_MASK                                                                    0x00000E00L
23451 #define SQ_THREAD_TRACE_MODE__MASK_HS_MASK                                                                    0x00007000L
23452 #define SQ_THREAD_TRACE_MODE__MASK_LS_MASK                                                                    0x00038000L
23453 #define SQ_THREAD_TRACE_MODE__MASK_CS_MASK                                                                    0x001C0000L
23454 #define SQ_THREAD_TRACE_MODE__MODE_MASK                                                                       0x00600000L
23455 #define SQ_THREAD_TRACE_MODE__CAPTURE_MODE_MASK                                                               0x01800000L
23456 #define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN_MASK                                                               0x02000000L
23457 #define SQ_THREAD_TRACE_MODE__TC_PERF_EN_MASK                                                                 0x04000000L
23458 #define SQ_THREAD_TRACE_MODE__ISSUE_MASK_MASK                                                                 0x18000000L
23459 #define SQ_THREAD_TRACE_MODE__TEST_MODE_MASK                                                                  0x20000000L
23460 #define SQ_THREAD_TRACE_MODE__INTERRUPT_EN_MASK                                                               0x40000000L
23461 #define SQ_THREAD_TRACE_MODE__WRAP_MASK                                                                       0x80000000L
23462 //SQ_THREAD_TRACE_BASE2
23463 #define SQ_THREAD_TRACE_BASE2__ADDR_HI__SHIFT                                                                 0x0
23464 #define SQ_THREAD_TRACE_BASE2__ADDR_HI_MASK                                                                   0x0000000FL
23465 //SQ_THREAD_TRACE_TOKEN_MASK2
23466 #define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK__SHIFT                                                         0x0
23467 #define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK_MASK                                                           0xFFFFFFFFL
23468 //SQ_THREAD_TRACE_WPTR
23469 #define SQ_THREAD_TRACE_WPTR__WPTR__SHIFT                                                                     0x0
23470 #define SQ_THREAD_TRACE_WPTR__READ_OFFSET__SHIFT                                                              0x1e
23471 #define SQ_THREAD_TRACE_WPTR__WPTR_MASK                                                                       0x3FFFFFFFL
23472 #define SQ_THREAD_TRACE_WPTR__READ_OFFSET_MASK                                                                0xC0000000L
23473 //SQ_THREAD_TRACE_STATUS
23474 #define SQ_THREAD_TRACE_STATUS__FINISH_PENDING__SHIFT                                                         0x0
23475 #define SQ_THREAD_TRACE_STATUS__FINISH_DONE__SHIFT                                                            0x10
23476 #define SQ_THREAD_TRACE_STATUS__UTC_ERROR__SHIFT                                                              0x1c
23477 #define SQ_THREAD_TRACE_STATUS__NEW_BUF__SHIFT                                                                0x1d
23478 #define SQ_THREAD_TRACE_STATUS__BUSY__SHIFT                                                                   0x1e
23479 #define SQ_THREAD_TRACE_STATUS__FULL__SHIFT                                                                   0x1f
23480 #define SQ_THREAD_TRACE_STATUS__FINISH_PENDING_MASK                                                           0x000003FFL
23481 #define SQ_THREAD_TRACE_STATUS__FINISH_DONE_MASK                                                              0x03FF0000L
23482 #define SQ_THREAD_TRACE_STATUS__UTC_ERROR_MASK                                                                0x10000000L
23483 #define SQ_THREAD_TRACE_STATUS__NEW_BUF_MASK                                                                  0x20000000L
23484 #define SQ_THREAD_TRACE_STATUS__BUSY_MASK                                                                     0x40000000L
23485 #define SQ_THREAD_TRACE_STATUS__FULL_MASK                                                                     0x80000000L
23486 //SQ_THREAD_TRACE_HIWATER
23487 #define SQ_THREAD_TRACE_HIWATER__HIWATER__SHIFT                                                               0x0
23488 #define SQ_THREAD_TRACE_HIWATER__HIWATER_MASK                                                                 0x00000007L
23489 //SQ_THREAD_TRACE_CNTR
23490 #define SQ_THREAD_TRACE_CNTR__CNTR__SHIFT                                                                     0x0
23491 #define SQ_THREAD_TRACE_CNTR__CNTR_MASK                                                                       0xFFFFFFFFL
23492 //SQ_THREAD_TRACE_USERDATA_0
23493 #define SQ_THREAD_TRACE_USERDATA_0__DATA__SHIFT                                                               0x0
23494 #define SQ_THREAD_TRACE_USERDATA_0__DATA_MASK                                                                 0xFFFFFFFFL
23495 //SQ_THREAD_TRACE_USERDATA_1
23496 #define SQ_THREAD_TRACE_USERDATA_1__DATA__SHIFT                                                               0x0
23497 #define SQ_THREAD_TRACE_USERDATA_1__DATA_MASK                                                                 0xFFFFFFFFL
23498 //SQ_THREAD_TRACE_USERDATA_2
23499 #define SQ_THREAD_TRACE_USERDATA_2__DATA__SHIFT                                                               0x0
23500 #define SQ_THREAD_TRACE_USERDATA_2__DATA_MASK                                                                 0xFFFFFFFFL
23501 //SQ_THREAD_TRACE_USERDATA_3
23502 #define SQ_THREAD_TRACE_USERDATA_3__DATA__SHIFT                                                               0x0
23503 #define SQ_THREAD_TRACE_USERDATA_3__DATA_MASK                                                                 0xFFFFFFFFL
23504 //SQC_CACHES
23505 #define SQC_CACHES__TARGET_INST__SHIFT                                                                        0x0
23506 #define SQC_CACHES__TARGET_DATA__SHIFT                                                                        0x1
23507 #define SQC_CACHES__INVALIDATE__SHIFT                                                                         0x2
23508 #define SQC_CACHES__WRITEBACK__SHIFT                                                                          0x3
23509 #define SQC_CACHES__VOL__SHIFT                                                                                0x4
23510 #define SQC_CACHES__COMPLETE__SHIFT                                                                           0x10
23511 #define SQC_CACHES__TARGET_INST_MASK                                                                          0x00000001L
23512 #define SQC_CACHES__TARGET_DATA_MASK                                                                          0x00000002L
23513 #define SQC_CACHES__INVALIDATE_MASK                                                                           0x00000004L
23514 #define SQC_CACHES__WRITEBACK_MASK                                                                            0x00000008L
23515 #define SQC_CACHES__VOL_MASK                                                                                  0x00000010L
23516 #define SQC_CACHES__COMPLETE_MASK                                                                             0x00010000L
23517 //SQC_WRITEBACK
23518 #define SQC_WRITEBACK__DWB__SHIFT                                                                             0x0
23519 #define SQC_WRITEBACK__DIRTY__SHIFT                                                                           0x1
23520 #define SQC_WRITEBACK__DWB_MASK                                                                               0x00000001L
23521 #define SQC_WRITEBACK__DIRTY_MASK                                                                             0x00000002L
23522 //DB_OCCLUSION_COUNT0_LOW
23523 #define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW__SHIFT                                                             0x0
23524 #define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW_MASK                                                               0xFFFFFFFFL
23525 //DB_OCCLUSION_COUNT0_HI
23526 #define DB_OCCLUSION_COUNT0_HI__COUNT_HI__SHIFT                                                               0x0
23527 #define DB_OCCLUSION_COUNT0_HI__COUNT_HI_MASK                                                                 0x7FFFFFFFL
23528 //DB_OCCLUSION_COUNT1_LOW
23529 #define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW__SHIFT                                                             0x0
23530 #define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW_MASK                                                               0xFFFFFFFFL
23531 //DB_OCCLUSION_COUNT1_HI
23532 #define DB_OCCLUSION_COUNT1_HI__COUNT_HI__SHIFT                                                               0x0
23533 #define DB_OCCLUSION_COUNT1_HI__COUNT_HI_MASK                                                                 0x7FFFFFFFL
23534 //DB_OCCLUSION_COUNT2_LOW
23535 #define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW__SHIFT                                                             0x0
23536 #define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW_MASK                                                               0xFFFFFFFFL
23537 //DB_OCCLUSION_COUNT2_HI
23538 #define DB_OCCLUSION_COUNT2_HI__COUNT_HI__SHIFT                                                               0x0
23539 #define DB_OCCLUSION_COUNT2_HI__COUNT_HI_MASK                                                                 0x7FFFFFFFL
23540 //DB_OCCLUSION_COUNT3_LOW
23541 #define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW__SHIFT                                                             0x0
23542 #define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW_MASK                                                               0xFFFFFFFFL
23543 //DB_OCCLUSION_COUNT3_HI
23544 #define DB_OCCLUSION_COUNT3_HI__COUNT_HI__SHIFT                                                               0x0
23545 #define DB_OCCLUSION_COUNT3_HI__COUNT_HI_MASK                                                                 0x7FFFFFFFL
23546 //DB_ZPASS_COUNT_LOW
23547 #define DB_ZPASS_COUNT_LOW__COUNT_LOW__SHIFT                                                                  0x0
23548 #define DB_ZPASS_COUNT_LOW__COUNT_LOW_MASK                                                                    0xFFFFFFFFL
23549 //DB_ZPASS_COUNT_HI
23550 #define DB_ZPASS_COUNT_HI__COUNT_HI__SHIFT                                                                    0x0
23551 #define DB_ZPASS_COUNT_HI__COUNT_HI_MASK                                                                      0x7FFFFFFFL
23552 //GDS_RD_ADDR
23553 #define GDS_RD_ADDR__READ_ADDR__SHIFT                                                                         0x0
23554 #define GDS_RD_ADDR__READ_ADDR_MASK                                                                           0xFFFFFFFFL
23555 //GDS_RD_DATA
23556 #define GDS_RD_DATA__READ_DATA__SHIFT                                                                         0x0
23557 #define GDS_RD_DATA__READ_DATA_MASK                                                                           0xFFFFFFFFL
23558 //GDS_RD_BURST_ADDR
23559 #define GDS_RD_BURST_ADDR__BURST_ADDR__SHIFT                                                                  0x0
23560 #define GDS_RD_BURST_ADDR__BURST_ADDR_MASK                                                                    0xFFFFFFFFL
23561 //GDS_RD_BURST_COUNT
23562 #define GDS_RD_BURST_COUNT__BURST_COUNT__SHIFT                                                                0x0
23563 #define GDS_RD_BURST_COUNT__BURST_COUNT_MASK                                                                  0xFFFFFFFFL
23564 //GDS_RD_BURST_DATA
23565 #define GDS_RD_BURST_DATA__BURST_DATA__SHIFT                                                                  0x0
23566 #define GDS_RD_BURST_DATA__BURST_DATA_MASK                                                                    0xFFFFFFFFL
23567 //GDS_WR_ADDR
23568 #define GDS_WR_ADDR__WRITE_ADDR__SHIFT                                                                        0x0
23569 #define GDS_WR_ADDR__WRITE_ADDR_MASK                                                                          0xFFFFFFFFL
23570 //GDS_WR_DATA
23571 #define GDS_WR_DATA__WRITE_DATA__SHIFT                                                                        0x0
23572 #define GDS_WR_DATA__WRITE_DATA_MASK                                                                          0xFFFFFFFFL
23573 //GDS_WR_BURST_ADDR
23574 #define GDS_WR_BURST_ADDR__WRITE_ADDR__SHIFT                                                                  0x0
23575 #define GDS_WR_BURST_ADDR__WRITE_ADDR_MASK                                                                    0xFFFFFFFFL
23576 //GDS_WR_BURST_DATA
23577 #define GDS_WR_BURST_DATA__WRITE_DATA__SHIFT                                                                  0x0
23578 #define GDS_WR_BURST_DATA__WRITE_DATA_MASK                                                                    0xFFFFFFFFL
23579 //GDS_WRITE_COMPLETE
23580 #define GDS_WRITE_COMPLETE__WRITE_COMPLETE__SHIFT                                                             0x0
23581 #define GDS_WRITE_COMPLETE__WRITE_COMPLETE_MASK                                                               0xFFFFFFFFL
23582 //GDS_ATOM_CNTL
23583 #define GDS_ATOM_CNTL__AINC__SHIFT                                                                            0x0
23584 #define GDS_ATOM_CNTL__UNUSED1__SHIFT                                                                         0x6
23585 #define GDS_ATOM_CNTL__DMODE__SHIFT                                                                           0x8
23586 #define GDS_ATOM_CNTL__UNUSED2__SHIFT                                                                         0xa
23587 #define GDS_ATOM_CNTL__AINC_MASK                                                                              0x0000003FL
23588 #define GDS_ATOM_CNTL__UNUSED1_MASK                                                                           0x000000C0L
23589 #define GDS_ATOM_CNTL__DMODE_MASK                                                                             0x00000300L
23590 #define GDS_ATOM_CNTL__UNUSED2_MASK                                                                           0xFFFFFC00L
23591 //GDS_ATOM_COMPLETE
23592 #define GDS_ATOM_COMPLETE__COMPLETE__SHIFT                                                                    0x0
23593 #define GDS_ATOM_COMPLETE__UNUSED__SHIFT                                                                      0x1
23594 #define GDS_ATOM_COMPLETE__COMPLETE_MASK                                                                      0x00000001L
23595 #define GDS_ATOM_COMPLETE__UNUSED_MASK                                                                        0xFFFFFFFEL
23596 //GDS_ATOM_BASE
23597 #define GDS_ATOM_BASE__BASE__SHIFT                                                                            0x0
23598 #define GDS_ATOM_BASE__UNUSED__SHIFT                                                                          0x10
23599 #define GDS_ATOM_BASE__BASE_MASK                                                                              0x0000FFFFL
23600 #define GDS_ATOM_BASE__UNUSED_MASK                                                                            0xFFFF0000L
23601 //GDS_ATOM_SIZE
23602 #define GDS_ATOM_SIZE__SIZE__SHIFT                                                                            0x0
23603 #define GDS_ATOM_SIZE__UNUSED__SHIFT                                                                          0x10
23604 #define GDS_ATOM_SIZE__SIZE_MASK                                                                              0x0000FFFFL
23605 #define GDS_ATOM_SIZE__UNUSED_MASK                                                                            0xFFFF0000L
23606 //GDS_ATOM_OFFSET0
23607 #define GDS_ATOM_OFFSET0__OFFSET0__SHIFT                                                                      0x0
23608 #define GDS_ATOM_OFFSET0__UNUSED__SHIFT                                                                       0x8
23609 #define GDS_ATOM_OFFSET0__OFFSET0_MASK                                                                        0x000000FFL
23610 #define GDS_ATOM_OFFSET0__UNUSED_MASK                                                                         0xFFFFFF00L
23611 //GDS_ATOM_OFFSET1
23612 #define GDS_ATOM_OFFSET1__OFFSET1__SHIFT                                                                      0x0
23613 #define GDS_ATOM_OFFSET1__UNUSED__SHIFT                                                                       0x8
23614 #define GDS_ATOM_OFFSET1__OFFSET1_MASK                                                                        0x000000FFL
23615 #define GDS_ATOM_OFFSET1__UNUSED_MASK                                                                         0xFFFFFF00L
23616 //GDS_ATOM_DST
23617 #define GDS_ATOM_DST__DST__SHIFT                                                                              0x0
23618 #define GDS_ATOM_DST__DST_MASK                                                                                0xFFFFFFFFL
23619 //GDS_ATOM_OP
23620 #define GDS_ATOM_OP__OP__SHIFT                                                                                0x0
23621 #define GDS_ATOM_OP__UNUSED__SHIFT                                                                            0x8
23622 #define GDS_ATOM_OP__OP_MASK                                                                                  0x000000FFL
23623 #define GDS_ATOM_OP__UNUSED_MASK                                                                              0xFFFFFF00L
23624 //GDS_ATOM_SRC0
23625 #define GDS_ATOM_SRC0__DATA__SHIFT                                                                            0x0
23626 #define GDS_ATOM_SRC0__DATA_MASK                                                                              0xFFFFFFFFL
23627 //GDS_ATOM_SRC0_U
23628 #define GDS_ATOM_SRC0_U__DATA__SHIFT                                                                          0x0
23629 #define GDS_ATOM_SRC0_U__DATA_MASK                                                                            0xFFFFFFFFL
23630 //GDS_ATOM_SRC1
23631 #define GDS_ATOM_SRC1__DATA__SHIFT                                                                            0x0
23632 #define GDS_ATOM_SRC1__DATA_MASK                                                                              0xFFFFFFFFL
23633 //GDS_ATOM_SRC1_U
23634 #define GDS_ATOM_SRC1_U__DATA__SHIFT                                                                          0x0
23635 #define GDS_ATOM_SRC1_U__DATA_MASK                                                                            0xFFFFFFFFL
23636 //GDS_ATOM_READ0
23637 #define GDS_ATOM_READ0__DATA__SHIFT                                                                           0x0
23638 #define GDS_ATOM_READ0__DATA_MASK                                                                             0xFFFFFFFFL
23639 //GDS_ATOM_READ0_U
23640 #define GDS_ATOM_READ0_U__DATA__SHIFT                                                                         0x0
23641 #define GDS_ATOM_READ0_U__DATA_MASK                                                                           0xFFFFFFFFL
23642 //GDS_ATOM_READ1
23643 #define GDS_ATOM_READ1__DATA__SHIFT                                                                           0x0
23644 #define GDS_ATOM_READ1__DATA_MASK                                                                             0xFFFFFFFFL
23645 //GDS_ATOM_READ1_U
23646 #define GDS_ATOM_READ1_U__DATA__SHIFT                                                                         0x0
23647 #define GDS_ATOM_READ1_U__DATA_MASK                                                                           0xFFFFFFFFL
23648 //GDS_GWS_RESOURCE_CNTL
23649 #define GDS_GWS_RESOURCE_CNTL__INDEX__SHIFT                                                                   0x0
23650 #define GDS_GWS_RESOURCE_CNTL__UNUSED__SHIFT                                                                  0x6
23651 #define GDS_GWS_RESOURCE_CNTL__INDEX_MASK                                                                     0x0000003FL
23652 #define GDS_GWS_RESOURCE_CNTL__UNUSED_MASK                                                                    0xFFFFFFC0L
23653 //GDS_GWS_RESOURCE
23654 #define GDS_GWS_RESOURCE__FLAG__SHIFT                                                                         0x0
23655 #define GDS_GWS_RESOURCE__COUNTER__SHIFT                                                                      0x1
23656 #define GDS_GWS_RESOURCE__TYPE__SHIFT                                                                         0xe
23657 #define GDS_GWS_RESOURCE__DED__SHIFT                                                                          0xf
23658 #define GDS_GWS_RESOURCE__RELEASE_ALL__SHIFT                                                                  0x10
23659 #define GDS_GWS_RESOURCE__HEAD_QUEUE__SHIFT                                                                   0x11
23660 #define GDS_GWS_RESOURCE__HEAD_VALID__SHIFT                                                                   0x1d
23661 #define GDS_GWS_RESOURCE__HEAD_FLAG__SHIFT                                                                    0x1e
23662 #define GDS_GWS_RESOURCE__HALTED__SHIFT                                                                       0x1f
23663 #define GDS_GWS_RESOURCE__FLAG_MASK                                                                           0x00000001L
23664 #define GDS_GWS_RESOURCE__COUNTER_MASK                                                                        0x00003FFEL
23665 #define GDS_GWS_RESOURCE__TYPE_MASK                                                                           0x00004000L
23666 #define GDS_GWS_RESOURCE__DED_MASK                                                                            0x00008000L
23667 #define GDS_GWS_RESOURCE__RELEASE_ALL_MASK                                                                    0x00010000L
23668 #define GDS_GWS_RESOURCE__HEAD_QUEUE_MASK                                                                     0x1FFE0000L
23669 #define GDS_GWS_RESOURCE__HEAD_VALID_MASK                                                                     0x20000000L
23670 #define GDS_GWS_RESOURCE__HEAD_FLAG_MASK                                                                      0x40000000L
23671 #define GDS_GWS_RESOURCE__HALTED_MASK                                                                         0x80000000L
23672 //GDS_GWS_RESOURCE_CNT
23673 #define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT__SHIFT                                                             0x0
23674 #define GDS_GWS_RESOURCE_CNT__UNUSED__SHIFT                                                                   0x10
23675 #define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT_MASK                                                               0x0000FFFFL
23676 #define GDS_GWS_RESOURCE_CNT__UNUSED_MASK                                                                     0xFFFF0000L
23677 //GDS_OA_CNTL
23678 #define GDS_OA_CNTL__INDEX__SHIFT                                                                             0x0
23679 #define GDS_OA_CNTL__UNUSED__SHIFT                                                                            0x4
23680 #define GDS_OA_CNTL__INDEX_MASK                                                                               0x0000000FL
23681 #define GDS_OA_CNTL__UNUSED_MASK                                                                              0xFFFFFFF0L
23682 //GDS_OA_COUNTER
23683 #define GDS_OA_COUNTER__SPACE_AVAILABLE__SHIFT                                                                0x0
23684 #define GDS_OA_COUNTER__SPACE_AVAILABLE_MASK                                                                  0xFFFFFFFFL
23685 //GDS_OA_ADDRESS
23686 #define GDS_OA_ADDRESS__DS_ADDRESS__SHIFT                                                                     0x0
23687 #define GDS_OA_ADDRESS__CRAWLER__SHIFT                                                                        0x10
23688 #define GDS_OA_ADDRESS__CRAWLER_TYPE__SHIFT                                                                   0x14
23689 #define GDS_OA_ADDRESS__UNUSED__SHIFT                                                                         0x16
23690 #define GDS_OA_ADDRESS__NO_ALLOC__SHIFT                                                                       0x1e
23691 #define GDS_OA_ADDRESS__ENABLE__SHIFT                                                                         0x1f
23692 #define GDS_OA_ADDRESS__DS_ADDRESS_MASK                                                                       0x0000FFFFL
23693 #define GDS_OA_ADDRESS__CRAWLER_MASK                                                                          0x000F0000L
23694 #define GDS_OA_ADDRESS__CRAWLER_TYPE_MASK                                                                     0x00300000L
23695 #define GDS_OA_ADDRESS__UNUSED_MASK                                                                           0x3FC00000L
23696 #define GDS_OA_ADDRESS__NO_ALLOC_MASK                                                                         0x40000000L
23697 #define GDS_OA_ADDRESS__ENABLE_MASK                                                                           0x80000000L
23698 //GDS_OA_INCDEC
23699 #define GDS_OA_INCDEC__VALUE__SHIFT                                                                           0x0
23700 #define GDS_OA_INCDEC__INCDEC__SHIFT                                                                          0x1f
23701 #define GDS_OA_INCDEC__VALUE_MASK                                                                             0x7FFFFFFFL
23702 #define GDS_OA_INCDEC__INCDEC_MASK                                                                            0x80000000L
23703 //GDS_OA_RING_SIZE
23704 #define GDS_OA_RING_SIZE__RING_SIZE__SHIFT                                                                    0x0
23705 #define GDS_OA_RING_SIZE__RING_SIZE_MASK                                                                      0xFFFFFFFFL
23706 //SPI_CONFIG_CNTL
23707 #define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY__SHIFT                                                            0x0
23708 #define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER__SHIFT                                                            0x15
23709 #define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS__SHIFT                                                         0x18
23710 #define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS__SHIFT                                                         0x19
23711 #define SPI_CONFIG_CNTL__RSRC_MGMT_RESET__SHIFT                                                               0x1a
23712 #define SPI_CONFIG_CNTL__TTRACE_STALL_ALL__SHIFT                                                              0x1b
23713 #define SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA__SHIFT                                                             0x1c
23714 #define SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA__SHIFT                                                               0x1d
23715 #define SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL__SHIFT                                                          0x1e
23716 #define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY_MASK                                                              0x001FFFFFL
23717 #define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER_MASK                                                              0x00E00000L
23718 #define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS_MASK                                                           0x01000000L
23719 #define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS_MASK                                                           0x02000000L
23720 #define SPI_CONFIG_CNTL__RSRC_MGMT_RESET_MASK                                                                 0x04000000L
23721 #define SPI_CONFIG_CNTL__TTRACE_STALL_ALL_MASK                                                                0x08000000L
23722 #define SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA_MASK                                                               0x10000000L
23723 #define SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA_MASK                                                                 0x20000000L
23724 #define SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL_MASK                                                            0xC0000000L
23725 //SPI_CONFIG_CNTL_1
23726 #define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT                                                              0x0
23727 #define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW__SHIFT                                                     0x4
23728 #define SPI_CONFIG_CNTL_1__BATON_RESET_DISABLE__SHIFT                                                         0x5
23729 #define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE__SHIFT                                                             0x6
23730 #define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT__SHIFT                                                             0x7
23731 #define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE__SHIFT                                                   0x8
23732 #define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE__SHIFT                                                            0x9
23733 #define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT__SHIFT                                                             0xa
23734 #define SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE__SHIFT                                                        0xe
23735 #define SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE__SHIFT                                                        0xf
23736 #define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE__SHIFT                                                               0x10
23737 #define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_MASK                                                                0x0000000FL
23738 #define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK                                                       0x00000010L
23739 #define SPI_CONFIG_CNTL_1__BATON_RESET_DISABLE_MASK                                                           0x00000020L
23740 #define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK                                                               0x00000040L
23741 #define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT_MASK                                                               0x00000080L
23742 #define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE_MASK                                                     0x00000100L
23743 #define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE_MASK                                                              0x00000200L
23744 #define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT_MASK                                                               0x00003C00L
23745 #define SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE_MASK                                                          0x00004000L
23746 #define SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE_MASK                                                          0x00008000L
23747 #define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE_MASK                                                                 0xFFFF0000L
23748 //SPI_CONFIG_CNTL_2
23749 #define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD__SHIFT                                    0x0
23750 #define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD__SHIFT                                      0x4
23751 #define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD_MASK                                      0x0000000FL
23752 #define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD_MASK                                        0x000000F0L
23753 //SPI_WAVE_LIMIT_CNTL
23754 #define SPI_WAVE_LIMIT_CNTL__PS_WAVE_GRAN__SHIFT                                                              0x0
23755 #define SPI_WAVE_LIMIT_CNTL__VS_WAVE_GRAN__SHIFT                                                              0x2
23756 #define SPI_WAVE_LIMIT_CNTL__GS_WAVE_GRAN__SHIFT                                                              0x4
23757 #define SPI_WAVE_LIMIT_CNTL__HS_WAVE_GRAN__SHIFT                                                              0x6
23758 #define SPI_WAVE_LIMIT_CNTL__PS_WAVE_GRAN_MASK                                                                0x00000003L
23759 #define SPI_WAVE_LIMIT_CNTL__VS_WAVE_GRAN_MASK                                                                0x0000000CL
23760 #define SPI_WAVE_LIMIT_CNTL__GS_WAVE_GRAN_MASK                                                                0x00000030L
23761 #define SPI_WAVE_LIMIT_CNTL__HS_WAVE_GRAN_MASK                                                                0x000000C0L
23762 
23763 // addressBlock: xcd0_gc_gccanedec
23764 //GC_CANE_ERR_STATUS
23765 #define GC_CANE_ERR_STATUS__SDPM_RDRSP_STATUS__SHIFT                                                          0x0
23766 #define GC_CANE_ERR_STATUS__SDPM_WRRSP_STATUS__SHIFT                                                          0x4
23767 #define GC_CANE_ERR_STATUS__SDPM_RDRSP_DATASTATUS__SHIFT                                                      0x8
23768 #define GC_CANE_ERR_STATUS__SDPM_RDRSP_DATAPARITY_ERROR__SHIFT                                                0xa
23769 #define GC_CANE_ERR_STATUS__SDPS_DAT_ERROR__SHIFT                                                             0xb
23770 #define GC_CANE_ERR_STATUS__SDPS_DAT_PARITY_ERROR__SHIFT                                                      0xc
23771 #define GC_CANE_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT                                                         0xd
23772 #define GC_CANE_ERR_STATUS__BUSY_ON_ERROR__SHIFT                                                              0xe
23773 #define GC_CANE_ERR_STATUS__BUSY_ON_UER_ERROR__SHIFT                                                          0xf
23774 #define GC_CANE_ERR_STATUS__FUE_FLAG__SHIFT                                                                   0x10
23775 #define GC_CANE_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT                                                         0x11
23776 #define GC_CANE_ERR_STATUS__LEVEL_INTERRUPT__SHIFT                                                            0x12
23777 #define GC_CANE_ERR_STATUS__SDPM_RDRSP_STATUS_MASK                                                            0x0000000FL
23778 #define GC_CANE_ERR_STATUS__SDPM_WRRSP_STATUS_MASK                                                            0x000000F0L
23779 #define GC_CANE_ERR_STATUS__SDPM_RDRSP_DATASTATUS_MASK                                                        0x00000300L
23780 #define GC_CANE_ERR_STATUS__SDPM_RDRSP_DATAPARITY_ERROR_MASK                                                  0x00000400L
23781 #define GC_CANE_ERR_STATUS__SDPS_DAT_ERROR_MASK                                                               0x00000800L
23782 #define GC_CANE_ERR_STATUS__SDPS_DAT_PARITY_ERROR_MASK                                                        0x00001000L
23783 #define GC_CANE_ERR_STATUS__CLEAR_ERROR_STATUS_MASK                                                           0x00002000L
23784 #define GC_CANE_ERR_STATUS__BUSY_ON_ERROR_MASK                                                                0x00004000L
23785 #define GC_CANE_ERR_STATUS__BUSY_ON_UER_ERROR_MASK                                                            0x00008000L
23786 #define GC_CANE_ERR_STATUS__FUE_FLAG_MASK                                                                     0x00010000L
23787 #define GC_CANE_ERR_STATUS__INTERRUPT_ON_FATAL_MASK                                                           0x00020000L
23788 #define GC_CANE_ERR_STATUS__LEVEL_INTERRUPT_MASK                                                              0x00040000L
23789 //GC_CANE_UE_ERR_STATUS_LO
23790 #define GC_CANE_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT                                                0x0
23791 #define GC_CANE_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT                                                   0x1
23792 #define GC_CANE_UE_ERR_STATUS_LO__ADDRESS__SHIFT                                                              0x2
23793 #define GC_CANE_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT                                                            0x18
23794 #define GC_CANE_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK                                                  0x00000001L
23795 #define GC_CANE_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK                                                     0x00000002L
23796 #define GC_CANE_UE_ERR_STATUS_LO__ADDRESS_MASK                                                                0x00FFFFFCL
23797 #define GC_CANE_UE_ERR_STATUS_LO__MEMORY_ID_MASK                                                              0xFF000000L
23798 //GC_CANE_UE_ERR_STATUS_HI
23799 #define GC_CANE_UE_ERR_STATUS_HI__ECC__SHIFT                                                                  0x0
23800 #define GC_CANE_UE_ERR_STATUS_HI__PARITY__SHIFT                                                               0x1
23801 #define GC_CANE_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT                                                  0x2
23802 #define GC_CANE_UE_ERR_STATUS_HI__ERR_INFO__SHIFT                                                             0x3
23803 #define GC_CANE_UE_ERR_STATUS_HI__UE_CNT__SHIFT                                                               0x17
23804 #define GC_CANE_UE_ERR_STATUS_HI__FED_CNT__SHIFT                                                              0x1a
23805 #define GC_CANE_UE_ERR_STATUS_HI__ECC_MASK                                                                    0x00000001L
23806 #define GC_CANE_UE_ERR_STATUS_HI__PARITY_MASK                                                                 0x00000002L
23807 #define GC_CANE_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK                                                    0x00000004L
23808 #define GC_CANE_UE_ERR_STATUS_HI__ERR_INFO_MASK                                                               0x007FFFF8L
23809 #define GC_CANE_UE_ERR_STATUS_HI__UE_CNT_MASK                                                                 0x03800000L
23810 #define GC_CANE_UE_ERR_STATUS_HI__FED_CNT_MASK                                                                0x1C000000L
23811 //GC_CANE_CE_ERR_STATUS_LO
23812 #define GC_CANE_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT                                                0x0
23813 #define GC_CANE_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT                                                   0x1
23814 #define GC_CANE_CE_ERR_STATUS_LO__ADDRESS__SHIFT                                                              0x2
23815 #define GC_CANE_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT                                                            0x18
23816 #define GC_CANE_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK                                                  0x00000001L
23817 #define GC_CANE_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK                                                     0x00000002L
23818 #define GC_CANE_CE_ERR_STATUS_LO__ADDRESS_MASK                                                                0x00FFFFFCL
23819 #define GC_CANE_CE_ERR_STATUS_LO__MEMORY_ID_MASK                                                              0xFF000000L
23820 //GC_CANE_CE_ERR_STATUS_HI
23821 #define GC_CANE_CE_ERR_STATUS_HI__ECC__SHIFT                                                                  0x0
23822 #define GC_CANE_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT                                                  0x2
23823 #define GC_CANE_CE_ERR_STATUS_HI__ERR_INFO__SHIFT                                                             0x3
23824 #define GC_CANE_CE_ERR_STATUS_HI__CE_CNT__SHIFT                                                               0x17
23825 #define GC_CANE_CE_ERR_STATUS_HI__POISON__SHIFT                                                               0x1a
23826 #define GC_CANE_CE_ERR_STATUS_HI__ECC_MASK                                                                    0x00000001L
23827 #define GC_CANE_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK                                                    0x00000004L
23828 #define GC_CANE_CE_ERR_STATUS_HI__ERR_INFO_MASK                                                               0x007FFFF8L
23829 #define GC_CANE_CE_ERR_STATUS_HI__CE_CNT_MASK                                                                 0x03800000L
23830 #define GC_CANE_CE_ERR_STATUS_HI__POISON_MASK                                                                 0x04000000L
23831 
23832 // addressBlock: xcd0_gc_perfddec
23833 //CPG_PERFCOUNTER1_LO
23834 #define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
23835 #define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
23836 //CPG_PERFCOUNTER1_HI
23837 #define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
23838 #define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
23839 //CPG_PERFCOUNTER0_LO
23840 #define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
23841 #define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
23842 //CPG_PERFCOUNTER0_HI
23843 #define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
23844 #define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
23845 //CPC_PERFCOUNTER1_LO
23846 #define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
23847 #define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
23848 //CPC_PERFCOUNTER1_HI
23849 #define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
23850 #define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
23851 //CPC_PERFCOUNTER0_LO
23852 #define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
23853 #define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
23854 //CPC_PERFCOUNTER0_HI
23855 #define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
23856 #define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
23857 //CPF_PERFCOUNTER1_LO
23858 #define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
23859 #define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
23860 //CPF_PERFCOUNTER1_HI
23861 #define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
23862 #define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
23863 //CPF_PERFCOUNTER0_LO
23864 #define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
23865 #define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
23866 //CPF_PERFCOUNTER0_HI
23867 #define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
23868 #define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
23869 //CPF_LATENCY_STATS_DATA
23870 #define CPF_LATENCY_STATS_DATA__DATA__SHIFT                                                                   0x0
23871 #define CPF_LATENCY_STATS_DATA__DATA_MASK                                                                     0xFFFFFFFFL
23872 //CPG_LATENCY_STATS_DATA
23873 #define CPG_LATENCY_STATS_DATA__DATA__SHIFT                                                                   0x0
23874 #define CPG_LATENCY_STATS_DATA__DATA_MASK                                                                     0xFFFFFFFFL
23875 //CPC_LATENCY_STATS_DATA
23876 #define CPC_LATENCY_STATS_DATA__DATA__SHIFT                                                                   0x0
23877 #define CPC_LATENCY_STATS_DATA__DATA_MASK                                                                     0xFFFFFFFFL
23878 //GRBM_PERFCOUNTER0_LO
23879 #define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                           0x0
23880 #define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                             0xFFFFFFFFL
23881 //GRBM_PERFCOUNTER0_HI
23882 #define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                           0x0
23883 #define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                             0xFFFFFFFFL
23884 //GRBM_PERFCOUNTER1_LO
23885 #define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                           0x0
23886 #define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                             0xFFFFFFFFL
23887 //GRBM_PERFCOUNTER1_HI
23888 #define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                           0x0
23889 #define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                             0xFFFFFFFFL
23890 //GRBM_SE0_PERFCOUNTER_LO
23891 #define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT                                                        0x0
23892 #define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK                                                          0xFFFFFFFFL
23893 //GRBM_SE0_PERFCOUNTER_HI
23894 #define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT                                                        0x0
23895 #define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK                                                          0xFFFFFFFFL
23896 //GRBM_SE1_PERFCOUNTER_LO
23897 #define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT                                                        0x0
23898 #define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK                                                          0xFFFFFFFFL
23899 //GRBM_SE1_PERFCOUNTER_HI
23900 #define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT                                                        0x0
23901 #define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK                                                          0xFFFFFFFFL
23902 //GRBM_SE2_PERFCOUNTER_LO
23903 #define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT                                                        0x0
23904 #define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK                                                          0xFFFFFFFFL
23905 //GRBM_SE2_PERFCOUNTER_HI
23906 #define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT                                                        0x0
23907 #define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK                                                          0xFFFFFFFFL
23908 //GRBM_SE3_PERFCOUNTER_LO
23909 #define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT                                                        0x0
23910 #define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK                                                          0xFFFFFFFFL
23911 //GRBM_SE3_PERFCOUNTER_HI
23912 #define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT                                                        0x0
23913 #define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK                                                          0xFFFFFFFFL
23914 //WD_PERFCOUNTER0_LO
23915 #define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
23916 #define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
23917 //WD_PERFCOUNTER0_HI
23918 #define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
23919 #define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
23920 //WD_PERFCOUNTER1_LO
23921 #define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
23922 #define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
23923 //WD_PERFCOUNTER1_HI
23924 #define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
23925 #define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
23926 //WD_PERFCOUNTER2_LO
23927 #define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
23928 #define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
23929 //WD_PERFCOUNTER2_HI
23930 #define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
23931 #define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
23932 //WD_PERFCOUNTER3_LO
23933 #define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
23934 #define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
23935 //WD_PERFCOUNTER3_HI
23936 #define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
23937 #define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
23938 //IA_PERFCOUNTER0_LO
23939 #define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
23940 #define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
23941 //IA_PERFCOUNTER0_HI
23942 #define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
23943 #define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
23944 //IA_PERFCOUNTER1_LO
23945 #define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
23946 #define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
23947 //IA_PERFCOUNTER1_HI
23948 #define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
23949 #define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
23950 //IA_PERFCOUNTER2_LO
23951 #define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
23952 #define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
23953 //IA_PERFCOUNTER2_HI
23954 #define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
23955 #define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
23956 //IA_PERFCOUNTER3_LO
23957 #define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
23958 #define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
23959 //IA_PERFCOUNTER3_HI
23960 #define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
23961 #define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
23962 //VGT_PERFCOUNTER0_LO
23963 #define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
23964 #define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
23965 //VGT_PERFCOUNTER0_HI
23966 #define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
23967 #define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
23968 //VGT_PERFCOUNTER1_LO
23969 #define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
23970 #define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
23971 //VGT_PERFCOUNTER1_HI
23972 #define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
23973 #define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
23974 //VGT_PERFCOUNTER2_LO
23975 #define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
23976 #define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
23977 //VGT_PERFCOUNTER2_HI
23978 #define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
23979 #define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
23980 //VGT_PERFCOUNTER3_LO
23981 #define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
23982 #define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
23983 //VGT_PERFCOUNTER3_HI
23984 #define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
23985 #define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
23986 //PA_SU_PERFCOUNTER0_LO
23987 #define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
23988 #define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
23989 //PA_SU_PERFCOUNTER0_HI
23990 #define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
23991 #define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                            0x0000FFFFL
23992 //PA_SU_PERFCOUNTER1_LO
23993 #define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
23994 #define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
23995 //PA_SU_PERFCOUNTER1_HI
23996 #define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
23997 #define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                            0x0000FFFFL
23998 //PA_SU_PERFCOUNTER2_LO
23999 #define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
24000 #define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
24001 //PA_SU_PERFCOUNTER2_HI
24002 #define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
24003 #define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                            0x0000FFFFL
24004 //PA_SU_PERFCOUNTER3_LO
24005 #define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
24006 #define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
24007 //PA_SU_PERFCOUNTER3_HI
24008 #define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
24009 #define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                            0x0000FFFFL
24010 //PA_SC_PERFCOUNTER0_LO
24011 #define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
24012 #define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
24013 //PA_SC_PERFCOUNTER0_HI
24014 #define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
24015 #define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
24016 //PA_SC_PERFCOUNTER1_LO
24017 #define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
24018 #define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
24019 //PA_SC_PERFCOUNTER1_HI
24020 #define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
24021 #define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
24022 //PA_SC_PERFCOUNTER2_LO
24023 #define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
24024 #define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
24025 //PA_SC_PERFCOUNTER2_HI
24026 #define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
24027 #define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
24028 //PA_SC_PERFCOUNTER3_LO
24029 #define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
24030 #define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
24031 //PA_SC_PERFCOUNTER3_HI
24032 #define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
24033 #define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
24034 //PA_SC_PERFCOUNTER4_LO
24035 #define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
24036 #define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
24037 //PA_SC_PERFCOUNTER4_HI
24038 #define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
24039 #define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
24040 //PA_SC_PERFCOUNTER5_LO
24041 #define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
24042 #define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
24043 //PA_SC_PERFCOUNTER5_HI
24044 #define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
24045 #define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
24046 //PA_SC_PERFCOUNTER6_LO
24047 #define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
24048 #define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
24049 //PA_SC_PERFCOUNTER6_HI
24050 #define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
24051 #define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
24052 //PA_SC_PERFCOUNTER7_LO
24053 #define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
24054 #define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
24055 //PA_SC_PERFCOUNTER7_HI
24056 #define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
24057 #define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
24058 //SPI_PERFCOUNTER0_HI
24059 #define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
24060 #define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
24061 //SPI_PERFCOUNTER0_LO
24062 #define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
24063 #define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
24064 //SPI_PERFCOUNTER1_HI
24065 #define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
24066 #define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
24067 //SPI_PERFCOUNTER1_LO
24068 #define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
24069 #define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
24070 //SPI_PERFCOUNTER2_HI
24071 #define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
24072 #define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
24073 //SPI_PERFCOUNTER2_LO
24074 #define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
24075 #define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
24076 //SPI_PERFCOUNTER3_HI
24077 #define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
24078 #define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
24079 //SPI_PERFCOUNTER3_LO
24080 #define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
24081 #define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
24082 //SPI_PERFCOUNTER4_HI
24083 #define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
24084 #define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
24085 //SPI_PERFCOUNTER4_LO
24086 #define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
24087 #define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
24088 //SPI_PERFCOUNTER5_HI
24089 #define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
24090 #define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
24091 //SPI_PERFCOUNTER5_LO
24092 #define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
24093 #define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
24094 //SQ_PERFCOUNTER0_LO
24095 #define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
24096 #define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
24097 //SQ_PERFCOUNTER0_HI
24098 #define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
24099 #define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
24100 //SQ_PERFCOUNTER1_LO
24101 #define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
24102 #define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
24103 //SQ_PERFCOUNTER1_HI
24104 #define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
24105 #define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
24106 //SQ_PERFCOUNTER2_LO
24107 #define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
24108 #define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
24109 //SQ_PERFCOUNTER2_HI
24110 #define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
24111 #define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
24112 //SQ_PERFCOUNTER3_LO
24113 #define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
24114 #define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
24115 //SQ_PERFCOUNTER3_HI
24116 #define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
24117 #define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
24118 //SQ_PERFCOUNTER4_LO
24119 #define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
24120 #define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
24121 //SQ_PERFCOUNTER4_HI
24122 #define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
24123 #define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
24124 //SQ_PERFCOUNTER5_LO
24125 #define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
24126 #define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
24127 //SQ_PERFCOUNTER5_HI
24128 #define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
24129 #define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
24130 //SQ_PERFCOUNTER6_LO
24131 #define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
24132 #define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
24133 //SQ_PERFCOUNTER6_HI
24134 #define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
24135 #define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
24136 //SQ_PERFCOUNTER7_LO
24137 #define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
24138 #define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
24139 //SQ_PERFCOUNTER7_HI
24140 #define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
24141 #define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
24142 //SQ_PERFCOUNTER8_LO
24143 #define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
24144 #define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
24145 //SQ_PERFCOUNTER8_HI
24146 #define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
24147 #define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
24148 //SQ_PERFCOUNTER9_LO
24149 #define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
24150 #define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
24151 //SQ_PERFCOUNTER9_HI
24152 #define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
24153 #define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
24154 //SQ_PERFCOUNTER10_LO
24155 #define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
24156 #define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
24157 //SQ_PERFCOUNTER10_HI
24158 #define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
24159 #define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
24160 //SQ_PERFCOUNTER11_LO
24161 #define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
24162 #define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
24163 //SQ_PERFCOUNTER11_HI
24164 #define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
24165 #define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
24166 //SQ_PERFCOUNTER12_LO
24167 #define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
24168 #define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
24169 //SQ_PERFCOUNTER12_HI
24170 #define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
24171 #define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
24172 //SQ_PERFCOUNTER13_LO
24173 #define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
24174 #define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
24175 //SQ_PERFCOUNTER13_HI
24176 #define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
24177 #define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
24178 //SQ_PERFCOUNTER14_LO
24179 #define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
24180 #define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
24181 //SQ_PERFCOUNTER14_HI
24182 #define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
24183 #define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
24184 //SQ_PERFCOUNTER15_LO
24185 #define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
24186 #define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
24187 //SQ_PERFCOUNTER15_HI
24188 #define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
24189 #define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
24190 //SX_PERFCOUNTER0_LO
24191 #define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
24192 #define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
24193 //SX_PERFCOUNTER0_HI
24194 #define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
24195 #define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
24196 //SX_PERFCOUNTER1_LO
24197 #define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
24198 #define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
24199 //SX_PERFCOUNTER1_HI
24200 #define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
24201 #define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
24202 //SX_PERFCOUNTER2_LO
24203 #define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
24204 #define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
24205 //SX_PERFCOUNTER2_HI
24206 #define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
24207 #define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
24208 //SX_PERFCOUNTER3_LO
24209 #define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
24210 #define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
24211 //SX_PERFCOUNTER3_HI
24212 #define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
24213 #define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
24214 //GDS_PERFCOUNTER0_LO
24215 #define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
24216 #define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
24217 //GDS_PERFCOUNTER0_HI
24218 #define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
24219 #define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
24220 //GDS_PERFCOUNTER1_LO
24221 #define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
24222 #define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
24223 //GDS_PERFCOUNTER1_HI
24224 #define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
24225 #define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
24226 //GDS_PERFCOUNTER2_LO
24227 #define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
24228 #define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
24229 //GDS_PERFCOUNTER2_HI
24230 #define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
24231 #define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
24232 //GDS_PERFCOUNTER3_LO
24233 #define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
24234 #define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
24235 //GDS_PERFCOUNTER3_HI
24236 #define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
24237 #define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
24238 //TA_PERFCOUNTER0_LO
24239 #define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
24240 #define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
24241 //TA_PERFCOUNTER0_HI
24242 #define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
24243 #define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
24244 //TA_PERFCOUNTER1_LO
24245 #define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
24246 #define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
24247 //TA_PERFCOUNTER1_HI
24248 #define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
24249 #define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
24250 //TD_PERFCOUNTER0_LO
24251 #define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
24252 #define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
24253 //TD_PERFCOUNTER0_HI
24254 #define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
24255 #define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
24256 //TD_PERFCOUNTER1_LO
24257 #define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
24258 #define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
24259 //TD_PERFCOUNTER1_HI
24260 #define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
24261 #define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
24262 //TCP_PERFCOUNTER0_LO
24263 #define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
24264 #define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
24265 //TCP_PERFCOUNTER0_HI
24266 #define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
24267 #define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
24268 //TCP_PERFCOUNTER1_LO
24269 #define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
24270 #define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
24271 //TCP_PERFCOUNTER1_HI
24272 #define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
24273 #define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
24274 //TCP_PERFCOUNTER2_LO
24275 #define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
24276 #define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
24277 //TCP_PERFCOUNTER2_HI
24278 #define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
24279 #define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
24280 //TCP_PERFCOUNTER3_LO
24281 #define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
24282 #define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
24283 //TCP_PERFCOUNTER3_HI
24284 #define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
24285 #define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
24286 //TCC_PERFCOUNTER0_LO
24287 #define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
24288 #define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
24289 //TCC_PERFCOUNTER0_HI
24290 #define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
24291 #define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
24292 //TCC_PERFCOUNTER1_LO
24293 #define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
24294 #define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
24295 //TCC_PERFCOUNTER1_HI
24296 #define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
24297 #define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
24298 //TCC_PERFCOUNTER2_LO
24299 #define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
24300 #define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
24301 //TCC_PERFCOUNTER2_HI
24302 #define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
24303 #define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
24304 //TCC_PERFCOUNTER3_LO
24305 #define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
24306 #define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
24307 //TCC_PERFCOUNTER3_HI
24308 #define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
24309 #define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
24310 //TCA_PERFCOUNTER0_LO
24311 #define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
24312 #define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
24313 //TCA_PERFCOUNTER0_HI
24314 #define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
24315 #define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
24316 //TCA_PERFCOUNTER1_LO
24317 #define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
24318 #define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
24319 //TCA_PERFCOUNTER1_HI
24320 #define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
24321 #define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
24322 //TCA_PERFCOUNTER2_LO
24323 #define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
24324 #define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
24325 //TCA_PERFCOUNTER2_HI
24326 #define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
24327 #define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
24328 //TCA_PERFCOUNTER3_LO
24329 #define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
24330 #define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
24331 //TCA_PERFCOUNTER3_HI
24332 #define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
24333 #define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
24334 //CB_PERFCOUNTER0_LO
24335 #define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
24336 #define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
24337 //CB_PERFCOUNTER0_HI
24338 #define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
24339 #define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
24340 //CB_PERFCOUNTER1_LO
24341 #define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
24342 #define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
24343 //CB_PERFCOUNTER1_HI
24344 #define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
24345 #define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
24346 //CB_PERFCOUNTER2_LO
24347 #define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
24348 #define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
24349 //CB_PERFCOUNTER2_HI
24350 #define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
24351 #define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
24352 //CB_PERFCOUNTER3_LO
24353 #define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
24354 #define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
24355 //CB_PERFCOUNTER3_HI
24356 #define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
24357 #define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
24358 //DB_PERFCOUNTER0_LO
24359 #define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
24360 #define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
24361 //DB_PERFCOUNTER0_HI
24362 #define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
24363 #define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
24364 //DB_PERFCOUNTER1_LO
24365 #define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
24366 #define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
24367 //DB_PERFCOUNTER1_HI
24368 #define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
24369 #define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
24370 //DB_PERFCOUNTER2_LO
24371 #define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
24372 #define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
24373 //DB_PERFCOUNTER2_HI
24374 #define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
24375 #define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
24376 //DB_PERFCOUNTER3_LO
24377 #define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
24378 #define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
24379 //DB_PERFCOUNTER3_HI
24380 #define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
24381 #define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
24382 //RLC_PERFCOUNTER0_LO
24383 #define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
24384 #define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
24385 //RLC_PERFCOUNTER0_HI
24386 #define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
24387 #define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
24388 //RLC_PERFCOUNTER1_LO
24389 #define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
24390 #define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
24391 //RLC_PERFCOUNTER1_HI
24392 #define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
24393 #define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
24394 //RMI_PERFCOUNTER0_LO
24395 #define RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
24396 #define RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
24397 //RMI_PERFCOUNTER0_HI
24398 #define RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
24399 #define RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
24400 //RMI_PERFCOUNTER1_LO
24401 #define RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
24402 #define RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
24403 //RMI_PERFCOUNTER1_HI
24404 #define RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
24405 #define RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
24406 //RMI_PERFCOUNTER2_LO
24407 #define RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
24408 #define RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
24409 //RMI_PERFCOUNTER2_HI
24410 #define RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
24411 #define RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
24412 //RMI_PERFCOUNTER3_LO
24413 #define RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
24414 #define RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
24415 //RMI_PERFCOUNTER3_HI
24416 #define RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
24417 #define RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
24418 
24419 
24420 // addressBlock: xcd0_gc_utcl2_atcl2pfcntrdec
24421 //ATC_L2_PERFCOUNTER_LO
24422 #define ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                              0x0
24423 #define ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                0xFFFFFFFFL
24424 //ATC_L2_PERFCOUNTER_HI
24425 #define ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                              0x0
24426 #define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                           0x10
24427 #define ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                0x0000FFFFL
24428 #define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                             0xFFFF0000L
24429 
24430 
24431 // addressBlock: xcd0_gc_utcl2_vml2prdec
24432 //MC_VM_L2_PERFCOUNTER_LO
24433 #define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                            0x0
24434 #define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK                                                              0xFFFFFFFFL
24435 //MC_VM_L2_PERFCOUNTER_HI
24436 #define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                            0x0
24437 #define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                         0x10
24438 #define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK                                                              0x0000FFFFL
24439 #define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                           0xFFFF0000L
24440 
24441 
24442 // addressBlock: xcd0_gc_utcl2_l2tlbprdec
24443 //L2TLB_PERFCOUNTER_LO
24444 #define L2TLB_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                               0x0
24445 #define L2TLB_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                 0xFFFFFFFFL
24446 //L2TLB_PERFCOUNTER_HI
24447 #define L2TLB_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                               0x0
24448 #define L2TLB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                            0x10
24449 #define L2TLB_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                 0x0000FFFFL
24450 #define L2TLB_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                              0xFFFF0000L
24451 
24452 
24453 // addressBlock: xcd0_gc_perfsdec
24454 //CPG_PERFCOUNTER1_SELECT
24455 #define CPG_PERFCOUNTER1_SELECT__CNTR_SEL0__SHIFT                                                             0x0
24456 #define CPG_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT                                                             0xa
24457 #define CPG_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT                                                              0x14
24458 #define CPG_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT                                                            0x18
24459 #define CPG_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT                                                            0x1c
24460 #define CPG_PERFCOUNTER1_SELECT__CNTR_SEL0_MASK                                                               0x000003FFL
24461 #define CPG_PERFCOUNTER1_SELECT__CNTR_SEL1_MASK                                                               0x000FFC00L
24462 #define CPG_PERFCOUNTER1_SELECT__SPM_MODE_MASK                                                                0x00F00000L
24463 #define CPG_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK                                                              0x0F000000L
24464 #define CPG_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK                                                              0xF0000000L
24465 //CPG_PERFCOUNTER0_SELECT1
24466 #define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL2__SHIFT                                                            0x0
24467 #define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT                                                            0xa
24468 #define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT                                                           0x18
24469 #define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT                                                           0x1c
24470 #define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL2_MASK                                                              0x000003FFL
24471 #define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL3_MASK                                                              0x000FFC00L
24472 #define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK                                                             0x0F000000L
24473 #define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK                                                             0xF0000000L
24474 //CPG_PERFCOUNTER0_SELECT
24475 #define CPG_PERFCOUNTER0_SELECT__CNTR_SEL0__SHIFT                                                             0x0
24476 #define CPG_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT                                                             0xa
24477 #define CPG_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT                                                              0x14
24478 #define CPG_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT                                                            0x18
24479 #define CPG_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT                                                            0x1c
24480 #define CPG_PERFCOUNTER0_SELECT__CNTR_SEL0_MASK                                                               0x000003FFL
24481 #define CPG_PERFCOUNTER0_SELECT__CNTR_SEL1_MASK                                                               0x000FFC00L
24482 #define CPG_PERFCOUNTER0_SELECT__SPM_MODE_MASK                                                                0x00F00000L
24483 #define CPG_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK                                                              0x0F000000L
24484 #define CPG_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK                                                              0xF0000000L
24485 //CPC_PERFCOUNTER1_SELECT
24486 #define CPC_PERFCOUNTER1_SELECT__CNTR_SEL0__SHIFT                                                             0x0
24487 #define CPC_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT                                                              0x14
24488 #define CPC_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT                                                            0x1c
24489 #define CPC_PERFCOUNTER1_SELECT__CNTR_SEL0_MASK                                                               0x000003FFL
24490 #define CPC_PERFCOUNTER1_SELECT__SPM_MODE_MASK                                                                0x00F00000L
24491 #define CPC_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK                                                              0xF0000000L
24492 //CPC_PERFCOUNTER0_SELECT1
24493 #define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL2__SHIFT                                                            0x0
24494 #define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT                                                            0xa
24495 #define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT                                                           0x18
24496 #define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT                                                           0x1c
24497 #define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL2_MASK                                                              0x000003FFL
24498 #define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL3_MASK                                                              0x000FFC00L
24499 #define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK                                                             0x0F000000L
24500 #define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK                                                             0xF0000000L
24501 //CPF_PERFCOUNTER1_SELECT
24502 #define CPF_PERFCOUNTER1_SELECT__CNTR_SEL0__SHIFT                                                             0x0
24503 #define CPF_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT                                                             0xa
24504 #define CPF_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT                                                              0x14
24505 #define CPF_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT                                                            0x18
24506 #define CPF_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT                                                            0x1c
24507 #define CPF_PERFCOUNTER1_SELECT__CNTR_SEL0_MASK                                                               0x000003FFL
24508 #define CPF_PERFCOUNTER1_SELECT__CNTR_SEL1_MASK                                                               0x000FFC00L
24509 #define CPF_PERFCOUNTER1_SELECT__SPM_MODE_MASK                                                                0x00F00000L
24510 #define CPF_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK                                                              0x0F000000L
24511 #define CPF_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK                                                              0xF0000000L
24512 //CPF_PERFCOUNTER0_SELECT1
24513 #define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL2__SHIFT                                                            0x0
24514 #define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT                                                            0xa
24515 #define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT                                                           0x18
24516 #define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT                                                           0x1c
24517 #define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL2_MASK                                                              0x000003FFL
24518 #define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL3_MASK                                                              0x000FFC00L
24519 #define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK                                                             0x0F000000L
24520 #define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK                                                             0xF0000000L
24521 //CPF_PERFCOUNTER0_SELECT
24522 #define CPF_PERFCOUNTER0_SELECT__CNTR_SEL0__SHIFT                                                             0x0
24523 #define CPF_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT                                                             0xa
24524 #define CPF_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT                                                              0x14
24525 #define CPF_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT                                                            0x18
24526 #define CPF_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT                                                            0x1c
24527 #define CPF_PERFCOUNTER0_SELECT__CNTR_SEL0_MASK                                                               0x000003FFL
24528 #define CPF_PERFCOUNTER0_SELECT__CNTR_SEL1_MASK                                                               0x000FFC00L
24529 #define CPF_PERFCOUNTER0_SELECT__SPM_MODE_MASK                                                                0x00F00000L
24530 #define CPF_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK                                                              0x0F000000L
24531 #define CPF_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK                                                              0xF0000000L
24532 //CP_PERFMON_CNTL
24533 #define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                                 0x0
24534 #define CP_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT                                                             0x4
24535 #define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT                                                           0x8
24536 #define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT                                                         0xa
24537 #define CP_PERFMON_CNTL__PERFMON_STATE_MASK                                                                   0x0000000FL
24538 #define CP_PERFMON_CNTL__SPM_PERFMON_STATE_MASK                                                               0x000000F0L
24539 #define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK                                                             0x00000300L
24540 #define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK                                                           0x00000400L
24541 //CPC_PERFCOUNTER0_SELECT
24542 #define CPC_PERFCOUNTER0_SELECT__CNTR_SEL0__SHIFT                                                             0x0
24543 #define CPC_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT                                                             0xa
24544 #define CPC_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT                                                              0x14
24545 #define CPC_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT                                                            0x18
24546 #define CPC_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT                                                            0x1c
24547 #define CPC_PERFCOUNTER0_SELECT__CNTR_SEL0_MASK                                                               0x000003FFL
24548 #define CPC_PERFCOUNTER0_SELECT__CNTR_SEL1_MASK                                                               0x000FFC00L
24549 #define CPC_PERFCOUNTER0_SELECT__SPM_MODE_MASK                                                                0x00F00000L
24550 #define CPC_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK                                                              0x0F000000L
24551 #define CPC_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK                                                              0xF0000000L
24552 //CPF_TC_PERF_COUNTER_WINDOW_SELECT
24553 #define CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT                                                       0x0
24554 #define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT                                                      0x1e
24555 #define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT                                                      0x1f
24556 #define CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK                                                         0x00000007L
24557 #define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK                                                        0x40000000L
24558 #define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK                                                        0x80000000L
24559 //CPG_TC_PERF_COUNTER_WINDOW_SELECT
24560 #define CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT                                                       0x0
24561 #define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT                                                      0x1e
24562 #define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT                                                      0x1f
24563 #define CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK                                                         0x0000001FL
24564 #define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK                                                        0x40000000L
24565 #define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK                                                        0x80000000L
24566 //CPF_LATENCY_STATS_SELECT
24567 #define CPF_LATENCY_STATS_SELECT__INDEX__SHIFT                                                                0x0
24568 #define CPF_LATENCY_STATS_SELECT__CLEAR__SHIFT                                                                0x1e
24569 #define CPF_LATENCY_STATS_SELECT__ENABLE__SHIFT                                                               0x1f
24570 #define CPF_LATENCY_STATS_SELECT__INDEX_MASK                                                                  0x0000000FL
24571 #define CPF_LATENCY_STATS_SELECT__CLEAR_MASK                                                                  0x40000000L
24572 #define CPF_LATENCY_STATS_SELECT__ENABLE_MASK                                                                 0x80000000L
24573 //CPG_LATENCY_STATS_SELECT
24574 #define CPG_LATENCY_STATS_SELECT__INDEX__SHIFT                                                                0x0
24575 #define CPG_LATENCY_STATS_SELECT__CLEAR__SHIFT                                                                0x1e
24576 #define CPG_LATENCY_STATS_SELECT__ENABLE__SHIFT                                                               0x1f
24577 #define CPG_LATENCY_STATS_SELECT__INDEX_MASK                                                                  0x0000001FL
24578 #define CPG_LATENCY_STATS_SELECT__CLEAR_MASK                                                                  0x40000000L
24579 #define CPG_LATENCY_STATS_SELECT__ENABLE_MASK                                                                 0x80000000L
24580 //CPC_LATENCY_STATS_SELECT
24581 #define CPC_LATENCY_STATS_SELECT__INDEX__SHIFT                                                                0x0
24582 #define CPC_LATENCY_STATS_SELECT__CLEAR__SHIFT                                                                0x1e
24583 #define CPC_LATENCY_STATS_SELECT__ENABLE__SHIFT                                                               0x1f
24584 #define CPC_LATENCY_STATS_SELECT__INDEX_MASK                                                                  0x00000007L
24585 #define CPC_LATENCY_STATS_SELECT__CLEAR_MASK                                                                  0x40000000L
24586 #define CPC_LATENCY_STATS_SELECT__ENABLE_MASK                                                                 0x80000000L
24587 //CP_DRAW_OBJECT
24588 #define CP_DRAW_OBJECT__OBJECT__SHIFT                                                                         0x0
24589 #define CP_DRAW_OBJECT__OBJECT_MASK                                                                           0xFFFFFFFFL
24590 //CP_DRAW_OBJECT_COUNTER
24591 #define CP_DRAW_OBJECT_COUNTER__COUNT__SHIFT                                                                  0x0
24592 #define CP_DRAW_OBJECT_COUNTER__COUNT_MASK                                                                    0x0000FFFFL
24593 //CP_DRAW_WINDOW_MASK_HI
24594 #define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI__SHIFT                                                         0x0
24595 #define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI_MASK                                                           0xFFFFFFFFL
24596 //CP_DRAW_WINDOW_HI
24597 #define CP_DRAW_WINDOW_HI__WINDOW_HI__SHIFT                                                                   0x0
24598 #define CP_DRAW_WINDOW_HI__WINDOW_HI_MASK                                                                     0xFFFFFFFFL
24599 //CP_DRAW_WINDOW_LO
24600 #define CP_DRAW_WINDOW_LO__MIN__SHIFT                                                                         0x0
24601 #define CP_DRAW_WINDOW_LO__MAX__SHIFT                                                                         0x10
24602 #define CP_DRAW_WINDOW_LO__MIN_MASK                                                                           0x0000FFFFL
24603 #define CP_DRAW_WINDOW_LO__MAX_MASK                                                                           0xFFFF0000L
24604 //CP_DRAW_WINDOW_CNTL
24605 #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX__SHIFT                                                0x0
24606 #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN__SHIFT                                                0x1
24607 #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI__SHIFT                                                    0x2
24608 #define CP_DRAW_WINDOW_CNTL__MODE__SHIFT                                                                      0x8
24609 #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX_MASK                                                  0x00000001L
24610 #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN_MASK                                                  0x00000002L
24611 #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI_MASK                                                      0x00000004L
24612 #define CP_DRAW_WINDOW_CNTL__MODE_MASK                                                                        0x00000100L
24613 //GRBM_PERFCOUNTER0_SELECT
24614 #define GRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                             0x0
24615 #define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT                                           0xa
24616 #define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT                                           0xb
24617 #define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT                                           0xc
24618 #define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT                                            0xd
24619 #define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT                                            0xe
24620 #define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT                                           0x10
24621 #define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT                                            0x11
24622 #define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT                                            0x12
24623 #define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT                                          0x13
24624 #define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT                                            0x14
24625 #define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT                                            0x15
24626 #define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT                                            0x16
24627 #define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT                                            0x17
24628 #define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT                                           0x18
24629 #define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT                                           0x19
24630 #define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT                                           0x1a
24631 #define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT                                            0x1b
24632 #define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT                                            0x1c
24633 #define GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT                                         0x1d
24634 #define GRBM_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT                                            0x1e
24635 #define GRBM_PERFCOUNTER0_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT                                           0x1f
24636 #define GRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                               0x0000003FL
24637 #define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK                                             0x00000400L
24638 #define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK                                             0x00000800L
24639 #define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK                                             0x00001000L
24640 #define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK                                              0x00002000L
24641 #define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK                                              0x00004000L
24642 #define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK                                             0x00010000L
24643 #define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK                                              0x00020000L
24644 #define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK                                              0x00040000L
24645 #define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK                                            0x00080000L
24646 #define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK                                              0x00100000L
24647 #define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK                                              0x00200000L
24648 #define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK                                              0x00400000L
24649 #define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK                                              0x00800000L
24650 #define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK                                             0x01000000L
24651 #define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK                                             0x02000000L
24652 #define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK                                             0x04000000L
24653 #define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK                                              0x08000000L
24654 #define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK                                              0x10000000L
24655 #define GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK                                           0x20000000L
24656 #define GRBM_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK                                              0x40000000L
24657 #define GRBM_PERFCOUNTER0_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK                                             0x80000000L
24658 //GRBM_PERFCOUNTER1_SELECT
24659 #define GRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                             0x0
24660 #define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT                                           0xa
24661 #define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT                                           0xb
24662 #define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT                                           0xc
24663 #define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT                                            0xd
24664 #define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT                                            0xe
24665 #define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT                                           0x10
24666 #define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT                                            0x11
24667 #define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT                                            0x12
24668 #define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT                                          0x13
24669 #define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT                                            0x14
24670 #define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT                                            0x15
24671 #define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT                                            0x16
24672 #define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT                                            0x17
24673 #define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT                                           0x18
24674 #define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT                                           0x19
24675 #define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT                                           0x1a
24676 #define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT                                            0x1b
24677 #define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT                                            0x1c
24678 #define GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT                                         0x1d
24679 #define GRBM_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT                                            0x1e
24680 #define GRBM_PERFCOUNTER1_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT                                           0x1f
24681 #define GRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                               0x0000003FL
24682 #define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK                                             0x00000400L
24683 #define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK                                             0x00000800L
24684 #define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK                                             0x00001000L
24685 #define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK                                              0x00002000L
24686 #define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK                                              0x00004000L
24687 #define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK                                             0x00010000L
24688 #define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK                                              0x00020000L
24689 #define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK                                              0x00040000L
24690 #define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK                                            0x00080000L
24691 #define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK                                              0x00100000L
24692 #define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK                                              0x00200000L
24693 #define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK                                              0x00400000L
24694 #define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK                                              0x00800000L
24695 #define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK                                             0x01000000L
24696 #define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK                                             0x02000000L
24697 #define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK                                             0x04000000L
24698 #define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK                                              0x08000000L
24699 #define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK                                              0x10000000L
24700 #define GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK                                           0x20000000L
24701 #define GRBM_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK                                              0x40000000L
24702 #define GRBM_PERFCOUNTER1_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK                                             0x80000000L
24703 //GRBM_SE0_PERFCOUNTER_SELECT
24704 #define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL__SHIFT                                                          0x0
24705 #define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT                                        0xa
24706 #define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT                                        0xb
24707 #define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT                                         0xc
24708 #define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT                                         0xd
24709 #define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT                                        0xf
24710 #define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT                                         0x10
24711 #define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT                                         0x11
24712 #define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT                                         0x12
24713 #define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT                                        0x13
24714 #define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT                                         0x14
24715 #define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT                                        0x15
24716 #define GRBM_SE0_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT                                        0x16
24717 #define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK                                                            0x0000003FL
24718 #define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK                                          0x00000400L
24719 #define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK                                          0x00000800L
24720 #define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK                                           0x00001000L
24721 #define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK                                           0x00002000L
24722 #define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK                                          0x00008000L
24723 #define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK                                           0x00010000L
24724 #define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK                                           0x00020000L
24725 #define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK                                           0x00040000L
24726 #define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK                                          0x00080000L
24727 #define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK                                           0x00100000L
24728 #define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK                                          0x00200000L
24729 #define GRBM_SE0_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK                                          0x00400000L
24730 //GRBM_SE1_PERFCOUNTER_SELECT
24731 #define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL__SHIFT                                                          0x0
24732 #define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT                                        0xa
24733 #define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT                                        0xb
24734 #define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT                                         0xc
24735 #define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT                                         0xd
24736 #define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT                                        0xf
24737 #define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT                                         0x10
24738 #define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT                                         0x11
24739 #define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT                                         0x12
24740 #define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT                                        0x13
24741 #define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT                                         0x14
24742 #define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT                                        0x15
24743 #define GRBM_SE1_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT                                        0x16
24744 #define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL_MASK                                                            0x0000003FL
24745 #define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK                                          0x00000400L
24746 #define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK                                          0x00000800L
24747 #define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK                                           0x00001000L
24748 #define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK                                           0x00002000L
24749 #define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK                                          0x00008000L
24750 #define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK                                           0x00010000L
24751 #define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK                                           0x00020000L
24752 #define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK                                           0x00040000L
24753 #define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK                                          0x00080000L
24754 #define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK                                           0x00100000L
24755 #define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK                                          0x00200000L
24756 #define GRBM_SE1_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK                                          0x00400000L
24757 //GRBM_SE2_PERFCOUNTER_SELECT
24758 #define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL__SHIFT                                                          0x0
24759 #define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT                                        0xa
24760 #define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT                                        0xb
24761 #define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT                                         0xc
24762 #define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT                                         0xd
24763 #define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT                                        0xf
24764 #define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT                                         0x10
24765 #define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT                                         0x11
24766 #define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT                                         0x12
24767 #define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT                                        0x13
24768 #define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT                                         0x14
24769 #define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT                                        0x15
24770 #define GRBM_SE2_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT                                        0x16
24771 #define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL_MASK                                                            0x0000003FL
24772 #define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK                                          0x00000400L
24773 #define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK                                          0x00000800L
24774 #define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK                                           0x00001000L
24775 #define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK                                           0x00002000L
24776 #define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK                                          0x00008000L
24777 #define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK                                           0x00010000L
24778 #define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK                                           0x00020000L
24779 #define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK                                           0x00040000L
24780 #define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK                                          0x00080000L
24781 #define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK                                           0x00100000L
24782 #define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK                                          0x00200000L
24783 #define GRBM_SE2_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK                                          0x00400000L
24784 //GRBM_SE3_PERFCOUNTER_SELECT
24785 #define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL__SHIFT                                                          0x0
24786 #define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT                                        0xa
24787 #define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT                                        0xb
24788 #define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT                                         0xc
24789 #define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT                                         0xd
24790 #define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT                                        0xf
24791 #define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT                                         0x10
24792 #define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT                                         0x11
24793 #define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT                                         0x12
24794 #define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT                                        0x13
24795 #define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT                                         0x14
24796 #define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT                                        0x15
24797 #define GRBM_SE3_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT                                        0x16
24798 #define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL_MASK                                                            0x0000003FL
24799 #define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK                                          0x00000400L
24800 #define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK                                          0x00000800L
24801 #define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK                                           0x00001000L
24802 #define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK                                           0x00002000L
24803 #define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK                                          0x00008000L
24804 #define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK                                           0x00010000L
24805 #define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK                                           0x00020000L
24806 #define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK                                           0x00040000L
24807 #define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK                                          0x00080000L
24808 #define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK                                           0x00100000L
24809 #define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK                                          0x00200000L
24810 #define GRBM_SE3_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK                                          0x00400000L
24811 //WD_PERFCOUNTER0_SELECT
24812 #define WD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                               0x0
24813 #define WD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                              0x1c
24814 #define WD_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                 0x000000FFL
24815 #define WD_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                                0xF0000000L
24816 //WD_PERFCOUNTER1_SELECT
24817 #define WD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                               0x0
24818 #define WD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                              0x1c
24819 #define WD_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                 0x000000FFL
24820 #define WD_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                                0xF0000000L
24821 //WD_PERFCOUNTER2_SELECT
24822 #define WD_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                               0x0
24823 #define WD_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                              0x1c
24824 #define WD_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                                 0x000000FFL
24825 #define WD_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                                0xF0000000L
24826 //WD_PERFCOUNTER3_SELECT
24827 #define WD_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                               0x0
24828 #define WD_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                              0x1c
24829 #define WD_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                                 0x000000FFL
24830 #define WD_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                                0xF0000000L
24831 //IA_PERFCOUNTER0_SELECT
24832 #define IA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                               0x0
24833 #define IA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                              0xa
24834 #define IA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                              0x14
24835 #define IA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                             0x18
24836 #define IA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                              0x1c
24837 #define IA_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                 0x000003FFL
24838 #define IA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                                0x000FFC00L
24839 #define IA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
24840 #define IA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                               0x0F000000L
24841 #define IA_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                                0xF0000000L
24842 //IA_PERFCOUNTER1_SELECT
24843 #define IA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                               0x0
24844 #define IA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                              0x1c
24845 #define IA_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                 0x000000FFL
24846 #define IA_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                                0xF0000000L
24847 //IA_PERFCOUNTER2_SELECT
24848 #define IA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                               0x0
24849 #define IA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                              0x1c
24850 #define IA_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                                 0x000000FFL
24851 #define IA_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                                0xF0000000L
24852 //IA_PERFCOUNTER3_SELECT
24853 #define IA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                               0x0
24854 #define IA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                              0x1c
24855 #define IA_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                                 0x000000FFL
24856 #define IA_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                                0xF0000000L
24857 //IA_PERFCOUNTER0_SELECT1
24858 #define IA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                             0x0
24859 #define IA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                             0xa
24860 #define IA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                            0x18
24861 #define IA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                            0x1c
24862 #define IA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                               0x000003FFL
24863 #define IA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                               0x000FFC00L
24864 #define IA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                              0x0F000000L
24865 #define IA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                              0xF0000000L
24866 //VGT_PERFCOUNTER0_SELECT
24867 #define VGT_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                              0x0
24868 #define VGT_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                             0xa
24869 #define VGT_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                             0x14
24870 #define VGT_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                            0x18
24871 #define VGT_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                             0x1c
24872 #define VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                0x000003FFL
24873 #define VGT_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
24874 #define VGT_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
24875 #define VGT_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
24876 #define VGT_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                               0xF0000000L
24877 //VGT_PERFCOUNTER1_SELECT
24878 #define VGT_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                              0x0
24879 #define VGT_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                             0xa
24880 #define VGT_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                             0x14
24881 #define VGT_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT                                                            0x18
24882 #define VGT_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                             0x1c
24883 #define VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                0x000003FFL
24884 #define VGT_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
24885 #define VGT_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
24886 #define VGT_PERFCOUNTER1_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
24887 #define VGT_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                               0xF0000000L
24888 //VGT_PERFCOUNTER2_SELECT
24889 #define VGT_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                              0x0
24890 #define VGT_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                             0x1c
24891 #define VGT_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                                0x000000FFL
24892 #define VGT_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                               0xF0000000L
24893 //VGT_PERFCOUNTER3_SELECT
24894 #define VGT_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                              0x0
24895 #define VGT_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                             0x1c
24896 #define VGT_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                                0x000000FFL
24897 #define VGT_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                               0xF0000000L
24898 //VGT_PERFCOUNTER0_SELECT1
24899 #define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                            0x0
24900 #define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                            0xa
24901 #define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                           0x18
24902 #define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                           0x1c
24903 #define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
24904 #define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
24905 #define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                             0x0F000000L
24906 #define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                             0xF0000000L
24907 //VGT_PERFCOUNTER1_SELECT1
24908 #define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT                                                            0x0
24909 #define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT                                                            0xa
24910 #define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT                                                           0x18
24911 #define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT                                                           0x1c
24912 #define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
24913 #define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
24914 #define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK                                                             0x0F000000L
24915 #define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK                                                             0xF0000000L
24916 //VGT_PERFCOUNTER_SEID_MASK
24917 #define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK__SHIFT                                               0x0
24918 #define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK_MASK                                                 0x000000FFL
24919 //PA_SU_PERFCOUNTER0_SELECT
24920 #define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                            0x0
24921 #define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                           0xa
24922 #define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                           0x14
24923 #define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                          0x18
24924 #define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                           0x1c
24925 #define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                              0x000003FFL
24926 #define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                             0x000FFC00L
24927 #define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                             0x00F00000L
24928 #define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                            0x0F000000L
24929 #define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                             0xF0000000L
24930 //PA_SU_PERFCOUNTER0_SELECT1
24931 #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                          0x0
24932 #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                          0xa
24933 #define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                         0x18
24934 #define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                         0x1c
24935 #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                            0x000003FFL
24936 #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                            0x000FFC00L
24937 #define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                           0x0F000000L
24938 #define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                           0xF0000000L
24939 //PA_SU_PERFCOUNTER1_SELECT
24940 #define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                            0x0
24941 #define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                           0xa
24942 #define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                           0x14
24943 #define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT                                                          0x18
24944 #define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                           0x1c
24945 #define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                              0x000003FFL
24946 #define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                             0x000FFC00L
24947 #define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                             0x00F00000L
24948 #define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE1_MASK                                                            0x0F000000L
24949 #define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                             0xF0000000L
24950 //PA_SU_PERFCOUNTER1_SELECT1
24951 #define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT                                                          0x0
24952 #define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT                                                          0xa
24953 #define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT                                                         0x18
24954 #define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT                                                         0x1c
24955 #define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK                                                            0x000003FFL
24956 #define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK                                                            0x000FFC00L
24957 #define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK                                                           0x0F000000L
24958 #define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK                                                           0xF0000000L
24959 //PA_SU_PERFCOUNTER2_SELECT
24960 #define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                            0x0
24961 #define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                           0x14
24962 #define PA_SU_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                           0x1c
24963 #define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                              0x000003FFL
24964 #define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                             0x00F00000L
24965 #define PA_SU_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                             0xF0000000L
24966 //PA_SU_PERFCOUNTER3_SELECT
24967 #define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                            0x0
24968 #define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT                                                           0x14
24969 #define PA_SU_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                           0x1c
24970 #define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                              0x000003FFL
24971 #define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE_MASK                                                             0x00F00000L
24972 #define PA_SU_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                             0xF0000000L
24973 //PA_SC_PERFCOUNTER0_SELECT
24974 #define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                            0x0
24975 #define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                           0xa
24976 #define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                           0x14
24977 #define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                          0x18
24978 #define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                           0x1c
24979 #define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                              0x000003FFL
24980 #define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                             0x000FFC00L
24981 #define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                             0x00F00000L
24982 #define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                            0x0F000000L
24983 #define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                             0xF0000000L
24984 //PA_SC_PERFCOUNTER0_SELECT1
24985 #define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                          0x0
24986 #define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                          0xa
24987 #define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                         0x18
24988 #define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                         0x1c
24989 #define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                            0x000003FFL
24990 #define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                            0x000FFC00L
24991 #define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                           0x0F000000L
24992 #define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                           0xF0000000L
24993 //PA_SC_PERFCOUNTER1_SELECT
24994 #define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                            0x0
24995 #define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                              0x000003FFL
24996 //PA_SC_PERFCOUNTER2_SELECT
24997 #define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                            0x0
24998 #define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                              0x000003FFL
24999 //PA_SC_PERFCOUNTER3_SELECT
25000 #define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                            0x0
25001 #define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                              0x000003FFL
25002 //PA_SC_PERFCOUNTER4_SELECT
25003 #define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT                                                            0x0
25004 #define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL_MASK                                                              0x000003FFL
25005 //PA_SC_PERFCOUNTER5_SELECT
25006 #define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT                                                            0x0
25007 #define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL_MASK                                                              0x000003FFL
25008 //PA_SC_PERFCOUNTER6_SELECT
25009 #define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT                                                            0x0
25010 #define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL_MASK                                                              0x000003FFL
25011 //PA_SC_PERFCOUNTER7_SELECT
25012 #define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT                                                            0x0
25013 #define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL_MASK                                                              0x000003FFL
25014 //SPI_PERFCOUNTER0_SELECT
25015 #define SPI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                              0x0
25016 #define SPI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                             0xa
25017 #define SPI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                             0x14
25018 #define SPI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                            0x18
25019 #define SPI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                             0x1c
25020 #define SPI_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                0x000003FFL
25021 #define SPI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
25022 #define SPI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
25023 #define SPI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
25024 #define SPI_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                               0xF0000000L
25025 //SPI_PERFCOUNTER1_SELECT
25026 #define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                              0x0
25027 #define SPI_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                             0xa
25028 #define SPI_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                             0x14
25029 #define SPI_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT                                                            0x18
25030 #define SPI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                             0x1c
25031 #define SPI_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                0x000003FFL
25032 #define SPI_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
25033 #define SPI_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
25034 #define SPI_PERFCOUNTER1_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
25035 #define SPI_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                               0xF0000000L
25036 //SPI_PERFCOUNTER2_SELECT
25037 #define SPI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                              0x0
25038 #define SPI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT                                                             0xa
25039 #define SPI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                             0x14
25040 #define SPI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT                                                            0x18
25041 #define SPI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                             0x1c
25042 #define SPI_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                                0x000003FFL
25043 #define SPI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
25044 #define SPI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
25045 #define SPI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
25046 #define SPI_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                               0xF0000000L
25047 //SPI_PERFCOUNTER3_SELECT
25048 #define SPI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                              0x0
25049 #define SPI_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT                                                             0xa
25050 #define SPI_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT                                                             0x14
25051 #define SPI_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT                                                            0x18
25052 #define SPI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                             0x1c
25053 #define SPI_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                                0x000003FFL
25054 #define SPI_PERFCOUNTER3_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
25055 #define SPI_PERFCOUNTER3_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
25056 #define SPI_PERFCOUNTER3_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
25057 #define SPI_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                               0xF0000000L
25058 //SPI_PERFCOUNTER0_SELECT1
25059 #define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                            0x0
25060 #define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                            0xa
25061 #define SPI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                           0x18
25062 #define SPI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                           0x1c
25063 #define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
25064 #define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
25065 #define SPI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                             0x0F000000L
25066 #define SPI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                             0xF0000000L
25067 //SPI_PERFCOUNTER1_SELECT1
25068 #define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT                                                            0x0
25069 #define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT                                                            0xa
25070 #define SPI_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT                                                           0x18
25071 #define SPI_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT                                                           0x1c
25072 #define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
25073 #define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
25074 #define SPI_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK                                                             0x0F000000L
25075 #define SPI_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK                                                             0xF0000000L
25076 //SPI_PERFCOUNTER2_SELECT1
25077 #define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT                                                            0x0
25078 #define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT                                                            0xa
25079 #define SPI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT                                                           0x18
25080 #define SPI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT                                                           0x1c
25081 #define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
25082 #define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
25083 #define SPI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK                                                             0x0F000000L
25084 #define SPI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK                                                             0xF0000000L
25085 //SPI_PERFCOUNTER3_SELECT1
25086 #define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT                                                            0x0
25087 #define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT                                                            0xa
25088 #define SPI_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT                                                           0x18
25089 #define SPI_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT                                                           0x1c
25090 #define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
25091 #define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
25092 #define SPI_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK                                                             0x0F000000L
25093 #define SPI_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK                                                             0xF0000000L
25094 //SPI_PERFCOUNTER4_SELECT
25095 #define SPI_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT                                                              0x0
25096 #define SPI_PERFCOUNTER4_SELECT__PERF_SEL_MASK                                                                0x000000FFL
25097 //SPI_PERFCOUNTER5_SELECT
25098 #define SPI_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT                                                              0x0
25099 #define SPI_PERFCOUNTER5_SELECT__PERF_SEL_MASK                                                                0x000000FFL
25100 //SPI_PERFCOUNTER_BINS
25101 #define SPI_PERFCOUNTER_BINS__BIN0_MIN__SHIFT                                                                 0x0
25102 #define SPI_PERFCOUNTER_BINS__BIN0_MAX__SHIFT                                                                 0x4
25103 #define SPI_PERFCOUNTER_BINS__BIN1_MIN__SHIFT                                                                 0x8
25104 #define SPI_PERFCOUNTER_BINS__BIN1_MAX__SHIFT                                                                 0xc
25105 #define SPI_PERFCOUNTER_BINS__BIN2_MIN__SHIFT                                                                 0x10
25106 #define SPI_PERFCOUNTER_BINS__BIN2_MAX__SHIFT                                                                 0x14
25107 #define SPI_PERFCOUNTER_BINS__BIN3_MIN__SHIFT                                                                 0x18
25108 #define SPI_PERFCOUNTER_BINS__BIN3_MAX__SHIFT                                                                 0x1c
25109 #define SPI_PERFCOUNTER_BINS__BIN0_MIN_MASK                                                                   0x0000000FL
25110 #define SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK                                                                   0x000000F0L
25111 #define SPI_PERFCOUNTER_BINS__BIN1_MIN_MASK                                                                   0x00000F00L
25112 #define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK                                                                   0x0000F000L
25113 #define SPI_PERFCOUNTER_BINS__BIN2_MIN_MASK                                                                   0x000F0000L
25114 #define SPI_PERFCOUNTER_BINS__BIN2_MAX_MASK                                                                   0x00F00000L
25115 #define SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK                                                                   0x0F000000L
25116 #define SPI_PERFCOUNTER_BINS__BIN3_MAX_MASK                                                                   0xF0000000L
25117 //SQ_PERFCOUNTER0_SELECT
25118 #define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                               0x0
25119 #define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK__SHIFT                                                          0xc
25120 #define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK__SHIFT                                                        0x10
25121 #define SQ_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT                                                               0x14
25122 #define SQ_PERFCOUNTER0_SELECT__SIMD_MASK__SHIFT                                                              0x18
25123 #define SQ_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                              0x1c
25124 #define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
25125 #define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK_MASK                                                            0x0000F000L
25126 #define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK_MASK                                                          0x000F0000L
25127 #define SQ_PERFCOUNTER0_SELECT__SPM_MODE_MASK                                                                 0x00F00000L
25128 #define SQ_PERFCOUNTER0_SELECT__SIMD_MASK_MASK                                                                0x0F000000L
25129 #define SQ_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                                0xF0000000L
25130 //SQ_PERFCOUNTER1_SELECT
25131 #define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                               0x0
25132 #define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK__SHIFT                                                          0xc
25133 #define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK__SHIFT                                                        0x10
25134 #define SQ_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT                                                               0x14
25135 #define SQ_PERFCOUNTER1_SELECT__SIMD_MASK__SHIFT                                                              0x18
25136 #define SQ_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                              0x1c
25137 #define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
25138 #define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK_MASK                                                            0x0000F000L
25139 #define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK_MASK                                                          0x000F0000L
25140 #define SQ_PERFCOUNTER1_SELECT__SPM_MODE_MASK                                                                 0x00F00000L
25141 #define SQ_PERFCOUNTER1_SELECT__SIMD_MASK_MASK                                                                0x0F000000L
25142 #define SQ_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                                0xF0000000L
25143 //SQ_PERFCOUNTER2_SELECT
25144 #define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                               0x0
25145 #define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK__SHIFT                                                          0xc
25146 #define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK__SHIFT                                                        0x10
25147 #define SQ_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT                                                               0x14
25148 #define SQ_PERFCOUNTER2_SELECT__SIMD_MASK__SHIFT                                                              0x18
25149 #define SQ_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                              0x1c
25150 #define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
25151 #define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK_MASK                                                            0x0000F000L
25152 #define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK_MASK                                                          0x000F0000L
25153 #define SQ_PERFCOUNTER2_SELECT__SPM_MODE_MASK                                                                 0x00F00000L
25154 #define SQ_PERFCOUNTER2_SELECT__SIMD_MASK_MASK                                                                0x0F000000L
25155 #define SQ_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                                0xF0000000L
25156 //SQ_PERFCOUNTER3_SELECT
25157 #define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                               0x0
25158 #define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK__SHIFT                                                          0xc
25159 #define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK__SHIFT                                                        0x10
25160 #define SQ_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT                                                               0x14
25161 #define SQ_PERFCOUNTER3_SELECT__SIMD_MASK__SHIFT                                                              0x18
25162 #define SQ_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                              0x1c
25163 #define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
25164 #define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK_MASK                                                            0x0000F000L
25165 #define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK_MASK                                                          0x000F0000L
25166 #define SQ_PERFCOUNTER3_SELECT__SPM_MODE_MASK                                                                 0x00F00000L
25167 #define SQ_PERFCOUNTER3_SELECT__SIMD_MASK_MASK                                                                0x0F000000L
25168 #define SQ_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                                0xF0000000L
25169 //SQ_PERFCOUNTER4_SELECT
25170 #define SQ_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT                                                               0x0
25171 #define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK__SHIFT                                                          0xc
25172 #define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK__SHIFT                                                        0x10
25173 #define SQ_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT                                                               0x14
25174 #define SQ_PERFCOUNTER4_SELECT__SIMD_MASK__SHIFT                                                              0x18
25175 #define SQ_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT                                                              0x1c
25176 #define SQ_PERFCOUNTER4_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
25177 #define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK_MASK                                                            0x0000F000L
25178 #define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK_MASK                                                          0x000F0000L
25179 #define SQ_PERFCOUNTER4_SELECT__SPM_MODE_MASK                                                                 0x00F00000L
25180 #define SQ_PERFCOUNTER4_SELECT__SIMD_MASK_MASK                                                                0x0F000000L
25181 #define SQ_PERFCOUNTER4_SELECT__PERF_MODE_MASK                                                                0xF0000000L
25182 //SQ_PERFCOUNTER5_SELECT
25183 #define SQ_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT                                                               0x0
25184 #define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK__SHIFT                                                          0xc
25185 #define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK__SHIFT                                                        0x10
25186 #define SQ_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT                                                               0x14
25187 #define SQ_PERFCOUNTER5_SELECT__SIMD_MASK__SHIFT                                                              0x18
25188 #define SQ_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT                                                              0x1c
25189 #define SQ_PERFCOUNTER5_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
25190 #define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK_MASK                                                            0x0000F000L
25191 #define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK_MASK                                                          0x000F0000L
25192 #define SQ_PERFCOUNTER5_SELECT__SPM_MODE_MASK                                                                 0x00F00000L
25193 #define SQ_PERFCOUNTER5_SELECT__SIMD_MASK_MASK                                                                0x0F000000L
25194 #define SQ_PERFCOUNTER5_SELECT__PERF_MODE_MASK                                                                0xF0000000L
25195 //SQ_PERFCOUNTER6_SELECT
25196 #define SQ_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT                                                               0x0
25197 #define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK__SHIFT                                                          0xc
25198 #define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK__SHIFT                                                        0x10
25199 #define SQ_PERFCOUNTER6_SELECT__SPM_MODE__SHIFT                                                               0x14
25200 #define SQ_PERFCOUNTER6_SELECT__SIMD_MASK__SHIFT                                                              0x18
25201 #define SQ_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT                                                              0x1c
25202 #define SQ_PERFCOUNTER6_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
25203 #define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK_MASK                                                            0x0000F000L
25204 #define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK_MASK                                                          0x000F0000L
25205 #define SQ_PERFCOUNTER6_SELECT__SPM_MODE_MASK                                                                 0x00F00000L
25206 #define SQ_PERFCOUNTER6_SELECT__SIMD_MASK_MASK                                                                0x0F000000L
25207 #define SQ_PERFCOUNTER6_SELECT__PERF_MODE_MASK                                                                0xF0000000L
25208 //SQ_PERFCOUNTER7_SELECT
25209 #define SQ_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT                                                               0x0
25210 #define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK__SHIFT                                                          0xc
25211 #define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK__SHIFT                                                        0x10
25212 #define SQ_PERFCOUNTER7_SELECT__SPM_MODE__SHIFT                                                               0x14
25213 #define SQ_PERFCOUNTER7_SELECT__SIMD_MASK__SHIFT                                                              0x18
25214 #define SQ_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT                                                              0x1c
25215 #define SQ_PERFCOUNTER7_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
25216 #define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK_MASK                                                            0x0000F000L
25217 #define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK_MASK                                                          0x000F0000L
25218 #define SQ_PERFCOUNTER7_SELECT__SPM_MODE_MASK                                                                 0x00F00000L
25219 #define SQ_PERFCOUNTER7_SELECT__SIMD_MASK_MASK                                                                0x0F000000L
25220 #define SQ_PERFCOUNTER7_SELECT__PERF_MODE_MASK                                                                0xF0000000L
25221 //SQ_PERFCOUNTER8_SELECT
25222 #define SQ_PERFCOUNTER8_SELECT__PERF_SEL__SHIFT                                                               0x0
25223 #define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK__SHIFT                                                          0xc
25224 #define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK__SHIFT                                                        0x10
25225 #define SQ_PERFCOUNTER8_SELECT__SPM_MODE__SHIFT                                                               0x14
25226 #define SQ_PERFCOUNTER8_SELECT__SIMD_MASK__SHIFT                                                              0x18
25227 #define SQ_PERFCOUNTER8_SELECT__PERF_MODE__SHIFT                                                              0x1c
25228 #define SQ_PERFCOUNTER8_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
25229 #define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK_MASK                                                            0x0000F000L
25230 #define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK_MASK                                                          0x000F0000L
25231 #define SQ_PERFCOUNTER8_SELECT__SPM_MODE_MASK                                                                 0x00F00000L
25232 #define SQ_PERFCOUNTER8_SELECT__SIMD_MASK_MASK                                                                0x0F000000L
25233 #define SQ_PERFCOUNTER8_SELECT__PERF_MODE_MASK                                                                0xF0000000L
25234 //SQ_PERFCOUNTER9_SELECT
25235 #define SQ_PERFCOUNTER9_SELECT__PERF_SEL__SHIFT                                                               0x0
25236 #define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK__SHIFT                                                          0xc
25237 #define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK__SHIFT                                                        0x10
25238 #define SQ_PERFCOUNTER9_SELECT__SPM_MODE__SHIFT                                                               0x14
25239 #define SQ_PERFCOUNTER9_SELECT__SIMD_MASK__SHIFT                                                              0x18
25240 #define SQ_PERFCOUNTER9_SELECT__PERF_MODE__SHIFT                                                              0x1c
25241 #define SQ_PERFCOUNTER9_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
25242 #define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK_MASK                                                            0x0000F000L
25243 #define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK_MASK                                                          0x000F0000L
25244 #define SQ_PERFCOUNTER9_SELECT__SPM_MODE_MASK                                                                 0x00F00000L
25245 #define SQ_PERFCOUNTER9_SELECT__SIMD_MASK_MASK                                                                0x0F000000L
25246 #define SQ_PERFCOUNTER9_SELECT__PERF_MODE_MASK                                                                0xF0000000L
25247 //SQ_PERFCOUNTER10_SELECT
25248 #define SQ_PERFCOUNTER10_SELECT__PERF_SEL__SHIFT                                                              0x0
25249 #define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK__SHIFT                                                         0xc
25250 #define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK__SHIFT                                                       0x10
25251 #define SQ_PERFCOUNTER10_SELECT__SPM_MODE__SHIFT                                                              0x14
25252 #define SQ_PERFCOUNTER10_SELECT__SIMD_MASK__SHIFT                                                             0x18
25253 #define SQ_PERFCOUNTER10_SELECT__PERF_MODE__SHIFT                                                             0x1c
25254 #define SQ_PERFCOUNTER10_SELECT__PERF_SEL_MASK                                                                0x000001FFL
25255 #define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK_MASK                                                           0x0000F000L
25256 #define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK_MASK                                                         0x000F0000L
25257 #define SQ_PERFCOUNTER10_SELECT__SPM_MODE_MASK                                                                0x00F00000L
25258 #define SQ_PERFCOUNTER10_SELECT__SIMD_MASK_MASK                                                               0x0F000000L
25259 #define SQ_PERFCOUNTER10_SELECT__PERF_MODE_MASK                                                               0xF0000000L
25260 //SQ_PERFCOUNTER11_SELECT
25261 #define SQ_PERFCOUNTER11_SELECT__PERF_SEL__SHIFT                                                              0x0
25262 #define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK__SHIFT                                                         0xc
25263 #define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK__SHIFT                                                       0x10
25264 #define SQ_PERFCOUNTER11_SELECT__SPM_MODE__SHIFT                                                              0x14
25265 #define SQ_PERFCOUNTER11_SELECT__SIMD_MASK__SHIFT                                                             0x18
25266 #define SQ_PERFCOUNTER11_SELECT__PERF_MODE__SHIFT                                                             0x1c
25267 #define SQ_PERFCOUNTER11_SELECT__PERF_SEL_MASK                                                                0x000001FFL
25268 #define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK_MASK                                                           0x0000F000L
25269 #define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK_MASK                                                         0x000F0000L
25270 #define SQ_PERFCOUNTER11_SELECT__SPM_MODE_MASK                                                                0x00F00000L
25271 #define SQ_PERFCOUNTER11_SELECT__SIMD_MASK_MASK                                                               0x0F000000L
25272 #define SQ_PERFCOUNTER11_SELECT__PERF_MODE_MASK                                                               0xF0000000L
25273 //SQ_PERFCOUNTER12_SELECT
25274 #define SQ_PERFCOUNTER12_SELECT__PERF_SEL__SHIFT                                                              0x0
25275 #define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK__SHIFT                                                         0xc
25276 #define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK__SHIFT                                                       0x10
25277 #define SQ_PERFCOUNTER12_SELECT__SPM_MODE__SHIFT                                                              0x14
25278 #define SQ_PERFCOUNTER12_SELECT__SIMD_MASK__SHIFT                                                             0x18
25279 #define SQ_PERFCOUNTER12_SELECT__PERF_MODE__SHIFT                                                             0x1c
25280 #define SQ_PERFCOUNTER12_SELECT__PERF_SEL_MASK                                                                0x000001FFL
25281 #define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK_MASK                                                           0x0000F000L
25282 #define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK_MASK                                                         0x000F0000L
25283 #define SQ_PERFCOUNTER12_SELECT__SPM_MODE_MASK                                                                0x00F00000L
25284 #define SQ_PERFCOUNTER12_SELECT__SIMD_MASK_MASK                                                               0x0F000000L
25285 #define SQ_PERFCOUNTER12_SELECT__PERF_MODE_MASK                                                               0xF0000000L
25286 //SQ_PERFCOUNTER13_SELECT
25287 #define SQ_PERFCOUNTER13_SELECT__PERF_SEL__SHIFT                                                              0x0
25288 #define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK__SHIFT                                                         0xc
25289 #define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK__SHIFT                                                       0x10
25290 #define SQ_PERFCOUNTER13_SELECT__SPM_MODE__SHIFT                                                              0x14
25291 #define SQ_PERFCOUNTER13_SELECT__SIMD_MASK__SHIFT                                                             0x18
25292 #define SQ_PERFCOUNTER13_SELECT__PERF_MODE__SHIFT                                                             0x1c
25293 #define SQ_PERFCOUNTER13_SELECT__PERF_SEL_MASK                                                                0x000001FFL
25294 #define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK_MASK                                                           0x0000F000L
25295 #define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK_MASK                                                         0x000F0000L
25296 #define SQ_PERFCOUNTER13_SELECT__SPM_MODE_MASK                                                                0x00F00000L
25297 #define SQ_PERFCOUNTER13_SELECT__SIMD_MASK_MASK                                                               0x0F000000L
25298 #define SQ_PERFCOUNTER13_SELECT__PERF_MODE_MASK                                                               0xF0000000L
25299 //SQ_PERFCOUNTER14_SELECT
25300 #define SQ_PERFCOUNTER14_SELECT__PERF_SEL__SHIFT                                                              0x0
25301 #define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK__SHIFT                                                         0xc
25302 #define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK__SHIFT                                                       0x10
25303 #define SQ_PERFCOUNTER14_SELECT__SPM_MODE__SHIFT                                                              0x14
25304 #define SQ_PERFCOUNTER14_SELECT__SIMD_MASK__SHIFT                                                             0x18
25305 #define SQ_PERFCOUNTER14_SELECT__PERF_MODE__SHIFT                                                             0x1c
25306 #define SQ_PERFCOUNTER14_SELECT__PERF_SEL_MASK                                                                0x000001FFL
25307 #define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK_MASK                                                           0x0000F000L
25308 #define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK_MASK                                                         0x000F0000L
25309 #define SQ_PERFCOUNTER14_SELECT__SPM_MODE_MASK                                                                0x00F00000L
25310 #define SQ_PERFCOUNTER14_SELECT__SIMD_MASK_MASK                                                               0x0F000000L
25311 #define SQ_PERFCOUNTER14_SELECT__PERF_MODE_MASK                                                               0xF0000000L
25312 //SQ_PERFCOUNTER15_SELECT
25313 #define SQ_PERFCOUNTER15_SELECT__PERF_SEL__SHIFT                                                              0x0
25314 #define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK__SHIFT                                                         0xc
25315 #define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK__SHIFT                                                       0x10
25316 #define SQ_PERFCOUNTER15_SELECT__SPM_MODE__SHIFT                                                              0x14
25317 #define SQ_PERFCOUNTER15_SELECT__SIMD_MASK__SHIFT                                                             0x18
25318 #define SQ_PERFCOUNTER15_SELECT__PERF_MODE__SHIFT                                                             0x1c
25319 #define SQ_PERFCOUNTER15_SELECT__PERF_SEL_MASK                                                                0x000001FFL
25320 #define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK_MASK                                                           0x0000F000L
25321 #define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK_MASK                                                         0x000F0000L
25322 #define SQ_PERFCOUNTER15_SELECT__SPM_MODE_MASK                                                                0x00F00000L
25323 #define SQ_PERFCOUNTER15_SELECT__SIMD_MASK_MASK                                                               0x0F000000L
25324 #define SQ_PERFCOUNTER15_SELECT__PERF_MODE_MASK                                                               0xF0000000L
25325 //SQ_PERFCOUNTER_CTRL
25326 #define SQ_PERFCOUNTER_CTRL__PS_EN__SHIFT                                                                     0x0
25327 #define SQ_PERFCOUNTER_CTRL__VS_EN__SHIFT                                                                     0x1
25328 #define SQ_PERFCOUNTER_CTRL__GS_EN__SHIFT                                                                     0x2
25329 #define SQ_PERFCOUNTER_CTRL__ES_EN__SHIFT                                                                     0x3
25330 #define SQ_PERFCOUNTER_CTRL__HS_EN__SHIFT                                                                     0x4
25331 #define SQ_PERFCOUNTER_CTRL__LS_EN__SHIFT                                                                     0x5
25332 #define SQ_PERFCOUNTER_CTRL__CS_EN__SHIFT                                                                     0x6
25333 #define SQ_PERFCOUNTER_CTRL__CNTR_RATE__SHIFT                                                                 0x8
25334 #define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH__SHIFT                                                             0xd
25335 #define SQ_PERFCOUNTER_CTRL__VMID_MASK__SHIFT                                                                 0x10
25336 #define SQ_PERFCOUNTER_CTRL__PS_EN_MASK                                                                       0x00000001L
25337 #define SQ_PERFCOUNTER_CTRL__VS_EN_MASK                                                                       0x00000002L
25338 #define SQ_PERFCOUNTER_CTRL__GS_EN_MASK                                                                       0x00000004L
25339 #define SQ_PERFCOUNTER_CTRL__ES_EN_MASK                                                                       0x00000008L
25340 #define SQ_PERFCOUNTER_CTRL__HS_EN_MASK                                                                       0x00000010L
25341 #define SQ_PERFCOUNTER_CTRL__LS_EN_MASK                                                                       0x00000020L
25342 #define SQ_PERFCOUNTER_CTRL__CS_EN_MASK                                                                       0x00000040L
25343 #define SQ_PERFCOUNTER_CTRL__CNTR_RATE_MASK                                                                   0x00001F00L
25344 #define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH_MASK                                                               0x00002000L
25345 #define SQ_PERFCOUNTER_CTRL__VMID_MASK_MASK                                                                   0xFFFF0000L
25346 //SQ_PERFCOUNTER_MASK
25347 #define SQ_PERFCOUNTER_MASK__SH0_MASK__SHIFT                                                                  0x0
25348 #define SQ_PERFCOUNTER_MASK__SH1_MASK__SHIFT                                                                  0x10
25349 #define SQ_PERFCOUNTER_MASK__SH0_MASK_MASK                                                                    0x0000FFFFL
25350 #define SQ_PERFCOUNTER_MASK__SH1_MASK_MASK                                                                    0xFFFF0000L
25351 //SQ_PERFCOUNTER_CTRL2
25352 #define SQ_PERFCOUNTER_CTRL2__FORCE_EN__SHIFT                                                                 0x0
25353 #define SQ_PERFCOUNTER_CTRL2__FORCE_EN_MASK                                                                   0x00000001L
25354 //SX_PERFCOUNTER0_SELECT
25355 #define SX_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                               0x0
25356 #define SX_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                              0xa
25357 #define SX_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                              0x14
25358 #define SX_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                             0x18
25359 #define SX_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                              0x1c
25360 #define SX_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                 0x000003FFL
25361 #define SX_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                                0x000FFC00L
25362 #define SX_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
25363 #define SX_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                               0x0F000000L
25364 #define SX_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                                0xF0000000L
25365 //SX_PERFCOUNTER1_SELECT
25366 #define SX_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                               0x0
25367 #define SX_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                              0xa
25368 #define SX_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                              0x14
25369 #define SX_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT                                                             0x18
25370 #define SX_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                              0x1c
25371 #define SX_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                 0x000003FFL
25372 #define SX_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                                0x000FFC00L
25373 #define SX_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
25374 #define SX_PERFCOUNTER1_SELECT__PERF_MODE1_MASK                                                               0x0F000000L
25375 #define SX_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                                0xF0000000L
25376 //SX_PERFCOUNTER2_SELECT
25377 #define SX_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                               0x0
25378 #define SX_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                              0x14
25379 #define SX_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                              0x1c
25380 #define SX_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                                 0x000003FFL
25381 #define SX_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
25382 #define SX_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                                0xF0000000L
25383 //SX_PERFCOUNTER3_SELECT
25384 #define SX_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                               0x0
25385 #define SX_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT                                                              0x14
25386 #define SX_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                              0x1c
25387 #define SX_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                                 0x000003FFL
25388 #define SX_PERFCOUNTER3_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
25389 #define SX_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                                0xF0000000L
25390 //SX_PERFCOUNTER0_SELECT1
25391 #define SX_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                             0x0
25392 #define SX_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                             0xa
25393 #define SX_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                            0x18
25394 #define SX_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                            0x1c
25395 #define SX_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                               0x000003FFL
25396 #define SX_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                               0x000FFC00L
25397 #define SX_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                              0x0F000000L
25398 #define SX_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                              0xF0000000L
25399 //SX_PERFCOUNTER1_SELECT1
25400 #define SX_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT                                                             0x0
25401 #define SX_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT                                                             0xa
25402 #define SX_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT                                                            0x18
25403 #define SX_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT                                                            0x1c
25404 #define SX_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK                                                               0x000003FFL
25405 #define SX_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK                                                               0x000FFC00L
25406 #define SX_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK                                                              0x0F000000L
25407 #define SX_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK                                                              0xF0000000L
25408 //GDS_PERFCOUNTER0_SELECT
25409 #define GDS_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                              0x0
25410 #define GDS_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                             0xa
25411 #define GDS_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                             0x14
25412 #define GDS_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                            0x18
25413 #define GDS_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                             0x1c
25414 #define GDS_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                0x000003FFL
25415 #define GDS_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
25416 #define GDS_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
25417 #define GDS_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
25418 #define GDS_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                               0xF0000000L
25419 //GDS_PERFCOUNTER1_SELECT
25420 #define GDS_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                              0x0
25421 #define GDS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                             0x14
25422 #define GDS_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                             0x1c
25423 #define GDS_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                0x000003FFL
25424 #define GDS_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
25425 #define GDS_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                               0xF0000000L
25426 //GDS_PERFCOUNTER2_SELECT
25427 #define GDS_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                              0x0
25428 #define GDS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                             0x14
25429 #define GDS_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                             0x1c
25430 #define GDS_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                                0x000003FFL
25431 #define GDS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
25432 #define GDS_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                               0xF0000000L
25433 //GDS_PERFCOUNTER3_SELECT
25434 #define GDS_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                              0x0
25435 #define GDS_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT                                                             0x14
25436 #define GDS_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                             0x1c
25437 #define GDS_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                                0x000003FFL
25438 #define GDS_PERFCOUNTER3_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
25439 #define GDS_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                               0xF0000000L
25440 //GDS_PERFCOUNTER0_SELECT1
25441 #define GDS_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                            0x0
25442 #define GDS_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                            0xa
25443 #define GDS_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                           0x18
25444 #define GDS_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                           0x1c
25445 #define GDS_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
25446 #define GDS_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
25447 #define GDS_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                             0x0F000000L
25448 #define GDS_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                             0xF0000000L
25449 //TA_PERFCOUNTER0_SELECT
25450 #define TA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                               0x0
25451 #define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                              0xa
25452 #define TA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                              0x14
25453 #define TA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                             0x18
25454 #define TA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                              0x1c
25455 #define TA_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                 0x0000007FL
25456 #define TA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                                0x0001FC00L
25457 #define TA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
25458 #define TA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                               0x0F000000L
25459 #define TA_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                                0xF0000000L
25460 //TA_PERFCOUNTER0_SELECT1
25461 #define TA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                             0x0
25462 #define TA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                             0xa
25463 #define TA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                            0x18
25464 #define TA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                            0x1c
25465 #define TA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                               0x0000007FL
25466 #define TA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                               0x0001FC00L
25467 #define TA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                              0x0F000000L
25468 #define TA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                              0xF0000000L
25469 //TA_PERFCOUNTER1_SELECT
25470 #define TA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                               0x0
25471 #define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                              0x14
25472 #define TA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                              0x1c
25473 #define TA_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                 0x0000007FL
25474 #define TA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
25475 #define TA_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                                0xF0000000L
25476 //TD_PERFCOUNTER0_SELECT
25477 #define TD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                               0x0
25478 #define TD_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                              0xa
25479 #define TD_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                              0x14
25480 #define TD_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                             0x18
25481 #define TD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                              0x1c
25482 #define TD_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                 0x0000003FL
25483 #define TD_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                                0x0000FC00L
25484 #define TD_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
25485 #define TD_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                               0x0F000000L
25486 #define TD_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                                0xF0000000L
25487 //TD_PERFCOUNTER0_SELECT1
25488 #define TD_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                             0x0
25489 #define TD_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                             0xa
25490 #define TD_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                            0x18
25491 #define TD_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                            0x1c
25492 #define TD_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                               0x0000003FL
25493 #define TD_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                               0x0000FC00L
25494 #define TD_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                              0x0F000000L
25495 #define TD_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                              0xF0000000L
25496 //TD_PERFCOUNTER1_SELECT
25497 #define TD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                               0x0
25498 #define TD_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                              0x14
25499 #define TD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                              0x1c
25500 #define TD_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                 0x0000003FL
25501 #define TD_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
25502 #define TD_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                                0xF0000000L
25503 //TCP_PERFCOUNTER0_SELECT
25504 #define TCP_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                              0x0
25505 #define TCP_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                             0xa
25506 #define TCP_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                             0x14
25507 #define TCP_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                            0x18
25508 #define TCP_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                             0x1c
25509 #define TCP_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                0x0000007FL
25510 #define TCP_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                               0x0001FC00L
25511 #define TCP_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
25512 #define TCP_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
25513 #define TCP_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                               0xF0000000L
25514 //TCP_PERFCOUNTER0_SELECT1
25515 #define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                            0x0
25516 #define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                            0xa
25517 #define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                           0x18
25518 #define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                           0x1c
25519 #define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                              0x0000007FL
25520 #define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                              0x0001FC00L
25521 #define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                             0x0F000000L
25522 #define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                             0xF0000000L
25523 //TCP_PERFCOUNTER1_SELECT
25524 #define TCP_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                              0x0
25525 #define TCP_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                             0xa
25526 #define TCP_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                             0x14
25527 #define TCP_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT                                                            0x18
25528 #define TCP_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                             0x1c
25529 #define TCP_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                0x0000007FL
25530 #define TCP_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                               0x0001FC00L
25531 #define TCP_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
25532 #define TCP_PERFCOUNTER1_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
25533 #define TCP_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                               0xF0000000L
25534 //TCP_PERFCOUNTER1_SELECT1
25535 #define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT                                                            0x0
25536 #define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT                                                            0xa
25537 #define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT                                                           0x18
25538 #define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT                                                           0x1c
25539 #define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK                                                              0x0000007FL
25540 #define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK                                                              0x0001FC00L
25541 #define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK                                                             0x0F000000L
25542 #define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK                                                             0xF0000000L
25543 //TCP_PERFCOUNTER2_SELECT
25544 #define TCP_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                              0x0
25545 #define TCP_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                             0x14
25546 #define TCP_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                             0x1c
25547 #define TCP_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                                0x0000007FL
25548 #define TCP_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
25549 #define TCP_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                               0xF0000000L
25550 //TCP_PERFCOUNTER3_SELECT
25551 #define TCP_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                              0x0
25552 #define TCP_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT                                                             0x14
25553 #define TCP_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                             0x1c
25554 #define TCP_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                                0x0000007FL
25555 #define TCP_PERFCOUNTER3_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
25556 #define TCP_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                               0xF0000000L
25557 //TCC_PERFCOUNTER0_SELECT
25558 #define TCC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                              0x0
25559 #define TCC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                             0xa
25560 #define TCC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                             0x14
25561 #define TCC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                            0x18
25562 #define TCC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                             0x1c
25563 #define TCC_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                0x000003FFL
25564 #define TCC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
25565 #define TCC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
25566 #define TCC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
25567 #define TCC_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                               0xF0000000L
25568 //TCC_PERFCOUNTER0_SELECT1
25569 #define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                            0x0
25570 #define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                            0xa
25571 #define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                           0x18
25572 #define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                           0x1c
25573 #define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
25574 #define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
25575 #define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                             0x0F000000L
25576 #define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                             0xF0000000L
25577 //TCC_PERFCOUNTER1_SELECT
25578 #define TCC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                              0x0
25579 #define TCC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                             0xa
25580 #define TCC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                             0x14
25581 #define TCC_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT                                                            0x18
25582 #define TCC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                             0x1c
25583 #define TCC_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                0x000003FFL
25584 #define TCC_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
25585 #define TCC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
25586 #define TCC_PERFCOUNTER1_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
25587 #define TCC_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                               0xF0000000L
25588 //TCC_PERFCOUNTER1_SELECT1
25589 #define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT                                                            0x0
25590 #define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT                                                            0xa
25591 #define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT                                                           0x18
25592 #define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT                                                           0x1c
25593 #define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
25594 #define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
25595 #define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK                                                             0x0F000000L
25596 #define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK                                                             0xF0000000L
25597 //TCC_PERFCOUNTER2_SELECT
25598 #define TCC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                              0x0
25599 #define TCC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                             0x14
25600 #define TCC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                             0x1c
25601 #define TCC_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                                0x000003FFL
25602 #define TCC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
25603 #define TCC_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                               0xF0000000L
25604 //TCC_PERFCOUNTER3_SELECT
25605 #define TCC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                              0x0
25606 #define TCC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT                                                             0x14
25607 #define TCC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                             0x1c
25608 #define TCC_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                                0x000003FFL
25609 #define TCC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
25610 #define TCC_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                               0xF0000000L
25611 //TCA_PERFCOUNTER0_SELECT
25612 #define TCA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                              0x0
25613 #define TCA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                             0xa
25614 #define TCA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                             0x14
25615 #define TCA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                            0x18
25616 #define TCA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                             0x1c
25617 #define TCA_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                0x000003FFL
25618 #define TCA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
25619 #define TCA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
25620 #define TCA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
25621 #define TCA_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                               0xF0000000L
25622 //TCA_PERFCOUNTER0_SELECT1
25623 #define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                            0x0
25624 #define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                            0xa
25625 #define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                           0x18
25626 #define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                           0x1c
25627 #define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
25628 #define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
25629 #define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                             0x0F000000L
25630 #define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                             0xF0000000L
25631 //TCA_PERFCOUNTER1_SELECT
25632 #define TCA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                              0x0
25633 #define TCA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                             0xa
25634 #define TCA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                             0x14
25635 #define TCA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT                                                            0x18
25636 #define TCA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                             0x1c
25637 #define TCA_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                0x000003FFL
25638 #define TCA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
25639 #define TCA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
25640 #define TCA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
25641 #define TCA_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                               0xF0000000L
25642 //TCA_PERFCOUNTER1_SELECT1
25643 #define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT                                                            0x0
25644 #define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT                                                            0xa
25645 #define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT                                                           0x18
25646 #define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT                                                           0x1c
25647 #define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
25648 #define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
25649 #define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK                                                             0x0F000000L
25650 #define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK                                                             0xF0000000L
25651 //TCA_PERFCOUNTER2_SELECT
25652 #define TCA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                              0x0
25653 #define TCA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                             0x14
25654 #define TCA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                             0x1c
25655 #define TCA_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                                0x000003FFL
25656 #define TCA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
25657 #define TCA_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                               0xF0000000L
25658 //TCA_PERFCOUNTER3_SELECT
25659 #define TCA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                              0x0
25660 #define TCA_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT                                                             0x14
25661 #define TCA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                             0x1c
25662 #define TCA_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                                0x000003FFL
25663 #define TCA_PERFCOUNTER3_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
25664 #define TCA_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                               0xF0000000L
25665 //CB_PERFCOUNTER_FILTER
25666 #define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE__SHIFT                                                        0x0
25667 #define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL__SHIFT                                                           0x1
25668 #define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE__SHIFT                                                    0x4
25669 #define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL__SHIFT                                                       0x5
25670 #define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE__SHIFT                                                     0xa
25671 #define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL__SHIFT                                                        0xb
25672 #define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE__SHIFT                                                       0xc
25673 #define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL__SHIFT                                                          0xd
25674 #define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE__SHIFT                                               0x11
25675 #define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL__SHIFT                                                  0x12
25676 #define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE__SHIFT                                             0x15
25677 #define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL__SHIFT                                                0x16
25678 #define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE_MASK                                                          0x00000001L
25679 #define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL_MASK                                                             0x0000000EL
25680 #define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE_MASK                                                      0x00000010L
25681 #define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL_MASK                                                         0x000003E0L
25682 #define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE_MASK                                                       0x00000400L
25683 #define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL_MASK                                                          0x00000800L
25684 #define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE_MASK                                                         0x00001000L
25685 #define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL_MASK                                                            0x0000E000L
25686 #define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE_MASK                                                 0x00020000L
25687 #define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL_MASK                                                    0x001C0000L
25688 #define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE_MASK                                               0x00200000L
25689 #define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL_MASK                                                  0x00C00000L
25690 //CB_PERFCOUNTER0_SELECT
25691 #define CB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                               0x0
25692 #define CB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                              0xa
25693 #define CB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                              0x14
25694 #define CB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                             0x18
25695 #define CB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                              0x1c
25696 #define CB_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
25697 #define CB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                                0x0007FC00L
25698 #define CB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
25699 #define CB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                               0x0F000000L
25700 #define CB_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                                0xF0000000L
25701 //CB_PERFCOUNTER0_SELECT1
25702 #define CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                             0x0
25703 #define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                             0xa
25704 #define CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                            0x18
25705 #define CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                            0x1c
25706 #define CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                               0x000001FFL
25707 #define CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                               0x0007FC00L
25708 #define CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                              0x0F000000L
25709 #define CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                              0xF0000000L
25710 //CB_PERFCOUNTER1_SELECT
25711 #define CB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                               0x0
25712 #define CB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                              0x1c
25713 #define CB_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
25714 #define CB_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                                0xF0000000L
25715 //CB_PERFCOUNTER2_SELECT
25716 #define CB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                               0x0
25717 #define CB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                              0x1c
25718 #define CB_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
25719 #define CB_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                                0xF0000000L
25720 //CB_PERFCOUNTER3_SELECT
25721 #define CB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                               0x0
25722 #define CB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                              0x1c
25723 #define CB_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
25724 #define CB_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                                0xF0000000L
25725 //DB_PERFCOUNTER0_SELECT
25726 #define DB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                               0x0
25727 #define DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                              0xa
25728 #define DB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                              0x14
25729 #define DB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                             0x18
25730 #define DB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                              0x1c
25731 #define DB_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                 0x000003FFL
25732 #define DB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                                0x000FFC00L
25733 #define DB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
25734 #define DB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                               0x0F000000L
25735 #define DB_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                                0xF0000000L
25736 //DB_PERFCOUNTER0_SELECT1
25737 #define DB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                             0x0
25738 #define DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                             0xa
25739 #define DB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                            0x18
25740 #define DB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                            0x1c
25741 #define DB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                               0x000003FFL
25742 #define DB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                               0x000FFC00L
25743 #define DB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                              0x0F000000L
25744 #define DB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                              0xF0000000L
25745 //DB_PERFCOUNTER1_SELECT
25746 #define DB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                               0x0
25747 #define DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                              0xa
25748 #define DB_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                              0x14
25749 #define DB_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT                                                             0x18
25750 #define DB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                              0x1c
25751 #define DB_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                 0x000003FFL
25752 #define DB_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                                0x000FFC00L
25753 #define DB_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
25754 #define DB_PERFCOUNTER1_SELECT__PERF_MODE1_MASK                                                               0x0F000000L
25755 #define DB_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                                0xF0000000L
25756 //DB_PERFCOUNTER1_SELECT1
25757 #define DB_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT                                                             0x0
25758 #define DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT                                                             0xa
25759 #define DB_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT                                                            0x18
25760 #define DB_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT                                                            0x1c
25761 #define DB_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK                                                               0x000003FFL
25762 #define DB_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK                                                               0x000FFC00L
25763 #define DB_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK                                                              0x0F000000L
25764 #define DB_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK                                                              0xF0000000L
25765 //DB_PERFCOUNTER2_SELECT
25766 #define DB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                               0x0
25767 #define DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT                                                              0xa
25768 #define DB_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                              0x14
25769 #define DB_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT                                                             0x18
25770 #define DB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                              0x1c
25771 #define DB_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                                 0x000003FFL
25772 #define DB_PERFCOUNTER2_SELECT__PERF_SEL1_MASK                                                                0x000FFC00L
25773 #define DB_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
25774 #define DB_PERFCOUNTER2_SELECT__PERF_MODE1_MASK                                                               0x0F000000L
25775 #define DB_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                                0xF0000000L
25776 //DB_PERFCOUNTER3_SELECT
25777 #define DB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                               0x0
25778 #define DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT                                                              0xa
25779 #define DB_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT                                                              0x14
25780 #define DB_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT                                                             0x18
25781 #define DB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                              0x1c
25782 #define DB_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                                 0x000003FFL
25783 #define DB_PERFCOUNTER3_SELECT__PERF_SEL1_MASK                                                                0x000FFC00L
25784 #define DB_PERFCOUNTER3_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
25785 #define DB_PERFCOUNTER3_SELECT__PERF_MODE1_MASK                                                               0x0F000000L
25786 #define DB_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                                0xF0000000L
25787 //RLC_SPM_PERFMON_CNTL
25788 #define RLC_SPM_PERFMON_CNTL__RESERVED1__SHIFT                                                                0x0
25789 #define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE__SHIFT                                                        0xc
25790 #define RLC_SPM_PERFMON_CNTL__RESERVED__SHIFT                                                                 0xe
25791 #define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL__SHIFT                                                  0x10
25792 #define RLC_SPM_PERFMON_CNTL__RESERVED1_MASK                                                                  0x00000FFFL
25793 #define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK                                                          0x00003000L
25794 #define RLC_SPM_PERFMON_CNTL__RESERVED_MASK                                                                   0x0000C000L
25795 #define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL_MASK                                                    0xFFFF0000L
25796 //RLC_SPM_PERFMON_RING_BASE_LO
25797 #define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO__SHIFT                                                     0x0
25798 #define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO_MASK                                                       0xFFFFFFFFL
25799 //RLC_SPM_PERFMON_RING_BASE_HI
25800 #define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI__SHIFT                                                     0x0
25801 #define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED__SHIFT                                                         0x10
25802 #define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI_MASK                                                       0x0000FFFFL
25803 #define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED_MASK                                                           0xFFFF0000L
25804 //RLC_SPM_PERFMON_RING_SIZE
25805 #define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE__SHIFT                                                      0x0
25806 #define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE_MASK                                                        0xFFFFFFFFL
25807 //RLC_SPM_PERFMON_SEGMENT_SIZE
25808 #define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE__SHIFT                                             0x0
25809 #define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1__SHIFT                                                        0x8
25810 #define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE__SHIFT                                                  0xb
25811 #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE__SHIFT                                                     0x10
25812 #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE__SHIFT                                                     0x15
25813 #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE__SHIFT                                                     0x1a
25814 #define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED__SHIFT                                                         0x1f
25815 #define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE_MASK                                               0x000000FFL
25816 #define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1_MASK                                                          0x00000700L
25817 #define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE_MASK                                                    0x0000F800L
25818 #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE_MASK                                                       0x001F0000L
25819 #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE_MASK                                                       0x03E00000L
25820 #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE_MASK                                                       0x7C000000L
25821 #define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED_MASK                                                           0x80000000L
25822 //RLC_SPM_SE_MUXSEL_ADDR
25823 #define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT                                                       0x0
25824 #define RLC_SPM_SE_MUXSEL_ADDR__RESERVED__SHIFT                                                               0x8
25825 #define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK                                                         0x000000FFL
25826 #define RLC_SPM_SE_MUXSEL_ADDR__RESERVED_MASK                                                                 0xFFFFFF00L
25827 //RLC_SPM_SE_MUXSEL_DATA
25828 #define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT                                                       0x0
25829 #define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA_MASK                                                         0xFFFFFFFFL
25830 //RLC_SPM_CPG_PERFMON_SAMPLE_DELAY
25831 #define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                         0x0
25832 #define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                     0x8
25833 #define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                           0x000000FFL
25834 #define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                       0xFFFFFF00L
25835 //RLC_SPM_CPC_PERFMON_SAMPLE_DELAY
25836 #define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                         0x0
25837 #define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                     0x8
25838 #define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                           0x000000FFL
25839 #define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                       0xFFFFFF00L
25840 //RLC_SPM_CPF_PERFMON_SAMPLE_DELAY
25841 #define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                         0x0
25842 #define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                     0x8
25843 #define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                           0x000000FFL
25844 #define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                       0xFFFFFF00L
25845 //RLC_SPM_CB_PERFMON_SAMPLE_DELAY
25846 #define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                          0x0
25847 #define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                      0x8
25848 #define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                            0x000000FFL
25849 #define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                        0xFFFFFF00L
25850 //RLC_SPM_DB_PERFMON_SAMPLE_DELAY
25851 #define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                          0x0
25852 #define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                      0x8
25853 #define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                            0x000000FFL
25854 #define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                        0xFFFFFF00L
25855 //RLC_SPM_PA_PERFMON_SAMPLE_DELAY
25856 #define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                          0x0
25857 #define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                      0x8
25858 #define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                            0x000000FFL
25859 #define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                        0xFFFFFF00L
25860 //RLC_SPM_GDS_PERFMON_SAMPLE_DELAY
25861 #define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                         0x0
25862 #define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                     0x8
25863 #define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                           0x000000FFL
25864 #define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                       0xFFFFFF00L
25865 //RLC_SPM_IA_PERFMON_SAMPLE_DELAY
25866 #define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                          0x0
25867 #define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                      0x8
25868 #define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                            0x000000FFL
25869 #define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                        0xFFFFFF00L
25870 //RLC_SPM_SC_PERFMON_SAMPLE_DELAY
25871 #define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                          0x0
25872 #define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                      0x8
25873 #define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                            0x000000FFL
25874 #define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                        0xFFFFFF00L
25875 //RLC_SPM_TCC_PERFMON_SAMPLE_DELAY
25876 #define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                         0x0
25877 #define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                     0x8
25878 #define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                           0x000000FFL
25879 #define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                       0xFFFFFF00L
25880 //RLC_SPM_TCA_PERFMON_SAMPLE_DELAY
25881 #define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                         0x0
25882 #define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                     0x8
25883 #define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                           0x000000FFL
25884 #define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                       0xFFFFFF00L
25885 //RLC_SPM_TCP_PERFMON_SAMPLE_DELAY
25886 #define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                         0x0
25887 #define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                     0x8
25888 #define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                           0x000000FFL
25889 #define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                       0xFFFFFF00L
25890 //RLC_SPM_TA_PERFMON_SAMPLE_DELAY
25891 #define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                          0x0
25892 #define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                      0x8
25893 #define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                            0x000000FFL
25894 #define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                        0xFFFFFF00L
25895 //RLC_SPM_TD_PERFMON_SAMPLE_DELAY
25896 #define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                          0x0
25897 #define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                      0x8
25898 #define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                            0x000000FFL
25899 #define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                        0xFFFFFF00L
25900 //RLC_SPM_VGT_PERFMON_SAMPLE_DELAY
25901 #define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                         0x0
25902 #define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                     0x8
25903 #define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                           0x000000FFL
25904 #define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                       0xFFFFFF00L
25905 //RLC_SPM_SPI_PERFMON_SAMPLE_DELAY
25906 #define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                         0x0
25907 #define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                     0x8
25908 #define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                           0x000000FFL
25909 #define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                       0xFFFFFF00L
25910 //RLC_SPM_SQG_PERFMON_SAMPLE_DELAY
25911 #define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                         0x0
25912 #define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                     0x8
25913 #define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                           0x000000FFL
25914 #define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                       0xFFFFFF00L
25915 //RLC_SPM_SX_PERFMON_SAMPLE_DELAY
25916 #define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                          0x0
25917 #define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                      0x8
25918 #define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                            0x000000FFL
25919 #define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                        0xFFFFFF00L
25920 //RLC_SPM_GLOBAL_MUXSEL_ADDR
25921 #define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT                                                   0x0
25922 #define RLC_SPM_GLOBAL_MUXSEL_ADDR__RESERVED__SHIFT                                                           0x7
25923 #define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK                                                     0x0000007FL
25924 #define RLC_SPM_GLOBAL_MUXSEL_ADDR__RESERVED_MASK                                                             0xFFFFFF80L
25925 //RLC_SPM_GLOBAL_MUXSEL_DATA
25926 #define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT                                                   0x0
25927 #define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA_MASK                                                     0xFFFFFFFFL
25928 //RLC_SPM_RING_RDPTR
25929 #define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR__SHIFT                                                         0x0
25930 #define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR_MASK                                                           0xFFFFFFFFL
25931 //RLC_SPM_SEGMENT_THRESHOLD
25932 #define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD__SHIFT                                               0x0
25933 #define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD_MASK                                                 0xFFFFFFFFL
25934 //RLC_SPM_RMI_PERFMON_SAMPLE_DELAY
25935 #define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                         0x0
25936 #define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                     0x8
25937 #define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                           0x000000FFL
25938 #define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                       0xFFFFFF00L
25939 //RLC_SPM_PERFMON_SAMPLE_DELAY_MAX
25940 #define RLC_SPM_PERFMON_SAMPLE_DELAY_MAX__PERFMON_MAX_SAMPLE_DELAY__SHIFT                                     0x0
25941 #define RLC_SPM_PERFMON_SAMPLE_DELAY_MAX__RESERVED__SHIFT                                                     0x8
25942 #define RLC_SPM_PERFMON_SAMPLE_DELAY_MAX__PERFMON_MAX_SAMPLE_DELAY_MASK                                       0x000000FFL
25943 #define RLC_SPM_PERFMON_SAMPLE_DELAY_MAX__RESERVED_MASK                                                       0xFFFFFF00L
25944 //RLC_PERFMON_CNTL
25945 #define RLC_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                                0x0
25946 #define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT                                                        0xa
25947 #define RLC_PERFMON_CNTL__PERFMON_STATE_MASK                                                                  0x00000007L
25948 #define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK                                                          0x00000400L
25949 //RLC_PERFCOUNTER0_SELECT
25950 #define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT                                                    0x0
25951 #define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK                                                      0x00FFL
25952 //RLC_PERFCOUNTER1_SELECT
25953 #define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT                                                    0x0
25954 #define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK                                                      0x00FFL
25955 //RLC_GPU_IOV_PERF_CNT_CNTL
25956 #define RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE__SHIFT                                                              0x0
25957 #define RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT__SHIFT                                                         0x1
25958 #define RLC_GPU_IOV_PERF_CNT_CNTL__RESET__SHIFT                                                               0x2
25959 #define RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED__SHIFT                                                            0x3
25960 #define RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE_MASK                                                                0x00000001L
25961 #define RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT_MASK                                                           0x00000002L
25962 #define RLC_GPU_IOV_PERF_CNT_CNTL__RESET_MASK                                                                 0x00000004L
25963 #define RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED_MASK                                                              0xFFFFFFF8L
25964 //RLC_GPU_IOV_PERF_CNT_WR_ADDR
25965 #define RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID__SHIFT                                                             0x0
25966 #define RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID__SHIFT                                                           0x4
25967 #define RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED__SHIFT                                                         0x6
25968 #define RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID_MASK                                                               0x0000000FL
25969 #define RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID_MASK                                                             0x00000030L
25970 #define RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED_MASK                                                           0xFFFFFFC0L
25971 //RLC_GPU_IOV_PERF_CNT_WR_DATA
25972 #define RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA__SHIFT                                                             0x0
25973 #define RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA_MASK                                                               0x0000000FL
25974 //RLC_GPU_IOV_PERF_CNT_RD_ADDR
25975 #define RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID__SHIFT                                                             0x0
25976 #define RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID__SHIFT                                                           0x4
25977 #define RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED__SHIFT                                                         0x6
25978 #define RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID_MASK                                                               0x0000000FL
25979 #define RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID_MASK                                                             0x00000030L
25980 #define RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED_MASK                                                           0xFFFFFFC0L
25981 //RLC_GPU_IOV_PERF_CNT_RD_DATA
25982 #define RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA__SHIFT                                                             0x0
25983 #define RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA_MASK                                                               0x0000000FL
25984 //RMI_PERFCOUNTER0_SELECT
25985 #define RMI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                              0x0
25986 #define RMI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                             0xa
25987 #define RMI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                             0x14
25988 #define RMI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                            0x18
25989 #define RMI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                             0x1c
25990 #define RMI_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                0x000001FFL
25991 #define RMI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                               0x0007FC00L
25992 #define RMI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
25993 #define RMI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
25994 #define RMI_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                               0xF0000000L
25995 //RMI_PERFCOUNTER0_SELECT1
25996 #define RMI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                            0x0
25997 #define RMI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                            0xa
25998 #define RMI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                           0x18
25999 #define RMI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                           0x1c
26000 #define RMI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                              0x000001FFL
26001 #define RMI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                              0x0007FC00L
26002 #define RMI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                             0x0F000000L
26003 #define RMI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                             0xF0000000L
26004 //RMI_PERFCOUNTER1_SELECT
26005 #define RMI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                              0x0
26006 #define RMI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                             0x1c
26007 #define RMI_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                0x000001FFL
26008 #define RMI_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                               0xF0000000L
26009 //RMI_PERFCOUNTER2_SELECT
26010 #define RMI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                              0x0
26011 #define RMI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT                                                             0xa
26012 #define RMI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                             0x14
26013 #define RMI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT                                                            0x18
26014 #define RMI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                             0x1c
26015 #define RMI_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                                0x000001FFL
26016 #define RMI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK                                                               0x0007FC00L
26017 #define RMI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
26018 #define RMI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
26019 #define RMI_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                               0xF0000000L
26020 //RMI_PERFCOUNTER2_SELECT1
26021 #define RMI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT                                                            0x0
26022 #define RMI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT                                                            0xa
26023 #define RMI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT                                                           0x18
26024 #define RMI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT                                                           0x1c
26025 #define RMI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK                                                              0x000001FFL
26026 #define RMI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK                                                              0x0007FC00L
26027 #define RMI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK                                                             0x0F000000L
26028 #define RMI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK                                                             0xF0000000L
26029 //RMI_PERFCOUNTER3_SELECT
26030 #define RMI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                              0x0
26031 #define RMI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                             0x1c
26032 #define RMI_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                                0x000001FFL
26033 #define RMI_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                               0xF0000000L
26034 //RMI_PERF_COUNTER_CNTL
26035 #define RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL__SHIFT                                                 0x0
26036 #define RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL__SHIFT                                                 0x2
26037 #define RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL__SHIFT                                                          0x4
26038 #define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0__SHIFT                                                 0x6
26039 #define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1__SHIFT                                                 0x8
26040 #define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID__SHIFT                                                        0xa
26041 #define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID__SHIFT                                                       0xe
26042 #define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD__SHIFT                                     0x13
26043 #define RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET__SHIFT                                                         0x19
26044 #define RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL__SHIFT                                                       0x1a
26045 #define RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL_MASK                                                   0x00000003L
26046 #define RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL_MASK                                                   0x0000000CL
26047 #define RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL_MASK                                                            0x00000030L
26048 #define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0_MASK                                                   0x000000C0L
26049 #define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1_MASK                                                   0x00000300L
26050 #define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID_MASK                                                          0x00003C00L
26051 #define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID_MASK                                                         0x0007C000L
26052 #define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD_MASK                                       0x01F80000L
26053 #define RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET_MASK                                                           0x02000000L
26054 #define RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL_MASK                                                         0x04000000L
26055 
26056 
26057 // addressBlock: xcd0_gc_utcl2_atcl2pfcntldec
26058 //ATC_L2_PERFCOUNTER0_CFG
26059 #define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                              0x0
26060 #define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                          0x8
26061 #define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                             0x18
26062 #define ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                0x1c
26063 #define ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                 0x1d
26064 #define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                0x000000FFL
26065 #define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                            0x0000FF00L
26066 #define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                               0x0F000000L
26067 #define ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK                                                                  0x10000000L
26068 #define ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK                                                                   0x20000000L
26069 //ATC_L2_PERFCOUNTER1_CFG
26070 #define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                              0x0
26071 #define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                          0x8
26072 #define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                             0x18
26073 #define ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                0x1c
26074 #define ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                 0x1d
26075 #define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                0x000000FFL
26076 #define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                            0x0000FF00L
26077 #define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                               0x0F000000L
26078 #define ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK                                                                  0x10000000L
26079 #define ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK                                                                   0x20000000L
26080 //ATC_L2_PERFCOUNTER_RSLT_CNTL
26081 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                              0x0
26082 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                    0x8
26083 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                     0x10
26084 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                       0x18
26085 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                        0x19
26086 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                             0x1a
26087 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                0x0000000FL
26088 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                      0x0000FF00L
26089 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                       0x00FF0000L
26090 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                         0x01000000L
26091 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                          0x02000000L
26092 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                               0x04000000L
26093 
26094 
26095 // addressBlock: xcd0_gc_utcl2_vml2pldec
26096 //MC_VM_L2_PERFCOUNTER0_CFG
26097 #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                            0x0
26098 #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                        0x8
26099 #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                           0x18
26100 #define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                              0x1c
26101 #define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                               0x1d
26102 #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                              0x000000FFL
26103 #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                          0x0000FF00L
26104 #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                             0x0F000000L
26105 #define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK                                                                0x10000000L
26106 #define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK                                                                 0x20000000L
26107 //MC_VM_L2_PERFCOUNTER1_CFG
26108 #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                            0x0
26109 #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                        0x8
26110 #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                           0x18
26111 #define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                              0x1c
26112 #define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                               0x1d
26113 #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                              0x000000FFL
26114 #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                          0x0000FF00L
26115 #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                             0x0F000000L
26116 #define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK                                                                0x10000000L
26117 #define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK                                                                 0x20000000L
26118 //MC_VM_L2_PERFCOUNTER2_CFG
26119 #define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT                                                            0x0
26120 #define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT                                                        0x8
26121 #define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT                                                           0x18
26122 #define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT                                                              0x1c
26123 #define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT                                                               0x1d
26124 #define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK                                                              0x000000FFL
26125 #define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK                                                          0x0000FF00L
26126 #define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK                                                             0x0F000000L
26127 #define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK                                                                0x10000000L
26128 #define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK                                                                 0x20000000L
26129 //MC_VM_L2_PERFCOUNTER3_CFG
26130 #define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT                                                            0x0
26131 #define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT                                                        0x8
26132 #define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT                                                           0x18
26133 #define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT                                                              0x1c
26134 #define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT                                                               0x1d
26135 #define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK                                                              0x000000FFL
26136 #define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK                                                          0x0000FF00L
26137 #define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK                                                             0x0F000000L
26138 #define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK                                                                0x10000000L
26139 #define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK                                                                 0x20000000L
26140 //MC_VM_L2_PERFCOUNTER4_CFG
26141 #define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT                                                            0x0
26142 #define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT                                                        0x8
26143 #define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT                                                           0x18
26144 #define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT                                                              0x1c
26145 #define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT                                                               0x1d
26146 #define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK                                                              0x000000FFL
26147 #define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK                                                          0x0000FF00L
26148 #define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK                                                             0x0F000000L
26149 #define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK                                                                0x10000000L
26150 #define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK                                                                 0x20000000L
26151 //MC_VM_L2_PERFCOUNTER5_CFG
26152 #define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT                                                            0x0
26153 #define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT                                                        0x8
26154 #define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT                                                           0x18
26155 #define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT                                                              0x1c
26156 #define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT                                                               0x1d
26157 #define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK                                                              0x000000FFL
26158 #define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK                                                          0x0000FF00L
26159 #define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK                                                             0x0F000000L
26160 #define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK                                                                0x10000000L
26161 #define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK                                                                 0x20000000L
26162 //MC_VM_L2_PERFCOUNTER6_CFG
26163 #define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT                                                            0x0
26164 #define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT                                                        0x8
26165 #define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT                                                           0x18
26166 #define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT                                                              0x1c
26167 #define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT                                                               0x1d
26168 #define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK                                                              0x000000FFL
26169 #define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK                                                          0x0000FF00L
26170 #define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK                                                             0x0F000000L
26171 #define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK                                                                0x10000000L
26172 #define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK                                                                 0x20000000L
26173 //MC_VM_L2_PERFCOUNTER7_CFG
26174 #define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT                                                            0x0
26175 #define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT                                                        0x8
26176 #define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT                                                           0x18
26177 #define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT                                                              0x1c
26178 #define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT                                                               0x1d
26179 #define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK                                                              0x000000FFL
26180 #define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK                                                          0x0000FF00L
26181 #define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK                                                             0x0F000000L
26182 #define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK                                                                0x10000000L
26183 #define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK                                                                 0x20000000L
26184 //MC_VM_L2_PERFCOUNTER_RSLT_CNTL
26185 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                            0x0
26186 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                  0x8
26187 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                   0x10
26188 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                     0x18
26189 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                      0x19
26190 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                           0x1a
26191 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                              0x0000000FL
26192 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                    0x0000FF00L
26193 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                     0x00FF0000L
26194 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                       0x01000000L
26195 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                        0x02000000L
26196 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                             0x04000000L
26197 
26198 
26199 // addressBlock: xcd0_gc_utcl2_l2tlbpldec
26200 //L2TLB_PERFCOUNTER0_CFG
26201 #define L2TLB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                               0x0
26202 #define L2TLB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                           0x8
26203 #define L2TLB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                              0x18
26204 #define L2TLB_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                 0x1c
26205 #define L2TLB_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                  0x1d
26206 #define L2TLB_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                 0x000000FFL
26207 #define L2TLB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
26208 #define L2TLB_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                                0x0F000000L
26209 #define L2TLB_PERFCOUNTER0_CFG__ENABLE_MASK                                                                   0x10000000L
26210 #define L2TLB_PERFCOUNTER0_CFG__CLEAR_MASK                                                                    0x20000000L
26211 //L2TLB_PERFCOUNTER1_CFG
26212 #define L2TLB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                               0x0
26213 #define L2TLB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                           0x8
26214 #define L2TLB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                              0x18
26215 #define L2TLB_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                 0x1c
26216 #define L2TLB_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                  0x1d
26217 #define L2TLB_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                 0x000000FFL
26218 #define L2TLB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
26219 #define L2TLB_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                                0x0F000000L
26220 #define L2TLB_PERFCOUNTER1_CFG__ENABLE_MASK                                                                   0x10000000L
26221 #define L2TLB_PERFCOUNTER1_CFG__CLEAR_MASK                                                                    0x20000000L
26222 //L2TLB_PERFCOUNTER2_CFG
26223 #define L2TLB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT                                                               0x0
26224 #define L2TLB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT                                                           0x8
26225 #define L2TLB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT                                                              0x18
26226 #define L2TLB_PERFCOUNTER2_CFG__ENABLE__SHIFT                                                                 0x1c
26227 #define L2TLB_PERFCOUNTER2_CFG__CLEAR__SHIFT                                                                  0x1d
26228 #define L2TLB_PERFCOUNTER2_CFG__PERF_SEL_MASK                                                                 0x000000FFL
26229 #define L2TLB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
26230 #define L2TLB_PERFCOUNTER2_CFG__PERF_MODE_MASK                                                                0x0F000000L
26231 #define L2TLB_PERFCOUNTER2_CFG__ENABLE_MASK                                                                   0x10000000L
26232 #define L2TLB_PERFCOUNTER2_CFG__CLEAR_MASK                                                                    0x20000000L
26233 //L2TLB_PERFCOUNTER3_CFG
26234 #define L2TLB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT                                                               0x0
26235 #define L2TLB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT                                                           0x8
26236 #define L2TLB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT                                                              0x18
26237 #define L2TLB_PERFCOUNTER3_CFG__ENABLE__SHIFT                                                                 0x1c
26238 #define L2TLB_PERFCOUNTER3_CFG__CLEAR__SHIFT                                                                  0x1d
26239 #define L2TLB_PERFCOUNTER3_CFG__PERF_SEL_MASK                                                                 0x000000FFL
26240 #define L2TLB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
26241 #define L2TLB_PERFCOUNTER3_CFG__PERF_MODE_MASK                                                                0x0F000000L
26242 #define L2TLB_PERFCOUNTER3_CFG__ENABLE_MASK                                                                   0x10000000L
26243 #define L2TLB_PERFCOUNTER3_CFG__CLEAR_MASK                                                                    0x20000000L
26244 //L2TLB_PERFCOUNTER_RSLT_CNTL
26245 #define L2TLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                               0x0
26246 #define L2TLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                     0x8
26247 #define L2TLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                      0x10
26248 #define L2TLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                        0x18
26249 #define L2TLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                         0x19
26250 #define L2TLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                              0x1a
26251 #define L2TLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                 0x0000000FL
26252 #define L2TLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                       0x0000FF00L
26253 #define L2TLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                        0x00FF0000L
26254 #define L2TLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                          0x01000000L
26255 #define L2TLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                           0x02000000L
26256 #define L2TLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                                0x04000000L
26257 
26258 
26259 // addressBlock: xcd0_gc_gdflldec
26260 //GDFLL_EDC_HYSTERESIS_CNTL
26261 #define GDFLL_EDC_HYSTERESIS_CNTL__MAX_HYSTERESIS__SHIFT                                                      0x0
26262 #define GDFLL_EDC_HYSTERESIS_CNTL__MAX_HYSTERESIS_MASK                                                        0x000000FFL
26263 //GDFLL_EDC_HYSTERESIS_STAT
26264 #define GDFLL_EDC_HYSTERESIS_STAT__HYSTERESIS_CNT__SHIFT                                                      0x0
26265 #define GDFLL_EDC_HYSTERESIS_STAT__EDC__SHIFT                                                                 0x8
26266 #define GDFLL_EDC_HYSTERESIS_STAT__HYSTERESIS_CNT_MASK                                                        0x000000FFL
26267 #define GDFLL_EDC_HYSTERESIS_STAT__EDC_MASK                                                                   0x00000100L
26268 
26269 
26270 // addressBlock: xcd0_gc_rlcpdec
26271 //RLC_CNTL
26272 #define RLC_CNTL__RLC_ENABLE_F32__SHIFT                                                                       0x0
26273 #define RLC_CNTL__FORCE_RETRY__SHIFT                                                                          0x1
26274 #define RLC_CNTL__READ_CACHE_DISABLE__SHIFT                                                                   0x2
26275 #define RLC_CNTL__RLC_STEP_F32__SHIFT                                                                         0x3
26276 #define RLC_CNTL__RESERVED__SHIFT                                                                             0x4
26277 #define RLC_CNTL__RLC_ENABLE_F32_MASK                                                                         0x00000001L
26278 #define RLC_CNTL__FORCE_RETRY_MASK                                                                            0x00000002L
26279 #define RLC_CNTL__READ_CACHE_DISABLE_MASK                                                                     0x00000004L
26280 #define RLC_CNTL__RLC_STEP_F32_MASK                                                                           0x00000008L
26281 #define RLC_CNTL__RESERVED_MASK                                                                               0xFFFFFFF0L
26282 //RLC_CGCG_CGLS_CTRL_2
26283 #define RLC_CGCG_CGLS_CTRL_2__CANE_STAT_BUSY_MASK__SHIFT                                                      0x0
26284 #define RLC_CGCG_CGLS_CTRL_2__RESERVED__SHIFT                                                                 0x1
26285 #define RLC_CGCG_CGLS_CTRL_2__CANE_STAT_BUSY_MASK_MASK                                                        0x00000001L
26286 #define RLC_CGCG_CGLS_CTRL_2__RESERVED_MASK                                                                   0xFFFFFFFEL
26287 //RLC_STAT
26288 #define RLC_STAT__RLC_BUSY__SHIFT                                                                             0x0
26289 #define RLC_STAT__RLC_SRM_BUSY__SHIFT                                                                         0x1
26290 #define RLC_STAT__RLC_GPM_BUSY__SHIFT                                                                         0x2
26291 #define RLC_STAT__RLC_SPM_BUSY__SHIFT                                                                         0x3
26292 #define RLC_STAT__MC_BUSY__SHIFT                                                                              0x4
26293 #define RLC_STAT__RLC_THREAD_0_BUSY__SHIFT                                                                    0x5
26294 #define RLC_STAT__RLC_THREAD_1_BUSY__SHIFT                                                                    0x6
26295 #define RLC_STAT__RLC_THREAD_2_BUSY__SHIFT                                                                    0x7
26296 #define RLC_STAT__RESERVED__SHIFT                                                                             0x8
26297 #define RLC_STAT__RLC_BUSY_MASK                                                                               0x00000001L
26298 #define RLC_STAT__RLC_SRM_BUSY_MASK                                                                           0x00000002L
26299 #define RLC_STAT__RLC_GPM_BUSY_MASK                                                                           0x00000004L
26300 #define RLC_STAT__RLC_SPM_BUSY_MASK                                                                           0x00000008L
26301 #define RLC_STAT__MC_BUSY_MASK                                                                                0x00000010L
26302 #define RLC_STAT__RLC_THREAD_0_BUSY_MASK                                                                      0x00000020L
26303 #define RLC_STAT__RLC_THREAD_1_BUSY_MASK                                                                      0x00000040L
26304 #define RLC_STAT__RLC_THREAD_2_BUSY_MASK                                                                      0x00000080L
26305 #define RLC_STAT__RESERVED_MASK                                                                               0xFFFFFF00L
26306 //RLC_SAFE_MODE
26307 #define RLC_SAFE_MODE__CMD__SHIFT                                                                             0x0
26308 #define RLC_SAFE_MODE__MESSAGE__SHIFT                                                                         0x1
26309 #define RLC_SAFE_MODE__RESERVED1__SHIFT                                                                       0x5
26310 #define RLC_SAFE_MODE__RESPONSE__SHIFT                                                                        0x8
26311 #define RLC_SAFE_MODE__RESERVED__SHIFT                                                                        0xc
26312 #define RLC_SAFE_MODE__CMD_MASK                                                                               0x00000001L
26313 #define RLC_SAFE_MODE__MESSAGE_MASK                                                                           0x0000001EL
26314 #define RLC_SAFE_MODE__RESERVED1_MASK                                                                         0x000000E0L
26315 #define RLC_SAFE_MODE__RESPONSE_MASK                                                                          0x00000F00L
26316 #define RLC_SAFE_MODE__RESERVED_MASK                                                                          0xFFFFF000L
26317 //RLC_MEM_SLP_CNTL
26318 #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN__SHIFT                                                                0x0
26319 #define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN__SHIFT                                                                0x1
26320 #define RLC_MEM_SLP_CNTL__RESERVED__SHIFT                                                                     0x2
26321 #define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE__SHIFT                                                      0x7
26322 #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY__SHIFT                                                          0x8
26323 #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY__SHIFT                                                         0x10
26324 #define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT                                                                    0x18
26325 #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK                                                                  0x00000001L
26326 #define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK                                                                  0x00000002L
26327 #define RLC_MEM_SLP_CNTL__RESERVED_MASK                                                                       0x0000007CL
26328 #define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE_MASK                                                        0x00000080L
26329 #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY_MASK                                                            0x0000FF00L
26330 #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY_MASK                                                           0x00FF0000L
26331 #define RLC_MEM_SLP_CNTL__RESERVED1_MASK                                                                      0xFF000000L
26332 //SMU_RLC_RESPONSE
26333 #define SMU_RLC_RESPONSE__RESP__SHIFT                                                                         0x0
26334 #define SMU_RLC_RESPONSE__RESP_MASK                                                                           0xFFFFFFFFL
26335 //RLC_RLCV_SAFE_MODE
26336 #define RLC_RLCV_SAFE_MODE__CMD__SHIFT                                                                        0x0
26337 #define RLC_RLCV_SAFE_MODE__MESSAGE__SHIFT                                                                    0x1
26338 #define RLC_RLCV_SAFE_MODE__RESERVED1__SHIFT                                                                  0x5
26339 #define RLC_RLCV_SAFE_MODE__RESPONSE__SHIFT                                                                   0x8
26340 #define RLC_RLCV_SAFE_MODE__RESERVED__SHIFT                                                                   0xc
26341 #define RLC_RLCV_SAFE_MODE__CMD_MASK                                                                          0x00000001L
26342 #define RLC_RLCV_SAFE_MODE__MESSAGE_MASK                                                                      0x0000001EL
26343 #define RLC_RLCV_SAFE_MODE__RESERVED1_MASK                                                                    0x000000E0L
26344 #define RLC_RLCV_SAFE_MODE__RESPONSE_MASK                                                                     0x00000F00L
26345 #define RLC_RLCV_SAFE_MODE__RESERVED_MASK                                                                     0xFFFFF000L
26346 //RLC_SMU_SAFE_MODE
26347 #define RLC_SMU_SAFE_MODE__CMD__SHIFT                                                                         0x0
26348 #define RLC_SMU_SAFE_MODE__MESSAGE__SHIFT                                                                     0x1
26349 #define RLC_SMU_SAFE_MODE__RESERVED1__SHIFT                                                                   0x5
26350 #define RLC_SMU_SAFE_MODE__RESPONSE__SHIFT                                                                    0x8
26351 #define RLC_SMU_SAFE_MODE__RESERVED__SHIFT                                                                    0xc
26352 #define RLC_SMU_SAFE_MODE__CMD_MASK                                                                           0x00000001L
26353 #define RLC_SMU_SAFE_MODE__MESSAGE_MASK                                                                       0x0000001EL
26354 #define RLC_SMU_SAFE_MODE__RESERVED1_MASK                                                                     0x000000E0L
26355 #define RLC_SMU_SAFE_MODE__RESPONSE_MASK                                                                      0x00000F00L
26356 #define RLC_SMU_SAFE_MODE__RESERVED_MASK                                                                      0xFFFFF000L
26357 //RLC_RLCV_COMMAND
26358 #define RLC_RLCV_COMMAND__CMD__SHIFT                                                                          0x0
26359 #define RLC_RLCV_COMMAND__RESERVED__SHIFT                                                                     0x4
26360 #define RLC_RLCV_COMMAND__CMD_MASK                                                                            0x0000000FL
26361 #define RLC_RLCV_COMMAND__RESERVED_MASK                                                                       0xFFFFFFF0L
26362 //RLC_REFCLOCK_TIMESTAMP_LSB
26363 #define RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB__SHIFT                                                      0x0
26364 #define RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB_MASK                                                        0xFFFFFFFFL
26365 //RLC_REFCLOCK_TIMESTAMP_MSB
26366 #define RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB__SHIFT                                                      0x0
26367 #define RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB_MASK                                                        0xFFFFFFFFL
26368 //RLC_GPM_TIMER_INT_0
26369 #define RLC_GPM_TIMER_INT_0__TIMER__SHIFT                                                                     0x0
26370 #define RLC_GPM_TIMER_INT_0__TIMER_MASK                                                                       0xFFFFFFFFL
26371 //RLC_GPM_TIMER_INT_1
26372 #define RLC_GPM_TIMER_INT_1__TIMER__SHIFT                                                                     0x0
26373 #define RLC_GPM_TIMER_INT_1__TIMER_MASK                                                                       0xFFFFFFFFL
26374 //RLC_GPM_TIMER_INT_2
26375 #define RLC_GPM_TIMER_INT_2__TIMER__SHIFT                                                                     0x0
26376 #define RLC_GPM_TIMER_INT_2__TIMER_MASK                                                                       0xFFFFFFFFL
26377 //RLC_GPM_TIMER_CTRL
26378 #define RLC_GPM_TIMER_CTRL__TIMER_0_EN__SHIFT                                                                 0x0
26379 #define RLC_GPM_TIMER_CTRL__TIMER_1_EN__SHIFT                                                                 0x1
26380 #define RLC_GPM_TIMER_CTRL__TIMER_2_EN__SHIFT                                                                 0x2
26381 #define RLC_GPM_TIMER_CTRL__TIMER_3_EN__SHIFT                                                                 0x3
26382 #define RLC_GPM_TIMER_CTRL__RESERVED__SHIFT                                                                   0x4
26383 #define RLC_GPM_TIMER_CTRL__TIMER_0_EN_MASK                                                                   0x00000001L
26384 #define RLC_GPM_TIMER_CTRL__TIMER_1_EN_MASK                                                                   0x00000002L
26385 #define RLC_GPM_TIMER_CTRL__TIMER_2_EN_MASK                                                                   0x00000004L
26386 #define RLC_GPM_TIMER_CTRL__TIMER_3_EN_MASK                                                                   0x00000008L
26387 #define RLC_GPM_TIMER_CTRL__RESERVED_MASK                                                                     0xFFFFFFF0L
26388 //RLC_LB_CNTR_MAX
26389 #define RLC_LB_CNTR_MAX__LB_CNTR_MAX__SHIFT                                                                   0x0
26390 #define RLC_LB_CNTR_MAX__LB_CNTR_MAX_MASK                                                                     0xFFFFFFFFL
26391 //RLC_GPM_TIMER_STAT
26392 #define RLC_GPM_TIMER_STAT__TIMER_0_STAT__SHIFT                                                               0x0
26393 #define RLC_GPM_TIMER_STAT__TIMER_1_STAT__SHIFT                                                               0x1
26394 #define RLC_GPM_TIMER_STAT__TIMER_2_STAT__SHIFT                                                               0x2
26395 #define RLC_GPM_TIMER_STAT__TIMER_3_STAT__SHIFT                                                               0x3
26396 #define RLC_GPM_TIMER_STAT__TIMER_0_ENABLE_SYNC__SHIFT                                                        0x8
26397 #define RLC_GPM_TIMER_STAT__TIMER_1_ENABLE_SYNC__SHIFT                                                        0x9
26398 #define RLC_GPM_TIMER_STAT__TIMER_2_ENABLE_SYNC__SHIFT                                                        0xa
26399 #define RLC_GPM_TIMER_STAT__TIMER_3_ENABLE_SYNC__SHIFT                                                        0xb
26400 #define RLC_GPM_TIMER_STAT__RESERVED__SHIFT                                                                   0xc
26401 #define RLC_GPM_TIMER_STAT__TIMER_0_STAT_MASK                                                                 0x00000001L
26402 #define RLC_GPM_TIMER_STAT__TIMER_1_STAT_MASK                                                                 0x00000002L
26403 #define RLC_GPM_TIMER_STAT__TIMER_2_STAT_MASK                                                                 0x00000004L
26404 #define RLC_GPM_TIMER_STAT__TIMER_3_STAT_MASK                                                                 0x00000008L
26405 #define RLC_GPM_TIMER_STAT__TIMER_0_ENABLE_SYNC_MASK                                                          0x00000100L
26406 #define RLC_GPM_TIMER_STAT__TIMER_1_ENABLE_SYNC_MASK                                                          0x00000200L
26407 #define RLC_GPM_TIMER_STAT__TIMER_2_ENABLE_SYNC_MASK                                                          0x00000400L
26408 #define RLC_GPM_TIMER_STAT__TIMER_3_ENABLE_SYNC_MASK                                                          0x00000800L
26409 #define RLC_GPM_TIMER_STAT__RESERVED_MASK                                                                     0xFFFFF000L
26410 //RLC_GPM_TIMER_INT_3
26411 #define RLC_GPM_TIMER_INT_3__TIMER__SHIFT                                                                     0x0
26412 #define RLC_GPM_TIMER_INT_3__TIMER_MASK                                                                       0xFFFFFFFFL
26413 //RLC_SERDES_WR_NONCU_MASTER_MASK_1
26414 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SE_MASTER_MASK_1__SHIFT                                            0x0
26415 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_MASTER_MASK_1__SHIFT                                            0x10
26416 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_GFX_MASTER_MASK_1__SHIFT                                        0x11
26417 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__TC0_1_MASTER_MASK__SHIFT                                           0x12
26418 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_1__SHIFT                                                  0x13
26419 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE4_MASTER_MASK__SHIFT                                          0x14
26420 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE5_MASTER_MASK__SHIFT                                          0x15
26421 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE6_MASTER_MASK__SHIFT                                          0x16
26422 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE7_MASTER_MASK__SHIFT                                          0x17
26423 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__EA_1_MASTER_MASK__SHIFT                                            0x18
26424 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED__SHIFT                                                    0x19
26425 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SE_MASTER_MASK_1_MASK                                              0x0000FFFFL
26426 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_MASTER_MASK_1_MASK                                              0x00010000L
26427 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_GFX_MASTER_MASK_1_MASK                                          0x00020000L
26428 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__TC0_1_MASTER_MASK_MASK                                             0x00040000L
26429 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_1_MASK                                                    0x00080000L
26430 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE4_MASTER_MASK_MASK                                            0x00100000L
26431 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE5_MASTER_MASK_MASK                                            0x00200000L
26432 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE6_MASTER_MASK_MASK                                            0x00400000L
26433 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE7_MASTER_MASK_MASK                                            0x00800000L
26434 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__EA_1_MASTER_MASK_MASK                                              0x01000000L
26435 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_MASK                                                      0xFE000000L
26436 //RLC_SERDES_NONCU_MASTER_BUSY_1
26437 #define RLC_SERDES_NONCU_MASTER_BUSY_1__SE_MASTER_BUSY_1__SHIFT                                               0x0
26438 #define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_MASTER_BUSY_1__SHIFT                                               0x10
26439 #define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_GFX_MASTER_BUSY_1__SHIFT                                           0x11
26440 #define RLC_SERDES_NONCU_MASTER_BUSY_1__TC0_MASTER_BUSY_1__SHIFT                                              0x12
26441 #define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_1__SHIFT                                                     0x13
26442 #define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE4_MASTER_BUSY__SHIFT                                             0x14
26443 #define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE5_MASTER_BUSY__SHIFT                                             0x15
26444 #define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE6_MASTER_BUSY__SHIFT                                             0x16
26445 #define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE7_MASTER_BUSY__SHIFT                                             0x17
26446 #define RLC_SERDES_NONCU_MASTER_BUSY_1__EA_1_MASTER_BUSY__SHIFT                                               0x18
26447 #define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED__SHIFT                                                       0x19
26448 #define RLC_SERDES_NONCU_MASTER_BUSY_1__SE_MASTER_BUSY_1_MASK                                                 0x0000FFFFL
26449 #define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_MASTER_BUSY_1_MASK                                                 0x00010000L
26450 #define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_GFX_MASTER_BUSY_1_MASK                                             0x00020000L
26451 #define RLC_SERDES_NONCU_MASTER_BUSY_1__TC0_MASTER_BUSY_1_MASK                                                0x00040000L
26452 #define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_1_MASK                                                       0x00080000L
26453 #define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE4_MASTER_BUSY_MASK                                               0x00100000L
26454 #define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE5_MASTER_BUSY_MASK                                               0x00200000L
26455 #define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE6_MASTER_BUSY_MASK                                               0x00400000L
26456 #define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE7_MASTER_BUSY_MASK                                               0x00800000L
26457 #define RLC_SERDES_NONCU_MASTER_BUSY_1__EA_1_MASTER_BUSY_MASK                                                 0x01000000L
26458 #define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_MASK                                                         0xFE000000L
26459 //RLC_INT_STAT
26460 #define RLC_INT_STAT__LAST_CP_RLC_INT_ID__SHIFT                                                               0x0
26461 #define RLC_INT_STAT__CP_RLC_INT_PENDING__SHIFT                                                               0x8
26462 #define RLC_INT_STAT__RESERVED__SHIFT                                                                         0x9
26463 #define RLC_INT_STAT__LAST_CP_RLC_INT_ID_MASK                                                                 0x000000FFL
26464 #define RLC_INT_STAT__CP_RLC_INT_PENDING_MASK                                                                 0x00000100L
26465 #define RLC_INT_STAT__RESERVED_MASK                                                                           0xFFFFFE00L
26466 //RLC_LB_CNTL
26467 #define RLC_LB_CNTL__LOAD_BALANCE_ENABLE__SHIFT                                                               0x0
26468 #define RLC_LB_CNTL__LB_CNT_CP_BUSY__SHIFT                                                                    0x1
26469 #define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE__SHIFT                                                                0x2
26470 #define RLC_LB_CNTL__LB_CNT_REG_INC__SHIFT                                                                    0x3
26471 #define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST__SHIFT                                                             0x4
26472 #define RLC_LB_CNTL__RESERVED__SHIFT                                                                          0xc
26473 #define RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK                                                                 0x00000001L
26474 #define RLC_LB_CNTL__LB_CNT_CP_BUSY_MASK                                                                      0x00000002L
26475 #define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK                                                                  0x00000004L
26476 #define RLC_LB_CNTL__LB_CNT_REG_INC_MASK                                                                      0x00000008L
26477 #define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST_MASK                                                               0x00000FF0L
26478 #define RLC_LB_CNTL__RESERVED_MASK                                                                            0xFFFFF000L
26479 //RLC_MGCG_CTRL
26480 #define RLC_MGCG_CTRL__MGCG_EN__SHIFT                                                                         0x0
26481 #define RLC_MGCG_CTRL__SILICON_EN__SHIFT                                                                      0x1
26482 #define RLC_MGCG_CTRL__SIMULATION_EN__SHIFT                                                                   0x2
26483 #define RLC_MGCG_CTRL__ON_DELAY__SHIFT                                                                        0x3
26484 #define RLC_MGCG_CTRL__OFF_HYSTERESIS__SHIFT                                                                  0x7
26485 #define RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL__SHIFT                                                            0xf
26486 #define RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL__SHIFT                                                            0x10
26487 #define RLC_MGCG_CTRL__SPARE__SHIFT                                                                           0x11
26488 #define RLC_MGCG_CTRL__MGCG_EN_MASK                                                                           0x00000001L
26489 #define RLC_MGCG_CTRL__SILICON_EN_MASK                                                                        0x00000002L
26490 #define RLC_MGCG_CTRL__SIMULATION_EN_MASK                                                                     0x00000004L
26491 #define RLC_MGCG_CTRL__ON_DELAY_MASK                                                                          0x00000078L
26492 #define RLC_MGCG_CTRL__OFF_HYSTERESIS_MASK                                                                    0x00007F80L
26493 #define RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL_MASK                                                              0x00008000L
26494 #define RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL_MASK                                                              0x00010000L
26495 #define RLC_MGCG_CTRL__SPARE_MASK                                                                             0xFFFE0000L
26496 //RLC_LB_CNTR_INIT
26497 #define RLC_LB_CNTR_INIT__LB_CNTR_INIT__SHIFT                                                                 0x0
26498 #define RLC_LB_CNTR_INIT__LB_CNTR_INIT_MASK                                                                   0xFFFFFFFFL
26499 //RLC_LOAD_BALANCE_CNTR
26500 #define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR__SHIFT                                                   0x0
26501 #define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR_MASK                                                     0xFFFFFFFFL
26502 //RLC_JUMP_TABLE_RESTORE
26503 #define RLC_JUMP_TABLE_RESTORE__ADDR__SHIFT                                                                   0x0
26504 #define RLC_JUMP_TABLE_RESTORE__ADDR_MASK                                                                     0xFFFFFFFFL
26505 //RLC_PG_DELAY_2
26506 #define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE__SHIFT                                                           0x0
26507 #define RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT                                                               0x8
26508 #define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE__SHIFT                                                            0x10
26509 #define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE_MASK                                                             0x000000FFL
26510 #define RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK                                                                 0x0000FF00L
26511 #define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE_MASK                                                              0xFFFF0000L
26512 //RLC_GPU_CLOCK_COUNT_LSB
26513 #define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB__SHIFT                                                        0x0
26514 #define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB_MASK                                                          0xFFFFFFFFL
26515 //RLC_GPU_CLOCK_COUNT_MSB
26516 #define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB__SHIFT                                                        0x0
26517 #define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB_MASK                                                          0xFFFFFFFFL
26518 //RLC_CAPTURE_GPU_CLOCK_COUNT
26519 #define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE__SHIFT                                                           0x0
26520 #define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED__SHIFT                                                          0x1
26521 #define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE_MASK                                                             0x00000001L
26522 #define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED_MASK                                                            0xFFFFFFFEL
26523 //RLC_UCODE_CNTL
26524 #define RLC_UCODE_CNTL__RLC_UCODE_FLAGS__SHIFT                                                                0x0
26525 #define RLC_UCODE_CNTL__RLC_UCODE_FLAGS_MASK                                                                  0xFFFFFFFFL
26526 //RLC_GPM_THREAD_RESET
26527 #define RLC_GPM_THREAD_RESET__THREAD0_RESET__SHIFT                                                            0x0
26528 #define RLC_GPM_THREAD_RESET__THREAD1_RESET__SHIFT                                                            0x1
26529 #define RLC_GPM_THREAD_RESET__THREAD2_RESET__SHIFT                                                            0x2
26530 #define RLC_GPM_THREAD_RESET__THREAD3_RESET__SHIFT                                                            0x3
26531 #define RLC_GPM_THREAD_RESET__RESERVED__SHIFT                                                                 0x4
26532 #define RLC_GPM_THREAD_RESET__THREAD0_RESET_MASK                                                              0x00000001L
26533 #define RLC_GPM_THREAD_RESET__THREAD1_RESET_MASK                                                              0x00000002L
26534 #define RLC_GPM_THREAD_RESET__THREAD2_RESET_MASK                                                              0x00000004L
26535 #define RLC_GPM_THREAD_RESET__THREAD3_RESET_MASK                                                              0x00000008L
26536 #define RLC_GPM_THREAD_RESET__RESERVED_MASK                                                                   0xFFFFFFF0L
26537 //RLC_GPM_CP_DMA_COMPLETE_T0
26538 #define RLC_GPM_CP_DMA_COMPLETE_T0__DATA__SHIFT                                                               0x0
26539 #define RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED__SHIFT                                                           0x1
26540 #define RLC_GPM_CP_DMA_COMPLETE_T0__DATA_MASK                                                                 0x00000001L
26541 #define RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED_MASK                                                             0xFFFFFFFEL
26542 //RLC_GPM_CP_DMA_COMPLETE_T1
26543 #define RLC_GPM_CP_DMA_COMPLETE_T1__DATA__SHIFT                                                               0x0
26544 #define RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED__SHIFT                                                           0x1
26545 #define RLC_GPM_CP_DMA_COMPLETE_T1__DATA_MASK                                                                 0x00000001L
26546 #define RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED_MASK                                                             0xFFFFFFFEL
26547 //RLC_FIREWALL_VIOLATION
26548 #define RLC_FIREWALL_VIOLATION__ADDR__SHIFT                                                                   0x0
26549 #define RLC_FIREWALL_VIOLATION__ADDR_MASK                                                                     0xFFFFFFFFL
26550 //RLC_CLK_COUNT_GFXCLK_LSB
26551 #define RLC_CLK_COUNT_GFXCLK_LSB__COUNTER__SHIFT                                                              0x0
26552 #define RLC_CLK_COUNT_GFXCLK_LSB__COUNTER_MASK                                                                0xFFFFFFFFL
26553 //RLC_CLK_COUNT_GFXCLK_MSB
26554 #define RLC_CLK_COUNT_GFXCLK_MSB__COUNTER__SHIFT                                                              0x0
26555 #define RLC_CLK_COUNT_GFXCLK_MSB__COUNTER_MASK                                                                0xFFFFFFFFL
26556 //RLC_CLK_COUNT_REFCLK_LSB
26557 #define RLC_CLK_COUNT_REFCLK_LSB__COUNTER__SHIFT                                                              0x0
26558 #define RLC_CLK_COUNT_REFCLK_LSB__COUNTER_MASK                                                                0xFFFFFFFFL
26559 //RLC_CLK_COUNT_REFCLK_MSB
26560 #define RLC_CLK_COUNT_REFCLK_MSB__COUNTER__SHIFT                                                              0x0
26561 #define RLC_CLK_COUNT_REFCLK_MSB__COUNTER_MASK                                                                0xFFFFFFFFL
26562 //RLC_CLK_COUNT_CTRL
26563 #define RLC_CLK_COUNT_CTRL__GFXCLK_RUN__SHIFT                                                                 0x0
26564 #define RLC_CLK_COUNT_CTRL__GFXCLK_RESET__SHIFT                                                               0x1
26565 #define RLC_CLK_COUNT_CTRL__GFXCLK_SAMPLE__SHIFT                                                              0x2
26566 #define RLC_CLK_COUNT_CTRL__REFCLK_RUN__SHIFT                                                                 0x3
26567 #define RLC_CLK_COUNT_CTRL__REFCLK_RESET__SHIFT                                                               0x4
26568 #define RLC_CLK_COUNT_CTRL__REFCLK_SAMPLE__SHIFT                                                              0x5
26569 #define RLC_CLK_COUNT_CTRL__GFXCLK_RUN_MASK                                                                   0x00000001L
26570 #define RLC_CLK_COUNT_CTRL__GFXCLK_RESET_MASK                                                                 0x00000002L
26571 #define RLC_CLK_COUNT_CTRL__GFXCLK_SAMPLE_MASK                                                                0x00000004L
26572 #define RLC_CLK_COUNT_CTRL__REFCLK_RUN_MASK                                                                   0x00000008L
26573 #define RLC_CLK_COUNT_CTRL__REFCLK_RESET_MASK                                                                 0x00000010L
26574 #define RLC_CLK_COUNT_CTRL__REFCLK_SAMPLE_MASK                                                                0x00000020L
26575 //RLC_CLK_COUNT_STAT
26576 #define RLC_CLK_COUNT_STAT__GFXCLK_VALID__SHIFT                                                               0x0
26577 #define RLC_CLK_COUNT_STAT__REFCLK_VALID__SHIFT                                                               0x1
26578 #define RLC_CLK_COUNT_STAT__REFCLK_RUN_RESYNC__SHIFT                                                          0x2
26579 #define RLC_CLK_COUNT_STAT__REFCLK_RESET_RESYNC__SHIFT                                                        0x3
26580 #define RLC_CLK_COUNT_STAT__REFCLK_SAMPLE_RESYNC__SHIFT                                                       0x4
26581 #define RLC_CLK_COUNT_STAT__RESERVED__SHIFT                                                                   0x5
26582 #define RLC_CLK_COUNT_STAT__GFXCLK_VALID_MASK                                                                 0x00000001L
26583 #define RLC_CLK_COUNT_STAT__REFCLK_VALID_MASK                                                                 0x00000002L
26584 #define RLC_CLK_COUNT_STAT__REFCLK_RUN_RESYNC_MASK                                                            0x00000004L
26585 #define RLC_CLK_COUNT_STAT__REFCLK_RESET_RESYNC_MASK                                                          0x00000008L
26586 #define RLC_CLK_COUNT_STAT__REFCLK_SAMPLE_RESYNC_MASK                                                         0x00000010L
26587 #define RLC_CLK_COUNT_STAT__RESERVED_MASK                                                                     0xFFFFFFE0L
26588 //RLC_GPM_STAT
26589 #define RLC_GPM_STAT__RLC_BUSY__SHIFT                                                                         0x0
26590 #define RLC_GPM_STAT__GFX_POWER_STATUS__SHIFT                                                                 0x1
26591 #define RLC_GPM_STAT__GFX_CLOCK_STATUS__SHIFT                                                                 0x2
26592 #define RLC_GPM_STAT__GFX_LS_STATUS__SHIFT                                                                    0x3
26593 #define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS__SHIFT                                                        0x4
26594 #define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED__SHIFT                                                        0x5
26595 #define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED__SHIFT                                                        0x6
26596 #define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED__SHIFT                                                         0x7
26597 #define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED__SHIFT                                                         0x8
26598 #define RLC_GPM_STAT__SAVING_REGISTERS__SHIFT                                                                 0x9
26599 #define RLC_GPM_STAT__RESTORING_REGISTERS__SHIFT                                                              0xa
26600 #define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE__SHIFT                                                0xb
26601 #define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE__SHIFT                                                  0xc
26602 #define RLC_GPM_STAT__STATIC_CU_POWERING_UP__SHIFT                                                            0xd
26603 #define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN__SHIFT                                                          0xe
26604 #define RLC_GPM_STAT__DYN_CU_POWERING_UP__SHIFT                                                               0xf
26605 #define RLC_GPM_STAT__DYN_CU_POWERING_DOWN__SHIFT                                                             0x10
26606 #define RLC_GPM_STAT__ABORTED_PD_SEQUENCE__SHIFT                                                              0x11
26607 #define RLC_GPM_STAT__CMP_power_status__SHIFT                                                                 0x12
26608 #define RLC_GPM_STAT__RESERVED_1__SHIFT                                                                       0x13
26609 #define RLC_GPM_STAT__MGCG_OVERRIDE_STATUS__SHIFT                                                             0x15
26610 #define RLC_GPM_STAT__RLC_EXEC_ROM_CODE__SHIFT                                                                0x16
26611 #define RLC_GPM_STAT__FGCG_OVERRIDE_STATUS__SHIFT                                                             0x17
26612 #define RLC_GPM_STAT__PG_ERROR_STATUS__SHIFT                                                                  0x18
26613 #define RLC_GPM_STAT__RLC_BUSY_MASK                                                                           0x00000001L
26614 #define RLC_GPM_STAT__GFX_POWER_STATUS_MASK                                                                   0x00000002L
26615 #define RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK                                                                   0x00000004L
26616 #define RLC_GPM_STAT__GFX_LS_STATUS_MASK                                                                      0x00000008L
26617 #define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK                                                          0x00000010L
26618 #define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED_MASK                                                          0x00000020L
26619 #define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED_MASK                                                          0x00000040L
26620 #define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED_MASK                                                           0x00000080L
26621 #define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED_MASK                                                           0x00000100L
26622 #define RLC_GPM_STAT__SAVING_REGISTERS_MASK                                                                   0x00000200L
26623 #define RLC_GPM_STAT__RESTORING_REGISTERS_MASK                                                                0x00000400L
26624 #define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE_MASK                                                  0x00000800L
26625 #define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE_MASK                                                    0x00001000L
26626 #define RLC_GPM_STAT__STATIC_CU_POWERING_UP_MASK                                                              0x00002000L
26627 #define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN_MASK                                                            0x00004000L
26628 #define RLC_GPM_STAT__DYN_CU_POWERING_UP_MASK                                                                 0x00008000L
26629 #define RLC_GPM_STAT__DYN_CU_POWERING_DOWN_MASK                                                               0x00010000L
26630 #define RLC_GPM_STAT__ABORTED_PD_SEQUENCE_MASK                                                                0x00020000L
26631 #define RLC_GPM_STAT__CMP_power_status_MASK                                                                   0x00040000L
26632 #define RLC_GPM_STAT__RESERVED_1_MASK                                                                         0x00180000L
26633 #define RLC_GPM_STAT__MGCG_OVERRIDE_STATUS_MASK                                                               0x00200000L
26634 #define RLC_GPM_STAT__RLC_EXEC_ROM_CODE_MASK                                                                  0x00400000L
26635 #define RLC_GPM_STAT__FGCG_OVERRIDE_STATUS_MASK                                                               0x00800000L
26636 #define RLC_GPM_STAT__PG_ERROR_STATUS_MASK                                                                    0xFF000000L
26637 //RLC_GPU_CLOCK_32_RES_SEL
26638 #define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT                                                              0x0
26639 #define RLC_GPU_CLOCK_32_RES_SEL__RESERVED__SHIFT                                                             0x6
26640 #define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK                                                                0x0000003FL
26641 #define RLC_GPU_CLOCK_32_RES_SEL__RESERVED_MASK                                                               0xFFFFFFC0L
26642 //RLC_GPU_CLOCK_32
26643 #define RLC_GPU_CLOCK_32__GPU_CLOCK_32__SHIFT                                                                 0x0
26644 #define RLC_GPU_CLOCK_32__GPU_CLOCK_32_MASK                                                                   0xFFFFFFFFL
26645 //RLC_PG_CNTL
26646 #define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE__SHIFT                                                           0x0
26647 #define RLC_PG_CNTL__GFX_POWER_GATING_SRC__SHIFT                                                              0x1
26648 #define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE__SHIFT                                                              0x2
26649 #define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE__SHIFT                                                           0x3
26650 #define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE__SHIFT                                                            0x4
26651 #define RLC_PG_CNTL__RESERVED__SHIFT                                                                          0x5
26652 #define RLC_PG_CNTL__PG_OVERRIDE__SHIFT                                                                       0xe
26653 #define RLC_PG_CNTL__CP_PG_DISABLE__SHIFT                                                                     0xf
26654 #define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE__SHIFT                                                             0x10
26655 #define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE__SHIFT                                                     0x11
26656 #define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE__SHIFT                                                     0x12
26657 #define RLC_PG_CNTL__RESERVED1__SHIFT                                                                         0x13
26658 #define RLC_PG_CNTL__Ultra_Low_Voltage_Enable__SHIFT                                                          0x15
26659 #define RLC_PG_CNTL__RESERVED2__SHIFT                                                                         0x16
26660 #define RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE__SHIFT                                                             0x17
26661 #define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK                                                             0x00000001L
26662 #define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK                                                                0x00000002L
26663 #define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK                                                                0x00000004L
26664 #define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK                                                             0x00000008L
26665 #define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK                                                              0x00000010L
26666 #define RLC_PG_CNTL__RESERVED_MASK                                                                            0x00003FE0L
26667 #define RLC_PG_CNTL__PG_OVERRIDE_MASK                                                                         0x00004000L
26668 #define RLC_PG_CNTL__CP_PG_DISABLE_MASK                                                                       0x00008000L
26669 #define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE_MASK                                                               0x00010000L
26670 #define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK                                                       0x00020000L
26671 #define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK                                                       0x00040000L
26672 #define RLC_PG_CNTL__RESERVED1_MASK                                                                           0x00180000L
26673 #define RLC_PG_CNTL__Ultra_Low_Voltage_Enable_MASK                                                            0x00200000L
26674 #define RLC_PG_CNTL__RESERVED2_MASK                                                                           0x00400000L
26675 #define RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK                                                               0x00800000L
26676 //RLC_GPM_THREAD_PRIORITY
26677 #define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY__SHIFT                                                      0x0
26678 #define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY__SHIFT                                                      0x8
26679 #define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY__SHIFT                                                      0x10
26680 #define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY__SHIFT                                                      0x18
26681 #define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY_MASK                                                        0x000000FFL
26682 #define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY_MASK                                                        0x0000FF00L
26683 #define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY_MASK                                                        0x00FF0000L
26684 #define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY_MASK                                                        0xFF000000L
26685 //RLC_GPM_THREAD_ENABLE
26686 #define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE__SHIFT                                                          0x0
26687 #define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE__SHIFT                                                          0x1
26688 #define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE__SHIFT                                                          0x2
26689 #define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE__SHIFT                                                          0x3
26690 #define RLC_GPM_THREAD_ENABLE__RESERVED__SHIFT                                                                0x4
26691 #define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE_MASK                                                            0x00000001L
26692 #define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE_MASK                                                            0x00000002L
26693 #define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE_MASK                                                            0x00000004L
26694 #define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE_MASK                                                            0x00000008L
26695 #define RLC_GPM_THREAD_ENABLE__RESERVED_MASK                                                                  0xFFFFFFF0L
26696 //RLC_CGTT_MGCG_OVERRIDE
26697 #define RLC_CGTT_MGCG_OVERRIDE__RESERVED_0__SHIFT                                                             0x0
26698 #define RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE__SHIFT                                                 0x1
26699 #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE__SHIFT                                                    0x2
26700 #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE__SHIFT                                                    0x3
26701 #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE__SHIFT                                                    0x4
26702 #define RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE__SHIFT                                                0x5
26703 #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE__SHIFT                                                    0x6
26704 #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE__SHIFT                                                0x7
26705 #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE__SHIFT                                                    0x8
26706 #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE__SHIFT                                                0x9
26707 #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_PERF_CLK_EN__SHIFT                                                      0xa
26708 #define RLC_CGTT_MGCG_OVERRIDE__RESERVED_15_11__SHIFT                                                         0xb
26709 #define RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY__SHIFT                                                     0x10
26710 #define RLC_CGTT_MGCG_OVERRIDE__RESERVED_31_17__SHIFT                                                         0x11
26711 #define RLC_CGTT_MGCG_OVERRIDE__RESERVED_0_MASK                                                               0x00000001L
26712 #define RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK                                                   0x00000002L
26713 #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK                                                      0x00000004L
26714 #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK                                                      0x00000008L
26715 #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK                                                      0x00000010L
26716 #define RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK                                                  0x00000020L
26717 #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK                                                      0x00000040L
26718 #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK                                                  0x00000080L
26719 #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK                                                      0x00000100L
26720 #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK                                                  0x00000200L
26721 #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_PERF_CLK_EN_MASK                                                        0x00000400L
26722 #define RLC_CGTT_MGCG_OVERRIDE__RESERVED_15_11_MASK                                                           0x0000F800L
26723 #define RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK                                                       0x00010000L
26724 #define RLC_CGTT_MGCG_OVERRIDE__RESERVED_31_17_MASK                                                           0xFFFE0000L
26725 //RLC_CGCG_CGLS_CTRL
26726 #define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT                                                                    0x0
26727 #define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT                                                                    0x1
26728 #define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT                                                   0x2
26729 #define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT                                                    0x8
26730 #define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER__SHIFT                                                            0x1b
26731 #define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL__SHIFT                                                              0x1c
26732 #define RLC_CGCG_CGLS_CTRL__SLEEP_MODE__SHIFT                                                                 0x1d
26733 #define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN__SHIFT                                                             0x1f
26734 #define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK                                                                      0x00000001L
26735 #define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK                                                                      0x00000002L
26736 #define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK                                                     0x000000FCL
26737 #define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK                                                      0x07FFFF00L
26738 #define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER_MASK                                                              0x08000000L
26739 #define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK                                                                0x10000000L
26740 #define RLC_CGCG_CGLS_CTRL__SLEEP_MODE_MASK                                                                   0x60000000L
26741 #define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN_MASK                                                               0x80000000L
26742 //RLC_CGCG_RAMP_CTRL
26743 #define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT__SHIFT                                                        0x0
26744 #define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT__SHIFT                                                         0x4
26745 #define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT__SHIFT                                                          0x8
26746 #define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT__SHIFT                                                           0xc
26747 #define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT__SHIFT                                                             0x10
26748 #define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT__SHIFT                                                            0x1c
26749 #define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT_MASK                                                          0x0000000FL
26750 #define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT_MASK                                                           0x000000F0L
26751 #define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT_MASK                                                            0x00000F00L
26752 #define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT_MASK                                                             0x0000F000L
26753 #define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT_MASK                                                               0x0FFF0000L
26754 #define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT_MASK                                                              0xF0000000L
26755 //RLC_DYN_PG_STATUS
26756 #define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK__SHIFT                                                           0x0
26757 #define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK_MASK                                                             0xFFFFFFFFL
26758 //RLC_DYN_PG_REQUEST
26759 #define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK__SHIFT                                                         0x0
26760 #define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK_MASK                                                           0xFFFFFFFFL
26761 //RLC_PG_DELAY
26762 #define RLC_PG_DELAY__POWER_UP_DELAY__SHIFT                                                                   0x0
26763 #define RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT                                                                 0x8
26764 #define RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT                                                              0x10
26765 #define RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT                                                                  0x18
26766 #define RLC_PG_DELAY__POWER_UP_DELAY_MASK                                                                     0x000000FFL
26767 #define RLC_PG_DELAY__POWER_DOWN_DELAY_MASK                                                                   0x0000FF00L
26768 #define RLC_PG_DELAY__CMD_PROPAGATE_DELAY_MASK                                                                0x00FF0000L
26769 #define RLC_PG_DELAY__MEM_SLEEP_DELAY_MASK                                                                    0xFF000000L
26770 //RLC_CU_STATUS
26771 #define RLC_CU_STATUS__WORK_PENDING__SHIFT                                                                    0x0
26772 #define RLC_CU_STATUS__WORK_PENDING_MASK                                                                      0xFFFFFFFFL
26773 //RLC_LB_INIT_CU_MASK
26774 #define RLC_LB_INIT_CU_MASK__INIT_CU_MASK__SHIFT                                                              0x0
26775 #define RLC_LB_INIT_CU_MASK__INIT_CU_MASK_MASK                                                                0xFFFFFFFFL
26776 //RLC_LB_ALWAYS_ACTIVE_CU_MASK
26777 #define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK__SHIFT                                            0x0
26778 #define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK_MASK                                              0xFFFFFFFFL
26779 //RLC_LB_PARAMS
26780 #define RLC_LB_PARAMS__SKIP_L2_CHECK__SHIFT                                                                   0x0
26781 #define RLC_LB_PARAMS__FIFO_SAMPLES__SHIFT                                                                    0x1
26782 #define RLC_LB_PARAMS__PG_IDLE_SAMPLES__SHIFT                                                                 0x8
26783 #define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL__SHIFT                                                         0x10
26784 #define RLC_LB_PARAMS__SKIP_L2_CHECK_MASK                                                                     0x00000001L
26785 #define RLC_LB_PARAMS__FIFO_SAMPLES_MASK                                                                      0x000000FEL
26786 #define RLC_LB_PARAMS__PG_IDLE_SAMPLES_MASK                                                                   0x0000FF00L
26787 #define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL_MASK                                                           0xFFFF0000L
26788 //RLC_THREAD1_DELAY
26789 #define RLC_THREAD1_DELAY__CU_IDEL_DELAY__SHIFT                                                               0x0
26790 #define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY__SHIFT                                                       0x8
26791 #define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY__SHIFT                                                       0x10
26792 #define RLC_THREAD1_DELAY__SPARE__SHIFT                                                                       0x18
26793 #define RLC_THREAD1_DELAY__CU_IDEL_DELAY_MASK                                                                 0x000000FFL
26794 #define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY_MASK                                                         0x0000FF00L
26795 #define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY_MASK                                                         0x00FF0000L
26796 #define RLC_THREAD1_DELAY__SPARE_MASK                                                                         0xFF000000L
26797 //RLC_PG_ALWAYS_ON_CU_MASK
26798 #define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK__SHIFT                                                          0x0
26799 #define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK_MASK                                                            0xFFFFFFFFL
26800 //RLC_MAX_PG_CU
26801 #define RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT                                                               0x0
26802 #define RLC_MAX_PG_CU__SPARE__SHIFT                                                                           0x8
26803 #define RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK                                                                 0x000000FFL
26804 #define RLC_MAX_PG_CU__SPARE_MASK                                                                             0xFFFFFF00L
26805 //RLC_AUTO_PG_CTRL
26806 #define RLC_AUTO_PG_CTRL__AUTO_PG_EN__SHIFT                                                                   0x0
26807 #define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN__SHIFT                                                0x1
26808 #define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN__SHIFT                                                              0x2
26809 #define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT                                             0x3
26810 #define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD__SHIFT                                             0x13
26811 #define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK                                                                     0x00000001L
26812 #define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN_MASK                                                  0x00000002L
26813 #define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK                                                                0x00000004L
26814 #define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK                                               0x0007FFF8L
26815 #define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK                                               0xFFF80000L
26816 //RLC_SMU_GRBM_REG_SAVE_CTRL
26817 #define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE__SHIFT                                                0x0
26818 #define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE__SHIFT                                                              0x1
26819 #define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE_MASK                                                  0x00000001L
26820 #define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE_MASK                                                                0xFFFFFFFEL
26821 //RLC_SERDES_RD_PENDING
26822 #define RLC_SERDES_RD_PENDING__RD_PENDING__SHIFT                                                              0x0
26823 #define RLC_SERDES_RD_PENDING__RD_PENDING_MASK                                                                0x00000001L
26824 //RLC_SERDES_RD_MASTER_INDEX
26825 #define RLC_SERDES_RD_MASTER_INDEX__CU_ID__SHIFT                                                              0x0
26826 #define RLC_SERDES_RD_MASTER_INDEX__SH_ID__SHIFT                                                              0x4
26827 #define RLC_SERDES_RD_MASTER_INDEX__SE_ID__SHIFT                                                              0x6
26828 #define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID__SHIFT                                                        0x9
26829 #define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU__SHIFT                                                           0xc
26830 #define RLC_SERDES_RD_MASTER_INDEX__NON_SE__SHIFT                                                             0xd
26831 #define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID__SHIFT                                                        0x11
26832 #define RLC_SERDES_RD_MASTER_INDEX__SPARE__SHIFT                                                              0x13
26833 #define RLC_SERDES_RD_MASTER_INDEX__CU_ID_MASK                                                                0x0000000FL
26834 #define RLC_SERDES_RD_MASTER_INDEX__SH_ID_MASK                                                                0x00000030L
26835 #define RLC_SERDES_RD_MASTER_INDEX__SE_ID_MASK                                                                0x000001C0L
26836 #define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID_MASK                                                          0x00000E00L
26837 #define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_MASK                                                             0x00001000L
26838 #define RLC_SERDES_RD_MASTER_INDEX__NON_SE_MASK                                                               0x0001E000L
26839 #define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID_MASK                                                          0x00060000L
26840 #define RLC_SERDES_RD_MASTER_INDEX__SPARE_MASK                                                                0xFFF80000L
26841 //RLC_SERDES_RD_DATA_0
26842 #define RLC_SERDES_RD_DATA_0__DATA__SHIFT                                                                     0x0
26843 #define RLC_SERDES_RD_DATA_0__DATA_MASK                                                                       0xFFFFFFFFL
26844 //RLC_SERDES_RD_DATA_1
26845 #define RLC_SERDES_RD_DATA_1__DATA__SHIFT                                                                     0x0
26846 #define RLC_SERDES_RD_DATA_1__DATA_MASK                                                                       0xFFFFFFFFL
26847 //RLC_SERDES_RD_DATA_2
26848 #define RLC_SERDES_RD_DATA_2__DATA__SHIFT                                                                     0x0
26849 #define RLC_SERDES_RD_DATA_2__DATA_MASK                                                                       0xFFFFFFFFL
26850 //RLC_SERDES_WR_CU_MASTER_MASK
26851 #define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK__SHIFT                                                      0x0
26852 #define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK_MASK                                                        0xFFFFFFFFL
26853 //RLC_SERDES_WR_NONCU_MASTER_MASK
26854 #define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK__SHIFT                                                0x0
26855 #define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK__SHIFT                                                0x10
26856 #define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK__SHIFT                                            0x11
26857 #define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK__SHIFT                                               0x12
26858 #define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK__SHIFT                                               0x13
26859 #define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK__SHIFT                                            0x14
26860 #define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK__SHIFT                                            0x15
26861 #define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK__SHIFT                                            0x16
26862 #define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK__SHIFT                                            0x17
26863 #define RLC_SERDES_WR_NONCU_MASTER_MASK__EA_0_MASTER_MASK__SHIFT                                              0x18
26864 #define RLC_SERDES_WR_NONCU_MASTER_MASK__TC2_MASTER_MASK__SHIFT                                               0x19
26865 #define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED__SHIFT                                                      0x1a
26866 #define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK_MASK                                                  0x0000FFFFL
26867 #define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK_MASK                                                  0x00010000L
26868 #define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK_MASK                                              0x00020000L
26869 #define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK_MASK                                                 0x00040000L
26870 #define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK_MASK                                                 0x00080000L
26871 #define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK_MASK                                              0x00100000L
26872 #define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK_MASK                                              0x00200000L
26873 #define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK_MASK                                              0x00400000L
26874 #define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK_MASK                                              0x00800000L
26875 #define RLC_SERDES_WR_NONCU_MASTER_MASK__EA_0_MASTER_MASK_MASK                                                0x01000000L
26876 #define RLC_SERDES_WR_NONCU_MASTER_MASK__TC2_MASTER_MASK_MASK                                                 0x02000000L
26877 #define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED_MASK                                                        0xFC000000L
26878 //RLC_SERDES_WR_CTRL
26879 #define RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT                                                                   0x0
26880 #define RLC_SERDES_WR_CTRL__POWER_DOWN__SHIFT                                                                 0x8
26881 #define RLC_SERDES_WR_CTRL__POWER_UP__SHIFT                                                                   0x9
26882 #define RLC_SERDES_WR_CTRL__P1_SELECT__SHIFT                                                                  0xa
26883 #define RLC_SERDES_WR_CTRL__P2_SELECT__SHIFT                                                                  0xb
26884 #define RLC_SERDES_WR_CTRL__WRITE_COMMAND__SHIFT                                                              0xc
26885 #define RLC_SERDES_WR_CTRL__READ_COMMAND__SHIFT                                                               0xd
26886 #define RLC_SERDES_WR_CTRL__RDDATA_RESET__SHIFT                                                               0xe
26887 #define RLC_SERDES_WR_CTRL__SHORT_FORMAT__SHIFT                                                               0xf
26888 #define RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT                                                                   0x10
26889 #define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE__SHIFT                                                              0x1a
26890 #define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR__SHIFT                                                              0x1b
26891 #define RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT                                                                   0x1c
26892 #define RLC_SERDES_WR_CTRL__BPM_ADDR_MASK                                                                     0x000000FFL
26893 #define RLC_SERDES_WR_CTRL__POWER_DOWN_MASK                                                                   0x00000100L
26894 #define RLC_SERDES_WR_CTRL__POWER_UP_MASK                                                                     0x00000200L
26895 #define RLC_SERDES_WR_CTRL__P1_SELECT_MASK                                                                    0x00000400L
26896 #define RLC_SERDES_WR_CTRL__P2_SELECT_MASK                                                                    0x00000800L
26897 #define RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK                                                                0x00001000L
26898 #define RLC_SERDES_WR_CTRL__READ_COMMAND_MASK                                                                 0x00002000L
26899 #define RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK                                                                 0x00004000L
26900 #define RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK                                                                 0x00008000L
26901 #define RLC_SERDES_WR_CTRL__BPM_DATA_MASK                                                                     0x03FF0000L
26902 #define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK                                                                0x04000000L
26903 #define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR_MASK                                                                0x08000000L
26904 #define RLC_SERDES_WR_CTRL__REG_ADDR_MASK                                                                     0xF0000000L
26905 //RLC_SERDES_WR_DATA
26906 #define RLC_SERDES_WR_DATA__DATA__SHIFT                                                                       0x0
26907 #define RLC_SERDES_WR_DATA__DATA_MASK                                                                         0xFFFFFFFFL
26908 //RLC_SERDES_CU_MASTER_BUSY
26909 #define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY__SHIFT                                                           0x0
26910 #define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY_MASK                                                             0xFFFFFFFFL
26911 //RLC_SERDES_NONCU_MASTER_BUSY
26912 #define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY__SHIFT                                                   0x0
26913 #define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY__SHIFT                                                   0x10
26914 #define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY__SHIFT                                               0x11
26915 #define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY__SHIFT                                                  0x12
26916 #define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY__SHIFT                                                  0x13
26917 #define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY__SHIFT                                               0x14
26918 #define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY__SHIFT                                               0x15
26919 #define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY__SHIFT                                               0x16
26920 #define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY__SHIFT                                               0x17
26921 #define RLC_SERDES_NONCU_MASTER_BUSY__EA_0_MASTER_BUSY__SHIFT                                                 0x18
26922 #define RLC_SERDES_NONCU_MASTER_BUSY__TC2_MASTER_BUSY__SHIFT                                                  0x19
26923 #define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED__SHIFT                                                         0x1a
26924 #define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK                                                     0x0000FFFFL
26925 #define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK                                                     0x00010000L
26926 #define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY_MASK                                                 0x00020000L
26927 #define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK                                                    0x00040000L
26928 #define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK                                                    0x00080000L
26929 #define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY_MASK                                                 0x00100000L
26930 #define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY_MASK                                                 0x00200000L
26931 #define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY_MASK                                                 0x00400000L
26932 #define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY_MASK                                                 0x00800000L
26933 #define RLC_SERDES_NONCU_MASTER_BUSY__EA_0_MASTER_BUSY_MASK                                                   0x01000000L
26934 #define RLC_SERDES_NONCU_MASTER_BUSY__TC2_MASTER_BUSY_MASK                                                    0x02000000L
26935 #define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED_MASK                                                           0xFC000000L
26936 //RLC_GPM_GENERAL_0
26937 #define RLC_GPM_GENERAL_0__DATA__SHIFT                                                                        0x0
26938 #define RLC_GPM_GENERAL_0__DATA_MASK                                                                          0xFFFFFFFFL
26939 //RLC_GPM_GENERAL_1
26940 #define RLC_GPM_GENERAL_1__DATA__SHIFT                                                                        0x0
26941 #define RLC_GPM_GENERAL_1__DATA_MASK                                                                          0xFFFFFFFFL
26942 //RLC_GPM_GENERAL_2
26943 #define RLC_GPM_GENERAL_2__DATA__SHIFT                                                                        0x0
26944 #define RLC_GPM_GENERAL_2__DATA_MASK                                                                          0xFFFFFFFFL
26945 //RLC_GPM_GENERAL_3
26946 #define RLC_GPM_GENERAL_3__DATA__SHIFT                                                                        0x0
26947 #define RLC_GPM_GENERAL_3__DATA_MASK                                                                          0xFFFFFFFFL
26948 //RLC_GPM_GENERAL_4
26949 #define RLC_GPM_GENERAL_4__DATA__SHIFT                                                                        0x0
26950 #define RLC_GPM_GENERAL_4__DATA_MASK                                                                          0xFFFFFFFFL
26951 //RLC_GPM_GENERAL_5
26952 #define RLC_GPM_GENERAL_5__DATA__SHIFT                                                                        0x0
26953 #define RLC_GPM_GENERAL_5__DATA_MASK                                                                          0xFFFFFFFFL
26954 //RLC_GPM_GENERAL_6
26955 #define RLC_GPM_GENERAL_6__DATA__SHIFT                                                                        0x0
26956 #define RLC_GPM_GENERAL_6__DATA_MASK                                                                          0xFFFFFFFFL
26957 //RLC_GPM_GENERAL_7
26958 #define RLC_GPM_GENERAL_7__DATA__SHIFT                                                                        0x0
26959 #define RLC_GPM_GENERAL_7__DATA_MASK                                                                          0xFFFFFFFFL
26960 //RLC_GPM_SCRATCH_ADDR
26961 #define RLC_GPM_SCRATCH_ADDR__ADDR__SHIFT                                                                     0x0
26962 #define RLC_GPM_SCRATCH_ADDR__RESERVED__SHIFT                                                                 0x9
26963 #define RLC_GPM_SCRATCH_ADDR__ADDR_MASK                                                                       0x000001FFL
26964 #define RLC_GPM_SCRATCH_ADDR__RESERVED_MASK                                                                   0xFFFFFE00L
26965 //RLC_GPM_SCRATCH_DATA
26966 #define RLC_GPM_SCRATCH_DATA__DATA__SHIFT                                                                     0x0
26967 #define RLC_GPM_SCRATCH_DATA__DATA_MASK                                                                       0xFFFFFFFFL
26968 //RLC_STATIC_PG_STATUS
26969 #define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK__SHIFT                                                        0x0
26970 #define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK_MASK                                                          0xFFFFFFFFL
26971 //RLC_SPM_MC_CNTL
26972 #define RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT                                                                  0x0
26973 #define RLC_SPM_MC_CNTL__RLC_SPM_POLICY__SHIFT                                                                0x4
26974 #define RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR__SHIFT                                                             0x5
26975 #define RLC_SPM_MC_CNTL__RLC_SPM_FED__SHIFT                                                                   0x6
26976 #define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER__SHIFT                                                            0x7
26977 #define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE__SHIFT                                                                 0x8
26978 #define RLC_SPM_MC_CNTL__RESERVED__SHIFT                                                                      0xa
26979 #define RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK                                                                    0x0000000FL
26980 #define RLC_SPM_MC_CNTL__RLC_SPM_POLICY_MASK                                                                  0x00000010L
26981 #define RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR_MASK                                                               0x00000020L
26982 #define RLC_SPM_MC_CNTL__RLC_SPM_FED_MASK                                                                     0x00000040L
26983 #define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER_MASK                                                              0x00000080L
26984 #define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_MASK                                                                   0x00000300L
26985 #define RLC_SPM_MC_CNTL__RESERVED_MASK                                                                        0xFFFFFC00L
26986 //RLC_SPM_INT_CNTL
26987 #define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL__SHIFT                                                             0x0
26988 #define RLC_SPM_INT_CNTL__RESERVED__SHIFT                                                                     0x1
26989 #define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL_MASK                                                               0x00000001L
26990 #define RLC_SPM_INT_CNTL__RESERVED_MASK                                                                       0xFFFFFFFEL
26991 //RLC_SPM_INT_STATUS
26992 #define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS__SHIFT                                                         0x0
26993 #define RLC_SPM_INT_STATUS__RESERVED__SHIFT                                                                   0x1
26994 #define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS_MASK                                                           0x00000001L
26995 #define RLC_SPM_INT_STATUS__RESERVED_MASK                                                                     0xFFFFFFFEL
26996 //RLC_SMU_MESSAGE
26997 #define RLC_SMU_MESSAGE__CMD__SHIFT                                                                           0x0
26998 #define RLC_SMU_MESSAGE__CMD_MASK                                                                             0xFFFFFFFFL
26999 //RLC_GPM_LOG_SIZE
27000 #define RLC_GPM_LOG_SIZE__SIZE__SHIFT                                                                         0x0
27001 #define RLC_GPM_LOG_SIZE__SIZE_MASK                                                                           0xFFFFFFFFL
27002 //RLC_PG_DELAY_3
27003 #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT                                                        0x0
27004 #define RLC_PG_DELAY_3__RESERVED__SHIFT                                                                       0x8
27005 #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK                                                          0x000000FFL
27006 #define RLC_PG_DELAY_3__RESERVED_MASK                                                                         0xFFFFFF00L
27007 //RLC_GPR_REG1
27008 #define RLC_GPR_REG1__DATA__SHIFT                                                                             0x0
27009 #define RLC_GPR_REG1__DATA_MASK                                                                               0xFFFFFFFFL
27010 //RLC_GPR_REG2
27011 #define RLC_GPR_REG2__DATA__SHIFT                                                                             0x0
27012 #define RLC_GPR_REG2__DATA_MASK                                                                               0xFFFFFFFFL
27013 //RLC_GPM_LOG_CONT
27014 #define RLC_GPM_LOG_CONT__CONT__SHIFT                                                                         0x0
27015 #define RLC_GPM_LOG_CONT__CONT_MASK                                                                           0xFFFFFFFFL
27016 //RLC_GPM_INT_DISABLE_TH0
27017 #define RLC_GPM_INT_DISABLE_TH0__DISABLE__SHIFT                                                               0x0
27018 #define RLC_GPM_INT_DISABLE_TH0__DISABLE_MASK                                                                 0xFFFFFFFFL
27019 //RLC_GPM_INT_FORCE_TH0
27020 #define RLC_GPM_INT_FORCE_TH0__FORCE__SHIFT                                                                   0x0
27021 #define RLC_GPM_INT_FORCE_TH0__FORCE_MASK                                                                     0xFFFFFFFFL
27022 //RLC_GPM_INT_FORCE_TH1
27023 #define RLC_GPM_INT_FORCE_TH1__FORCE__SHIFT                                                                   0x0
27024 #define RLC_GPM_INT_FORCE_TH1__FORCE_MASK                                                                     0xFFFFFFFFL
27025 //RLC_SRM_CNTL
27026 #define RLC_SRM_CNTL__SRM_ENABLE__SHIFT                                                                       0x0
27027 #define RLC_SRM_CNTL__AUTO_INCR_ADDR__SHIFT                                                                   0x1
27028 #define RLC_SRM_CNTL__RESERVED__SHIFT                                                                         0x2
27029 #define RLC_SRM_CNTL__SRM_ENABLE_MASK                                                                         0x00000001L
27030 #define RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK                                                                     0x00000002L
27031 #define RLC_SRM_CNTL__RESERVED_MASK                                                                           0xFFFFFFFCL
27032 //RLC_SRM_ARAM_ADDR
27033 #define RLC_SRM_ARAM_ADDR__ADDR__SHIFT                                                                        0x0
27034 #define RLC_SRM_ARAM_ADDR__RESERVED__SHIFT                                                                    0xb
27035 #define RLC_SRM_ARAM_ADDR__ADDR_MASK                                                                          0x000007FFL
27036 #define RLC_SRM_ARAM_ADDR__RESERVED_MASK                                                                      0xFFFFF800L
27037 //RLC_SRM_ARAM_DATA
27038 #define RLC_SRM_ARAM_DATA__DATA__SHIFT                                                                        0x0
27039 #define RLC_SRM_ARAM_DATA__DATA_MASK                                                                          0xFFFFFFFFL
27040 //RLC_SRM_DRAM_ADDR
27041 #define RLC_SRM_DRAM_ADDR__ADDR__SHIFT                                                                        0x0
27042 #define RLC_SRM_DRAM_ADDR__RESERVED__SHIFT                                                                    0xb
27043 #define RLC_SRM_DRAM_ADDR__ADDR_MASK                                                                          0x000007FFL
27044 #define RLC_SRM_DRAM_ADDR__RESERVED_MASK                                                                      0xFFFFF800L
27045 //RLC_SRM_DRAM_DATA
27046 #define RLC_SRM_DRAM_DATA__DATA__SHIFT                                                                        0x0
27047 #define RLC_SRM_DRAM_DATA__DATA_MASK                                                                          0xFFFFFFFFL
27048 //RLC_SRM_GPM_COMMAND
27049 #define RLC_SRM_GPM_COMMAND__OP__SHIFT                                                                        0x0
27050 #define RLC_SRM_GPM_COMMAND__INDEX_CNTL__SHIFT                                                                0x1
27051 #define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM__SHIFT                                                            0x2
27052 #define RLC_SRM_GPM_COMMAND__SIZE__SHIFT                                                                      0x5
27053 #define RLC_SRM_GPM_COMMAND__RESERVED_16__SHIFT                                                               0x10
27054 #define RLC_SRM_GPM_COMMAND__START_OFFSET__SHIFT                                                              0x11
27055 #define RLC_SRM_GPM_COMMAND__RESERVED_30_29__SHIFT                                                            0x1d
27056 #define RLC_SRM_GPM_COMMAND__DEST_MEMORY__SHIFT                                                               0x1f
27057 #define RLC_SRM_GPM_COMMAND__OP_MASK                                                                          0x00000001L
27058 #define RLC_SRM_GPM_COMMAND__INDEX_CNTL_MASK                                                                  0x00000002L
27059 #define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM_MASK                                                              0x0000001CL
27060 #define RLC_SRM_GPM_COMMAND__SIZE_MASK                                                                        0x0000FFE0L
27061 #define RLC_SRM_GPM_COMMAND__RESERVED_16_MASK                                                                 0x00010000L
27062 #define RLC_SRM_GPM_COMMAND__START_OFFSET_MASK                                                                0x0FFE0000L
27063 #define RLC_SRM_GPM_COMMAND__RESERVED_30_29_MASK                                                              0x60000000L
27064 #define RLC_SRM_GPM_COMMAND__DEST_MEMORY_MASK                                                                 0x80000000L
27065 //RLC_SRM_GPM_COMMAND_STATUS
27066 #define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY__SHIFT                                                         0x0
27067 #define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL__SHIFT                                                          0x1
27068 #define RLC_SRM_GPM_COMMAND_STATUS__RESERVED__SHIFT                                                           0x2
27069 #define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY_MASK                                                           0x00000001L
27070 #define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL_MASK                                                            0x00000002L
27071 #define RLC_SRM_GPM_COMMAND_STATUS__RESERVED_MASK                                                             0xFFFFFFFCL
27072 //RLC_SRM_RLCV_COMMAND
27073 #define RLC_SRM_RLCV_COMMAND__OP__SHIFT                                                                       0x0
27074 #define RLC_SRM_RLCV_COMMAND__INDEX_CNTL__SHIFT                                                               0x1
27075 #define RLC_SRM_RLCV_COMMAND__INDEX_CNTL_NUM__SHIFT                                                           0x2
27076 #define RLC_SRM_RLCV_COMMAND__SIZE__SHIFT                                                                     0x5
27077 #define RLC_SRM_RLCV_COMMAND__RESERVED_16__SHIFT                                                              0x10
27078 #define RLC_SRM_RLCV_COMMAND__START_OFFSET__SHIFT                                                             0x11
27079 #define RLC_SRM_RLCV_COMMAND__RESERVED1__SHIFT                                                                0x1c
27080 #define RLC_SRM_RLCV_COMMAND__DEST_MEMORY__SHIFT                                                              0x1f
27081 #define RLC_SRM_RLCV_COMMAND__OP_MASK                                                                         0x00000001L
27082 #define RLC_SRM_RLCV_COMMAND__INDEX_CNTL_MASK                                                                 0x00000002L
27083 #define RLC_SRM_RLCV_COMMAND__INDEX_CNTL_NUM_MASK                                                             0x0000001CL
27084 #define RLC_SRM_RLCV_COMMAND__SIZE_MASK                                                                       0x0000FFE0L
27085 #define RLC_SRM_RLCV_COMMAND__RESERVED_16_MASK                                                                0x00010000L
27086 #define RLC_SRM_RLCV_COMMAND__START_OFFSET_MASK                                                               0x0FFE0000L
27087 #define RLC_SRM_RLCV_COMMAND__RESERVED1_MASK                                                                  0x70000000L
27088 #define RLC_SRM_RLCV_COMMAND__DEST_MEMORY_MASK                                                                0x80000000L
27089 //RLC_SRM_RLCV_COMMAND_STATUS
27090 #define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY__SHIFT                                                        0x0
27091 #define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL__SHIFT                                                         0x1
27092 #define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED__SHIFT                                                          0x2
27093 #define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY_MASK                                                          0x00000001L
27094 #define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL_MASK                                                           0x00000002L
27095 #define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED_MASK                                                            0xFFFFFFFCL
27096 //RLC_SRM_INDEX_CNTL_ADDR_0
27097 #define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS__SHIFT                                                             0x0
27098 #define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED__SHIFT                                                            0x10
27099 #define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS_MASK                                                               0x0000FFFFL
27100 #define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED_MASK                                                              0xFFFF0000L
27101 //RLC_SRM_INDEX_CNTL_ADDR_1
27102 #define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS__SHIFT                                                             0x0
27103 #define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED__SHIFT                                                            0x10
27104 #define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS_MASK                                                               0x0000FFFFL
27105 #define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED_MASK                                                              0xFFFF0000L
27106 //RLC_SRM_INDEX_CNTL_ADDR_2
27107 #define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS__SHIFT                                                             0x0
27108 #define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED__SHIFT                                                            0x10
27109 #define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS_MASK                                                               0x0000FFFFL
27110 #define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED_MASK                                                              0xFFFF0000L
27111 //RLC_SRM_INDEX_CNTL_ADDR_3
27112 #define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS__SHIFT                                                             0x0
27113 #define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED__SHIFT                                                            0x10
27114 #define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS_MASK                                                               0x0000FFFFL
27115 #define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED_MASK                                                              0xFFFF0000L
27116 //RLC_SRM_INDEX_CNTL_ADDR_4
27117 #define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS__SHIFT                                                             0x0
27118 #define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED__SHIFT                                                            0x10
27119 #define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS_MASK                                                               0x0000FFFFL
27120 #define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED_MASK                                                              0xFFFF0000L
27121 //RLC_SRM_INDEX_CNTL_ADDR_5
27122 #define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS__SHIFT                                                             0x0
27123 #define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED__SHIFT                                                            0x10
27124 #define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS_MASK                                                               0x0000FFFFL
27125 #define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED_MASK                                                              0xFFFF0000L
27126 //RLC_SRM_INDEX_CNTL_ADDR_6
27127 #define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS__SHIFT                                                             0x0
27128 #define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED__SHIFT                                                            0x10
27129 #define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS_MASK                                                               0x0000FFFFL
27130 #define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED_MASK                                                              0xFFFF0000L
27131 //RLC_SRM_INDEX_CNTL_ADDR_7
27132 #define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS__SHIFT                                                             0x0
27133 #define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED__SHIFT                                                            0x10
27134 #define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS_MASK                                                               0x0000FFFFL
27135 #define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED_MASK                                                              0xFFFF0000L
27136 //RLC_SRM_INDEX_CNTL_DATA_0
27137 #define RLC_SRM_INDEX_CNTL_DATA_0__DATA__SHIFT                                                                0x0
27138 #define RLC_SRM_INDEX_CNTL_DATA_0__DATA_MASK                                                                  0xFFFFFFFFL
27139 //RLC_SRM_INDEX_CNTL_DATA_1
27140 #define RLC_SRM_INDEX_CNTL_DATA_1__DATA__SHIFT                                                                0x0
27141 #define RLC_SRM_INDEX_CNTL_DATA_1__DATA_MASK                                                                  0xFFFFFFFFL
27142 //RLC_SRM_INDEX_CNTL_DATA_2
27143 #define RLC_SRM_INDEX_CNTL_DATA_2__DATA__SHIFT                                                                0x0
27144 #define RLC_SRM_INDEX_CNTL_DATA_2__DATA_MASK                                                                  0xFFFFFFFFL
27145 //RLC_SRM_INDEX_CNTL_DATA_3
27146 #define RLC_SRM_INDEX_CNTL_DATA_3__DATA__SHIFT                                                                0x0
27147 #define RLC_SRM_INDEX_CNTL_DATA_3__DATA_MASK                                                                  0xFFFFFFFFL
27148 //RLC_SRM_INDEX_CNTL_DATA_4
27149 #define RLC_SRM_INDEX_CNTL_DATA_4__DATA__SHIFT                                                                0x0
27150 #define RLC_SRM_INDEX_CNTL_DATA_4__DATA_MASK                                                                  0xFFFFFFFFL
27151 //RLC_SRM_INDEX_CNTL_DATA_5
27152 #define RLC_SRM_INDEX_CNTL_DATA_5__DATA__SHIFT                                                                0x0
27153 #define RLC_SRM_INDEX_CNTL_DATA_5__DATA_MASK                                                                  0xFFFFFFFFL
27154 //RLC_SRM_INDEX_CNTL_DATA_6
27155 #define RLC_SRM_INDEX_CNTL_DATA_6__DATA__SHIFT                                                                0x0
27156 #define RLC_SRM_INDEX_CNTL_DATA_6__DATA_MASK                                                                  0xFFFFFFFFL
27157 //RLC_SRM_INDEX_CNTL_DATA_7
27158 #define RLC_SRM_INDEX_CNTL_DATA_7__DATA__SHIFT                                                                0x0
27159 #define RLC_SRM_INDEX_CNTL_DATA_7__DATA_MASK                                                                  0xFFFFFFFFL
27160 //RLC_SRM_STAT
27161 #define RLC_SRM_STAT__SRM_BUSY__SHIFT                                                                         0x0
27162 #define RLC_SRM_STAT__SRM_BUSY_DELAY__SHIFT                                                                   0x1
27163 #define RLC_SRM_STAT__RESERVED__SHIFT                                                                         0x2
27164 #define RLC_SRM_STAT__SRM_BUSY_MASK                                                                           0x00000001L
27165 #define RLC_SRM_STAT__SRM_BUSY_DELAY_MASK                                                                     0x00000002L
27166 #define RLC_SRM_STAT__RESERVED_MASK                                                                           0xFFFFFFFCL
27167 //RLC_SRM_GPM_ABORT
27168 #define RLC_SRM_GPM_ABORT__ABORT__SHIFT                                                                       0x0
27169 #define RLC_SRM_GPM_ABORT__RESERVED__SHIFT                                                                    0x1
27170 #define RLC_SRM_GPM_ABORT__ABORT_MASK                                                                         0x00000001L
27171 #define RLC_SRM_GPM_ABORT__RESERVED_MASK                                                                      0xFFFFFFFEL
27172 //RLC_CSIB_ADDR_LO
27173 #define RLC_CSIB_ADDR_LO__ADDRESS__SHIFT                                                                      0x0
27174 #define RLC_CSIB_ADDR_LO__ADDRESS_MASK                                                                        0xFFFFFFFFL
27175 //RLC_CSIB_ADDR_HI
27176 #define RLC_CSIB_ADDR_HI__ADDRESS__SHIFT                                                                      0x0
27177 #define RLC_CSIB_ADDR_HI__ADDRESS_MASK                                                                        0x0000FFFFL
27178 //RLC_CSIB_LENGTH
27179 #define RLC_CSIB_LENGTH__LENGTH__SHIFT                                                                        0x0
27180 #define RLC_CSIB_LENGTH__LENGTH_MASK                                                                          0xFFFFFFFFL
27181 //RLC_SMU_COMMAND
27182 #define RLC_SMU_COMMAND__CMD__SHIFT                                                                           0x0
27183 #define RLC_SMU_COMMAND__CMD_MASK                                                                             0xFFFFFFFFL
27184 //RLC_CP_SCHEDULERS
27185 #define RLC_CP_SCHEDULERS__scheduler0__SHIFT                                                                  0x0
27186 #define RLC_CP_SCHEDULERS__scheduler1__SHIFT                                                                  0x8
27187 #define RLC_CP_SCHEDULERS__scheduler2__SHIFT                                                                  0x10
27188 #define RLC_CP_SCHEDULERS__scheduler3__SHIFT                                                                  0x18
27189 #define RLC_CP_SCHEDULERS__scheduler0_MASK                                                                    0x000000FFL
27190 #define RLC_CP_SCHEDULERS__scheduler1_MASK                                                                    0x0000FF00L
27191 #define RLC_CP_SCHEDULERS__scheduler2_MASK                                                                    0x00FF0000L
27192 #define RLC_CP_SCHEDULERS__scheduler3_MASK                                                                    0xFF000000L
27193 //RLC_SMU_ARGUMENT_1
27194 #define RLC_SMU_ARGUMENT_1__ARG__SHIFT                                                                        0x0
27195 #define RLC_SMU_ARGUMENT_1__ARG_MASK                                                                          0xFFFFFFFFL
27196 //RLC_SMU_ARGUMENT_2
27197 #define RLC_SMU_ARGUMENT_2__ARG__SHIFT                                                                        0x0
27198 #define RLC_SMU_ARGUMENT_2__ARG_MASK                                                                          0xFFFFFFFFL
27199 //RLC_GPM_GENERAL_8
27200 #define RLC_GPM_GENERAL_8__DATA__SHIFT                                                                        0x0
27201 #define RLC_GPM_GENERAL_8__DATA_MASK                                                                          0xFFFFFFFFL
27202 //RLC_GPM_GENERAL_9
27203 #define RLC_GPM_GENERAL_9__DATA__SHIFT                                                                        0x0
27204 #define RLC_GPM_GENERAL_9__DATA_MASK                                                                          0xFFFFFFFFL
27205 //RLC_GPM_GENERAL_10
27206 #define RLC_GPM_GENERAL_10__DATA__SHIFT                                                                       0x0
27207 #define RLC_GPM_GENERAL_10__DATA_MASK                                                                         0xFFFFFFFFL
27208 //RLC_GPM_GENERAL_11
27209 #define RLC_GPM_GENERAL_11__DATA__SHIFT                                                                       0x0
27210 #define RLC_GPM_GENERAL_11__DATA_MASK                                                                         0xFFFFFFFFL
27211 //RLC_GPM_GENERAL_12
27212 #define RLC_GPM_GENERAL_12__DATA__SHIFT                                                                       0x0
27213 #define RLC_GPM_GENERAL_12__DATA_MASK                                                                         0xFFFFFFFFL
27214 //RLC_GPM_UTCL1_CNTL_0
27215 #define RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT__SHIFT                                                     0x0
27216 #define RLC_GPM_UTCL1_CNTL_0__DROP_MODE__SHIFT                                                                0x18
27217 #define RLC_GPM_UTCL1_CNTL_0__RESERVED__SHIFT                                                                 0x19
27218 #define RLC_GPM_UTCL1_CNTL_0__INVALIDATE__SHIFT                                                               0x1a
27219 #define RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE__SHIFT                                                          0x1b
27220 #define RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP__SHIFT                                                              0x1c
27221 #define RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT_MASK                                                       0x000FFFFFL
27222 #define RLC_GPM_UTCL1_CNTL_0__DROP_MODE_MASK                                                                  0x01000000L
27223 #define RLC_GPM_UTCL1_CNTL_0__RESERVED_MASK                                                                   0x02000000L
27224 #define RLC_GPM_UTCL1_CNTL_0__INVALIDATE_MASK                                                                 0x04000000L
27225 #define RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE_MASK                                                            0x08000000L
27226 #define RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP_MASK                                                                0x10000000L
27227 //RLC_GPM_UTCL1_CNTL_1
27228 #define RLC_GPM_UTCL1_CNTL_1__XNACK_REDO_TIMER_CNT__SHIFT                                                     0x0
27229 #define RLC_GPM_UTCL1_CNTL_1__DROP_MODE__SHIFT                                                                0x18
27230 #define RLC_GPM_UTCL1_CNTL_1__RESERVED__SHIFT                                                                 0x19
27231 #define RLC_GPM_UTCL1_CNTL_1__INVALIDATE__SHIFT                                                               0x1a
27232 #define RLC_GPM_UTCL1_CNTL_1__FRAG_LIMIT_MODE__SHIFT                                                          0x1b
27233 #define RLC_GPM_UTCL1_CNTL_1__FORCE_SNOOP__SHIFT                                                              0x1c
27234 #define RLC_GPM_UTCL1_CNTL_1__XNACK_REDO_TIMER_CNT_MASK                                                       0x000FFFFFL
27235 #define RLC_GPM_UTCL1_CNTL_1__DROP_MODE_MASK                                                                  0x01000000L
27236 #define RLC_GPM_UTCL1_CNTL_1__RESERVED_MASK                                                                   0x02000000L
27237 #define RLC_GPM_UTCL1_CNTL_1__INVALIDATE_MASK                                                                 0x04000000L
27238 #define RLC_GPM_UTCL1_CNTL_1__FRAG_LIMIT_MODE_MASK                                                            0x08000000L
27239 #define RLC_GPM_UTCL1_CNTL_1__FORCE_SNOOP_MASK                                                                0x10000000L
27240 //RLC_GPM_UTCL1_CNTL_2
27241 #define RLC_GPM_UTCL1_CNTL_2__XNACK_REDO_TIMER_CNT__SHIFT                                                     0x0
27242 #define RLC_GPM_UTCL1_CNTL_2__DROP_MODE__SHIFT                                                                0x18
27243 #define RLC_GPM_UTCL1_CNTL_2__RESERVED__SHIFT                                                                 0x19
27244 #define RLC_GPM_UTCL1_CNTL_2__INVALIDATE__SHIFT                                                               0x1a
27245 #define RLC_GPM_UTCL1_CNTL_2__FRAG_LIMIT_MODE__SHIFT                                                          0x1b
27246 #define RLC_GPM_UTCL1_CNTL_2__FORCE_SNOOP__SHIFT                                                              0x1c
27247 #define RLC_GPM_UTCL1_CNTL_2__XNACK_REDO_TIMER_CNT_MASK                                                       0x000FFFFFL
27248 #define RLC_GPM_UTCL1_CNTL_2__DROP_MODE_MASK                                                                  0x01000000L
27249 #define RLC_GPM_UTCL1_CNTL_2__RESERVED_MASK                                                                   0x02000000L
27250 #define RLC_GPM_UTCL1_CNTL_2__INVALIDATE_MASK                                                                 0x04000000L
27251 #define RLC_GPM_UTCL1_CNTL_2__FRAG_LIMIT_MODE_MASK                                                            0x08000000L
27252 #define RLC_GPM_UTCL1_CNTL_2__FORCE_SNOOP_MASK                                                                0x10000000L
27253 //RLC_SPM_UTCL1_CNTL
27254 #define RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT                                                       0x0
27255 #define RLC_SPM_UTCL1_CNTL__DROP_MODE__SHIFT                                                                  0x18
27256 #define RLC_SPM_UTCL1_CNTL__RESERVED__SHIFT                                                                   0x19
27257 #define RLC_SPM_UTCL1_CNTL__INVALIDATE__SHIFT                                                                 0x1a
27258 #define RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT                                                            0x1b
27259 #define RLC_SPM_UTCL1_CNTL__FORCE_SNOOP__SHIFT                                                                0x1c
27260 #define RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK                                                         0x000FFFFFL
27261 #define RLC_SPM_UTCL1_CNTL__DROP_MODE_MASK                                                                    0x01000000L
27262 #define RLC_SPM_UTCL1_CNTL__RESERVED_MASK                                                                     0x02000000L
27263 #define RLC_SPM_UTCL1_CNTL__INVALIDATE_MASK                                                                   0x04000000L
27264 #define RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK                                                              0x08000000L
27265 #define RLC_SPM_UTCL1_CNTL__FORCE_SNOOP_MASK                                                                  0x10000000L
27266 //RLC_UTCL1_STATUS_2
27267 #define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY__SHIFT                                                         0x0
27268 #define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY__SHIFT                                                         0x1
27269 #define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY__SHIFT                                                         0x2
27270 #define RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY__SHIFT                                                             0x3
27271 #define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_BUSY__SHIFT                                                       0x4
27272 #define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans__SHIFT                                                 0x5
27273 #define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans__SHIFT                                                 0x6
27274 #define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans__SHIFT                                                 0x7
27275 #define RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans__SHIFT                                                     0x8
27276 #define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_StallOnTrans__SHIFT                                               0x9
27277 #define RLC_UTCL1_STATUS_2__RESERVED__SHIFT                                                                   0xa
27278 #define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY_MASK                                                           0x00000001L
27279 #define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY_MASK                                                           0x00000002L
27280 #define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY_MASK                                                           0x00000004L
27281 #define RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY_MASK                                                               0x00000008L
27282 #define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_BUSY_MASK                                                         0x00000010L
27283 #define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans_MASK                                                   0x00000020L
27284 #define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans_MASK                                                   0x00000040L
27285 #define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans_MASK                                                   0x00000080L
27286 #define RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans_MASK                                                       0x00000100L
27287 #define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_StallOnTrans_MASK                                                 0x00000200L
27288 #define RLC_UTCL1_STATUS_2__RESERVED_MASK                                                                     0xFFFFFC00L
27289 //RLC_LB_THR_CONFIG_2
27290 #define RLC_LB_THR_CONFIG_2__DATA__SHIFT                                                                      0x0
27291 #define RLC_LB_THR_CONFIG_2__DATA_MASK                                                                        0xFFFFFFFFL
27292 //RLC_LB_THR_CONFIG_3
27293 #define RLC_LB_THR_CONFIG_3__DATA__SHIFT                                                                      0x0
27294 #define RLC_LB_THR_CONFIG_3__DATA_MASK                                                                        0xFFFFFFFFL
27295 //RLC_LB_THR_CONFIG_4
27296 #define RLC_LB_THR_CONFIG_4__DATA__SHIFT                                                                      0x0
27297 #define RLC_LB_THR_CONFIG_4__DATA_MASK                                                                        0xFFFFFFFFL
27298 //RLC_SPM_UTCL1_ERROR_1
27299 #define RLC_SPM_UTCL1_ERROR_1__Translated_ReqError__SHIFT                                                     0x0
27300 #define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid__SHIFT                                                 0x2
27301 #define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT                                             0x6
27302 #define RLC_SPM_UTCL1_ERROR_1__Translated_ReqError_MASK                                                       0x00000003L
27303 #define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid_MASK                                                   0x0000003CL
27304 #define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK                                               0x000003C0L
27305 //RLC_SPM_UTCL1_ERROR_2
27306 #define RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT                                             0x0
27307 #define RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK                                               0xFFFFFFFFL
27308 //RLC_GPM_UTCL1_TH0_ERROR_1
27309 #define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError__SHIFT                                                 0x0
27310 #define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid__SHIFT                                             0x2
27311 #define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT                                         0x6
27312 #define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError_MASK                                                   0x00000003L
27313 #define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid_MASK                                               0x0000003CL
27314 #define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB_MASK                                           0x000003C0L
27315 //RLC_LB_THR_CONFIG_1
27316 #define RLC_LB_THR_CONFIG_1__DATA__SHIFT                                                                      0x0
27317 #define RLC_LB_THR_CONFIG_1__DATA_MASK                                                                        0xFFFFFFFFL
27318 //RLC_GPM_UTCL1_TH0_ERROR_2
27319 #define RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT                                         0x0
27320 #define RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB_MASK                                           0xFFFFFFFFL
27321 //RLC_GPM_UTCL1_TH1_ERROR_1
27322 #define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqError__SHIFT                                                 0x0
27323 #define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorVmid__SHIFT                                             0x2
27324 #define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT                                         0x6
27325 #define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqError_MASK                                                   0x00000003L
27326 #define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorVmid_MASK                                               0x0000003CL
27327 #define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK                                           0x000003C0L
27328 //RLC_GPM_UTCL1_TH1_ERROR_2
27329 #define RLC_GPM_UTCL1_TH1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT                                         0x0
27330 #define RLC_GPM_UTCL1_TH1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK                                           0xFFFFFFFFL
27331 //RLC_GPM_UTCL1_TH2_ERROR_1
27332 #define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqError__SHIFT                                                 0x0
27333 #define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorVmid__SHIFT                                             0x2
27334 #define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT                                         0x6
27335 #define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqError_MASK                                                   0x00000003L
27336 #define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorVmid_MASK                                               0x0000003CL
27337 #define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorAddr_MSB_MASK                                           0x000003C0L
27338 //RLC_GPM_UTCL1_TH2_ERROR_2
27339 #define RLC_GPM_UTCL1_TH2_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT                                         0x0
27340 #define RLC_GPM_UTCL1_TH2_ERROR_2__Translated_ReqErrorAddr_LSB_MASK                                           0xFFFFFFFFL
27341 //RLC_SEMAPHORE_0
27342 #define RLC_SEMAPHORE_0__CLIENT_ID__SHIFT                                                                     0x0
27343 #define RLC_SEMAPHORE_0__RESERVED__SHIFT                                                                      0x5
27344 #define RLC_SEMAPHORE_0__CLIENT_ID_MASK                                                                       0x0000001FL
27345 #define RLC_SEMAPHORE_0__RESERVED_MASK                                                                        0xFFFFFFE0L
27346 //RLC_SEMAPHORE_1
27347 #define RLC_SEMAPHORE_1__CLIENT_ID__SHIFT                                                                     0x0
27348 #define RLC_SEMAPHORE_1__RESERVED__SHIFT                                                                      0x5
27349 #define RLC_SEMAPHORE_1__CLIENT_ID_MASK                                                                       0x0000001FL
27350 #define RLC_SEMAPHORE_1__RESERVED_MASK                                                                        0xFFFFFFE0L
27351 //RLC_CP_EOF_INT
27352 #define RLC_CP_EOF_INT__INTERRUPT__SHIFT                                                                      0x0
27353 #define RLC_CP_EOF_INT__RESERVED__SHIFT                                                                       0x1
27354 #define RLC_CP_EOF_INT__INTERRUPT_MASK                                                                        0x00000001L
27355 #define RLC_CP_EOF_INT__RESERVED_MASK                                                                         0xFFFFFFFEL
27356 //RLC_CP_EOF_INT_CNT
27357 #define RLC_CP_EOF_INT_CNT__CNT__SHIFT                                                                        0x0
27358 #define RLC_CP_EOF_INT_CNT__CNT_MASK                                                                          0xFFFFFFFFL
27359 //RLC_SPARE_INT
27360 #define RLC_SPARE_INT__INTERRUPT__SHIFT                                                                       0x0
27361 #define RLC_SPARE_INT__RESERVED__SHIFT                                                                        0x1
27362 #define RLC_SPARE_INT__INTERRUPT_MASK                                                                         0x00000001L
27363 #define RLC_SPARE_INT__RESERVED_MASK                                                                          0xFFFFFFFEL
27364 //RLC_PREWALKER_UTCL1_CNTL
27365 #define RLC_PREWALKER_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT                                                 0x0
27366 #define RLC_PREWALKER_UTCL1_CNTL__DROP_MODE__SHIFT                                                            0x18
27367 #define RLC_PREWALKER_UTCL1_CNTL__RESERVED__SHIFT                                                             0x19
27368 #define RLC_PREWALKER_UTCL1_CNTL__INVALIDATE__SHIFT                                                           0x1a
27369 #define RLC_PREWALKER_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT                                                      0x1b
27370 #define RLC_PREWALKER_UTCL1_CNTL__FORCE_SNOOP__SHIFT                                                          0x1c
27371 #define RLC_PREWALKER_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK                                                   0x000FFFFFL
27372 #define RLC_PREWALKER_UTCL1_CNTL__DROP_MODE_MASK                                                              0x01000000L
27373 #define RLC_PREWALKER_UTCL1_CNTL__RESERVED_MASK                                                               0x02000000L
27374 #define RLC_PREWALKER_UTCL1_CNTL__INVALIDATE_MASK                                                             0x04000000L
27375 #define RLC_PREWALKER_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK                                                        0x08000000L
27376 #define RLC_PREWALKER_UTCL1_CNTL__FORCE_SNOOP_MASK                                                            0x10000000L
27377 //RLC_PREWALKER_UTCL1_TRIG
27378 #define RLC_PREWALKER_UTCL1_TRIG__VALID__SHIFT                                                                0x0
27379 #define RLC_PREWALKER_UTCL1_TRIG__VMID__SHIFT                                                                 0x1
27380 #define RLC_PREWALKER_UTCL1_TRIG__PRIME_MODE__SHIFT                                                           0x5
27381 #define RLC_PREWALKER_UTCL1_TRIG__READ_PERM__SHIFT                                                            0x6
27382 #define RLC_PREWALKER_UTCL1_TRIG__WRITE_PERM__SHIFT                                                           0x7
27383 #define RLC_PREWALKER_UTCL1_TRIG__EXEC_PERM__SHIFT                                                            0x8
27384 #define RLC_PREWALKER_UTCL1_TRIG__RESERVED__SHIFT                                                             0x9
27385 #define RLC_PREWALKER_UTCL1_TRIG__READY__SHIFT                                                                0x1f
27386 #define RLC_PREWALKER_UTCL1_TRIG__VALID_MASK                                                                  0x00000001L
27387 #define RLC_PREWALKER_UTCL1_TRIG__VMID_MASK                                                                   0x0000001EL
27388 #define RLC_PREWALKER_UTCL1_TRIG__PRIME_MODE_MASK                                                             0x00000020L
27389 #define RLC_PREWALKER_UTCL1_TRIG__READ_PERM_MASK                                                              0x00000040L
27390 #define RLC_PREWALKER_UTCL1_TRIG__WRITE_PERM_MASK                                                             0x00000080L
27391 #define RLC_PREWALKER_UTCL1_TRIG__EXEC_PERM_MASK                                                              0x00000100L
27392 #define RLC_PREWALKER_UTCL1_TRIG__RESERVED_MASK                                                               0x7FFFFE00L
27393 #define RLC_PREWALKER_UTCL1_TRIG__READY_MASK                                                                  0x80000000L
27394 //RLC_PREWALKER_UTCL1_ADDR_LSB
27395 #define RLC_PREWALKER_UTCL1_ADDR_LSB__ADDR_LSB__SHIFT                                                         0x0
27396 #define RLC_PREWALKER_UTCL1_ADDR_LSB__ADDR_LSB_MASK                                                           0xFFFFFFFFL
27397 //RLC_PREWALKER_UTCL1_ADDR_MSB
27398 #define RLC_PREWALKER_UTCL1_ADDR_MSB__ADDR_MSB__SHIFT                                                         0x0
27399 #define RLC_PREWALKER_UTCL1_ADDR_MSB__ADDR_MSB_MASK                                                           0x0000FFFFL
27400 //RLC_PREWALKER_UTCL1_SIZE_LSB
27401 #define RLC_PREWALKER_UTCL1_SIZE_LSB__SIZE_LSB__SHIFT                                                         0x0
27402 #define RLC_PREWALKER_UTCL1_SIZE_LSB__SIZE_LSB_MASK                                                           0xFFFFFFFFL
27403 //RLC_PREWALKER_UTCL1_SIZE_MSB
27404 #define RLC_PREWALKER_UTCL1_SIZE_MSB__SIZE_MSB__SHIFT                                                         0x0
27405 #define RLC_PREWALKER_UTCL1_SIZE_MSB__SIZE_MSB_MASK                                                           0x00000003L
27406 //RLC_DSM_TRIG
27407 #define RLC_DSM_TRIG__START__SHIFT                                                                            0x0
27408 #define RLC_DSM_TRIG__START_MASK                                                                              0x00000001L
27409 //RLC_UTCL1_STATUS
27410 #define RLC_UTCL1_STATUS__FAULT_DETECTED__SHIFT                                                               0x0
27411 #define RLC_UTCL1_STATUS__RETRY_DETECTED__SHIFT                                                               0x1
27412 #define RLC_UTCL1_STATUS__PRT_DETECTED__SHIFT                                                                 0x2
27413 #define RLC_UTCL1_STATUS__RESERVED__SHIFT                                                                     0x3
27414 #define RLC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT                                                                0x8
27415 #define RLC_UTCL1_STATUS__RESERVED_1__SHIFT                                                                   0xe
27416 #define RLC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT                                                                0x10
27417 #define RLC_UTCL1_STATUS__RESERVED_2__SHIFT                                                                   0x16
27418 #define RLC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT                                                                  0x18
27419 #define RLC_UTCL1_STATUS__RESERVED_3__SHIFT                                                                   0x1e
27420 #define RLC_UTCL1_STATUS__FAULT_DETECTED_MASK                                                                 0x00000001L
27421 #define RLC_UTCL1_STATUS__RETRY_DETECTED_MASK                                                                 0x00000002L
27422 #define RLC_UTCL1_STATUS__PRT_DETECTED_MASK                                                                   0x00000004L
27423 #define RLC_UTCL1_STATUS__RESERVED_MASK                                                                       0x000000F8L
27424 #define RLC_UTCL1_STATUS__FAULT_UTCL1ID_MASK                                                                  0x00003F00L
27425 #define RLC_UTCL1_STATUS__RESERVED_1_MASK                                                                     0x0000C000L
27426 #define RLC_UTCL1_STATUS__RETRY_UTCL1ID_MASK                                                                  0x003F0000L
27427 #define RLC_UTCL1_STATUS__RESERVED_2_MASK                                                                     0x00C00000L
27428 #define RLC_UTCL1_STATUS__PRT_UTCL1ID_MASK                                                                    0x3F000000L
27429 #define RLC_UTCL1_STATUS__RESERVED_3_MASK                                                                     0xC0000000L
27430 //RLC_R2I_CNTL_0
27431 #define RLC_R2I_CNTL_0__Data__SHIFT                                                                           0x0
27432 #define RLC_R2I_CNTL_0__Data_MASK                                                                             0xFFFFFFFFL
27433 //RLC_R2I_CNTL_1
27434 #define RLC_R2I_CNTL_1__Data__SHIFT                                                                           0x0
27435 #define RLC_R2I_CNTL_1__Data_MASK                                                                             0xFFFFFFFFL
27436 //RLC_R2I_CNTL_2
27437 #define RLC_R2I_CNTL_2__Data__SHIFT                                                                           0x0
27438 #define RLC_R2I_CNTL_2__Data_MASK                                                                             0xFFFFFFFFL
27439 //RLC_R2I_CNTL_3
27440 #define RLC_R2I_CNTL_3__Data__SHIFT                                                                           0x0
27441 #define RLC_R2I_CNTL_3__Data_MASK                                                                             0xFFFFFFFFL
27442 //RLC_UTCL2_CNTL
27443 #define RLC_UTCL2_CNTL__MTYPE_NO_PTE_MODE__SHIFT                                                              0x0
27444 #define RLC_UTCL2_CNTL__IGNORE_PTE_PERMISSION__SHIFT                                                          0x1
27445 #define RLC_UTCL2_CNTL__RESERVED__SHIFT                                                                       0x2
27446 #define RLC_UTCL2_CNTL__MTYPE_NO_PTE_MODE_MASK                                                                0x00000001L
27447 #define RLC_UTCL2_CNTL__IGNORE_PTE_PERMISSION_MASK                                                            0x00000002L
27448 #define RLC_UTCL2_CNTL__RESERVED_MASK                                                                         0xFFFFFFFCL
27449 //RLC_LBPW_CU_STAT
27450 #define RLC_LBPW_CU_STAT__MAX_CU__SHIFT                                                                       0x0
27451 #define RLC_LBPW_CU_STAT__ON_CU__SHIFT                                                                        0x10
27452 #define RLC_LBPW_CU_STAT__MAX_CU_MASK                                                                         0x0000FFFFL
27453 #define RLC_LBPW_CU_STAT__ON_CU_MASK                                                                          0xFFFF0000L
27454 //RLC_DS_CNTL
27455 #define RLC_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK__SHIFT                                                          0x0
27456 #define RLC_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK__SHIFT                                                           0x1
27457 #define RLC_DS_CNTL__GFX_CLK_TCC_RLC_GRBM_CC_RESIDENT_MASK__SHIFT                                             0x2
27458 #define RLC_DS_CNTL__GFX_CLK_EA_RLC_GRBM_STAT_BUSY_MASK__SHIFT                                                0x3
27459 #define RLC_DS_CNTL__RESRVED__SHIFT                                                                           0x4
27460 #define RLC_DS_CNTL__SOC_CLK_TCC_RLC_GRBM_CC_RESIDENT_MASK__SHIFT                                             0xe
27461 #define RLC_DS_CNTL__SOC_CLK_EA_RLC_GRBM_STAT_BUSY_MASK__SHIFT                                                0xf
27462 #define RLC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK__SHIFT                                                          0x10
27463 #define RLC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK__SHIFT                                                           0x11
27464 #define RLC_DS_CNTL__RESRVED_1__SHIFT                                                                         0x12
27465 #define RLC_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK_MASK                                                            0x00000001L
27466 #define RLC_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK_MASK                                                             0x00000002L
27467 #define RLC_DS_CNTL__GFX_CLK_TCC_RLC_GRBM_CC_RESIDENT_MASK_MASK                                               0x00000004L
27468 #define RLC_DS_CNTL__GFX_CLK_EA_RLC_GRBM_STAT_BUSY_MASK_MASK                                                  0x00000008L
27469 #define RLC_DS_CNTL__RESRVED_MASK                                                                             0x00003FF0L
27470 #define RLC_DS_CNTL__SOC_CLK_TCC_RLC_GRBM_CC_RESIDENT_MASK_MASK                                               0x00004000L
27471 #define RLC_DS_CNTL__SOC_CLK_EA_RLC_GRBM_STAT_BUSY_MASK_MASK                                                  0x00008000L
27472 #define RLC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK_MASK                                                            0x00010000L
27473 #define RLC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK_MASK                                                             0x00020000L
27474 #define RLC_DS_CNTL__RESRVED_1_MASK                                                                           0xFFFC0000L
27475 //RLC_GPM_INT_STAT_TH0
27476 #define RLC_GPM_INT_STAT_TH0__STATUS__SHIFT                                                                   0x0
27477 #define RLC_GPM_INT_STAT_TH0__STATUS_MASK                                                                     0xFFFFFFFFL
27478 //RLC_GPM_GENERAL_13
27479 #define RLC_GPM_GENERAL_13__DATA__SHIFT                                                                       0x0
27480 #define RLC_GPM_GENERAL_13__DATA_MASK                                                                         0xFFFFFFFFL
27481 //RLC_GPM_GENERAL_14
27482 #define RLC_GPM_GENERAL_14__DATA__SHIFT                                                                       0x0
27483 #define RLC_GPM_GENERAL_14__DATA_MASK                                                                         0xFFFFFFFFL
27484 //RLC_GPM_GENERAL_15
27485 #define RLC_GPM_GENERAL_15__DATA__SHIFT                                                                       0x0
27486 #define RLC_GPM_GENERAL_15__DATA_MASK                                                                         0xFFFFFFFFL
27487 //RLC_SPARE_INT_1
27488 #define RLC_SPARE_INT_1__INTERRUPT__SHIFT                                                                     0x0
27489 #define RLC_SPARE_INT_1__RESERVED__SHIFT                                                                      0x1
27490 #define RLC_SPARE_INT_1__INTERRUPT_MASK                                                                       0x00000001L
27491 #define RLC_SPARE_INT_1__RESERVED_MASK                                                                        0xFFFFFFFEL
27492 //RLC_RLCV_SPARE_INT_1
27493 #define RLC_RLCV_SPARE_INT_1__INTERRUPT__SHIFT                                                                0x0
27494 #define RLC_RLCV_SPARE_INT_1__RESERVED__SHIFT                                                                 0x1
27495 #define RLC_RLCV_SPARE_INT_1__INTERRUPT_MASK                                                                  0x00000001L
27496 #define RLC_RLCV_SPARE_INT_1__RESERVED_MASK                                                                   0xFFFFFFFEL
27497 //RLC_SEMAPHORE_2
27498 #define RLC_SEMAPHORE_2__CLIENT_ID__SHIFT                                                                     0x0
27499 #define RLC_SEMAPHORE_2__RESERVED__SHIFT                                                                      0x5
27500 #define RLC_SEMAPHORE_2__CLIENT_ID_MASK                                                                       0x0000001FL
27501 #define RLC_SEMAPHORE_2__RESERVED_MASK                                                                        0xFFFFFFE0L
27502 //RLC_SEMAPHORE_3
27503 #define RLC_SEMAPHORE_3__CLIENT_ID__SHIFT                                                                     0x0
27504 #define RLC_SEMAPHORE_3__RESERVED__SHIFT                                                                      0x5
27505 #define RLC_SEMAPHORE_3__CLIENT_ID_MASK                                                                       0x0000001FL
27506 #define RLC_SEMAPHORE_3__RESERVED_MASK                                                                        0xFFFFFFE0L
27507 //RLC_SMU_ARGUMENT_3
27508 #define RLC_SMU_ARGUMENT_3__ARG__SHIFT                                                                        0x0
27509 #define RLC_SMU_ARGUMENT_3__ARG_MASK                                                                          0xFFFFFFFFL
27510 //RLC_SMU_ARGUMENT_4
27511 #define RLC_SMU_ARGUMENT_4__ARG__SHIFT                                                                        0x0
27512 #define RLC_SMU_ARGUMENT_4__ARG_MASK                                                                          0xFFFFFFFFL
27513 //RLC_GPU_CLOCK_COUNT_LSB_1
27514 #define RLC_GPU_CLOCK_COUNT_LSB_1__GPU_CLOCKS_LSB__SHIFT                                                      0x0
27515 #define RLC_GPU_CLOCK_COUNT_LSB_1__GPU_CLOCKS_LSB_MASK                                                        0xFFFFFFFFL
27516 //RLC_GPU_CLOCK_COUNT_MSB_1
27517 #define RLC_GPU_CLOCK_COUNT_MSB_1__GPU_CLOCKS_MSB__SHIFT                                                      0x0
27518 #define RLC_GPU_CLOCK_COUNT_MSB_1__GPU_CLOCKS_MSB_MASK                                                        0xFFFFFFFFL
27519 //RLC_CAPTURE_GPU_CLOCK_COUNT_1
27520 #define RLC_CAPTURE_GPU_CLOCK_COUNT_1__CAPTURE__SHIFT                                                         0x0
27521 #define RLC_CAPTURE_GPU_CLOCK_COUNT_1__RESERVED__SHIFT                                                        0x1
27522 #define RLC_CAPTURE_GPU_CLOCK_COUNT_1__CAPTURE_MASK                                                           0x00000001L
27523 #define RLC_CAPTURE_GPU_CLOCK_COUNT_1__RESERVED_MASK                                                          0xFFFFFFFEL
27524 //RLC_GPU_CLOCK_COUNT_LSB_2
27525 #define RLC_GPU_CLOCK_COUNT_LSB_2__GPU_CLOCKS_LSB__SHIFT                                                      0x0
27526 #define RLC_GPU_CLOCK_COUNT_LSB_2__GPU_CLOCKS_LSB_MASK                                                        0xFFFFFFFFL
27527 //RLC_GPU_CLOCK_COUNT_MSB_2
27528 #define RLC_GPU_CLOCK_COUNT_MSB_2__GPU_CLOCKS_MSB__SHIFT                                                      0x0
27529 #define RLC_GPU_CLOCK_COUNT_MSB_2__GPU_CLOCKS_MSB_MASK                                                        0xFFFFFFFFL
27530 //RLC_CAPTURE_GPU_CLOCK_COUNT_2
27531 #define RLC_CAPTURE_GPU_CLOCK_COUNT_2__CAPTURE__SHIFT                                                         0x0
27532 #define RLC_CAPTURE_GPU_CLOCK_COUNT_2__RESERVED__SHIFT                                                        0x1
27533 #define RLC_CAPTURE_GPU_CLOCK_COUNT_2__CAPTURE_MASK                                                           0x00000001L
27534 #define RLC_CAPTURE_GPU_CLOCK_COUNT_2__RESERVED_MASK                                                          0xFFFFFFFEL
27535 //RLC_CPG_STAT_INVAL
27536 #define RLC_CPG_STAT_INVAL__CPG_stat_inval__SHIFT                                                             0x0
27537 #define RLC_CPG_STAT_INVAL__CPG_stat_inval_MASK                                                               0x00000001L
27538 //RLC_UE_ERR_STATUS_LOW
27539 #define RLC_UE_ERR_STATUS_LOW__ERR_STATUS_VALID_FLAG__SHIFT                                                   0x0
27540 #define RLC_UE_ERR_STATUS_LOW__ADDRESS_VALID_FLAG__SHIFT                                                      0x1
27541 #define RLC_UE_ERR_STATUS_LOW__ADDRESS__SHIFT                                                                 0x2
27542 #define RLC_UE_ERR_STATUS_LOW__MEMORY_ID__SHIFT                                                               0x18
27543 #define RLC_UE_ERR_STATUS_LOW__ERR_STATUS_VALID_FLAG_MASK                                                     0x00000001L
27544 #define RLC_UE_ERR_STATUS_LOW__ADDRESS_VALID_FLAG_MASK                                                        0x00000002L
27545 #define RLC_UE_ERR_STATUS_LOW__ADDRESS_MASK                                                                   0x00FFFFFCL
27546 #define RLC_UE_ERR_STATUS_LOW__MEMORY_ID_MASK                                                                 0xFF000000L
27547 //RLC_UE_ERR_STATUS_HIGH
27548 #define RLC_UE_ERR_STATUS_HIGH__ECC__SHIFT                                                                    0x0
27549 #define RLC_UE_ERR_STATUS_HIGH__PARITY__SHIFT                                                                 0x1
27550 #define RLC_UE_ERR_STATUS_HIGH__ERR_INFO_VALID_FLAG__SHIFT                                                    0x2
27551 #define RLC_UE_ERR_STATUS_HIGH__ERR_INFO__SHIFT                                                               0x3
27552 #define RLC_UE_ERR_STATUS_HIGH__UE_CNT__SHIFT                                                                 0x17
27553 #define RLC_UE_ERR_STATUS_HIGH__FED_CNT__SHIFT                                                                0x1a
27554 #define RLC_UE_ERR_STATUS_HIGH__RESERVED__SHIFT                                                               0x1d
27555 #define RLC_UE_ERR_STATUS_HIGH__ECC_MASK                                                                      0x00000001L
27556 #define RLC_UE_ERR_STATUS_HIGH__PARITY_MASK                                                                   0x00000002L
27557 #define RLC_UE_ERR_STATUS_HIGH__ERR_INFO_VALID_FLAG_MASK                                                      0x00000004L
27558 #define RLC_UE_ERR_STATUS_HIGH__ERR_INFO_MASK                                                                 0x007FFFF8L
27559 #define RLC_UE_ERR_STATUS_HIGH__UE_CNT_MASK                                                                   0x03800000L
27560 #define RLC_UE_ERR_STATUS_HIGH__FED_CNT_MASK                                                                  0x1C000000L
27561 #define RLC_UE_ERR_STATUS_HIGH__RESERVED_MASK                                                                 0xE0000000L
27562 //RLC_DSM_CNTL
27563 #define RLC_DSM_CNTL__RLCG_INSTR_RAM_IRRITATOR_DATA_SEL__SHIFT                                                0x0
27564 #define RLC_DSM_CNTL__RLCG_INSTR_RAM_IRRITATOR_SINGLE_WRITE__SHIFT                                            0x2
27565 #define RLC_DSM_CNTL__RLCG_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT                                              0x3
27566 #define RLC_DSM_CNTL__RLCG_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT                                          0x5
27567 #define RLC_DSM_CNTL__RLCV_INSTR_RAM_IRRITATOR_DATA_SEL__SHIFT                                                0x6
27568 #define RLC_DSM_CNTL__RLCV_INSTR_RAM_IRRITATOR_SINGLE_WRITE__SHIFT                                            0x8
27569 #define RLC_DSM_CNTL__RLCV_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT                                              0x9
27570 #define RLC_DSM_CNTL__RLCV_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT                                          0xb
27571 #define RLC_DSM_CNTL__RLC_TCTAG_RAM_IRRITATOR_DATA_SEL__SHIFT                                                 0xc
27572 #define RLC_DSM_CNTL__RLC_TCTAG_RAM_IRRITATOR_SINGLE_WRITE__SHIFT                                             0xe
27573 #define RLC_DSM_CNTL__RLC_SPM_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT                                           0xf
27574 #define RLC_DSM_CNTL__RLC_SPM_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT                                       0x11
27575 #define RLC_DSM_CNTL__RLC_SRM_DATA_RAM_IRRITATOR_DATA_SEL__SHIFT                                              0x12
27576 #define RLC_DSM_CNTL__RLC_SRM_DATA_RAM_IRRITATOR_SINGLE_WRITE__SHIFT                                          0x14
27577 #define RLC_DSM_CNTL__RLC_SRM_ADDR_RAM_IRRITATOR_DATA_SEL__SHIFT                                              0x15
27578 #define RLC_DSM_CNTL__RLC_SRM_ADDR_RAM_IRRITATOR_SINGLE_WRITE__SHIFT                                          0x17
27579 #define RLC_DSM_CNTL__RLCG_INSTR_RAM_IRRITATOR_DATA_SEL_MASK                                                  0x00000003L
27580 #define RLC_DSM_CNTL__RLCG_INSTR_RAM_IRRITATOR_SINGLE_WRITE_MASK                                              0x00000004L
27581 #define RLC_DSM_CNTL__RLCG_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK                                                0x00000018L
27582 #define RLC_DSM_CNTL__RLCG_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK                                            0x00000020L
27583 #define RLC_DSM_CNTL__RLCV_INSTR_RAM_IRRITATOR_DATA_SEL_MASK                                                  0x000000C0L
27584 #define RLC_DSM_CNTL__RLCV_INSTR_RAM_IRRITATOR_SINGLE_WRITE_MASK                                              0x00000100L
27585 #define RLC_DSM_CNTL__RLCV_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK                                                0x00000600L
27586 #define RLC_DSM_CNTL__RLCV_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK                                            0x00000800L
27587 #define RLC_DSM_CNTL__RLC_TCTAG_RAM_IRRITATOR_DATA_SEL_MASK                                                   0x00003000L
27588 #define RLC_DSM_CNTL__RLC_TCTAG_RAM_IRRITATOR_SINGLE_WRITE_MASK                                               0x00004000L
27589 #define RLC_DSM_CNTL__RLC_SPM_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK                                             0x00018000L
27590 #define RLC_DSM_CNTL__RLC_SPM_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK                                         0x00020000L
27591 #define RLC_DSM_CNTL__RLC_SRM_DATA_RAM_IRRITATOR_DATA_SEL_MASK                                                0x000C0000L
27592 #define RLC_DSM_CNTL__RLC_SRM_DATA_RAM_IRRITATOR_SINGLE_WRITE_MASK                                            0x00100000L
27593 #define RLC_DSM_CNTL__RLC_SRM_ADDR_RAM_IRRITATOR_DATA_SEL_MASK                                                0x00600000L
27594 #define RLC_DSM_CNTL__RLC_SRM_ADDR_RAM_IRRITATOR_SINGLE_WRITE_MASK                                            0x00800000L
27595 //RLC_DSM_CNTLA
27596 #define RLC_DSM_CNTLA__RLC_SPM_SE0_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT                                      0x0
27597 #define RLC_DSM_CNTLA__RLC_SPM_SE0_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT                                  0x2
27598 #define RLC_DSM_CNTLA__RLC_SPM_SE1_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT                                      0x3
27599 #define RLC_DSM_CNTLA__RLC_SPM_SE1_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT                                  0x5
27600 #define RLC_DSM_CNTLA__RLC_SPM_SE2_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT                                      0x6
27601 #define RLC_DSM_CNTLA__RLC_SPM_SE2_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT                                  0x8
27602 #define RLC_DSM_CNTLA__RLC_SPM_SE3_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT                                      0x9
27603 #define RLC_DSM_CNTLA__RLC_SPM_SE3_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT                                  0xb
27604 #define RLC_DSM_CNTLA__RLC_SPM_SE0_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK                                        0x00000003L
27605 #define RLC_DSM_CNTLA__RLC_SPM_SE0_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK                                    0x00000004L
27606 #define RLC_DSM_CNTLA__RLC_SPM_SE1_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK                                        0x00000018L
27607 #define RLC_DSM_CNTLA__RLC_SPM_SE1_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK                                    0x00000020L
27608 #define RLC_DSM_CNTLA__RLC_SPM_SE2_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK                                        0x000000C0L
27609 #define RLC_DSM_CNTLA__RLC_SPM_SE2_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK                                    0x00000100L
27610 #define RLC_DSM_CNTLA__RLC_SPM_SE3_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK                                        0x00000600L
27611 #define RLC_DSM_CNTLA__RLC_SPM_SE3_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK                                    0x00000800L
27612 //RLC_DSM_CNTL2
27613 #define RLC_DSM_CNTL2__RLCG_INSTR_RAM_ENABLE_ERROR_INJECT__SHIFT                                              0x0
27614 #define RLC_DSM_CNTL2__RLCG_INSTR_RAM_SELECT_INJECT_DELAY__SHIFT                                              0x2
27615 #define RLC_DSM_CNTL2__RLCG_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT                                            0x3
27616 #define RLC_DSM_CNTL2__RLCG_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT                                            0x5
27617 #define RLC_DSM_CNTL2__RLCV_INSTR_RAM_ENABLE_ERROR_INJECT__SHIFT                                              0x6
27618 #define RLC_DSM_CNTL2__RLCV_INSTR_RAM_SELECT_INJECT_DELAY__SHIFT                                              0x8
27619 #define RLC_DSM_CNTL2__RLCV_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT                                            0x9
27620 #define RLC_DSM_CNTL2__RLCV_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT                                            0xb
27621 #define RLC_DSM_CNTL2__RLC_TCTAG_RAM_ENABLE_ERROR_INJECT__SHIFT                                               0xc
27622 #define RLC_DSM_CNTL2__RLC_TCTAG_RAM_SELECT_INJECT_DELAY__SHIFT                                               0xe
27623 #define RLC_DSM_CNTL2__RLC_SPM_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT                                         0xf
27624 #define RLC_DSM_CNTL2__RLC_SPM_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT                                         0x11
27625 #define RLC_DSM_CNTL2__RLC_SRM_DATA_RAM_ENABLE_ERROR_INJECT__SHIFT                                            0x12
27626 #define RLC_DSM_CNTL2__RLC_SRM_DATA_RAM_SELECT_INJECT_DELAY__SHIFT                                            0x14
27627 #define RLC_DSM_CNTL2__RLC_SRM_ADDR_RAM_ENABLE_ERROR_INJECT__SHIFT                                            0x15
27628 #define RLC_DSM_CNTL2__RLC_SRM_ADDR_RAM_SELECT_INJECT_DELAY__SHIFT                                            0x17
27629 #define RLC_DSM_CNTL2__INJECT_DELAY__SHIFT                                                                    0x1a
27630 #define RLC_DSM_CNTL2__RLCG_INSTR_RAM_ENABLE_ERROR_INJECT_MASK                                                0x00000003L
27631 #define RLC_DSM_CNTL2__RLCG_INSTR_RAM_SELECT_INJECT_DELAY_MASK                                                0x00000004L
27632 #define RLC_DSM_CNTL2__RLCG_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK                                              0x00000018L
27633 #define RLC_DSM_CNTL2__RLCG_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK                                              0x00000020L
27634 #define RLC_DSM_CNTL2__RLCV_INSTR_RAM_ENABLE_ERROR_INJECT_MASK                                                0x000000C0L
27635 #define RLC_DSM_CNTL2__RLCV_INSTR_RAM_SELECT_INJECT_DELAY_MASK                                                0x00000100L
27636 #define RLC_DSM_CNTL2__RLCV_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK                                              0x00000600L
27637 #define RLC_DSM_CNTL2__RLCV_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK                                              0x00000800L
27638 #define RLC_DSM_CNTL2__RLC_TCTAG_RAM_ENABLE_ERROR_INJECT_MASK                                                 0x00003000L
27639 #define RLC_DSM_CNTL2__RLC_TCTAG_RAM_SELECT_INJECT_DELAY_MASK                                                 0x00004000L
27640 #define RLC_DSM_CNTL2__RLC_SPM_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK                                           0x00018000L
27641 #define RLC_DSM_CNTL2__RLC_SPM_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK                                           0x00020000L
27642 #define RLC_DSM_CNTL2__RLC_SRM_DATA_RAM_ENABLE_ERROR_INJECT_MASK                                              0x000C0000L
27643 #define RLC_DSM_CNTL2__RLC_SRM_DATA_RAM_SELECT_INJECT_DELAY_MASK                                              0x00100000L
27644 #define RLC_DSM_CNTL2__RLC_SRM_ADDR_RAM_ENABLE_ERROR_INJECT_MASK                                              0x00600000L
27645 #define RLC_DSM_CNTL2__RLC_SRM_ADDR_RAM_SELECT_INJECT_DELAY_MASK                                              0x00800000L
27646 #define RLC_DSM_CNTL2__INJECT_DELAY_MASK                                                                      0xFC000000L
27647 //RLC_DSM_CNTL2A
27648 #define RLC_DSM_CNTL2A__RLC_SPM_SE0_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT                                    0x0
27649 #define RLC_DSM_CNTL2A__RLC_SPM_SE0_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT                                    0x2
27650 #define RLC_DSM_CNTL2A__RLC_SPM_SE1_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT                                    0x3
27651 #define RLC_DSM_CNTL2A__RLC_SPM_SE1_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT                                    0x5
27652 #define RLC_DSM_CNTL2A__RLC_SPM_SE2_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT                                    0x6
27653 #define RLC_DSM_CNTL2A__RLC_SPM_SE2_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT                                    0x8
27654 #define RLC_DSM_CNTL2A__RLC_SPM_SE3_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT                                    0x9
27655 #define RLC_DSM_CNTL2A__RLC_SPM_SE3_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT                                    0xb
27656 #define RLC_DSM_CNTL2A__RLC_SPM_SE0_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK                                      0x00000003L
27657 #define RLC_DSM_CNTL2A__RLC_SPM_SE0_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK                                      0x00000004L
27658 #define RLC_DSM_CNTL2A__RLC_SPM_SE1_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK                                      0x00000018L
27659 #define RLC_DSM_CNTL2A__RLC_SPM_SE1_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK                                      0x00000020L
27660 #define RLC_DSM_CNTL2A__RLC_SPM_SE2_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK                                      0x000000C0L
27661 #define RLC_DSM_CNTL2A__RLC_SPM_SE2_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK                                      0x00000100L
27662 #define RLC_DSM_CNTL2A__RLC_SPM_SE3_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK                                      0x00000600L
27663 #define RLC_DSM_CNTL2A__RLC_SPM_SE3_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK                                      0x00000800L
27664 //RLC_CE_ERR_STATUS_LOW
27665 #define RLC_CE_ERR_STATUS_LOW__ERR_STATUS_VALID_FLAG__SHIFT                                                   0x0
27666 #define RLC_CE_ERR_STATUS_LOW__ADDRESS_VALID_FLAG__SHIFT                                                      0x1
27667 #define RLC_CE_ERR_STATUS_LOW__ADDRESS__SHIFT                                                                 0x2
27668 #define RLC_CE_ERR_STATUS_LOW__MEMORY_ID__SHIFT                                                               0x18
27669 #define RLC_CE_ERR_STATUS_LOW__ERR_STATUS_VALID_FLAG_MASK                                                     0x00000001L
27670 #define RLC_CE_ERR_STATUS_LOW__ADDRESS_VALID_FLAG_MASK                                                        0x00000002L
27671 #define RLC_CE_ERR_STATUS_LOW__ADDRESS_MASK                                                                   0x00FFFFFCL
27672 #define RLC_CE_ERR_STATUS_LOW__MEMORY_ID_MASK                                                                 0xFF000000L
27673 //RLC_CE_ERR_STATUS_HIGH
27674 #define RLC_CE_ERR_STATUS_HIGH__ECC__SHIFT                                                                    0x0
27675 #define RLC_CE_ERR_STATUS_HIGH__OTHER__SHIFT                                                                  0x1
27676 #define RLC_CE_ERR_STATUS_HIGH__ERR_INFO_VALID_FLAG__SHIFT                                                    0x2
27677 #define RLC_CE_ERR_STATUS_HIGH__ERR_INFO__SHIFT                                                               0x3
27678 #define RLC_CE_ERR_STATUS_HIGH__CE_CNT__SHIFT                                                                 0x17
27679 #define RLC_CE_ERR_STATUS_HIGH__POISON__SHIFT                                                                 0x1a
27680 #define RLC_CE_ERR_STATUS_HIGH__RESERVED__SHIFT                                                               0x1b
27681 #define RLC_CE_ERR_STATUS_HIGH__ECC_MASK                                                                      0x00000001L
27682 #define RLC_CE_ERR_STATUS_HIGH__OTHER_MASK                                                                    0x00000002L
27683 #define RLC_CE_ERR_STATUS_HIGH__ERR_INFO_VALID_FLAG_MASK                                                      0x00000004L
27684 #define RLC_CE_ERR_STATUS_HIGH__ERR_INFO_MASK                                                                 0x007FFFF8L
27685 #define RLC_CE_ERR_STATUS_HIGH__CE_CNT_MASK                                                                   0x03800000L
27686 #define RLC_CE_ERR_STATUS_HIGH__POISON_MASK                                                                   0x04000000L
27687 #define RLC_CE_ERR_STATUS_HIGH__RESERVED_MASK                                                                 0xF8000000L
27688 //RLC_RLCV_SPARE_INT
27689 #define RLC_RLCV_SPARE_INT__INTERRUPT__SHIFT                                                                  0x0
27690 #define RLC_RLCV_SPARE_INT__RESERVED__SHIFT                                                                   0x1
27691 #define RLC_RLCV_SPARE_INT__INTERRUPT_MASK                                                                    0x00000001L
27692 #define RLC_RLCV_SPARE_INT__RESERVED_MASK                                                                     0xFFFFFFFEL
27693 //RLC_SMU_CLK_REQ
27694 #define RLC_SMU_CLK_REQ__VALID__SHIFT                                                                         0x0
27695 #define RLC_SMU_CLK_REQ__VALID_MASK                                                                           0x00000001L
27696 
27697 
27698 // addressBlock: xcd0_gc_pwrdec
27699 //CGTS_SM_CTRL_REG
27700 #define CGTS_SM_CTRL_REG__ON_SEQ_DELAY__SHIFT                                                                 0x0
27701 #define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY__SHIFT                                                                0x4
27702 #define CGTS_SM_CTRL_REG__MGCG_ENABLED__SHIFT                                                                 0xc
27703 #define CGTS_SM_CTRL_REG__BASE_MODE__SHIFT                                                                    0x10
27704 #define CGTS_SM_CTRL_REG__SM_MODE__SHIFT                                                                      0x11
27705 #define CGTS_SM_CTRL_REG__SM_MODE_ENABLE__SHIFT                                                               0x14
27706 #define CGTS_SM_CTRL_REG__OVERRIDE__SHIFT                                                                     0x15
27707 #define CGTS_SM_CTRL_REG__LS_OVERRIDE__SHIFT                                                                  0x16
27708 #define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN__SHIFT                                                            0x17
27709 #define CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT                                                               0x18
27710 #define CGTS_SM_CTRL_REG__ON_SEQ_DELAY_MASK                                                                   0x0000000FL
27711 #define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY_MASK                                                                  0x00000FF0L
27712 #define CGTS_SM_CTRL_REG__MGCG_ENABLED_MASK                                                                   0x00001000L
27713 #define CGTS_SM_CTRL_REG__BASE_MODE_MASK                                                                      0x00010000L
27714 #define CGTS_SM_CTRL_REG__SM_MODE_MASK                                                                        0x000E0000L
27715 #define CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK                                                                 0x00100000L
27716 #define CGTS_SM_CTRL_REG__OVERRIDE_MASK                                                                       0x00200000L
27717 #define CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK                                                                    0x00400000L
27718 #define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK                                                              0x00800000L
27719 #define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK                                                                 0xFF000000L
27720 //CGTS_RD_CTRL_REG
27721 #define CGTS_RD_CTRL_REG__ROW_MUX_SEL__SHIFT                                                                  0x0
27722 #define CGTS_RD_CTRL_REG__REG_MUX_SEL__SHIFT                                                                  0x8
27723 #define CGTS_RD_CTRL_REG__ROW_MUX_SEL_MASK                                                                    0x0000001FL
27724 #define CGTS_RD_CTRL_REG__REG_MUX_SEL_MASK                                                                    0x00001F00L
27725 //CGTS_RD_REG
27726 #define CGTS_RD_REG__READ_DATA__SHIFT                                                                         0x0
27727 #define CGTS_RD_REG__READ_DATA_MASK                                                                           0x00003FFFL
27728 //CGTS_TCC_DISABLE
27729 #define CGTS_TCC_DISABLE__WRITE_DIS__SHIFT                                                                    0x0
27730 #define CGTS_TCC_DISABLE__TCC_DISABLE__SHIFT                                                                  0x10
27731 #define CGTS_TCC_DISABLE__WRITE_DIS_MASK                                                                      0x00000001L
27732 #define CGTS_TCC_DISABLE__TCC_DISABLE_MASK                                                                    0xFFFF0000L
27733 //CGTS_USER_TCC_DISABLE
27734 #define CGTS_USER_TCC_DISABLE__TCC_DISABLE__SHIFT                                                             0x10
27735 #define CGTS_USER_TCC_DISABLE__TCC_DISABLE_MASK                                                               0xFFFF0000L
27736 //CGTS_CU0_SP0_CTRL_REG
27737 #define CGTS_CU0_SP0_CTRL_REG__SP00__SHIFT                                                                    0x0
27738 #define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT                                                           0x7
27739 #define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT                                                      0x8
27740 #define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT                                                        0xa
27741 #define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT                                                  0xb
27742 #define CGTS_CU0_SP0_CTRL_REG__SP01__SHIFT                                                                    0x10
27743 #define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT                                                           0x17
27744 #define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT                                                      0x18
27745 #define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT                                                        0x1a
27746 #define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT                                                  0x1b
27747 #define CGTS_CU0_SP0_CTRL_REG__SP00_MASK                                                                      0x0000007FL
27748 #define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE_MASK                                                             0x00000080L
27749 #define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK                                                        0x00000300L
27750 #define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK                                                          0x00000400L
27751 #define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK                                                    0x00000800L
27752 #define CGTS_CU0_SP0_CTRL_REG__SP01_MASK                                                                      0x007F0000L
27753 #define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE_MASK                                                             0x00800000L
27754 #define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK                                                        0x03000000L
27755 #define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK                                                          0x04000000L
27756 #define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK                                                    0x08000000L
27757 //CGTS_CU0_LDS_SQ_CTRL_REG
27758 #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS__SHIFT                                                                  0x0
27759 #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT                                                         0x7
27760 #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT                                                    0x8
27761 #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT                                                      0xa
27762 #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
27763 #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ__SHIFT                                                                   0x10
27764 #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT                                                          0x17
27765 #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT                                                     0x18
27766 #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT                                                       0x1a
27767 #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
27768 #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_MASK                                                                    0x0000007FL
27769 #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK                                                           0x00000080L
27770 #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK                                                      0x00000300L
27771 #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK                                                        0x00000400L
27772 #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
27773 #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_MASK                                                                     0x007F0000L
27774 #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK                                                            0x00800000L
27775 #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK                                                       0x03000000L
27776 #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK                                                         0x04000000L
27777 #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
27778 //CGTS_CU0_TA_SQC_CTRL_REG
27779 #define CGTS_CU0_TA_SQC_CTRL_REG__TA__SHIFT                                                                   0x0
27780 #define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT                                                          0x7
27781 #define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                                     0x8
27782 #define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                                       0xa
27783 #define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
27784 #define CGTS_CU0_TA_SQC_CTRL_REG__SQC__SHIFT                                                                  0x10
27785 #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT                                                         0x17
27786 #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT                                                    0x18
27787 #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT                                                      0x1a
27788 #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT                                                0x1b
27789 #define CGTS_CU0_TA_SQC_CTRL_REG__TA_MASK                                                                     0x0000007FL
27790 #define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK                                                            0x00000080L
27791 #define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                                       0x00000300L
27792 #define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK                                                         0x00000400L
27793 #define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
27794 #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_MASK                                                                    0x007F0000L
27795 #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK                                                           0x00800000L
27796 #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK                                                      0x03000000L
27797 #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK                                                        0x04000000L
27798 #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK                                                  0x08000000L
27799 //CGTS_CU0_SP1_CTRL_REG
27800 #define CGTS_CU0_SP1_CTRL_REG__SP10__SHIFT                                                                    0x0
27801 #define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT                                                           0x7
27802 #define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT                                                      0x8
27803 #define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT                                                        0xa
27804 #define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT                                                  0xb
27805 #define CGTS_CU0_SP1_CTRL_REG__SP11__SHIFT                                                                    0x10
27806 #define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT                                                           0x17
27807 #define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT                                                      0x18
27808 #define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT                                                        0x1a
27809 #define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT                                                  0x1b
27810 #define CGTS_CU0_SP1_CTRL_REG__SP10_MASK                                                                      0x0000007FL
27811 #define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE_MASK                                                             0x00000080L
27812 #define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK                                                        0x00000300L
27813 #define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK                                                          0x00000400L
27814 #define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK                                                    0x00000800L
27815 #define CGTS_CU0_SP1_CTRL_REG__SP11_MASK                                                                      0x007F0000L
27816 #define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE_MASK                                                             0x00800000L
27817 #define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK                                                        0x03000000L
27818 #define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK                                                          0x04000000L
27819 #define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK                                                    0x08000000L
27820 //CGTS_CU0_TD_TCP_CTRL_REG
27821 #define CGTS_CU0_TD_TCP_CTRL_REG__TD__SHIFT                                                                   0x0
27822 #define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT                                                          0x7
27823 #define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                                     0x8
27824 #define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                                       0xa
27825 #define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
27826 #define CGTS_CU0_TD_TCP_CTRL_REG__TCPF__SHIFT                                                                 0x10
27827 #define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                        0x17
27828 #define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                                   0x18
27829 #define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                                     0x1a
27830 #define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                               0x1b
27831 #define CGTS_CU0_TD_TCP_CTRL_REG__TD_MASK                                                                     0x0000007FL
27832 #define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK                                                            0x00000080L
27833 #define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                                       0x00000300L
27834 #define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK                                                         0x00000400L
27835 #define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
27836 #define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_MASK                                                                   0x007F0000L
27837 #define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                          0x00800000L
27838 #define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                                     0x03000000L
27839 #define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                       0x04000000L
27840 #define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                                 0x08000000L
27841 //CGTS_CU1_SP0_CTRL_REG
27842 #define CGTS_CU1_SP0_CTRL_REG__SP00__SHIFT                                                                    0x0
27843 #define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT                                                           0x7
27844 #define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT                                                      0x8
27845 #define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT                                                        0xa
27846 #define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT                                                  0xb
27847 #define CGTS_CU1_SP0_CTRL_REG__SP01__SHIFT                                                                    0x10
27848 #define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT                                                           0x17
27849 #define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT                                                      0x18
27850 #define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT                                                        0x1a
27851 #define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT                                                  0x1b
27852 #define CGTS_CU1_SP0_CTRL_REG__SP00_MASK                                                                      0x0000007FL
27853 #define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE_MASK                                                             0x00000080L
27854 #define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK                                                        0x00000300L
27855 #define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK                                                          0x00000400L
27856 #define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK                                                    0x00000800L
27857 #define CGTS_CU1_SP0_CTRL_REG__SP01_MASK                                                                      0x007F0000L
27858 #define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE_MASK                                                             0x00800000L
27859 #define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK                                                        0x03000000L
27860 #define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK                                                          0x04000000L
27861 #define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK                                                    0x08000000L
27862 //CGTS_CU1_LDS_SQ_CTRL_REG
27863 #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS__SHIFT                                                                  0x0
27864 #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT                                                         0x7
27865 #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT                                                    0x8
27866 #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT                                                      0xa
27867 #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
27868 #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ__SHIFT                                                                   0x10
27869 #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT                                                          0x17
27870 #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT                                                     0x18
27871 #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT                                                       0x1a
27872 #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
27873 #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_MASK                                                                    0x0000007FL
27874 #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK                                                           0x00000080L
27875 #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK                                                      0x00000300L
27876 #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK                                                        0x00000400L
27877 #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
27878 #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_MASK                                                                     0x007F0000L
27879 #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK                                                            0x00800000L
27880 #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK                                                       0x03000000L
27881 #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK                                                         0x04000000L
27882 #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
27883 //CGTS_CU1_TA_SQC_CTRL_REG
27884 #define CGTS_CU1_TA_SQC_CTRL_REG__TA__SHIFT                                                                   0x0
27885 #define CGTS_CU1_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT                                                          0x7
27886 #define CGTS_CU1_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                                     0x8
27887 #define CGTS_CU1_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                                       0xa
27888 #define CGTS_CU1_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
27889 #define CGTS_CU1_TA_SQC_CTRL_REG__TA_MASK                                                                     0x0000007FL
27890 #define CGTS_CU1_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK                                                            0x00000080L
27891 #define CGTS_CU1_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                                       0x00000300L
27892 #define CGTS_CU1_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK                                                         0x00000400L
27893 #define CGTS_CU1_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
27894 //CGTS_CU1_SP1_CTRL_REG
27895 #define CGTS_CU1_SP1_CTRL_REG__SP10__SHIFT                                                                    0x0
27896 #define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT                                                           0x7
27897 #define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT                                                      0x8
27898 #define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT                                                        0xa
27899 #define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT                                                  0xb
27900 #define CGTS_CU1_SP1_CTRL_REG__SP11__SHIFT                                                                    0x10
27901 #define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT                                                           0x17
27902 #define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT                                                      0x18
27903 #define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT                                                        0x1a
27904 #define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT                                                  0x1b
27905 #define CGTS_CU1_SP1_CTRL_REG__SP10_MASK                                                                      0x0000007FL
27906 #define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE_MASK                                                             0x00000080L
27907 #define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK                                                        0x00000300L
27908 #define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK                                                          0x00000400L
27909 #define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK                                                    0x00000800L
27910 #define CGTS_CU1_SP1_CTRL_REG__SP11_MASK                                                                      0x007F0000L
27911 #define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE_MASK                                                             0x00800000L
27912 #define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK                                                        0x03000000L
27913 #define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK                                                          0x04000000L
27914 #define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK                                                    0x08000000L
27915 //CGTS_CU1_TD_TCP_CTRL_REG
27916 #define CGTS_CU1_TD_TCP_CTRL_REG__TD__SHIFT                                                                   0x0
27917 #define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT                                                          0x7
27918 #define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                                     0x8
27919 #define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                                       0xa
27920 #define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
27921 #define CGTS_CU1_TD_TCP_CTRL_REG__TCPF__SHIFT                                                                 0x10
27922 #define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                        0x17
27923 #define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                                   0x18
27924 #define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                                     0x1a
27925 #define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                               0x1b
27926 #define CGTS_CU1_TD_TCP_CTRL_REG__TD_MASK                                                                     0x0000007FL
27927 #define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK                                                            0x00000080L
27928 #define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                                       0x00000300L
27929 #define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK                                                         0x00000400L
27930 #define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
27931 #define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_MASK                                                                   0x007F0000L
27932 #define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                          0x00800000L
27933 #define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                                     0x03000000L
27934 #define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                       0x04000000L
27935 #define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                                 0x08000000L
27936 //CGTS_CU2_SP0_CTRL_REG
27937 #define CGTS_CU2_SP0_CTRL_REG__SP00__SHIFT                                                                    0x0
27938 #define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT                                                           0x7
27939 #define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT                                                      0x8
27940 #define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT                                                        0xa
27941 #define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT                                                  0xb
27942 #define CGTS_CU2_SP0_CTRL_REG__SP01__SHIFT                                                                    0x10
27943 #define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT                                                           0x17
27944 #define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT                                                      0x18
27945 #define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT                                                        0x1a
27946 #define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT                                                  0x1b
27947 #define CGTS_CU2_SP0_CTRL_REG__SP00_MASK                                                                      0x0000007FL
27948 #define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE_MASK                                                             0x00000080L
27949 #define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK                                                        0x00000300L
27950 #define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK                                                          0x00000400L
27951 #define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK                                                    0x00000800L
27952 #define CGTS_CU2_SP0_CTRL_REG__SP01_MASK                                                                      0x007F0000L
27953 #define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE_MASK                                                             0x00800000L
27954 #define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK                                                        0x03000000L
27955 #define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK                                                          0x04000000L
27956 #define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK                                                    0x08000000L
27957 //CGTS_CU2_LDS_SQ_CTRL_REG
27958 #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS__SHIFT                                                                  0x0
27959 #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT                                                         0x7
27960 #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT                                                    0x8
27961 #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT                                                      0xa
27962 #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
27963 #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ__SHIFT                                                                   0x10
27964 #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT                                                          0x17
27965 #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT                                                     0x18
27966 #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT                                                       0x1a
27967 #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
27968 #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_MASK                                                                    0x0000007FL
27969 #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK                                                           0x00000080L
27970 #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK                                                      0x00000300L
27971 #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK                                                        0x00000400L
27972 #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
27973 #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_MASK                                                                     0x007F0000L
27974 #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK                                                            0x00800000L
27975 #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK                                                       0x03000000L
27976 #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK                                                         0x04000000L
27977 #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
27978 //CGTS_CU2_TA_SQC_CTRL_REG
27979 #define CGTS_CU2_TA_SQC_CTRL_REG__TA__SHIFT                                                                   0x0
27980 #define CGTS_CU2_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT                                                          0x7
27981 #define CGTS_CU2_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                                     0x8
27982 #define CGTS_CU2_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                                       0xa
27983 #define CGTS_CU2_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
27984 #define CGTS_CU2_TA_SQC_CTRL_REG__SQC__SHIFT                                                                  0x10
27985 #define CGTS_CU2_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT                                                         0x17
27986 #define CGTS_CU2_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT                                                    0x18
27987 #define CGTS_CU2_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT                                                      0x1a
27988 #define CGTS_CU2_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT                                                0x1b
27989 #define CGTS_CU2_TA_SQC_CTRL_REG__TA_MASK                                                                     0x0000007FL
27990 #define CGTS_CU2_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK                                                            0x00000080L
27991 #define CGTS_CU2_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                                       0x00000300L
27992 #define CGTS_CU2_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK                                                         0x00000400L
27993 #define CGTS_CU2_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
27994 #define CGTS_CU2_TA_SQC_CTRL_REG__SQC_MASK                                                                    0x007F0000L
27995 #define CGTS_CU2_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK                                                           0x00800000L
27996 #define CGTS_CU2_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK                                                      0x03000000L
27997 #define CGTS_CU2_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK                                                        0x04000000L
27998 #define CGTS_CU2_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK                                                  0x08000000L
27999 //CGTS_CU2_SP1_CTRL_REG
28000 #define CGTS_CU2_SP1_CTRL_REG__SP10__SHIFT                                                                    0x0
28001 #define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT                                                           0x7
28002 #define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT                                                      0x8
28003 #define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT                                                        0xa
28004 #define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT                                                  0xb
28005 #define CGTS_CU2_SP1_CTRL_REG__SP11__SHIFT                                                                    0x10
28006 #define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT                                                           0x17
28007 #define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT                                                      0x18
28008 #define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT                                                        0x1a
28009 #define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT                                                  0x1b
28010 #define CGTS_CU2_SP1_CTRL_REG__SP10_MASK                                                                      0x0000007FL
28011 #define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE_MASK                                                             0x00000080L
28012 #define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK                                                        0x00000300L
28013 #define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK                                                          0x00000400L
28014 #define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK                                                    0x00000800L
28015 #define CGTS_CU2_SP1_CTRL_REG__SP11_MASK                                                                      0x007F0000L
28016 #define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE_MASK                                                             0x00800000L
28017 #define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK                                                        0x03000000L
28018 #define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK                                                          0x04000000L
28019 #define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK                                                    0x08000000L
28020 //CGTS_CU2_TD_TCP_CTRL_REG
28021 #define CGTS_CU2_TD_TCP_CTRL_REG__TD__SHIFT                                                                   0x0
28022 #define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT                                                          0x7
28023 #define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                                     0x8
28024 #define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                                       0xa
28025 #define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
28026 #define CGTS_CU2_TD_TCP_CTRL_REG__TCPF__SHIFT                                                                 0x10
28027 #define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                        0x17
28028 #define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                                   0x18
28029 #define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                                     0x1a
28030 #define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                               0x1b
28031 #define CGTS_CU2_TD_TCP_CTRL_REG__TD_MASK                                                                     0x0000007FL
28032 #define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK                                                            0x00000080L
28033 #define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                                       0x00000300L
28034 #define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK                                                         0x00000400L
28035 #define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
28036 #define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_MASK                                                                   0x007F0000L
28037 #define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                          0x00800000L
28038 #define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                                     0x03000000L
28039 #define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                       0x04000000L
28040 #define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                                 0x08000000L
28041 //CGTS_CU3_SP0_CTRL_REG
28042 #define CGTS_CU3_SP0_CTRL_REG__SP00__SHIFT                                                                    0x0
28043 #define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT                                                           0x7
28044 #define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT                                                      0x8
28045 #define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT                                                        0xa
28046 #define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT                                                  0xb
28047 #define CGTS_CU3_SP0_CTRL_REG__SP01__SHIFT                                                                    0x10
28048 #define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT                                                           0x17
28049 #define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT                                                      0x18
28050 #define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT                                                        0x1a
28051 #define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT                                                  0x1b
28052 #define CGTS_CU3_SP0_CTRL_REG__SP00_MASK                                                                      0x0000007FL
28053 #define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE_MASK                                                             0x00000080L
28054 #define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK                                                        0x00000300L
28055 #define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK                                                          0x00000400L
28056 #define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK                                                    0x00000800L
28057 #define CGTS_CU3_SP0_CTRL_REG__SP01_MASK                                                                      0x007F0000L
28058 #define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE_MASK                                                             0x00800000L
28059 #define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK                                                        0x03000000L
28060 #define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK                                                          0x04000000L
28061 #define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK                                                    0x08000000L
28062 //CGTS_CU3_LDS_SQ_CTRL_REG
28063 #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS__SHIFT                                                                  0x0
28064 #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT                                                         0x7
28065 #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT                                                    0x8
28066 #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT                                                      0xa
28067 #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
28068 #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ__SHIFT                                                                   0x10
28069 #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT                                                          0x17
28070 #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT                                                     0x18
28071 #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT                                                       0x1a
28072 #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
28073 #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_MASK                                                                    0x0000007FL
28074 #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK                                                           0x00000080L
28075 #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK                                                      0x00000300L
28076 #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK                                                        0x00000400L
28077 #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
28078 #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_MASK                                                                     0x007F0000L
28079 #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK                                                            0x00800000L
28080 #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK                                                       0x03000000L
28081 #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK                                                         0x04000000L
28082 #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
28083 //CGTS_CU3_TA_SQC_CTRL_REG
28084 #define CGTS_CU3_TA_SQC_CTRL_REG__TA__SHIFT                                                                   0x0
28085 #define CGTS_CU3_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT                                                          0x7
28086 #define CGTS_CU3_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                                     0x8
28087 #define CGTS_CU3_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                                       0xa
28088 #define CGTS_CU3_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
28089 #define CGTS_CU3_TA_SQC_CTRL_REG__TA_MASK                                                                     0x0000007FL
28090 #define CGTS_CU3_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK                                                            0x00000080L
28091 #define CGTS_CU3_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                                       0x00000300L
28092 #define CGTS_CU3_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK                                                         0x00000400L
28093 #define CGTS_CU3_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
28094 //CGTS_CU3_SP1_CTRL_REG
28095 #define CGTS_CU3_SP1_CTRL_REG__SP10__SHIFT                                                                    0x0
28096 #define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT                                                           0x7
28097 #define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT                                                      0x8
28098 #define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT                                                        0xa
28099 #define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT                                                  0xb
28100 #define CGTS_CU3_SP1_CTRL_REG__SP11__SHIFT                                                                    0x10
28101 #define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT                                                           0x17
28102 #define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT                                                      0x18
28103 #define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT                                                        0x1a
28104 #define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT                                                  0x1b
28105 #define CGTS_CU3_SP1_CTRL_REG__SP10_MASK                                                                      0x0000007FL
28106 #define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE_MASK                                                             0x00000080L
28107 #define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK                                                        0x00000300L
28108 #define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK                                                          0x00000400L
28109 #define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK                                                    0x00000800L
28110 #define CGTS_CU3_SP1_CTRL_REG__SP11_MASK                                                                      0x007F0000L
28111 #define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE_MASK                                                             0x00800000L
28112 #define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK                                                        0x03000000L
28113 #define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK                                                          0x04000000L
28114 #define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK                                                    0x08000000L
28115 //CGTS_CU3_TD_TCP_CTRL_REG
28116 #define CGTS_CU3_TD_TCP_CTRL_REG__TD__SHIFT                                                                   0x0
28117 #define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT                                                          0x7
28118 #define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                                     0x8
28119 #define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                                       0xa
28120 #define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
28121 #define CGTS_CU3_TD_TCP_CTRL_REG__TCPF__SHIFT                                                                 0x10
28122 #define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                        0x17
28123 #define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                                   0x18
28124 #define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                                     0x1a
28125 #define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                               0x1b
28126 #define CGTS_CU3_TD_TCP_CTRL_REG__TD_MASK                                                                     0x0000007FL
28127 #define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK                                                            0x00000080L
28128 #define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                                       0x00000300L
28129 #define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK                                                         0x00000400L
28130 #define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
28131 #define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_MASK                                                                   0x007F0000L
28132 #define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                          0x00800000L
28133 #define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                                     0x03000000L
28134 #define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                       0x04000000L
28135 #define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                                 0x08000000L
28136 //CGTS_CU4_SP0_CTRL_REG
28137 #define CGTS_CU4_SP0_CTRL_REG__SP00__SHIFT                                                                    0x0
28138 #define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT                                                           0x7
28139 #define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT                                                      0x8
28140 #define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT                                                        0xa
28141 #define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT                                                  0xb
28142 #define CGTS_CU4_SP0_CTRL_REG__SP01__SHIFT                                                                    0x10
28143 #define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT                                                           0x17
28144 #define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT                                                      0x18
28145 #define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT                                                        0x1a
28146 #define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT                                                  0x1b
28147 #define CGTS_CU4_SP0_CTRL_REG__SP00_MASK                                                                      0x0000007FL
28148 #define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE_MASK                                                             0x00000080L
28149 #define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK                                                        0x00000300L
28150 #define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK                                                          0x00000400L
28151 #define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK                                                    0x00000800L
28152 #define CGTS_CU4_SP0_CTRL_REG__SP01_MASK                                                                      0x007F0000L
28153 #define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE_MASK                                                             0x00800000L
28154 #define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK                                                        0x03000000L
28155 #define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK                                                          0x04000000L
28156 #define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK                                                    0x08000000L
28157 //CGTS_CU4_LDS_SQ_CTRL_REG
28158 #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS__SHIFT                                                                  0x0
28159 #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT                                                         0x7
28160 #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT                                                    0x8
28161 #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT                                                      0xa
28162 #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
28163 #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ__SHIFT                                                                   0x10
28164 #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT                                                          0x17
28165 #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT                                                     0x18
28166 #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT                                                       0x1a
28167 #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
28168 #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_MASK                                                                    0x0000007FL
28169 #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK                                                           0x00000080L
28170 #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK                                                      0x00000300L
28171 #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK                                                        0x00000400L
28172 #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
28173 #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_MASK                                                                     0x007F0000L
28174 #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK                                                            0x00800000L
28175 #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK                                                       0x03000000L
28176 #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK                                                         0x04000000L
28177 #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
28178 //CGTS_CU4_TA_SQC_CTRL_REG
28179 #define CGTS_CU4_TA_SQC_CTRL_REG__TA__SHIFT                                                                   0x0
28180 #define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT                                                          0x7
28181 #define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                                     0x8
28182 #define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                                       0xa
28183 #define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
28184 #define CGTS_CU4_TA_SQC_CTRL_REG__SQC__SHIFT                                                                  0x10
28185 #define CGTS_CU4_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT                                                         0x17
28186 #define CGTS_CU4_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT                                                    0x18
28187 #define CGTS_CU4_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT                                                      0x1a
28188 #define CGTS_CU4_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT                                                0x1b
28189 #define CGTS_CU4_TA_SQC_CTRL_REG__TA_MASK                                                                     0x0000007FL
28190 #define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK                                                            0x00000080L
28191 #define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                                       0x00000300L
28192 #define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK                                                         0x00000400L
28193 #define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
28194 #define CGTS_CU4_TA_SQC_CTRL_REG__SQC_MASK                                                                    0x007F0000L
28195 #define CGTS_CU4_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK                                                           0x00800000L
28196 #define CGTS_CU4_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK                                                      0x03000000L
28197 #define CGTS_CU4_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK                                                        0x04000000L
28198 #define CGTS_CU4_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK                                                  0x08000000L
28199 //CGTS_CU4_SP1_CTRL_REG
28200 #define CGTS_CU4_SP1_CTRL_REG__SP10__SHIFT                                                                    0x0
28201 #define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT                                                           0x7
28202 #define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT                                                      0x8
28203 #define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT                                                        0xa
28204 #define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT                                                  0xb
28205 #define CGTS_CU4_SP1_CTRL_REG__SP11__SHIFT                                                                    0x10
28206 #define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT                                                           0x17
28207 #define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT                                                      0x18
28208 #define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT                                                        0x1a
28209 #define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT                                                  0x1b
28210 #define CGTS_CU4_SP1_CTRL_REG__SP10_MASK                                                                      0x0000007FL
28211 #define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE_MASK                                                             0x00000080L
28212 #define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK                                                        0x00000300L
28213 #define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK                                                          0x00000400L
28214 #define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK                                                    0x00000800L
28215 #define CGTS_CU4_SP1_CTRL_REG__SP11_MASK                                                                      0x007F0000L
28216 #define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE_MASK                                                             0x00800000L
28217 #define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK                                                        0x03000000L
28218 #define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK                                                          0x04000000L
28219 #define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK                                                    0x08000000L
28220 //CGTS_CU4_TD_TCP_CTRL_REG
28221 #define CGTS_CU4_TD_TCP_CTRL_REG__TD__SHIFT                                                                   0x0
28222 #define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT                                                          0x7
28223 #define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                                     0x8
28224 #define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                                       0xa
28225 #define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
28226 #define CGTS_CU4_TD_TCP_CTRL_REG__TCPF__SHIFT                                                                 0x10
28227 #define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                        0x17
28228 #define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                                   0x18
28229 #define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                                     0x1a
28230 #define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                               0x1b
28231 #define CGTS_CU4_TD_TCP_CTRL_REG__TD_MASK                                                                     0x0000007FL
28232 #define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK                                                            0x00000080L
28233 #define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                                       0x00000300L
28234 #define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK                                                         0x00000400L
28235 #define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
28236 #define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_MASK                                                                   0x007F0000L
28237 #define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                          0x00800000L
28238 #define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                                     0x03000000L
28239 #define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                       0x04000000L
28240 #define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                                 0x08000000L
28241 //CGTS_CU5_SP0_CTRL_REG
28242 #define CGTS_CU5_SP0_CTRL_REG__SP00__SHIFT                                                                    0x0
28243 #define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT                                                           0x7
28244 #define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT                                                      0x8
28245 #define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT                                                        0xa
28246 #define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT                                                  0xb
28247 #define CGTS_CU5_SP0_CTRL_REG__SP01__SHIFT                                                                    0x10
28248 #define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT                                                           0x17
28249 #define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT                                                      0x18
28250 #define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT                                                        0x1a
28251 #define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT                                                  0x1b
28252 #define CGTS_CU5_SP0_CTRL_REG__SP00_MASK                                                                      0x0000007FL
28253 #define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE_MASK                                                             0x00000080L
28254 #define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK                                                        0x00000300L
28255 #define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK                                                          0x00000400L
28256 #define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK                                                    0x00000800L
28257 #define CGTS_CU5_SP0_CTRL_REG__SP01_MASK                                                                      0x007F0000L
28258 #define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE_MASK                                                             0x00800000L
28259 #define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK                                                        0x03000000L
28260 #define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK                                                          0x04000000L
28261 #define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK                                                    0x08000000L
28262 //CGTS_CU5_LDS_SQ_CTRL_REG
28263 #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS__SHIFT                                                                  0x0
28264 #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT                                                         0x7
28265 #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT                                                    0x8
28266 #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT                                                      0xa
28267 #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
28268 #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ__SHIFT                                                                   0x10
28269 #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT                                                          0x17
28270 #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT                                                     0x18
28271 #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT                                                       0x1a
28272 #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
28273 #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_MASK                                                                    0x0000007FL
28274 #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK                                                           0x00000080L
28275 #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK                                                      0x00000300L
28276 #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK                                                        0x00000400L
28277 #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
28278 #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_MASK                                                                     0x007F0000L
28279 #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK                                                            0x00800000L
28280 #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK                                                       0x03000000L
28281 #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK                                                         0x04000000L
28282 #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
28283 //CGTS_CU5_TA_SQC_CTRL_REG
28284 #define CGTS_CU5_TA_SQC_CTRL_REG__TA__SHIFT                                                                   0x0
28285 #define CGTS_CU5_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT                                                          0x7
28286 #define CGTS_CU5_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                                     0x8
28287 #define CGTS_CU5_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                                       0xa
28288 #define CGTS_CU5_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
28289 #define CGTS_CU5_TA_SQC_CTRL_REG__TA_MASK                                                                     0x0000007FL
28290 #define CGTS_CU5_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK                                                            0x00000080L
28291 #define CGTS_CU5_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                                       0x00000300L
28292 #define CGTS_CU5_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK                                                         0x00000400L
28293 #define CGTS_CU5_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
28294 //CGTS_CU5_SP1_CTRL_REG
28295 #define CGTS_CU5_SP1_CTRL_REG__SP10__SHIFT                                                                    0x0
28296 #define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT                                                           0x7
28297 #define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT                                                      0x8
28298 #define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT                                                        0xa
28299 #define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT                                                  0xb
28300 #define CGTS_CU5_SP1_CTRL_REG__SP11__SHIFT                                                                    0x10
28301 #define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT                                                           0x17
28302 #define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT                                                      0x18
28303 #define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT                                                        0x1a
28304 #define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT                                                  0x1b
28305 #define CGTS_CU5_SP1_CTRL_REG__SP10_MASK                                                                      0x0000007FL
28306 #define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE_MASK                                                             0x00000080L
28307 #define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK                                                        0x00000300L
28308 #define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK                                                          0x00000400L
28309 #define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK                                                    0x00000800L
28310 #define CGTS_CU5_SP1_CTRL_REG__SP11_MASK                                                                      0x007F0000L
28311 #define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE_MASK                                                             0x00800000L
28312 #define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK                                                        0x03000000L
28313 #define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK                                                          0x04000000L
28314 #define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK                                                    0x08000000L
28315 //CGTS_CU5_TD_TCP_CTRL_REG
28316 #define CGTS_CU5_TD_TCP_CTRL_REG__TD__SHIFT                                                                   0x0
28317 #define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT                                                          0x7
28318 #define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                                     0x8
28319 #define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                                       0xa
28320 #define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
28321 #define CGTS_CU5_TD_TCP_CTRL_REG__TCPF__SHIFT                                                                 0x10
28322 #define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                        0x17
28323 #define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                                   0x18
28324 #define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                                     0x1a
28325 #define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                               0x1b
28326 #define CGTS_CU5_TD_TCP_CTRL_REG__TD_MASK                                                                     0x0000007FL
28327 #define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK                                                            0x00000080L
28328 #define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                                       0x00000300L
28329 #define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK                                                         0x00000400L
28330 #define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
28331 #define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_MASK                                                                   0x007F0000L
28332 #define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                          0x00800000L
28333 #define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                                     0x03000000L
28334 #define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                       0x04000000L
28335 #define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                                 0x08000000L
28336 //CGTS_CU6_SP0_CTRL_REG
28337 #define CGTS_CU6_SP0_CTRL_REG__SP00__SHIFT                                                                    0x0
28338 #define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT                                                           0x7
28339 #define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT                                                      0x8
28340 #define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT                                                        0xa
28341 #define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT                                                  0xb
28342 #define CGTS_CU6_SP0_CTRL_REG__SP01__SHIFT                                                                    0x10
28343 #define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT                                                           0x17
28344 #define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT                                                      0x18
28345 #define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT                                                        0x1a
28346 #define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT                                                  0x1b
28347 #define CGTS_CU6_SP0_CTRL_REG__SP00_MASK                                                                      0x0000007FL
28348 #define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE_MASK                                                             0x00000080L
28349 #define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK                                                        0x00000300L
28350 #define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK                                                          0x00000400L
28351 #define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK                                                    0x00000800L
28352 #define CGTS_CU6_SP0_CTRL_REG__SP01_MASK                                                                      0x007F0000L
28353 #define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE_MASK                                                             0x00800000L
28354 #define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK                                                        0x03000000L
28355 #define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK                                                          0x04000000L
28356 #define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK                                                    0x08000000L
28357 //CGTS_CU6_LDS_SQ_CTRL_REG
28358 #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS__SHIFT                                                                  0x0
28359 #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT                                                         0x7
28360 #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT                                                    0x8
28361 #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT                                                      0xa
28362 #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
28363 #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ__SHIFT                                                                   0x10
28364 #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT                                                          0x17
28365 #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT                                                     0x18
28366 #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT                                                       0x1a
28367 #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
28368 #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_MASK                                                                    0x0000007FL
28369 #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK                                                           0x00000080L
28370 #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK                                                      0x00000300L
28371 #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK                                                        0x00000400L
28372 #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
28373 #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_MASK                                                                     0x007F0000L
28374 #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK                                                            0x00800000L
28375 #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK                                                       0x03000000L
28376 #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK                                                         0x04000000L
28377 #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
28378 //CGTS_CU6_TA_SQC_CTRL_REG
28379 #define CGTS_CU6_TA_SQC_CTRL_REG__TA__SHIFT                                                                   0x0
28380 #define CGTS_CU6_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT                                                          0x7
28381 #define CGTS_CU6_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                                     0x8
28382 #define CGTS_CU6_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                                       0xa
28383 #define CGTS_CU6_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
28384 #define CGTS_CU6_TA_SQC_CTRL_REG__SQC__SHIFT                                                                  0x10
28385 #define CGTS_CU6_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT                                                         0x17
28386 #define CGTS_CU6_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT                                                    0x18
28387 #define CGTS_CU6_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT                                                      0x1a
28388 #define CGTS_CU6_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT                                                0x1b
28389 #define CGTS_CU6_TA_SQC_CTRL_REG__TA_MASK                                                                     0x0000007FL
28390 #define CGTS_CU6_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK                                                            0x00000080L
28391 #define CGTS_CU6_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                                       0x00000300L
28392 #define CGTS_CU6_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK                                                         0x00000400L
28393 #define CGTS_CU6_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
28394 #define CGTS_CU6_TA_SQC_CTRL_REG__SQC_MASK                                                                    0x007F0000L
28395 #define CGTS_CU6_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK                                                           0x00800000L
28396 #define CGTS_CU6_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK                                                      0x03000000L
28397 #define CGTS_CU6_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK                                                        0x04000000L
28398 #define CGTS_CU6_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK                                                  0x08000000L
28399 //CGTS_CU6_SP1_CTRL_REG
28400 #define CGTS_CU6_SP1_CTRL_REG__SP10__SHIFT                                                                    0x0
28401 #define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT                                                           0x7
28402 #define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT                                                      0x8
28403 #define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT                                                        0xa
28404 #define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT                                                  0xb
28405 #define CGTS_CU6_SP1_CTRL_REG__SP11__SHIFT                                                                    0x10
28406 #define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT                                                           0x17
28407 #define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT                                                      0x18
28408 #define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT                                                        0x1a
28409 #define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT                                                  0x1b
28410 #define CGTS_CU6_SP1_CTRL_REG__SP10_MASK                                                                      0x0000007FL
28411 #define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE_MASK                                                             0x00000080L
28412 #define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK                                                        0x00000300L
28413 #define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK                                                          0x00000400L
28414 #define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK                                                    0x00000800L
28415 #define CGTS_CU6_SP1_CTRL_REG__SP11_MASK                                                                      0x007F0000L
28416 #define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE_MASK                                                             0x00800000L
28417 #define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK                                                        0x03000000L
28418 #define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK                                                          0x04000000L
28419 #define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK                                                    0x08000000L
28420 //CGTS_CU6_TD_TCP_CTRL_REG
28421 #define CGTS_CU6_TD_TCP_CTRL_REG__TD__SHIFT                                                                   0x0
28422 #define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT                                                          0x7
28423 #define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                                     0x8
28424 #define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                                       0xa
28425 #define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
28426 #define CGTS_CU6_TD_TCP_CTRL_REG__TCPF__SHIFT                                                                 0x10
28427 #define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                        0x17
28428 #define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                                   0x18
28429 #define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                                     0x1a
28430 #define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                               0x1b
28431 #define CGTS_CU6_TD_TCP_CTRL_REG__TD_MASK                                                                     0x0000007FL
28432 #define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK                                                            0x00000080L
28433 #define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                                       0x00000300L
28434 #define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK                                                         0x00000400L
28435 #define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
28436 #define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_MASK                                                                   0x007F0000L
28437 #define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                          0x00800000L
28438 #define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                                     0x03000000L
28439 #define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                       0x04000000L
28440 #define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                                 0x08000000L
28441 //CGTS_CU7_SP0_CTRL_REG
28442 #define CGTS_CU7_SP0_CTRL_REG__SP00__SHIFT                                                                    0x0
28443 #define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT                                                           0x7
28444 #define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT                                                      0x8
28445 #define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT                                                        0xa
28446 #define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT                                                  0xb
28447 #define CGTS_CU7_SP0_CTRL_REG__SP01__SHIFT                                                                    0x10
28448 #define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT                                                           0x17
28449 #define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT                                                      0x18
28450 #define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT                                                        0x1a
28451 #define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT                                                  0x1b
28452 #define CGTS_CU7_SP0_CTRL_REG__SP00_MASK                                                                      0x0000007FL
28453 #define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE_MASK                                                             0x00000080L
28454 #define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK                                                        0x00000300L
28455 #define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK                                                          0x00000400L
28456 #define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK                                                    0x00000800L
28457 #define CGTS_CU7_SP0_CTRL_REG__SP01_MASK                                                                      0x007F0000L
28458 #define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE_MASK                                                             0x00800000L
28459 #define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK                                                        0x03000000L
28460 #define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK                                                          0x04000000L
28461 #define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK                                                    0x08000000L
28462 //CGTS_CU7_LDS_SQ_CTRL_REG
28463 #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS__SHIFT                                                                  0x0
28464 #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT                                                         0x7
28465 #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT                                                    0x8
28466 #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT                                                      0xa
28467 #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
28468 #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ__SHIFT                                                                   0x10
28469 #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT                                                          0x17
28470 #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT                                                     0x18
28471 #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT                                                       0x1a
28472 #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
28473 #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_MASK                                                                    0x0000007FL
28474 #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK                                                           0x00000080L
28475 #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK                                                      0x00000300L
28476 #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK                                                        0x00000400L
28477 #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
28478 #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_MASK                                                                     0x007F0000L
28479 #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK                                                            0x00800000L
28480 #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK                                                       0x03000000L
28481 #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK                                                         0x04000000L
28482 #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
28483 //CGTS_CU7_TA_SQC_CTRL_REG
28484 #define CGTS_CU7_TA_SQC_CTRL_REG__TA__SHIFT                                                                   0x0
28485 #define CGTS_CU7_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT                                                          0x7
28486 #define CGTS_CU7_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                                     0x8
28487 #define CGTS_CU7_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                                       0xa
28488 #define CGTS_CU7_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
28489 #define CGTS_CU7_TA_SQC_CTRL_REG__TA_MASK                                                                     0x0000007FL
28490 #define CGTS_CU7_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK                                                            0x00000080L
28491 #define CGTS_CU7_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                                       0x00000300L
28492 #define CGTS_CU7_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK                                                         0x00000400L
28493 #define CGTS_CU7_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
28494 //CGTS_CU7_SP1_CTRL_REG
28495 #define CGTS_CU7_SP1_CTRL_REG__SP10__SHIFT                                                                    0x0
28496 #define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT                                                           0x7
28497 #define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT                                                      0x8
28498 #define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT                                                        0xa
28499 #define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT                                                  0xb
28500 #define CGTS_CU7_SP1_CTRL_REG__SP11__SHIFT                                                                    0x10
28501 #define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT                                                           0x17
28502 #define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT                                                      0x18
28503 #define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT                                                        0x1a
28504 #define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT                                                  0x1b
28505 #define CGTS_CU7_SP1_CTRL_REG__SP10_MASK                                                                      0x0000007FL
28506 #define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE_MASK                                                             0x00000080L
28507 #define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK                                                        0x00000300L
28508 #define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK                                                          0x00000400L
28509 #define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK                                                    0x00000800L
28510 #define CGTS_CU7_SP1_CTRL_REG__SP11_MASK                                                                      0x007F0000L
28511 #define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE_MASK                                                             0x00800000L
28512 #define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK                                                        0x03000000L
28513 #define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK                                                          0x04000000L
28514 #define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK                                                    0x08000000L
28515 //CGTS_CU7_TD_TCP_CTRL_REG
28516 #define CGTS_CU7_TD_TCP_CTRL_REG__TD__SHIFT                                                                   0x0
28517 #define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT                                                          0x7
28518 #define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                                     0x8
28519 #define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                                       0xa
28520 #define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
28521 #define CGTS_CU7_TD_TCP_CTRL_REG__TCPF__SHIFT                                                                 0x10
28522 #define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                        0x17
28523 #define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                                   0x18
28524 #define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                                     0x1a
28525 #define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                               0x1b
28526 #define CGTS_CU7_TD_TCP_CTRL_REG__TD_MASK                                                                     0x0000007FL
28527 #define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK                                                            0x00000080L
28528 #define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                                       0x00000300L
28529 #define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK                                                         0x00000400L
28530 #define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
28531 #define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_MASK                                                                   0x007F0000L
28532 #define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                          0x00800000L
28533 #define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                                     0x03000000L
28534 #define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                       0x04000000L
28535 #define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                                 0x08000000L
28536 //CGTS_CU8_SP0_CTRL_REG
28537 #define CGTS_CU8_SP0_CTRL_REG__SP00__SHIFT                                                                    0x0
28538 #define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT                                                           0x7
28539 #define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT                                                      0x8
28540 #define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT                                                        0xa
28541 #define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT                                                  0xb
28542 #define CGTS_CU8_SP0_CTRL_REG__SP01__SHIFT                                                                    0x10
28543 #define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT                                                           0x17
28544 #define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT                                                      0x18
28545 #define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT                                                        0x1a
28546 #define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT                                                  0x1b
28547 #define CGTS_CU8_SP0_CTRL_REG__SP00_MASK                                                                      0x0000007FL
28548 #define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE_MASK                                                             0x00000080L
28549 #define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK                                                        0x00000300L
28550 #define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK                                                          0x00000400L
28551 #define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK                                                    0x00000800L
28552 #define CGTS_CU8_SP0_CTRL_REG__SP01_MASK                                                                      0x007F0000L
28553 #define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE_MASK                                                             0x00800000L
28554 #define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK                                                        0x03000000L
28555 #define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK                                                          0x04000000L
28556 #define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK                                                    0x08000000L
28557 //CGTS_CU8_LDS_SQ_CTRL_REG
28558 #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS__SHIFT                                                                  0x0
28559 #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT                                                         0x7
28560 #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT                                                    0x8
28561 #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT                                                      0xa
28562 #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
28563 #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ__SHIFT                                                                   0x10
28564 #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT                                                          0x17
28565 #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT                                                     0x18
28566 #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT                                                       0x1a
28567 #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
28568 #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_MASK                                                                    0x0000007FL
28569 #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK                                                           0x00000080L
28570 #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK                                                      0x00000300L
28571 #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK                                                        0x00000400L
28572 #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
28573 #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_MASK                                                                     0x007F0000L
28574 #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK                                                            0x00800000L
28575 #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK                                                       0x03000000L
28576 #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK                                                         0x04000000L
28577 #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
28578 //CGTS_CU8_TA_SQC_CTRL_REG
28579 #define CGTS_CU8_TA_SQC_CTRL_REG__TA__SHIFT                                                                   0x0
28580 #define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT                                                          0x7
28581 #define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                                     0x8
28582 #define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                                       0xa
28583 #define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
28584 #define CGTS_CU8_TA_SQC_CTRL_REG__SQC__SHIFT                                                                  0x10
28585 #define CGTS_CU8_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT                                                         0x17
28586 #define CGTS_CU8_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT                                                    0x18
28587 #define CGTS_CU8_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT                                                      0x1a
28588 #define CGTS_CU8_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT                                                0x1b
28589 #define CGTS_CU8_TA_SQC_CTRL_REG__TA_MASK                                                                     0x0000007FL
28590 #define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK                                                            0x00000080L
28591 #define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                                       0x00000300L
28592 #define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK                                                         0x00000400L
28593 #define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
28594 #define CGTS_CU8_TA_SQC_CTRL_REG__SQC_MASK                                                                    0x007F0000L
28595 #define CGTS_CU8_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK                                                           0x00800000L
28596 #define CGTS_CU8_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK                                                      0x03000000L
28597 #define CGTS_CU8_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK                                                        0x04000000L
28598 #define CGTS_CU8_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK                                                  0x08000000L
28599 //CGTS_CU8_SP1_CTRL_REG
28600 #define CGTS_CU8_SP1_CTRL_REG__SP10__SHIFT                                                                    0x0
28601 #define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT                                                           0x7
28602 #define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT                                                      0x8
28603 #define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT                                                        0xa
28604 #define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT                                                  0xb
28605 #define CGTS_CU8_SP1_CTRL_REG__SP11__SHIFT                                                                    0x10
28606 #define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT                                                           0x17
28607 #define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT                                                      0x18
28608 #define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT                                                        0x1a
28609 #define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT                                                  0x1b
28610 #define CGTS_CU8_SP1_CTRL_REG__SP10_MASK                                                                      0x0000007FL
28611 #define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE_MASK                                                             0x00000080L
28612 #define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK                                                        0x00000300L
28613 #define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK                                                          0x00000400L
28614 #define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK                                                    0x00000800L
28615 #define CGTS_CU8_SP1_CTRL_REG__SP11_MASK                                                                      0x007F0000L
28616 #define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE_MASK                                                             0x00800000L
28617 #define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK                                                        0x03000000L
28618 #define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK                                                          0x04000000L
28619 #define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK                                                    0x08000000L
28620 //CGTS_CU8_TD_TCP_CTRL_REG
28621 #define CGTS_CU8_TD_TCP_CTRL_REG__TD__SHIFT                                                                   0x0
28622 #define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT                                                          0x7
28623 #define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                                     0x8
28624 #define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                                       0xa
28625 #define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
28626 #define CGTS_CU8_TD_TCP_CTRL_REG__TCPF__SHIFT                                                                 0x10
28627 #define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                        0x17
28628 #define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                                   0x18
28629 #define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                                     0x1a
28630 #define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                               0x1b
28631 #define CGTS_CU8_TD_TCP_CTRL_REG__TD_MASK                                                                     0x0000007FL
28632 #define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK                                                            0x00000080L
28633 #define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                                       0x00000300L
28634 #define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK                                                         0x00000400L
28635 #define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
28636 #define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_MASK                                                                   0x007F0000L
28637 #define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                          0x00800000L
28638 #define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                                     0x03000000L
28639 #define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                       0x04000000L
28640 #define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                                 0x08000000L
28641 //CGTS_CU9_SP0_CTRL_REG
28642 #define CGTS_CU9_SP0_CTRL_REG__SP00__SHIFT                                                                    0x0
28643 #define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT                                                           0x7
28644 #define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT                                                      0x8
28645 #define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT                                                        0xa
28646 #define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT                                                  0xb
28647 #define CGTS_CU9_SP0_CTRL_REG__SP01__SHIFT                                                                    0x10
28648 #define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT                                                           0x17
28649 #define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT                                                      0x18
28650 #define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT                                                        0x1a
28651 #define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT                                                  0x1b
28652 #define CGTS_CU9_SP0_CTRL_REG__SP00_MASK                                                                      0x0000007FL
28653 #define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE_MASK                                                             0x00000080L
28654 #define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK                                                        0x00000300L
28655 #define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK                                                          0x00000400L
28656 #define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK                                                    0x00000800L
28657 #define CGTS_CU9_SP0_CTRL_REG__SP01_MASK                                                                      0x007F0000L
28658 #define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE_MASK                                                             0x00800000L
28659 #define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK                                                        0x03000000L
28660 #define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK                                                          0x04000000L
28661 #define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK                                                    0x08000000L
28662 //CGTS_CU9_LDS_SQ_CTRL_REG
28663 #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS__SHIFT                                                                  0x0
28664 #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT                                                         0x7
28665 #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT                                                    0x8
28666 #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT                                                      0xa
28667 #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
28668 #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ__SHIFT                                                                   0x10
28669 #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT                                                          0x17
28670 #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT                                                     0x18
28671 #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT                                                       0x1a
28672 #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
28673 #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_MASK                                                                    0x0000007FL
28674 #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK                                                           0x00000080L
28675 #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK                                                      0x00000300L
28676 #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK                                                        0x00000400L
28677 #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
28678 #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_MASK                                                                     0x007F0000L
28679 #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK                                                            0x00800000L
28680 #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK                                                       0x03000000L
28681 #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK                                                         0x04000000L
28682 #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
28683 //CGTS_CU9_TA_SQC_CTRL_REG
28684 #define CGTS_CU9_TA_SQC_CTRL_REG__TA__SHIFT                                                                   0x0
28685 #define CGTS_CU9_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT                                                          0x7
28686 #define CGTS_CU9_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                                     0x8
28687 #define CGTS_CU9_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                                       0xa
28688 #define CGTS_CU9_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
28689 #define CGTS_CU9_TA_SQC_CTRL_REG__TA_MASK                                                                     0x0000007FL
28690 #define CGTS_CU9_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK                                                            0x00000080L
28691 #define CGTS_CU9_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                                       0x00000300L
28692 #define CGTS_CU9_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK                                                         0x00000400L
28693 #define CGTS_CU9_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
28694 //CGTS_CU9_SP1_CTRL_REG
28695 #define CGTS_CU9_SP1_CTRL_REG__SP10__SHIFT                                                                    0x0
28696 #define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT                                                           0x7
28697 #define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT                                                      0x8
28698 #define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT                                                        0xa
28699 #define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT                                                  0xb
28700 #define CGTS_CU9_SP1_CTRL_REG__SP11__SHIFT                                                                    0x10
28701 #define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT                                                           0x17
28702 #define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT                                                      0x18
28703 #define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT                                                        0x1a
28704 #define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT                                                  0x1b
28705 #define CGTS_CU9_SP1_CTRL_REG__SP10_MASK                                                                      0x0000007FL
28706 #define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE_MASK                                                             0x00000080L
28707 #define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK                                                        0x00000300L
28708 #define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK                                                          0x00000400L
28709 #define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK                                                    0x00000800L
28710 #define CGTS_CU9_SP1_CTRL_REG__SP11_MASK                                                                      0x007F0000L
28711 #define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE_MASK                                                             0x00800000L
28712 #define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK                                                        0x03000000L
28713 #define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK                                                          0x04000000L
28714 #define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK                                                    0x08000000L
28715 //CGTS_CU9_TD_TCP_CTRL_REG
28716 #define CGTS_CU9_TD_TCP_CTRL_REG__TD__SHIFT                                                                   0x0
28717 #define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT                                                          0x7
28718 #define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                                     0x8
28719 #define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                                       0xa
28720 #define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
28721 #define CGTS_CU9_TD_TCP_CTRL_REG__TCPF__SHIFT                                                                 0x10
28722 #define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                        0x17
28723 #define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                                   0x18
28724 #define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                                     0x1a
28725 #define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                               0x1b
28726 #define CGTS_CU9_TD_TCP_CTRL_REG__TD_MASK                                                                     0x0000007FL
28727 #define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK                                                            0x00000080L
28728 #define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                                       0x00000300L
28729 #define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK                                                         0x00000400L
28730 #define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
28731 #define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_MASK                                                                   0x007F0000L
28732 #define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                          0x00800000L
28733 #define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                                     0x03000000L
28734 #define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                       0x04000000L
28735 #define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                                 0x08000000L
28736 //CGTS_CU10_SP0_CTRL_REG
28737 #define CGTS_CU10_SP0_CTRL_REG__SP00__SHIFT                                                                   0x0
28738 #define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT                                                          0x7
28739 #define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT                                                     0x8
28740 #define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT                                                       0xa
28741 #define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
28742 #define CGTS_CU10_SP0_CTRL_REG__SP01__SHIFT                                                                   0x10
28743 #define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT                                                          0x17
28744 #define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT                                                     0x18
28745 #define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT                                                       0x1a
28746 #define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
28747 #define CGTS_CU10_SP0_CTRL_REG__SP00_MASK                                                                     0x0000007FL
28748 #define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE_MASK                                                            0x00000080L
28749 #define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK                                                       0x00000300L
28750 #define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK                                                         0x00000400L
28751 #define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
28752 #define CGTS_CU10_SP0_CTRL_REG__SP01_MASK                                                                     0x007F0000L
28753 #define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE_MASK                                                            0x00800000L
28754 #define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK                                                       0x03000000L
28755 #define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK                                                         0x04000000L
28756 #define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
28757 //CGTS_CU10_LDS_SQ_CTRL_REG
28758 #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS__SHIFT                                                                 0x0
28759 #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT                                                        0x7
28760 #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT                                                   0x8
28761 #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT                                                     0xa
28762 #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT                                               0xb
28763 #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ__SHIFT                                                                  0x10
28764 #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT                                                         0x17
28765 #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT                                                    0x18
28766 #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT                                                      0x1a
28767 #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT                                                0x1b
28768 #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_MASK                                                                   0x0000007FL
28769 #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK                                                          0x00000080L
28770 #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK                                                     0x00000300L
28771 #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK                                                       0x00000400L
28772 #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK                                                 0x00000800L
28773 #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_MASK                                                                    0x007F0000L
28774 #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK                                                           0x00800000L
28775 #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK                                                      0x03000000L
28776 #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK                                                        0x04000000L
28777 #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK                                                  0x08000000L
28778 //CGTS_CU10_TA_SQC_CTRL_REG
28779 #define CGTS_CU10_TA_SQC_CTRL_REG__TA__SHIFT                                                                  0x0
28780 #define CGTS_CU10_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT                                                         0x7
28781 #define CGTS_CU10_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                                    0x8
28782 #define CGTS_CU10_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                                      0xa
28783 #define CGTS_CU10_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
28784 #define CGTS_CU10_TA_SQC_CTRL_REG__SQC__SHIFT                                                                 0x10
28785 #define CGTS_CU10_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT                                                        0x17
28786 #define CGTS_CU10_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT                                                   0x18
28787 #define CGTS_CU10_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT                                                     0x1a
28788 #define CGTS_CU10_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT                                               0x1b
28789 #define CGTS_CU10_TA_SQC_CTRL_REG__TA_MASK                                                                    0x0000007FL
28790 #define CGTS_CU10_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK                                                           0x00000080L
28791 #define CGTS_CU10_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                                      0x00000300L
28792 #define CGTS_CU10_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK                                                        0x00000400L
28793 #define CGTS_CU10_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
28794 #define CGTS_CU10_TA_SQC_CTRL_REG__SQC_MASK                                                                   0x007F0000L
28795 #define CGTS_CU10_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK                                                          0x00800000L
28796 #define CGTS_CU10_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK                                                     0x03000000L
28797 #define CGTS_CU10_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK                                                       0x04000000L
28798 #define CGTS_CU10_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK                                                 0x08000000L
28799 //CGTS_CU10_SP1_CTRL_REG
28800 #define CGTS_CU10_SP1_CTRL_REG__SP10__SHIFT                                                                   0x0
28801 #define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT                                                          0x7
28802 #define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT                                                     0x8
28803 #define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT                                                       0xa
28804 #define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
28805 #define CGTS_CU10_SP1_CTRL_REG__SP11__SHIFT                                                                   0x10
28806 #define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT                                                          0x17
28807 #define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT                                                     0x18
28808 #define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT                                                       0x1a
28809 #define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
28810 #define CGTS_CU10_SP1_CTRL_REG__SP10_MASK                                                                     0x0000007FL
28811 #define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE_MASK                                                            0x00000080L
28812 #define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK                                                       0x00000300L
28813 #define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK                                                         0x00000400L
28814 #define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
28815 #define CGTS_CU10_SP1_CTRL_REG__SP11_MASK                                                                     0x007F0000L
28816 #define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE_MASK                                                            0x00800000L
28817 #define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK                                                       0x03000000L
28818 #define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK                                                         0x04000000L
28819 #define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
28820 //CGTS_CU10_TD_TCP_CTRL_REG
28821 #define CGTS_CU10_TD_TCP_CTRL_REG__TD__SHIFT                                                                  0x0
28822 #define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT                                                         0x7
28823 #define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                                    0x8
28824 #define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                                      0xa
28825 #define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
28826 #define CGTS_CU10_TD_TCP_CTRL_REG__TCPF__SHIFT                                                                0x10
28827 #define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                       0x17
28828 #define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                                  0x18
28829 #define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                                    0x1a
28830 #define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                              0x1b
28831 #define CGTS_CU10_TD_TCP_CTRL_REG__TD_MASK                                                                    0x0000007FL
28832 #define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK                                                           0x00000080L
28833 #define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                                      0x00000300L
28834 #define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK                                                        0x00000400L
28835 #define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
28836 #define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_MASK                                                                  0x007F0000L
28837 #define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                         0x00800000L
28838 #define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                                    0x03000000L
28839 #define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                      0x04000000L
28840 #define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                                0x08000000L
28841 //CGTS_CU11_SP0_CTRL_REG
28842 #define CGTS_CU11_SP0_CTRL_REG__SP00__SHIFT                                                                   0x0
28843 #define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT                                                          0x7
28844 #define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT                                                     0x8
28845 #define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT                                                       0xa
28846 #define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
28847 #define CGTS_CU11_SP0_CTRL_REG__SP01__SHIFT                                                                   0x10
28848 #define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT                                                          0x17
28849 #define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT                                                     0x18
28850 #define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT                                                       0x1a
28851 #define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
28852 #define CGTS_CU11_SP0_CTRL_REG__SP00_MASK                                                                     0x0000007FL
28853 #define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE_MASK                                                            0x00000080L
28854 #define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK                                                       0x00000300L
28855 #define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK                                                         0x00000400L
28856 #define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
28857 #define CGTS_CU11_SP0_CTRL_REG__SP01_MASK                                                                     0x007F0000L
28858 #define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE_MASK                                                            0x00800000L
28859 #define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK                                                       0x03000000L
28860 #define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK                                                         0x04000000L
28861 #define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
28862 //CGTS_CU11_LDS_SQ_CTRL_REG
28863 #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS__SHIFT                                                                 0x0
28864 #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT                                                        0x7
28865 #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT                                                   0x8
28866 #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT                                                     0xa
28867 #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT                                               0xb
28868 #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ__SHIFT                                                                  0x10
28869 #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT                                                         0x17
28870 #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT                                                    0x18
28871 #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT                                                      0x1a
28872 #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT                                                0x1b
28873 #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_MASK                                                                   0x0000007FL
28874 #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK                                                          0x00000080L
28875 #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK                                                     0x00000300L
28876 #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK                                                       0x00000400L
28877 #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK                                                 0x00000800L
28878 #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_MASK                                                                    0x007F0000L
28879 #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK                                                           0x00800000L
28880 #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK                                                      0x03000000L
28881 #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK                                                        0x04000000L
28882 #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK                                                  0x08000000L
28883 //CGTS_CU11_TA_SQC_CTRL_REG
28884 #define CGTS_CU11_TA_SQC_CTRL_REG__TA__SHIFT                                                                  0x0
28885 #define CGTS_CU11_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT                                                         0x7
28886 #define CGTS_CU11_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                                    0x8
28887 #define CGTS_CU11_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                                      0xa
28888 #define CGTS_CU11_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
28889 #define CGTS_CU11_TA_SQC_CTRL_REG__TA_MASK                                                                    0x0000007FL
28890 #define CGTS_CU11_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK                                                           0x00000080L
28891 #define CGTS_CU11_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                                      0x00000300L
28892 #define CGTS_CU11_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK                                                        0x00000400L
28893 #define CGTS_CU11_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
28894 //CGTS_CU11_SP1_CTRL_REG
28895 #define CGTS_CU11_SP1_CTRL_REG__SP10__SHIFT                                                                   0x0
28896 #define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT                                                          0x7
28897 #define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT                                                     0x8
28898 #define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT                                                       0xa
28899 #define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
28900 #define CGTS_CU11_SP1_CTRL_REG__SP11__SHIFT                                                                   0x10
28901 #define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT                                                          0x17
28902 #define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT                                                     0x18
28903 #define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT                                                       0x1a
28904 #define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
28905 #define CGTS_CU11_SP1_CTRL_REG__SP10_MASK                                                                     0x0000007FL
28906 #define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE_MASK                                                            0x00000080L
28907 #define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK                                                       0x00000300L
28908 #define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK                                                         0x00000400L
28909 #define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
28910 #define CGTS_CU11_SP1_CTRL_REG__SP11_MASK                                                                     0x007F0000L
28911 #define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE_MASK                                                            0x00800000L
28912 #define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK                                                       0x03000000L
28913 #define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK                                                         0x04000000L
28914 #define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
28915 //CGTS_CU11_TD_TCP_CTRL_REG
28916 #define CGTS_CU11_TD_TCP_CTRL_REG__TD__SHIFT                                                                  0x0
28917 #define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT                                                         0x7
28918 #define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                                    0x8
28919 #define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                                      0xa
28920 #define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
28921 #define CGTS_CU11_TD_TCP_CTRL_REG__TCPF__SHIFT                                                                0x10
28922 #define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                       0x17
28923 #define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                                  0x18
28924 #define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                                    0x1a
28925 #define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                              0x1b
28926 #define CGTS_CU11_TD_TCP_CTRL_REG__TD_MASK                                                                    0x0000007FL
28927 #define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK                                                           0x00000080L
28928 #define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                                      0x00000300L
28929 #define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK                                                        0x00000400L
28930 #define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
28931 #define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_MASK                                                                  0x007F0000L
28932 #define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                         0x00800000L
28933 #define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                                    0x03000000L
28934 #define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                      0x04000000L
28935 #define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                                0x08000000L
28936 //CGTS_CU12_SP0_CTRL_REG
28937 #define CGTS_CU12_SP0_CTRL_REG__SP00__SHIFT                                                                   0x0
28938 #define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT                                                          0x7
28939 #define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT                                                     0x8
28940 #define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT                                                       0xa
28941 #define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
28942 #define CGTS_CU12_SP0_CTRL_REG__SP01__SHIFT                                                                   0x10
28943 #define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT                                                          0x17
28944 #define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT                                                     0x18
28945 #define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT                                                       0x1a
28946 #define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
28947 #define CGTS_CU12_SP0_CTRL_REG__SP00_MASK                                                                     0x0000007FL
28948 #define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE_MASK                                                            0x00000080L
28949 #define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK                                                       0x00000300L
28950 #define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK                                                         0x00000400L
28951 #define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
28952 #define CGTS_CU12_SP0_CTRL_REG__SP01_MASK                                                                     0x007F0000L
28953 #define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE_MASK                                                            0x00800000L
28954 #define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK                                                       0x03000000L
28955 #define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK                                                         0x04000000L
28956 #define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
28957 //CGTS_CU12_LDS_SQ_CTRL_REG
28958 #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS__SHIFT                                                                 0x0
28959 #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT                                                        0x7
28960 #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT                                                   0x8
28961 #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT                                                     0xa
28962 #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT                                               0xb
28963 #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ__SHIFT                                                                  0x10
28964 #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT                                                         0x17
28965 #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT                                                    0x18
28966 #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT                                                      0x1a
28967 #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT                                                0x1b
28968 #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_MASK                                                                   0x0000007FL
28969 #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK                                                          0x00000080L
28970 #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK                                                     0x00000300L
28971 #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK                                                       0x00000400L
28972 #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK                                                 0x00000800L
28973 #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_MASK                                                                    0x007F0000L
28974 #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK                                                           0x00800000L
28975 #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK                                                      0x03000000L
28976 #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK                                                        0x04000000L
28977 #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK                                                  0x08000000L
28978 //CGTS_CU12_TA_SQC_CTRL_REG
28979 #define CGTS_CU12_TA_SQC_CTRL_REG__TA__SHIFT                                                                  0x0
28980 #define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT                                                         0x7
28981 #define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                                    0x8
28982 #define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                                      0xa
28983 #define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
28984 #define CGTS_CU12_TA_SQC_CTRL_REG__SQC__SHIFT                                                                 0x10
28985 #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT                                                        0x17
28986 #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT                                                   0x18
28987 #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT                                                     0x1a
28988 #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT                                               0x1b
28989 #define CGTS_CU12_TA_SQC_CTRL_REG__TA_MASK                                                                    0x0000007FL
28990 #define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK                                                           0x00000080L
28991 #define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                                      0x00000300L
28992 #define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK                                                        0x00000400L
28993 #define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
28994 #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_MASK                                                                   0x007F0000L
28995 #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK                                                          0x00800000L
28996 #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK                                                     0x03000000L
28997 #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK                                                       0x04000000L
28998 #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK                                                 0x08000000L
28999 //CGTS_CU12_SP1_CTRL_REG
29000 #define CGTS_CU12_SP1_CTRL_REG__SP10__SHIFT                                                                   0x0
29001 #define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT                                                          0x7
29002 #define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT                                                     0x8
29003 #define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT                                                       0xa
29004 #define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
29005 #define CGTS_CU12_SP1_CTRL_REG__SP11__SHIFT                                                                   0x10
29006 #define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT                                                          0x17
29007 #define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT                                                     0x18
29008 #define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT                                                       0x1a
29009 #define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
29010 #define CGTS_CU12_SP1_CTRL_REG__SP10_MASK                                                                     0x0000007FL
29011 #define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE_MASK                                                            0x00000080L
29012 #define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK                                                       0x00000300L
29013 #define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK                                                         0x00000400L
29014 #define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
29015 #define CGTS_CU12_SP1_CTRL_REG__SP11_MASK                                                                     0x007F0000L
29016 #define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE_MASK                                                            0x00800000L
29017 #define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK                                                       0x03000000L
29018 #define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK                                                         0x04000000L
29019 #define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
29020 //CGTS_CU12_TD_TCP_CTRL_REG
29021 #define CGTS_CU12_TD_TCP_CTRL_REG__TD__SHIFT                                                                  0x0
29022 #define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT                                                         0x7
29023 #define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                                    0x8
29024 #define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                                      0xa
29025 #define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
29026 #define CGTS_CU12_TD_TCP_CTRL_REG__TCPF__SHIFT                                                                0x10
29027 #define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                       0x17
29028 #define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                                  0x18
29029 #define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                                    0x1a
29030 #define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                              0x1b
29031 #define CGTS_CU12_TD_TCP_CTRL_REG__TD_MASK                                                                    0x0000007FL
29032 #define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK                                                           0x00000080L
29033 #define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                                      0x00000300L
29034 #define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK                                                        0x00000400L
29035 #define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
29036 #define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_MASK                                                                  0x007F0000L
29037 #define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                         0x00800000L
29038 #define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                                    0x03000000L
29039 #define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                      0x04000000L
29040 #define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                                0x08000000L
29041 //CGTS_CU13_SP0_CTRL_REG
29042 #define CGTS_CU13_SP0_CTRL_REG__SP00__SHIFT                                                                   0x0
29043 #define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT                                                          0x7
29044 #define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT                                                     0x8
29045 #define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT                                                       0xa
29046 #define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
29047 #define CGTS_CU13_SP0_CTRL_REG__SP01__SHIFT                                                                   0x10
29048 #define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT                                                          0x17
29049 #define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT                                                     0x18
29050 #define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT                                                       0x1a
29051 #define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
29052 #define CGTS_CU13_SP0_CTRL_REG__SP00_MASK                                                                     0x0000007FL
29053 #define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE_MASK                                                            0x00000080L
29054 #define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK                                                       0x00000300L
29055 #define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK                                                         0x00000400L
29056 #define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
29057 #define CGTS_CU13_SP0_CTRL_REG__SP01_MASK                                                                     0x007F0000L
29058 #define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE_MASK                                                            0x00800000L
29059 #define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK                                                       0x03000000L
29060 #define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK                                                         0x04000000L
29061 #define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
29062 //CGTS_CU13_LDS_SQ_CTRL_REG
29063 #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS__SHIFT                                                                 0x0
29064 #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT                                                        0x7
29065 #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT                                                   0x8
29066 #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT                                                     0xa
29067 #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT                                               0xb
29068 #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ__SHIFT                                                                  0x10
29069 #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT                                                         0x17
29070 #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT                                                    0x18
29071 #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT                                                      0x1a
29072 #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT                                                0x1b
29073 #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_MASK                                                                   0x0000007FL
29074 #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK                                                          0x00000080L
29075 #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK                                                     0x00000300L
29076 #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK                                                       0x00000400L
29077 #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK                                                 0x00000800L
29078 #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_MASK                                                                    0x007F0000L
29079 #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK                                                           0x00800000L
29080 #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK                                                      0x03000000L
29081 #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK                                                        0x04000000L
29082 #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK                                                  0x08000000L
29083 //CGTS_CU13_TA_SQC_CTRL_REG
29084 #define CGTS_CU13_TA_SQC_CTRL_REG__TA__SHIFT                                                                  0x0
29085 #define CGTS_CU13_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT                                                         0x7
29086 #define CGTS_CU13_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                                    0x8
29087 #define CGTS_CU13_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                                      0xa
29088 #define CGTS_CU13_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
29089 #define CGTS_CU13_TA_SQC_CTRL_REG__TA_MASK                                                                    0x0000007FL
29090 #define CGTS_CU13_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK                                                           0x00000080L
29091 #define CGTS_CU13_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                                      0x00000300L
29092 #define CGTS_CU13_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK                                                        0x00000400L
29093 #define CGTS_CU13_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
29094 //CGTS_CU13_SP1_CTRL_REG
29095 #define CGTS_CU13_SP1_CTRL_REG__SP10__SHIFT                                                                   0x0
29096 #define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT                                                          0x7
29097 #define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT                                                     0x8
29098 #define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT                                                       0xa
29099 #define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
29100 #define CGTS_CU13_SP1_CTRL_REG__SP11__SHIFT                                                                   0x10
29101 #define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT                                                          0x17
29102 #define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT                                                     0x18
29103 #define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT                                                       0x1a
29104 #define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
29105 #define CGTS_CU13_SP1_CTRL_REG__SP10_MASK                                                                     0x0000007FL
29106 #define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE_MASK                                                            0x00000080L
29107 #define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK                                                       0x00000300L
29108 #define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK                                                         0x00000400L
29109 #define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
29110 #define CGTS_CU13_SP1_CTRL_REG__SP11_MASK                                                                     0x007F0000L
29111 #define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE_MASK                                                            0x00800000L
29112 #define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK                                                       0x03000000L
29113 #define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK                                                         0x04000000L
29114 #define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
29115 //CGTS_CU13_TD_TCP_CTRL_REG
29116 #define CGTS_CU13_TD_TCP_CTRL_REG__TD__SHIFT                                                                  0x0
29117 #define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT                                                         0x7
29118 #define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                                    0x8
29119 #define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                                      0xa
29120 #define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
29121 #define CGTS_CU13_TD_TCP_CTRL_REG__TCPF__SHIFT                                                                0x10
29122 #define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                       0x17
29123 #define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                                  0x18
29124 #define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                                    0x1a
29125 #define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                              0x1b
29126 #define CGTS_CU13_TD_TCP_CTRL_REG__TD_MASK                                                                    0x0000007FL
29127 #define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK                                                           0x00000080L
29128 #define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                                      0x00000300L
29129 #define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK                                                        0x00000400L
29130 #define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
29131 #define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_MASK                                                                  0x007F0000L
29132 #define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                         0x00800000L
29133 #define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                                    0x03000000L
29134 #define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                      0x04000000L
29135 #define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                                0x08000000L
29136 //CGTS_CU14_SP0_CTRL_REG
29137 #define CGTS_CU14_SP0_CTRL_REG__SP00__SHIFT                                                                   0x0
29138 #define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT                                                          0x7
29139 #define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT                                                     0x8
29140 #define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT                                                       0xa
29141 #define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
29142 #define CGTS_CU14_SP0_CTRL_REG__SP01__SHIFT                                                                   0x10
29143 #define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT                                                          0x17
29144 #define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT                                                     0x18
29145 #define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT                                                       0x1a
29146 #define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
29147 #define CGTS_CU14_SP0_CTRL_REG__SP00_MASK                                                                     0x0000007FL
29148 #define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE_MASK                                                            0x00000080L
29149 #define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK                                                       0x00000300L
29150 #define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK                                                         0x00000400L
29151 #define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
29152 #define CGTS_CU14_SP0_CTRL_REG__SP01_MASK                                                                     0x007F0000L
29153 #define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE_MASK                                                            0x00800000L
29154 #define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK                                                       0x03000000L
29155 #define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK                                                         0x04000000L
29156 #define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
29157 //CGTS_CU14_LDS_SQ_CTRL_REG
29158 #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS__SHIFT                                                                 0x0
29159 #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT                                                        0x7
29160 #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT                                                   0x8
29161 #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT                                                     0xa
29162 #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT                                               0xb
29163 #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ__SHIFT                                                                  0x10
29164 #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT                                                         0x17
29165 #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT                                                    0x18
29166 #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT                                                      0x1a
29167 #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT                                                0x1b
29168 #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_MASK                                                                   0x0000007FL
29169 #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK                                                          0x00000080L
29170 #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK                                                     0x00000300L
29171 #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK                                                       0x00000400L
29172 #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK                                                 0x00000800L
29173 #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_MASK                                                                    0x007F0000L
29174 #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK                                                           0x00800000L
29175 #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK                                                      0x03000000L
29176 #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK                                                        0x04000000L
29177 #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK                                                  0x08000000L
29178 //CGTS_CU14_TA_SQC_CTRL_REG
29179 #define CGTS_CU14_TA_SQC_CTRL_REG__TA__SHIFT                                                                  0x0
29180 #define CGTS_CU14_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT                                                         0x7
29181 #define CGTS_CU14_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                                    0x8
29182 #define CGTS_CU14_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                                      0xa
29183 #define CGTS_CU14_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
29184 #define CGTS_CU14_TA_SQC_CTRL_REG__SQC__SHIFT                                                                 0x10
29185 #define CGTS_CU14_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT                                                        0x17
29186 #define CGTS_CU14_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT                                                   0x18
29187 #define CGTS_CU14_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT                                                     0x1a
29188 #define CGTS_CU14_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT                                               0x1b
29189 #define CGTS_CU14_TA_SQC_CTRL_REG__TA_MASK                                                                    0x0000007FL
29190 #define CGTS_CU14_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK                                                           0x00000080L
29191 #define CGTS_CU14_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                                      0x00000300L
29192 #define CGTS_CU14_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK                                                        0x00000400L
29193 #define CGTS_CU14_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
29194 #define CGTS_CU14_TA_SQC_CTRL_REG__SQC_MASK                                                                   0x007F0000L
29195 #define CGTS_CU14_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK                                                          0x00800000L
29196 #define CGTS_CU14_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK                                                     0x03000000L
29197 #define CGTS_CU14_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK                                                       0x04000000L
29198 #define CGTS_CU14_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK                                                 0x08000000L
29199 //CGTS_CU14_SP1_CTRL_REG
29200 #define CGTS_CU14_SP1_CTRL_REG__SP10__SHIFT                                                                   0x0
29201 #define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT                                                          0x7
29202 #define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT                                                     0x8
29203 #define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT                                                       0xa
29204 #define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
29205 #define CGTS_CU14_SP1_CTRL_REG__SP11__SHIFT                                                                   0x10
29206 #define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT                                                          0x17
29207 #define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT                                                     0x18
29208 #define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT                                                       0x1a
29209 #define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
29210 #define CGTS_CU14_SP1_CTRL_REG__SP10_MASK                                                                     0x0000007FL
29211 #define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE_MASK                                                            0x00000080L
29212 #define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK                                                       0x00000300L
29213 #define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK                                                         0x00000400L
29214 #define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
29215 #define CGTS_CU14_SP1_CTRL_REG__SP11_MASK                                                                     0x007F0000L
29216 #define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE_MASK                                                            0x00800000L
29217 #define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK                                                       0x03000000L
29218 #define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK                                                         0x04000000L
29219 #define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
29220 //CGTS_CU14_TD_TCP_CTRL_REG
29221 #define CGTS_CU14_TD_TCP_CTRL_REG__TD__SHIFT                                                                  0x0
29222 #define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT                                                         0x7
29223 #define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                                    0x8
29224 #define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                                      0xa
29225 #define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
29226 #define CGTS_CU14_TD_TCP_CTRL_REG__TCPF__SHIFT                                                                0x10
29227 #define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                       0x17
29228 #define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                                  0x18
29229 #define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                                    0x1a
29230 #define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                              0x1b
29231 #define CGTS_CU14_TD_TCP_CTRL_REG__TD_MASK                                                                    0x0000007FL
29232 #define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK                                                           0x00000080L
29233 #define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                                      0x00000300L
29234 #define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK                                                        0x00000400L
29235 #define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
29236 #define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_MASK                                                                  0x007F0000L
29237 #define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                         0x00800000L
29238 #define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                                    0x03000000L
29239 #define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                      0x04000000L
29240 #define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                                0x08000000L
29241 //CGTS_CU15_SP0_CTRL_REG
29242 #define CGTS_CU15_SP0_CTRL_REG__SP00__SHIFT                                                                   0x0
29243 #define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT                                                          0x7
29244 #define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT                                                     0x8
29245 #define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT                                                       0xa
29246 #define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
29247 #define CGTS_CU15_SP0_CTRL_REG__SP01__SHIFT                                                                   0x10
29248 #define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT                                                          0x17
29249 #define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT                                                     0x18
29250 #define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT                                                       0x1a
29251 #define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
29252 #define CGTS_CU15_SP0_CTRL_REG__SP00_MASK                                                                     0x0000007FL
29253 #define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE_MASK                                                            0x00000080L
29254 #define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK                                                       0x00000300L
29255 #define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK                                                         0x00000400L
29256 #define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
29257 #define CGTS_CU15_SP0_CTRL_REG__SP01_MASK                                                                     0x007F0000L
29258 #define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE_MASK                                                            0x00800000L
29259 #define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK                                                       0x03000000L
29260 #define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK                                                         0x04000000L
29261 #define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
29262 //CGTS_CU15_LDS_SQ_CTRL_REG
29263 #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS__SHIFT                                                                 0x0
29264 #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT                                                        0x7
29265 #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT                                                   0x8
29266 #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT                                                     0xa
29267 #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT                                               0xb
29268 #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ__SHIFT                                                                  0x10
29269 #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT                                                         0x17
29270 #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT                                                    0x18
29271 #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT                                                      0x1a
29272 #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT                                                0x1b
29273 #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_MASK                                                                   0x0000007FL
29274 #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK                                                          0x00000080L
29275 #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK                                                     0x00000300L
29276 #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK                                                       0x00000400L
29277 #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK                                                 0x00000800L
29278 #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_MASK                                                                    0x007F0000L
29279 #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK                                                           0x00800000L
29280 #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK                                                      0x03000000L
29281 #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK                                                        0x04000000L
29282 #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK                                                  0x08000000L
29283 //CGTS_CU15_TA_SQC_CTRL_REG
29284 #define CGTS_CU15_TA_SQC_CTRL_REG__TA__SHIFT                                                                  0x0
29285 #define CGTS_CU15_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT                                                         0x7
29286 #define CGTS_CU15_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                                    0x8
29287 #define CGTS_CU15_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                                      0xa
29288 #define CGTS_CU15_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
29289 #define CGTS_CU15_TA_SQC_CTRL_REG__TA_MASK                                                                    0x0000007FL
29290 #define CGTS_CU15_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK                                                           0x00000080L
29291 #define CGTS_CU15_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                                      0x00000300L
29292 #define CGTS_CU15_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK                                                        0x00000400L
29293 #define CGTS_CU15_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
29294 //CGTS_CU15_SP1_CTRL_REG
29295 #define CGTS_CU15_SP1_CTRL_REG__SP10__SHIFT                                                                   0x0
29296 #define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT                                                          0x7
29297 #define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT                                                     0x8
29298 #define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT                                                       0xa
29299 #define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
29300 #define CGTS_CU15_SP1_CTRL_REG__SP11__SHIFT                                                                   0x10
29301 #define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT                                                          0x17
29302 #define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT                                                     0x18
29303 #define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT                                                       0x1a
29304 #define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
29305 #define CGTS_CU15_SP1_CTRL_REG__SP10_MASK                                                                     0x0000007FL
29306 #define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE_MASK                                                            0x00000080L
29307 #define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK                                                       0x00000300L
29308 #define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK                                                         0x00000400L
29309 #define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
29310 #define CGTS_CU15_SP1_CTRL_REG__SP11_MASK                                                                     0x007F0000L
29311 #define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE_MASK                                                            0x00800000L
29312 #define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK                                                       0x03000000L
29313 #define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK                                                         0x04000000L
29314 #define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
29315 //CGTS_CU15_TD_TCP_CTRL_REG
29316 #define CGTS_CU15_TD_TCP_CTRL_REG__TD__SHIFT                                                                  0x0
29317 #define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT                                                         0x7
29318 #define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                                    0x8
29319 #define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                                      0xa
29320 #define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
29321 #define CGTS_CU15_TD_TCP_CTRL_REG__TCPF__SHIFT                                                                0x10
29322 #define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                       0x17
29323 #define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                                  0x18
29324 #define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                                    0x1a
29325 #define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                              0x1b
29326 #define CGTS_CU15_TD_TCP_CTRL_REG__TD_MASK                                                                    0x0000007FL
29327 #define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK                                                           0x00000080L
29328 #define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                                      0x00000300L
29329 #define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK                                                        0x00000400L
29330 #define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
29331 #define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_MASK                                                                  0x007F0000L
29332 #define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                         0x00800000L
29333 #define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                                    0x03000000L
29334 #define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                      0x04000000L
29335 #define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                                0x08000000L
29336 //CGTS_CU0_TCPI_CTRL_REG
29337 #define CGTS_CU0_TCPI_CTRL_REG__TCPI__SHIFT                                                                   0x0
29338 #define CGTS_CU0_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                          0x7
29339 #define CGTS_CU0_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                                     0x8
29340 #define CGTS_CU0_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                                       0xa
29341 #define CGTS_CU0_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
29342 #define CGTS_CU0_TCPI_CTRL_REG__RESERVED__SHIFT                                                               0xc
29343 #define CGTS_CU0_TCPI_CTRL_REG__TCPI_MASK                                                                     0x0000007FL
29344 #define CGTS_CU0_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK                                                            0x00000080L
29345 #define CGTS_CU0_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                                       0x00000300L
29346 #define CGTS_CU0_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                         0x00000400L
29347 #define CGTS_CU0_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
29348 #define CGTS_CU0_TCPI_CTRL_REG__RESERVED_MASK                                                                 0xFFFFF000L
29349 //CGTS_CU1_TCPI_CTRL_REG
29350 #define CGTS_CU1_TCPI_CTRL_REG__TCPI__SHIFT                                                                   0x0
29351 #define CGTS_CU1_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                          0x7
29352 #define CGTS_CU1_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                                     0x8
29353 #define CGTS_CU1_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                                       0xa
29354 #define CGTS_CU1_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
29355 #define CGTS_CU1_TCPI_CTRL_REG__RESERVED__SHIFT                                                               0xc
29356 #define CGTS_CU1_TCPI_CTRL_REG__TCPI_MASK                                                                     0x0000007FL
29357 #define CGTS_CU1_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK                                                            0x00000080L
29358 #define CGTS_CU1_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                                       0x00000300L
29359 #define CGTS_CU1_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                         0x00000400L
29360 #define CGTS_CU1_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
29361 #define CGTS_CU1_TCPI_CTRL_REG__RESERVED_MASK                                                                 0xFFFFF000L
29362 //CGTS_CU2_TCPI_CTRL_REG
29363 #define CGTS_CU2_TCPI_CTRL_REG__TCPI__SHIFT                                                                   0x0
29364 #define CGTS_CU2_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                          0x7
29365 #define CGTS_CU2_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                                     0x8
29366 #define CGTS_CU2_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                                       0xa
29367 #define CGTS_CU2_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
29368 #define CGTS_CU2_TCPI_CTRL_REG__RESERVED__SHIFT                                                               0xc
29369 #define CGTS_CU2_TCPI_CTRL_REG__TCPI_MASK                                                                     0x0000007FL
29370 #define CGTS_CU2_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK                                                            0x00000080L
29371 #define CGTS_CU2_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                                       0x00000300L
29372 #define CGTS_CU2_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                         0x00000400L
29373 #define CGTS_CU2_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
29374 #define CGTS_CU2_TCPI_CTRL_REG__RESERVED_MASK                                                                 0xFFFFF000L
29375 //CGTS_CU3_TCPI_CTRL_REG
29376 #define CGTS_CU3_TCPI_CTRL_REG__TCPI__SHIFT                                                                   0x0
29377 #define CGTS_CU3_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                          0x7
29378 #define CGTS_CU3_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                                     0x8
29379 #define CGTS_CU3_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                                       0xa
29380 #define CGTS_CU3_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
29381 #define CGTS_CU3_TCPI_CTRL_REG__RESERVED__SHIFT                                                               0xc
29382 #define CGTS_CU3_TCPI_CTRL_REG__TCPI_MASK                                                                     0x0000007FL
29383 #define CGTS_CU3_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK                                                            0x00000080L
29384 #define CGTS_CU3_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                                       0x00000300L
29385 #define CGTS_CU3_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                         0x00000400L
29386 #define CGTS_CU3_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
29387 #define CGTS_CU3_TCPI_CTRL_REG__RESERVED_MASK                                                                 0xFFFFF000L
29388 //CGTS_CU4_TCPI_CTRL_REG
29389 #define CGTS_CU4_TCPI_CTRL_REG__TCPI__SHIFT                                                                   0x0
29390 #define CGTS_CU4_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                          0x7
29391 #define CGTS_CU4_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                                     0x8
29392 #define CGTS_CU4_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                                       0xa
29393 #define CGTS_CU4_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
29394 #define CGTS_CU4_TCPI_CTRL_REG__RESERVED__SHIFT                                                               0xc
29395 #define CGTS_CU4_TCPI_CTRL_REG__TCPI_MASK                                                                     0x0000007FL
29396 #define CGTS_CU4_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK                                                            0x00000080L
29397 #define CGTS_CU4_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                                       0x00000300L
29398 #define CGTS_CU4_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                         0x00000400L
29399 #define CGTS_CU4_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
29400 #define CGTS_CU4_TCPI_CTRL_REG__RESERVED_MASK                                                                 0xFFFFF000L
29401 //CGTS_CU5_TCPI_CTRL_REG
29402 #define CGTS_CU5_TCPI_CTRL_REG__TCPI__SHIFT                                                                   0x0
29403 #define CGTS_CU5_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                          0x7
29404 #define CGTS_CU5_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                                     0x8
29405 #define CGTS_CU5_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                                       0xa
29406 #define CGTS_CU5_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
29407 #define CGTS_CU5_TCPI_CTRL_REG__RESERVED__SHIFT                                                               0xc
29408 #define CGTS_CU5_TCPI_CTRL_REG__TCPI_MASK                                                                     0x0000007FL
29409 #define CGTS_CU5_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK                                                            0x00000080L
29410 #define CGTS_CU5_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                                       0x00000300L
29411 #define CGTS_CU5_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                         0x00000400L
29412 #define CGTS_CU5_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
29413 #define CGTS_CU5_TCPI_CTRL_REG__RESERVED_MASK                                                                 0xFFFFF000L
29414 //CGTS_CU6_TCPI_CTRL_REG
29415 #define CGTS_CU6_TCPI_CTRL_REG__TCPI__SHIFT                                                                   0x0
29416 #define CGTS_CU6_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                          0x7
29417 #define CGTS_CU6_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                                     0x8
29418 #define CGTS_CU6_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                                       0xa
29419 #define CGTS_CU6_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
29420 #define CGTS_CU6_TCPI_CTRL_REG__RESERVED__SHIFT                                                               0xc
29421 #define CGTS_CU6_TCPI_CTRL_REG__TCPI_MASK                                                                     0x0000007FL
29422 #define CGTS_CU6_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK                                                            0x00000080L
29423 #define CGTS_CU6_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                                       0x00000300L
29424 #define CGTS_CU6_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                         0x00000400L
29425 #define CGTS_CU6_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
29426 #define CGTS_CU6_TCPI_CTRL_REG__RESERVED_MASK                                                                 0xFFFFF000L
29427 //CGTS_CU7_TCPI_CTRL_REG
29428 #define CGTS_CU7_TCPI_CTRL_REG__TCPI__SHIFT                                                                   0x0
29429 #define CGTS_CU7_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                          0x7
29430 #define CGTS_CU7_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                                     0x8
29431 #define CGTS_CU7_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                                       0xa
29432 #define CGTS_CU7_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
29433 #define CGTS_CU7_TCPI_CTRL_REG__RESERVED__SHIFT                                                               0xc
29434 #define CGTS_CU7_TCPI_CTRL_REG__TCPI_MASK                                                                     0x0000007FL
29435 #define CGTS_CU7_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK                                                            0x00000080L
29436 #define CGTS_CU7_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                                       0x00000300L
29437 #define CGTS_CU7_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                         0x00000400L
29438 #define CGTS_CU7_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
29439 #define CGTS_CU7_TCPI_CTRL_REG__RESERVED_MASK                                                                 0xFFFFF000L
29440 //CGTS_CU8_TCPI_CTRL_REG
29441 #define CGTS_CU8_TCPI_CTRL_REG__TCPI__SHIFT                                                                   0x0
29442 #define CGTS_CU8_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                          0x7
29443 #define CGTS_CU8_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                                     0x8
29444 #define CGTS_CU8_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                                       0xa
29445 #define CGTS_CU8_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
29446 #define CGTS_CU8_TCPI_CTRL_REG__RESERVED__SHIFT                                                               0xc
29447 #define CGTS_CU8_TCPI_CTRL_REG__TCPI_MASK                                                                     0x0000007FL
29448 #define CGTS_CU8_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK                                                            0x00000080L
29449 #define CGTS_CU8_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                                       0x00000300L
29450 #define CGTS_CU8_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                         0x00000400L
29451 #define CGTS_CU8_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
29452 #define CGTS_CU8_TCPI_CTRL_REG__RESERVED_MASK                                                                 0xFFFFF000L
29453 //CGTS_CU9_TCPI_CTRL_REG
29454 #define CGTS_CU9_TCPI_CTRL_REG__TCPI__SHIFT                                                                   0x0
29455 #define CGTS_CU9_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                          0x7
29456 #define CGTS_CU9_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                                     0x8
29457 #define CGTS_CU9_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                                       0xa
29458 #define CGTS_CU9_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
29459 #define CGTS_CU9_TCPI_CTRL_REG__RESERVED__SHIFT                                                               0xc
29460 #define CGTS_CU9_TCPI_CTRL_REG__TCPI_MASK                                                                     0x0000007FL
29461 #define CGTS_CU9_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK                                                            0x00000080L
29462 #define CGTS_CU9_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                                       0x00000300L
29463 #define CGTS_CU9_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                         0x00000400L
29464 #define CGTS_CU9_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
29465 #define CGTS_CU9_TCPI_CTRL_REG__RESERVED_MASK                                                                 0xFFFFF000L
29466 //CGTS_CU10_TCPI_CTRL_REG
29467 #define CGTS_CU10_TCPI_CTRL_REG__TCPI__SHIFT                                                                  0x0
29468 #define CGTS_CU10_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                         0x7
29469 #define CGTS_CU10_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                                    0x8
29470 #define CGTS_CU10_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                                      0xa
29471 #define CGTS_CU10_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
29472 #define CGTS_CU10_TCPI_CTRL_REG__RESERVED__SHIFT                                                              0xc
29473 #define CGTS_CU10_TCPI_CTRL_REG__TCPI_MASK                                                                    0x0000007FL
29474 #define CGTS_CU10_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK                                                           0x00000080L
29475 #define CGTS_CU10_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                                      0x00000300L
29476 #define CGTS_CU10_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                        0x00000400L
29477 #define CGTS_CU10_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
29478 #define CGTS_CU10_TCPI_CTRL_REG__RESERVED_MASK                                                                0xFFFFF000L
29479 //CGTS_CU11_TCPI_CTRL_REG
29480 #define CGTS_CU11_TCPI_CTRL_REG__TCPI__SHIFT                                                                  0x0
29481 #define CGTS_CU11_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                         0x7
29482 #define CGTS_CU11_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                                    0x8
29483 #define CGTS_CU11_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                                      0xa
29484 #define CGTS_CU11_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
29485 #define CGTS_CU11_TCPI_CTRL_REG__RESERVED__SHIFT                                                              0xc
29486 #define CGTS_CU11_TCPI_CTRL_REG__TCPI_MASK                                                                    0x0000007FL
29487 #define CGTS_CU11_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK                                                           0x00000080L
29488 #define CGTS_CU11_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                                      0x00000300L
29489 #define CGTS_CU11_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                        0x00000400L
29490 #define CGTS_CU11_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
29491 #define CGTS_CU11_TCPI_CTRL_REG__RESERVED_MASK                                                                0xFFFFF000L
29492 //CGTS_CU12_TCPI_CTRL_REG
29493 #define CGTS_CU12_TCPI_CTRL_REG__TCPI__SHIFT                                                                  0x0
29494 #define CGTS_CU12_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                         0x7
29495 #define CGTS_CU12_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                                    0x8
29496 #define CGTS_CU12_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                                      0xa
29497 #define CGTS_CU12_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
29498 #define CGTS_CU12_TCPI_CTRL_REG__RESERVED__SHIFT                                                              0xc
29499 #define CGTS_CU12_TCPI_CTRL_REG__TCPI_MASK                                                                    0x0000007FL
29500 #define CGTS_CU12_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK                                                           0x00000080L
29501 #define CGTS_CU12_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                                      0x00000300L
29502 #define CGTS_CU12_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                        0x00000400L
29503 #define CGTS_CU12_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
29504 #define CGTS_CU12_TCPI_CTRL_REG__RESERVED_MASK                                                                0xFFFFF000L
29505 //CGTS_CU13_TCPI_CTRL_REG
29506 #define CGTS_CU13_TCPI_CTRL_REG__TCPI__SHIFT                                                                  0x0
29507 #define CGTS_CU13_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                         0x7
29508 #define CGTS_CU13_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                                    0x8
29509 #define CGTS_CU13_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                                      0xa
29510 #define CGTS_CU13_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
29511 #define CGTS_CU13_TCPI_CTRL_REG__RESERVED__SHIFT                                                              0xc
29512 #define CGTS_CU13_TCPI_CTRL_REG__TCPI_MASK                                                                    0x0000007FL
29513 #define CGTS_CU13_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK                                                           0x00000080L
29514 #define CGTS_CU13_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                                      0x00000300L
29515 #define CGTS_CU13_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                        0x00000400L
29516 #define CGTS_CU13_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
29517 #define CGTS_CU13_TCPI_CTRL_REG__RESERVED_MASK                                                                0xFFFFF000L
29518 //CGTS_CU14_TCPI_CTRL_REG
29519 #define CGTS_CU14_TCPI_CTRL_REG__TCPI__SHIFT                                                                  0x0
29520 #define CGTS_CU14_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                         0x7
29521 #define CGTS_CU14_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                                    0x8
29522 #define CGTS_CU14_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                                      0xa
29523 #define CGTS_CU14_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
29524 #define CGTS_CU14_TCPI_CTRL_REG__RESERVED__SHIFT                                                              0xc
29525 #define CGTS_CU14_TCPI_CTRL_REG__TCPI_MASK                                                                    0x0000007FL
29526 #define CGTS_CU14_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK                                                           0x00000080L
29527 #define CGTS_CU14_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                                      0x00000300L
29528 #define CGTS_CU14_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                        0x00000400L
29529 #define CGTS_CU14_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
29530 #define CGTS_CU14_TCPI_CTRL_REG__RESERVED_MASK                                                                0xFFFFF000L
29531 //CGTS_CU15_TCPI_CTRL_REG
29532 #define CGTS_CU15_TCPI_CTRL_REG__TCPI__SHIFT                                                                  0x0
29533 #define CGTS_CU15_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                         0x7
29534 #define CGTS_CU15_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                                    0x8
29535 #define CGTS_CU15_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                                      0xa
29536 #define CGTS_CU15_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
29537 #define CGTS_CU15_TCPI_CTRL_REG__RESERVED__SHIFT                                                              0xc
29538 #define CGTS_CU15_TCPI_CTRL_REG__TCPI_MASK                                                                    0x0000007FL
29539 #define CGTS_CU15_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK                                                           0x00000080L
29540 #define CGTS_CU15_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                                      0x00000300L
29541 #define CGTS_CU15_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                        0x00000400L
29542 #define CGTS_CU15_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
29543 #define CGTS_CU15_TCPI_CTRL_REG__RESERVED_MASK                                                                0xFFFFF000L
29544 //CGTT_SPI_PS_CLK_CTRL
29545 #define CGTT_SPI_PS_CLK_CTRL__ON_DELAY__SHIFT                                                                 0x0
29546 #define CGTT_SPI_PS_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                           0x4
29547 #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                     0x10
29548 #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                     0x11
29549 #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                     0x12
29550 #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                     0x13
29551 #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                     0x14
29552 #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                     0x15
29553 #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                     0x16
29554 #define CGTT_SPI_PS_CLK_CTRL__GRP6_OVERRIDE__SHIFT                                                            0x18
29555 #define CGTT_SPI_PS_CLK_CTRL__GRP5_OVERRIDE__SHIFT                                                            0x19
29556 #define CGTT_SPI_PS_CLK_CTRL__GRP4_OVERRIDE__SHIFT                                                            0x1a
29557 #define CGTT_SPI_PS_CLK_CTRL__GRP3_OVERRIDE__SHIFT                                                            0x1b
29558 #define CGTT_SPI_PS_CLK_CTRL__GRP2_OVERRIDE__SHIFT                                                            0x1c
29559 #define CGTT_SPI_PS_CLK_CTRL__GRP1_OVERRIDE__SHIFT                                                            0x1d
29560 #define CGTT_SPI_PS_CLK_CTRL__GRP0_OVERRIDE__SHIFT                                                            0x1e
29561 #define CGTT_SPI_PS_CLK_CTRL__REG_OVERRIDE__SHIFT                                                             0x1f
29562 #define CGTT_SPI_PS_CLK_CTRL__ON_DELAY_MASK                                                                   0x0000000FL
29563 #define CGTT_SPI_PS_CLK_CTRL__OFF_HYSTERESIS_MASK                                                             0x00000FF0L
29564 #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                       0x00010000L
29565 #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                       0x00020000L
29566 #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                       0x00040000L
29567 #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                       0x00080000L
29568 #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                       0x00100000L
29569 #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                       0x00200000L
29570 #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                       0x00400000L
29571 #define CGTT_SPI_PS_CLK_CTRL__GRP6_OVERRIDE_MASK                                                              0x01000000L
29572 #define CGTT_SPI_PS_CLK_CTRL__GRP5_OVERRIDE_MASK                                                              0x02000000L
29573 #define CGTT_SPI_PS_CLK_CTRL__GRP4_OVERRIDE_MASK                                                              0x04000000L
29574 #define CGTT_SPI_PS_CLK_CTRL__GRP3_OVERRIDE_MASK                                                              0x08000000L
29575 #define CGTT_SPI_PS_CLK_CTRL__GRP2_OVERRIDE_MASK                                                              0x10000000L
29576 #define CGTT_SPI_PS_CLK_CTRL__GRP1_OVERRIDE_MASK                                                              0x20000000L
29577 #define CGTT_SPI_PS_CLK_CTRL__GRP0_OVERRIDE_MASK                                                              0x40000000L
29578 #define CGTT_SPI_PS_CLK_CTRL__REG_OVERRIDE_MASK                                                               0x80000000L
29579 //CGTT_SPIS_CLK_CTRL
29580 #define CGTT_SPIS_CLK_CTRL__ON_DELAY__SHIFT                                                                   0x0
29581 #define CGTT_SPIS_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                             0x4
29582 #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                       0x10
29583 #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                       0x11
29584 #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                       0x12
29585 #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                       0x13
29586 #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                       0x14
29587 #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                       0x15
29588 #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                       0x16
29589 #define CGTT_SPIS_CLK_CTRL__GRP6_OVERRIDE__SHIFT                                                              0x18
29590 #define CGTT_SPIS_CLK_CTRL__GRP5_OVERRIDE__SHIFT                                                              0x19
29591 #define CGTT_SPIS_CLK_CTRL__GRP4_OVERRIDE__SHIFT                                                              0x1a
29592 #define CGTT_SPIS_CLK_CTRL__GRP3_OVERRIDE__SHIFT                                                              0x1b
29593 #define CGTT_SPIS_CLK_CTRL__GRP2_OVERRIDE__SHIFT                                                              0x1c
29594 #define CGTT_SPIS_CLK_CTRL__GRP1_OVERRIDE__SHIFT                                                              0x1d
29595 #define CGTT_SPIS_CLK_CTRL__GRP0_OVERRIDE__SHIFT                                                              0x1e
29596 #define CGTT_SPIS_CLK_CTRL__REG_OVERRIDE__SHIFT                                                               0x1f
29597 #define CGTT_SPIS_CLK_CTRL__ON_DELAY_MASK                                                                     0x0000000FL
29598 #define CGTT_SPIS_CLK_CTRL__OFF_HYSTERESIS_MASK                                                               0x00000FF0L
29599 #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                         0x00010000L
29600 #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                         0x00020000L
29601 #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                         0x00040000L
29602 #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                         0x00080000L
29603 #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                         0x00100000L
29604 #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                         0x00200000L
29605 #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                         0x00400000L
29606 #define CGTT_SPIS_CLK_CTRL__GRP6_OVERRIDE_MASK                                                                0x01000000L
29607 #define CGTT_SPIS_CLK_CTRL__GRP5_OVERRIDE_MASK                                                                0x02000000L
29608 #define CGTT_SPIS_CLK_CTRL__GRP4_OVERRIDE_MASK                                                                0x04000000L
29609 #define CGTT_SPIS_CLK_CTRL__GRP3_OVERRIDE_MASK                                                                0x08000000L
29610 #define CGTT_SPIS_CLK_CTRL__GRP2_OVERRIDE_MASK                                                                0x10000000L
29611 #define CGTT_SPIS_CLK_CTRL__GRP1_OVERRIDE_MASK                                                                0x20000000L
29612 #define CGTT_SPIS_CLK_CTRL__GRP0_OVERRIDE_MASK                                                                0x40000000L
29613 #define CGTT_SPIS_CLK_CTRL__REG_OVERRIDE_MASK                                                                 0x80000000L
29614 //CGTX_SPI_DEBUG_CLK_CTRL
29615 #define CGTX_SPI_DEBUG_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT                                                      0x0
29616 #define CGTX_SPI_DEBUG_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT                                                      0x6
29617 #define CGTX_SPI_DEBUG_CLK_CTRL__ALL_CLK_ON_OVERRIDE__SHIFT                                                   0x7
29618 #define CGTX_SPI_DEBUG_CLK_CTRL__SPI_SH_CLK_CONTROL__SHIFT                                                    0x8
29619 #define CGTX_SPI_DEBUG_CLK_CTRL__SPI_REPEATER_FGCG_OVERRIDE__SHIFT                                            0x9
29620 #define CGTX_SPI_DEBUG_CLK_CTRL__GRP5_CG_OFF_HYST_MASK                                                        0x0000003FL
29621 #define CGTX_SPI_DEBUG_CLK_CTRL__GRP5_CG_OVERRIDE_MASK                                                        0x00000040L
29622 #define CGTX_SPI_DEBUG_CLK_CTRL__ALL_CLK_ON_OVERRIDE_MASK                                                     0x00000080L
29623 #define CGTX_SPI_DEBUG_CLK_CTRL__SPI_SH_CLK_CONTROL_MASK                                                      0x00000100L
29624 #define CGTX_SPI_DEBUG_CLK_CTRL__SPI_REPEATER_FGCG_OVERRIDE_MASK                                              0x00000200L
29625 //CGTT_SPI_CLK_CTRL
29626 #define CGTT_SPI_CLK_CTRL__ON_DELAY__SHIFT                                                                    0x0
29627 #define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                              0x4
29628 #define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                        0x14
29629 #define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                        0x15
29630 #define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                        0x16
29631 #define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE__SHIFT                                                               0x1c
29632 #define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE__SHIFT                                                               0x1d
29633 #define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE__SHIFT                                                               0x1e
29634 #define CGTT_SPI_CLK_CTRL__REG_OVERRIDE__SHIFT                                                                0x1f
29635 #define CGTT_SPI_CLK_CTRL__ON_DELAY_MASK                                                                      0x0000000FL
29636 #define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
29637 #define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                          0x00100000L
29638 #define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                          0x00200000L
29639 #define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                          0x00400000L
29640 #define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE_MASK                                                                 0x10000000L
29641 #define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE_MASK                                                                 0x20000000L
29642 #define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE_MASK                                                                 0x40000000L
29643 #define CGTT_SPI_CLK_CTRL__REG_OVERRIDE_MASK                                                                  0x80000000L
29644 //CGTT_PC_CLK_CTRL
29645 #define CGTT_PC_CLK_CTRL__ON_DELAY__SHIFT                                                                     0x0
29646 #define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                               0x4
29647 #define CGTT_PC_CLK_CTRL__PC_RAM_FGCG_OVERRIDE__SHIFT                                                         0x11
29648 #define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT                                                             0x12
29649 #define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT                                                             0x18
29650 #define CGTT_PC_CLK_CTRL__PC_WRITE_CLK_EN_OVERRIDE__SHIFT                                                     0x19
29651 #define CGTT_PC_CLK_CTRL__PC_READ_CLK_EN_OVERRIDE__SHIFT                                                      0x1a
29652 #define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE__SHIFT                                                               0x1b
29653 #define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE__SHIFT                                                               0x1c
29654 #define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE__SHIFT                                                               0x1d
29655 #define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE__SHIFT                                                               0x1e
29656 #define CGTT_PC_CLK_CTRL__REG_OVERRIDE__SHIFT                                                                 0x1f
29657 #define CGTT_PC_CLK_CTRL__ON_DELAY_MASK                                                                       0x0000000FL
29658 #define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                 0x00000FF0L
29659 #define CGTT_PC_CLK_CTRL__PC_RAM_FGCG_OVERRIDE_MASK                                                           0x00020000L
29660 #define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST_MASK                                                               0x00FC0000L
29661 #define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE_MASK                                                               0x01000000L
29662 #define CGTT_PC_CLK_CTRL__PC_WRITE_CLK_EN_OVERRIDE_MASK                                                       0x02000000L
29663 #define CGTT_PC_CLK_CTRL__PC_READ_CLK_EN_OVERRIDE_MASK                                                        0x04000000L
29664 #define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE_MASK                                                                 0x08000000L
29665 #define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE_MASK                                                                 0x10000000L
29666 #define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE_MASK                                                                 0x20000000L
29667 #define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE_MASK                                                                 0x40000000L
29668 #define CGTT_PC_CLK_CTRL__REG_OVERRIDE_MASK                                                                   0x80000000L
29669 //CGTT_BCI_CLK_CTRL
29670 #define CGTT_BCI_CLK_CTRL__ON_DELAY__SHIFT                                                                    0x0
29671 #define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                              0x4
29672 #define CGTT_BCI_CLK_CTRL__RESERVED__SHIFT                                                                    0xc
29673 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                        0x10
29674 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                        0x11
29675 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                        0x12
29676 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                        0x13
29677 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                        0x14
29678 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                        0x15
29679 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                        0x16
29680 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                        0x17
29681 #define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE__SHIFT                                                              0x18
29682 #define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE__SHIFT                                                              0x19
29683 #define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE__SHIFT                                                              0x1a
29684 #define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE__SHIFT                                                              0x1b
29685 #define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE__SHIFT                                                              0x1c
29686 #define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE__SHIFT                                                              0x1d
29687 #define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE__SHIFT                                                              0x1e
29688 #define CGTT_BCI_CLK_CTRL__REG_OVERRIDE__SHIFT                                                                0x1f
29689 #define CGTT_BCI_CLK_CTRL__ON_DELAY_MASK                                                                      0x0000000FL
29690 #define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
29691 #define CGTT_BCI_CLK_CTRL__RESERVED_MASK                                                                      0x0000F000L
29692 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                          0x00010000L
29693 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                          0x00020000L
29694 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                          0x00040000L
29695 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                          0x00080000L
29696 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                          0x00100000L
29697 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                          0x00200000L
29698 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                          0x00400000L
29699 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                          0x00800000L
29700 #define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE_MASK                                                                0x01000000L
29701 #define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE_MASK                                                                0x02000000L
29702 #define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE_MASK                                                                0x04000000L
29703 #define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE_MASK                                                                0x08000000L
29704 #define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE_MASK                                                                0x10000000L
29705 #define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE_MASK                                                                0x20000000L
29706 #define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE_MASK                                                                0x40000000L
29707 #define CGTT_BCI_CLK_CTRL__REG_OVERRIDE_MASK                                                                  0x80000000L
29708 //CGTT_VGT_CLK_CTRL
29709 #define CGTT_VGT_CLK_CTRL__ON_DELAY__SHIFT                                                                    0x0
29710 #define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                              0x4
29711 #define CGTT_VGT_CLK_CTRL__PERF_ENABLE__SHIFT                                                                 0xf
29712 #define CGTT_VGT_CLK_CTRL__DBG_ENABLE__SHIFT                                                                  0x10
29713 #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                        0x11
29714 #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                        0x12
29715 #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                        0x13
29716 #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                        0x14
29717 #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                        0x15
29718 #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                        0x16
29719 #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                        0x17
29720 #define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE9__SHIFT                                                              0x18
29721 #define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE8__SHIFT                                                              0x19
29722 #define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7__SHIFT                                                              0x1a
29723 #define CGTT_VGT_CLK_CTRL__PRIMGEN_OVERRIDE__SHIFT                                                            0x1b
29724 #define CGTT_VGT_CLK_CTRL__TESS_OVERRIDE__SHIFT                                                               0x1c
29725 #define CGTT_VGT_CLK_CTRL__GS_OVERRIDE__SHIFT                                                                 0x1d
29726 #define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE__SHIFT                                                               0x1e
29727 #define CGTT_VGT_CLK_CTRL__REG_OVERRIDE__SHIFT                                                                0x1f
29728 #define CGTT_VGT_CLK_CTRL__ON_DELAY_MASK                                                                      0x0000000FL
29729 #define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
29730 #define CGTT_VGT_CLK_CTRL__PERF_ENABLE_MASK                                                                   0x00008000L
29731 #define CGTT_VGT_CLK_CTRL__DBG_ENABLE_MASK                                                                    0x00010000L
29732 #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                          0x00020000L
29733 #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                          0x00040000L
29734 #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                          0x00080000L
29735 #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                          0x00100000L
29736 #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                          0x00200000L
29737 #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                          0x00400000L
29738 #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                          0x00800000L
29739 #define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE9_MASK                                                                0x01000000L
29740 #define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE8_MASK                                                                0x02000000L
29741 #define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7_MASK                                                                0x04000000L
29742 #define CGTT_VGT_CLK_CTRL__PRIMGEN_OVERRIDE_MASK                                                              0x08000000L
29743 #define CGTT_VGT_CLK_CTRL__TESS_OVERRIDE_MASK                                                                 0x10000000L
29744 #define CGTT_VGT_CLK_CTRL__GS_OVERRIDE_MASK                                                                   0x20000000L
29745 #define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE_MASK                                                                 0x40000000L
29746 #define CGTT_VGT_CLK_CTRL__REG_OVERRIDE_MASK                                                                  0x80000000L
29747 //CGTT_IA_CLK_CTRL
29748 #define CGTT_IA_CLK_CTRL__ON_DELAY__SHIFT                                                                     0x0
29749 #define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                               0x4
29750 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                         0x10
29751 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                         0x11
29752 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                         0x12
29753 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                         0x13
29754 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                         0x14
29755 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                         0x15
29756 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                         0x16
29757 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                         0x17
29758 #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT                                                               0x18
29759 #define CGTT_IA_CLK_CTRL__PERF_ENABLE__SHIFT                                                                  0x19
29760 #define CGTT_IA_CLK_CTRL__DBG_ENABLE__SHIFT                                                                   0x1a
29761 #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                               0x1b
29762 #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                               0x1c
29763 #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2__SHIFT                                                               0x1d
29764 #define CGTT_IA_CLK_CTRL__CORE_OVERRIDE__SHIFT                                                                0x1e
29765 #define CGTT_IA_CLK_CTRL__REG_OVERRIDE__SHIFT                                                                 0x1f
29766 #define CGTT_IA_CLK_CTRL__ON_DELAY_MASK                                                                       0x0000000FL
29767 #define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                 0x00000FF0L
29768 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                           0x00010000L
29769 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                           0x00020000L
29770 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                           0x00040000L
29771 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                           0x00080000L
29772 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                           0x00100000L
29773 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                           0x00200000L
29774 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                           0x00400000L
29775 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                           0x00800000L
29776 #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7_MASK                                                                 0x01000000L
29777 #define CGTT_IA_CLK_CTRL__PERF_ENABLE_MASK                                                                    0x02000000L
29778 #define CGTT_IA_CLK_CTRL__DBG_ENABLE_MASK                                                                     0x04000000L
29779 #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4_MASK                                                                 0x08000000L
29780 #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3_MASK                                                                 0x10000000L
29781 #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2_MASK                                                                 0x20000000L
29782 #define CGTT_IA_CLK_CTRL__CORE_OVERRIDE_MASK                                                                  0x40000000L
29783 #define CGTT_IA_CLK_CTRL__REG_OVERRIDE_MASK                                                                   0x80000000L
29784 //CGTT_WD_CLK_CTRL
29785 #define CGTT_WD_CLK_CTRL__ON_DELAY__SHIFT                                                                     0x0
29786 #define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                               0x4
29787 #define CGTT_WD_CLK_CTRL__PERF_ENABLE__SHIFT                                                                  0xf
29788 #define CGTT_WD_CLK_CTRL__DBG_ENABLE__SHIFT                                                                   0x10
29789 #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                         0x11
29790 #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                         0x12
29791 #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                         0x13
29792 #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                         0x14
29793 #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                         0x15
29794 #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                         0x16
29795 #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                         0x17
29796 #define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE8__SHIFT                                                               0x19
29797 #define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7__SHIFT                                                               0x1a
29798 #define CGTT_WD_CLK_CTRL__PRIMGEN_OVERRIDE__SHIFT                                                             0x1b
29799 #define CGTT_WD_CLK_CTRL__TESS_OVERRIDE__SHIFT                                                                0x1c
29800 #define CGTT_WD_CLK_CTRL__CORE_OVERRIDE__SHIFT                                                                0x1d
29801 #define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE__SHIFT                                                          0x1e
29802 #define CGTT_WD_CLK_CTRL__REG_OVERRIDE__SHIFT                                                                 0x1f
29803 #define CGTT_WD_CLK_CTRL__ON_DELAY_MASK                                                                       0x0000000FL
29804 #define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                 0x00000FF0L
29805 #define CGTT_WD_CLK_CTRL__PERF_ENABLE_MASK                                                                    0x00008000L
29806 #define CGTT_WD_CLK_CTRL__DBG_ENABLE_MASK                                                                     0x00010000L
29807 #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                           0x00020000L
29808 #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                           0x00040000L
29809 #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                           0x00080000L
29810 #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                           0x00100000L
29811 #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                           0x00200000L
29812 #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                           0x00400000L
29813 #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                           0x00800000L
29814 #define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE8_MASK                                                                 0x02000000L
29815 #define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7_MASK                                                                 0x04000000L
29816 #define CGTT_WD_CLK_CTRL__PRIMGEN_OVERRIDE_MASK                                                               0x08000000L
29817 #define CGTT_WD_CLK_CTRL__TESS_OVERRIDE_MASK                                                                  0x10000000L
29818 #define CGTT_WD_CLK_CTRL__CORE_OVERRIDE_MASK                                                                  0x20000000L
29819 #define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE_MASK                                                            0x40000000L
29820 #define CGTT_WD_CLK_CTRL__REG_OVERRIDE_MASK                                                                   0x80000000L
29821 //CGTT_PA_CLK_CTRL
29822 #define CGTT_PA_CLK_CTRL__ON_DELAY__SHIFT                                                                     0x0
29823 #define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                               0x4
29824 #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                         0x10
29825 #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                         0x11
29826 #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                         0x12
29827 #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                         0x13
29828 #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                         0x14
29829 #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                         0x15
29830 #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                         0x16
29831 #define CGTT_PA_CLK_CTRL__DEBUG_BUS_EN__SHIFT                                                                 0x17
29832 #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT                                                               0x18
29833 #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT                                                               0x19
29834 #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT                                                               0x1a
29835 #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                               0x1b
29836 #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                               0x1c
29837 #define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE__SHIFT                                                              0x1d
29838 #define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE__SHIFT                                                              0x1e
29839 #define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE__SHIFT                                                             0x1f
29840 #define CGTT_PA_CLK_CTRL__ON_DELAY_MASK                                                                       0x0000000FL
29841 #define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                 0x00000FF0L
29842 #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                           0x00010000L
29843 #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                           0x00020000L
29844 #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                           0x00040000L
29845 #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                           0x00080000L
29846 #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                           0x00100000L
29847 #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                           0x00200000L
29848 #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                           0x00400000L
29849 #define CGTT_PA_CLK_CTRL__DEBUG_BUS_EN_MASK                                                                   0x00800000L
29850 #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7_MASK                                                                 0x01000000L
29851 #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6_MASK                                                                 0x02000000L
29852 #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5_MASK                                                                 0x04000000L
29853 #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4_MASK                                                                 0x08000000L
29854 #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3_MASK                                                                 0x10000000L
29855 #define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE_MASK                                                                0x20000000L
29856 #define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE_MASK                                                                0x40000000L
29857 #define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE_MASK                                                               0x80000000L
29858 //CGTT_SC_CLK_CTRL0
29859 #define CGTT_SC_CLK_CTRL0__ON_DELAY__SHIFT                                                                    0x0
29860 #define CGTT_SC_CLK_CTRL0__OFF_HYSTERESIS__SHIFT                                                              0x4
29861 #define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_STALL_OVERRIDE__SHIFT                                              0x10
29862 #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE5__SHIFT                                                        0x11
29863 #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE4__SHIFT                                                        0x12
29864 #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE3__SHIFT                                                        0x13
29865 #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE2__SHIFT                                                        0x14
29866 #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE1__SHIFT                                                        0x15
29867 #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE0__SHIFT                                                        0x16
29868 #define CGTT_SC_CLK_CTRL0__REG_CLK_STALL_OVERRIDE__SHIFT                                                      0x17
29869 #define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_OVERRIDE__SHIFT                                                    0x18
29870 #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT                                                              0x19
29871 #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT                                                              0x1a
29872 #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT                                                              0x1b
29873 #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT                                                              0x1c
29874 #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT                                                              0x1d
29875 #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT                                                              0x1e
29876 #define CGTT_SC_CLK_CTRL0__REG_CLK_OVERRIDE__SHIFT                                                            0x1f
29877 #define CGTT_SC_CLK_CTRL0__ON_DELAY_MASK                                                                      0x0000000FL
29878 #define CGTT_SC_CLK_CTRL0__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
29879 #define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_STALL_OVERRIDE_MASK                                                0x00010000L
29880 #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE5_MASK                                                          0x00020000L
29881 #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE4_MASK                                                          0x00040000L
29882 #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE3_MASK                                                          0x00080000L
29883 #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE2_MASK                                                          0x00100000L
29884 #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE1_MASK                                                          0x00200000L
29885 #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE0_MASK                                                          0x00400000L
29886 #define CGTT_SC_CLK_CTRL0__REG_CLK_STALL_OVERRIDE_MASK                                                        0x00800000L
29887 #define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_OVERRIDE_MASK                                                      0x01000000L
29888 #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE5_MASK                                                                0x02000000L
29889 #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE4_MASK                                                                0x04000000L
29890 #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE3_MASK                                                                0x08000000L
29891 #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE2_MASK                                                                0x10000000L
29892 #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE1_MASK                                                                0x20000000L
29893 #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE0_MASK                                                                0x40000000L
29894 #define CGTT_SC_CLK_CTRL0__REG_CLK_OVERRIDE_MASK                                                              0x80000000L
29895 //CGTT_SC_CLK_CTRL1
29896 #define CGTT_SC_CLK_CTRL1__ON_DELAY__SHIFT                                                                    0x0
29897 #define CGTT_SC_CLK_CTRL1__OFF_HYSTERESIS__SHIFT                                                              0x4
29898 #define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE__SHIFT                                              0x11
29899 #define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_STALL_OVERRIDE__SHIFT                                              0x12
29900 #define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_STALL_OVERRIDE__SHIFT                                     0x13
29901 #define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_STALL_OVERRIDE__SHIFT                                           0x14
29902 #define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_STALL_OVERRIDE__SHIFT                                            0x15
29903 #define CGTT_SC_CLK_CTRL1__PBB_CLK_STALL_OVERRIDE__SHIFT                                                      0x16
29904 #define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE__SHIFT                                                    0x19
29905 #define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_OVERRIDE__SHIFT                                                    0x1a
29906 #define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_OVERRIDE__SHIFT                                           0x1b
29907 #define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_OVERRIDE__SHIFT                                                 0x1c
29908 #define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_OVERRIDE__SHIFT                                                  0x1d
29909 #define CGTT_SC_CLK_CTRL1__PBB_CLK_OVERRIDE__SHIFT                                                            0x1e
29910 #define CGTT_SC_CLK_CTRL1__ON_DELAY_MASK                                                                      0x0000000FL
29911 #define CGTT_SC_CLK_CTRL1__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
29912 #define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE_MASK                                                0x00020000L
29913 #define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_STALL_OVERRIDE_MASK                                                0x00040000L
29914 #define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_STALL_OVERRIDE_MASK                                       0x00080000L
29915 #define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_STALL_OVERRIDE_MASK                                             0x00100000L
29916 #define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_STALL_OVERRIDE_MASK                                              0x00200000L
29917 #define CGTT_SC_CLK_CTRL1__PBB_CLK_STALL_OVERRIDE_MASK                                                        0x00400000L
29918 #define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE_MASK                                                      0x02000000L
29919 #define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_OVERRIDE_MASK                                                      0x04000000L
29920 #define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_OVERRIDE_MASK                                             0x08000000L
29921 #define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_OVERRIDE_MASK                                                   0x10000000L
29922 #define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_OVERRIDE_MASK                                                    0x20000000L
29923 #define CGTT_SC_CLK_CTRL1__PBB_CLK_OVERRIDE_MASK                                                              0x40000000L
29924 //CGTT_SC_CLK_CTRL2
29925 #define CGTT_SC_CLK_CTRL2__ON_DELAY__SHIFT                                                                    0x0
29926 #define CGTT_SC_CLK_CTRL2__OFF_HYSTERESIS__SHIFT                                                              0x4
29927 #define CGTT_SC_CLK_CTRL2__SCF_SCB_INTF_CLK_OVERRIDE__SHIFT                                                   0x1b
29928 #define CGTT_SC_CLK_CTRL2__SC_PKR_INTF_CLK_OVERRIDE__SHIFT                                                    0x1c
29929 #define CGTT_SC_CLK_CTRL2__SC_DB_INTF_CLK_OVERRIDE__SHIFT                                                     0x1d
29930 #define CGTT_SC_CLK_CTRL2__PA_SC_INTF_CLK_OVERRIDE__SHIFT                                                     0x1e
29931 #define CGTT_SC_CLK_CTRL2__ON_DELAY_MASK                                                                      0x0000000FL
29932 #define CGTT_SC_CLK_CTRL2__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
29933 #define CGTT_SC_CLK_CTRL2__SCF_SCB_INTF_CLK_OVERRIDE_MASK                                                     0x08000000L
29934 #define CGTT_SC_CLK_CTRL2__SC_PKR_INTF_CLK_OVERRIDE_MASK                                                      0x10000000L
29935 #define CGTT_SC_CLK_CTRL2__SC_DB_INTF_CLK_OVERRIDE_MASK                                                       0x20000000L
29936 #define CGTT_SC_CLK_CTRL2__PA_SC_INTF_CLK_OVERRIDE_MASK                                                       0x40000000L
29937 //CGTT_SQ_CLK_CTRL
29938 #define CGTT_SQ_CLK_CTRL__ON_DELAY__SHIFT                                                                     0x0
29939 #define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                               0x4
29940 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                         0x10
29941 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                         0x11
29942 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                         0x12
29943 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                         0x13
29944 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                         0x14
29945 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                         0x15
29946 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                         0x16
29947 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                         0x17
29948 #define CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE__SHIFT                                                             0x1d
29949 #define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE__SHIFT                                                                0x1e
29950 #define CGTT_SQ_CLK_CTRL__REG_OVERRIDE__SHIFT                                                                 0x1f
29951 #define CGTT_SQ_CLK_CTRL__ON_DELAY_MASK                                                                       0x0000000FL
29952 #define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                 0x00000FF0L
29953 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                           0x00010000L
29954 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                           0x00020000L
29955 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                           0x00040000L
29956 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                           0x00080000L
29957 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                           0x00100000L
29958 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                           0x00200000L
29959 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                           0x00400000L
29960 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                           0x00800000L
29961 #define CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE_MASK                                                               0x20000000L
29962 #define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE_MASK                                                                  0x40000000L
29963 #define CGTT_SQ_CLK_CTRL__REG_OVERRIDE_MASK                                                                   0x80000000L
29964 //CGTT_SQG_CLK_CTRL
29965 #define CGTT_SQG_CLK_CTRL__ON_DELAY__SHIFT                                                                    0x0
29966 #define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                              0x4
29967 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                        0x10
29968 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                        0x11
29969 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                        0x12
29970 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                        0x13
29971 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                        0x14
29972 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                        0x15
29973 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                        0x16
29974 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                        0x17
29975 #define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE__SHIFT                                                             0x1c
29976 #define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE__SHIFT                                                            0x1d
29977 #define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE__SHIFT                                                               0x1e
29978 #define CGTT_SQG_CLK_CTRL__REG_OVERRIDE__SHIFT                                                                0x1f
29979 #define CGTT_SQG_CLK_CTRL__ON_DELAY_MASK                                                                      0x0000000FL
29980 #define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
29981 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                          0x00010000L
29982 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                          0x00020000L
29983 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                          0x00040000L
29984 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                          0x00080000L
29985 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                          0x00100000L
29986 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                          0x00200000L
29987 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                          0x00400000L
29988 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                          0x00800000L
29989 #define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE_MASK                                                               0x10000000L
29990 #define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE_MASK                                                              0x20000000L
29991 #define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE_MASK                                                                 0x40000000L
29992 #define CGTT_SQG_CLK_CTRL__REG_OVERRIDE_MASK                                                                  0x80000000L
29993 //SQ_ALU_CLK_CTRL
29994 #define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT                                                               0x0
29995 #define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT                                                               0x10
29996 #define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0_MASK                                                                 0x0000FFFFL
29997 #define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1_MASK                                                                 0xFFFF0000L
29998 //SQ_TEX_CLK_CTRL
29999 #define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT                                                               0x0
30000 #define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT                                                               0x10
30001 #define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0_MASK                                                                 0x0000FFFFL
30002 #define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1_MASK                                                                 0xFFFF0000L
30003 //SQ_LDS_CLK_CTRL
30004 #define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT                                                               0x0
30005 #define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT                                                               0x10
30006 #define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0_MASK                                                                 0x0000FFFFL
30007 #define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1_MASK                                                                 0xFFFF0000L
30008 //SQ_POWER_THROTTLE
30009 #define SQ_POWER_THROTTLE__MIN_POWER__SHIFT                                                                   0x0
30010 #define SQ_POWER_THROTTLE__MAX_POWER__SHIFT                                                                   0x10
30011 #define SQ_POWER_THROTTLE__PHASE_OFFSET__SHIFT                                                                0x1e
30012 #define SQ_POWER_THROTTLE__MIN_POWER_MASK                                                                     0x00003FFFL
30013 #define SQ_POWER_THROTTLE__MAX_POWER_MASK                                                                     0x3FFF0000L
30014 #define SQ_POWER_THROTTLE__PHASE_OFFSET_MASK                                                                  0xC0000000L
30015 //SQ_POWER_THROTTLE2
30016 #define SQ_POWER_THROTTLE2__MAX_POWER_DELTA__SHIFT                                                            0x0
30017 #define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE__SHIFT                                                   0x10
30018 #define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO__SHIFT                                                   0x1b
30019 #define SQ_POWER_THROTTLE2__USE_REF_CLOCK__SHIFT                                                              0x1f
30020 #define SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK                                                              0x00003FFFL
30021 #define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK                                                     0x03FF0000L
30022 #define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK                                                     0x78000000L
30023 #define SQ_POWER_THROTTLE2__USE_REF_CLOCK_MASK                                                                0x80000000L
30024 //TD_CGTT_CTRL
30025 #define TD_CGTT_CTRL__ON_DELAY__SHIFT                                                                         0x0
30026 #define TD_CGTT_CTRL__OFF_HYSTERESIS__SHIFT                                                                   0x4
30027 #define TD_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT                                                                   0x18
30028 #define TD_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT                                                                   0x19
30029 #define TD_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT                                                                   0x1a
30030 #define TD_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT                                                                   0x1b
30031 #define TD_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT                                                                   0x1c
30032 #define TD_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT                                                                   0x1d
30033 #define TD_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT                                                                   0x1e
30034 #define TD_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT                                                                   0x1f
30035 #define TD_CGTT_CTRL__ON_DELAY_MASK                                                                           0x0000000FL
30036 #define TD_CGTT_CTRL__OFF_HYSTERESIS_MASK                                                                     0x00000FF0L
30037 #define TD_CGTT_CTRL__SOFT_OVERRIDE7_MASK                                                                     0x01000000L
30038 #define TD_CGTT_CTRL__SOFT_OVERRIDE6_MASK                                                                     0x02000000L
30039 #define TD_CGTT_CTRL__SOFT_OVERRIDE5_MASK                                                                     0x04000000L
30040 #define TD_CGTT_CTRL__SOFT_OVERRIDE4_MASK                                                                     0x08000000L
30041 #define TD_CGTT_CTRL__SOFT_OVERRIDE3_MASK                                                                     0x10000000L
30042 #define TD_CGTT_CTRL__SOFT_OVERRIDE2_MASK                                                                     0x20000000L
30043 #define TD_CGTT_CTRL__SOFT_OVERRIDE1_MASK                                                                     0x40000000L
30044 #define TD_CGTT_CTRL__SOFT_OVERRIDE0_MASK                                                                     0x80000000L
30045 //TA_CGTT_CTRL
30046 #define TA_CGTT_CTRL__ON_DELAY__SHIFT                                                                         0x0
30047 #define TA_CGTT_CTRL__OFF_HYSTERESIS__SHIFT                                                                   0x4
30048 #define TA_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT                                                                   0x18
30049 #define TA_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT                                                                   0x19
30050 #define TA_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT                                                                   0x1a
30051 #define TA_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT                                                                   0x1b
30052 #define TA_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT                                                                   0x1c
30053 #define TA_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT                                                                   0x1d
30054 #define TA_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT                                                                   0x1e
30055 #define TA_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT                                                                   0x1f
30056 #define TA_CGTT_CTRL__ON_DELAY_MASK                                                                           0x0000000FL
30057 #define TA_CGTT_CTRL__OFF_HYSTERESIS_MASK                                                                     0x00000FF0L
30058 #define TA_CGTT_CTRL__SOFT_OVERRIDE7_MASK                                                                     0x01000000L
30059 #define TA_CGTT_CTRL__SOFT_OVERRIDE6_MASK                                                                     0x02000000L
30060 #define TA_CGTT_CTRL__SOFT_OVERRIDE5_MASK                                                                     0x04000000L
30061 #define TA_CGTT_CTRL__SOFT_OVERRIDE4_MASK                                                                     0x08000000L
30062 #define TA_CGTT_CTRL__SOFT_OVERRIDE3_MASK                                                                     0x10000000L
30063 #define TA_CGTT_CTRL__SOFT_OVERRIDE2_MASK                                                                     0x20000000L
30064 #define TA_CGTT_CTRL__SOFT_OVERRIDE1_MASK                                                                     0x40000000L
30065 #define TA_CGTT_CTRL__SOFT_OVERRIDE0_MASK                                                                     0x80000000L
30066 //CGTT_TCPI_CLK_CTRL
30067 #define CGTT_TCPI_CLK_CTRL__ON_DELAY__SHIFT                                                                   0x0
30068 #define CGTT_TCPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                             0x4
30069 #define CGTT_TCPI_CLK_CTRL__SPARE__SHIFT                                                                      0xc
30070 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                       0x10
30071 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                       0x11
30072 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                       0x12
30073 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                       0x13
30074 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                       0x14
30075 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                       0x15
30076 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                       0x16
30077 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                       0x17
30078 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT                                                             0x18
30079 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT                                                             0x19
30080 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT                                                             0x1a
30081 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                             0x1b
30082 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                             0x1c
30083 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT                                                             0x1d
30084 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT                                                             0x1e
30085 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT                                                             0x1f
30086 #define CGTT_TCPI_CLK_CTRL__ON_DELAY_MASK                                                                     0x0000000FL
30087 #define CGTT_TCPI_CLK_CTRL__OFF_HYSTERESIS_MASK                                                               0x00000FF0L
30088 #define CGTT_TCPI_CLK_CTRL__SPARE_MASK                                                                        0x0000F000L
30089 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                         0x00010000L
30090 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                         0x00020000L
30091 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                         0x00040000L
30092 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                         0x00080000L
30093 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                         0x00100000L
30094 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                         0x00200000L
30095 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                         0x00400000L
30096 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                         0x00800000L
30097 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE7_MASK                                                               0x01000000L
30098 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE6_MASK                                                               0x02000000L
30099 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE5_MASK                                                               0x04000000L
30100 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE4_MASK                                                               0x08000000L
30101 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE3_MASK                                                               0x10000000L
30102 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE2_MASK                                                               0x20000000L
30103 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE1_MASK                                                               0x40000000L
30104 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE0_MASK                                                               0x80000000L
30105 //TCX_CGTT_SCLK_CTRL
30106 #define TCX_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT                                                             0x4
30107 #define TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT                                                             0x1a
30108 #define TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                             0x1b
30109 #define TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                             0x1c
30110 #define TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT                                                             0x1d
30111 #define TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT                                                             0x1e
30112 #define TCX_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK                                                               0x00000FF0L
30113 #define TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK                                                               0x04000000L
30114 #define TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK                                                               0x08000000L
30115 #define TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK                                                               0x10000000L
30116 #define TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK                                                               0x20000000L
30117 #define TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK                                                               0x40000000L
30118 //DB_CGTT_CLK_CTRL_0
30119 #define DB_CGTT_CLK_CTRL_0__ON_DELAY__SHIFT                                                                   0x0
30120 #define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS__SHIFT                                                             0x4
30121 #define DB_CGTT_CLK_CTRL_0__RESERVED__SHIFT                                                                   0xc
30122 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE7__SHIFT                                                       0x10
30123 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE6__SHIFT                                                       0x11
30124 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE5__SHIFT                                                       0x12
30125 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE4__SHIFT                                                       0x13
30126 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE3__SHIFT                                                       0x14
30127 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE2__SHIFT                                                       0x15
30128 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE1__SHIFT                                                       0x16
30129 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE0__SHIFT                                                       0x17
30130 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7__SHIFT                                                             0x18
30131 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6__SHIFT                                                             0x19
30132 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5__SHIFT                                                             0x1a
30133 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4__SHIFT                                                             0x1b
30134 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3__SHIFT                                                             0x1c
30135 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2__SHIFT                                                             0x1d
30136 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1__SHIFT                                                             0x1e
30137 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0__SHIFT                                                             0x1f
30138 #define DB_CGTT_CLK_CTRL_0__ON_DELAY_MASK                                                                     0x0000000FL
30139 #define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS_MASK                                                               0x00000FF0L
30140 #define DB_CGTT_CLK_CTRL_0__RESERVED_MASK                                                                     0x0000F000L
30141 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE7_MASK                                                         0x00010000L
30142 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE6_MASK                                                         0x00020000L
30143 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE5_MASK                                                         0x00040000L
30144 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE4_MASK                                                         0x00080000L
30145 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE3_MASK                                                         0x00100000L
30146 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE2_MASK                                                         0x00200000L
30147 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE1_MASK                                                         0x00400000L
30148 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE0_MASK                                                         0x00800000L
30149 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7_MASK                                                               0x01000000L
30150 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6_MASK                                                               0x02000000L
30151 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5_MASK                                                               0x04000000L
30152 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4_MASK                                                               0x08000000L
30153 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3_MASK                                                               0x10000000L
30154 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2_MASK                                                               0x20000000L
30155 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1_MASK                                                               0x40000000L
30156 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0_MASK                                                               0x80000000L
30157 //CB_CGTT_SCLK_CTRL
30158 #define CB_CGTT_SCLK_CTRL__ON_DELAY__SHIFT                                                                    0x0
30159 #define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT                                                              0x4
30160 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                        0x10
30161 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                        0x11
30162 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                        0x12
30163 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                        0x13
30164 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                        0x14
30165 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                        0x15
30166 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                        0x16
30167 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                        0x17
30168 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT                                                              0x18
30169 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT                                                              0x19
30170 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT                                                              0x1a
30171 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                              0x1b
30172 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                              0x1c
30173 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT                                                              0x1d
30174 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT                                                              0x1e
30175 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT                                                              0x1f
30176 #define CB_CGTT_SCLK_CTRL__ON_DELAY_MASK                                                                      0x0000000FL
30177 #define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
30178 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                          0x00010000L
30179 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                          0x00020000L
30180 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                          0x00040000L
30181 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                          0x00080000L
30182 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                          0x00100000L
30183 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                          0x00200000L
30184 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                          0x00400000L
30185 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                          0x00800000L
30186 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK                                                                0x01000000L
30187 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK                                                                0x02000000L
30188 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK                                                                0x04000000L
30189 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK                                                                0x08000000L
30190 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK                                                                0x10000000L
30191 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK                                                                0x20000000L
30192 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK                                                                0x40000000L
30193 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK                                                                0x80000000L
30194 //TCC_CGTT_SCLK_CTRL
30195 #define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT                                                             0x4
30196 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT                                                             0x19
30197 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT                                                             0x1a
30198 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                             0x1b
30199 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                             0x1c
30200 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT                                                             0x1d
30201 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT                                                             0x1e
30202 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT                                                             0x1f
30203 #define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK                                                               0x00000FF0L
30204 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK                                                               0x02000000L
30205 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK                                                               0x04000000L
30206 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK                                                               0x08000000L
30207 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK                                                               0x10000000L
30208 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK                                                               0x20000000L
30209 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK                                                               0x40000000L
30210 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK                                                               0x80000000L
30211 //TCC_CGTT_SCLK_CTRL2
30212 #define TCC_CGTT_SCLK_CTRL2__OFF_HYSTERESIS__SHIFT                                                            0x4
30213 #define TCC_CGTT_SCLK_CTRL2__SOFT_OVERRIDE4__SHIFT                                                            0x1b
30214 #define TCC_CGTT_SCLK_CTRL2__SOFT_OVERRIDE3__SHIFT                                                            0x1c
30215 #define TCC_CGTT_SCLK_CTRL2__SOFT_OVERRIDE2__SHIFT                                                            0x1d
30216 #define TCC_CGTT_SCLK_CTRL2__SOFT_OVERRIDE1__SHIFT                                                            0x1e
30217 #define TCC_CGTT_SCLK_CTRL2__OFF_HYSTERESIS_MASK                                                              0x00000FF0L
30218 #define TCC_CGTT_SCLK_CTRL2__SOFT_OVERRIDE4_MASK                                                              0x08000000L
30219 #define TCC_CGTT_SCLK_CTRL2__SOFT_OVERRIDE3_MASK                                                              0x10000000L
30220 #define TCC_CGTT_SCLK_CTRL2__SOFT_OVERRIDE2_MASK                                                              0x20000000L
30221 #define TCC_CGTT_SCLK_CTRL2__SOFT_OVERRIDE1_MASK                                                              0x40000000L
30222 //TCC_CGTT_SCLK_CTRL3
30223 #define TCC_CGTT_SCLK_CTRL3__OFF_HYSTERESIS__SHIFT                                                            0x4
30224 #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE18__SHIFT                                                           0xc
30225 #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE17__SHIFT                                                           0xd
30226 #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE16__SHIFT                                                           0xe
30227 #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE15__SHIFT                                                           0xf
30228 #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE14__SHIFT                                                           0x10
30229 #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE13__SHIFT                                                           0x11
30230 #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE12__SHIFT                                                           0x12
30231 #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE11__SHIFT                                                           0x13
30232 #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE10__SHIFT                                                           0x14
30233 #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE9__SHIFT                                                            0x15
30234 #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE8__SHIFT                                                            0x17
30235 #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE7__SHIFT                                                            0x18
30236 #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE6__SHIFT                                                            0x19
30237 #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE5__SHIFT                                                            0x1a
30238 #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE4__SHIFT                                                            0x1b
30239 #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE3__SHIFT                                                            0x1c
30240 #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE2__SHIFT                                                            0x1d
30241 #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE1__SHIFT                                                            0x1e
30242 #define TCC_CGTT_SCLK_CTRL3__OFF_HYSTERESIS_MASK                                                              0x00000FF0L
30243 #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE18_MASK                                                             0x00001000L
30244 #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE17_MASK                                                             0x00002000L
30245 #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE16_MASK                                                             0x00004000L
30246 #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE15_MASK                                                             0x00008000L
30247 #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE14_MASK                                                             0x00010000L
30248 #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE13_MASK                                                             0x00020000L
30249 #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE12_MASK                                                             0x00040000L
30250 #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE11_MASK                                                             0x00080000L
30251 #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE10_MASK                                                             0x00100000L
30252 #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE9_MASK                                                              0x00200000L
30253 #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE8_MASK                                                              0x00800000L
30254 #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE7_MASK                                                              0x01000000L
30255 #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE6_MASK                                                              0x02000000L
30256 #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE5_MASK                                                              0x04000000L
30257 #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE4_MASK                                                              0x08000000L
30258 #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE3_MASK                                                              0x10000000L
30259 #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE2_MASK                                                              0x20000000L
30260 #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE1_MASK                                                              0x40000000L
30261 //TCA_CGTT_SCLK_CTRL
30262 #define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT                                                             0x4
30263 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT                                                             0x1a
30264 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                             0x1b
30265 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                             0x1c
30266 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT                                                             0x1d
30267 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT                                                             0x1e
30268 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT                                                             0x1f
30269 #define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK                                                               0x00000FF0L
30270 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK                                                               0x04000000L
30271 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK                                                               0x08000000L
30272 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK                                                               0x10000000L
30273 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK                                                               0x20000000L
30274 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK                                                               0x40000000L
30275 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK                                                               0x80000000L
30276 //CGTT_CP_CLK_CTRL
30277 #define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                               0x4
30278 #define CGTT_CP_CLK_CTRL__MGLS_OVERRIDE__SHIFT                                                                0xf
30279 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                         0x10
30280 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                         0x11
30281 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                         0x12
30282 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                         0x13
30283 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                         0x14
30284 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                         0x15
30285 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                         0x16
30286 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                         0x17
30287 #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT                                                        0x1d
30288 #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT                                                            0x1e
30289 #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT                                                            0x1f
30290 #define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                 0x00000FF0L
30291 #define CGTT_CP_CLK_CTRL__MGLS_OVERRIDE_MASK                                                                  0x00008000L
30292 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                           0x00010000L
30293 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                           0x00020000L
30294 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                           0x00040000L
30295 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                           0x00080000L
30296 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                           0x00100000L
30297 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                           0x00200000L
30298 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                           0x00400000L
30299 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                           0x00800000L
30300 #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK                                                          0x20000000L
30301 #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK                                                              0x40000000L
30302 #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG_MASK                                                              0x80000000L
30303 //CGTT_CPC_CLK_CTRL
30304 #define CGTT_CPC_CLK_CTRL__REG_CLK_OFF_HYSTERESIS__SHIFT                                                      0x0
30305 #define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                              0x4
30306 #define CGTT_CPC_CLK_CTRL__MGLS_OVERRIDE__SHIFT                                                               0xf
30307 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                        0x10
30308 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                        0x11
30309 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                        0x12
30310 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                        0x13
30311 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                        0x14
30312 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                        0x15
30313 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                        0x16
30314 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                        0x17
30315 #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT                                                       0x1d
30316 #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT                                                           0x1e
30317 #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT                                                           0x1f
30318 #define CGTT_CPC_CLK_CTRL__REG_CLK_OFF_HYSTERESIS_MASK                                                        0x0000000FL
30319 #define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
30320 #define CGTT_CPC_CLK_CTRL__MGLS_OVERRIDE_MASK                                                                 0x00008000L
30321 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                          0x00010000L
30322 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                          0x00020000L
30323 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                          0x00040000L
30324 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                          0x00080000L
30325 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                          0x00100000L
30326 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                          0x00200000L
30327 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                          0x00400000L
30328 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                          0x00800000L
30329 #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK                                                         0x20000000L
30330 #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK                                                             0x40000000L
30331 #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK                                                             0x80000000L
30332 //CGTT_RLC_CLK_CTRL
30333 #define CGTT_RLC_CLK_CTRL__ON_DELAY__SHIFT                                                                    0x0
30334 #define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                              0x4
30335 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                        0x10
30336 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                        0x11
30337 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                        0x12
30338 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                        0x13
30339 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                        0x14
30340 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                        0x15
30341 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                        0x16
30342 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                        0x17
30343 #define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT                                                           0x1e
30344 #define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT                                                           0x1f
30345 #define CGTT_RLC_CLK_CTRL__ON_DELAY_MASK                                                                      0x0000000FL
30346 #define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
30347 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                          0x00010000L
30348 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                          0x00020000L
30349 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                          0x00040000L
30350 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                          0x00080000L
30351 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                          0x00100000L
30352 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                          0x00200000L
30353 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                          0x00400000L
30354 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                          0x00800000L
30355 #define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK                                                             0x40000000L
30356 #define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK                                                             0x80000000L
30357 //RLC_GFX_RM_CNTL
30358 #define RLC_GFX_RM_CNTL__RLC_GFX_RM_VALID__SHIFT                                                              0x0
30359 #define RLC_GFX_RM_CNTL__RESERVED__SHIFT                                                                      0x1
30360 #define RLC_GFX_RM_CNTL__RLC_GFX_RM_VALID_MASK                                                                0x00000001L
30361 #define RLC_GFX_RM_CNTL__RESERVED_MASK                                                                        0xFFFFFFFEL
30362 //RMI_CGTT_SCLK_CTRL
30363 #define RMI_CGTT_SCLK_CTRL__ON_DELAY__SHIFT                                                                   0x0
30364 #define RMI_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT                                                             0x4
30365 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                       0x10
30366 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                       0x11
30367 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                       0x12
30368 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                       0x13
30369 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                       0x14
30370 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                       0x15
30371 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                       0x16
30372 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                       0x17
30373 #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT                                                             0x19
30374 #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT                                                             0x1a
30375 #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                             0x1b
30376 #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                             0x1c
30377 #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT                                                             0x1d
30378 #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT                                                             0x1e
30379 #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT                                                             0x1f
30380 #define RMI_CGTT_SCLK_CTRL__ON_DELAY_MASK                                                                     0x0000000FL
30381 #define RMI_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK                                                               0x00000FF0L
30382 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                         0x00010000L
30383 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                         0x00020000L
30384 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                         0x00040000L
30385 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                         0x00080000L
30386 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                         0x00100000L
30387 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                         0x00200000L
30388 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                         0x00400000L
30389 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                         0x00800000L
30390 #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK                                                               0x02000000L
30391 #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK                                                               0x04000000L
30392 #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK                                                               0x08000000L
30393 #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK                                                               0x10000000L
30394 #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK                                                               0x20000000L
30395 #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK                                                               0x40000000L
30396 #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK                                                               0x80000000L
30397 //CGTT_TCPF_CLK_CTRL
30398 #define CGTT_TCPF_CLK_CTRL__ON_DELAY__SHIFT                                                                   0x0
30399 #define CGTT_TCPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                             0x4
30400 #define CGTT_TCPF_CLK_CTRL__SPARE__SHIFT                                                                      0xc
30401 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                       0x10
30402 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                       0x11
30403 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                       0x12
30404 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                       0x13
30405 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                       0x14
30406 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                       0x15
30407 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                       0x16
30408 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                       0x17
30409 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE7__SHIFT                                                             0x18
30410 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE6__SHIFT                                                             0x19
30411 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE5__SHIFT                                                             0x1a
30412 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                             0x1b
30413 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                             0x1c
30414 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE2__SHIFT                                                             0x1d
30415 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE1__SHIFT                                                             0x1e
30416 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE0__SHIFT                                                             0x1f
30417 #define CGTT_TCPF_CLK_CTRL__ON_DELAY_MASK                                                                     0x0000000FL
30418 #define CGTT_TCPF_CLK_CTRL__OFF_HYSTERESIS_MASK                                                               0x00000FF0L
30419 #define CGTT_TCPF_CLK_CTRL__SPARE_MASK                                                                        0x0000F000L
30420 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                         0x00010000L
30421 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                         0x00020000L
30422 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                         0x00040000L
30423 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                         0x00080000L
30424 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                         0x00100000L
30425 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                         0x00200000L
30426 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                         0x00400000L
30427 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                         0x00800000L
30428 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE7_MASK                                                               0x01000000L
30429 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE6_MASK                                                               0x02000000L
30430 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE5_MASK                                                               0x04000000L
30431 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE4_MASK                                                               0x08000000L
30432 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE3_MASK                                                               0x10000000L
30433 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE2_MASK                                                               0x20000000L
30434 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE1_MASK                                                               0x40000000L
30435 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE0_MASK                                                               0x80000000L
30436 
30437 
30438 // addressBlock: xcd0_gc_hypdec
30439 //CP_HYP_PFP_UCODE_ADDR
30440 #define CP_HYP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT                                                              0x0
30441 #define CP_HYP_PFP_UCODE_ADDR__UCODE_ADDR_MASK                                                                0x00003FFFL
30442 //CP_PFP_UCODE_ADDR
30443 #define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT                                                                  0x0
30444 #define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK                                                                    0x00003FFFL
30445 //CP_HYP_PFP_UCODE_DATA
30446 #define CP_HYP_PFP_UCODE_DATA__UCODE_DATA__SHIFT                                                              0x0
30447 #define CP_HYP_PFP_UCODE_DATA__UCODE_DATA_MASK                                                                0xFFFFFFFFL
30448 //CP_PFP_UCODE_DATA
30449 #define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT                                                                  0x0
30450 #define CP_PFP_UCODE_DATA__UCODE_DATA_MASK                                                                    0xFFFFFFFFL
30451 //CP_HYP_ME_UCODE_ADDR
30452 #define CP_HYP_ME_UCODE_ADDR__UCODE_ADDR__SHIFT                                                               0x0
30453 #define CP_HYP_ME_UCODE_ADDR__UCODE_ADDR_MASK                                                                 0x00001FFFL
30454 //CP_ME_RAM_RADDR
30455 #define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT                                                                  0x0
30456 #define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK                                                                    0x00001FFFL
30457 //CP_ME_RAM_WADDR
30458 #define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT                                                                  0x0
30459 #define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK                                                                    0x00001FFFL
30460 //CP_HYP_ME_UCODE_DATA
30461 #define CP_HYP_ME_UCODE_DATA__UCODE_DATA__SHIFT                                                               0x0
30462 #define CP_HYP_ME_UCODE_DATA__UCODE_DATA_MASK                                                                 0xFFFFFFFFL
30463 //CP_ME_RAM_DATA
30464 #define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT                                                                    0x0
30465 #define CP_ME_RAM_DATA__ME_RAM_DATA_MASK                                                                      0xFFFFFFFFL
30466 //CP_CE_UCODE_ADDR
30467 #define CP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT                                                                   0x0
30468 #define CP_CE_UCODE_ADDR__UCODE_ADDR_MASK                                                                     0x00000FFFL
30469 //CP_HYP_CE_UCODE_ADDR
30470 #define CP_HYP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT                                                               0x0
30471 #define CP_HYP_CE_UCODE_ADDR__UCODE_ADDR_MASK                                                                 0x00000FFFL
30472 //CP_CE_UCODE_DATA
30473 #define CP_CE_UCODE_DATA__UCODE_DATA__SHIFT                                                                   0x0
30474 #define CP_CE_UCODE_DATA__UCODE_DATA_MASK                                                                     0xFFFFFFFFL
30475 //CP_HYP_CE_UCODE_DATA
30476 #define CP_HYP_CE_UCODE_DATA__UCODE_DATA__SHIFT                                                               0x0
30477 #define CP_HYP_CE_UCODE_DATA__UCODE_DATA_MASK                                                                 0xFFFFFFFFL
30478 //CP_HYP_MEC1_UCODE_ADDR
30479 #define CP_HYP_MEC1_UCODE_ADDR__UCODE_ADDR__SHIFT                                                             0x0
30480 #define CP_HYP_MEC1_UCODE_ADDR__UCODE_ADDR_MASK                                                               0x0001FFFFL
30481 //CP_MEC_ME1_UCODE_ADDR
30482 #define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR__SHIFT                                                              0x0
30483 #define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR_MASK                                                                0x0001FFFFL
30484 //CP_HYP_MEC1_UCODE_DATA
30485 #define CP_HYP_MEC1_UCODE_DATA__UCODE_DATA__SHIFT                                                             0x0
30486 #define CP_HYP_MEC1_UCODE_DATA__UCODE_DATA_MASK                                                               0xFFFFFFFFL
30487 //CP_MEC_ME1_UCODE_DATA
30488 #define CP_MEC_ME1_UCODE_DATA__UCODE_DATA__SHIFT                                                              0x0
30489 #define CP_MEC_ME1_UCODE_DATA__UCODE_DATA_MASK                                                                0xFFFFFFFFL
30490 //CP_HYP_MEC2_UCODE_ADDR
30491 #define CP_HYP_MEC2_UCODE_ADDR__UCODE_ADDR__SHIFT                                                             0x0
30492 #define CP_HYP_MEC2_UCODE_ADDR__UCODE_ADDR_MASK                                                               0x0001FFFFL
30493 //CP_MEC_ME2_UCODE_ADDR
30494 #define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR__SHIFT                                                              0x0
30495 #define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR_MASK                                                                0x0001FFFFL
30496 //CP_HYP_MEC2_UCODE_DATA
30497 #define CP_HYP_MEC2_UCODE_DATA__UCODE_DATA__SHIFT                                                             0x0
30498 #define CP_HYP_MEC2_UCODE_DATA__UCODE_DATA_MASK                                                               0xFFFFFFFFL
30499 //CP_MEC_ME2_UCODE_DATA
30500 #define CP_MEC_ME2_UCODE_DATA__UCODE_DATA__SHIFT                                                              0x0
30501 #define CP_MEC_ME2_UCODE_DATA__UCODE_DATA_MASK                                                                0xFFFFFFFFL
30502 //CP_HYP_PFP_UCODE_CHKSUM
30503 #define CP_HYP_PFP_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT                                                          0x0
30504 #define CP_HYP_PFP_UCODE_CHKSUM__UCODE_CHKSUM_MASK                                                            0xFFFFFFFFL
30505 //CP_HYP_CE_UCODE_CHKSUM
30506 #define CP_HYP_CE_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT                                                           0x0
30507 #define CP_HYP_CE_UCODE_CHKSUM__UCODE_CHKSUM_MASK                                                             0xFFFFFFFFL
30508 //CP_HYP_ME_UCODE_CHKSUM
30509 #define CP_HYP_ME_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT                                                           0x0
30510 #define CP_HYP_ME_UCODE_CHKSUM__UCODE_CHKSUM_MASK                                                             0xFFFFFFFFL
30511 //CP_HYP_MEC_ME1_UCODE_CHKSUM
30512 #define CP_HYP_MEC_ME1_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT                                                      0x0
30513 #define CP_HYP_MEC_ME1_UCODE_CHKSUM__UCODE_CHKSUM_MASK                                                        0xFFFFFFFFL
30514 //CP_HYP_MEC_ME2_UCODE_CHKSUM
30515 #define CP_HYP_MEC_ME2_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT                                                      0x0
30516 #define CP_HYP_MEC_ME2_UCODE_CHKSUM__UCODE_CHKSUM_MASK                                                        0xFFFFFFFFL
30517 //CP_HYP_XCP_CTL
30518 #define CP_HYP_XCP_CTL__VIRTUAL_XCC_ID__SHIFT                                                                 0x0
30519 #define CP_HYP_XCP_CTL__NUM_XCC_IN_XCP__SHIFT                                                                 0x3
30520 #define CP_HYP_XCP_CTL__VIRTUAL_XCC_ID_MASK                                                                   0x00000007L
30521 #define CP_HYP_XCP_CTL__NUM_XCC_IN_XCP_MASK                                                                   0x00000078L
30522 //RLC_GPM_UCODE_ADDR
30523 #define RLC_GPM_UCODE_ADDR__UCODE_ADDR__SHIFT                                                                 0x0
30524 #define RLC_GPM_UCODE_ADDR__RESERVED__SHIFT                                                                   0xe
30525 #define RLC_GPM_UCODE_ADDR__UCODE_ADDR_MASK                                                                   0x00003FFFL
30526 #define RLC_GPM_UCODE_ADDR__RESERVED_MASK                                                                     0xFFFFC000L
30527 //RLC_GPM_UCODE_DATA
30528 #define RLC_GPM_UCODE_DATA__UCODE_DATA__SHIFT                                                                 0x0
30529 #define RLC_GPM_UCODE_DATA__UCODE_DATA_MASK                                                                   0xFFFFFFFFL
30530 //GRBM_GFX_INDEX_SR_SELECT
30531 #define GRBM_GFX_INDEX_SR_SELECT__INDEX__SHIFT                                                                0x0
30532 #define GRBM_GFX_INDEX_SR_SELECT__VF_PF__SHIFT                                                                0x1f
30533 #define GRBM_GFX_INDEX_SR_SELECT__INDEX_MASK                                                                  0x00000007L
30534 #define GRBM_GFX_INDEX_SR_SELECT__VF_PF_MASK                                                                  0x80000000L
30535 //GRBM_GFX_INDEX_SR_DATA
30536 #define GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX__SHIFT                                                         0x0
30537 #define GRBM_GFX_INDEX_SR_DATA__SH_INDEX__SHIFT                                                               0x8
30538 #define GRBM_GFX_INDEX_SR_DATA__SE_INDEX__SHIFT                                                               0x10
30539 #define GRBM_GFX_INDEX_SR_DATA__SH_BROADCAST_WRITES__SHIFT                                                    0x1d
30540 #define GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES__SHIFT                                              0x1e
30541 #define GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES__SHIFT                                                    0x1f
30542 #define GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX_MASK                                                           0x000000FFL
30543 #define GRBM_GFX_INDEX_SR_DATA__SH_INDEX_MASK                                                                 0x0000FF00L
30544 #define GRBM_GFX_INDEX_SR_DATA__SE_INDEX_MASK                                                                 0x00FF0000L
30545 #define GRBM_GFX_INDEX_SR_DATA__SH_BROADCAST_WRITES_MASK                                                      0x20000000L
30546 #define GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES_MASK                                                0x40000000L
30547 #define GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES_MASK                                                      0x80000000L
30548 //GRBM_GFX_CNTL_SR_SELECT
30549 #define GRBM_GFX_CNTL_SR_SELECT__INDEX__SHIFT                                                                 0x0
30550 #define GRBM_GFX_CNTL_SR_SELECT__VF_PF__SHIFT                                                                 0x1f
30551 #define GRBM_GFX_CNTL_SR_SELECT__INDEX_MASK                                                                   0x00000007L
30552 #define GRBM_GFX_CNTL_SR_SELECT__VF_PF_MASK                                                                   0x80000000L
30553 //GRBM_GFX_CNTL_SR_DATA
30554 #define GRBM_GFX_CNTL_SR_DATA__PIPEID__SHIFT                                                                  0x0
30555 #define GRBM_GFX_CNTL_SR_DATA__MEID__SHIFT                                                                    0x2
30556 #define GRBM_GFX_CNTL_SR_DATA__VMID__SHIFT                                                                    0x4
30557 #define GRBM_GFX_CNTL_SR_DATA__QUEUEID__SHIFT                                                                 0x8
30558 #define GRBM_GFX_CNTL_SR_DATA__PIPEID_MASK                                                                    0x00000003L
30559 #define GRBM_GFX_CNTL_SR_DATA__MEID_MASK                                                                      0x0000000CL
30560 #define GRBM_GFX_CNTL_SR_DATA__VMID_MASK                                                                      0x000000F0L
30561 #define GRBM_GFX_CNTL_SR_DATA__QUEUEID_MASK                                                                   0x00000700L
30562 //GRBM_MCM_ADDR
30563 #define GRBM_MCM_ADDR__MCM_ADDR_IH__SHIFT                                                                     0x0
30564 #define GRBM_MCM_ADDR__MCM_ADDR_IH_MASK                                                                       0x000000FFL
30565 //RLC_GPU_IOV_VF_ENABLE
30566 #define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE__SHIFT                                                               0x0
30567 #define RLC_GPU_IOV_VF_ENABLE__RESERVED__SHIFT                                                                0x1
30568 #define RLC_GPU_IOV_VF_ENABLE__VF_NUM__SHIFT                                                                  0x10
30569 #define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE_MASK                                                                 0x00000001L
30570 #define RLC_GPU_IOV_VF_ENABLE__RESERVED_MASK                                                                  0x0000FFFEL
30571 #define RLC_GPU_IOV_VF_ENABLE__VF_NUM_MASK                                                                    0xFFFF0000L
30572 //RLC_GPU_IOV_CFG_REG6
30573 #define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE__SHIFT                                                               0x0
30574 #define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION__SHIFT                                                           0x7
30575 #define RLC_GPU_IOV_CFG_REG6__RESERVED__SHIFT                                                                 0x8
30576 #define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET__SHIFT                                                             0xa
30577 #define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE_MASK                                                                 0x0000007FL
30578 #define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION_MASK                                                             0x00000080L
30579 #define RLC_GPU_IOV_CFG_REG6__RESERVED_MASK                                                                   0x00000300L
30580 #define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET_MASK                                                               0xFFFFFC00L
30581 //RLC_GPU_IOV_CFG_REG8
30582 #define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS__SHIFT                                                           0x0
30583 #define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS_MASK                                                             0xFFFFFFFFL
30584 //RLC_RLCV_TIMER_INT_0
30585 #define RLC_RLCV_TIMER_INT_0__TIMER__SHIFT                                                                    0x0
30586 #define RLC_RLCV_TIMER_INT_0__TIMER_MASK                                                                      0xFFFFFFFFL
30587 //RLC_RLCV_TIMER_CTRL
30588 #define RLC_RLCV_TIMER_CTRL__TIMER_0_EN__SHIFT                                                                0x0
30589 #define RLC_RLCV_TIMER_CTRL__TIMER_1_EN__SHIFT                                                                0x1
30590 #define RLC_RLCV_TIMER_CTRL__RESERVED__SHIFT                                                                  0x2
30591 #define RLC_RLCV_TIMER_CTRL__TIMER_0_EN_MASK                                                                  0x00000001L
30592 #define RLC_RLCV_TIMER_CTRL__TIMER_1_EN_MASK                                                                  0x00000002L
30593 #define RLC_RLCV_TIMER_CTRL__RESERVED_MASK                                                                    0xFFFFFFFCL
30594 //RLC_RLCV_TIMER_STAT
30595 #define RLC_RLCV_TIMER_STAT__TIMER_0_STAT__SHIFT                                                              0x0
30596 #define RLC_RLCV_TIMER_STAT__TIMER_1_STAT__SHIFT                                                              0x1
30597 #define RLC_RLCV_TIMER_STAT__RESERVED__SHIFT                                                                  0x2
30598 #define RLC_RLCV_TIMER_STAT__TIMER_0_ENABLE_SYNC__SHIFT                                                       0x8
30599 #define RLC_RLCV_TIMER_STAT__TIMER_1_ENABLE_SYNC__SHIFT                                                       0x9
30600 #define RLC_RLCV_TIMER_STAT__TIMER_0_STAT_MASK                                                                0x00000001L
30601 #define RLC_RLCV_TIMER_STAT__TIMER_1_STAT_MASK                                                                0x00000002L
30602 #define RLC_RLCV_TIMER_STAT__RESERVED_MASK                                                                    0x000000FCL
30603 #define RLC_RLCV_TIMER_STAT__TIMER_0_ENABLE_SYNC_MASK                                                         0x00000100L
30604 #define RLC_RLCV_TIMER_STAT__TIMER_1_ENABLE_SYNC_MASK                                                         0x00000200L
30605 //RLC_GPU_IOV_VF_DOORBELL_STATUS
30606 #define RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS__SHIFT                                             0x0
30607 #define RLC_GPU_IOV_VF_DOORBELL_STATUS__RESERVED__SHIFT                                                       0x10
30608 #define RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS__SHIFT                                             0x1f
30609 #define RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_MASK                                               0x0000FFFFL
30610 #define RLC_GPU_IOV_VF_DOORBELL_STATUS__RESERVED_MASK                                                         0x7FFF0000L
30611 #define RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS_MASK                                               0x80000000L
30612 //RLC_GPU_IOV_VF_DOORBELL_STATUS_SET
30613 #define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET__SHIFT                                     0x0
30614 #define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__RESERVED__SHIFT                                                   0x10
30615 #define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET__SHIFT                                     0x1f
30616 #define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET_MASK                                       0x0000FFFFL
30617 #define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__RESERVED_MASK                                                     0x7FFF0000L
30618 #define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET_MASK                                       0x80000000L
30619 //RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR
30620 #define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR__SHIFT                                     0x0
30621 #define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__RESERVED__SHIFT                                                   0x10
30622 #define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR__SHIFT                                     0x1f
30623 #define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR_MASK                                       0x0000FFFFL
30624 #define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__RESERVED_MASK                                                     0x7FFF0000L
30625 #define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR_MASK                                       0x80000000L
30626 //RLC_GPU_IOV_VF_MASK
30627 #define RLC_GPU_IOV_VF_MASK__VF_MASK__SHIFT                                                                   0x0
30628 #define RLC_GPU_IOV_VF_MASK__RESERVED__SHIFT                                                                  0x10
30629 #define RLC_GPU_IOV_VF_MASK__VF_MASK_MASK                                                                     0x0000FFFFL
30630 #define RLC_GPU_IOV_VF_MASK__RESERVED_MASK                                                                    0xFFFF0000L
30631 //RLC_HYP_SEMAPHORE_0
30632 #define RLC_HYP_SEMAPHORE_0__CLIENT_ID__SHIFT                                                                 0x0
30633 #define RLC_HYP_SEMAPHORE_0__RESERVED__SHIFT                                                                  0x5
30634 #define RLC_HYP_SEMAPHORE_0__CLIENT_ID_MASK                                                                   0x0000001FL
30635 #define RLC_HYP_SEMAPHORE_0__RESERVED_MASK                                                                    0xFFFFFFE0L
30636 //RLC_HYP_SEMAPHORE_1
30637 #define RLC_HYP_SEMAPHORE_1__CLIENT_ID__SHIFT                                                                 0x0
30638 #define RLC_HYP_SEMAPHORE_1__RESERVED__SHIFT                                                                  0x5
30639 #define RLC_HYP_SEMAPHORE_1__CLIENT_ID_MASK                                                                   0x0000001FL
30640 #define RLC_HYP_SEMAPHORE_1__RESERVED_MASK                                                                    0xFFFFFFE0L
30641 //RLC_CLK_CNTL
30642 #define RLC_CLK_CNTL__RLC_SRM_CLK_CNTL__SHIFT                                                                 0x0
30643 #define RLC_CLK_CNTL__RLC_SPM_CLK_CNTL__SHIFT                                                                 0x2
30644 #define RLC_CLK_CNTL__RLC_GPM_CLK_CNTL__SHIFT                                                                 0x4
30645 #define RLC_CLK_CNTL__RLC_CMN_CLK_CNTL__SHIFT                                                                 0x5
30646 #define RLC_CLK_CNTL__RLC_TC_CLK_CNTL__SHIFT                                                                  0x6
30647 #define RLC_CLK_CNTL__RLC_SPP_CLK_CNTL__SHIFT                                                                 0x7
30648 #define RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE__SHIFT                                                      0x8
30649 #define RLC_CLK_CNTL__RLC_EDC_OVERRIDE__SHIFT                                                                 0x9
30650 #define RLC_CLK_CNTL__RESERVED_11_10__SHIFT                                                                   0xa
30651 #define RLC_CLK_CNTL__RLC_TC_FGCG_REP_OVERRIDE__SHIFT                                                         0xc
30652 #define RLC_CLK_CNTL__RLC_DFLL_CLK_CNTL__SHIFT                                                                0xd
30653 #define RLC_CLK_CNTL__DBGBUS_CLK_ACTIVE_OVERRIDE__SHIFT                                                       0xe
30654 #define RLC_CLK_CNTL__RLC_CAC2_CLK_CNTL__SHIFT                                                                0xf
30655 #define RLC_CLK_CNTL__RESERVED_1__SHIFT                                                                       0x11
30656 #define RLC_CLK_CNTL__RLC_UTCL2_FGCG_OVERRIDE__SHIFT                                                          0x12
30657 #define RLC_CLK_CNTL__RESERVED__SHIFT                                                                         0x13
30658 #define RLC_CLK_CNTL__RLC_SRM_CLK_CNTL_MASK                                                                   0x00000003L
30659 #define RLC_CLK_CNTL__RLC_SPM_CLK_CNTL_MASK                                                                   0x0000000CL
30660 #define RLC_CLK_CNTL__RLC_GPM_CLK_CNTL_MASK                                                                   0x00000010L
30661 #define RLC_CLK_CNTL__RLC_CMN_CLK_CNTL_MASK                                                                   0x00000020L
30662 #define RLC_CLK_CNTL__RLC_TC_CLK_CNTL_MASK                                                                    0x00000040L
30663 #define RLC_CLK_CNTL__RLC_SPP_CLK_CNTL_MASK                                                                   0x00000080L
30664 #define RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK                                                        0x00000100L
30665 #define RLC_CLK_CNTL__RLC_EDC_OVERRIDE_MASK                                                                   0x00000200L
30666 #define RLC_CLK_CNTL__RESERVED_11_10_MASK                                                                     0x00000C00L
30667 #define RLC_CLK_CNTL__RLC_TC_FGCG_REP_OVERRIDE_MASK                                                           0x00001000L
30668 #define RLC_CLK_CNTL__RLC_DFLL_CLK_CNTL_MASK                                                                  0x00002000L
30669 #define RLC_CLK_CNTL__DBGBUS_CLK_ACTIVE_OVERRIDE_MASK                                                         0x00004000L
30670 #define RLC_CLK_CNTL__RLC_CAC2_CLK_CNTL_MASK                                                                  0x00018000L
30671 #define RLC_CLK_CNTL__RESERVED_1_MASK                                                                         0x00020000L
30672 #define RLC_CLK_CNTL__RLC_UTCL2_FGCG_OVERRIDE_MASK                                                            0x00040000L
30673 #define RLC_CLK_CNTL__RESERVED_MASK                                                                           0xFFF80000L
30674 //RLC_GPU_IOV_SCH_BLOCK
30675 #define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID__SHIFT                                                            0x0
30676 #define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver__SHIFT                                                           0x4
30677 #define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size__SHIFT                                                          0x8
30678 #define RLC_GPU_IOV_SCH_BLOCK__RESERVED__SHIFT                                                                0x10
30679 #define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID_MASK                                                              0x0000000FL
30680 #define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver_MASK                                                             0x000000F0L
30681 #define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size_MASK                                                            0x00007F00L
30682 #define RLC_GPU_IOV_SCH_BLOCK__RESERVED_MASK                                                                  0x7FFF0000L
30683 //RLC_GPU_IOV_CFG_REG1
30684 #define RLC_GPU_IOV_CFG_REG1__CMD_TYPE__SHIFT                                                                 0x0
30685 #define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE__SHIFT                                                              0x4
30686 #define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN__SHIFT                                                      0x5
30687 #define RLC_GPU_IOV_CFG_REG1__RESERVED__SHIFT                                                                 0x6
30688 #define RLC_GPU_IOV_CFG_REG1__FCN_ID__SHIFT                                                                   0x8
30689 #define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID__SHIFT                                                              0x10
30690 #define RLC_GPU_IOV_CFG_REG1__RESERVED1__SHIFT                                                                0x18
30691 #define RLC_GPU_IOV_CFG_REG1__CMD_TYPE_MASK                                                                   0x0000000FL
30692 #define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_MASK                                                                0x00000010L
30693 #define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN_MASK                                                        0x00000020L
30694 #define RLC_GPU_IOV_CFG_REG1__RESERVED_MASK                                                                   0x000000C0L
30695 #define RLC_GPU_IOV_CFG_REG1__FCN_ID_MASK                                                                     0x0000FF00L
30696 #define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID_MASK                                                                0x00FF0000L
30697 #define RLC_GPU_IOV_CFG_REG1__RESERVED1_MASK                                                                  0xFF000000L
30698 //RLC_GPU_IOV_CFG_REG2
30699 #define RLC_GPU_IOV_CFG_REG2__CMD_STATUS__SHIFT                                                               0x0
30700 #define RLC_GPU_IOV_CFG_REG2__RESERVED__SHIFT                                                                 0x4
30701 #define RLC_GPU_IOV_CFG_REG2__CMD_STATUS_MASK                                                                 0x0000000FL
30702 #define RLC_GPU_IOV_CFG_REG2__RESERVED_MASK                                                                   0xFFFFFFF0L
30703 //RLC_GPU_IOV_VM_BUSY_STATUS
30704 #define RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS__SHIFT                                                     0x0
30705 #define RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS_MASK                                                       0xFFFFFFFFL
30706 //RLC_GPU_IOV_SCH_0
30707 #define RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS__SHIFT                                                            0x0
30708 #define RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS_MASK                                                              0xFFFFFFFFL
30709 //RLC_GPU_IOV_ACTIVE_FCN_ID
30710 #define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID__SHIFT                                                               0x0
30711 #define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED__SHIFT                                                            0x4
30712 #define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF__SHIFT                                                               0x1f
30713 #define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID_MASK                                                                 0x0000000FL
30714 #define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED_MASK                                                              0x7FFFFFF0L
30715 #define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF_MASK                                                                 0x80000000L
30716 //RLC_GPU_IOV_SCH_3
30717 #define RLC_GPU_IOV_SCH_3__Time_Quanta_Def__SHIFT                                                             0x0
30718 #define RLC_GPU_IOV_SCH_3__Time_Quanta_Def_MASK                                                               0xFFFFFFFFL
30719 //RLC_GPU_IOV_SCH_1
30720 #define RLC_GPU_IOV_SCH_1__DATA__SHIFT                                                                        0x0
30721 #define RLC_GPU_IOV_SCH_1__DATA_MASK                                                                          0xFFFFFFFFL
30722 //RLC_GPU_IOV_SCH_2
30723 #define RLC_GPU_IOV_SCH_2__DATA__SHIFT                                                                        0x0
30724 #define RLC_GPU_IOV_SCH_2__DATA_MASK                                                                          0xFFFFFFFFL
30725 //RLC_GPU_IOV_INT_STAT
30726 #define RLC_GPU_IOV_INT_STAT__STATUS__SHIFT                                                                   0x0
30727 #define RLC_GPU_IOV_INT_STAT__STATUS_MASK                                                                     0xFFFFFFFFL
30728 //RLC_RLCV_TIMER_INT_1
30729 #define RLC_RLCV_TIMER_INT_1__TIMER__SHIFT                                                                    0x0
30730 #define RLC_RLCV_TIMER_INT_1__TIMER_MASK                                                                      0xFFFFFFFFL
30731 //RLC_GPU_IOV_UCODE_ADDR
30732 #define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR__SHIFT                                                             0x0
30733 #define RLC_GPU_IOV_UCODE_ADDR__RESERVED__SHIFT                                                               0xc
30734 #define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR_MASK                                                               0x00000FFFL
30735 #define RLC_GPU_IOV_UCODE_ADDR__RESERVED_MASK                                                                 0xFFFFF000L
30736 //RLC_GPU_IOV_UCODE_DATA
30737 #define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA__SHIFT                                                             0x0
30738 #define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA_MASK                                                               0xFFFFFFFFL
30739 //RLC_GPU_IOV_SCRATCH_ADDR
30740 #define RLC_GPU_IOV_SCRATCH_ADDR__ADDR__SHIFT                                                                 0x0
30741 #define RLC_GPU_IOV_SCRATCH_ADDR__RESERVED__SHIFT                                                             0x9
30742 #define RLC_GPU_IOV_SCRATCH_ADDR__ADDR_MASK                                                                   0x000001FFL
30743 #define RLC_GPU_IOV_SCRATCH_ADDR__RESERVED_MASK                                                               0xFFFFFE00L
30744 //RLC_GPU_IOV_SCRATCH_DATA
30745 #define RLC_GPU_IOV_SCRATCH_DATA__DATA__SHIFT                                                                 0x0
30746 #define RLC_GPU_IOV_SCRATCH_DATA__DATA_MASK                                                                   0xFFFFFFFFL
30747 //RLC_GPU_IOV_F32_CNTL
30748 #define RLC_GPU_IOV_F32_CNTL__ENABLE__SHIFT                                                                   0x0
30749 #define RLC_GPU_IOV_F32_CNTL__RESERVED__SHIFT                                                                 0x1
30750 #define RLC_GPU_IOV_F32_CNTL__ENABLE_MASK                                                                     0x00000001L
30751 #define RLC_GPU_IOV_F32_CNTL__RESERVED_MASK                                                                   0xFFFFFFFEL
30752 //RLC_GPU_IOV_F32_RESET
30753 #define RLC_GPU_IOV_F32_RESET__RESET__SHIFT                                                                   0x0
30754 #define RLC_GPU_IOV_F32_RESET__RESERVED__SHIFT                                                                0x1
30755 #define RLC_GPU_IOV_F32_RESET__RESET_MASK                                                                     0x00000001L
30756 #define RLC_GPU_IOV_F32_RESET__RESERVED_MASK                                                                  0xFFFFFFFEL
30757 //RLC_GPU_IOV_SDMA0_STATUS
30758 #define RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED__SHIFT                                                            0x0
30759 #define RLC_GPU_IOV_SDMA0_STATUS__RESERVED__SHIFT                                                             0x1
30760 #define RLC_GPU_IOV_SDMA0_STATUS__SAVED__SHIFT                                                                0x8
30761 #define RLC_GPU_IOV_SDMA0_STATUS__RESERVED1__SHIFT                                                            0x9
30762 #define RLC_GPU_IOV_SDMA0_STATUS__RESTORED__SHIFT                                                             0xc
30763 #define RLC_GPU_IOV_SDMA0_STATUS__RESERVED2__SHIFT                                                            0xd
30764 #define RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED_MASK                                                              0x00000001L
30765 #define RLC_GPU_IOV_SDMA0_STATUS__RESERVED_MASK                                                               0x000000FEL
30766 #define RLC_GPU_IOV_SDMA0_STATUS__SAVED_MASK                                                                  0x00000100L
30767 #define RLC_GPU_IOV_SDMA0_STATUS__RESERVED1_MASK                                                              0x00000E00L
30768 #define RLC_GPU_IOV_SDMA0_STATUS__RESTORED_MASK                                                               0x00001000L
30769 #define RLC_GPU_IOV_SDMA0_STATUS__RESERVED2_MASK                                                              0xFFFFE000L
30770 //RLC_GPU_IOV_SDMA1_STATUS
30771 #define RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED__SHIFT                                                            0x0
30772 #define RLC_GPU_IOV_SDMA1_STATUS__RESERVED__SHIFT                                                             0x1
30773 #define RLC_GPU_IOV_SDMA1_STATUS__SAVED__SHIFT                                                                0x8
30774 #define RLC_GPU_IOV_SDMA1_STATUS__RESERVED1__SHIFT                                                            0x9
30775 #define RLC_GPU_IOV_SDMA1_STATUS__RESTORED__SHIFT                                                             0xc
30776 #define RLC_GPU_IOV_SDMA1_STATUS__RESERVED2__SHIFT                                                            0xd
30777 #define RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED_MASK                                                              0x00000001L
30778 #define RLC_GPU_IOV_SDMA1_STATUS__RESERVED_MASK                                                               0x000000FEL
30779 #define RLC_GPU_IOV_SDMA1_STATUS__SAVED_MASK                                                                  0x00000100L
30780 #define RLC_GPU_IOV_SDMA1_STATUS__RESERVED1_MASK                                                              0x00000E00L
30781 #define RLC_GPU_IOV_SDMA1_STATUS__RESTORED_MASK                                                               0x00001000L
30782 #define RLC_GPU_IOV_SDMA1_STATUS__RESERVED2_MASK                                                              0xFFFFE000L
30783 //RLC_GPU_IOV_SMU_RESPONSE
30784 #define RLC_GPU_IOV_SMU_RESPONSE__RESP__SHIFT                                                                 0x0
30785 #define RLC_GPU_IOV_SMU_RESPONSE__RESP_MASK                                                                   0xFFFFFFFFL
30786 //RLC_GPU_IOV_VIRT_RESET_REQ
30787 #define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR__SHIFT                                                             0x0
30788 #define RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED__SHIFT                                                           0x10
30789 #define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR__SHIFT                                                        0x1f
30790 #define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR_MASK                                                               0x0000FFFFL
30791 #define RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED_MASK                                                             0x7FFF0000L
30792 #define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR_MASK                                                          0x80000000L
30793 //RLC_GPU_IOV_RLC_RESPONSE
30794 #define RLC_GPU_IOV_RLC_RESPONSE__RESP__SHIFT                                                                 0x0
30795 #define RLC_GPU_IOV_RLC_RESPONSE__RESP_MASK                                                                   0xFFFFFFFFL
30796 //RLC_GPU_IOV_INT_DISABLE
30797 #define RLC_GPU_IOV_INT_DISABLE__DISABLE__SHIFT                                                               0x0
30798 #define RLC_GPU_IOV_INT_DISABLE__DISABLE_MASK                                                                 0xFFFFFFFFL
30799 //RLC_GPU_IOV_INT_FORCE
30800 #define RLC_GPU_IOV_INT_FORCE__FORCE__SHIFT                                                                   0x0
30801 #define RLC_GPU_IOV_INT_FORCE__FORCE_MASK                                                                     0xFFFFFFFFL
30802 //RLC_GPU_IOV_SDMA0_BUSY_STATUS
30803 #define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS__SHIFT                                                  0x0
30804 #define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS_MASK                                                    0xFFFFFFFFL
30805 //RLC_GPU_IOV_SDMA1_BUSY_STATUS
30806 #define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS__SHIFT                                                  0x0
30807 #define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS_MASK                                                    0xFFFFFFFFL
30808 //RLC_HYP_SEMAPHORE_2
30809 #define RLC_HYP_SEMAPHORE_2__CLIENT_ID__SHIFT                                                                 0x0
30810 #define RLC_HYP_SEMAPHORE_2__RESERVED__SHIFT                                                                  0x5
30811 #define RLC_HYP_SEMAPHORE_2__CLIENT_ID_MASK                                                                   0x0000001FL
30812 #define RLC_HYP_SEMAPHORE_2__RESERVED_MASK                                                                    0xFFFFFFE0L
30813 //RLC_HYP_SEMAPHORE_3
30814 #define RLC_HYP_SEMAPHORE_3__CLIENT_ID__SHIFT                                                                 0x0
30815 #define RLC_HYP_SEMAPHORE_3__RESERVED__SHIFT                                                                  0x5
30816 #define RLC_HYP_SEMAPHORE_3__CLIENT_ID_MASK                                                                   0x0000001FL
30817 #define RLC_HYP_SEMAPHORE_3__RESERVED_MASK                                                                    0xFFFFFFE0L
30818 //RLC_GPU_IOV_SDMA2_STATUS
30819 #define RLC_GPU_IOV_SDMA2_STATUS__PREEMPTED__SHIFT                                                            0x0
30820 #define RLC_GPU_IOV_SDMA2_STATUS__RESERVED__SHIFT                                                             0x1
30821 #define RLC_GPU_IOV_SDMA2_STATUS__SAVED__SHIFT                                                                0x8
30822 #define RLC_GPU_IOV_SDMA2_STATUS__RESERVED1__SHIFT                                                            0x9
30823 #define RLC_GPU_IOV_SDMA2_STATUS__RESTORED__SHIFT                                                             0xc
30824 #define RLC_GPU_IOV_SDMA2_STATUS__RESERVED2__SHIFT                                                            0xd
30825 #define RLC_GPU_IOV_SDMA2_STATUS__PREEMPTED_MASK                                                              0x00000001L
30826 #define RLC_GPU_IOV_SDMA2_STATUS__RESERVED_MASK                                                               0x000000FEL
30827 #define RLC_GPU_IOV_SDMA2_STATUS__SAVED_MASK                                                                  0x00000100L
30828 #define RLC_GPU_IOV_SDMA2_STATUS__RESERVED1_MASK                                                              0x00000E00L
30829 #define RLC_GPU_IOV_SDMA2_STATUS__RESTORED_MASK                                                               0x00001000L
30830 #define RLC_GPU_IOV_SDMA2_STATUS__RESERVED2_MASK                                                              0xFFFFE000L
30831 //RLC_GPU_IOV_SDMA3_STATUS
30832 #define RLC_GPU_IOV_SDMA3_STATUS__PREEMPTED__SHIFT                                                            0x0
30833 #define RLC_GPU_IOV_SDMA3_STATUS__RESERVED__SHIFT                                                             0x1
30834 #define RLC_GPU_IOV_SDMA3_STATUS__SAVED__SHIFT                                                                0x8
30835 #define RLC_GPU_IOV_SDMA3_STATUS__RESERVED1__SHIFT                                                            0x9
30836 #define RLC_GPU_IOV_SDMA3_STATUS__RESTORED__SHIFT                                                             0xc
30837 #define RLC_GPU_IOV_SDMA3_STATUS__RESERVED2__SHIFT                                                            0xd
30838 #define RLC_GPU_IOV_SDMA3_STATUS__PREEMPTED_MASK                                                              0x00000001L
30839 #define RLC_GPU_IOV_SDMA3_STATUS__RESERVED_MASK                                                               0x000000FEL
30840 #define RLC_GPU_IOV_SDMA3_STATUS__SAVED_MASK                                                                  0x00000100L
30841 #define RLC_GPU_IOV_SDMA3_STATUS__RESERVED1_MASK                                                              0x00000E00L
30842 #define RLC_GPU_IOV_SDMA3_STATUS__RESTORED_MASK                                                               0x00001000L
30843 #define RLC_GPU_IOV_SDMA3_STATUS__RESERVED2_MASK                                                              0xFFFFE000L
30844 //RLC_GPU_IOV_SDMA4_STATUS
30845 #define RLC_GPU_IOV_SDMA4_STATUS__PREEMPTED__SHIFT                                                            0x0
30846 #define RLC_GPU_IOV_SDMA4_STATUS__RESERVED__SHIFT                                                             0x1
30847 #define RLC_GPU_IOV_SDMA4_STATUS__SAVED__SHIFT                                                                0x8
30848 #define RLC_GPU_IOV_SDMA4_STATUS__RESERVED1__SHIFT                                                            0x9
30849 #define RLC_GPU_IOV_SDMA4_STATUS__RESTORED__SHIFT                                                             0xc
30850 #define RLC_GPU_IOV_SDMA4_STATUS__RESERVED2__SHIFT                                                            0xd
30851 #define RLC_GPU_IOV_SDMA4_STATUS__PREEMPTED_MASK                                                              0x00000001L
30852 #define RLC_GPU_IOV_SDMA4_STATUS__RESERVED_MASK                                                               0x000000FEL
30853 #define RLC_GPU_IOV_SDMA4_STATUS__SAVED_MASK                                                                  0x00000100L
30854 #define RLC_GPU_IOV_SDMA4_STATUS__RESERVED1_MASK                                                              0x00000E00L
30855 #define RLC_GPU_IOV_SDMA4_STATUS__RESTORED_MASK                                                               0x00001000L
30856 #define RLC_GPU_IOV_SDMA4_STATUS__RESERVED2_MASK                                                              0xFFFFE000L
30857 //RLC_GPU_IOV_SDMA5_STATUS
30858 #define RLC_GPU_IOV_SDMA5_STATUS__PREEMPTED__SHIFT                                                            0x0
30859 #define RLC_GPU_IOV_SDMA5_STATUS__RESERVED__SHIFT                                                             0x1
30860 #define RLC_GPU_IOV_SDMA5_STATUS__SAVED__SHIFT                                                                0x8
30861 #define RLC_GPU_IOV_SDMA5_STATUS__RESERVED1__SHIFT                                                            0x9
30862 #define RLC_GPU_IOV_SDMA5_STATUS__RESTORED__SHIFT                                                             0xc
30863 #define RLC_GPU_IOV_SDMA5_STATUS__RESERVED2__SHIFT                                                            0xd
30864 #define RLC_GPU_IOV_SDMA5_STATUS__PREEMPTED_MASK                                                              0x00000001L
30865 #define RLC_GPU_IOV_SDMA5_STATUS__RESERVED_MASK                                                               0x000000FEL
30866 #define RLC_GPU_IOV_SDMA5_STATUS__SAVED_MASK                                                                  0x00000100L
30867 #define RLC_GPU_IOV_SDMA5_STATUS__RESERVED1_MASK                                                              0x00000E00L
30868 #define RLC_GPU_IOV_SDMA5_STATUS__RESTORED_MASK                                                               0x00001000L
30869 #define RLC_GPU_IOV_SDMA5_STATUS__RESERVED2_MASK                                                              0xFFFFE000L
30870 //RLC_GPU_IOV_SDMA6_STATUS
30871 #define RLC_GPU_IOV_SDMA6_STATUS__PREEMPTED__SHIFT                                                            0x0
30872 #define RLC_GPU_IOV_SDMA6_STATUS__RESERVED__SHIFT                                                             0x1
30873 #define RLC_GPU_IOV_SDMA6_STATUS__SAVED__SHIFT                                                                0x8
30874 #define RLC_GPU_IOV_SDMA6_STATUS__RESERVED1__SHIFT                                                            0x9
30875 #define RLC_GPU_IOV_SDMA6_STATUS__RESTORED__SHIFT                                                             0xc
30876 #define RLC_GPU_IOV_SDMA6_STATUS__RESERVED2__SHIFT                                                            0xd
30877 #define RLC_GPU_IOV_SDMA6_STATUS__PREEMPTED_MASK                                                              0x00000001L
30878 #define RLC_GPU_IOV_SDMA6_STATUS__RESERVED_MASK                                                               0x000000FEL
30879 #define RLC_GPU_IOV_SDMA6_STATUS__SAVED_MASK                                                                  0x00000100L
30880 #define RLC_GPU_IOV_SDMA6_STATUS__RESERVED1_MASK                                                              0x00000E00L
30881 #define RLC_GPU_IOV_SDMA6_STATUS__RESTORED_MASK                                                               0x00001000L
30882 #define RLC_GPU_IOV_SDMA6_STATUS__RESERVED2_MASK                                                              0xFFFFE000L
30883 //RLC_GPU_IOV_SDMA7_STATUS
30884 #define RLC_GPU_IOV_SDMA7_STATUS__PREEMPTED__SHIFT                                                            0x0
30885 #define RLC_GPU_IOV_SDMA7_STATUS__RESERVED__SHIFT                                                             0x1
30886 #define RLC_GPU_IOV_SDMA7_STATUS__SAVED__SHIFT                                                                0x8
30887 #define RLC_GPU_IOV_SDMA7_STATUS__RESERVED1__SHIFT                                                            0x9
30888 #define RLC_GPU_IOV_SDMA7_STATUS__RESTORED__SHIFT                                                             0xc
30889 #define RLC_GPU_IOV_SDMA7_STATUS__RESERVED2__SHIFT                                                            0xd
30890 #define RLC_GPU_IOV_SDMA7_STATUS__PREEMPTED_MASK                                                              0x00000001L
30891 #define RLC_GPU_IOV_SDMA7_STATUS__RESERVED_MASK                                                               0x000000FEL
30892 #define RLC_GPU_IOV_SDMA7_STATUS__SAVED_MASK                                                                  0x00000100L
30893 #define RLC_GPU_IOV_SDMA7_STATUS__RESERVED1_MASK                                                              0x00000E00L
30894 #define RLC_GPU_IOV_SDMA7_STATUS__RESTORED_MASK                                                               0x00001000L
30895 #define RLC_GPU_IOV_SDMA7_STATUS__RESERVED2_MASK                                                              0xFFFFE000L
30896 //RLC_GPU_IOV_SDMA2_BUSY_STATUS
30897 #define RLC_GPU_IOV_SDMA2_BUSY_STATUS__VM_BUSY_STATUS__SHIFT                                                  0x0
30898 #define RLC_GPU_IOV_SDMA2_BUSY_STATUS__VM_BUSY_STATUS_MASK                                                    0xFFFFFFFFL
30899 //RLC_GPU_IOV_SDMA3_BUSY_STATUS
30900 #define RLC_GPU_IOV_SDMA3_BUSY_STATUS__VM_BUSY_STATUS__SHIFT                                                  0x0
30901 #define RLC_GPU_IOV_SDMA3_BUSY_STATUS__VM_BUSY_STATUS_MASK                                                    0xFFFFFFFFL
30902 //RLC_GPU_IOV_SDMA4_BUSY_STATUS
30903 #define RLC_GPU_IOV_SDMA4_BUSY_STATUS__VM_BUSY_STATUS__SHIFT                                                  0x0
30904 #define RLC_GPU_IOV_SDMA4_BUSY_STATUS__VM_BUSY_STATUS_MASK                                                    0xFFFFFFFFL
30905 //RLC_GPU_IOV_SDMA5_BUSY_STATUS
30906 #define RLC_GPU_IOV_SDMA5_BUSY_STATUS__VM_BUSY_STATUS__SHIFT                                                  0x0
30907 #define RLC_GPU_IOV_SDMA5_BUSY_STATUS__VM_BUSY_STATUS_MASK                                                    0xFFFFFFFFL
30908 //RLC_GPU_IOV_SDMA6_BUSY_STATUS
30909 #define RLC_GPU_IOV_SDMA6_BUSY_STATUS__VM_BUSY_STATUS__SHIFT                                                  0x0
30910 #define RLC_GPU_IOV_SDMA6_BUSY_STATUS__VM_BUSY_STATUS_MASK                                                    0xFFFFFFFFL
30911 //RLC_GPU_IOV_SDMA7_BUSY_STATUS
30912 #define RLC_GPU_IOV_SDMA7_BUSY_STATUS__VM_BUSY_STATUS__SHIFT                                                  0x0
30913 #define RLC_GPU_IOV_SDMA7_BUSY_STATUS__VM_BUSY_STATUS_MASK                                                    0xFFFFFFFFL
30914 
30915 
30916 // addressBlock: xcd0_gc_utcl2_vmsharedhvdec
30917 //MC_VM_FB_SIZE_OFFSET_VF0
30918 #define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT                                                           0x0
30919 #define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT                                                         0x10
30920 #define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK                                                             0x0000FFFFL
30921 #define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK                                                           0xFFFF0000L
30922 //MC_VM_FB_SIZE_OFFSET_VF1
30923 #define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT                                                           0x0
30924 #define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT                                                         0x10
30925 #define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK                                                             0x0000FFFFL
30926 #define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK                                                           0xFFFF0000L
30927 //MC_VM_FB_SIZE_OFFSET_VF2
30928 #define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT                                                           0x0
30929 #define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT                                                         0x10
30930 #define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK                                                             0x0000FFFFL
30931 #define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK                                                           0xFFFF0000L
30932 //MC_VM_FB_SIZE_OFFSET_VF3
30933 #define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT                                                           0x0
30934 #define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT                                                         0x10
30935 #define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK                                                             0x0000FFFFL
30936 #define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK                                                           0xFFFF0000L
30937 //MC_VM_FB_SIZE_OFFSET_VF4
30938 #define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT                                                           0x0
30939 #define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT                                                         0x10
30940 #define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK                                                             0x0000FFFFL
30941 #define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK                                                           0xFFFF0000L
30942 //MC_VM_FB_SIZE_OFFSET_VF5
30943 #define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT                                                           0x0
30944 #define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT                                                         0x10
30945 #define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK                                                             0x0000FFFFL
30946 #define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK                                                           0xFFFF0000L
30947 //MC_VM_FB_SIZE_OFFSET_VF6
30948 #define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT                                                           0x0
30949 #define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT                                                         0x10
30950 #define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK                                                             0x0000FFFFL
30951 #define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK                                                           0xFFFF0000L
30952 //MC_VM_FB_SIZE_OFFSET_VF7
30953 #define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT                                                           0x0
30954 #define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT                                                         0x10
30955 #define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK                                                             0x0000FFFFL
30956 #define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK                                                           0xFFFF0000L
30957 //MC_VM_FB_SIZE_OFFSET_VF8
30958 #define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT                                                           0x0
30959 #define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT                                                         0x10
30960 #define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK                                                             0x0000FFFFL
30961 #define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK                                                           0xFFFF0000L
30962 //MC_VM_FB_SIZE_OFFSET_VF9
30963 #define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT                                                           0x0
30964 #define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT                                                         0x10
30965 #define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK                                                             0x0000FFFFL
30966 #define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK                                                           0xFFFF0000L
30967 //MC_VM_FB_SIZE_OFFSET_VF10
30968 #define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT                                                          0x0
30969 #define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT                                                        0x10
30970 #define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK                                                            0x0000FFFFL
30971 #define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK                                                          0xFFFF0000L
30972 //MC_VM_FB_SIZE_OFFSET_VF11
30973 #define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT                                                          0x0
30974 #define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT                                                        0x10
30975 #define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK                                                            0x0000FFFFL
30976 #define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK                                                          0xFFFF0000L
30977 //MC_VM_FB_SIZE_OFFSET_VF12
30978 #define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT                                                          0x0
30979 #define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT                                                        0x10
30980 #define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK                                                            0x0000FFFFL
30981 #define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK                                                          0xFFFF0000L
30982 //MC_VM_FB_SIZE_OFFSET_VF13
30983 #define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT                                                          0x0
30984 #define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT                                                        0x10
30985 #define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK                                                            0x0000FFFFL
30986 #define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK                                                          0xFFFF0000L
30987 //MC_VM_FB_SIZE_OFFSET_VF14
30988 #define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT                                                          0x0
30989 #define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT                                                        0x10
30990 #define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK                                                            0x0000FFFFL
30991 #define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK                                                          0xFFFF0000L
30992 //MC_VM_FB_SIZE_OFFSET_VF15
30993 #define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT                                                          0x0
30994 #define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT                                                        0x10
30995 #define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK                                                            0x0000FFFFL
30996 #define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK                                                          0xFFFF0000L
30997 //VM_IOMMU_MMIO_CNTRL_1
30998 #define VM_IOMMU_MMIO_CNTRL_1__MARC_EN__SHIFT                                                                 0x8
30999 #define VM_IOMMU_MMIO_CNTRL_1__MARC_EN_MASK                                                                   0x00000100L
31000 //MC_VM_MARC_BASE_LO_0
31001 #define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT                                                           0xc
31002 #define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK                                                             0xFFFFF000L
31003 //MC_VM_MARC_BASE_LO_1
31004 #define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT                                                           0xc
31005 #define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK                                                             0xFFFFF000L
31006 //MC_VM_MARC_BASE_LO_2
31007 #define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT                                                           0xc
31008 #define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK                                                             0xFFFFF000L
31009 //MC_VM_MARC_BASE_LO_3
31010 #define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT                                                           0xc
31011 #define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK                                                             0xFFFFF000L
31012 //MC_VM_MARC_BASE_HI_0
31013 #define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT                                                           0x0
31014 #define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK                                                             0x000FFFFFL
31015 //MC_VM_MARC_BASE_HI_1
31016 #define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT                                                           0x0
31017 #define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK                                                             0x000FFFFFL
31018 //MC_VM_MARC_BASE_HI_2
31019 #define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT                                                           0x0
31020 #define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK                                                             0x000FFFFFL
31021 //MC_VM_MARC_BASE_HI_3
31022 #define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT                                                           0x0
31023 #define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK                                                             0x000FFFFFL
31024 //MC_VM_MARC_RELOC_LO_0
31025 #define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT                                                           0x0
31026 #define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT                                                         0x1
31027 #define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT                                                         0xc
31028 #define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK                                                             0x00000001L
31029 #define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK                                                           0x00000002L
31030 #define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK                                                           0xFFFFF000L
31031 //MC_VM_MARC_RELOC_LO_1
31032 #define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT                                                           0x0
31033 #define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT                                                         0x1
31034 #define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT                                                         0xc
31035 #define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK                                                             0x00000001L
31036 #define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK                                                           0x00000002L
31037 #define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK                                                           0xFFFFF000L
31038 //MC_VM_MARC_RELOC_LO_2
31039 #define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT                                                           0x0
31040 #define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT                                                         0x1
31041 #define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT                                                         0xc
31042 #define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK                                                             0x00000001L
31043 #define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK                                                           0x00000002L
31044 #define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK                                                           0xFFFFF000L
31045 //MC_VM_MARC_RELOC_LO_3
31046 #define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT                                                           0x0
31047 #define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT                                                         0x1
31048 #define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT                                                         0xc
31049 #define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK                                                             0x00000001L
31050 #define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK                                                           0x00000002L
31051 #define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK                                                           0xFFFFF000L
31052 //MC_VM_MARC_RELOC_HI_0
31053 #define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT                                                         0x0
31054 #define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK                                                           0x000FFFFFL
31055 //MC_VM_MARC_RELOC_HI_1
31056 #define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT                                                         0x0
31057 #define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK                                                           0x000FFFFFL
31058 //MC_VM_MARC_RELOC_HI_2
31059 #define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT                                                         0x0
31060 #define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK                                                           0x000FFFFFL
31061 //MC_VM_MARC_RELOC_HI_3
31062 #define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT                                                         0x0
31063 #define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK                                                           0x000FFFFFL
31064 //MC_VM_MARC_LEN_LO_0
31065 #define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT                                                             0xc
31066 #define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK                                                               0xFFFFF000L
31067 //MC_VM_MARC_LEN_LO_1
31068 #define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT                                                             0xc
31069 #define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK                                                               0xFFFFF000L
31070 //MC_VM_MARC_LEN_LO_2
31071 #define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT                                                             0xc
31072 #define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK                                                               0xFFFFF000L
31073 //MC_VM_MARC_LEN_LO_3
31074 #define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT                                                             0xc
31075 #define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK                                                               0xFFFFF000L
31076 //MC_VM_MARC_LEN_HI_0
31077 #define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT                                                             0x0
31078 #define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK                                                               0x000FFFFFL
31079 //MC_VM_MARC_LEN_HI_1
31080 #define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT                                                             0x0
31081 #define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK                                                               0x000FFFFFL
31082 //MC_VM_MARC_LEN_HI_2
31083 #define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT                                                             0x0
31084 #define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK                                                               0x000FFFFFL
31085 //MC_VM_MARC_LEN_HI_3
31086 #define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT                                                             0x0
31087 #define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK                                                               0x000FFFFFL
31088 //VM_IOMMU_CONTROL_REGISTER
31089 #define VM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT                                                             0x0
31090 #define VM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK                                                               0x00000001L
31091 //VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER
31092 #define VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT                                  0xd
31093 #define VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK                                    0x00002000L
31094 //VM_PCIE_ATS_CNTL
31095 #define VM_PCIE_ATS_CNTL__STU__SHIFT                                                                          0x10
31096 #define VM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                                                   0x1f
31097 #define VM_PCIE_ATS_CNTL__STU_MASK                                                                            0x001F0000L
31098 #define VM_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                                                     0x80000000L
31099 //VM_PCIE_ATS_CNTL_VF_0
31100 #define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT                                                              0x1f
31101 #define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK                                                                0x80000000L
31102 //VM_PCIE_ATS_CNTL_VF_1
31103 #define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT                                                              0x1f
31104 #define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK                                                                0x80000000L
31105 //VM_PCIE_ATS_CNTL_VF_2
31106 #define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT                                                              0x1f
31107 #define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK                                                                0x80000000L
31108 //VM_PCIE_ATS_CNTL_VF_3
31109 #define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT                                                              0x1f
31110 #define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK                                                                0x80000000L
31111 //VM_PCIE_ATS_CNTL_VF_4
31112 #define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT                                                              0x1f
31113 #define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK                                                                0x80000000L
31114 //VM_PCIE_ATS_CNTL_VF_5
31115 #define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT                                                              0x1f
31116 #define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK                                                                0x80000000L
31117 //VM_PCIE_ATS_CNTL_VF_6
31118 #define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT                                                              0x1f
31119 #define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK                                                                0x80000000L
31120 //VM_PCIE_ATS_CNTL_VF_7
31121 #define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT                                                              0x1f
31122 #define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK                                                                0x80000000L
31123 //VM_PCIE_ATS_CNTL_VF_8
31124 #define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT                                                              0x1f
31125 #define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK                                                                0x80000000L
31126 //VM_PCIE_ATS_CNTL_VF_9
31127 #define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT                                                              0x1f
31128 #define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK                                                                0x80000000L
31129 //VM_PCIE_ATS_CNTL_VF_10
31130 #define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT                                                             0x1f
31131 #define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK                                                               0x80000000L
31132 //VM_PCIE_ATS_CNTL_VF_11
31133 #define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT                                                             0x1f
31134 #define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK                                                               0x80000000L
31135 //VM_PCIE_ATS_CNTL_VF_12
31136 #define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT                                                             0x1f
31137 #define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK                                                               0x80000000L
31138 //VM_PCIE_ATS_CNTL_VF_13
31139 #define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT                                                             0x1f
31140 #define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK                                                               0x80000000L
31141 //VM_PCIE_ATS_CNTL_VF_14
31142 #define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT                                                             0x1f
31143 #define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK                                                               0x80000000L
31144 //VM_PCIE_ATS_CNTL_VF_15
31145 #define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT                                                             0x1f
31146 #define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK                                                               0x80000000L
31147 //MC_SHARED_ACTIVE_FCN_ID
31148 #define MC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT                                                                  0x0
31149 #define MC_SHARED_ACTIVE_FCN_ID__VF__SHIFT                                                                    0x1f
31150 #define MC_SHARED_ACTIVE_FCN_ID__VFID_MASK                                                                    0x0000000FL
31151 #define MC_SHARED_ACTIVE_FCN_ID__VF_MASK                                                                      0x80000000L
31152 //MC_VM_XGMI_GPUIOV_ENABLE
31153 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0__SHIFT                                                           0x0
31154 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1__SHIFT                                                           0x1
31155 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2__SHIFT                                                           0x2
31156 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3__SHIFT                                                           0x3
31157 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4__SHIFT                                                           0x4
31158 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5__SHIFT                                                           0x5
31159 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6__SHIFT                                                           0x6
31160 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7__SHIFT                                                           0x7
31161 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF8__SHIFT                                                           0x8
31162 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF9__SHIFT                                                           0x9
31163 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF10__SHIFT                                                          0xa
31164 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF11__SHIFT                                                          0xb
31165 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF12__SHIFT                                                          0xc
31166 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF13__SHIFT                                                          0xd
31167 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF14__SHIFT                                                          0xe
31168 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF15__SHIFT                                                          0xf
31169 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF__SHIFT                                                            0x1f
31170 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0_MASK                                                             0x00000001L
31171 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1_MASK                                                             0x00000002L
31172 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2_MASK                                                             0x00000004L
31173 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3_MASK                                                             0x00000008L
31174 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4_MASK                                                             0x00000010L
31175 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5_MASK                                                             0x00000020L
31176 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6_MASK                                                             0x00000040L
31177 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7_MASK                                                             0x00000080L
31178 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF8_MASK                                                             0x00000100L
31179 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF9_MASK                                                             0x00000200L
31180 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF10_MASK                                                            0x00000400L
31181 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF11_MASK                                                            0x00000800L
31182 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF12_MASK                                                            0x00001000L
31183 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF13_MASK                                                            0x00002000L
31184 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF14_MASK                                                            0x00004000L
31185 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF15_MASK                                                            0x00008000L
31186 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF_MASK                                                              0x80000000L
31187 
31188 
31189 // addressBlock: xcd0_gc_pspdec
31190 //CPG_PSP_DEBUG
31191 #define CPG_PSP_DEBUG__PRIV_VIOLATION_CNTL__SHIFT                                                             0x0
31192 #define CPG_PSP_DEBUG__VMID_VIOLATION_CNTL__SHIFT                                                             0x2
31193 #define CPG_PSP_DEBUG__PRIV_VIOLATION_CNTL_MASK                                                               0x00000003L
31194 #define CPG_PSP_DEBUG__VMID_VIOLATION_CNTL_MASK                                                               0x00000004L
31195 //CPC_PSP_DEBUG
31196 #define CPC_PSP_DEBUG__PRIV_VIOLATION_CNTL__SHIFT                                                             0x0
31197 #define CPC_PSP_DEBUG__VMID_VIOLATION_CNTL__SHIFT                                                             0x2
31198 #define CPC_PSP_DEBUG__UTCL2IUGPAOVERRIDE__SHIFT                                                              0x3
31199 #define CPC_PSP_DEBUG__CPC_DC_FIX_DISABLE__SHIFT                                                              0x4
31200 #define CPC_PSP_DEBUG__PRIV_VIOLATION_CNTL_MASK                                                               0x00000003L
31201 #define CPC_PSP_DEBUG__VMID_VIOLATION_CNTL_MASK                                                               0x00000004L
31202 #define CPC_PSP_DEBUG__UTCL2IUGPAOVERRIDE_MASK                                                                0x00000008L
31203 #define CPC_PSP_DEBUG__CPC_DC_FIX_DISABLE_MASK                                                                0x00000010L
31204 //CP_PSP_XCP_CTL
31205 #define CP_PSP_XCP_CTL__PHYSICAL_XCC_ID__SHIFT                                                                0x0
31206 #define CP_PSP_XCP_CTL__XCC_DIE_ID__SHIFT                                                                     0x3
31207 #define CP_PSP_XCP_CTL__PHYSICAL_XCC_ID_MASK                                                                  0x00000007L
31208 #define CP_PSP_XCP_CTL__XCC_DIE_ID_MASK                                                                       0x00000038L
31209 //GRBM_SEC_CNTL
31210 #define GRBM_SEC_CNTL__DEBUG_ENABLE__SHIFT                                                                    0x0
31211 #define GRBM_SEC_CNTL__DEBUG_ENABLE_MASK                                                                      0x00000001L
31212 //GRBM_IOV_ERROR_FIFO_DATA
31213 #define GRBM_IOV_ERROR_FIFO_DATA__IOV_ADDR__SHIFT                                                             0x0
31214 #define GRBM_IOV_ERROR_FIFO_DATA__IOV_VFID__SHIFT                                                             0x12
31215 #define GRBM_IOV_ERROR_FIFO_DATA__IOV_SSRCID__SHIFT                                                           0x18
31216 #define GRBM_IOV_ERROR_FIFO_DATA__IOV_OP__SHIFT                                                               0x1c
31217 #define GRBM_IOV_ERROR_FIFO_DATA__IOV_VF__SHIFT                                                               0x1d
31218 #define GRBM_IOV_ERROR_FIFO_DATA__IOV_OVERFLOW__SHIFT                                                         0x1e
31219 #define GRBM_IOV_ERROR_FIFO_DATA__IOV_READ_VALID__SHIFT                                                       0x1f
31220 #define GRBM_IOV_ERROR_FIFO_DATA__IOV_ADDR_MASK                                                               0x0003FFFFL
31221 #define GRBM_IOV_ERROR_FIFO_DATA__IOV_VFID_MASK                                                               0x00FC0000L
31222 #define GRBM_IOV_ERROR_FIFO_DATA__IOV_SSRCID_MASK                                                             0x0F000000L
31223 #define GRBM_IOV_ERROR_FIFO_DATA__IOV_OP_MASK                                                                 0x10000000L
31224 #define GRBM_IOV_ERROR_FIFO_DATA__IOV_VF_MASK                                                                 0x20000000L
31225 #define GRBM_IOV_ERROR_FIFO_DATA__IOV_OVERFLOW_MASK                                                           0x40000000L
31226 #define GRBM_IOV_ERROR_FIFO_DATA__IOV_READ_VALID_MASK                                                         0x80000000L
31227 //GRBM_DSM_BYPASS
31228 #define GRBM_DSM_BYPASS__BYPASS_BITS__SHIFT                                                                   0x0
31229 #define GRBM_DSM_BYPASS__BYPASS_EN__SHIFT                                                                     0x2
31230 #define GRBM_DSM_BYPASS__BYPASS_BITS_MASK                                                                     0x00000003L
31231 #define GRBM_DSM_BYPASS__BYPASS_EN_MASK                                                                       0x00000004L
31232 //GRBM_CAM_INDEX
31233 #define GRBM_CAM_INDEX__CAM_INDEX__SHIFT                                                                      0x0
31234 #define GRBM_CAM_INDEX__CAM_INDEX_MASK                                                                        0x00000007L
31235 //GRBM_HYP_CAM_INDEX
31236 #define GRBM_HYP_CAM_INDEX__CAM_INDEX__SHIFT                                                                  0x0
31237 #define GRBM_HYP_CAM_INDEX__CAM_INDEX_MASK                                                                    0x00000007L
31238 //GRBM_CAM_DATA
31239 #define GRBM_CAM_DATA__CAM_ADDR__SHIFT                                                                        0x0
31240 #define GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT                                                                   0x10
31241 #define GRBM_CAM_DATA__CAM_ADDR_MASK                                                                          0x0000FFFFL
31242 #define GRBM_CAM_DATA__CAM_REMAPADDR_MASK                                                                     0xFFFF0000L
31243 //GRBM_HYP_CAM_DATA
31244 #define GRBM_HYP_CAM_DATA__CAM_ADDR__SHIFT                                                                    0x0
31245 #define GRBM_HYP_CAM_DATA__CAM_REMAPADDR__SHIFT                                                               0x10
31246 #define GRBM_HYP_CAM_DATA__CAM_ADDR_MASK                                                                      0x0000FFFFL
31247 #define GRBM_HYP_CAM_DATA__CAM_REMAPADDR_MASK                                                                 0xFFFF0000L
31248 //RLC_FWL_FIRST_VIOL_ADDR
31249 #define RLC_FWL_FIRST_VIOL_ADDR__VIOL_STATUS__SHIFT                                                           0x0
31250 #define RLC_FWL_FIRST_VIOL_ADDR__VIOL_OP__SHIFT                                                               0x1
31251 #define RLC_FWL_FIRST_VIOL_ADDR__VIOL_ADDR__SHIFT                                                             0x2
31252 #define RLC_FWL_FIRST_VIOL_ADDR__VIOL_APERTURE_ID__SHIFT                                                      0x14
31253 #define RLC_FWL_FIRST_VIOL_ADDR__VIOL_STATUS_MASK                                                             0x00000001L
31254 #define RLC_FWL_FIRST_VIOL_ADDR__VIOL_OP_MASK                                                                 0x00000002L
31255 #define RLC_FWL_FIRST_VIOL_ADDR__VIOL_ADDR_MASK                                                               0x000FFFFCL
31256 #define RLC_FWL_FIRST_VIOL_ADDR__VIOL_APERTURE_ID_MASK                                                        0xFFF00000L
31257 
31258 
31259 // addressBlock: sqind
31260 //SQ_DEBUG_STS_LOCAL
31261 #define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT                                                                       0x0
31262 #define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL__SHIFT                                                                 0x4
31263 #define SQ_DEBUG_STS_LOCAL__BUSY_MASK                                                                         0x00000001L
31264 #define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL_MASK                                                                   0x000003F0L
31265 //SQ_DEBUG_CTRL_LOCAL
31266 #define SQ_DEBUG_CTRL_LOCAL__UNUSED__SHIFT                                                                    0x0
31267 #define SQ_DEBUG_CTRL_LOCAL__PERF_SEL_INSTS_VALU_MFMA_NON_WAVE__SHIFT                                         0x8
31268 #define SQ_DEBUG_CTRL_LOCAL__PERF_SEL_INSTS_VALU_MFMA_MOPS_NON_WAVE__SHIFT                                    0x9
31269 #define SQ_DEBUG_CTRL_LOCAL__UNUSED_MASK                                                                      0x000000FFL
31270 #define SQ_DEBUG_CTRL_LOCAL__PERF_SEL_INSTS_VALU_MFMA_NON_WAVE_MASK                                           0x00000100L
31271 #define SQ_DEBUG_CTRL_LOCAL__PERF_SEL_INSTS_VALU_MFMA_MOPS_NON_WAVE_MASK                                      0x00000200L
31272 //SQ_WAVE_VALID_AND_IDLE
31273 #define SQ_WAVE_VALID_AND_IDLE__WAVE_SLOT__SHIFT                                                              0x0
31274 #define SQ_WAVE_VALID_AND_IDLE__WAVE_SLOT_MASK                                                                0xFFFFFFFFL
31275 //SQ_PERF_SNAPSHOT_DATA
31276 //SQ_PERF_SNAPSHOT_DATA1
31277 //SQ_PERF_SNAPSHOT_PC_LO
31278 //SQ_PERF_SNAPSHOT_PC_HI
31279 //SQ_WAVE_MODE
31280 #define SQ_WAVE_MODE__FP_ROUND__SHIFT                                                                         0x0
31281 #define SQ_WAVE_MODE__FP_DENORM__SHIFT                                                                        0x4
31282 #define SQ_WAVE_MODE__DX10_CLAMP__SHIFT                                                                       0x8
31283 #define SQ_WAVE_MODE__IEEE__SHIFT                                                                             0x9
31284 #define SQ_WAVE_MODE__LOD_CLAMPED__SHIFT                                                                      0xa
31285 #define SQ_WAVE_MODE__DEBUG_EN__SHIFT                                                                         0xb
31286 #define SQ_WAVE_MODE__EXCP_EN__SHIFT                                                                          0xc
31287 #define SQ_WAVE_MODE__FP16_OVFL__SHIFT                                                                        0x17
31288 #define SQ_WAVE_MODE__POPS_PACKER0__SHIFT                                                                     0x18
31289 #define SQ_WAVE_MODE__POPS_PACKER1__SHIFT                                                                     0x19
31290 #define SQ_WAVE_MODE__DISABLE_PERF__SHIFT                                                                     0x1a
31291 #define SQ_WAVE_MODE__GPR_IDX_EN__SHIFT                                                                       0x1b
31292 #define SQ_WAVE_MODE__VSKIP__SHIFT                                                                            0x1c
31293 #define SQ_WAVE_MODE__CSP__SHIFT                                                                              0x1d
31294 #define SQ_WAVE_MODE__FP_ROUND_MASK                                                                           0x0000000FL
31295 #define SQ_WAVE_MODE__FP_DENORM_MASK                                                                          0x000000F0L
31296 #define SQ_WAVE_MODE__DX10_CLAMP_MASK                                                                         0x00000100L
31297 #define SQ_WAVE_MODE__IEEE_MASK                                                                               0x00000200L
31298 #define SQ_WAVE_MODE__LOD_CLAMPED_MASK                                                                        0x00000400L
31299 #define SQ_WAVE_MODE__DEBUG_EN_MASK                                                                           0x00000800L
31300 #define SQ_WAVE_MODE__EXCP_EN_MASK                                                                            0x001FF000L
31301 #define SQ_WAVE_MODE__FP16_OVFL_MASK                                                                          0x00800000L
31302 #define SQ_WAVE_MODE__POPS_PACKER0_MASK                                                                       0x01000000L
31303 #define SQ_WAVE_MODE__POPS_PACKER1_MASK                                                                       0x02000000L
31304 #define SQ_WAVE_MODE__DISABLE_PERF_MASK                                                                       0x04000000L
31305 #define SQ_WAVE_MODE__GPR_IDX_EN_MASK                                                                         0x08000000L
31306 #define SQ_WAVE_MODE__VSKIP_MASK                                                                              0x10000000L
31307 #define SQ_WAVE_MODE__CSP_MASK                                                                                0xE0000000L
31308 //SQ_WAVE_STATUS
31309 #define SQ_WAVE_STATUS__SCC__SHIFT                                                                            0x0
31310 #define SQ_WAVE_STATUS__SPI_PRIO__SHIFT                                                                       0x1
31311 #define SQ_WAVE_STATUS__USER_PRIO__SHIFT                                                                      0x3
31312 #define SQ_WAVE_STATUS__PRIV__SHIFT                                                                           0x5
31313 #define SQ_WAVE_STATUS__TRAP_EN__SHIFT                                                                        0x6
31314 #define SQ_WAVE_STATUS__TTRACE_EN__SHIFT                                                                      0x7
31315 #define SQ_WAVE_STATUS__EXPORT_RDY__SHIFT                                                                     0x8
31316 #define SQ_WAVE_STATUS__EXECZ__SHIFT                                                                          0x9
31317 #define SQ_WAVE_STATUS__VCCZ__SHIFT                                                                           0xa
31318 #define SQ_WAVE_STATUS__IN_TG__SHIFT                                                                          0xb
31319 #define SQ_WAVE_STATUS__IN_BARRIER__SHIFT                                                                     0xc
31320 #define SQ_WAVE_STATUS__HALT__SHIFT                                                                           0xd
31321 #define SQ_WAVE_STATUS__TRAP__SHIFT                                                                           0xe
31322 #define SQ_WAVE_STATUS__TTRACE_CU_EN__SHIFT                                                                   0xf
31323 #define SQ_WAVE_STATUS__VALID__SHIFT                                                                          0x10
31324 #define SQ_WAVE_STATUS__ECC_ERR__SHIFT                                                                        0x11
31325 #define SQ_WAVE_STATUS__SKIP_EXPORT__SHIFT                                                                    0x12
31326 #define SQ_WAVE_STATUS__PERF_EN__SHIFT                                                                        0x13
31327 #define SQ_WAVE_STATUS__COND_DBG_USER__SHIFT                                                                  0x14
31328 #define SQ_WAVE_STATUS__COND_DBG_SYS__SHIFT                                                                   0x15
31329 #define SQ_WAVE_STATUS__ALLOW_REPLAY__SHIFT                                                                   0x16
31330 #define SQ_WAVE_STATUS__FATAL_HALT__SHIFT                                                                     0x17
31331 #define SQ_WAVE_STATUS__MUST_EXPORT__SHIFT                                                                    0x1b
31332 #define SQ_WAVE_STATUS__SCRATCH_EN__SHIFT                                                                     0x1c
31333 #define SQ_WAVE_STATUS__IDLE__SHIFT                                                                           0x1f
31334 #define SQ_WAVE_STATUS__SCC_MASK                                                                              0x00000001L
31335 #define SQ_WAVE_STATUS__SPI_PRIO_MASK                                                                         0x00000006L
31336 #define SQ_WAVE_STATUS__USER_PRIO_MASK                                                                        0x00000018L
31337 #define SQ_WAVE_STATUS__PRIV_MASK                                                                             0x00000020L
31338 #define SQ_WAVE_STATUS__TRAP_EN_MASK                                                                          0x00000040L
31339 #define SQ_WAVE_STATUS__TTRACE_EN_MASK                                                                        0x00000080L
31340 #define SQ_WAVE_STATUS__EXPORT_RDY_MASK                                                                       0x00000100L
31341 #define SQ_WAVE_STATUS__EXECZ_MASK                                                                            0x00000200L
31342 #define SQ_WAVE_STATUS__VCCZ_MASK                                                                             0x00000400L
31343 #define SQ_WAVE_STATUS__IN_TG_MASK                                                                            0x00000800L
31344 #define SQ_WAVE_STATUS__IN_BARRIER_MASK                                                                       0x00001000L
31345 #define SQ_WAVE_STATUS__HALT_MASK                                                                             0x00002000L
31346 #define SQ_WAVE_STATUS__TRAP_MASK                                                                             0x00004000L
31347 #define SQ_WAVE_STATUS__TTRACE_CU_EN_MASK                                                                     0x00008000L
31348 #define SQ_WAVE_STATUS__VALID_MASK                                                                            0x00010000L
31349 #define SQ_WAVE_STATUS__ECC_ERR_MASK                                                                          0x00020000L
31350 #define SQ_WAVE_STATUS__SKIP_EXPORT_MASK                                                                      0x00040000L
31351 #define SQ_WAVE_STATUS__PERF_EN_MASK                                                                          0x00080000L
31352 #define SQ_WAVE_STATUS__COND_DBG_USER_MASK                                                                    0x00100000L
31353 #define SQ_WAVE_STATUS__COND_DBG_SYS_MASK                                                                     0x00200000L
31354 #define SQ_WAVE_STATUS__ALLOW_REPLAY_MASK                                                                     0x00400000L
31355 #define SQ_WAVE_STATUS__FATAL_HALT_MASK                                                                       0x00800000L
31356 #define SQ_WAVE_STATUS__MUST_EXPORT_MASK                                                                      0x08000000L
31357 #define SQ_WAVE_STATUS__SCRATCH_EN_MASK                                                                       0x10000000L
31358 #define SQ_WAVE_STATUS__IDLE_MASK                                                                             0x80000000L
31359 //SQ_WAVE_TRAPSTS
31360 #define SQ_WAVE_TRAPSTS__EXCP__SHIFT                                                                          0x0
31361 #define SQ_WAVE_TRAPSTS__SAVECTX__SHIFT                                                                       0xa
31362 #define SQ_WAVE_TRAPSTS__ILLEGAL_INST__SHIFT                                                                  0xb
31363 #define SQ_WAVE_TRAPSTS__EXCP_HI__SHIFT                                                                       0xc
31364 #define SQ_WAVE_TRAPSTS__EXCP_CYCLE__SHIFT                                                                    0x10
31365 #define SQ_WAVE_TRAPSTS__HOST_TRAP__SHIFT                                                                     0x16
31366 #define SQ_WAVE_TRAPSTS__WAVE_END__SHIFT                                                                      0x18
31367 #define SQ_WAVE_TRAPSTS__TRAP_AFTER_INST__SHIFT                                                               0x19
31368 #define SQ_WAVE_TRAPSTS__PERF_SNAPSHOT__SHIFT                                                                 0x1a
31369 #define SQ_WAVE_TRAPSTS__XNACK_ERROR__SHIFT                                                                   0x1c
31370 #define SQ_WAVE_TRAPSTS__DP_RATE__SHIFT                                                                       0x1d
31371 #define SQ_WAVE_TRAPSTS__EXCP_MASK                                                                            0x000001FFL
31372 #define SQ_WAVE_TRAPSTS__SAVECTX_MASK                                                                         0x00000400L
31373 #define SQ_WAVE_TRAPSTS__ILLEGAL_INST_MASK                                                                    0x00000800L
31374 #define SQ_WAVE_TRAPSTS__EXCP_HI_MASK                                                                         0x00007000L
31375 #define SQ_WAVE_TRAPSTS__EXCP_CYCLE_MASK                                                                      0x003F0000L
31376 #define SQ_WAVE_TRAPSTS__HOST_TRAP_MASK                                                                       0x00400000L
31377 #define SQ_WAVE_TRAPSTS__WAVE_END_MASK                                                                        0x01000000L
31378 #define SQ_WAVE_TRAPSTS__TRAP_AFTER_INST_MASK                                                                 0x02000000L
31379 #define SQ_WAVE_TRAPSTS__PERF_SNAPSHOT_MASK                                                                   0x04000000L
31380 #define SQ_WAVE_TRAPSTS__XNACK_ERROR_MASK                                                                     0x10000000L
31381 #define SQ_WAVE_TRAPSTS__DP_RATE_MASK                                                                         0xE0000000L
31382 //SQ_WAVE_HW_ID
31383 #define SQ_WAVE_HW_ID__WAVE_ID__SHIFT                                                                         0x0
31384 #define SQ_WAVE_HW_ID__SIMD_ID__SHIFT                                                                         0x4
31385 #define SQ_WAVE_HW_ID__PIPE_ID__SHIFT                                                                         0x6
31386 #define SQ_WAVE_HW_ID__CU_ID__SHIFT                                                                           0x8
31387 #define SQ_WAVE_HW_ID__SH_ID__SHIFT                                                                           0xc
31388 #define SQ_WAVE_HW_ID__SE_ID__SHIFT                                                                           0xd
31389 #define SQ_WAVE_HW_ID__TG_ID__SHIFT                                                                           0x10
31390 #define SQ_WAVE_HW_ID__VM_ID__SHIFT                                                                           0x14
31391 #define SQ_WAVE_HW_ID__QUEUE_ID__SHIFT                                                                        0x18
31392 #define SQ_WAVE_HW_ID__STATE_ID__SHIFT                                                                        0x1b
31393 #define SQ_WAVE_HW_ID__ME_ID__SHIFT                                                                           0x1e
31394 #define SQ_WAVE_HW_ID__WAVE_ID_MASK                                                                           0x0000000FL
31395 #define SQ_WAVE_HW_ID__SIMD_ID_MASK                                                                           0x00000030L
31396 #define SQ_WAVE_HW_ID__PIPE_ID_MASK                                                                           0x000000C0L
31397 #define SQ_WAVE_HW_ID__CU_ID_MASK                                                                             0x00000F00L
31398 #define SQ_WAVE_HW_ID__SH_ID_MASK                                                                             0x00001000L
31399 #define SQ_WAVE_HW_ID__SE_ID_MASK                                                                             0x0000E000L
31400 #define SQ_WAVE_HW_ID__TG_ID_MASK                                                                             0x000F0000L
31401 #define SQ_WAVE_HW_ID__VM_ID_MASK                                                                             0x00F00000L
31402 #define SQ_WAVE_HW_ID__QUEUE_ID_MASK                                                                          0x07000000L
31403 #define SQ_WAVE_HW_ID__STATE_ID_MASK                                                                          0x38000000L
31404 #define SQ_WAVE_HW_ID__ME_ID_MASK                                                                             0xC0000000L
31405 //SQ_WAVE_GPR_ALLOC
31406 #define SQ_WAVE_GPR_ALLOC__VGPR_BASE__SHIFT                                                                   0x0
31407 #define SQ_WAVE_GPR_ALLOC__VGPR_SIZE__SHIFT                                                                   0x6
31408 #define SQ_WAVE_GPR_ALLOC__ACCV_OFFSET__SHIFT                                                                 0xc
31409 #define SQ_WAVE_GPR_ALLOC__SGPR_BASE__SHIFT                                                                   0x12
31410 #define SQ_WAVE_GPR_ALLOC__SGPR_SIZE__SHIFT                                                                   0x18
31411 #define SQ_WAVE_GPR_ALLOC__VGPR_BASE_MASK                                                                     0x0000003FL
31412 #define SQ_WAVE_GPR_ALLOC__VGPR_SIZE_MASK                                                                     0x00000FC0L
31413 #define SQ_WAVE_GPR_ALLOC__ACCV_OFFSET_MASK                                                                   0x0003F000L
31414 #define SQ_WAVE_GPR_ALLOC__SGPR_BASE_MASK                                                                     0x00FC0000L
31415 #define SQ_WAVE_GPR_ALLOC__SGPR_SIZE_MASK                                                                     0x0F000000L
31416 //SQ_WAVE_LDS_ALLOC
31417 #define SQ_WAVE_LDS_ALLOC__LDS_BASE__SHIFT                                                                    0x0
31418 #define SQ_WAVE_LDS_ALLOC__LDS_SIZE__SHIFT                                                                    0xc
31419 #define SQ_WAVE_LDS_ALLOC__LDS_BASE_MASK                                                                      0x000000FFL
31420 #define SQ_WAVE_LDS_ALLOC__LDS_SIZE_MASK                                                                      0x001FF000L
31421 //SQ_WAVE_IB_STS
31422 #define SQ_WAVE_IB_STS__VM_CNT__SHIFT                                                                         0x0
31423 #define SQ_WAVE_IB_STS__EXP_CNT__SHIFT                                                                        0x4
31424 #define SQ_WAVE_IB_STS__LGKM_CNT__SHIFT                                                                       0x8
31425 #define SQ_WAVE_IB_STS__VALU_CNT__SHIFT                                                                       0xc
31426 #define SQ_WAVE_IB_STS__FIRST_REPLAY__SHIFT                                                                   0xf
31427 #define SQ_WAVE_IB_STS__RCNT__SHIFT                                                                           0x10
31428 #define SQ_WAVE_IB_STS__VM_CNT_HI__SHIFT                                                                      0x16
31429 #define SQ_WAVE_IB_STS__VM_CNT_MASK                                                                           0x0000000FL
31430 #define SQ_WAVE_IB_STS__EXP_CNT_MASK                                                                          0x00000070L
31431 #define SQ_WAVE_IB_STS__LGKM_CNT_MASK                                                                         0x00000F00L
31432 #define SQ_WAVE_IB_STS__VALU_CNT_MASK                                                                         0x00007000L
31433 #define SQ_WAVE_IB_STS__FIRST_REPLAY_MASK                                                                     0x00008000L
31434 #define SQ_WAVE_IB_STS__RCNT_MASK                                                                             0x001F0000L
31435 #define SQ_WAVE_IB_STS__VM_CNT_HI_MASK                                                                        0x00C00000L
31436 //SQ_WAVE_PC_LO
31437 #define SQ_WAVE_PC_LO__PC_LO__SHIFT                                                                           0x0
31438 #define SQ_WAVE_PC_LO__PC_LO_MASK                                                                             0xFFFFFFFFL
31439 //SQ_WAVE_PC_HI
31440 #define SQ_WAVE_PC_HI__PC_HI__SHIFT                                                                           0x0
31441 #define SQ_WAVE_PC_HI__PC_HI_MASK                                                                             0x0000FFFFL
31442 //SQ_WAVE_INST_DW0
31443 #define SQ_WAVE_INST_DW0__INST_DW0__SHIFT                                                                     0x0
31444 #define SQ_WAVE_INST_DW0__INST_DW0_MASK                                                                       0xFFFFFFFFL
31445 //SQ_WAVE_INST_DW1
31446 #define SQ_WAVE_INST_DW1__INST_DW1__SHIFT                                                                     0x0
31447 #define SQ_WAVE_INST_DW1__INST_DW1_MASK                                                                       0xFFFFFFFFL
31448 //SQ_WAVE_IB_DBG0
31449 #define SQ_WAVE_IB_DBG0__IBUF_ST__SHIFT                                                                       0x0
31450 #define SQ_WAVE_IB_DBG0__PC_INVALID__SHIFT                                                                    0x3
31451 #define SQ_WAVE_IB_DBG0__NEED_NEXT_DW__SHIFT                                                                  0x4
31452 #define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT__SHIFT                                                               0x5
31453 #define SQ_WAVE_IB_DBG0__IBUF_RPTR__SHIFT                                                                     0x8
31454 #define SQ_WAVE_IB_DBG0__IBUF_WPTR__SHIFT                                                                     0xa
31455 #define SQ_WAVE_IB_DBG0__INST_STR_ST__SHIFT                                                                   0x10
31456 #define SQ_WAVE_IB_DBG0__ECC_ST__SHIFT                                                                        0x18
31457 #define SQ_WAVE_IB_DBG0__IS_HYB__SHIFT                                                                        0x1a
31458 #define SQ_WAVE_IB_DBG0__HYB_CNT__SHIFT                                                                       0x1b
31459 #define SQ_WAVE_IB_DBG0__KILL__SHIFT                                                                          0x1d
31460 #define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH__SHIFT                                                              0x1e
31461 #define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_HI__SHIFT                                                            0x1f
31462 #define SQ_WAVE_IB_DBG0__IBUF_ST_MASK                                                                         0x00000007L
31463 #define SQ_WAVE_IB_DBG0__PC_INVALID_MASK                                                                      0x00000008L
31464 #define SQ_WAVE_IB_DBG0__NEED_NEXT_DW_MASK                                                                    0x00000010L
31465 #define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_MASK                                                                 0x000000E0L
31466 #define SQ_WAVE_IB_DBG0__IBUF_RPTR_MASK                                                                       0x00000300L
31467 #define SQ_WAVE_IB_DBG0__IBUF_WPTR_MASK                                                                       0x00000C00L
31468 #define SQ_WAVE_IB_DBG0__INST_STR_ST_MASK                                                                     0x000F0000L
31469 #define SQ_WAVE_IB_DBG0__ECC_ST_MASK                                                                          0x03000000L
31470 #define SQ_WAVE_IB_DBG0__IS_HYB_MASK                                                                          0x04000000L
31471 #define SQ_WAVE_IB_DBG0__HYB_CNT_MASK                                                                         0x18000000L
31472 #define SQ_WAVE_IB_DBG0__KILL_MASK                                                                            0x20000000L
31473 #define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH_MASK                                                                0x40000000L
31474 #define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_HI_MASK                                                              0x80000000L
31475 //SQ_WAVE_IB_DBG1
31476 #define SQ_WAVE_IB_DBG1__IXNACK__SHIFT                                                                        0x0
31477 #define SQ_WAVE_IB_DBG1__XNACK__SHIFT                                                                         0x1
31478 #define SQ_WAVE_IB_DBG1__TA_NEED_RESET__SHIFT                                                                 0x2
31479 #define SQ_WAVE_IB_DBG1__XCNT__SHIFT                                                                          0x4
31480 #define SQ_WAVE_IB_DBG1__QCNT__SHIFT                                                                          0xb
31481 #define SQ_WAVE_IB_DBG1__RCNT__SHIFT                                                                          0x12
31482 #define SQ_WAVE_IB_DBG1__MISC_CNT__SHIFT                                                                      0x19
31483 #define SQ_WAVE_IB_DBG1__IXNACK_MASK                                                                          0x00000001L
31484 #define SQ_WAVE_IB_DBG1__XNACK_MASK                                                                           0x00000002L
31485 #define SQ_WAVE_IB_DBG1__TA_NEED_RESET_MASK                                                                   0x00000004L
31486 #define SQ_WAVE_IB_DBG1__XCNT_MASK                                                                            0x000001F0L
31487 #define SQ_WAVE_IB_DBG1__QCNT_MASK                                                                            0x0000F800L
31488 #define SQ_WAVE_IB_DBG1__RCNT_MASK                                                                            0x007C0000L
31489 #define SQ_WAVE_IB_DBG1__MISC_CNT_MASK                                                                        0xFE000000L
31490 //SQ_WAVE_FLUSH_IB
31491 #define SQ_WAVE_FLUSH_IB__UNUSED__SHIFT                                                                       0x0
31492 #define SQ_WAVE_FLUSH_IB__UNUSED_MASK                                                                         0xFFFFFFFFL
31493 //SQ_WAVE_TTMP0
31494 #define SQ_WAVE_TTMP0__DATA__SHIFT                                                                            0x0
31495 #define SQ_WAVE_TTMP0__DATA_MASK                                                                              0xFFFFFFFFL
31496 //SQ_WAVE_TTMP1
31497 #define SQ_WAVE_TTMP1__DATA__SHIFT                                                                            0x0
31498 #define SQ_WAVE_TTMP1__DATA_MASK                                                                              0xFFFFFFFFL
31499 //SQ_WAVE_TTMP2
31500 #define SQ_WAVE_TTMP2__DATA__SHIFT                                                                            0x0
31501 #define SQ_WAVE_TTMP2__DATA_MASK                                                                              0xFFFFFFFFL
31502 //SQ_WAVE_TTMP3
31503 #define SQ_WAVE_TTMP3__DATA__SHIFT                                                                            0x0
31504 #define SQ_WAVE_TTMP3__DATA_MASK                                                                              0xFFFFFFFFL
31505 //SQ_WAVE_TTMP4
31506 #define SQ_WAVE_TTMP4__DATA__SHIFT                                                                            0x0
31507 #define SQ_WAVE_TTMP4__DATA_MASK                                                                              0xFFFFFFFFL
31508 //SQ_WAVE_TTMP5
31509 #define SQ_WAVE_TTMP5__DATA__SHIFT                                                                            0x0
31510 #define SQ_WAVE_TTMP5__DATA_MASK                                                                              0xFFFFFFFFL
31511 //SQ_WAVE_TTMP6
31512 #define SQ_WAVE_TTMP6__DATA__SHIFT                                                                            0x0
31513 #define SQ_WAVE_TTMP6__DATA_MASK                                                                              0xFFFFFFFFL
31514 //SQ_WAVE_TTMP7
31515 #define SQ_WAVE_TTMP7__DATA__SHIFT                                                                            0x0
31516 #define SQ_WAVE_TTMP7__DATA_MASK                                                                              0xFFFFFFFFL
31517 //SQ_WAVE_TTMP8
31518 #define SQ_WAVE_TTMP8__DATA__SHIFT                                                                            0x0
31519 #define SQ_WAVE_TTMP8__DATA_MASK                                                                              0xFFFFFFFFL
31520 //SQ_WAVE_TTMP9
31521 #define SQ_WAVE_TTMP9__DATA__SHIFT                                                                            0x0
31522 #define SQ_WAVE_TTMP9__DATA_MASK                                                                              0xFFFFFFFFL
31523 //SQ_WAVE_TTMP10
31524 #define SQ_WAVE_TTMP10__DATA__SHIFT                                                                           0x0
31525 #define SQ_WAVE_TTMP10__DATA_MASK                                                                             0xFFFFFFFFL
31526 //SQ_WAVE_TTMP11
31527 #define SQ_WAVE_TTMP11__DATA__SHIFT                                                                           0x0
31528 #define SQ_WAVE_TTMP11__DATA_MASK                                                                             0xFFFFFFFFL
31529 //SQ_WAVE_TTMP12
31530 #define SQ_WAVE_TTMP12__DATA__SHIFT                                                                           0x0
31531 #define SQ_WAVE_TTMP12__DATA_MASK                                                                             0xFFFFFFFFL
31532 //SQ_WAVE_TTMP13
31533 #define SQ_WAVE_TTMP13__DATA__SHIFT                                                                           0x0
31534 #define SQ_WAVE_TTMP13__DATA_MASK                                                                             0xFFFFFFFFL
31535 //SQ_WAVE_TTMP14
31536 #define SQ_WAVE_TTMP14__DATA__SHIFT                                                                           0x0
31537 #define SQ_WAVE_TTMP14__DATA_MASK                                                                             0xFFFFFFFFL
31538 //SQ_WAVE_TTMP15
31539 #define SQ_WAVE_TTMP15__DATA__SHIFT                                                                           0x0
31540 #define SQ_WAVE_TTMP15__DATA_MASK                                                                             0xFFFFFFFFL
31541 //SQ_WAVE_M0
31542 #define SQ_WAVE_M0__M0__SHIFT                                                                                 0x0
31543 #define SQ_WAVE_M0__M0_MASK                                                                                   0xFFFFFFFFL
31544 //SQ_WAVE_EXEC_LO
31545 #define SQ_WAVE_EXEC_LO__EXEC_LO__SHIFT                                                                       0x0
31546 #define SQ_WAVE_EXEC_LO__EXEC_LO_MASK                                                                         0xFFFFFFFFL
31547 //SQ_WAVE_EXEC_HI
31548 #define SQ_WAVE_EXEC_HI__EXEC_HI__SHIFT                                                                       0x0
31549 #define SQ_WAVE_EXEC_HI__EXEC_HI_MASK                                                                         0xFFFFFFFFL
31550 //SQ_INTERRUPT_WORD_AUTO_CTXID
31551 #define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE__SHIFT                                                     0x0
31552 #define SQ_INTERRUPT_WORD_AUTO_CTXID__WLT__SHIFT                                                              0x1
31553 #define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_BUF_FULL__SHIFT                                            0x2
31554 #define SQ_INTERRUPT_WORD_AUTO_CTXID__REG_TIMESTAMP__SHIFT                                                    0x3
31555 #define SQ_INTERRUPT_WORD_AUTO_CTXID__CMD_TIMESTAMP__SHIFT                                                    0x4
31556 #define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_CMD_OVERFLOW__SHIFT                                                0x5
31557 #define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_REG_OVERFLOW__SHIFT                                                0x6
31558 #define SQ_INTERRUPT_WORD_AUTO_CTXID__IMMED_OVERFLOW__SHIFT                                                   0x7
31559 #define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_UTC_ERROR__SHIFT                                           0x8
31560 #define SQ_INTERRUPT_WORD_AUTO_CTXID__SE_ID__SHIFT                                                            0x18
31561 #define SQ_INTERRUPT_WORD_AUTO_CTXID__ENCODING__SHIFT                                                         0x1a
31562 #define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_MASK                                                       0x0000001L
31563 #define SQ_INTERRUPT_WORD_AUTO_CTXID__WLT_MASK                                                                0x0000002L
31564 #define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_BUF_FULL_MASK                                              0x0000004L
31565 #define SQ_INTERRUPT_WORD_AUTO_CTXID__REG_TIMESTAMP_MASK                                                      0x0000008L
31566 #define SQ_INTERRUPT_WORD_AUTO_CTXID__CMD_TIMESTAMP_MASK                                                      0x0000010L
31567 #define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_CMD_OVERFLOW_MASK                                                  0x0000020L
31568 #define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_REG_OVERFLOW_MASK                                                  0x0000040L
31569 #define SQ_INTERRUPT_WORD_AUTO_CTXID__IMMED_OVERFLOW_MASK                                                     0x0000080L
31570 #define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_UTC_ERROR_MASK                                             0x0000100L
31571 #define SQ_INTERRUPT_WORD_AUTO_CTXID__SE_ID_MASK                                                              0x3000000L
31572 #define SQ_INTERRUPT_WORD_AUTO_CTXID__ENCODING_MASK                                                           0xC000000L
31573 //SQ_INTERRUPT_WORD_AUTO_HI
31574 #define SQ_INTERRUPT_WORD_AUTO_HI__SE_ID__SHIFT                                                               0x8
31575 #define SQ_INTERRUPT_WORD_AUTO_HI__ENCODING__SHIFT                                                            0xa
31576 #define SQ_INTERRUPT_WORD_AUTO_HI__SE_ID_MASK                                                                 0x300L
31577 #define SQ_INTERRUPT_WORD_AUTO_HI__ENCODING_MASK                                                              0xC00L
31578 //SQ_INTERRUPT_WORD_AUTO_LO
31579 #define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE__SHIFT                                                        0x0
31580 #define SQ_INTERRUPT_WORD_AUTO_LO__WLT__SHIFT                                                                 0x1
31581 #define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_BUF_FULL__SHIFT                                               0x2
31582 #define SQ_INTERRUPT_WORD_AUTO_LO__REG_TIMESTAMP__SHIFT                                                       0x3
31583 #define SQ_INTERRUPT_WORD_AUTO_LO__CMD_TIMESTAMP__SHIFT                                                       0x4
31584 #define SQ_INTERRUPT_WORD_AUTO_LO__HOST_CMD_OVERFLOW__SHIFT                                                   0x5
31585 #define SQ_INTERRUPT_WORD_AUTO_LO__HOST_REG_OVERFLOW__SHIFT                                                   0x6
31586 #define SQ_INTERRUPT_WORD_AUTO_LO__IMMED_OVERFLOW__SHIFT                                                      0x7
31587 #define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_UTC_ERROR__SHIFT                                              0x8
31588 #define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_MASK                                                          0x001L
31589 #define SQ_INTERRUPT_WORD_AUTO_LO__WLT_MASK                                                                   0x002L
31590 #define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_BUF_FULL_MASK                                                 0x004L
31591 #define SQ_INTERRUPT_WORD_AUTO_LO__REG_TIMESTAMP_MASK                                                         0x008L
31592 #define SQ_INTERRUPT_WORD_AUTO_LO__CMD_TIMESTAMP_MASK                                                         0x010L
31593 #define SQ_INTERRUPT_WORD_AUTO_LO__HOST_CMD_OVERFLOW_MASK                                                     0x020L
31594 #define SQ_INTERRUPT_WORD_AUTO_LO__HOST_REG_OVERFLOW_MASK                                                     0x040L
31595 #define SQ_INTERRUPT_WORD_AUTO_LO__IMMED_OVERFLOW_MASK                                                        0x080L
31596 #define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_UTC_ERROR_MASK                                                0x100L
31597 //SQ_INTERRUPT_WORD_CMN_CTXID
31598 #define SQ_INTERRUPT_WORD_CMN_CTXID__SE_ID__SHIFT                                                             0x18
31599 #define SQ_INTERRUPT_WORD_CMN_CTXID__ENCODING__SHIFT                                                          0x1a
31600 #define SQ_INTERRUPT_WORD_CMN_CTXID__SE_ID_MASK                                                               0x3000000L
31601 #define SQ_INTERRUPT_WORD_CMN_CTXID__ENCODING_MASK                                                            0xC000000L
31602 //SQ_INTERRUPT_WORD_CMN_HI
31603 #define SQ_INTERRUPT_WORD_CMN_HI__SE_ID__SHIFT                                                                0x8
31604 #define SQ_INTERRUPT_WORD_CMN_HI__ENCODING__SHIFT                                                             0xa
31605 #define SQ_INTERRUPT_WORD_CMN_HI__SE_ID_MASK                                                                  0x300L
31606 #define SQ_INTERRUPT_WORD_CMN_HI__ENCODING_MASK                                                               0xC00L
31607 //SQ_INTERRUPT_WORD_WAVE_CTXID
31608 #define SQ_INTERRUPT_WORD_WAVE_CTXID__DATA__SHIFT                                                             0x0
31609 #define SQ_INTERRUPT_WORD_WAVE_CTXID__SH_ID__SHIFT                                                            0xc
31610 #define SQ_INTERRUPT_WORD_WAVE_CTXID__PRIV__SHIFT                                                             0xd
31611 #define SQ_INTERRUPT_WORD_WAVE_CTXID__WAVE_ID__SHIFT                                                          0xe
31612 #define SQ_INTERRUPT_WORD_WAVE_CTXID__SIMD_ID__SHIFT                                                          0x12
31613 #define SQ_INTERRUPT_WORD_WAVE_CTXID__CU_ID__SHIFT                                                            0x14
31614 #define SQ_INTERRUPT_WORD_WAVE_CTXID__SE_ID__SHIFT                                                            0x18
31615 #define SQ_INTERRUPT_WORD_WAVE_CTXID__ENCODING__SHIFT                                                         0x1a
31616 #define SQ_INTERRUPT_WORD_WAVE_CTXID__DATA_MASK                                                               0x0000FFFL
31617 #define SQ_INTERRUPT_WORD_WAVE_CTXID__SH_ID_MASK                                                              0x0001000L
31618 #define SQ_INTERRUPT_WORD_WAVE_CTXID__PRIV_MASK                                                               0x0002000L
31619 #define SQ_INTERRUPT_WORD_WAVE_CTXID__WAVE_ID_MASK                                                            0x003C000L
31620 #define SQ_INTERRUPT_WORD_WAVE_CTXID__SIMD_ID_MASK                                                            0x00C0000L
31621 #define SQ_INTERRUPT_WORD_WAVE_CTXID__CU_ID_MASK                                                              0x0F00000L
31622 #define SQ_INTERRUPT_WORD_WAVE_CTXID__SE_ID_MASK                                                              0x3000000L
31623 #define SQ_INTERRUPT_WORD_WAVE_CTXID__ENCODING_MASK                                                           0xC000000L
31624 //SQ_INTERRUPT_WORD_WAVE_HI
31625 #define SQ_INTERRUPT_WORD_WAVE_HI__CU_ID__SHIFT                                                               0x0
31626 #define SQ_INTERRUPT_WORD_WAVE_HI__VM_ID__SHIFT                                                               0x4
31627 #define SQ_INTERRUPT_WORD_WAVE_HI__SE_ID__SHIFT                                                               0x8
31628 #define SQ_INTERRUPT_WORD_WAVE_HI__ENCODING__SHIFT                                                            0xa
31629 #define SQ_INTERRUPT_WORD_WAVE_HI__CU_ID_MASK                                                                 0x00FL
31630 #define SQ_INTERRUPT_WORD_WAVE_HI__VM_ID_MASK                                                                 0x0F0L
31631 #define SQ_INTERRUPT_WORD_WAVE_HI__SE_ID_MASK                                                                 0x300L
31632 #define SQ_INTERRUPT_WORD_WAVE_HI__ENCODING_MASK                                                              0xC00L
31633 //SQ_INTERRUPT_WORD_WAVE_LO
31634 #define SQ_INTERRUPT_WORD_WAVE_LO__DATA__SHIFT                                                                0x0
31635 #define SQ_INTERRUPT_WORD_WAVE_LO__SH_ID__SHIFT                                                               0x18
31636 #define SQ_INTERRUPT_WORD_WAVE_LO__PRIV__SHIFT                                                                0x19
31637 #define SQ_INTERRUPT_WORD_WAVE_LO__WAVE_ID__SHIFT                                                             0x1a
31638 #define SQ_INTERRUPT_WORD_WAVE_LO__SIMD_ID__SHIFT                                                             0x1e
31639 #define SQ_INTERRUPT_WORD_WAVE_LO__DATA_MASK                                                                  0x00FFFFFFL
31640 #define SQ_INTERRUPT_WORD_WAVE_LO__SH_ID_MASK                                                                 0x01000000L
31641 #define SQ_INTERRUPT_WORD_WAVE_LO__PRIV_MASK                                                                  0x02000000L
31642 #define SQ_INTERRUPT_WORD_WAVE_LO__WAVE_ID_MASK                                                               0x3C000000L
31643 #define SQ_INTERRUPT_WORD_WAVE_LO__SIMD_ID_MASK                                                               0xC0000000L
31644 
31645 
31646 
31647 #endif
31648