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Searched defs:SPRN_L1CSR1 (Results 1 – 2 of 2) sorted by relevance

/openbmc/linux/arch/powerpc/include/asm/
H A Dreg_booke.h174 #define SPRN_L1CSR1 0x3F3 /* L1 Cache Control and Status Register 1 */ macro
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dprocessor.h491 #define SPRN_L1CSR1 0x3f3 /* L1 Instruction Cache Control and Status Register 1 */ macro