xref: /openbmc/linux/drivers/iommu/sprd-iommu.c (revision b62841e4)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Unisoc IOMMU driver
4  *
5  * Copyright (C) 2020 Unisoc, Inc.
6  * Author: Chunyan Zhang <chunyan.zhang@unisoc.com>
7  */
8 
9 #include <linux/clk.h>
10 #include <linux/device.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/errno.h>
13 #include <linux/iommu.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/module.h>
16 #include <linux/of_platform.h>
17 #include <linux/platform_device.h>
18 #include <linux/regmap.h>
19 #include <linux/slab.h>
20 
21 #define SPRD_IOMMU_PAGE_SHIFT	12
22 #define SPRD_IOMMU_PAGE_SIZE	SZ_4K
23 
24 #define SPRD_EX_CFG		0x0
25 #define SPRD_IOMMU_VAOR_BYPASS	BIT(4)
26 #define SPRD_IOMMU_GATE_EN	BIT(1)
27 #define SPRD_IOMMU_EN		BIT(0)
28 #define SPRD_EX_UPDATE		0x4
29 #define SPRD_EX_FIRST_VPN	0x8
30 #define SPRD_EX_VPN_RANGE	0xc
31 #define SPRD_EX_FIRST_PPN	0x10
32 #define SPRD_EX_DEFAULT_PPN	0x14
33 
34 #define SPRD_IOMMU_VERSION	0x0
35 #define SPRD_VERSION_MASK	GENMASK(15, 8)
36 #define SPRD_VERSION_SHIFT	0x8
37 #define SPRD_VAU_CFG		0x4
38 #define SPRD_VAU_UPDATE		0x8
39 #define SPRD_VAU_AUTH_CFG	0xc
40 #define SPRD_VAU_FIRST_PPN	0x10
41 #define SPRD_VAU_DEFAULT_PPN_RD	0x14
42 #define SPRD_VAU_DEFAULT_PPN_WR	0x18
43 #define SPRD_VAU_FIRST_VPN	0x1c
44 #define SPRD_VAU_VPN_RANGE	0x20
45 
46 enum sprd_iommu_version {
47 	SPRD_IOMMU_EX,
48 	SPRD_IOMMU_VAU,
49 };
50 
51 /*
52  * struct sprd_iommu_device - high-level sprd IOMMU device representation,
53  * including hardware information and configuration, also driver data, etc
54  *
55  * @ver: sprd IOMMU IP version
56  * @prot_page_va: protect page base virtual address
57  * @prot_page_pa: protect page base physical address, data would be
58  *		  written to here while translation fault
59  * @base: mapped base address for accessing registers
60  * @dev: pointer to basic device structure
61  * @iommu: IOMMU core representation
62  * @group: IOMMU group
63  * @eb: gate clock which controls IOMMU access
64  */
65 struct sprd_iommu_device {
66 	struct sprd_iommu_domain	*dom;
67 	enum sprd_iommu_version	ver;
68 	u32			*prot_page_va;
69 	dma_addr_t		prot_page_pa;
70 	void __iomem		*base;
71 	struct device		*dev;
72 	struct iommu_device	iommu;
73 	struct iommu_group	*group;
74 	struct clk		*eb;
75 };
76 
77 struct sprd_iommu_domain {
78 	spinlock_t		pgtlock; /* lock for page table */
79 	struct iommu_domain	domain;
80 	u32			*pgt_va; /* page table virtual address base */
81 	dma_addr_t		pgt_pa; /* page table physical address base */
82 	struct sprd_iommu_device	*sdev;
83 };
84 
85 static const struct iommu_ops sprd_iommu_ops;
86 
to_sprd_domain(struct iommu_domain * dom)87 static struct sprd_iommu_domain *to_sprd_domain(struct iommu_domain *dom)
88 {
89 	return container_of(dom, struct sprd_iommu_domain, domain);
90 }
91 
92 static inline void
sprd_iommu_write(struct sprd_iommu_device * sdev,unsigned int reg,u32 val)93 sprd_iommu_write(struct sprd_iommu_device *sdev, unsigned int reg, u32 val)
94 {
95 	writel_relaxed(val, sdev->base + reg);
96 }
97 
98 static inline u32
sprd_iommu_read(struct sprd_iommu_device * sdev,unsigned int reg)99 sprd_iommu_read(struct sprd_iommu_device *sdev, unsigned int reg)
100 {
101 	return readl_relaxed(sdev->base + reg);
102 }
103 
104 static inline void
sprd_iommu_update_bits(struct sprd_iommu_device * sdev,unsigned int reg,u32 mask,u32 shift,u32 val)105 sprd_iommu_update_bits(struct sprd_iommu_device *sdev, unsigned int reg,
106 		  u32 mask, u32 shift, u32 val)
107 {
108 	u32 t = sprd_iommu_read(sdev, reg);
109 
110 	t = (t & (~(mask << shift))) | ((val & mask) << shift);
111 	sprd_iommu_write(sdev, reg, t);
112 }
113 
114 static inline int
sprd_iommu_get_version(struct sprd_iommu_device * sdev)115 sprd_iommu_get_version(struct sprd_iommu_device *sdev)
116 {
117 	int ver = (sprd_iommu_read(sdev, SPRD_IOMMU_VERSION) &
118 		   SPRD_VERSION_MASK) >> SPRD_VERSION_SHIFT;
119 
120 	switch (ver) {
121 	case SPRD_IOMMU_EX:
122 	case SPRD_IOMMU_VAU:
123 		return ver;
124 	default:
125 		return -EINVAL;
126 	}
127 }
128 
129 static size_t
sprd_iommu_pgt_size(struct iommu_domain * domain)130 sprd_iommu_pgt_size(struct iommu_domain *domain)
131 {
132 	return ((domain->geometry.aperture_end -
133 		 domain->geometry.aperture_start + 1) >>
134 		SPRD_IOMMU_PAGE_SHIFT) * sizeof(u32);
135 }
136 
sprd_iommu_domain_alloc(unsigned int domain_type)137 static struct iommu_domain *sprd_iommu_domain_alloc(unsigned int domain_type)
138 {
139 	struct sprd_iommu_domain *dom;
140 
141 	if (domain_type != IOMMU_DOMAIN_DMA && domain_type != IOMMU_DOMAIN_UNMANAGED)
142 		return NULL;
143 
144 	dom = kzalloc(sizeof(*dom), GFP_KERNEL);
145 	if (!dom)
146 		return NULL;
147 
148 	spin_lock_init(&dom->pgtlock);
149 
150 	dom->domain.geometry.aperture_start = 0;
151 	dom->domain.geometry.aperture_end = SZ_256M - 1;
152 	dom->domain.geometry.force_aperture = true;
153 
154 	return &dom->domain;
155 }
156 
sprd_iommu_first_vpn(struct sprd_iommu_domain * dom)157 static void sprd_iommu_first_vpn(struct sprd_iommu_domain *dom)
158 {
159 	struct sprd_iommu_device *sdev = dom->sdev;
160 	u32 val;
161 	unsigned int reg;
162 
163 	if (sdev->ver == SPRD_IOMMU_EX)
164 		reg = SPRD_EX_FIRST_VPN;
165 	else
166 		reg = SPRD_VAU_FIRST_VPN;
167 
168 	val = dom->domain.geometry.aperture_start >> SPRD_IOMMU_PAGE_SHIFT;
169 	sprd_iommu_write(sdev, reg, val);
170 }
171 
sprd_iommu_vpn_range(struct sprd_iommu_domain * dom)172 static void sprd_iommu_vpn_range(struct sprd_iommu_domain *dom)
173 {
174 	struct sprd_iommu_device *sdev = dom->sdev;
175 	u32 val;
176 	unsigned int reg;
177 
178 	if (sdev->ver == SPRD_IOMMU_EX)
179 		reg = SPRD_EX_VPN_RANGE;
180 	else
181 		reg = SPRD_VAU_VPN_RANGE;
182 
183 	val = (dom->domain.geometry.aperture_end -
184 	       dom->domain.geometry.aperture_start) >> SPRD_IOMMU_PAGE_SHIFT;
185 	sprd_iommu_write(sdev, reg, val);
186 }
187 
sprd_iommu_first_ppn(struct sprd_iommu_domain * dom)188 static void sprd_iommu_first_ppn(struct sprd_iommu_domain *dom)
189 {
190 	u32 val = dom->pgt_pa >> SPRD_IOMMU_PAGE_SHIFT;
191 	struct sprd_iommu_device *sdev = dom->sdev;
192 	unsigned int reg;
193 
194 	if (sdev->ver == SPRD_IOMMU_EX)
195 		reg = SPRD_EX_FIRST_PPN;
196 	else
197 		reg = SPRD_VAU_FIRST_PPN;
198 
199 	sprd_iommu_write(sdev, reg, val);
200 }
201 
sprd_iommu_default_ppn(struct sprd_iommu_device * sdev)202 static void sprd_iommu_default_ppn(struct sprd_iommu_device *sdev)
203 {
204 	u32 val = sdev->prot_page_pa >> SPRD_IOMMU_PAGE_SHIFT;
205 
206 	if (sdev->ver == SPRD_IOMMU_EX) {
207 		sprd_iommu_write(sdev, SPRD_EX_DEFAULT_PPN, val);
208 	} else if (sdev->ver == SPRD_IOMMU_VAU) {
209 		sprd_iommu_write(sdev, SPRD_VAU_DEFAULT_PPN_RD, val);
210 		sprd_iommu_write(sdev, SPRD_VAU_DEFAULT_PPN_WR, val);
211 	}
212 }
213 
sprd_iommu_hw_en(struct sprd_iommu_device * sdev,bool en)214 static void sprd_iommu_hw_en(struct sprd_iommu_device *sdev, bool en)
215 {
216 	unsigned int reg_cfg;
217 	u32 mask, val;
218 
219 	if (sdev->ver == SPRD_IOMMU_EX)
220 		reg_cfg = SPRD_EX_CFG;
221 	else
222 		reg_cfg = SPRD_VAU_CFG;
223 
224 	mask = SPRD_IOMMU_EN | SPRD_IOMMU_GATE_EN;
225 	val = en ? mask : 0;
226 	sprd_iommu_update_bits(sdev, reg_cfg, mask, 0, val);
227 }
228 
sprd_iommu_cleanup(struct sprd_iommu_domain * dom)229 static void sprd_iommu_cleanup(struct sprd_iommu_domain *dom)
230 {
231 	size_t pgt_size;
232 
233 	/* Nothing need to do if the domain hasn't been attached */
234 	if (!dom->sdev)
235 		return;
236 
237 	pgt_size = sprd_iommu_pgt_size(&dom->domain);
238 	dma_free_coherent(dom->sdev->dev, pgt_size, dom->pgt_va, dom->pgt_pa);
239 	sprd_iommu_hw_en(dom->sdev, false);
240 	dom->sdev = NULL;
241 }
242 
sprd_iommu_domain_free(struct iommu_domain * domain)243 static void sprd_iommu_domain_free(struct iommu_domain *domain)
244 {
245 	struct sprd_iommu_domain *dom = to_sprd_domain(domain);
246 
247 	sprd_iommu_cleanup(dom);
248 	kfree(dom);
249 }
250 
sprd_iommu_attach_device(struct iommu_domain * domain,struct device * dev)251 static int sprd_iommu_attach_device(struct iommu_domain *domain,
252 				    struct device *dev)
253 {
254 	struct sprd_iommu_device *sdev = dev_iommu_priv_get(dev);
255 	struct sprd_iommu_domain *dom = to_sprd_domain(domain);
256 	size_t pgt_size = sprd_iommu_pgt_size(domain);
257 
258 	/* The device is attached to this domain */
259 	if (sdev->dom == dom)
260 		return 0;
261 
262 	/* The first time that domain is attaching to a device */
263 	if (!dom->pgt_va) {
264 		dom->pgt_va = dma_alloc_coherent(sdev->dev, pgt_size, &dom->pgt_pa, GFP_KERNEL);
265 		if (!dom->pgt_va)
266 			return -ENOMEM;
267 
268 		dom->sdev = sdev;
269 	}
270 
271 	sdev->dom = dom;
272 
273 	/*
274 	 * One sprd IOMMU serves one client device only, disabled it before
275 	 * configure mapping table to avoid access conflict in case other
276 	 * mapping table is stored in.
277 	 */
278 	sprd_iommu_hw_en(sdev, false);
279 	sprd_iommu_first_ppn(dom);
280 	sprd_iommu_first_vpn(dom);
281 	sprd_iommu_vpn_range(dom);
282 	sprd_iommu_default_ppn(sdev);
283 	sprd_iommu_hw_en(sdev, true);
284 
285 	return 0;
286 }
287 
sprd_iommu_map(struct iommu_domain * domain,unsigned long iova,phys_addr_t paddr,size_t pgsize,size_t pgcount,int prot,gfp_t gfp,size_t * mapped)288 static int sprd_iommu_map(struct iommu_domain *domain, unsigned long iova,
289 			  phys_addr_t paddr, size_t pgsize, size_t pgcount,
290 			  int prot, gfp_t gfp, size_t *mapped)
291 {
292 	struct sprd_iommu_domain *dom = to_sprd_domain(domain);
293 	size_t size = pgcount * SPRD_IOMMU_PAGE_SIZE;
294 	unsigned long flags;
295 	unsigned int i;
296 	u32 *pgt_base_iova;
297 	u32 pabase = (u32)paddr;
298 	unsigned long start = domain->geometry.aperture_start;
299 	unsigned long end = domain->geometry.aperture_end;
300 
301 	if (!dom->sdev) {
302 		pr_err("No sprd_iommu_device attached to the domain\n");
303 		return -EINVAL;
304 	}
305 
306 	if (iova < start || (iova + size) > (end + 1)) {
307 		dev_err(dom->sdev->dev, "(iova(0x%lx) + size(%zx)) are not in the range!\n",
308 			iova, size);
309 		return -EINVAL;
310 	}
311 
312 	pgt_base_iova = dom->pgt_va + ((iova - start) >> SPRD_IOMMU_PAGE_SHIFT);
313 
314 	spin_lock_irqsave(&dom->pgtlock, flags);
315 	for (i = 0; i < pgcount; i++) {
316 		pgt_base_iova[i] = pabase >> SPRD_IOMMU_PAGE_SHIFT;
317 		pabase += SPRD_IOMMU_PAGE_SIZE;
318 	}
319 	spin_unlock_irqrestore(&dom->pgtlock, flags);
320 
321 	*mapped = size;
322 	return 0;
323 }
324 
sprd_iommu_unmap(struct iommu_domain * domain,unsigned long iova,size_t pgsize,size_t pgcount,struct iommu_iotlb_gather * iotlb_gather)325 static size_t sprd_iommu_unmap(struct iommu_domain *domain, unsigned long iova,
326 			       size_t pgsize, size_t pgcount,
327 			       struct iommu_iotlb_gather *iotlb_gather)
328 {
329 	struct sprd_iommu_domain *dom = to_sprd_domain(domain);
330 	unsigned long flags;
331 	u32 *pgt_base_iova;
332 	size_t size = pgcount * SPRD_IOMMU_PAGE_SIZE;
333 	unsigned long start = domain->geometry.aperture_start;
334 	unsigned long end = domain->geometry.aperture_end;
335 
336 	if (iova < start || (iova + size) > (end + 1))
337 		return 0;
338 
339 	pgt_base_iova = dom->pgt_va + ((iova - start) >> SPRD_IOMMU_PAGE_SHIFT);
340 
341 	spin_lock_irqsave(&dom->pgtlock, flags);
342 	memset(pgt_base_iova, 0, pgcount * sizeof(u32));
343 	spin_unlock_irqrestore(&dom->pgtlock, flags);
344 
345 	return size;
346 }
347 
sprd_iommu_sync_map(struct iommu_domain * domain,unsigned long iova,size_t size)348 static void sprd_iommu_sync_map(struct iommu_domain *domain,
349 				unsigned long iova, size_t size)
350 {
351 	struct sprd_iommu_domain *dom = to_sprd_domain(domain);
352 	unsigned int reg;
353 
354 	if (dom->sdev->ver == SPRD_IOMMU_EX)
355 		reg = SPRD_EX_UPDATE;
356 	else
357 		reg = SPRD_VAU_UPDATE;
358 
359 	/* clear IOMMU TLB buffer after page table updated */
360 	sprd_iommu_write(dom->sdev, reg, 0xffffffff);
361 }
362 
sprd_iommu_sync(struct iommu_domain * domain,struct iommu_iotlb_gather * iotlb_gather)363 static void sprd_iommu_sync(struct iommu_domain *domain,
364 			    struct iommu_iotlb_gather *iotlb_gather)
365 {
366 	sprd_iommu_sync_map(domain, 0, 0);
367 }
368 
sprd_iommu_iova_to_phys(struct iommu_domain * domain,dma_addr_t iova)369 static phys_addr_t sprd_iommu_iova_to_phys(struct iommu_domain *domain,
370 					   dma_addr_t iova)
371 {
372 	struct sprd_iommu_domain *dom = to_sprd_domain(domain);
373 	unsigned long flags;
374 	phys_addr_t pa;
375 	unsigned long start = domain->geometry.aperture_start;
376 	unsigned long end = domain->geometry.aperture_end;
377 
378 	if (WARN_ON(iova < start || iova > end))
379 		return 0;
380 
381 	spin_lock_irqsave(&dom->pgtlock, flags);
382 	pa = *(dom->pgt_va + ((iova - start) >> SPRD_IOMMU_PAGE_SHIFT));
383 	pa = (pa << SPRD_IOMMU_PAGE_SHIFT) + ((iova - start) & (SPRD_IOMMU_PAGE_SIZE - 1));
384 	spin_unlock_irqrestore(&dom->pgtlock, flags);
385 
386 	return pa;
387 }
388 
sprd_iommu_probe_device(struct device * dev)389 static struct iommu_device *sprd_iommu_probe_device(struct device *dev)
390 {
391 	struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
392 	struct sprd_iommu_device *sdev;
393 
394 	if (!fwspec || fwspec->ops != &sprd_iommu_ops)
395 		return ERR_PTR(-ENODEV);
396 
397 	sdev = dev_iommu_priv_get(dev);
398 
399 	return &sdev->iommu;
400 }
401 
sprd_iommu_device_group(struct device * dev)402 static struct iommu_group *sprd_iommu_device_group(struct device *dev)
403 {
404 	struct sprd_iommu_device *sdev = dev_iommu_priv_get(dev);
405 
406 	return iommu_group_ref_get(sdev->group);
407 }
408 
sprd_iommu_of_xlate(struct device * dev,struct of_phandle_args * args)409 static int sprd_iommu_of_xlate(struct device *dev, struct of_phandle_args *args)
410 {
411 	struct platform_device *pdev;
412 
413 	if (!dev_iommu_priv_get(dev)) {
414 		pdev = of_find_device_by_node(args->np);
415 		dev_iommu_priv_set(dev, platform_get_drvdata(pdev));
416 		platform_device_put(pdev);
417 	}
418 
419 	return 0;
420 }
421 
422 
423 static const struct iommu_ops sprd_iommu_ops = {
424 	.domain_alloc	= sprd_iommu_domain_alloc,
425 	.probe_device	= sprd_iommu_probe_device,
426 	.device_group	= sprd_iommu_device_group,
427 	.of_xlate	= sprd_iommu_of_xlate,
428 	.pgsize_bitmap	= SPRD_IOMMU_PAGE_SIZE,
429 	.owner		= THIS_MODULE,
430 	.default_domain_ops = &(const struct iommu_domain_ops) {
431 		.attach_dev	= sprd_iommu_attach_device,
432 		.map_pages	= sprd_iommu_map,
433 		.unmap_pages	= sprd_iommu_unmap,
434 		.iotlb_sync_map	= sprd_iommu_sync_map,
435 		.iotlb_sync	= sprd_iommu_sync,
436 		.iova_to_phys	= sprd_iommu_iova_to_phys,
437 		.free		= sprd_iommu_domain_free,
438 	}
439 };
440 
441 static const struct of_device_id sprd_iommu_of_match[] = {
442 	{ .compatible = "sprd,iommu-v1" },
443 	{ },
444 };
445 MODULE_DEVICE_TABLE(of, sprd_iommu_of_match);
446 
447 /*
448  * Clock is not required, access to some of IOMMUs is controlled by gate
449  * clk, enabled clocks for that kind of IOMMUs before accessing.
450  * Return 0 for success or no clocks found.
451  */
sprd_iommu_clk_enable(struct sprd_iommu_device * sdev)452 static int sprd_iommu_clk_enable(struct sprd_iommu_device *sdev)
453 {
454 	struct clk *eb;
455 
456 	eb = devm_clk_get_optional(sdev->dev, NULL);
457 	if (!eb)
458 		return 0;
459 
460 	if (IS_ERR(eb))
461 		return PTR_ERR(eb);
462 
463 	sdev->eb = eb;
464 	return clk_prepare_enable(eb);
465 }
466 
sprd_iommu_clk_disable(struct sprd_iommu_device * sdev)467 static void sprd_iommu_clk_disable(struct sprd_iommu_device *sdev)
468 {
469 	if (sdev->eb)
470 		clk_disable_unprepare(sdev->eb);
471 }
472 
sprd_iommu_probe(struct platform_device * pdev)473 static int sprd_iommu_probe(struct platform_device *pdev)
474 {
475 	struct sprd_iommu_device *sdev;
476 	struct device *dev = &pdev->dev;
477 	void __iomem *base;
478 	int ret;
479 
480 	sdev = devm_kzalloc(dev, sizeof(*sdev), GFP_KERNEL);
481 	if (!sdev)
482 		return -ENOMEM;
483 
484 	base = devm_platform_ioremap_resource(pdev, 0);
485 	if (IS_ERR(base)) {
486 		dev_err(dev, "Failed to get ioremap resource.\n");
487 		return PTR_ERR(base);
488 	}
489 	sdev->base = base;
490 
491 	sdev->prot_page_va = dma_alloc_coherent(dev, SPRD_IOMMU_PAGE_SIZE,
492 						&sdev->prot_page_pa, GFP_KERNEL);
493 	if (!sdev->prot_page_va)
494 		return -ENOMEM;
495 
496 	platform_set_drvdata(pdev, sdev);
497 	sdev->dev = dev;
498 
499 	/* All the client devices are in the same iommu-group */
500 	sdev->group = iommu_group_alloc();
501 	if (IS_ERR(sdev->group)) {
502 		ret = PTR_ERR(sdev->group);
503 		goto free_page;
504 	}
505 
506 	ret = iommu_device_sysfs_add(&sdev->iommu, dev, NULL, dev_name(dev));
507 	if (ret)
508 		goto put_group;
509 
510 	ret = iommu_device_register(&sdev->iommu, &sprd_iommu_ops, dev);
511 	if (ret)
512 		goto remove_sysfs;
513 
514 	ret = sprd_iommu_clk_enable(sdev);
515 	if (ret)
516 		goto unregister_iommu;
517 
518 	ret = sprd_iommu_get_version(sdev);
519 	if (ret < 0) {
520 		dev_err(dev, "IOMMU version(%d) is invalid.\n", ret);
521 		goto disable_clk;
522 	}
523 	sdev->ver = ret;
524 
525 	return 0;
526 
527 disable_clk:
528 	sprd_iommu_clk_disable(sdev);
529 unregister_iommu:
530 	iommu_device_unregister(&sdev->iommu);
531 remove_sysfs:
532 	iommu_device_sysfs_remove(&sdev->iommu);
533 put_group:
534 	iommu_group_put(sdev->group);
535 free_page:
536 	dma_free_coherent(sdev->dev, SPRD_IOMMU_PAGE_SIZE, sdev->prot_page_va, sdev->prot_page_pa);
537 	return ret;
538 }
539 
sprd_iommu_remove(struct platform_device * pdev)540 static void sprd_iommu_remove(struct platform_device *pdev)
541 {
542 	struct sprd_iommu_device *sdev = platform_get_drvdata(pdev);
543 
544 	dma_free_coherent(sdev->dev, SPRD_IOMMU_PAGE_SIZE, sdev->prot_page_va, sdev->prot_page_pa);
545 
546 	iommu_group_put(sdev->group);
547 	sdev->group = NULL;
548 
549 	platform_set_drvdata(pdev, NULL);
550 	iommu_device_sysfs_remove(&sdev->iommu);
551 	iommu_device_unregister(&sdev->iommu);
552 }
553 
554 static struct platform_driver sprd_iommu_driver = {
555 	.driver	= {
556 		.name		= "sprd-iommu",
557 		.of_match_table	= sprd_iommu_of_match,
558 		.suppress_bind_attrs = true,
559 	},
560 	.probe	= sprd_iommu_probe,
561 	.remove_new = sprd_iommu_remove,
562 };
563 module_platform_driver(sprd_iommu_driver);
564 
565 MODULE_DESCRIPTION("IOMMU driver for Unisoc SoCs");
566 MODULE_ALIAS("platform:sprd-iommu");
567 MODULE_LICENSE("GPL");
568