1 /*
2  *   Copyright (c) 2011, 2012, Qualcomm Atheros Communications Inc.
3  *   Copyright (c) 2014, I2SE GmbH
4  *
5  *   Permission to use, copy, modify, and/or distribute this software
6  *   for any purpose with or without fee is hereby granted, provided
7  *   that the above copyright notice and this permission notice appear
8  *   in all copies.
9  *
10  *   THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
11  *   WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
12  *   WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL
13  *   THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR
14  *   CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
15  *   LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT,
16  *   NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
17  *   CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18  *
19  */
20 
21 /*   Qualcomm Atheros SPI register definition.
22  *
23  *   This module is designed to define the Qualcomm Atheros SPI
24  *   register placeholders.
25  */
26 
27 #ifndef _QCA_7K_H
28 #define _QCA_7K_H
29 
30 #include <linux/types.h>
31 
32 #include "qca_spi.h"
33 
34 #define QCA7K_SPI_READ     (1 << 15)
35 #define QCA7K_SPI_WRITE    (0 << 15)
36 #define QCA7K_SPI_INTERNAL (1 << 14)
37 #define QCA7K_SPI_EXTERNAL (0 << 14)
38 
39 #define QCASPI_CMD_LEN    2
40 #define QCASPI_HW_PKT_LEN 4
41 #define QCASPI_HW_BUF_LEN 0xC5B
42 
43 /*   SPI registers;                               */
44 #define SPI_REG_BFR_SIZE        0x0100
45 #define SPI_REG_WRBUF_SPC_AVA   0x0200
46 #define SPI_REG_RDBUF_BYTE_AVA  0x0300
47 #define SPI_REG_SPI_CONFIG      0x0400
48 #define SPI_REG_SPI_STATUS      0x0500
49 #define SPI_REG_INTR_CAUSE      0x0C00
50 #define SPI_REG_INTR_ENABLE     0x0D00
51 #define SPI_REG_RDBUF_WATERMARK 0x1200
52 #define SPI_REG_WRBUF_WATERMARK 0x1300
53 #define SPI_REG_SIGNATURE       0x1A00
54 #define SPI_REG_ACTION_CTRL     0x1B00
55 
56 /*   SPI_CONFIG register definition;             */
57 #define QCASPI_SLAVE_RESET_BIT  BIT(6)
58 
59 /*   INTR_CAUSE/ENABLE register definition.      */
60 #define SPI_INT_WRBUF_BELOW_WM  BIT(10)
61 #define SPI_INT_CPU_ON          BIT(6)
62 #define SPI_INT_ADDR_ERR        BIT(3)
63 #define SPI_INT_WRBUF_ERR       BIT(2)
64 #define SPI_INT_RDBUF_ERR       BIT(1)
65 #define SPI_INT_PKT_AVLBL       BIT(0)
66 
67 void qcaspi_spi_error(struct qcaspi *qca);
68 int qcaspi_read_register(struct qcaspi *qca, u16 reg, u16 *result);
69 int qcaspi_write_register(struct qcaspi *qca, u16 reg, u16 value, int retry);
70 
71 #endif /* _QCA_7K_H */
72