xref: /openbmc/linux/drivers/spi/spi-mt7621.c (revision 749396cb)
1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // spi-mt7621.c -- MediaTek MT7621 SPI controller driver
4 //
5 // Copyright (C) 2011 Sergiy <piratfm@gmail.com>
6 // Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
7 // Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name>
8 //
9 // Some parts are based on spi-orion.c:
10 //   Author: Shadi Ammouri <shadi@marvell.com>
11 //   Copyright (C) 2007-2008 Marvell Ltd.
12 
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/io.h>
16 #include <linux/module.h>
17 #include <linux/of.h>
18 #include <linux/of_device.h>
19 #include <linux/platform_device.h>
20 #include <linux/reset.h>
21 #include <linux/spi/spi.h>
22 
23 #define DRIVER_NAME		"spi-mt7621"
24 
25 /* in usec */
26 #define RALINK_SPI_WAIT_MAX_LOOP 2000
27 
28 /* SPISTAT register bit field */
29 #define SPISTAT_BUSY		BIT(0)
30 
31 #define MT7621_SPI_TRANS	0x00
32 #define SPITRANS_BUSY		BIT(16)
33 
34 #define MT7621_SPI_OPCODE	0x04
35 #define MT7621_SPI_DATA0	0x08
36 #define MT7621_SPI_DATA4	0x18
37 #define SPI_CTL_TX_RX_CNT_MASK	0xff
38 #define SPI_CTL_START		BIT(8)
39 
40 #define MT7621_SPI_MASTER	0x28
41 #define MASTER_MORE_BUFMODE	BIT(2)
42 #define MASTER_FULL_DUPLEX	BIT(10)
43 #define MASTER_RS_CLK_SEL	GENMASK(27, 16)
44 #define MASTER_RS_CLK_SEL_SHIFT	16
45 #define MASTER_RS_SLAVE_SEL	GENMASK(31, 29)
46 
47 #define MT7621_SPI_MOREBUF	0x2c
48 #define MT7621_SPI_POLAR	0x38
49 #define MT7621_SPI_SPACE	0x3c
50 
51 #define MT7621_CPHA		BIT(5)
52 #define MT7621_CPOL		BIT(4)
53 #define MT7621_LSB_FIRST	BIT(3)
54 
55 struct mt7621_spi {
56 	struct spi_controller	*master;
57 	void __iomem		*base;
58 	unsigned int		sys_freq;
59 	unsigned int		speed;
60 	int			pending_write;
61 };
62 
spidev_to_mt7621_spi(struct spi_device * spi)63 static inline struct mt7621_spi *spidev_to_mt7621_spi(struct spi_device *spi)
64 {
65 	return spi_controller_get_devdata(spi->master);
66 }
67 
mt7621_spi_read(struct mt7621_spi * rs,u32 reg)68 static inline u32 mt7621_spi_read(struct mt7621_spi *rs, u32 reg)
69 {
70 	return ioread32(rs->base + reg);
71 }
72 
mt7621_spi_write(struct mt7621_spi * rs,u32 reg,u32 val)73 static inline void mt7621_spi_write(struct mt7621_spi *rs, u32 reg, u32 val)
74 {
75 	iowrite32(val, rs->base + reg);
76 }
77 
mt7621_spi_set_cs(struct spi_device * spi,int enable)78 static void mt7621_spi_set_cs(struct spi_device *spi, int enable)
79 {
80 	struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
81 	int cs = spi_get_chipselect(spi, 0);
82 	u32 polar = 0;
83 	u32 master;
84 
85 	/*
86 	 * Select SPI device 7, enable "more buffer mode" and disable
87 	 * full-duplex (only half-duplex really works on this chip
88 	 * reliably)
89 	 */
90 	master = mt7621_spi_read(rs, MT7621_SPI_MASTER);
91 	master |= MASTER_RS_SLAVE_SEL | MASTER_MORE_BUFMODE;
92 	master &= ~MASTER_FULL_DUPLEX;
93 	mt7621_spi_write(rs, MT7621_SPI_MASTER, master);
94 
95 	rs->pending_write = 0;
96 
97 	if (enable)
98 		polar = BIT(cs);
99 	mt7621_spi_write(rs, MT7621_SPI_POLAR, polar);
100 }
101 
mt7621_spi_prepare(struct spi_device * spi,unsigned int speed)102 static int mt7621_spi_prepare(struct spi_device *spi, unsigned int speed)
103 {
104 	struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
105 	u32 rate;
106 	u32 reg;
107 
108 	dev_dbg(&spi->dev, "speed:%u\n", speed);
109 
110 	rate = DIV_ROUND_UP(rs->sys_freq, speed);
111 	dev_dbg(&spi->dev, "rate-1:%u\n", rate);
112 
113 	if (rate > 4097)
114 		return -EINVAL;
115 
116 	if (rate < 2)
117 		rate = 2;
118 
119 	reg = mt7621_spi_read(rs, MT7621_SPI_MASTER);
120 	reg &= ~MASTER_RS_CLK_SEL;
121 	reg |= (rate - 2) << MASTER_RS_CLK_SEL_SHIFT;
122 	rs->speed = speed;
123 
124 	reg &= ~MT7621_LSB_FIRST;
125 	if (spi->mode & SPI_LSB_FIRST)
126 		reg |= MT7621_LSB_FIRST;
127 
128 	/*
129 	 * This SPI controller seems to be tested on SPI flash only and some
130 	 * bits are swizzled under other SPI modes probably due to incorrect
131 	 * wiring inside the silicon. Only mode 0 works correctly.
132 	 */
133 	reg &= ~(MT7621_CPHA | MT7621_CPOL);
134 
135 	mt7621_spi_write(rs, MT7621_SPI_MASTER, reg);
136 
137 	return 0;
138 }
139 
mt7621_spi_wait_till_ready(struct mt7621_spi * rs)140 static inline int mt7621_spi_wait_till_ready(struct mt7621_spi *rs)
141 {
142 	int i;
143 
144 	for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
145 		u32 status;
146 
147 		status = mt7621_spi_read(rs, MT7621_SPI_TRANS);
148 		if ((status & SPITRANS_BUSY) == 0)
149 			return 0;
150 		cpu_relax();
151 		udelay(1);
152 	}
153 
154 	return -ETIMEDOUT;
155 }
156 
mt7621_spi_read_half_duplex(struct mt7621_spi * rs,int rx_len,u8 * buf)157 static void mt7621_spi_read_half_duplex(struct mt7621_spi *rs,
158 					int rx_len, u8 *buf)
159 {
160 	int tx_len;
161 
162 	/*
163 	 * Combine with any pending write, and perform one or more half-duplex
164 	 * transactions reading 'len' bytes. Data to be written is already in
165 	 * MT7621_SPI_DATA.
166 	 */
167 	tx_len = rs->pending_write;
168 	rs->pending_write = 0;
169 
170 	while (rx_len || tx_len) {
171 		int i;
172 		u32 val = (min(tx_len, 4) * 8) << 24;
173 		int rx = min(rx_len, 32);
174 
175 		if (tx_len > 4)
176 			val |= (tx_len - 4) * 8;
177 		val |= (rx * 8) << 12;
178 		mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val);
179 
180 		tx_len = 0;
181 
182 		val = mt7621_spi_read(rs, MT7621_SPI_TRANS);
183 		val |= SPI_CTL_START;
184 		mt7621_spi_write(rs, MT7621_SPI_TRANS, val);
185 
186 		mt7621_spi_wait_till_ready(rs);
187 
188 		for (i = 0; i < rx; i++) {
189 			if ((i % 4) == 0)
190 				val = mt7621_spi_read(rs, MT7621_SPI_DATA0 + i);
191 			*buf++ = val & 0xff;
192 			val >>= 8;
193 		}
194 
195 		rx_len -= i;
196 	}
197 }
198 
mt7621_spi_flush(struct mt7621_spi * rs)199 static inline void mt7621_spi_flush(struct mt7621_spi *rs)
200 {
201 	mt7621_spi_read_half_duplex(rs, 0, NULL);
202 }
203 
mt7621_spi_write_half_duplex(struct mt7621_spi * rs,int tx_len,const u8 * buf)204 static void mt7621_spi_write_half_duplex(struct mt7621_spi *rs,
205 					 int tx_len, const u8 *buf)
206 {
207 	int len = rs->pending_write;
208 	int val = 0;
209 
210 	if (len & 3) {
211 		val = mt7621_spi_read(rs, MT7621_SPI_OPCODE + (len & ~3));
212 		if (len < 4) {
213 			val <<= (4 - len) * 8;
214 			val = swab32(val);
215 		}
216 	}
217 
218 	while (tx_len > 0) {
219 		if (len >= 36) {
220 			rs->pending_write = len;
221 			mt7621_spi_flush(rs);
222 			len = 0;
223 		}
224 
225 		val |= *buf++ << (8 * (len & 3));
226 		len++;
227 		if ((len & 3) == 0) {
228 			if (len == 4)
229 				/* The byte-order of the opcode is weird! */
230 				val = swab32(val);
231 			mt7621_spi_write(rs, MT7621_SPI_OPCODE + len - 4, val);
232 			val = 0;
233 		}
234 		tx_len -= 1;
235 	}
236 
237 	if (len & 3) {
238 		if (len < 4) {
239 			val = swab32(val);
240 			val >>= (4 - len) * 8;
241 		}
242 		mt7621_spi_write(rs, MT7621_SPI_OPCODE + (len & ~3), val);
243 	}
244 
245 	rs->pending_write = len;
246 }
247 
mt7621_spi_transfer_one_message(struct spi_controller * master,struct spi_message * m)248 static int mt7621_spi_transfer_one_message(struct spi_controller *master,
249 					   struct spi_message *m)
250 {
251 	struct mt7621_spi *rs = spi_controller_get_devdata(master);
252 	struct spi_device *spi = m->spi;
253 	unsigned int speed = spi->max_speed_hz;
254 	struct spi_transfer *t = NULL;
255 	int status = 0;
256 
257 	mt7621_spi_wait_till_ready(rs);
258 
259 	list_for_each_entry(t, &m->transfers, transfer_list)
260 		if (t->speed_hz < speed)
261 			speed = t->speed_hz;
262 
263 	if (mt7621_spi_prepare(spi, speed)) {
264 		status = -EIO;
265 		goto msg_done;
266 	}
267 
268 	/* Assert CS */
269 	mt7621_spi_set_cs(spi, 1);
270 
271 	m->actual_length = 0;
272 	list_for_each_entry(t, &m->transfers, transfer_list) {
273 		if ((t->rx_buf) && (t->tx_buf)) {
274 			/*
275 			 * This controller will shift some extra data out
276 			 * of spi_opcode if (mosi_bit_cnt > 0) &&
277 			 * (cmd_bit_cnt == 0). So the claimed full-duplex
278 			 * support is broken since we have no way to read
279 			 * the MISO value during that bit.
280 			 */
281 			status = -EIO;
282 			goto msg_done;
283 		} else if (t->rx_buf) {
284 			mt7621_spi_read_half_duplex(rs, t->len, t->rx_buf);
285 		} else if (t->tx_buf) {
286 			mt7621_spi_write_half_duplex(rs, t->len, t->tx_buf);
287 		}
288 		m->actual_length += t->len;
289 	}
290 
291 	/* Flush data and deassert CS */
292 	mt7621_spi_flush(rs);
293 	mt7621_spi_set_cs(spi, 0);
294 
295 msg_done:
296 	m->status = status;
297 	spi_finalize_current_message(master);
298 
299 	return 0;
300 }
301 
mt7621_spi_setup(struct spi_device * spi)302 static int mt7621_spi_setup(struct spi_device *spi)
303 {
304 	struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
305 
306 	if ((spi->max_speed_hz == 0) ||
307 	    (spi->max_speed_hz > (rs->sys_freq / 2)))
308 		spi->max_speed_hz = rs->sys_freq / 2;
309 
310 	if (spi->max_speed_hz < (rs->sys_freq / 4097)) {
311 		dev_err(&spi->dev, "setup: requested speed is too low %d Hz\n",
312 			spi->max_speed_hz);
313 		return -EINVAL;
314 	}
315 
316 	return 0;
317 }
318 
319 static const struct of_device_id mt7621_spi_match[] = {
320 	{ .compatible = "ralink,mt7621-spi" },
321 	{},
322 };
323 MODULE_DEVICE_TABLE(of, mt7621_spi_match);
324 
mt7621_spi_probe(struct platform_device * pdev)325 static int mt7621_spi_probe(struct platform_device *pdev)
326 {
327 	const struct of_device_id *match;
328 	struct spi_controller *master;
329 	struct mt7621_spi *rs;
330 	void __iomem *base;
331 	struct clk *clk;
332 	int ret;
333 
334 	match = of_match_device(mt7621_spi_match, &pdev->dev);
335 	if (!match)
336 		return -EINVAL;
337 
338 	base = devm_platform_ioremap_resource(pdev, 0);
339 	if (IS_ERR(base))
340 		return PTR_ERR(base);
341 
342 	clk = devm_clk_get_enabled(&pdev->dev, NULL);
343 	if (IS_ERR(clk))
344 		return dev_err_probe(&pdev->dev, PTR_ERR(clk),
345 				     "unable to get SYS clock\n");
346 
347 	master = devm_spi_alloc_master(&pdev->dev, sizeof(*rs));
348 	if (!master) {
349 		dev_info(&pdev->dev, "master allocation failed\n");
350 		return -ENOMEM;
351 	}
352 
353 	master->mode_bits = SPI_LSB_FIRST;
354 	master->flags = SPI_CONTROLLER_HALF_DUPLEX;
355 	master->setup = mt7621_spi_setup;
356 	master->transfer_one_message = mt7621_spi_transfer_one_message;
357 	master->bits_per_word_mask = SPI_BPW_MASK(8);
358 	master->dev.of_node = pdev->dev.of_node;
359 	master->num_chipselect = 2;
360 
361 	dev_set_drvdata(&pdev->dev, master);
362 
363 	rs = spi_controller_get_devdata(master);
364 	rs->base = base;
365 	rs->master = master;
366 	rs->sys_freq = clk_get_rate(clk);
367 	rs->pending_write = 0;
368 	dev_info(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
369 
370 	ret = device_reset(&pdev->dev);
371 	if (ret) {
372 		dev_err(&pdev->dev, "SPI reset failed!\n");
373 		return ret;
374 	}
375 
376 	return devm_spi_register_controller(&pdev->dev, master);
377 }
378 
379 MODULE_ALIAS("platform:" DRIVER_NAME);
380 
381 static struct platform_driver mt7621_spi_driver = {
382 	.driver = {
383 		.name = DRIVER_NAME,
384 		.of_match_table = mt7621_spi_match,
385 	},
386 	.probe = mt7621_spi_probe,
387 };
388 
389 module_platform_driver(mt7621_spi_driver);
390 
391 MODULE_DESCRIPTION("MT7621 SPI driver");
392 MODULE_AUTHOR("Felix Fietkau <nbd@nbd.name>");
393 MODULE_LICENSE("GPL");
394