1 /* 2 * Allwinner SPI Bus Serial Interface Emulation 3 * 4 * Copyright (C) 2024 Strahinja Jankovic <strahinja.p.jankovic@gmail.com> 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 * for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, see <http://www.gnu.org/licenses/>. 18 * 19 * SPDX-License-Identifier: GPL-2.0-or-later 20 */ 21 22 #include "qemu/osdep.h" 23 #include "hw/irq.h" 24 #include "hw/ssi/allwinner-a10-spi.h" 25 #include "migration/vmstate.h" 26 #include "qemu/log.h" 27 #include "qemu/module.h" 28 #include "trace.h" 29 30 /* Allwinner SPI memory map */ 31 #define SPI_RXDATA_REG 0x00 /* receive data register */ 32 #define SPI_TXDATA_REG 0x04 /* transmit data register */ 33 #define SPI_CTL_REG 0x08 /* control register */ 34 #define SPI_INTCTL_REG 0x0c /* interrupt control register */ 35 #define SPI_INT_STA_REG 0x10 /* interrupt status register */ 36 #define SPI_DMACTL_REG 0x14 /* DMA control register */ 37 #define SPI_WAIT_REG 0x18 /* wait clock counter register */ 38 #define SPI_CCTL_REG 0x1c /* clock rate control register */ 39 #define SPI_BC_REG 0x20 /* burst control register */ 40 #define SPI_TC_REG 0x24 /* transmit counter register */ 41 #define SPI_FIFO_STA_REG 0x28 /* FIFO status register */ 42 43 /* Data register */ 44 #define SPI_DATA_RESET 0 45 46 /* Control register */ 47 #define SPI_CTL_SDC (1 << 19) 48 #define SPI_CTL_TP_EN (1 << 18) 49 #define SPI_CTL_SS_LEVEL (1 << 17) 50 #define SPI_CTL_SS_CTRL (1 << 16) 51 #define SPI_CTL_DHB (1 << 15) 52 #define SPI_CTL_DDB (1 << 14) 53 #define SPI_CTL_SS (3 << 12) 54 #define SPI_CTL_SS_SHIFT 12 55 #define SPI_CTL_RPSM (1 << 11) 56 #define SPI_CTL_XCH (1 << 10) 57 #define SPI_CTL_RF_RST (1 << 9) 58 #define SPI_CTL_TF_RST (1 << 8) 59 #define SPI_CTL_SSCTL (1 << 7) 60 #define SPI_CTL_LMTF (1 << 6) 61 #define SPI_CTL_DMAMC (1 << 5) 62 #define SPI_CTL_SSPOL (1 << 4) 63 #define SPI_CTL_POL (1 << 3) 64 #define SPI_CTL_PHA (1 << 2) 65 #define SPI_CTL_MODE (1 << 1) 66 #define SPI_CTL_EN (1 << 0) 67 #define SPI_CTL_MASK 0xFFFFFu 68 #define SPI_CTL_RESET 0x0002001Cu 69 70 /* Interrupt control register */ 71 #define SPI_INTCTL_SS_INT_EN (1 << 17) 72 #define SPI_INTCTL_TX_INT_EN (1 << 16) 73 #define SPI_INTCTL_TF_UR_INT_EN (1 << 14) 74 #define SPI_INTCTL_TF_OF_INT_EN (1 << 13) 75 #define SPI_INTCTL_TF_E34_INT_EN (1 << 12) 76 #define SPI_INTCTL_TF_E14_INT_EN (1 << 11) 77 #define SPI_INTCTL_TF_FL_INT_EN (1 << 10) 78 #define SPI_INTCTL_TF_HALF_EMP_INT_EN (1 << 9) 79 #define SPI_INTCTL_TF_EMP_INT_EN (1 << 8) 80 #define SPI_INTCTL_RF_UR_INT_EN (1 << 6) 81 #define SPI_INTCTL_RF_OF_INT_EN (1 << 5) 82 #define SPI_INTCTL_RF_E34_INT_EN (1 << 4) 83 #define SPI_INTCTL_RF_E14_INT_EN (1 << 3) 84 #define SPI_INTCTL_RF_FU_INT_EN (1 << 2) 85 #define SPI_INTCTL_RF_HALF_FU_INT_EN (1 << 1) 86 #define SPI_INTCTL_RF_RDY_INT_EN (1 << 0) 87 #define SPI_INTCTL_MASK 0x37F7Fu 88 #define SPI_INTCTL_RESET 0 89 90 /* Interrupt status register */ 91 #define SPI_INT_STA_INT_CBF (1 << 31) 92 #define SPI_INT_STA_SSI (1 << 17) 93 #define SPI_INT_STA_TC (1 << 16) 94 #define SPI_INT_STA_TU (1 << 14) 95 #define SPI_INT_STA_TO (1 << 13) 96 #define SPI_INT_STA_TE34 (1 << 12) 97 #define SPI_INT_STA_TE14 (1 << 11) 98 #define SPI_INT_STA_TF (1 << 10) 99 #define SPI_INT_STA_THE (1 << 9) 100 #define SPI_INT_STA_TE (1 << 8) 101 #define SPI_INT_STA_RU (1 << 6) 102 #define SPI_INT_STA_RO (1 << 5) 103 #define SPI_INT_STA_RF34 (1 << 4) 104 #define SPI_INT_STA_RF14 (1 << 3) 105 #define SPI_INT_STA_RF (1 << 2) 106 #define SPI_INT_STA_RHF (1 << 1) 107 #define SPI_INT_STA_RR (1 << 0) 108 #define SPI_INT_STA_MASK 0x80037F7Fu 109 #define SPI_INT_STA_RESET 0x00001B00u 110 111 /* DMA control register - not implemented */ 112 #define SPI_DMACTL_RESET 0 113 114 /* Wait clock register */ 115 #define SPI_WAIT_REG_WCC_MASK 0xFFFFu 116 #define SPI_WAIT_RESET 0 117 118 /* Clock control register - not implemented */ 119 #define SPI_CCTL_RESET 2 120 121 /* Burst count register */ 122 #define SPI_BC_BC_MASK 0xFFFFFFu 123 #define SPI_BC_RESET 0 124 125 /* Transmi counter register */ 126 #define SPI_TC_WTC_MASK 0xFFFFFFu 127 #define SPI_TC_RESET 0 128 129 /* FIFO status register */ 130 #define SPI_FIFO_STA_CNT_MASK 0x7F 131 #define SPI_FIFO_STA_TF_CNT_SHIFT 16 132 #define SPI_FIFO_STA_RF_CNT_SHIFT 0 133 #define SPI_FIFO_STA_RESET 0 134 135 #define REG_INDEX(offset) (offset / sizeof(uint32_t)) 136 137 allwinner_a10_spi_get_regname(unsigned offset)138 static const char *allwinner_a10_spi_get_regname(unsigned offset) 139 { 140 switch (offset) { 141 case SPI_RXDATA_REG: 142 return "RXDATA"; 143 case SPI_TXDATA_REG: 144 return "TXDATA"; 145 case SPI_CTL_REG: 146 return "CTL"; 147 case SPI_INTCTL_REG: 148 return "INTCTL"; 149 case SPI_INT_STA_REG: 150 return "INT_STA"; 151 case SPI_DMACTL_REG: 152 return "DMACTL"; 153 case SPI_WAIT_REG: 154 return "WAIT"; 155 case SPI_CCTL_REG: 156 return "CCTL"; 157 case SPI_BC_REG: 158 return "BC"; 159 case SPI_TC_REG: 160 return "TC"; 161 case SPI_FIFO_STA_REG: 162 return "FIFO_STA"; 163 default: 164 return "[?]"; 165 } 166 } 167 allwinner_a10_spi_is_enabled(AWA10SPIState * s)168 static bool allwinner_a10_spi_is_enabled(AWA10SPIState *s) 169 { 170 return s->regs[REG_INDEX(SPI_CTL_REG)] & SPI_CTL_EN; 171 } 172 allwinner_a10_spi_txfifo_reset(AWA10SPIState * s)173 static void allwinner_a10_spi_txfifo_reset(AWA10SPIState *s) 174 { 175 fifo8_reset(&s->tx_fifo); 176 s->regs[REG_INDEX(SPI_INT_STA_REG)] |= (SPI_INT_STA_TE | SPI_INT_STA_TE14 | 177 SPI_INT_STA_THE | SPI_INT_STA_TE34); 178 s->regs[REG_INDEX(SPI_INT_STA_REG)] &= ~(SPI_INT_STA_TU | SPI_INT_STA_TO); 179 } 180 allwinner_a10_spi_rxfifo_reset(AWA10SPIState * s)181 static void allwinner_a10_spi_rxfifo_reset(AWA10SPIState *s) 182 { 183 fifo8_reset(&s->rx_fifo); 184 s->regs[REG_INDEX(SPI_INT_STA_REG)] &= 185 ~(SPI_INT_STA_RU | SPI_INT_STA_RO | SPI_INT_STA_RF | SPI_INT_STA_RR | 186 SPI_INT_STA_RHF | SPI_INT_STA_RF14 | SPI_INT_STA_RF34); 187 } 188 allwinner_a10_spi_selected_channel(AWA10SPIState * s)189 static uint8_t allwinner_a10_spi_selected_channel(AWA10SPIState *s) 190 { 191 return (s->regs[REG_INDEX(SPI_CTL_REG)] & SPI_CTL_SS) >> SPI_CTL_SS_SHIFT; 192 } 193 allwinner_a10_spi_reset_hold(Object * obj,ResetType type)194 static void allwinner_a10_spi_reset_hold(Object *obj, ResetType type) 195 { 196 AWA10SPIState *s = AW_A10_SPI(obj); 197 198 s->regs[REG_INDEX(SPI_RXDATA_REG)] = SPI_DATA_RESET; 199 s->regs[REG_INDEX(SPI_TXDATA_REG)] = SPI_DATA_RESET; 200 s->regs[REG_INDEX(SPI_CTL_REG)] = SPI_CTL_RESET; 201 s->regs[REG_INDEX(SPI_INTCTL_REG)] = SPI_INTCTL_RESET; 202 s->regs[REG_INDEX(SPI_INT_STA_REG)] = SPI_INT_STA_RESET; 203 s->regs[REG_INDEX(SPI_DMACTL_REG)] = SPI_DMACTL_RESET; 204 s->regs[REG_INDEX(SPI_WAIT_REG)] = SPI_WAIT_RESET; 205 s->regs[REG_INDEX(SPI_CCTL_REG)] = SPI_CCTL_RESET; 206 s->regs[REG_INDEX(SPI_BC_REG)] = SPI_BC_RESET; 207 s->regs[REG_INDEX(SPI_TC_REG)] = SPI_TC_RESET; 208 s->regs[REG_INDEX(SPI_FIFO_STA_REG)] = SPI_FIFO_STA_RESET; 209 210 allwinner_a10_spi_txfifo_reset(s); 211 allwinner_a10_spi_rxfifo_reset(s); 212 } 213 allwinner_a10_spi_update_irq(AWA10SPIState * s)214 static void allwinner_a10_spi_update_irq(AWA10SPIState *s) 215 { 216 bool level; 217 218 if (fifo8_is_empty(&s->rx_fifo)) { 219 s->regs[REG_INDEX(SPI_INT_STA_REG)] &= ~SPI_INT_STA_RR; 220 } else { 221 s->regs[REG_INDEX(SPI_INT_STA_REG)] |= SPI_INT_STA_RR; 222 } 223 224 if (fifo8_num_used(&s->rx_fifo) >= (AW_A10_SPI_FIFO_SIZE >> 2)) { 225 s->regs[REG_INDEX(SPI_INT_STA_REG)] |= SPI_INT_STA_RF14; 226 } else { 227 s->regs[REG_INDEX(SPI_INT_STA_REG)] &= ~SPI_INT_STA_RF14; 228 } 229 230 if (fifo8_num_used(&s->rx_fifo) >= (AW_A10_SPI_FIFO_SIZE >> 1)) { 231 s->regs[REG_INDEX(SPI_INT_STA_REG)] |= SPI_INT_STA_RHF; 232 } else { 233 s->regs[REG_INDEX(SPI_INT_STA_REG)] &= ~SPI_INT_STA_RHF; 234 } 235 236 if (fifo8_num_free(&s->rx_fifo) <= (AW_A10_SPI_FIFO_SIZE >> 2)) { 237 s->regs[REG_INDEX(SPI_INT_STA_REG)] |= SPI_INT_STA_RF34; 238 } else { 239 s->regs[REG_INDEX(SPI_INT_STA_REG)] &= ~SPI_INT_STA_RF34; 240 } 241 242 if (fifo8_is_full(&s->rx_fifo)) { 243 s->regs[REG_INDEX(SPI_INT_STA_REG)] |= SPI_INT_STA_RF; 244 } else { 245 s->regs[REG_INDEX(SPI_INT_STA_REG)] &= ~SPI_INT_STA_RF; 246 } 247 248 if (fifo8_is_empty(&s->tx_fifo)) { 249 s->regs[REG_INDEX(SPI_INT_STA_REG)] |= SPI_INT_STA_TE; 250 } else { 251 s->regs[REG_INDEX(SPI_INT_STA_REG)] &= ~SPI_INT_STA_TE; 252 } 253 254 if (fifo8_num_free(&s->tx_fifo) >= (AW_A10_SPI_FIFO_SIZE >> 2)) { 255 s->regs[REG_INDEX(SPI_INT_STA_REG)] |= SPI_INT_STA_TE14; 256 } else { 257 s->regs[REG_INDEX(SPI_INT_STA_REG)] &= ~SPI_INT_STA_TE14; 258 } 259 260 if (fifo8_num_free(&s->tx_fifo) >= (AW_A10_SPI_FIFO_SIZE >> 1)) { 261 s->regs[REG_INDEX(SPI_INT_STA_REG)] |= SPI_INT_STA_THE; 262 } else { 263 s->regs[REG_INDEX(SPI_INT_STA_REG)] &= ~SPI_INT_STA_THE; 264 } 265 266 if (fifo8_num_used(&s->tx_fifo) <= (AW_A10_SPI_FIFO_SIZE >> 2)) { 267 s->regs[REG_INDEX(SPI_INT_STA_REG)] |= SPI_INT_STA_TE34; 268 } else { 269 s->regs[REG_INDEX(SPI_INT_STA_REG)] &= ~SPI_INT_STA_TE34; 270 } 271 272 if (fifo8_is_full(&s->rx_fifo)) { 273 s->regs[REG_INDEX(SPI_INT_STA_REG)] |= SPI_INT_STA_TF; 274 } else { 275 s->regs[REG_INDEX(SPI_INT_STA_REG)] &= ~SPI_INT_STA_TF; 276 } 277 278 level = (s->regs[REG_INDEX(SPI_INT_STA_REG)] & 279 s->regs[REG_INDEX(SPI_INTCTL_REG)]) != 0; 280 281 qemu_set_irq(s->irq, level); 282 283 trace_allwinner_a10_spi_update_irq(level); 284 } 285 allwinner_a10_spi_flush_txfifo(AWA10SPIState * s)286 static void allwinner_a10_spi_flush_txfifo(AWA10SPIState *s) 287 { 288 uint32_t burst_count = s->regs[REG_INDEX(SPI_BC_REG)]; 289 uint32_t tx_burst = s->regs[REG_INDEX(SPI_TC_REG)]; 290 trace_allwinner_a10_spi_burst_length(tx_burst); 291 292 trace_allwinner_a10_spi_flush_txfifo_begin(fifo8_num_used(&s->tx_fifo), 293 fifo8_num_used(&s->rx_fifo)); 294 295 while (!fifo8_is_empty(&s->tx_fifo)) { 296 uint8_t tx = fifo8_pop(&s->tx_fifo); 297 uint8_t rx = 0; 298 bool fill_rx = true; 299 300 trace_allwinner_a10_spi_tx(tx); 301 302 /* Write one byte at a time */ 303 rx = ssi_transfer(s->bus, tx); 304 305 trace_allwinner_a10_spi_rx(rx); 306 307 /* Check DHB here to determine if RX bytes should be stored */ 308 if (s->regs[REG_INDEX(SPI_CTL_REG)] & SPI_CTL_DHB) { 309 /* Store rx bytes only after WTC transfers */ 310 if (tx_burst > 0u) { 311 fill_rx = false; 312 tx_burst--; 313 } 314 } 315 316 if (fill_rx) { 317 if (fifo8_is_full(&s->rx_fifo)) { 318 s->regs[REG_INDEX(SPI_INT_STA_REG)] |= SPI_INT_STA_RF; 319 } else { 320 fifo8_push(&s->rx_fifo, rx); 321 } 322 } 323 324 allwinner_a10_spi_update_irq(s); 325 326 burst_count--; 327 328 if (burst_count == 0) { 329 s->regs[REG_INDEX(SPI_INT_STA_REG)] |= SPI_INT_STA_TC; 330 s->regs[REG_INDEX(SPI_CTL_REG)] &= ~SPI_CTL_XCH; 331 break; 332 } 333 } 334 335 if (fifo8_is_empty(&s->tx_fifo)) { 336 s->regs[REG_INDEX(SPI_INT_STA_REG)] |= SPI_INT_STA_TC; 337 s->regs[REG_INDEX(SPI_CTL_REG)] &= ~SPI_CTL_XCH; 338 } 339 340 trace_allwinner_a10_spi_flush_txfifo_end(fifo8_num_used(&s->tx_fifo), 341 fifo8_num_used(&s->rx_fifo)); 342 } 343 allwinner_a10_spi_read(void * opaque,hwaddr offset,unsigned size)344 static uint64_t allwinner_a10_spi_read(void *opaque, hwaddr offset, 345 unsigned size) 346 { 347 uint32_t value = 0; 348 AWA10SPIState *s = opaque; 349 uint32_t index = offset >> 2; 350 351 if (offset > SPI_FIFO_STA_REG) { 352 qemu_log_mask(LOG_GUEST_ERROR, 353 "[%s]%s: Bad register at offset 0x%" HWADDR_PRIx "\n", 354 TYPE_AW_A10_SPI, __func__, offset); 355 return 0; 356 } 357 358 value = s->regs[index]; 359 360 if (allwinner_a10_spi_is_enabled(s)) { 361 switch (offset) { 362 case SPI_RXDATA_REG: 363 if (fifo8_is_empty(&s->rx_fifo)) { 364 /* value is undefined */ 365 value = 0xdeadbeef; 366 } else { 367 /* read from the RX FIFO */ 368 value = fifo8_pop(&s->rx_fifo); 369 } 370 break; 371 case SPI_TXDATA_REG: 372 qemu_log_mask(LOG_GUEST_ERROR, 373 "[%s]%s: Trying to read from TX FIFO\n", 374 TYPE_AW_A10_SPI, __func__); 375 376 /* Reading from TXDATA gives 0 */ 377 break; 378 case SPI_FIFO_STA_REG: 379 /* Read current tx/rx fifo data count */ 380 value = fifo8_num_used(&s->tx_fifo) << SPI_FIFO_STA_TF_CNT_SHIFT | 381 fifo8_num_used(&s->rx_fifo) << SPI_FIFO_STA_RF_CNT_SHIFT; 382 break; 383 case SPI_CTL_REG: 384 case SPI_INTCTL_REG: 385 case SPI_INT_STA_REG: 386 case SPI_DMACTL_REG: 387 case SPI_WAIT_REG: 388 case SPI_CCTL_REG: 389 case SPI_BC_REG: 390 case SPI_TC_REG: 391 break; 392 default: 393 qemu_log_mask(LOG_GUEST_ERROR, 394 "%s: bad offset 0x%x\n", __func__, 395 (uint32_t)offset); 396 break; 397 } 398 399 allwinner_a10_spi_update_irq(s); 400 } 401 trace_allwinner_a10_spi_read(allwinner_a10_spi_get_regname(offset), value); 402 403 return value; 404 } 405 allwinner_a10_spi_update_cs_level(AWA10SPIState * s,int cs_line_nr)406 static bool allwinner_a10_spi_update_cs_level(AWA10SPIState *s, int cs_line_nr) 407 { 408 if (cs_line_nr == allwinner_a10_spi_selected_channel(s)) { 409 return (s->regs[REG_INDEX(SPI_CTL_REG)] & SPI_CTL_SS_LEVEL) != 0; 410 } else { 411 return (s->regs[REG_INDEX(SPI_CTL_REG)] & SPI_CTL_SSPOL) != 0; 412 } 413 } 414 allwinner_a10_spi_write(void * opaque,hwaddr offset,uint64_t value,unsigned size)415 static void allwinner_a10_spi_write(void *opaque, hwaddr offset, uint64_t value, 416 unsigned size) 417 { 418 AWA10SPIState *s = opaque; 419 uint32_t index = offset >> 2; 420 int i = 0; 421 422 if (offset > SPI_FIFO_STA_REG) { 423 qemu_log_mask(LOG_GUEST_ERROR, 424 "[%s]%s: Bad register at offset 0x%" HWADDR_PRIx "\n", 425 TYPE_AW_A10_SPI, __func__, offset); 426 return; 427 } 428 429 trace_allwinner_a10_spi_write(allwinner_a10_spi_get_regname(offset), 430 (uint32_t)value); 431 432 if (!allwinner_a10_spi_is_enabled(s)) { 433 /* Block is disabled */ 434 if (offset != SPI_CTL_REG) { 435 /* Ignore access */ 436 return; 437 } 438 } 439 440 switch (offset) { 441 case SPI_RXDATA_REG: 442 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to write to RX FIFO\n", 443 TYPE_AW_A10_SPI, __func__); 444 break; 445 case SPI_TXDATA_REG: 446 if (fifo8_is_full(&s->tx_fifo)) { 447 /* Ignore writes if queue is full */ 448 break; 449 } 450 451 fifo8_push(&s->tx_fifo, (uint8_t)value); 452 453 break; 454 case SPI_INT_STA_REG: 455 /* Handle W1C bits - everything except SPI_INT_STA_INT_CBF. */ 456 value &= ~SPI_INT_STA_INT_CBF; 457 s->regs[REG_INDEX(SPI_INT_STA_REG)] &= ~(value & SPI_INT_STA_MASK); 458 break; 459 case SPI_CTL_REG: 460 s->regs[REG_INDEX(SPI_CTL_REG)] = value; 461 462 for (i = 0; i < AW_A10_SPI_CS_LINES_NR; i++) { 463 qemu_set_irq( 464 s->cs_lines[i], 465 allwinner_a10_spi_update_cs_level(s, i)); 466 } 467 468 if (s->regs[REG_INDEX(SPI_CTL_REG)] & SPI_CTL_XCH) { 469 /* Request to start emitting */ 470 allwinner_a10_spi_flush_txfifo(s); 471 } 472 if (s->regs[REG_INDEX(SPI_CTL_REG)] & SPI_CTL_TF_RST) { 473 allwinner_a10_spi_txfifo_reset(s); 474 s->regs[REG_INDEX(SPI_CTL_REG)] &= ~SPI_CTL_TF_RST; 475 } 476 if (s->regs[REG_INDEX(SPI_CTL_REG)] & SPI_CTL_RF_RST) { 477 allwinner_a10_spi_rxfifo_reset(s); 478 s->regs[REG_INDEX(SPI_CTL_REG)] &= ~SPI_CTL_RF_RST; 479 } 480 break; 481 case SPI_INTCTL_REG: 482 case SPI_DMACTL_REG: 483 case SPI_WAIT_REG: 484 case SPI_CCTL_REG: 485 case SPI_BC_REG: 486 case SPI_TC_REG: 487 case SPI_FIFO_STA_REG: 488 s->regs[index] = value; 489 break; 490 default: 491 qemu_log_mask(LOG_GUEST_ERROR, 492 "%s: bad offset 0x%x\n", __func__, 493 (uint32_t)offset); 494 break; 495 } 496 497 allwinner_a10_spi_update_irq(s); 498 } 499 500 static const MemoryRegionOps allwinner_a10_spi_ops = { 501 .read = allwinner_a10_spi_read, 502 .write = allwinner_a10_spi_write, 503 .valid.min_access_size = 1, 504 .valid.max_access_size = 4, 505 .endianness = DEVICE_NATIVE_ENDIAN, 506 }; 507 508 static const VMStateDescription allwinner_a10_spi_vmstate = { 509 .name = TYPE_AW_A10_SPI, 510 .version_id = 1, 511 .minimum_version_id = 1, 512 .fields = (const VMStateField[]) { 513 VMSTATE_FIFO8(tx_fifo, AWA10SPIState), 514 VMSTATE_FIFO8(rx_fifo, AWA10SPIState), 515 VMSTATE_UINT32_ARRAY(regs, AWA10SPIState, AW_A10_SPI_REGS_NUM), 516 VMSTATE_END_OF_LIST() 517 } 518 }; 519 allwinner_a10_spi_realize(DeviceState * dev,Error ** errp)520 static void allwinner_a10_spi_realize(DeviceState *dev, Error **errp) 521 { 522 AWA10SPIState *s = AW_A10_SPI(dev); 523 int i = 0; 524 525 memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_a10_spi_ops, s, 526 TYPE_AW_A10_SPI, AW_A10_SPI_IOSIZE); 527 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); 528 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); 529 530 s->bus = ssi_create_bus(dev, "spi"); 531 for (i = 0; i < AW_A10_SPI_CS_LINES_NR; i++) { 532 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->cs_lines[i]); 533 } 534 fifo8_create(&s->tx_fifo, AW_A10_SPI_FIFO_SIZE); 535 fifo8_create(&s->rx_fifo, AW_A10_SPI_FIFO_SIZE); 536 } 537 allwinner_a10_spi_class_init(ObjectClass * klass,void * data)538 static void allwinner_a10_spi_class_init(ObjectClass *klass, void *data) 539 { 540 DeviceClass *dc = DEVICE_CLASS(klass); 541 ResettableClass *rc = RESETTABLE_CLASS(klass); 542 543 rc->phases.hold = allwinner_a10_spi_reset_hold; 544 dc->vmsd = &allwinner_a10_spi_vmstate; 545 dc->realize = allwinner_a10_spi_realize; 546 dc->desc = "Allwinner A10 SPI Controller"; 547 } 548 549 static const TypeInfo allwinner_a10_spi_type_info = { 550 .name = TYPE_AW_A10_SPI, 551 .parent = TYPE_SYS_BUS_DEVICE, 552 .instance_size = sizeof(AWA10SPIState), 553 .class_init = allwinner_a10_spi_class_init, 554 }; 555 allwinner_a10_spi_register_types(void)556 static void allwinner_a10_spi_register_types(void) 557 { 558 type_register_static(&allwinner_a10_spi_type_info); 559 } 560 561 type_init(allwinner_a10_spi_register_types) 562