1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2010-2013 NVIDIA Corporation
4 * With help from the mpc8xxx SPI driver
5 * With more help from omap3_spi SPI driver
6 */
7
8 #include <common.h>
9 #include <dm.h>
10 #include <errno.h>
11 #include <asm/io.h>
12 #include <asm/gpio.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/pinmux.h>
15 #include <asm/arch-tegra/clk_rst.h>
16 #include <spi.h>
17 #include <fdtdec.h>
18 #include "tegra_spi.h"
19
20 DECLARE_GLOBAL_DATA_PTR;
21
22 #define SPI_CMD_GO BIT(30)
23 #define SPI_CMD_ACTIVE_SCLK_SHIFT 26
24 #define SPI_CMD_ACTIVE_SCLK_MASK (3 << SPI_CMD_ACTIVE_SCLK_SHIFT)
25 #define SPI_CMD_CK_SDA BIT(21)
26 #define SPI_CMD_ACTIVE_SDA_SHIFT 18
27 #define SPI_CMD_ACTIVE_SDA_MASK (3 << SPI_CMD_ACTIVE_SDA_SHIFT)
28 #define SPI_CMD_CS_POL BIT(16)
29 #define SPI_CMD_TXEN BIT(15)
30 #define SPI_CMD_RXEN BIT(14)
31 #define SPI_CMD_CS_VAL BIT(13)
32 #define SPI_CMD_CS_SOFT BIT(12)
33 #define SPI_CMD_CS_DELAY BIT(9)
34 #define SPI_CMD_CS3_EN BIT(8)
35 #define SPI_CMD_CS2_EN BIT(7)
36 #define SPI_CMD_CS1_EN BIT(6)
37 #define SPI_CMD_CS0_EN BIT(5)
38 #define SPI_CMD_BIT_LENGTH BIT(4)
39 #define SPI_CMD_BIT_LENGTH_MASK GENMASK(4, 0)
40
41 #define SPI_STAT_BSY BIT(31)
42 #define SPI_STAT_RDY BIT(30)
43 #define SPI_STAT_RXF_FLUSH BIT(29)
44 #define SPI_STAT_TXF_FLUSH BIT(28)
45 #define SPI_STAT_RXF_UNR BIT(27)
46 #define SPI_STAT_TXF_OVF BIT(26)
47 #define SPI_STAT_RXF_EMPTY BIT(25)
48 #define SPI_STAT_RXF_FULL BIT(24)
49 #define SPI_STAT_TXF_EMPTY BIT(23)
50 #define SPI_STAT_TXF_FULL BIT(22)
51 #define SPI_STAT_SEL_TXRX_N BIT(16)
52 #define SPI_STAT_CUR_BLKCNT BIT(15)
53
54 #define SPI_TIMEOUT 1000
55 #define TEGRA_SPI_MAX_FREQ 52000000
56
57 struct spi_regs {
58 u32 command; /* SPI_COMMAND_0 register */
59 u32 status; /* SPI_STATUS_0 register */
60 u32 rx_cmp; /* SPI_RX_CMP_0 register */
61 u32 dma_ctl; /* SPI_DMA_CTL_0 register */
62 u32 tx_fifo; /* SPI_TX_FIFO_0 register */
63 u32 rsvd[3]; /* offsets 0x14 to 0x1F reserved */
64 u32 rx_fifo; /* SPI_RX_FIFO_0 register */
65 };
66
67 struct tegra20_sflash_priv {
68 struct spi_regs *regs;
69 unsigned int freq;
70 unsigned int mode;
71 int periph_id;
72 int valid;
73 int last_transaction_us;
74 };
75
tegra20_sflash_cs_info(struct udevice * bus,unsigned int cs,struct spi_cs_info * info)76 int tegra20_sflash_cs_info(struct udevice *bus, unsigned int cs,
77 struct spi_cs_info *info)
78 {
79 /* Tegra20 SPI-Flash - only 1 device ('bus/cs') */
80 if (cs != 0)
81 return -ENODEV;
82 else
83 return 0;
84 }
85
tegra20_sflash_ofdata_to_platdata(struct udevice * bus)86 static int tegra20_sflash_ofdata_to_platdata(struct udevice *bus)
87 {
88 struct tegra_spi_platdata *plat = bus->platdata;
89 const void *blob = gd->fdt_blob;
90 int node = dev_of_offset(bus);
91
92 plat->base = devfdt_get_addr(bus);
93 plat->periph_id = clock_decode_periph_id(bus);
94
95 if (plat->periph_id == PERIPH_ID_NONE) {
96 debug("%s: could not decode periph id %d\n", __func__,
97 plat->periph_id);
98 return -FDT_ERR_NOTFOUND;
99 }
100
101 /* Use 500KHz as a suitable default */
102 plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
103 500000);
104 plat->deactivate_delay_us = fdtdec_get_int(blob, node,
105 "spi-deactivate-delay", 0);
106 debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
107 __func__, plat->base, plat->periph_id, plat->frequency,
108 plat->deactivate_delay_us);
109
110 return 0;
111 }
112
tegra20_sflash_probe(struct udevice * bus)113 static int tegra20_sflash_probe(struct udevice *bus)
114 {
115 struct tegra_spi_platdata *plat = dev_get_platdata(bus);
116 struct tegra20_sflash_priv *priv = dev_get_priv(bus);
117
118 priv->regs = (struct spi_regs *)plat->base;
119
120 priv->last_transaction_us = timer_get_us();
121 priv->freq = plat->frequency;
122 priv->periph_id = plat->periph_id;
123
124 /* Change SPI clock to correct frequency, PLLP_OUT0 source */
125 clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH,
126 priv->freq);
127
128 return 0;
129 }
130
tegra20_sflash_claim_bus(struct udevice * dev)131 static int tegra20_sflash_claim_bus(struct udevice *dev)
132 {
133 struct udevice *bus = dev->parent;
134 struct tegra20_sflash_priv *priv = dev_get_priv(bus);
135 struct spi_regs *regs = priv->regs;
136 u32 reg;
137
138 /* Change SPI clock to correct frequency, PLLP_OUT0 source */
139 clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH,
140 priv->freq);
141
142 /* Clear stale status here */
143 reg = SPI_STAT_RDY | SPI_STAT_RXF_FLUSH | SPI_STAT_TXF_FLUSH | \
144 SPI_STAT_RXF_UNR | SPI_STAT_TXF_OVF;
145 writel(reg, ®s->status);
146 debug("%s: STATUS = %08x\n", __func__, readl(®s->status));
147
148 /*
149 * Use sw-controlled CS, so we can clock in data after ReadID, etc.
150 */
151 reg = (priv->mode & 1) << SPI_CMD_ACTIVE_SDA_SHIFT;
152 if (priv->mode & 2)
153 reg |= 1 << SPI_CMD_ACTIVE_SCLK_SHIFT;
154 clrsetbits_le32(®s->command, SPI_CMD_ACTIVE_SCLK_MASK |
155 SPI_CMD_ACTIVE_SDA_MASK, SPI_CMD_CS_SOFT | reg);
156 debug("%s: COMMAND = %08x\n", __func__, readl(®s->command));
157
158 /*
159 * SPI pins on Tegra20 are muxed - change pinmux later due to UART
160 * issue.
161 */
162 pinmux_set_func(PMUX_PINGRP_GMD, PMUX_FUNC_SFLASH);
163 pinmux_tristate_disable(PMUX_PINGRP_LSPI);
164 pinmux_set_func(PMUX_PINGRP_GMC, PMUX_FUNC_SFLASH);
165
166 return 0;
167 }
168
spi_cs_activate(struct udevice * dev)169 static void spi_cs_activate(struct udevice *dev)
170 {
171 struct udevice *bus = dev->parent;
172 struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
173 struct tegra20_sflash_priv *priv = dev_get_priv(bus);
174
175 /* If it's too soon to do another transaction, wait */
176 if (pdata->deactivate_delay_us &&
177 priv->last_transaction_us) {
178 ulong delay_us; /* The delay completed so far */
179 delay_us = timer_get_us() - priv->last_transaction_us;
180 if (delay_us < pdata->deactivate_delay_us)
181 udelay(pdata->deactivate_delay_us - delay_us);
182 }
183
184 /* CS is negated on Tegra, so drive a 1 to get a 0 */
185 setbits_le32(&priv->regs->command, SPI_CMD_CS_VAL);
186 }
187
spi_cs_deactivate(struct udevice * dev)188 static void spi_cs_deactivate(struct udevice *dev)
189 {
190 struct udevice *bus = dev->parent;
191 struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
192 struct tegra20_sflash_priv *priv = dev_get_priv(bus);
193
194 /* CS is negated on Tegra, so drive a 0 to get a 1 */
195 clrbits_le32(&priv->regs->command, SPI_CMD_CS_VAL);
196
197 /* Remember time of this transaction so we can honour the bus delay */
198 if (pdata->deactivate_delay_us)
199 priv->last_transaction_us = timer_get_us();
200 }
201
tegra20_sflash_xfer(struct udevice * dev,unsigned int bitlen,const void * data_out,void * data_in,unsigned long flags)202 static int tegra20_sflash_xfer(struct udevice *dev, unsigned int bitlen,
203 const void *data_out, void *data_in,
204 unsigned long flags)
205 {
206 struct udevice *bus = dev->parent;
207 struct tegra20_sflash_priv *priv = dev_get_priv(bus);
208 struct spi_regs *regs = priv->regs;
209 u32 reg, tmpdout, tmpdin = 0;
210 const u8 *dout = data_out;
211 u8 *din = data_in;
212 int num_bytes;
213 int ret;
214
215 debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
216 __func__, bus->seq, spi_chip_select(dev), dout, din, bitlen);
217 if (bitlen % 8)
218 return -1;
219 num_bytes = bitlen / 8;
220
221 ret = 0;
222
223 reg = readl(®s->status);
224 writel(reg, ®s->status); /* Clear all SPI events via R/W */
225 debug("spi_xfer entry: STATUS = %08x\n", reg);
226
227 reg = readl(®s->command);
228 reg |= SPI_CMD_TXEN | SPI_CMD_RXEN;
229 writel(reg, ®s->command);
230 debug("spi_xfer: COMMAND = %08x\n", readl(®s->command));
231
232 if (flags & SPI_XFER_BEGIN)
233 spi_cs_activate(dev);
234
235 /* handle data in 32-bit chunks */
236 while (num_bytes > 0) {
237 int bytes;
238 int is_read = 0;
239 int tm, i;
240
241 tmpdout = 0;
242 bytes = (num_bytes > 4) ? 4 : num_bytes;
243
244 if (dout != NULL) {
245 for (i = 0; i < bytes; ++i)
246 tmpdout = (tmpdout << 8) | dout[i];
247 }
248
249 num_bytes -= bytes;
250 if (dout)
251 dout += bytes;
252
253 clrsetbits_le32(®s->command, SPI_CMD_BIT_LENGTH_MASK,
254 bytes * 8 - 1);
255 writel(tmpdout, ®s->tx_fifo);
256 setbits_le32(®s->command, SPI_CMD_GO);
257
258 /*
259 * Wait for SPI transmit FIFO to empty, or to time out.
260 * The RX FIFO status will be read and cleared last
261 */
262 for (tm = 0, is_read = 0; tm < SPI_TIMEOUT; ++tm) {
263 u32 status;
264
265 status = readl(®s->status);
266
267 /* We can exit when we've had both RX and TX activity */
268 if (is_read && (status & SPI_STAT_TXF_EMPTY))
269 break;
270
271 if ((status & (SPI_STAT_BSY | SPI_STAT_RDY)) !=
272 SPI_STAT_RDY)
273 tm++;
274
275 else if (!(status & SPI_STAT_RXF_EMPTY)) {
276 tmpdin = readl(®s->rx_fifo);
277 is_read = 1;
278
279 /* swap bytes read in */
280 if (din != NULL) {
281 for (i = bytes - 1; i >= 0; --i) {
282 din[i] = tmpdin & 0xff;
283 tmpdin >>= 8;
284 }
285 din += bytes;
286 }
287 }
288 }
289
290 if (tm >= SPI_TIMEOUT)
291 ret = tm;
292
293 /* clear ACK RDY, etc. bits */
294 writel(readl(®s->status), ®s->status);
295 }
296
297 if (flags & SPI_XFER_END)
298 spi_cs_deactivate(dev);
299
300 debug("spi_xfer: transfer ended. Value=%08x, status = %08x\n",
301 tmpdin, readl(®s->status));
302
303 if (ret) {
304 printf("spi_xfer: timeout during SPI transfer, tm %d\n", ret);
305 return -1;
306 }
307
308 return 0;
309 }
310
tegra20_sflash_set_speed(struct udevice * bus,uint speed)311 static int tegra20_sflash_set_speed(struct udevice *bus, uint speed)
312 {
313 struct tegra_spi_platdata *plat = bus->platdata;
314 struct tegra20_sflash_priv *priv = dev_get_priv(bus);
315
316 if (speed > plat->frequency)
317 speed = plat->frequency;
318 priv->freq = speed;
319 debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
320
321 return 0;
322 }
323
tegra20_sflash_set_mode(struct udevice * bus,uint mode)324 static int tegra20_sflash_set_mode(struct udevice *bus, uint mode)
325 {
326 struct tegra20_sflash_priv *priv = dev_get_priv(bus);
327
328 priv->mode = mode;
329 debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
330
331 return 0;
332 }
333
334 static const struct dm_spi_ops tegra20_sflash_ops = {
335 .claim_bus = tegra20_sflash_claim_bus,
336 .xfer = tegra20_sflash_xfer,
337 .set_speed = tegra20_sflash_set_speed,
338 .set_mode = tegra20_sflash_set_mode,
339 .cs_info = tegra20_sflash_cs_info,
340 };
341
342 static const struct udevice_id tegra20_sflash_ids[] = {
343 { .compatible = "nvidia,tegra20-sflash" },
344 { }
345 };
346
347 U_BOOT_DRIVER(tegra20_sflash) = {
348 .name = "tegra20_sflash",
349 .id = UCLASS_SPI,
350 .of_match = tegra20_sflash_ids,
351 .ops = &tegra20_sflash_ops,
352 .ofdata_to_platdata = tegra20_sflash_ofdata_to_platdata,
353 .platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata),
354 .priv_auto_alloc_size = sizeof(struct tegra20_sflash_priv),
355 .probe = tegra20_sflash_probe,
356 };
357