1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2005, Intec Automation Inc.
4 * Copyright (C) 2014, Freescale Semiconductor, Inc.
5 */
6
7 #include <linux/mtd/spi-nor.h>
8
9 #include "core.h"
10
11 /* flash_info mfr_flag. Used to read proprietary FSR register. */
12 #define USE_FSR BIT(0)
13
14 #define SPINOR_OP_RDFSR 0x70 /* Read flag status register */
15 #define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */
16 #define SPINOR_OP_MT_DTR_RD 0xfd /* Fast Read opcode in DTR mode */
17 #define SPINOR_OP_MT_RD_ANY_REG 0x85 /* Read volatile register */
18 #define SPINOR_OP_MT_WR_ANY_REG 0x81 /* Write volatile register */
19 #define SPINOR_REG_MT_CFR0V 0x00 /* For setting octal DTR mode */
20 #define SPINOR_REG_MT_CFR1V 0x01 /* For setting dummy cycles */
21 #define SPINOR_REG_MT_CFR1V_DEF 0x1f /* Default dummy cycles */
22 #define SPINOR_MT_OCT_DTR 0xe7 /* Enable Octal DTR. */
23 #define SPINOR_MT_EXSPI 0xff /* Enable Extended SPI (default) */
24
25 /* Flag Status Register bits */
26 #define FSR_READY BIT(7) /* Device status, 0 = Busy, 1 = Ready */
27 #define FSR_E_ERR BIT(5) /* Erase operation status */
28 #define FSR_P_ERR BIT(4) /* Program operation status */
29 #define FSR_PT_ERR BIT(1) /* Protection error bit */
30
31 /* Micron ST SPI NOR flash operations. */
32 #define MICRON_ST_NOR_WR_ANY_REG_OP(naddr, addr, ndata, buf) \
33 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 0), \
34 SPI_MEM_OP_ADDR(naddr, addr, 0), \
35 SPI_MEM_OP_NO_DUMMY, \
36 SPI_MEM_OP_DATA_OUT(ndata, buf, 0))
37
38 #define MICRON_ST_RDFSR_OP(buf) \
39 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDFSR, 0), \
40 SPI_MEM_OP_NO_ADDR, \
41 SPI_MEM_OP_NO_DUMMY, \
42 SPI_MEM_OP_DATA_IN(1, buf, 0))
43
44 #define MICRON_ST_CLFSR_OP \
45 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLFSR, 0), \
46 SPI_MEM_OP_NO_ADDR, \
47 SPI_MEM_OP_NO_DUMMY, \
48 SPI_MEM_OP_NO_DATA)
49
micron_st_nor_octal_dtr_en(struct spi_nor * nor)50 static int micron_st_nor_octal_dtr_en(struct spi_nor *nor)
51 {
52 struct spi_mem_op op;
53 u8 *buf = nor->bouncebuf;
54 int ret;
55 u8 addr_mode_nbytes = nor->params->addr_mode_nbytes;
56
57 /* Use 20 dummy cycles for memory array reads. */
58 *buf = 20;
59 op = (struct spi_mem_op)
60 MICRON_ST_NOR_WR_ANY_REG_OP(addr_mode_nbytes,
61 SPINOR_REG_MT_CFR1V, 1, buf);
62 ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto);
63 if (ret)
64 return ret;
65
66 buf[0] = SPINOR_MT_OCT_DTR;
67 op = (struct spi_mem_op)
68 MICRON_ST_NOR_WR_ANY_REG_OP(addr_mode_nbytes,
69 SPINOR_REG_MT_CFR0V, 1, buf);
70 ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto);
71 if (ret)
72 return ret;
73
74 /* Read flash ID to make sure the switch was successful. */
75 ret = spi_nor_read_id(nor, 0, 8, buf, SNOR_PROTO_8_8_8_DTR);
76 if (ret) {
77 dev_dbg(nor->dev, "error %d reading JEDEC ID after enabling 8D-8D-8D mode\n", ret);
78 return ret;
79 }
80
81 if (memcmp(buf, nor->info->id, nor->info->id_len))
82 return -EINVAL;
83
84 return 0;
85 }
86
micron_st_nor_octal_dtr_dis(struct spi_nor * nor)87 static int micron_st_nor_octal_dtr_dis(struct spi_nor *nor)
88 {
89 struct spi_mem_op op;
90 u8 *buf = nor->bouncebuf;
91 int ret;
92
93 /*
94 * The register is 1-byte wide, but 1-byte transactions are not allowed
95 * in 8D-8D-8D mode. The next register is the dummy cycle configuration
96 * register. Since the transaction needs to be at least 2 bytes wide,
97 * set the next register to its default value. This also makes sense
98 * because the value was changed when enabling 8D-8D-8D mode, it should
99 * be reset when disabling.
100 */
101 buf[0] = SPINOR_MT_EXSPI;
102 buf[1] = SPINOR_REG_MT_CFR1V_DEF;
103 op = (struct spi_mem_op)
104 MICRON_ST_NOR_WR_ANY_REG_OP(nor->addr_nbytes,
105 SPINOR_REG_MT_CFR0V, 2, buf);
106 ret = spi_nor_write_any_volatile_reg(nor, &op, SNOR_PROTO_8_8_8_DTR);
107 if (ret)
108 return ret;
109
110 /* Read flash ID to make sure the switch was successful. */
111 ret = spi_nor_read_id(nor, 0, 0, buf, SNOR_PROTO_1_1_1);
112 if (ret) {
113 dev_dbg(nor->dev, "error %d reading JEDEC ID after disabling 8D-8D-8D mode\n", ret);
114 return ret;
115 }
116
117 if (memcmp(buf, nor->info->id, nor->info->id_len))
118 return -EINVAL;
119
120 return 0;
121 }
122
micron_st_nor_set_octal_dtr(struct spi_nor * nor,bool enable)123 static int micron_st_nor_set_octal_dtr(struct spi_nor *nor, bool enable)
124 {
125 return enable ? micron_st_nor_octal_dtr_en(nor) :
126 micron_st_nor_octal_dtr_dis(nor);
127 }
128
mt35xu512aba_default_init(struct spi_nor * nor)129 static void mt35xu512aba_default_init(struct spi_nor *nor)
130 {
131 nor->params->set_octal_dtr = micron_st_nor_set_octal_dtr;
132 }
133
mt35xu512aba_post_sfdp_fixup(struct spi_nor * nor)134 static int mt35xu512aba_post_sfdp_fixup(struct spi_nor *nor)
135 {
136 /* Set the Fast Read settings. */
137 nor->params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8_DTR;
138 spi_nor_set_read_settings(&nor->params->reads[SNOR_CMD_READ_8_8_8_DTR],
139 0, 20, SPINOR_OP_MT_DTR_RD,
140 SNOR_PROTO_8_8_8_DTR);
141
142 nor->cmd_ext_type = SPI_NOR_EXT_REPEAT;
143 nor->params->rdsr_dummy = 8;
144 nor->params->rdsr_addr_nbytes = 0;
145
146 /*
147 * The BFPT quad enable field is set to a reserved value so the quad
148 * enable function is ignored by spi_nor_parse_bfpt(). Make sure we
149 * disable it.
150 */
151 nor->params->quad_enable = NULL;
152
153 return 0;
154 }
155
156 static const struct spi_nor_fixups mt35xu512aba_fixups = {
157 .default_init = mt35xu512aba_default_init,
158 .post_sfdp = mt35xu512aba_post_sfdp_fixup,
159 };
160
161 static const struct flash_info micron_nor_parts[] = {
162 { "mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512)
163 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_OCTAL_READ |
164 SPI_NOR_OCTAL_DTR_READ | SPI_NOR_OCTAL_DTR_PP)
165 FIXUP_FLAGS(SPI_NOR_4B_OPCODES | SPI_NOR_IO_MODE_EN_VOLATILE)
166 MFR_FLAGS(USE_FSR)
167 .fixups = &mt35xu512aba_fixups
168 },
169 { "mt35xu02g", INFO(0x2c5b1c, 0, 128 * 1024, 2048)
170 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_OCTAL_READ)
171 FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
172 MFR_FLAGS(USE_FSR)
173 },
174 };
175
176 static const struct flash_info st_nor_parts[] = {
177 { "n25q016a", INFO(0x20bb15, 0, 64 * 1024, 32)
178 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) },
179 { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64)
180 NO_SFDP_FLAGS(SPI_NOR_QUAD_READ) },
181 { "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64)
182 NO_SFDP_FLAGS(SPI_NOR_QUAD_READ) },
183 { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128)
184 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) },
185 { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128)
186 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) },
187 { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256)
188 FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
189 SPI_NOR_BP3_SR_BIT6)
190 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ)
191 MFR_FLAGS(USE_FSR)
192 },
193 { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256)
194 FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
195 SPI_NOR_BP3_SR_BIT6)
196 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ)
197 MFR_FLAGS(USE_FSR)
198 },
199 { "mt25ql256a", INFO6(0x20ba19, 0x104400, 64 * 1024, 512)
200 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
201 FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
202 MFR_FLAGS(USE_FSR)
203 },
204 { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512)
205 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
206 SPI_NOR_QUAD_READ)
207 MFR_FLAGS(USE_FSR)
208 },
209 { "mt25qu256a", INFO6(0x20bb19, 0x104400, 64 * 1024, 512)
210 FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
211 SPI_NOR_BP3_SR_BIT6)
212 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
213 FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
214 MFR_FLAGS(USE_FSR)
215 },
216 { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512)
217 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ)
218 MFR_FLAGS(USE_FSR)
219 },
220 { "mt25ql512a", INFO6(0x20ba20, 0x104400, 64 * 1024, 1024)
221 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
222 FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
223 MFR_FLAGS(USE_FSR)
224 },
225 { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024)
226 FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
227 SPI_NOR_BP3_SR_BIT6)
228 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ)
229 MFR_FLAGS(USE_FSR)
230 },
231 { "mt25qu512a", INFO6(0x20bb20, 0x104400, 64 * 1024, 1024)
232 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
233 FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
234 MFR_FLAGS(USE_FSR)
235 },
236 { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024)
237 FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
238 SPI_NOR_BP3_SR_BIT6)
239 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ)
240 MFR_FLAGS(USE_FSR)
241 },
242 { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048)
243 FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
244 SPI_NOR_BP3_SR_BIT6 | NO_CHIP_ERASE)
245 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ)
246 MFR_FLAGS(USE_FSR)
247 },
248 { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048)
249 FLAGS(NO_CHIP_ERASE)
250 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ)
251 MFR_FLAGS(USE_FSR)
252 },
253 { "mt25ql02g", INFO(0x20ba22, 0, 64 * 1024, 4096)
254 FLAGS(NO_CHIP_ERASE)
255 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ)
256 MFR_FLAGS(USE_FSR)
257 },
258 { "mt25qu02g", INFO(0x20bb22, 0, 64 * 1024, 4096)
259 FLAGS(NO_CHIP_ERASE)
260 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
261 SPI_NOR_QUAD_READ)
262 MFR_FLAGS(USE_FSR)
263 },
264
265 { "m25p05", INFO(0x202010, 0, 32 * 1024, 2) },
266 { "m25p10", INFO(0x202011, 0, 32 * 1024, 4) },
267 { "m25p20", INFO(0x202012, 0, 64 * 1024, 4) },
268 { "m25p40", INFO(0x202013, 0, 64 * 1024, 8) },
269 { "m25p80", INFO(0x202014, 0, 64 * 1024, 16) },
270 { "m25p16", INFO(0x202015, 0, 64 * 1024, 32) },
271 { "m25p32", INFO(0x202016, 0, 64 * 1024, 64) },
272 { "m25p64", INFO(0x202017, 0, 64 * 1024, 128) },
273 { "m25p128", INFO(0x202018, 0, 256 * 1024, 64) },
274
275 { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2) },
276 { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4) },
277 { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4) },
278 { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8) },
279 { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16) },
280 { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32) },
281 { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64) },
282 { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128) },
283 { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64) },
284
285 { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2) },
286 { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16) },
287 { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32) },
288
289 { "m25pe20", INFO(0x208012, 0, 64 * 1024, 4) },
290 { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16) },
291 { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32)
292 NO_SFDP_FLAGS(SECT_4K) },
293
294 { "m25px16", INFO(0x207115, 0, 64 * 1024, 32)
295 NO_SFDP_FLAGS(SECT_4K) },
296 { "m25px32", INFO(0x207116, 0, 64 * 1024, 64)
297 NO_SFDP_FLAGS(SECT_4K) },
298 { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64)
299 NO_SFDP_FLAGS(SECT_4K) },
300 { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64)
301 NO_SFDP_FLAGS(SECT_4K) },
302 { "m25px64", INFO(0x207117, 0, 64 * 1024, 128) },
303 { "m25px80", INFO(0x207114, 0, 64 * 1024, 16) },
304 };
305
306 /**
307 * micron_st_nor_read_fsr() - Read the Flag Status Register.
308 * @nor: pointer to 'struct spi_nor'
309 * @fsr: pointer to a DMA-able buffer where the value of the
310 * Flag Status Register will be written. Should be at least 2
311 * bytes.
312 *
313 * Return: 0 on success, -errno otherwise.
314 */
micron_st_nor_read_fsr(struct spi_nor * nor,u8 * fsr)315 static int micron_st_nor_read_fsr(struct spi_nor *nor, u8 *fsr)
316 {
317 int ret;
318
319 if (nor->spimem) {
320 struct spi_mem_op op = MICRON_ST_RDFSR_OP(fsr);
321
322 if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) {
323 op.addr.nbytes = nor->params->rdsr_addr_nbytes;
324 op.dummy.nbytes = nor->params->rdsr_dummy;
325 /*
326 * We don't want to read only one byte in DTR mode. So,
327 * read 2 and then discard the second byte.
328 */
329 op.data.nbytes = 2;
330 }
331
332 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
333
334 ret = spi_mem_exec_op(nor->spimem, &op);
335 } else {
336 ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDFSR, fsr,
337 1);
338 }
339
340 if (ret)
341 dev_dbg(nor->dev, "error %d reading FSR\n", ret);
342
343 return ret;
344 }
345
346 /**
347 * micron_st_nor_clear_fsr() - Clear the Flag Status Register.
348 * @nor: pointer to 'struct spi_nor'.
349 */
micron_st_nor_clear_fsr(struct spi_nor * nor)350 static void micron_st_nor_clear_fsr(struct spi_nor *nor)
351 {
352 int ret;
353
354 if (nor->spimem) {
355 struct spi_mem_op op = MICRON_ST_CLFSR_OP;
356
357 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
358
359 ret = spi_mem_exec_op(nor->spimem, &op);
360 } else {
361 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_CLFSR,
362 NULL, 0);
363 }
364
365 if (ret)
366 dev_dbg(nor->dev, "error %d clearing FSR\n", ret);
367 }
368
369 /**
370 * micron_st_nor_ready() - Query the Status Register as well as the Flag Status
371 * Register to see if the flash is ready for new commands. If there are any
372 * errors in the FSR clear them.
373 * @nor: pointer to 'struct spi_nor'.
374 *
375 * Return: 1 if ready, 0 if not ready, -errno on errors.
376 */
micron_st_nor_ready(struct spi_nor * nor)377 static int micron_st_nor_ready(struct spi_nor *nor)
378 {
379 int sr_ready, ret;
380
381 sr_ready = spi_nor_sr_ready(nor);
382 if (sr_ready < 0)
383 return sr_ready;
384
385 ret = micron_st_nor_read_fsr(nor, nor->bouncebuf);
386 if (ret) {
387 /*
388 * Some controllers, such as Intel SPI, do not support low
389 * level operations such as reading the flag status
390 * register. They only expose small amount of high level
391 * operations to the software. If this is the case we use
392 * only the status register value.
393 */
394 return ret == -EOPNOTSUPP ? sr_ready : ret;
395 }
396
397 if (nor->bouncebuf[0] & (FSR_E_ERR | FSR_P_ERR)) {
398 if (nor->bouncebuf[0] & FSR_E_ERR)
399 dev_err(nor->dev, "Erase operation failed.\n");
400 else
401 dev_err(nor->dev, "Program operation failed.\n");
402
403 if (nor->bouncebuf[0] & FSR_PT_ERR)
404 dev_err(nor->dev,
405 "Attempted to modify a protected sector.\n");
406
407 micron_st_nor_clear_fsr(nor);
408
409 /*
410 * WEL bit remains set to one when an erase or page program
411 * error occurs. Issue a Write Disable command to protect
412 * against inadvertent writes that can possibly corrupt the
413 * contents of the memory.
414 */
415 ret = spi_nor_write_disable(nor);
416 if (ret)
417 return ret;
418
419 return -EIO;
420 }
421
422 return sr_ready && !!(nor->bouncebuf[0] & FSR_READY);
423 }
424
micron_st_nor_default_init(struct spi_nor * nor)425 static void micron_st_nor_default_init(struct spi_nor *nor)
426 {
427 nor->flags |= SNOR_F_HAS_LOCK;
428 nor->flags &= ~SNOR_F_HAS_16BIT_SR;
429 nor->params->quad_enable = NULL;
430 }
431
micron_st_nor_late_init(struct spi_nor * nor)432 static int micron_st_nor_late_init(struct spi_nor *nor)
433 {
434 struct spi_nor_flash_parameter *params = nor->params;
435
436 if (nor->info->mfr_flags & USE_FSR)
437 params->ready = micron_st_nor_ready;
438
439 if (!params->set_4byte_addr_mode)
440 params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode_wren_en4b_ex4b;
441
442 return 0;
443 }
444
445 static const struct spi_nor_fixups micron_st_nor_fixups = {
446 .default_init = micron_st_nor_default_init,
447 .late_init = micron_st_nor_late_init,
448 };
449
450 const struct spi_nor_manufacturer spi_nor_micron = {
451 .name = "micron",
452 .parts = micron_nor_parts,
453 .nparts = ARRAY_SIZE(micron_nor_parts),
454 .fixups = µn_st_nor_fixups,
455 };
456
457 const struct spi_nor_manufacturer spi_nor_st = {
458 .name = "st",
459 .parts = st_nor_parts,
460 .nparts = ARRAY_SIZE(st_nor_parts),
461 .fixups = µn_st_nor_fixups,
462 };
463