1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2014 Freescale Semiconductor, Inc.
4 * Synced from Linux v4.19
5 */
6
7 #ifndef __LINUX_MTD_SPI_NOR_H
8 #define __LINUX_MTD_SPI_NOR_H
9
10 #include <linux/bitops.h>
11 #include <linux/mtd/cfi.h>
12 #include <linux/mtd/mtd.h>
13
14 /*
15 * Manufacturer IDs
16 *
17 * The first byte returned from the flash after sending opcode SPINOR_OP_RDID.
18 * Sometimes these are the same as CFI IDs, but sometimes they aren't.
19 */
20 #define SNOR_MFR_ATMEL CFI_MFR_ATMEL
21 #define SNOR_MFR_GIGADEVICE 0xc8
22 #define SNOR_MFR_INTEL CFI_MFR_INTEL
23 #define SNOR_MFR_ST CFI_MFR_ST /* ST Micro <--> Micron */
24 #define SNOR_MFR_MICRON CFI_MFR_MICRON /* ST Micro <--> Micron */
25 #define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX
26 #define SNOR_MFR_SPANSION CFI_MFR_AMD
27 #define SNOR_MFR_SST CFI_MFR_SST
28 #define SNOR_MFR_WINBOND 0xef /* Also used by some Spansion */
29 #define SNOR_MFR_ISSI 0x9d
30 #define SNOR_MFR_CYPRESS 0x34
31
32 /*
33 * Note on opcode nomenclature: some opcodes have a format like
34 * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number
35 * of I/O lines used for the opcode, address, and data (respectively). The
36 * FUNCTION has an optional suffix of '4', to represent an opcode which
37 * requires a 4-byte (32-bit) address.
38 */
39
40 /* Flash opcodes. */
41 #define SPINOR_OP_WREN 0x06 /* Write enable */
42 #define SPINOR_OP_RDSR 0x05 /* Read status register */
43 #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */
44 #define SPINOR_OP_RDSR2 0x3f /* Read status register 2 */
45 #define SPINOR_OP_WRSR2 0x3e /* Write status register 2 */
46 #define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */
47 #define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */
48 #define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */
49 #define SPINOR_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */
50 #define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */
51 #define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */
52 #define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */
53 #define SPINOR_OP_PP_1_1_4 0x32 /* Quad page program */
54 #define SPINOR_OP_PP_1_4_4 0x38 /* Quad page program */
55 #define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */
56 #define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
57 #define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */
58 #define SPINOR_OP_CHIP_ERASE 0xc7 /* Erase whole flash chip */
59 #define SPINOR_OP_SE 0xd8 /* Sector erase (usually 64KiB) */
60 #define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */
61 #define SPINOR_OP_RDSFDP 0x5a /* Read SFDP */
62 #define SPINOR_OP_RDCR 0x35 /* Read configuration register */
63 #define SPINOR_OP_RDFSR 0x70 /* Read flag status register */
64 #define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */
65 #define SPINOR_OP_RDEAR 0xc8 /* Read Extended Address Register */
66 #define SPINOR_OP_WREAR 0xc5 /* Write Extended Address Register */
67
68 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
69 #define SPINOR_OP_READ_4B 0x13 /* Read data bytes (low frequency) */
70 #define SPINOR_OP_READ_FAST_4B 0x0c /* Read data bytes (high frequency) */
71 #define SPINOR_OP_READ_1_1_2_4B 0x3c /* Read data bytes (Dual Output SPI) */
72 #define SPINOR_OP_READ_1_2_2_4B 0xbc /* Read data bytes (Dual I/O SPI) */
73 #define SPINOR_OP_READ_1_1_4_4B 0x6c /* Read data bytes (Quad Output SPI) */
74 #define SPINOR_OP_READ_1_4_4_4B 0xec /* Read data bytes (Quad I/O SPI) */
75 #define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */
76 #define SPINOR_OP_PP_1_1_4_4B 0x34 /* Quad page program */
77 #define SPINOR_OP_PP_1_4_4_4B 0x3e /* Quad page program */
78 #define SPINOR_OP_BE_4K_4B 0x21 /* Erase 4KiB block */
79 #define SPINOR_OP_BE_32K_4B 0x5c /* Erase 32KiB block */
80 #define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */
81
82 /* Double Transfer Rate opcodes - defined in JEDEC JESD216B. */
83 #define SPINOR_OP_READ_1_1_1_DTR 0x0d
84 #define SPINOR_OP_READ_1_2_2_DTR 0xbd
85 #define SPINOR_OP_READ_1_4_4_DTR 0xed
86
87 #define SPINOR_OP_READ_1_1_1_DTR_4B 0x0e
88 #define SPINOR_OP_READ_1_2_2_DTR_4B 0xbe
89 #define SPINOR_OP_READ_1_4_4_DTR_4B 0xee
90
91 /* Used for SST flashes only. */
92 #define SPINOR_OP_BP 0x02 /* Byte program */
93 #define SPINOR_OP_WRDI 0x04 /* Write disable */
94 #define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */
95 #define SPINOR_OP_SST_RDNVCR 0xB5 /* Read nonvolatile configuration register */
96 #define SPINOR_OP_SST_WRNVCR 0xB1 /* Write nonvolatile configuration register */
97 #define SPINOR_SST_RST_HOLD_CTRL BIT(4)
98
99 /* Used for S3AN flashes only */
100 #define SPINOR_OP_XSE 0x50 /* Sector erase */
101 #define SPINOR_OP_XPP 0x82 /* Page program */
102 #define SPINOR_OP_XRDSR 0xd7 /* Read status register */
103
104 #define XSR_PAGESIZE BIT(0) /* Page size in Po2 or Linear */
105 #define XSR_RDY BIT(7) /* Ready */
106
107 /* Used for Macronix and Winbond flashes. */
108 #define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */
109 #define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */
110
111 #define SPINOR_OP_WINBOND_RDSR2 0x35
112 #define SPINOR_OP_WINBOND_WRSR2 0x31
113
114 /* Used for Spansion flashes only. */
115 #define SPINOR_OP_BRWR 0x17 /* Bank register write */
116 #define SPINOR_OP_BRRD 0x16 /* Bank register read */
117 #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */
118 #define SPINOR_OP_EX4B_CYPRESS 0xB8 /* Exit 4-byte mode */
119 #define SPINOR_OP_RDAR 0x65 /* Read any register */
120 #define SPINOR_OP_WRAR 0x71 /* Write any register */
121 #define SPINOR_REG_ADDR_STR1V 0x00800000
122 #define SPINOR_REG_ADDR_CFR1V 0x00800002
123 #define SPINOR_REG_ADDR_CFR3V 0x00800004
124 #define CFR3V_UNHYSA BIT(3) /* Uniform sectors or not */
125 #define CFR3V_PGMBUF BIT(4) /* Program buffer size */
126
127 /* Used for Micron flashes only. */
128 #define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */
129 #define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */
130 #define SPINOR_OP_MICRON_RDNVCR 0xB5 /* Read nonvolatile configuration register */
131 #define SPINOR_OP_MICRON_WRNVCR 0xB1 /* Write nonvolatile configuration register */
132
133 /* Status Register bits. */
134 #define SR_WIP BIT(0) /* Write in progress */
135 #define SR_WEL BIT(1) /* Write enable latch */
136 /* meaning of other SR_* bits may differ between vendors */
137 #define SR_BP0 BIT(2) /* Block protect 0 */
138 #define SR_BP1 BIT(3) /* Block protect 1 */
139 #define SR_BP2 BIT(4) /* Block protect 2 */
140 #define SR_TB BIT(5) /* Top/Bottom protect */
141 #define SR_SRWD BIT(7) /* SR write protect */
142 /* Spansion/Cypress specific status bits */
143 #define SR_E_ERR BIT(5)
144 #define SR_P_ERR BIT(6)
145
146 #define SR_QUAD_EN_MX BIT(6) /* Macronix Quad I/O */
147
148 /* Enhanced Volatile Configuration Register bits */
149 #define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */
150 #define MICRON_RST_HOLD_CTRL BIT(4)
151
152 /* Flag Status Register bits */
153 #define FSR_READY BIT(7) /* Device status, 0 = Busy, 1 = Ready */
154 #define FSR_E_ERR BIT(5) /* Erase operation status */
155 #define FSR_P_ERR BIT(4) /* Program operation status */
156 #define FSR_PT_ERR BIT(1) /* Protection error bit */
157
158 /* Configuration Register bits. */
159 #define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */
160
161 /* Status Register 2 bits. */
162 #define SR2_QUAD_EN_BIT7 BIT(7)
163 #define SR2_QUAD_EN_BIT1 BIT(1)
164
165 /* Supported SPI protocols */
166 #define SNOR_PROTO_INST_MASK GENMASK(23, 16)
167 #define SNOR_PROTO_INST_SHIFT 16
168 #define SNOR_PROTO_INST(_nbits) \
169 ((((unsigned long)(_nbits)) << SNOR_PROTO_INST_SHIFT) & \
170 SNOR_PROTO_INST_MASK)
171
172 #define SNOR_PROTO_ADDR_MASK GENMASK(15, 8)
173 #define SNOR_PROTO_ADDR_SHIFT 8
174 #define SNOR_PROTO_ADDR(_nbits) \
175 ((((unsigned long)(_nbits)) << SNOR_PROTO_ADDR_SHIFT) & \
176 SNOR_PROTO_ADDR_MASK)
177
178 #define SNOR_PROTO_DATA_MASK GENMASK(7, 0)
179 #define SNOR_PROTO_DATA_SHIFT 0
180 #define SNOR_PROTO_DATA(_nbits) \
181 ((((unsigned long)(_nbits)) << SNOR_PROTO_DATA_SHIFT) & \
182 SNOR_PROTO_DATA_MASK)
183
184 #define SNOR_PROTO_IS_DTR BIT(24) /* Double Transfer Rate */
185
186 #define SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits) \
187 (SNOR_PROTO_INST(_inst_nbits) | \
188 SNOR_PROTO_ADDR(_addr_nbits) | \
189 SNOR_PROTO_DATA(_data_nbits))
190 #define SNOR_PROTO_DTR(_inst_nbits, _addr_nbits, _data_nbits) \
191 (SNOR_PROTO_IS_DTR | \
192 SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits))
193
194 enum spi_nor_protocol {
195 SNOR_PROTO_1_1_1 = SNOR_PROTO_STR(1, 1, 1),
196 SNOR_PROTO_1_1_2 = SNOR_PROTO_STR(1, 1, 2),
197 SNOR_PROTO_1_1_4 = SNOR_PROTO_STR(1, 1, 4),
198 SNOR_PROTO_1_1_8 = SNOR_PROTO_STR(1, 1, 8),
199 SNOR_PROTO_1_2_2 = SNOR_PROTO_STR(1, 2, 2),
200 SNOR_PROTO_1_4_4 = SNOR_PROTO_STR(1, 4, 4),
201 SNOR_PROTO_1_8_8 = SNOR_PROTO_STR(1, 8, 8),
202 SNOR_PROTO_2_2_2 = SNOR_PROTO_STR(2, 2, 2),
203 SNOR_PROTO_4_4_4 = SNOR_PROTO_STR(4, 4, 4),
204 SNOR_PROTO_8_8_8 = SNOR_PROTO_STR(8, 8, 8),
205
206 SNOR_PROTO_1_1_1_DTR = SNOR_PROTO_DTR(1, 1, 1),
207 SNOR_PROTO_1_2_2_DTR = SNOR_PROTO_DTR(1, 2, 2),
208 SNOR_PROTO_1_4_4_DTR = SNOR_PROTO_DTR(1, 4, 4),
209 SNOR_PROTO_1_8_8_DTR = SNOR_PROTO_DTR(1, 8, 8),
210 };
211
spi_nor_protocol_is_dtr(enum spi_nor_protocol proto)212 static inline bool spi_nor_protocol_is_dtr(enum spi_nor_protocol proto)
213 {
214 return !!(proto & SNOR_PROTO_IS_DTR);
215 }
216
spi_nor_get_protocol_inst_nbits(enum spi_nor_protocol proto)217 static inline u8 spi_nor_get_protocol_inst_nbits(enum spi_nor_protocol proto)
218 {
219 return ((unsigned long)(proto & SNOR_PROTO_INST_MASK)) >>
220 SNOR_PROTO_INST_SHIFT;
221 }
222
spi_nor_get_protocol_addr_nbits(enum spi_nor_protocol proto)223 static inline u8 spi_nor_get_protocol_addr_nbits(enum spi_nor_protocol proto)
224 {
225 return ((unsigned long)(proto & SNOR_PROTO_ADDR_MASK)) >>
226 SNOR_PROTO_ADDR_SHIFT;
227 }
228
spi_nor_get_protocol_data_nbits(enum spi_nor_protocol proto)229 static inline u8 spi_nor_get_protocol_data_nbits(enum spi_nor_protocol proto)
230 {
231 return ((unsigned long)(proto & SNOR_PROTO_DATA_MASK)) >>
232 SNOR_PROTO_DATA_SHIFT;
233 }
234
spi_nor_get_protocol_width(enum spi_nor_protocol proto)235 static inline u8 spi_nor_get_protocol_width(enum spi_nor_protocol proto)
236 {
237 return spi_nor_get_protocol_data_nbits(proto);
238 }
239
240 #define SPI_NOR_MAX_CMD_SIZE 8
241 enum spi_nor_ops {
242 SPI_NOR_OPS_READ = 0,
243 SPI_NOR_OPS_WRITE,
244 SPI_NOR_OPS_ERASE,
245 SPI_NOR_OPS_LOCK,
246 SPI_NOR_OPS_UNLOCK,
247 };
248
249 enum spi_nor_option_flags {
250 SNOR_F_USE_FSR = BIT(0),
251 SNOR_F_HAS_SR_TB = BIT(1),
252 SNOR_F_NO_OP_CHIP_ERASE = BIT(2),
253 SNOR_F_S3AN_ADDR_DEFAULT = BIT(3),
254 SNOR_F_READY_XSR_RDY = BIT(4),
255 SNOR_F_USE_CLSR = BIT(5),
256 SNOR_F_BROKEN_RESET = BIT(6),
257 };
258
259 /**
260 * struct flash_info - Forward declaration of a structure used internally by
261 * spi_nor_scan()
262 */
263 struct flash_info;
264
265 /* TODO: Remove, once all users of spi_flash interface are moved to MTD */
266 #define spi_flash spi_nor
267
268 /**
269 * struct spi_nor - Structure for defining a the SPI NOR layer
270 * @mtd: point to a mtd_info structure
271 * @lock: the lock for the read/write/erase/lock/unlock operations
272 * @dev: point to a spi device, or a spi nor controller device.
273 * @info: spi-nor part JDEC MFR id and other info
274 * @page_size: the page size of the SPI NOR
275 * @addr_width: number of address bytes
276 * @erase_opcode: the opcode for erasing a sector
277 * @read_opcode: the read opcode
278 * @read_dummy: the dummy needed by the read operation
279 * @program_opcode: the program opcode
280 * @bank_read_cmd: Bank read cmd
281 * @bank_write_cmd: Bank write cmd
282 * @bank_curr: Current flash bank
283 * @sst_write_second: used by the SST write operation
284 * @flags: flag options for the current SPI-NOR (SNOR_F_*)
285 * @read_proto: the SPI protocol for read operations
286 * @write_proto: the SPI protocol for write operations
287 * @reg_proto the SPI protocol for read_reg/write_reg/erase operations
288 * @cmd_buf: used by the write_reg
289 * @prepare: [OPTIONAL] do some preparations for the
290 * read/write/erase/lock/unlock operations
291 * @unprepare: [OPTIONAL] do some post work after the
292 * read/write/erase/lock/unlock operations
293 * @read_reg: [DRIVER-SPECIFIC] read out the register
294 * @write_reg: [DRIVER-SPECIFIC] write data to the register
295 * @read: [DRIVER-SPECIFIC] read data from the SPI NOR
296 * @write: [DRIVER-SPECIFIC] write data to the SPI NOR
297 * @erase: [DRIVER-SPECIFIC] erase a sector of the SPI NOR
298 * at the offset @offs; if not provided by the driver,
299 * spi-nor will send the erase opcode via write_reg()
300 * @flash_lock: [FLASH-SPECIFIC] lock a region of the SPI NOR
301 * @flash_unlock: [FLASH-SPECIFIC] unlock a region of the SPI NOR
302 * @flash_is_locked: [FLASH-SPECIFIC] check if a region of the SPI NOR is
303 * @quad_enable: [FLASH-SPECIFIC] enables SPI NOR quad mode
304 * completely locked
305 * @priv: the private data
306 */
307 struct spi_nor {
308 struct mtd_info mtd;
309 struct udevice *dev;
310 struct spi_slave *spi;
311 const struct flash_info *info;
312 u32 page_size;
313 u8 addr_width;
314 u8 erase_opcode;
315 u8 read_opcode;
316 u8 read_dummy;
317 u8 program_opcode;
318 #ifdef CONFIG_SPI_FLASH_BAR
319 u8 bank_read_cmd;
320 u8 bank_write_cmd;
321 u8 bank_curr;
322 #endif
323 enum spi_nor_protocol read_proto;
324 enum spi_nor_protocol write_proto;
325 enum spi_nor_protocol reg_proto;
326 bool sst_write_second;
327 u32 flags;
328 u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE];
329
330 int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops);
331 void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops);
332 int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
333 int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
334
335 ssize_t (*read)(struct spi_nor *nor, loff_t from,
336 size_t len, u_char *read_buf);
337 ssize_t (*write)(struct spi_nor *nor, loff_t to,
338 size_t len, const u_char *write_buf);
339 int (*erase)(struct spi_nor *nor, loff_t offs);
340
341 int (*flash_lock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
342 int (*flash_unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
343 int (*flash_is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len);
344 int (*quad_enable)(struct spi_nor *nor);
345 int (*flash_lock_by_host_ctrl)(struct spi_nor *nor, u32 ofs, size_t len);
346 int (*flash_unlock_by_host_ctrl)(struct spi_nor *nor, u32 ofs, size_t len);
347
348 void *priv;
349 /* Compatibility for spi_flash, remove once sf layer is merged with mtd */
350 const char *name;
351 u32 size;
352 u32 sector_size;
353 u32 erase_size;
354 };
355
spi_nor_set_flash_node(struct spi_nor * nor,const struct device_node * np)356 static inline void spi_nor_set_flash_node(struct spi_nor *nor,
357 const struct device_node *np)
358 {
359 mtd_set_of_node(&nor->mtd, np);
360 }
361
362 static inline const struct
spi_nor_get_flash_node(struct spi_nor * nor)363 device_node *spi_nor_get_flash_node(struct spi_nor *nor)
364 {
365 return mtd_get_of_node(&nor->mtd);
366 }
367
368 /**
369 * struct spi_nor_hwcaps - Structure for describing the hardware capabilies
370 * supported by the SPI controller (bus master).
371 * @mask: the bitmask listing all the supported hw capabilies
372 */
373 struct spi_nor_hwcaps {
374 u32 mask;
375 };
376
377 /*
378 *(Fast) Read capabilities.
379 * MUST be ordered by priority: the higher bit position, the higher priority.
380 * As a matter of performances, it is relevant to use Octo SPI protocols first,
381 * then Quad SPI protocols before Dual SPI protocols, Fast Read and lastly
382 * (Slow) Read.
383 */
384 #define SNOR_HWCAPS_READ_MASK GENMASK(14, 0)
385 #define SNOR_HWCAPS_READ BIT(0)
386 #define SNOR_HWCAPS_READ_FAST BIT(1)
387 #define SNOR_HWCAPS_READ_1_1_1_DTR BIT(2)
388
389 #define SNOR_HWCAPS_READ_DUAL GENMASK(6, 3)
390 #define SNOR_HWCAPS_READ_1_1_2 BIT(3)
391 #define SNOR_HWCAPS_READ_1_2_2 BIT(4)
392 #define SNOR_HWCAPS_READ_2_2_2 BIT(5)
393 #define SNOR_HWCAPS_READ_1_2_2_DTR BIT(6)
394
395 #define SNOR_HWCAPS_READ_QUAD GENMASK(10, 7)
396 #define SNOR_HWCAPS_READ_1_1_4 BIT(7)
397 #define SNOR_HWCAPS_READ_1_4_4 BIT(8)
398 #define SNOR_HWCAPS_READ_4_4_4 BIT(9)
399 #define SNOR_HWCAPS_READ_1_4_4_DTR BIT(10)
400
401 #define SNOR_HWCPAS_READ_OCTO GENMASK(14, 11)
402 #define SNOR_HWCAPS_READ_1_1_8 BIT(11)
403 #define SNOR_HWCAPS_READ_1_8_8 BIT(12)
404 #define SNOR_HWCAPS_READ_8_8_8 BIT(13)
405 #define SNOR_HWCAPS_READ_1_8_8_DTR BIT(14)
406
407 /*
408 * Page Program capabilities.
409 * MUST be ordered by priority: the higher bit position, the higher priority.
410 * Like (Fast) Read capabilities, Octo/Quad SPI protocols are preferred to the
411 * legacy SPI 1-1-1 protocol.
412 * Note that Dual Page Programs are not supported because there is no existing
413 * JEDEC/SFDP standard to define them. Also at this moment no SPI flash memory
414 * implements such commands.
415 */
416 #define SNOR_HWCAPS_PP_MASK GENMASK(22, 16)
417 #define SNOR_HWCAPS_PP BIT(16)
418
419 #define SNOR_HWCAPS_PP_QUAD GENMASK(19, 17)
420 #define SNOR_HWCAPS_PP_1_1_4 BIT(17)
421 #define SNOR_HWCAPS_PP_1_4_4 BIT(18)
422 #define SNOR_HWCAPS_PP_4_4_4 BIT(19)
423
424 #define SNOR_HWCAPS_PP_OCTO GENMASK(22, 20)
425 #define SNOR_HWCAPS_PP_1_1_8 BIT(20)
426 #define SNOR_HWCAPS_PP_1_8_8 BIT(21)
427 #define SNOR_HWCAPS_PP_8_8_8 BIT(22)
428
429 /**
430 * spi_nor_scan() - scan the SPI NOR
431 * @nor: the spi_nor structure
432 *
433 * The drivers can use this function to scan the SPI NOR.
434 * In the scanning, it will try to get all the necessary information to
435 * fill the mtd_info{} and the spi_nor{}.
436 *
437 * Return: 0 for success, others for failure.
438 */
439 int spi_nor_scan(struct spi_nor *nor);
440
441 #endif
442