xref: /openbmc/linux/drivers/i2c/busses/i2c-brcmstb.c (revision f9dce8d6)
1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (C) 2014 Broadcom Corporation
3 
4 #include <linux/clk.h>
5 #include <linux/delay.h>
6 #include <linux/device.h>
7 #include <linux/i2c.h>
8 #include <linux/interrupt.h>
9 #include <linux/io.h>
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/platform_device.h>
13 #include <linux/sched.h>
14 #include <linux/slab.h>
15 
16 #define N_DATA_REGS					8
17 
18 /*
19  * PER_I2C/BSC count register mask depends on 1 byte/4 byte data register
20  * size. Cable modem and DSL SoCs with Peripheral i2c cores use 1 byte per
21  * data register whereas STB SoCs use 4 byte per data register transfer,
22  * account for this difference in total count per transaction and mask to
23  * use.
24  */
25 #define BSC_CNT_REG1_MASK(nb)	(nb == 1 ? GENMASK(3, 0) : GENMASK(5, 0))
26 #define BSC_CNT_REG1_SHIFT	0
27 
28 /* BSC CTL register field definitions */
29 #define BSC_CTL_REG_DTF_MASK				0x00000003
30 #define BSC_CTL_REG_SCL_SEL_MASK			0x00000030
31 #define BSC_CTL_REG_SCL_SEL_SHIFT			4
32 #define BSC_CTL_REG_INT_EN_MASK				0x00000040
33 #define BSC_CTL_REG_INT_EN_SHIFT			6
34 #define BSC_CTL_REG_DIV_CLK_MASK			0x00000080
35 
36 /* BSC_IIC_ENABLE r/w enable and interrupt field definitions */
37 #define BSC_IIC_EN_RESTART_MASK				0x00000040
38 #define BSC_IIC_EN_NOSTART_MASK				0x00000020
39 #define BSC_IIC_EN_NOSTOP_MASK				0x00000010
40 #define BSC_IIC_EN_NOACK_MASK				0x00000004
41 #define BSC_IIC_EN_INTRP_MASK				0x00000002
42 #define BSC_IIC_EN_ENABLE_MASK				0x00000001
43 
44 /* BSC_CTLHI control register field definitions */
45 #define BSC_CTLHI_REG_INPUT_SWITCHING_LEVEL_MASK	0x00000080
46 #define BSC_CTLHI_REG_DATAREG_SIZE_MASK			0x00000040
47 #define BSC_CTLHI_REG_IGNORE_ACK_MASK			0x00000002
48 #define BSC_CTLHI_REG_WAIT_DIS_MASK			0x00000001
49 
50 #define I2C_TIMEOUT					100 /* msecs */
51 
52 /* Condition mask used for non combined transfer */
53 #define COND_RESTART		BSC_IIC_EN_RESTART_MASK
54 #define COND_NOSTART		BSC_IIC_EN_NOSTART_MASK
55 #define COND_NOSTOP		BSC_IIC_EN_NOSTOP_MASK
56 #define COND_START_STOP		(COND_RESTART | COND_NOSTART | COND_NOSTOP)
57 
58 /* BSC data transfer direction */
59 #define DTF_WR_MASK		0x00000000
60 #define DTF_RD_MASK		0x00000001
61 /* BSC data transfer direction combined format */
62 #define DTF_RD_WR_MASK		0x00000002
63 #define DTF_WR_RD_MASK		0x00000003
64 
65 #define INT_ENABLE		true
66 #define INT_DISABLE		false
67 
68 /* BSC block register map structure to cache fields to be written */
69 struct bsc_regs {
70 	u32	chip_address;           /* slave address */
71 	u32	data_in[N_DATA_REGS];   /* tx data buffer*/
72 	u32	cnt_reg;		/* rx/tx data length */
73 	u32	ctl_reg;		/* control register */
74 	u32	iic_enable;		/* xfer enable and status */
75 	u32	data_out[N_DATA_REGS];  /* rx data buffer */
76 	u32	ctlhi_reg;		/* more control fields */
77 	u32	scl_param;		/* reserved */
78 };
79 
80 struct bsc_clk_param {
81 	u32 hz;
82 	u32 scl_mask;
83 	u32 div_mask;
84 };
85 
86 enum bsc_xfer_cmd {
87 	CMD_WR,
88 	CMD_RD,
89 	CMD_WR_NOACK,
90 	CMD_RD_NOACK,
91 };
92 
93 static char const *cmd_string[] = {
94 	[CMD_WR] = "WR",
95 	[CMD_RD] = "RD",
96 	[CMD_WR_NOACK] = "WR NOACK",
97 	[CMD_RD_NOACK] = "RD NOACK",
98 };
99 
100 enum bus_speeds {
101 	SPD_375K,
102 	SPD_390K,
103 	SPD_187K,
104 	SPD_200K,
105 	SPD_93K,
106 	SPD_97K,
107 	SPD_46K,
108 	SPD_50K
109 };
110 
111 static const struct bsc_clk_param bsc_clk[] = {
112 	[SPD_375K] = {
113 		.hz = 375000,
114 		.scl_mask = SPD_375K << BSC_CTL_REG_SCL_SEL_SHIFT,
115 		.div_mask = 0
116 	},
117 	[SPD_390K] = {
118 		.hz = 390000,
119 		.scl_mask = SPD_390K << BSC_CTL_REG_SCL_SEL_SHIFT,
120 		.div_mask = 0
121 	},
122 	[SPD_187K] = {
123 		.hz = 187500,
124 		.scl_mask = SPD_187K << BSC_CTL_REG_SCL_SEL_SHIFT,
125 		.div_mask = 0
126 	},
127 	[SPD_200K] = {
128 		.hz = 200000,
129 		.scl_mask = SPD_200K << BSC_CTL_REG_SCL_SEL_SHIFT,
130 		.div_mask = 0
131 	},
132 	[SPD_93K]  = {
133 		.hz = 93750,
134 		.scl_mask = SPD_375K << BSC_CTL_REG_SCL_SEL_SHIFT,
135 		.div_mask = BSC_CTL_REG_DIV_CLK_MASK
136 	},
137 	[SPD_97K]  = {
138 		.hz = 97500,
139 		.scl_mask = SPD_390K << BSC_CTL_REG_SCL_SEL_SHIFT,
140 		.div_mask = BSC_CTL_REG_DIV_CLK_MASK
141 	},
142 	[SPD_46K]  = {
143 		.hz = 46875,
144 		.scl_mask = SPD_187K << BSC_CTL_REG_SCL_SEL_SHIFT,
145 		.div_mask = BSC_CTL_REG_DIV_CLK_MASK
146 	},
147 	[SPD_50K]  = {
148 		.hz = 50000,
149 		.scl_mask = SPD_200K << BSC_CTL_REG_SCL_SEL_SHIFT,
150 		.div_mask = BSC_CTL_REG_DIV_CLK_MASK
151 	}
152 };
153 
154 struct brcmstb_i2c_dev {
155 	struct device *device;
156 	void __iomem *base;
157 	int irq;
158 	struct bsc_regs *bsc_regmap;
159 	struct i2c_adapter adapter;
160 	struct completion done;
161 	u32 clk_freq_hz;
162 	int data_regsz;
163 };
164 
165 /* register accessors for both be and le cpu arch */
166 #ifdef CONFIG_CPU_BIG_ENDIAN
167 #define __bsc_readl(_reg) ioread32be(_reg)
168 #define __bsc_writel(_val, _reg) iowrite32be(_val, _reg)
169 #else
170 #define __bsc_readl(_reg) ioread32(_reg)
171 #define __bsc_writel(_val, _reg) iowrite32(_val, _reg)
172 #endif
173 
174 #define bsc_readl(_dev, _reg)						\
175 	__bsc_readl(_dev->base + offsetof(struct bsc_regs, _reg))
176 
177 #define bsc_writel(_dev, _val, _reg)					\
178 	__bsc_writel(_val, _dev->base + offsetof(struct bsc_regs, _reg))
179 
brcmstb_i2c_get_xfersz(struct brcmstb_i2c_dev * dev)180 static inline int brcmstb_i2c_get_xfersz(struct brcmstb_i2c_dev *dev)
181 {
182 	return (N_DATA_REGS * dev->data_regsz);
183 }
184 
brcmstb_i2c_get_data_regsz(struct brcmstb_i2c_dev * dev)185 static inline int brcmstb_i2c_get_data_regsz(struct brcmstb_i2c_dev *dev)
186 {
187 	return dev->data_regsz;
188 }
189 
brcmstb_i2c_enable_disable_irq(struct brcmstb_i2c_dev * dev,bool int_en)190 static void brcmstb_i2c_enable_disable_irq(struct brcmstb_i2c_dev *dev,
191 					   bool int_en)
192 {
193 
194 	if (int_en)
195 		/* Enable BSC  CTL interrupt line */
196 		dev->bsc_regmap->ctl_reg |= BSC_CTL_REG_INT_EN_MASK;
197 	else
198 		/* Disable BSC CTL interrupt line */
199 		dev->bsc_regmap->ctl_reg &= ~BSC_CTL_REG_INT_EN_MASK;
200 
201 	barrier();
202 	bsc_writel(dev, dev->bsc_regmap->ctl_reg, ctl_reg);
203 }
204 
brcmstb_i2c_isr(int irq,void * devid)205 static irqreturn_t brcmstb_i2c_isr(int irq, void *devid)
206 {
207 	struct brcmstb_i2c_dev *dev = devid;
208 	u32 status_bsc_ctl = bsc_readl(dev, ctl_reg);
209 	u32 status_iic_intrp = bsc_readl(dev, iic_enable);
210 
211 	dev_dbg(dev->device, "isr CTL_REG %x IIC_EN %x\n",
212 		status_bsc_ctl, status_iic_intrp);
213 
214 	if (!(status_bsc_ctl & BSC_CTL_REG_INT_EN_MASK))
215 		return IRQ_NONE;
216 
217 	brcmstb_i2c_enable_disable_irq(dev, INT_DISABLE);
218 	complete(&dev->done);
219 
220 	dev_dbg(dev->device, "isr handled");
221 	return IRQ_HANDLED;
222 }
223 
224 /* Wait for device to be ready */
brcmstb_i2c_wait_if_busy(struct brcmstb_i2c_dev * dev)225 static int brcmstb_i2c_wait_if_busy(struct brcmstb_i2c_dev *dev)
226 {
227 	unsigned long timeout = jiffies + msecs_to_jiffies(I2C_TIMEOUT);
228 
229 	while ((bsc_readl(dev, iic_enable) & BSC_IIC_EN_INTRP_MASK)) {
230 		if (time_after(jiffies, timeout))
231 			return -ETIMEDOUT;
232 		cpu_relax();
233 	}
234 	return 0;
235 }
236 
237 /* i2c xfer completion function, handles both irq and polling mode */
brcmstb_i2c_wait_for_completion(struct brcmstb_i2c_dev * dev)238 static int brcmstb_i2c_wait_for_completion(struct brcmstb_i2c_dev *dev)
239 {
240 	int ret = 0;
241 	unsigned long timeout = msecs_to_jiffies(I2C_TIMEOUT);
242 
243 	if (dev->irq >= 0) {
244 		if (!wait_for_completion_timeout(&dev->done, timeout))
245 			ret = -ETIMEDOUT;
246 	} else {
247 		/* we are in polling mode */
248 		u32 bsc_intrp;
249 		unsigned long time_left = jiffies + timeout;
250 
251 		do {
252 			bsc_intrp = bsc_readl(dev, iic_enable) &
253 				BSC_IIC_EN_INTRP_MASK;
254 			if (time_after(jiffies, time_left)) {
255 				ret = -ETIMEDOUT;
256 				break;
257 			}
258 			cpu_relax();
259 		} while (!bsc_intrp);
260 	}
261 
262 	if (dev->irq < 0 || ret == -ETIMEDOUT)
263 		brcmstb_i2c_enable_disable_irq(dev, INT_DISABLE);
264 
265 	return ret;
266 }
267 
268 /* Set xfer START/STOP conditions for subsequent transfer */
brcmstb_set_i2c_start_stop(struct brcmstb_i2c_dev * dev,u32 cond_flag)269 static void brcmstb_set_i2c_start_stop(struct brcmstb_i2c_dev *dev,
270 				       u32 cond_flag)
271 {
272 	u32 regval = dev->bsc_regmap->iic_enable;
273 
274 	dev->bsc_regmap->iic_enable = (regval & ~COND_START_STOP) | cond_flag;
275 }
276 
277 /* Send I2C request check completion */
brcmstb_send_i2c_cmd(struct brcmstb_i2c_dev * dev,enum bsc_xfer_cmd cmd)278 static int brcmstb_send_i2c_cmd(struct brcmstb_i2c_dev *dev,
279 				enum bsc_xfer_cmd cmd)
280 {
281 	int rc = 0;
282 	struct bsc_regs *pi2creg = dev->bsc_regmap;
283 
284 	/* Make sure the hardware is ready */
285 	rc = brcmstb_i2c_wait_if_busy(dev);
286 	if (rc < 0)
287 		return rc;
288 
289 	/* only if we are in interrupt mode */
290 	if (dev->irq >= 0)
291 		reinit_completion(&dev->done);
292 
293 	/* enable BSC CTL interrupt line */
294 	brcmstb_i2c_enable_disable_irq(dev, INT_ENABLE);
295 
296 	/* initiate transfer by setting iic_enable */
297 	pi2creg->iic_enable |= BSC_IIC_EN_ENABLE_MASK;
298 	bsc_writel(dev, pi2creg->iic_enable, iic_enable);
299 
300 	/* Wait for transaction to finish or timeout */
301 	rc = brcmstb_i2c_wait_for_completion(dev);
302 	if (rc) {
303 		dev_dbg(dev->device, "intr timeout for cmd %s\n",
304 			cmd_string[cmd]);
305 		goto cmd_out;
306 	}
307 
308 	if ((cmd == CMD_RD || cmd == CMD_WR) &&
309 	    bsc_readl(dev, iic_enable) & BSC_IIC_EN_NOACK_MASK) {
310 		rc = -EREMOTEIO;
311 		dev_dbg(dev->device, "controller received NOACK intr for %s\n",
312 			cmd_string[cmd]);
313 	}
314 
315 cmd_out:
316 	bsc_writel(dev, 0, cnt_reg);
317 	bsc_writel(dev, 0, iic_enable);
318 
319 	return rc;
320 }
321 
322 /* Actual data transfer through the BSC master */
brcmstb_i2c_xfer_bsc_data(struct brcmstb_i2c_dev * dev,u8 * buf,unsigned int len,struct i2c_msg * pmsg)323 static int brcmstb_i2c_xfer_bsc_data(struct brcmstb_i2c_dev *dev,
324 				     u8 *buf, unsigned int len,
325 				     struct i2c_msg *pmsg)
326 {
327 	int cnt, byte, i, rc;
328 	enum bsc_xfer_cmd cmd;
329 	u32 ctl_reg;
330 	struct bsc_regs *pi2creg = dev->bsc_regmap;
331 	int no_ack = pmsg->flags & I2C_M_IGNORE_NAK;
332 	int data_regsz = brcmstb_i2c_get_data_regsz(dev);
333 
334 	/* see if the transaction needs to check NACK conditions */
335 	if (no_ack) {
336 		cmd = (pmsg->flags & I2C_M_RD) ? CMD_RD_NOACK
337 			: CMD_WR_NOACK;
338 		pi2creg->ctlhi_reg |= BSC_CTLHI_REG_IGNORE_ACK_MASK;
339 	} else {
340 		cmd = (pmsg->flags & I2C_M_RD) ? CMD_RD : CMD_WR;
341 		pi2creg->ctlhi_reg &= ~BSC_CTLHI_REG_IGNORE_ACK_MASK;
342 	}
343 	bsc_writel(dev, pi2creg->ctlhi_reg, ctlhi_reg);
344 
345 	/* set data transfer direction */
346 	ctl_reg = pi2creg->ctl_reg & ~BSC_CTL_REG_DTF_MASK;
347 	if (cmd == CMD_WR || cmd == CMD_WR_NOACK)
348 		pi2creg->ctl_reg = ctl_reg | DTF_WR_MASK;
349 	else
350 		pi2creg->ctl_reg = ctl_reg | DTF_RD_MASK;
351 
352 	/* set the read/write length */
353 	bsc_writel(dev, BSC_CNT_REG1_MASK(data_regsz) &
354 		   (len << BSC_CNT_REG1_SHIFT), cnt_reg);
355 
356 	/* Write data into data_in register */
357 
358 	if (cmd == CMD_WR || cmd == CMD_WR_NOACK) {
359 		for (cnt = 0, i = 0; cnt < len; cnt += data_regsz, i++) {
360 			u32 word = 0;
361 
362 			for (byte = 0; byte < data_regsz; byte++) {
363 				word >>= BITS_PER_BYTE;
364 				if ((cnt + byte) < len)
365 					word |= buf[cnt + byte] <<
366 					(BITS_PER_BYTE * (data_regsz - 1));
367 			}
368 			bsc_writel(dev, word, data_in[i]);
369 		}
370 	}
371 
372 	/* Initiate xfer, the function will return on completion */
373 	rc = brcmstb_send_i2c_cmd(dev, cmd);
374 
375 	if (rc != 0) {
376 		dev_dbg(dev->device, "%s failure", cmd_string[cmd]);
377 		return rc;
378 	}
379 
380 	/* Read data from data_out register */
381 	if (cmd == CMD_RD || cmd == CMD_RD_NOACK) {
382 		for (cnt = 0, i = 0; cnt < len; cnt += data_regsz, i++) {
383 			u32 data = bsc_readl(dev, data_out[i]);
384 
385 			for (byte = 0; byte < data_regsz &&
386 				     (byte + cnt) < len; byte++) {
387 				buf[cnt + byte] = data & 0xff;
388 				data >>= BITS_PER_BYTE;
389 			}
390 		}
391 	}
392 
393 	return 0;
394 }
395 
396 /* Write a single byte of data to the i2c bus */
brcmstb_i2c_write_data_byte(struct brcmstb_i2c_dev * dev,u8 * buf,unsigned int nak_expected)397 static int brcmstb_i2c_write_data_byte(struct brcmstb_i2c_dev *dev,
398 				       u8 *buf, unsigned int nak_expected)
399 {
400 	enum bsc_xfer_cmd cmd = nak_expected ? CMD_WR : CMD_WR_NOACK;
401 
402 	bsc_writel(dev, 1, cnt_reg);
403 	bsc_writel(dev, *buf, data_in);
404 
405 	return brcmstb_send_i2c_cmd(dev, cmd);
406 }
407 
408 /* Send i2c address */
brcmstb_i2c_do_addr(struct brcmstb_i2c_dev * dev,struct i2c_msg * msg)409 static int brcmstb_i2c_do_addr(struct brcmstb_i2c_dev *dev,
410 			       struct i2c_msg *msg)
411 {
412 	unsigned char addr;
413 
414 	if (msg->flags & I2C_M_TEN) {
415 		/* First byte is 11110XX0 where XX is upper 2 bits */
416 		addr = 0xF0 | ((msg->addr & 0x300) >> 7);
417 		bsc_writel(dev, addr, chip_address);
418 
419 		/* Second byte is the remaining 8 bits */
420 		addr = msg->addr & 0xFF;
421 		if (brcmstb_i2c_write_data_byte(dev, &addr, 0) < 0)
422 			return -EREMOTEIO;
423 
424 		if (msg->flags & I2C_M_RD) {
425 			/* For read, send restart without stop condition */
426 			brcmstb_set_i2c_start_stop(dev, COND_RESTART
427 						   | COND_NOSTOP);
428 			/* Then re-send the first byte with the read bit set */
429 			addr = 0xF0 | ((msg->addr & 0x300) >> 7) | 0x01;
430 			if (brcmstb_i2c_write_data_byte(dev, &addr, 0) < 0)
431 				return -EREMOTEIO;
432 
433 		}
434 	} else {
435 		addr = i2c_8bit_addr_from_msg(msg);
436 
437 		bsc_writel(dev, addr, chip_address);
438 	}
439 
440 	return 0;
441 }
442 
443 /* Master transfer function */
brcmstb_i2c_xfer(struct i2c_adapter * adapter,struct i2c_msg msgs[],int num)444 static int brcmstb_i2c_xfer(struct i2c_adapter *adapter,
445 			    struct i2c_msg msgs[], int num)
446 {
447 	struct brcmstb_i2c_dev *dev = i2c_get_adapdata(adapter);
448 	struct i2c_msg *pmsg;
449 	int rc = 0;
450 	int i;
451 	int bytes_to_xfer;
452 	u8 *tmp_buf;
453 	int len = 0;
454 	int xfersz = brcmstb_i2c_get_xfersz(dev);
455 	u32 cond, cond_per_msg;
456 
457 	/* Loop through all messages */
458 	for (i = 0; i < num; i++) {
459 		pmsg = &msgs[i];
460 		len = pmsg->len;
461 		tmp_buf = pmsg->buf;
462 
463 		dev_dbg(dev->device,
464 			"msg# %d/%d flg %x buf %x len %d\n", i,
465 			num - 1, pmsg->flags,
466 			pmsg->buf ? pmsg->buf[0] : '0', pmsg->len);
467 
468 		if (i < (num - 1) && (msgs[i + 1].flags & I2C_M_NOSTART))
469 			cond = ~COND_START_STOP;
470 		else
471 			cond = COND_RESTART | COND_NOSTOP;
472 
473 		brcmstb_set_i2c_start_stop(dev, cond);
474 
475 		/* Send slave address */
476 		if (!(pmsg->flags & I2C_M_NOSTART)) {
477 			rc = brcmstb_i2c_do_addr(dev, pmsg);
478 			if (rc < 0) {
479 				dev_dbg(dev->device,
480 					"NACK for addr %2.2x msg#%d rc = %d\n",
481 					pmsg->addr, i, rc);
482 				goto out;
483 			}
484 		}
485 
486 		cond_per_msg = cond;
487 
488 		/* Perform data transfer */
489 		while (len) {
490 			bytes_to_xfer = min(len, xfersz);
491 
492 			if (len <= xfersz) {
493 				if (i == (num - 1))
494 					cond_per_msg = cond_per_msg &
495 						~(COND_RESTART | COND_NOSTOP);
496 				else
497 					cond_per_msg = cond;
498 			} else {
499 				cond_per_msg = (cond_per_msg & ~COND_RESTART) |
500 					COND_NOSTOP;
501 			}
502 
503 			brcmstb_set_i2c_start_stop(dev, cond_per_msg);
504 
505 			rc = brcmstb_i2c_xfer_bsc_data(dev, tmp_buf,
506 						       bytes_to_xfer, pmsg);
507 			if (rc < 0)
508 				goto out;
509 
510 			len -=  bytes_to_xfer;
511 			tmp_buf += bytes_to_xfer;
512 
513 			cond_per_msg = COND_NOSTART | COND_NOSTOP;
514 		}
515 	}
516 
517 	rc = num;
518 out:
519 	return rc;
520 
521 }
522 
brcmstb_i2c_functionality(struct i2c_adapter * adap)523 static u32 brcmstb_i2c_functionality(struct i2c_adapter *adap)
524 {
525 	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR
526 		| I2C_FUNC_NOSTART | I2C_FUNC_PROTOCOL_MANGLING;
527 }
528 
529 static const struct i2c_algorithm brcmstb_i2c_algo = {
530 	.master_xfer = brcmstb_i2c_xfer,
531 	.functionality = brcmstb_i2c_functionality,
532 };
533 
brcmstb_i2c_set_bus_speed(struct brcmstb_i2c_dev * dev)534 static void brcmstb_i2c_set_bus_speed(struct brcmstb_i2c_dev *dev)
535 {
536 	int i = 0, num_speeds = ARRAY_SIZE(bsc_clk);
537 	u32 clk_freq_hz = dev->clk_freq_hz;
538 
539 	for (i = 0; i < num_speeds; i++) {
540 		if (bsc_clk[i].hz == clk_freq_hz) {
541 			dev->bsc_regmap->ctl_reg &= ~(BSC_CTL_REG_SCL_SEL_MASK
542 						| BSC_CTL_REG_DIV_CLK_MASK);
543 			dev->bsc_regmap->ctl_reg |= (bsc_clk[i].scl_mask |
544 						     bsc_clk[i].div_mask);
545 			bsc_writel(dev, dev->bsc_regmap->ctl_reg, ctl_reg);
546 			break;
547 		}
548 	}
549 
550 	/* in case we did not get find a valid speed */
551 	if (i == num_speeds) {
552 		i = (bsc_readl(dev, ctl_reg) & BSC_CTL_REG_SCL_SEL_MASK) >>
553 			BSC_CTL_REG_SCL_SEL_SHIFT;
554 		dev_warn(dev->device, "leaving current clock-frequency @ %dHz\n",
555 			bsc_clk[i].hz);
556 	}
557 }
558 
brcmstb_i2c_set_bsc_reg_defaults(struct brcmstb_i2c_dev * dev)559 static void brcmstb_i2c_set_bsc_reg_defaults(struct brcmstb_i2c_dev *dev)
560 {
561 	if (brcmstb_i2c_get_data_regsz(dev) == sizeof(u32))
562 		/* set 4 byte data in/out xfers  */
563 		dev->bsc_regmap->ctlhi_reg = BSC_CTLHI_REG_DATAREG_SIZE_MASK;
564 	else
565 		dev->bsc_regmap->ctlhi_reg &= ~BSC_CTLHI_REG_DATAREG_SIZE_MASK;
566 
567 	bsc_writel(dev, dev->bsc_regmap->ctlhi_reg, ctlhi_reg);
568 	/* set bus speed */
569 	brcmstb_i2c_set_bus_speed(dev);
570 }
571 
572 #define AUTOI2C_CTRL0		0x26c
573 #define AUTOI2C_CTRL0_RELEASE_BSC	BIT(1)
574 
bcm2711_release_bsc(struct brcmstb_i2c_dev * dev)575 static int bcm2711_release_bsc(struct brcmstb_i2c_dev *dev)
576 {
577 	struct platform_device *pdev = to_platform_device(dev->device);
578 	void __iomem *autoi2c;
579 
580 	/* Map hardware registers */
581 	autoi2c = devm_platform_ioremap_resource_byname(pdev, "auto-i2c");
582 	if (IS_ERR(autoi2c))
583 		return PTR_ERR(autoi2c);
584 
585 	writel(AUTOI2C_CTRL0_RELEASE_BSC, autoi2c + AUTOI2C_CTRL0);
586 	devm_iounmap(&pdev->dev, autoi2c);
587 
588 	/* We need to reset the controller after the release */
589 	dev->bsc_regmap->iic_enable = 0;
590 	bsc_writel(dev, dev->bsc_regmap->iic_enable, iic_enable);
591 
592 	return 0;
593 }
594 
brcmstb_i2c_probe(struct platform_device * pdev)595 static int brcmstb_i2c_probe(struct platform_device *pdev)
596 {
597 	struct brcmstb_i2c_dev *dev;
598 	struct i2c_adapter *adap;
599 	const char *int_name;
600 	int rc;
601 
602 	/* Allocate memory for private data structure */
603 	dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
604 	if (!dev)
605 		return -ENOMEM;
606 
607 	dev->bsc_regmap = devm_kzalloc(&pdev->dev, sizeof(*dev->bsc_regmap), GFP_KERNEL);
608 	if (!dev->bsc_regmap)
609 		return -ENOMEM;
610 
611 	platform_set_drvdata(pdev, dev);
612 	dev->device = &pdev->dev;
613 	init_completion(&dev->done);
614 
615 	/* Map hardware registers */
616 	dev->base = devm_platform_ioremap_resource(pdev, 0);
617 	if (IS_ERR(dev->base))
618 		return PTR_ERR(dev->base);
619 
620 	if (of_device_is_compatible(dev->device->of_node,
621 				    "brcm,bcm2711-hdmi-i2c")) {
622 		rc = bcm2711_release_bsc(dev);
623 		if (rc)
624 			return rc;
625 	}
626 
627 	rc = of_property_read_string(dev->device->of_node, "interrupt-names",
628 				     &int_name);
629 	if (rc < 0)
630 		int_name = NULL;
631 
632 	/* Get the interrupt number */
633 	dev->irq = platform_get_irq_optional(pdev, 0);
634 
635 	/* disable the bsc interrupt line */
636 	brcmstb_i2c_enable_disable_irq(dev, INT_DISABLE);
637 
638 	/* register the ISR handler */
639 	if (dev->irq >= 0) {
640 		rc = devm_request_irq(&pdev->dev, dev->irq, brcmstb_i2c_isr,
641 				      IRQF_SHARED,
642 				      int_name ? int_name : pdev->name,
643 				      dev);
644 
645 		if (rc) {
646 			dev_dbg(dev->device, "falling back to polling mode");
647 			dev->irq = -1;
648 		}
649 	}
650 
651 	if (of_property_read_u32(dev->device->of_node,
652 				 "clock-frequency", &dev->clk_freq_hz)) {
653 		dev_warn(dev->device, "setting clock-frequency@%dHz\n",
654 			 bsc_clk[0].hz);
655 		dev->clk_freq_hz = bsc_clk[0].hz;
656 	}
657 
658 	/* set the data in/out register size for compatible SoCs */
659 	if (of_device_is_compatible(dev->device->of_node,
660 				    "brcm,brcmper-i2c"))
661 		dev->data_regsz = sizeof(u8);
662 	else
663 		dev->data_regsz = sizeof(u32);
664 
665 	brcmstb_i2c_set_bsc_reg_defaults(dev);
666 
667 	/* Add the i2c adapter */
668 	adap = &dev->adapter;
669 	i2c_set_adapdata(adap, dev);
670 	adap->owner = THIS_MODULE;
671 	strscpy(adap->name, dev_name(&pdev->dev), sizeof(adap->name));
672 	adap->algo = &brcmstb_i2c_algo;
673 	adap->dev.parent = &pdev->dev;
674 	adap->dev.of_node = pdev->dev.of_node;
675 	rc = i2c_add_adapter(adap);
676 	if (rc)
677 		return rc;
678 
679 	dev_info(dev->device, "%s@%dhz registered in %s mode\n",
680 		 int_name ? int_name : " ", dev->clk_freq_hz,
681 		 (dev->irq >= 0) ? "interrupt" : "polling");
682 
683 	return 0;
684 }
685 
brcmstb_i2c_remove(struct platform_device * pdev)686 static void brcmstb_i2c_remove(struct platform_device *pdev)
687 {
688 	struct brcmstb_i2c_dev *dev = platform_get_drvdata(pdev);
689 
690 	i2c_del_adapter(&dev->adapter);
691 }
692 
brcmstb_i2c_suspend(struct device * dev)693 static int brcmstb_i2c_suspend(struct device *dev)
694 {
695 	struct brcmstb_i2c_dev *i2c_dev = dev_get_drvdata(dev);
696 
697 	i2c_mark_adapter_suspended(&i2c_dev->adapter);
698 	return 0;
699 }
700 
brcmstb_i2c_resume(struct device * dev)701 static int brcmstb_i2c_resume(struct device *dev)
702 {
703 	struct brcmstb_i2c_dev *i2c_dev = dev_get_drvdata(dev);
704 
705 	brcmstb_i2c_set_bsc_reg_defaults(i2c_dev);
706 	i2c_mark_adapter_resumed(&i2c_dev->adapter);
707 
708 	return 0;
709 }
710 
711 static DEFINE_SIMPLE_DEV_PM_OPS(brcmstb_i2c_pm, brcmstb_i2c_suspend,
712 				brcmstb_i2c_resume);
713 
714 static const struct of_device_id brcmstb_i2c_of_match[] = {
715 	{.compatible = "brcm,brcmstb-i2c"},
716 	{.compatible = "brcm,brcmper-i2c"},
717 	{.compatible = "brcm,bcm2711-hdmi-i2c"},
718 	{},
719 };
720 MODULE_DEVICE_TABLE(of, brcmstb_i2c_of_match);
721 
722 static struct platform_driver brcmstb_i2c_driver = {
723 	.driver = {
724 		   .name = "brcmstb-i2c",
725 		   .of_match_table = brcmstb_i2c_of_match,
726 		   .pm = pm_sleep_ptr(&brcmstb_i2c_pm),
727 		   },
728 	.probe = brcmstb_i2c_probe,
729 	.remove_new = brcmstb_i2c_remove,
730 };
731 module_platform_driver(brcmstb_i2c_driver);
732 
733 MODULE_AUTHOR("Kamal Dasu <kdasu@broadcom.com>");
734 MODULE_DESCRIPTION("Broadcom Settop I2C Driver");
735 MODULE_LICENSE("GPL v2");
736