1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 #ifndef SMU_13_0_0_PPTABLE_H 23 #define SMU_13_0_0_PPTABLE_H 24 25 #pragma pack(push, 1) 26 27 #define SMU_13_0_0_TABLE_FORMAT_REVISION 15 28 29 //// POWERPLAYTABLE::ulPlatformCaps 30 #define SMU_13_0_0_PP_PLATFORM_CAP_POWERPLAY 0x1 // This cap indicates whether CCC need to show Powerplay page. 31 #define SMU_13_0_0_PP_PLATFORM_CAP_SBIOSPOWERSOURCE 0x2 // This cap indicates whether power source notificaiton is done by SBIOS instead of OS. 32 #define SMU_13_0_0_PP_PLATFORM_CAP_HARDWAREDC 0x4 // This cap indicates whether DC mode notificaiton is done by GPIO pin directly. 33 #define SMU_13_0_0_PP_PLATFORM_CAP_BACO 0x8 // This cap indicates whether board supports the BACO circuitry. 34 #define SMU_13_0_0_PP_PLATFORM_CAP_MACO 0x10 // This cap indicates whether board supports the MACO circuitry. 35 #define SMU_13_0_0_PP_PLATFORM_CAP_SHADOWPSTATE 0x20 // This cap indicates whether board supports the Shadow Pstate. 36 37 // SMU_13_0_0_PP_THERMALCONTROLLER - Thermal Controller Type 38 #define SMU_13_0_0_PP_THERMALCONTROLLER_NONE 0 39 #define SMU_13_0_0_PP_THERMALCONTROLLER_NAVI21 28 40 41 #define SMU_13_0_0_PP_OVERDRIVE_VERSION 0x83 // OverDrive 8 Table Version 0.2 42 #define SMU_13_0_0_PP_POWERSAVINGCLOCK_VERSION 0x01 // Power Saving Clock Table Version 1.00 43 44 enum SMU_13_0_0_ODFEATURE_CAP { 45 SMU_13_0_0_ODCAP_GFXCLK_LIMITS = 0, 46 SMU_13_0_0_ODCAP_UCLK_LIMITS, 47 SMU_13_0_0_ODCAP_POWER_LIMIT, 48 SMU_13_0_0_ODCAP_FAN_ACOUSTIC_LIMIT, 49 SMU_13_0_0_ODCAP_FAN_SPEED_MIN, 50 SMU_13_0_0_ODCAP_TEMPERATURE_FAN, 51 SMU_13_0_0_ODCAP_TEMPERATURE_SYSTEM, 52 SMU_13_0_0_ODCAP_MEMORY_TIMING_TUNE, 53 SMU_13_0_0_ODCAP_FAN_ZERO_RPM_CONTROL, 54 SMU_13_0_0_ODCAP_AUTO_UV_ENGINE, 55 SMU_13_0_0_ODCAP_AUTO_OC_ENGINE, 56 SMU_13_0_0_ODCAP_AUTO_OC_MEMORY, 57 SMU_13_0_0_ODCAP_FAN_CURVE, 58 SMU_13_0_0_ODCAP_AUTO_FAN_ACOUSTIC_LIMIT, 59 SMU_13_0_0_ODCAP_POWER_MODE, 60 SMU_13_0_0_ODCAP_PER_ZONE_GFX_VOLTAGE_OFFSET, 61 SMU_13_0_0_ODCAP_COUNT, 62 }; 63 64 enum SMU_13_0_0_ODFEATURE_ID { 65 SMU_13_0_0_ODFEATURE_GFXCLK_LIMITS = 1 << SMU_13_0_0_ODCAP_GFXCLK_LIMITS, //GFXCLK Limit feature 66 SMU_13_0_0_ODFEATURE_UCLK_LIMITS = 1 << SMU_13_0_0_ODCAP_UCLK_LIMITS, //UCLK Limit feature 67 SMU_13_0_0_ODFEATURE_POWER_LIMIT = 1 << SMU_13_0_0_ODCAP_POWER_LIMIT, //Power Limit feature 68 SMU_13_0_0_ODFEATURE_FAN_ACOUSTIC_LIMIT = 1 << SMU_13_0_0_ODCAP_FAN_ACOUSTIC_LIMIT, //Fan Acoustic RPM feature 69 SMU_13_0_0_ODFEATURE_FAN_SPEED_MIN = 1 << SMU_13_0_0_ODCAP_FAN_SPEED_MIN, //Minimum Fan Speed feature 70 SMU_13_0_0_ODFEATURE_TEMPERATURE_FAN = 1 << SMU_13_0_0_ODCAP_TEMPERATURE_FAN, //Fan Target Temperature Limit feature 71 SMU_13_0_0_ODFEATURE_TEMPERATURE_SYSTEM = 1 << SMU_13_0_0_ODCAP_TEMPERATURE_SYSTEM, //Operating Temperature Limit feature 72 SMU_13_0_0_ODFEATURE_MEMORY_TIMING_TUNE = 1 << SMU_13_0_0_ODCAP_MEMORY_TIMING_TUNE, //AC Timing Tuning feature 73 SMU_13_0_0_ODFEATURE_FAN_ZERO_RPM_CONTROL = 1 << SMU_13_0_0_ODCAP_FAN_ZERO_RPM_CONTROL, //Zero RPM feature 74 SMU_13_0_0_ODFEATURE_AUTO_UV_ENGINE = 1 << SMU_13_0_0_ODCAP_AUTO_UV_ENGINE, //Auto Under Volt GFXCLK feature 75 SMU_13_0_0_ODFEATURE_AUTO_OC_ENGINE = 1 << SMU_13_0_0_ODCAP_AUTO_OC_ENGINE, //Auto Over Clock GFXCLK feature 76 SMU_13_0_0_ODFEATURE_AUTO_OC_MEMORY = 1 << SMU_13_0_0_ODCAP_AUTO_OC_MEMORY, //Auto Over Clock MCLK feature 77 SMU_13_0_0_ODFEATURE_FAN_CURVE = 1 << SMU_13_0_0_ODCAP_FAN_CURVE, //Fan Curve feature 78 SMU_13_0_0_ODFEATURE_AUTO_FAN_ACOUSTIC_LIMIT = 1 << SMU_13_0_0_ODCAP_AUTO_FAN_ACOUSTIC_LIMIT, //Auto Fan Acoustic RPM feature 79 SMU_13_0_0_ODFEATURE_POWER_MODE = 1 << SMU_13_0_0_ODCAP_POWER_MODE, //Optimized GPU Power Mode feature 80 SMU_13_0_0_ODFEATURE_PER_ZONE_GFX_VOLTAGE_OFFSET = 1 << SMU_13_0_0_ODCAP_PER_ZONE_GFX_VOLTAGE_OFFSET, //Perzone voltage offset feature 81 SMU_13_0_0_ODFEATURE_COUNT = 16, 82 }; 83 84 #define SMU_13_0_0_MAX_ODFEATURE 32 //Maximum Number of OD Features 85 86 enum SMU_13_0_0_ODSETTING_ID { 87 SMU_13_0_0_ODSETTING_GFXCLKFMAX = 0, 88 SMU_13_0_0_ODSETTING_GFXCLKFMIN, 89 SMU_13_0_0_ODSETTING_UCLKFMIN, 90 SMU_13_0_0_ODSETTING_UCLKFMAX, 91 SMU_13_0_0_ODSETTING_POWERPERCENTAGE, 92 SMU_13_0_0_ODSETTING_FANRPMMIN, 93 SMU_13_0_0_ODSETTING_FANRPMACOUSTICLIMIT, 94 SMU_13_0_0_ODSETTING_FANTARGETTEMPERATURE, 95 SMU_13_0_0_ODSETTING_OPERATINGTEMPMAX, 96 SMU_13_0_0_ODSETTING_ACTIMING, 97 SMU_13_0_0_ODSETTING_FAN_ZERO_RPM_CONTROL, 98 SMU_13_0_0_ODSETTING_AUTOUVENGINE, 99 SMU_13_0_0_ODSETTING_AUTOOCENGINE, 100 SMU_13_0_0_ODSETTING_AUTOOCMEMORY, 101 SMU_13_0_0_ODSETTING_FAN_CURVE_TEMPERATURE_1, 102 SMU_13_0_0_ODSETTING_FAN_CURVE_SPEED_1, 103 SMU_13_0_0_ODSETTING_FAN_CURVE_TEMPERATURE_2, 104 SMU_13_0_0_ODSETTING_FAN_CURVE_SPEED_2, 105 SMU_13_0_0_ODSETTING_FAN_CURVE_TEMPERATURE_3, 106 SMU_13_0_0_ODSETTING_FAN_CURVE_SPEED_3, 107 SMU_13_0_0_ODSETTING_FAN_CURVE_TEMPERATURE_4, 108 SMU_13_0_0_ODSETTING_FAN_CURVE_SPEED_4, 109 SMU_13_0_0_ODSETTING_FAN_CURVE_TEMPERATURE_5, 110 SMU_13_0_0_ODSETTING_FAN_CURVE_SPEED_5, 111 SMU_13_0_0_ODSETTING_AUTO_FAN_ACOUSTIC_LIMIT, 112 SMU_13_0_0_ODSETTING_POWER_MODE, 113 SMU_13_0_0_ODSETTING_PER_ZONE_GFX_VOLTAGE_OFFSET_POINT_1, 114 SMU_13_0_0_ODSETTING_PER_ZONE_GFX_VOLTAGE_OFFSET_POINT_2, 115 SMU_13_0_0_ODSETTING_PER_ZONE_GFX_VOLTAGE_OFFSET_POINT_3, 116 SMU_13_0_0_ODSETTING_PER_ZONE_GFX_VOLTAGE_OFFSET_POINT_4, 117 SMU_13_0_0_ODSETTING_PER_ZONE_GFX_VOLTAGE_OFFSET_POINT_5, 118 SMU_13_0_0_ODSETTING_PER_ZONE_GFX_VOLTAGE_OFFSET_POINT_6, 119 SMU_13_0_0_ODSETTING_COUNT, 120 }; 121 #define SMU_13_0_0_MAX_ODSETTING 64 //Maximum Number of ODSettings 122 123 enum SMU_13_0_0_PWRMODE_SETTING { 124 SMU_13_0_0_PMSETTING_POWER_LIMIT_QUIET = 0, 125 SMU_13_0_0_PMSETTING_POWER_LIMIT_BALANCE, 126 SMU_13_0_0_PMSETTING_POWER_LIMIT_TURBO, 127 SMU_13_0_0_PMSETTING_POWER_LIMIT_RAGE, 128 SMU_13_0_0_PMSETTING_ACOUSTIC_TEMP_QUIET, 129 SMU_13_0_0_PMSETTING_ACOUSTIC_TEMP_BALANCE, 130 SMU_13_0_0_PMSETTING_ACOUSTIC_TEMP_TURBO, 131 SMU_13_0_0_PMSETTING_ACOUSTIC_TEMP_RAGE, 132 SMU_13_0_0_PMSETTING_ACOUSTIC_TARGET_RPM_QUIET, 133 SMU_13_0_0_PMSETTING_ACOUSTIC_TARGET_RPM_BALANCE, 134 SMU_13_0_0_PMSETTING_ACOUSTIC_TARGET_RPM_TURBO, 135 SMU_13_0_0_PMSETTING_ACOUSTIC_TARGET_RPM_RAGE, 136 SMU_13_0_0_PMSETTING_ACOUSTIC_LIMIT_RPM_QUIET, 137 SMU_13_0_0_PMSETTING_ACOUSTIC_LIMIT_RPM_BALANCE, 138 SMU_13_0_0_PMSETTING_ACOUSTIC_LIMIT_RPM_TURBO, 139 SMU_13_0_0_PMSETTING_ACOUSTIC_LIMIT_RPM_RAGE, 140 }; 141 #define SMU_13_0_0_MAX_PMSETTING 32 //Maximum Number of PowerMode Settings 142 143 struct smu_13_0_0_overdrive_table { 144 uint8_t revision; //Revision = SMU_13_0_0_PP_OVERDRIVE_VERSION 145 uint8_t reserve[3]; //Zero filled field reserved for future use 146 uint32_t feature_count; //Total number of supported features 147 uint32_t setting_count; //Total number of supported settings 148 uint8_t cap[SMU_13_0_0_MAX_ODFEATURE]; //OD feature support flags 149 uint32_t max[SMU_13_0_0_MAX_ODSETTING]; //default maximum settings 150 uint32_t min[SMU_13_0_0_MAX_ODSETTING]; //default minimum settings 151 int16_t pm_setting[SMU_13_0_0_MAX_PMSETTING]; //Optimized power mode feature settings 152 }; 153 154 enum SMU_13_0_0_PPCLOCK_ID { 155 SMU_13_0_0_PPCLOCK_GFXCLK = 0, 156 SMU_13_0_0_PPCLOCK_SOCCLK, 157 SMU_13_0_0_PPCLOCK_UCLK, 158 SMU_13_0_0_PPCLOCK_FCLK, 159 SMU_13_0_0_PPCLOCK_DCLK_0, 160 SMU_13_0_0_PPCLOCK_VCLK_0, 161 SMU_13_0_0_PPCLOCK_DCLK_1, 162 SMU_13_0_0_PPCLOCK_VCLK_1, 163 SMU_13_0_0_PPCLOCK_DCEFCLK, 164 SMU_13_0_0_PPCLOCK_DISPCLK, 165 SMU_13_0_0_PPCLOCK_PIXCLK, 166 SMU_13_0_0_PPCLOCK_PHYCLK, 167 SMU_13_0_0_PPCLOCK_DTBCLK, 168 SMU_13_0_0_PPCLOCK_COUNT, 169 }; 170 #define SMU_13_0_0_MAX_PPCLOCK 16 //Maximum Number of PP Clocks 171 172 struct smu_13_0_0_powerplay_table { 173 struct atom_common_table_header header; //For SMU13, header.format_revision = 15, header.content_revision = 0 174 uint8_t table_revision; //For SMU13, table_revision = 2 175 uint8_t padding; 176 uint16_t table_size; //Driver portion table size. The offset to smc_pptable including header size 177 uint32_t golden_pp_id; //PPGen use only: PP Table ID on the Golden Data Base 178 uint32_t golden_revision; //PPGen use only: PP Table Revision on the Golden Data Base 179 uint16_t format_id; //PPGen use only: PPTable for different ASICs. For SMU13 this should be 0x80 180 uint32_t platform_caps; //POWERPLAYABLE::ulPlatformCaps 181 182 uint8_t thermal_controller_type; //one of SMU_13_0_0_PP_THERMALCONTROLLER 183 184 uint16_t small_power_limit1; 185 uint16_t small_power_limit2; 186 uint16_t boost_power_limit; //For Gemini Board, when the slave adapter is in BACO mode, the master adapter will use this boost power limit instead of the default power limit to boost the power limit. 187 uint16_t software_shutdown_temp; 188 189 uint32_t reserve[45]; 190 191 struct smu_13_0_0_overdrive_table overdrive_table; 192 uint8_t padding1; 193 PPTable_t smc_pptable; //PPTable_t in driver_if.h 194 }; 195 196 #pragma pack(pop) 197 198 #endif 199