1 /*
2  * Copyright 2019 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 #ifndef __SMU_V11_0_H__
24 #define __SMU_V11_0_H__
25 
26 #include "amdgpu_smu.h"
27 
28 #define SMU11_DRIVER_IF_VERSION_INV 0xFFFFFFFF
29 #define SMU11_DRIVER_IF_VERSION_ARCT 0x17
30 #define SMU11_DRIVER_IF_VERSION_NV10 0x37
31 #define SMU11_DRIVER_IF_VERSION_NV12 0x38
32 #define SMU11_DRIVER_IF_VERSION_NV14 0x38
33 #define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x40
34 #define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0xE
35 #define SMU11_DRIVER_IF_VERSION_VANGOGH 0x03
36 #define SMU11_DRIVER_IF_VERSION_Dimgrey_Cavefish 0xF
37 #define SMU11_DRIVER_IF_VERSION_Beige_Goby 0xD
38 #define SMU11_DRIVER_IF_VERSION_Cyan_Skillfish 0x8
39 
40 /* MP Apertures */
41 #define MP0_Public			0x03800000
42 #define MP0_SRAM			0x03900000
43 #define MP1_Public			0x03b00000
44 #define MP1_SRAM			0x03c00004
45 
46 /* address block */
47 #define smnMP1_FIRMWARE_FLAGS		0x3010024
48 #define smnMP0_FW_INTF			0x30101c0
49 #define smnMP1_PUB_CTRL			0x3010b14
50 
51 #define TEMP_RANGE_MIN			(0)
52 #define TEMP_RANGE_MAX			(80 * 1000)
53 
54 #define SMU11_TOOL_SIZE			0x19000
55 
56 #define MAX_DPM_LEVELS 16
57 #define MAX_PCIE_CONF 2
58 
59 #define CTF_OFFSET_EDGE			5
60 #define CTF_OFFSET_HOTSPOT		5
61 #define CTF_OFFSET_MEM			5
62 
63 #define LINK_WIDTH_MAX			6
64 #define LINK_SPEED_MAX			3
65 
66 static const __maybe_unused uint16_t link_width[] = {0, 1, 2, 4, 8, 12, 16};
67 
68 static const
69 struct smu_temperature_range __maybe_unused smu11_thermal_policy[] = {
70 	{-273150,  99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
71 	{ 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},
72 };
73 
74 struct smu_11_0_max_sustainable_clocks {
75 	uint32_t display_clock;
76 	uint32_t phy_clock;
77 	uint32_t pixel_clock;
78 	uint32_t uclock;
79 	uint32_t dcef_clock;
80 	uint32_t soc_clock;
81 };
82 
83 struct smu_11_0_dpm_clk_level {
84 	bool				enabled;
85 	uint32_t			value;
86 };
87 
88 struct smu_11_0_dpm_table {
89 	uint32_t			min;        /* MHz */
90 	uint32_t			max;        /* MHz */
91 	uint32_t			count;
92 	bool				is_fine_grained;
93 	struct smu_11_0_dpm_clk_level	dpm_levels[MAX_DPM_LEVELS];
94 };
95 
96 struct smu_11_0_pcie_table {
97 	uint8_t  pcie_gen[MAX_PCIE_CONF];
98 	uint8_t  pcie_lane[MAX_PCIE_CONF];
99 };
100 
101 struct smu_11_0_dpm_tables {
102 	struct smu_11_0_dpm_table        soc_table;
103 	struct smu_11_0_dpm_table        gfx_table;
104 	struct smu_11_0_dpm_table        uclk_table;
105 	struct smu_11_0_dpm_table        eclk_table;
106 	struct smu_11_0_dpm_table        vclk_table;
107 	struct smu_11_0_dpm_table        vclk1_table;
108 	struct smu_11_0_dpm_table        dclk_table;
109 	struct smu_11_0_dpm_table        dclk1_table;
110 	struct smu_11_0_dpm_table        dcef_table;
111 	struct smu_11_0_dpm_table        pixel_table;
112 	struct smu_11_0_dpm_table        display_table;
113 	struct smu_11_0_dpm_table        phy_table;
114 	struct smu_11_0_dpm_table        fclk_table;
115 	struct smu_11_0_pcie_table       pcie_table;
116 };
117 
118 struct smu_11_0_dpm_context {
119 	struct smu_11_0_dpm_tables  dpm_tables;
120 	uint32_t                    workload_policy_mask;
121 	uint32_t                    dcef_min_ds_clk;
122 };
123 
124 enum smu_11_0_power_state {
125 	SMU_11_0_POWER_STATE__D0 = 0,
126 	SMU_11_0_POWER_STATE__D1,
127 	SMU_11_0_POWER_STATE__D3, /* Sleep*/
128 	SMU_11_0_POWER_STATE__D4, /* Hibernate*/
129 	SMU_11_0_POWER_STATE__D5, /* Power off*/
130 };
131 
132 struct smu_11_0_power_context {
133 	uint32_t	power_source;
134 	uint8_t		in_power_limit_boost_mode;
135 	enum smu_11_0_power_state power_state;
136 };
137 
138 struct smu_11_5_power_context {
139 	uint32_t	power_source;
140 	uint8_t		in_power_limit_boost_mode;
141 	enum smu_11_0_power_state power_state;
142 
143 	uint32_t	current_fast_ppt_limit;
144 	uint32_t	default_fast_ppt_limit;
145 	uint32_t	max_fast_ppt_limit;
146 };
147 
148 #if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3)
149 
150 int smu_v11_0_init_microcode(struct smu_context *smu);
151 
152 void smu_v11_0_fini_microcode(struct smu_context *smu);
153 
154 int smu_v11_0_load_microcode(struct smu_context *smu);
155 
156 int smu_v11_0_init_smc_tables(struct smu_context *smu);
157 
158 int smu_v11_0_fini_smc_tables(struct smu_context *smu);
159 
160 int smu_v11_0_init_power(struct smu_context *smu);
161 
162 int smu_v11_0_fini_power(struct smu_context *smu);
163 
164 int smu_v11_0_check_fw_status(struct smu_context *smu);
165 
166 int smu_v11_0_setup_pptable(struct smu_context *smu);
167 
168 int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu);
169 
170 int smu_v11_0_check_fw_version(struct smu_context *smu);
171 
172 int smu_v11_0_set_driver_table_location(struct smu_context *smu);
173 
174 int smu_v11_0_set_tool_table_location(struct smu_context *smu);
175 
176 int smu_v11_0_notify_memory_pool_location(struct smu_context *smu);
177 
178 int smu_v11_0_system_features_control(struct smu_context *smu,
179 					     bool en);
180 
181 int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count);
182 
183 int smu_v11_0_set_allowed_mask(struct smu_context *smu);
184 
185 int smu_v11_0_notify_display_change(struct smu_context *smu);
186 
187 int smu_v11_0_get_current_power_limit(struct smu_context *smu,
188 				      uint32_t *power_limit);
189 
190 int smu_v11_0_set_power_limit(struct smu_context *smu,
191 			      enum smu_ppt_limit_type limit_type,
192 			      uint32_t limit);
193 
194 int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu);
195 
196 int smu_v11_0_enable_thermal_alert(struct smu_context *smu);
197 
198 int smu_v11_0_disable_thermal_alert(struct smu_context *smu);
199 
200 int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value);
201 
202 int smu_v11_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk);
203 
204 int
205 smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
206 					struct pp_display_clock_request
207 					*clock_req);
208 
209 uint32_t
210 smu_v11_0_get_fan_control_mode(struct smu_context *smu);
211 
212 int
213 smu_v11_0_set_fan_control_mode(struct smu_context *smu,
214 			       uint32_t mode);
215 
216 int smu_v11_0_set_fan_speed_pwm(struct smu_context *smu,
217 				    uint32_t speed);
218 
219 int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
220 				uint32_t speed);
221 
222 int smu_v11_0_get_fan_speed_pwm(struct smu_context *smu,
223 				    uint32_t *speed);
224 
225 int smu_v11_0_get_fan_speed_rpm(struct smu_context *smu,
226 				uint32_t *speed);
227 
228 int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
229 				     uint32_t pstate);
230 
231 int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable);
232 
233 int smu_v11_0_register_irq_handler(struct smu_context *smu);
234 
235 int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu);
236 
237 int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
238 		struct pp_smu_nv_clock_table *max_clocks);
239 
240 bool smu_v11_0_baco_is_support(struct smu_context *smu);
241 
242 enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu);
243 
244 int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state);
245 
246 int smu_v11_0_baco_enter(struct smu_context *smu);
247 int smu_v11_0_baco_exit(struct smu_context *smu);
248 
249 int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu,
250 				      enum smu_baco_seq baco_seq);
251 
252 int smu_v11_0_mode1_reset(struct smu_context *smu);
253 
254 int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
255 						 uint32_t *min, uint32_t *max);
256 
257 int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
258 			    uint32_t min, uint32_t max);
259 
260 int smu_v11_0_set_hard_freq_limited_range(struct smu_context *smu,
261 					  enum smu_clk_type clk_type,
262 					  uint32_t min,
263 					  uint32_t max);
264 
265 int smu_v11_0_set_performance_level(struct smu_context *smu,
266 				    enum amd_dpm_forced_level level);
267 
268 int smu_v11_0_set_power_source(struct smu_context *smu,
269 			       enum smu_power_src_type power_src);
270 
271 int smu_v11_0_get_dpm_freq_by_index(struct smu_context *smu,
272 				    enum smu_clk_type clk_type,
273 				    uint16_t level,
274 				    uint32_t *value);
275 
276 int smu_v11_0_get_dpm_level_count(struct smu_context *smu,
277 				  enum smu_clk_type clk_type,
278 				  uint32_t *value);
279 
280 int smu_v11_0_set_single_dpm_table(struct smu_context *smu,
281 				   enum smu_clk_type clk_type,
282 				   struct smu_11_0_dpm_table *single_dpm_table);
283 
284 int smu_v11_0_get_dpm_level_range(struct smu_context *smu,
285 				  enum smu_clk_type clk_type,
286 				  uint32_t *min_value,
287 				  uint32_t *max_value);
288 
289 int smu_v11_0_get_current_pcie_link_width_level(struct smu_context *smu);
290 
291 uint16_t smu_v11_0_get_current_pcie_link_width(struct smu_context *smu);
292 
293 int smu_v11_0_get_current_pcie_link_speed_level(struct smu_context *smu);
294 
295 uint16_t smu_v11_0_get_current_pcie_link_speed(struct smu_context *smu);
296 
297 int smu_v11_0_gfx_ulv_control(struct smu_context *smu,
298 			      bool enablement);
299 
300 int smu_v11_0_deep_sleep_control(struct smu_context *smu,
301 				 bool enablement);
302 
303 void smu_v11_0_interrupt_work(struct smu_context *smu);
304 
305 int smu_v11_0_handle_passthrough_sbr(struct smu_context *smu, bool enable);
306 
307 int smu_v11_0_restore_user_od_settings(struct smu_context *smu);
308 
309 void smu_v11_0_set_smu_mailbox_registers(struct smu_context *smu);
310 
311 #endif
312 #endif
313