1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
4 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
5 <mdsxyz123@yahoo.com>
6 Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de>
7 Copyright (C) 2010 Intel Corporation,
8 David Woodhouse <dwmw2@infradead.org>
9
10 */
11
12 /*
13 * Supports the following Intel I/O Controller Hubs (ICH):
14 *
15 * I/O Block I2C
16 * region SMBus Block proc. block
17 * Chip name PCI ID size PEC buffer call read
18 * ---------------------------------------------------------------------------
19 * 82801AA (ICH) 0x2413 16 no no no no
20 * 82801AB (ICH0) 0x2423 16 no no no no
21 * 82801BA (ICH2) 0x2443 16 no no no no
22 * 82801CA (ICH3) 0x2483 32 soft no no no
23 * 82801DB (ICH4) 0x24c3 32 hard yes no no
24 * 82801E (ICH5) 0x24d3 32 hard yes yes yes
25 * 6300ESB 0x25a4 32 hard yes yes yes
26 * 82801F (ICH6) 0x266a 32 hard yes yes yes
27 * 6310ESB/6320ESB 0x269b 32 hard yes yes yes
28 * 82801G (ICH7) 0x27da 32 hard yes yes yes
29 * 82801H (ICH8) 0x283e 32 hard yes yes yes
30 * 82801I (ICH9) 0x2930 32 hard yes yes yes
31 * EP80579 (Tolapai) 0x5032 32 hard yes yes yes
32 * ICH10 0x3a30 32 hard yes yes yes
33 * ICH10 0x3a60 32 hard yes yes yes
34 * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes
35 * 6 Series (PCH) 0x1c22 32 hard yes yes yes
36 * Patsburg (PCH) 0x1d22 32 hard yes yes yes
37 * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes
38 * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes
39 * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes
40 * DH89xxCC (PCH) 0x2330 32 hard yes yes yes
41 * Panther Point (PCH) 0x1e22 32 hard yes yes yes
42 * Lynx Point (PCH) 0x8c22 32 hard yes yes yes
43 * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes
44 * Avoton (SOC) 0x1f3c 32 hard yes yes yes
45 * Wellsburg (PCH) 0x8d22 32 hard yes yes yes
46 * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes
47 * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes
48 * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes
49 * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes
50 * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes
51 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes
52 * BayTrail (SOC) 0x0f12 32 hard yes yes yes
53 * Braswell (SOC) 0x2292 32 hard yes yes yes
54 * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes
55 * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes
56 * DNV (SOC) 0x19df 32 hard yes yes yes
57 * Emmitsburg (PCH) 0x1bc9 32 hard yes yes yes
58 * Broxton (SOC) 0x5ad4 32 hard yes yes yes
59 * Lewisburg (PCH) 0xa1a3 32 hard yes yes yes
60 * Lewisburg Supersku (PCH) 0xa223 32 hard yes yes yes
61 * Kaby Lake PCH-H (PCH) 0xa2a3 32 hard yes yes yes
62 * Gemini Lake (SOC) 0x31d4 32 hard yes yes yes
63 * Cannon Lake-H (PCH) 0xa323 32 hard yes yes yes
64 * Cannon Lake-LP (PCH) 0x9da3 32 hard yes yes yes
65 * Cedar Fork (PCH) 0x18df 32 hard yes yes yes
66 * Ice Lake-LP (PCH) 0x34a3 32 hard yes yes yes
67 * Ice Lake-N (PCH) 0x38a3 32 hard yes yes yes
68 * Comet Lake (PCH) 0x02a3 32 hard yes yes yes
69 * Comet Lake-H (PCH) 0x06a3 32 hard yes yes yes
70 * Elkhart Lake (PCH) 0x4b23 32 hard yes yes yes
71 * Tiger Lake-LP (PCH) 0xa0a3 32 hard yes yes yes
72 * Tiger Lake-H (PCH) 0x43a3 32 hard yes yes yes
73 * Jasper Lake (SOC) 0x4da3 32 hard yes yes yes
74 * Comet Lake-V (PCH) 0xa3a3 32 hard yes yes yes
75 * Alder Lake-S (PCH) 0x7aa3 32 hard yes yes yes
76 * Alder Lake-P (PCH) 0x51a3 32 hard yes yes yes
77 * Alder Lake-M (PCH) 0x54a3 32 hard yes yes yes
78 * Raptor Lake-S (PCH) 0x7a23 32 hard yes yes yes
79 * Meteor Lake-P (SOC) 0x7e22 32 hard yes yes yes
80 * Meteor Lake SoC-S (SOC) 0xae22 32 hard yes yes yes
81 * Meteor Lake PCH-S (PCH) 0x7f23 32 hard yes yes yes
82 * Birch Stream (SOC) 0x5796 32 hard yes yes yes
83 *
84 * Features supported by this driver:
85 * Software PEC no
86 * Hardware PEC yes
87 * Block buffer yes
88 * Block process call transaction yes
89 * I2C block read transaction yes (doesn't use the block buffer)
90 * Slave mode no
91 * SMBus Host Notify yes
92 * Interrupt processing yes
93 *
94 * See the file Documentation/i2c/busses/i2c-i801.rst for details.
95 */
96
97 #define DRV_NAME "i801_smbus"
98
99 #include <linux/interrupt.h>
100 #include <linux/module.h>
101 #include <linux/pci.h>
102 #include <linux/kernel.h>
103 #include <linux/stddef.h>
104 #include <linux/delay.h>
105 #include <linux/ioport.h>
106 #include <linux/init.h>
107 #include <linux/i2c.h>
108 #include <linux/i2c-smbus.h>
109 #include <linux/acpi.h>
110 #include <linux/io.h>
111 #include <linux/dmi.h>
112 #include <linux/slab.h>
113 #include <linux/string.h>
114 #include <linux/completion.h>
115 #include <linux/err.h>
116 #include <linux/platform_device.h>
117 #include <linux/platform_data/itco_wdt.h>
118 #include <linux/platform_data/x86/p2sb.h>
119 #include <linux/pm_runtime.h>
120 #include <linux/mutex.h>
121
122 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
123 #include <linux/gpio/machine.h>
124 #include <linux/platform_data/i2c-mux-gpio.h>
125 #endif
126
127 /* I801 SMBus address offsets */
128 #define SMBHSTSTS(p) (0 + (p)->smba)
129 #define SMBHSTCNT(p) (2 + (p)->smba)
130 #define SMBHSTCMD(p) (3 + (p)->smba)
131 #define SMBHSTADD(p) (4 + (p)->smba)
132 #define SMBHSTDAT0(p) (5 + (p)->smba)
133 #define SMBHSTDAT1(p) (6 + (p)->smba)
134 #define SMBBLKDAT(p) (7 + (p)->smba)
135 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */
136 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */
137 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */
138 #define SMBSLVSTS(p) (16 + (p)->smba) /* ICH3 and later */
139 #define SMBSLVCMD(p) (17 + (p)->smba) /* ICH3 and later */
140 #define SMBNTFDADD(p) (20 + (p)->smba) /* ICH3 and later */
141
142 /* PCI Address Constants */
143 #define SMBBAR 4
144 #define SMBHSTCFG 0x040
145 #define TCOBASE 0x050
146 #define TCOCTL 0x054
147
148 #define SBREG_SMBCTRL 0xc6000c
149 #define SBREG_SMBCTRL_DNV 0xcf000c
150
151 /* Host configuration bits for SMBHSTCFG */
152 #define SMBHSTCFG_HST_EN BIT(0)
153 #define SMBHSTCFG_SMB_SMI_EN BIT(1)
154 #define SMBHSTCFG_I2C_EN BIT(2)
155 #define SMBHSTCFG_SPD_WD BIT(4)
156
157 /* TCO configuration bits for TCOCTL */
158 #define TCOCTL_EN BIT(8)
159
160 /* Auxiliary status register bits, ICH4+ only */
161 #define SMBAUXSTS_CRCE BIT(0)
162 #define SMBAUXSTS_STCO BIT(1)
163
164 /* Auxiliary control register bits, ICH4+ only */
165 #define SMBAUXCTL_CRC BIT(0)
166 #define SMBAUXCTL_E32B BIT(1)
167
168 /* I801 command constants */
169 #define I801_QUICK 0x00
170 #define I801_BYTE 0x04
171 #define I801_BYTE_DATA 0x08
172 #define I801_WORD_DATA 0x0C
173 #define I801_PROC_CALL 0x10
174 #define I801_BLOCK_DATA 0x14
175 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
176 #define I801_BLOCK_PROC_CALL 0x1C
177
178 /* I801 Host Control register bits */
179 #define SMBHSTCNT_INTREN BIT(0)
180 #define SMBHSTCNT_KILL BIT(1)
181 #define SMBHSTCNT_LAST_BYTE BIT(5)
182 #define SMBHSTCNT_START BIT(6)
183 #define SMBHSTCNT_PEC_EN BIT(7) /* ICH3 and later */
184
185 /* I801 Hosts Status register bits */
186 #define SMBHSTSTS_BYTE_DONE BIT(7)
187 #define SMBHSTSTS_INUSE_STS BIT(6)
188 #define SMBHSTSTS_SMBALERT_STS BIT(5)
189 #define SMBHSTSTS_FAILED BIT(4)
190 #define SMBHSTSTS_BUS_ERR BIT(3)
191 #define SMBHSTSTS_DEV_ERR BIT(2)
192 #define SMBHSTSTS_INTR BIT(1)
193 #define SMBHSTSTS_HOST_BUSY BIT(0)
194
195 /* Host Notify Status register bits */
196 #define SMBSLVSTS_HST_NTFY_STS BIT(0)
197
198 /* Host Notify Command register bits */
199 #define SMBSLVCMD_SMBALERT_DISABLE BIT(2)
200 #define SMBSLVCMD_HST_NTFY_INTREN BIT(0)
201
202 #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
203 SMBHSTSTS_DEV_ERR)
204
205 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
206 STATUS_ERROR_FLAGS)
207
208 /* Older devices have their ID defined in <linux/pci_ids.h> */
209 #define PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS 0x02a3
210 #define PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS 0x06a3
211 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12
212 #define PCI_DEVICE_ID_INTEL_CDF_SMBUS 0x18df
213 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS 0x19df
214 #define PCI_DEVICE_ID_INTEL_EBG_SMBUS 0x1bc9
215 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22
216 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22
217 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
218 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70
219 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71
220 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72
221 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22
222 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c
223 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292
224 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330
225 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0
226 #define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS 0x31d4
227 #define PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS 0x34a3
228 #define PCI_DEVICE_ID_INTEL_ICELAKE_N_SMBUS 0x38a3
229 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
230 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS 0x43a3
231 #define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS 0x4b23
232 #define PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS 0x4da3
233 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_P_SMBUS 0x51a3
234 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_M_SMBUS 0x54a3
235 #define PCI_DEVICE_ID_INTEL_BIRCH_STREAM_SMBUS 0x5796
236 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS 0x5ad4
237 #define PCI_DEVICE_ID_INTEL_RAPTOR_LAKE_S_SMBUS 0x7a23
238 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS 0x7aa3
239 #define PCI_DEVICE_ID_INTEL_METEOR_LAKE_P_SMBUS 0x7e22
240 #define PCI_DEVICE_ID_INTEL_METEOR_LAKE_PCH_S_SMBUS 0x7f23
241 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22
242 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2
243 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22
244 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d
245 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e
246 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f
247 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22
248 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2
249 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS 0x9d23
250 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS 0x9da3
251 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS 0xa0a3
252 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123
253 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS 0xa1a3
254 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS 0xa223
255 #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS 0xa2a3
256 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS 0xa323
257 #define PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS 0xa3a3
258 #define PCI_DEVICE_ID_INTEL_METEOR_LAKE_SOC_S_SMBUS 0xae22
259
260 struct i801_mux_config {
261 char *gpio_chip;
262 unsigned values[3];
263 int n_values;
264 unsigned classes[3];
265 unsigned gpios[2]; /* Relative to gpio_chip->base */
266 int n_gpios;
267 };
268
269 struct i801_priv {
270 struct i2c_adapter adapter;
271 unsigned long smba;
272 unsigned char original_hstcfg;
273 unsigned char original_hstcnt;
274 unsigned char original_slvcmd;
275 struct pci_dev *pci_dev;
276 unsigned int features;
277
278 /* isr processing */
279 struct completion done;
280 u8 status;
281
282 /* Command state used by isr for byte-by-byte block transactions */
283 u8 cmd;
284 bool is_read;
285 int count;
286 int len;
287 u8 *data;
288
289 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
290 const struct i801_mux_config *mux_drvdata;
291 struct platform_device *mux_pdev;
292 struct gpiod_lookup_table *lookup;
293 #endif
294 struct platform_device *tco_pdev;
295
296 /*
297 * If set to true the host controller registers are reserved for
298 * ACPI AML use. Protected by acpi_lock.
299 */
300 bool acpi_reserved;
301 struct mutex acpi_lock;
302 };
303
304 #define FEATURE_SMBUS_PEC BIT(0)
305 #define FEATURE_BLOCK_BUFFER BIT(1)
306 #define FEATURE_BLOCK_PROC BIT(2)
307 #define FEATURE_I2C_BLOCK_READ BIT(3)
308 #define FEATURE_IRQ BIT(4)
309 #define FEATURE_HOST_NOTIFY BIT(5)
310 /* Not really a feature, but it's convenient to handle it as such */
311 #define FEATURE_IDF BIT(15)
312 #define FEATURE_TCO_SPT BIT(16)
313 #define FEATURE_TCO_CNL BIT(17)
314
315 static const char *i801_feature_names[] = {
316 "SMBus PEC",
317 "Block buffer",
318 "Block process call",
319 "I2C block read",
320 "Interrupt",
321 "SMBus Host Notify",
322 };
323
324 static unsigned int disable_features;
325 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
326 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
327 "\t\t 0x01 disable SMBus PEC\n"
328 "\t\t 0x02 disable the block buffer\n"
329 "\t\t 0x08 disable the I2C block read functionality\n"
330 "\t\t 0x10 don't use interrupts\n"
331 "\t\t 0x20 disable SMBus Host Notify ");
332
333 /* Make sure the SMBus host is ready to start transmitting.
334 Return 0 if it is, -EBUSY if it is not. */
i801_check_pre(struct i801_priv * priv)335 static int i801_check_pre(struct i801_priv *priv)
336 {
337 int status;
338
339 status = inb_p(SMBHSTSTS(priv));
340 if (status & SMBHSTSTS_HOST_BUSY) {
341 pci_err(priv->pci_dev, "SMBus is busy, can't use it!\n");
342 return -EBUSY;
343 }
344
345 status &= STATUS_FLAGS;
346 if (status) {
347 pci_dbg(priv->pci_dev, "Clearing status flags (%02x)\n", status);
348 outb_p(status, SMBHSTSTS(priv));
349 }
350
351 /*
352 * Clear CRC status if needed.
353 * During normal operation, i801_check_post() takes care
354 * of it after every operation. We do it here only in case
355 * the hardware was already in this state when the driver
356 * started.
357 */
358 if (priv->features & FEATURE_SMBUS_PEC) {
359 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
360 if (status) {
361 pci_dbg(priv->pci_dev, "Clearing aux status flags (%02x)\n", status);
362 outb_p(status, SMBAUXSTS(priv));
363 }
364 }
365
366 return 0;
367 }
368
i801_check_post(struct i801_priv * priv,int status)369 static int i801_check_post(struct i801_priv *priv, int status)
370 {
371 int result = 0;
372
373 /*
374 * If the SMBus is still busy, we give up
375 */
376 if (unlikely(status < 0)) {
377 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
378 /* try to stop the current command */
379 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
380 outb_p(SMBHSTCNT_KILL, SMBHSTCNT(priv));
381 usleep_range(1000, 2000);
382 outb_p(0, SMBHSTCNT(priv));
383
384 /* Check if it worked */
385 status = inb_p(SMBHSTSTS(priv));
386 if ((status & SMBHSTSTS_HOST_BUSY) ||
387 !(status & SMBHSTSTS_FAILED))
388 dev_err(&priv->pci_dev->dev,
389 "Failed terminating the transaction\n");
390 return -ETIMEDOUT;
391 }
392
393 if (status & SMBHSTSTS_FAILED) {
394 result = -EIO;
395 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
396 }
397 if (status & SMBHSTSTS_DEV_ERR) {
398 /*
399 * This may be a PEC error, check and clear it.
400 *
401 * AUXSTS is handled differently from HSTSTS.
402 * For HSTSTS, i801_isr() or i801_wait_intr()
403 * has already cleared the error bits in hardware,
404 * and we are passed a copy of the original value
405 * in "status".
406 * For AUXSTS, the hardware register is left
407 * for us to handle here.
408 * This is asymmetric, slightly iffy, but safe,
409 * since all this code is serialized and the CRCE
410 * bit is harmless as long as it's cleared before
411 * the next operation.
412 */
413 if ((priv->features & FEATURE_SMBUS_PEC) &&
414 (inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE)) {
415 outb_p(SMBAUXSTS_CRCE, SMBAUXSTS(priv));
416 result = -EBADMSG;
417 dev_dbg(&priv->pci_dev->dev, "PEC error\n");
418 } else {
419 result = -ENXIO;
420 dev_dbg(&priv->pci_dev->dev, "No response\n");
421 }
422 }
423 if (status & SMBHSTSTS_BUS_ERR) {
424 result = -EAGAIN;
425 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
426 }
427
428 return result;
429 }
430
431 /* Wait for BUSY being cleared and either INTR or an error flag being set */
i801_wait_intr(struct i801_priv * priv)432 static int i801_wait_intr(struct i801_priv *priv)
433 {
434 unsigned long timeout = jiffies + priv->adapter.timeout;
435 int status, busy;
436
437 do {
438 usleep_range(250, 500);
439 status = inb_p(SMBHSTSTS(priv));
440 busy = status & SMBHSTSTS_HOST_BUSY;
441 status &= STATUS_ERROR_FLAGS | SMBHSTSTS_INTR;
442 if (!busy && status)
443 return status & STATUS_ERROR_FLAGS;
444 } while (time_is_after_eq_jiffies(timeout));
445
446 return -ETIMEDOUT;
447 }
448
449 /* Wait for either BYTE_DONE or an error flag being set */
i801_wait_byte_done(struct i801_priv * priv)450 static int i801_wait_byte_done(struct i801_priv *priv)
451 {
452 unsigned long timeout = jiffies + priv->adapter.timeout;
453 int status;
454
455 do {
456 usleep_range(250, 500);
457 status = inb_p(SMBHSTSTS(priv));
458 if (status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE))
459 return status & STATUS_ERROR_FLAGS;
460 } while (time_is_after_eq_jiffies(timeout));
461
462 return -ETIMEDOUT;
463 }
464
i801_transaction(struct i801_priv * priv,int xact)465 static int i801_transaction(struct i801_priv *priv, int xact)
466 {
467 unsigned long result;
468 const struct i2c_adapter *adap = &priv->adapter;
469
470 if (priv->features & FEATURE_IRQ) {
471 reinit_completion(&priv->done);
472 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
473 SMBHSTCNT(priv));
474 result = wait_for_completion_timeout(&priv->done, adap->timeout);
475 return result ? priv->status : -ETIMEDOUT;
476 }
477
478 outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
479
480 return i801_wait_intr(priv);
481 }
482
i801_block_transaction_by_block(struct i801_priv * priv,union i2c_smbus_data * data,char read_write,int command)483 static int i801_block_transaction_by_block(struct i801_priv *priv,
484 union i2c_smbus_data *data,
485 char read_write, int command)
486 {
487 int i, len, status, xact;
488
489 switch (command) {
490 case I2C_SMBUS_BLOCK_PROC_CALL:
491 xact = I801_BLOCK_PROC_CALL;
492 break;
493 case I2C_SMBUS_BLOCK_DATA:
494 xact = I801_BLOCK_DATA;
495 break;
496 default:
497 return -EOPNOTSUPP;
498 }
499
500 /* Set block buffer mode */
501 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
502
503 if (read_write == I2C_SMBUS_WRITE) {
504 len = data->block[0];
505 outb_p(len, SMBHSTDAT0(priv));
506 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
507 for (i = 0; i < len; i++)
508 outb_p(data->block[i+1], SMBBLKDAT(priv));
509 }
510
511 status = i801_transaction(priv, xact);
512 if (status)
513 goto out;
514
515 if (read_write == I2C_SMBUS_READ ||
516 command == I2C_SMBUS_BLOCK_PROC_CALL) {
517 len = inb_p(SMBHSTDAT0(priv));
518 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
519 status = -EPROTO;
520 goto out;
521 }
522
523 data->block[0] = len;
524 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
525 for (i = 0; i < len; i++)
526 data->block[i + 1] = inb_p(SMBBLKDAT(priv));
527 }
528 out:
529 outb_p(inb_p(SMBAUXCTL(priv)) & ~SMBAUXCTL_E32B, SMBAUXCTL(priv));
530 return status;
531 }
532
i801_isr_byte_done(struct i801_priv * priv)533 static void i801_isr_byte_done(struct i801_priv *priv)
534 {
535 if (priv->is_read) {
536 /* For SMBus block reads, length is received with first byte */
537 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
538 (priv->count == 0)) {
539 priv->len = inb_p(SMBHSTDAT0(priv));
540 if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
541 dev_err(&priv->pci_dev->dev,
542 "Illegal SMBus block read size %d\n",
543 priv->len);
544 /* FIXME: Recover */
545 priv->len = I2C_SMBUS_BLOCK_MAX;
546 }
547 priv->data[-1] = priv->len;
548 }
549
550 /* Read next byte */
551 if (priv->count < priv->len)
552 priv->data[priv->count++] = inb(SMBBLKDAT(priv));
553 else
554 dev_dbg(&priv->pci_dev->dev,
555 "Discarding extra byte on block read\n");
556
557 /* Set LAST_BYTE for last byte of read transaction */
558 if (priv->count == priv->len - 1)
559 outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
560 SMBHSTCNT(priv));
561 } else if (priv->count < priv->len - 1) {
562 /* Write next byte, except for IRQ after last byte */
563 outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
564 }
565 }
566
i801_host_notify_isr(struct i801_priv * priv)567 static irqreturn_t i801_host_notify_isr(struct i801_priv *priv)
568 {
569 unsigned short addr;
570
571 addr = inb_p(SMBNTFDADD(priv)) >> 1;
572
573 /*
574 * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba)
575 * always returns 0. Our current implementation doesn't provide
576 * data, so we just ignore it.
577 */
578 i2c_handle_smbus_host_notify(&priv->adapter, addr);
579
580 /* clear Host Notify bit and return */
581 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
582 return IRQ_HANDLED;
583 }
584
585 /*
586 * There are three kinds of interrupts:
587 *
588 * 1) i801 signals transaction completion with one of these interrupts:
589 * INTR - Success
590 * DEV_ERR - Invalid command, NAK or communication timeout
591 * BUS_ERR - SMI# transaction collision
592 * FAILED - transaction was canceled due to a KILL request
593 * When any of these occur, update ->status and signal completion.
594 *
595 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
596 * occurs for each byte of a byte-by-byte to prepare the next byte.
597 *
598 * 3) Host Notify interrupts
599 */
i801_isr(int irq,void * dev_id)600 static irqreturn_t i801_isr(int irq, void *dev_id)
601 {
602 struct i801_priv *priv = dev_id;
603 u16 pcists;
604 u8 status;
605
606 /* Confirm this is our interrupt */
607 pci_read_config_word(priv->pci_dev, PCI_STATUS, &pcists);
608 if (!(pcists & PCI_STATUS_INTERRUPT))
609 return IRQ_NONE;
610
611 if (priv->features & FEATURE_HOST_NOTIFY) {
612 status = inb_p(SMBSLVSTS(priv));
613 if (status & SMBSLVSTS_HST_NTFY_STS)
614 return i801_host_notify_isr(priv);
615 }
616
617 status = inb_p(SMBHSTSTS(priv));
618 if ((status & (SMBHSTSTS_BYTE_DONE | STATUS_ERROR_FLAGS)) == SMBHSTSTS_BYTE_DONE)
619 i801_isr_byte_done(priv);
620
621 /*
622 * Clear IRQ sources: SMB_ALERT status is set after signal assertion
623 * independently of the interrupt generation being blocked or not
624 * so clear it always when the status is set.
625 */
626 status &= STATUS_FLAGS | SMBHSTSTS_SMBALERT_STS;
627 outb_p(status, SMBHSTSTS(priv));
628
629 status &= STATUS_ERROR_FLAGS | SMBHSTSTS_INTR;
630 if (status) {
631 priv->status = status & STATUS_ERROR_FLAGS;
632 complete(&priv->done);
633 }
634
635 return IRQ_HANDLED;
636 }
637
638 /*
639 * For "byte-by-byte" block transactions:
640 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
641 * I2C read uses cmd=I801_I2C_BLOCK_DATA
642 */
i801_block_transaction_byte_by_byte(struct i801_priv * priv,union i2c_smbus_data * data,char read_write,int command)643 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
644 union i2c_smbus_data *data,
645 char read_write, int command)
646 {
647 int i, len;
648 int smbcmd;
649 int status;
650 unsigned long result;
651 const struct i2c_adapter *adap = &priv->adapter;
652
653 if (command == I2C_SMBUS_BLOCK_PROC_CALL)
654 return -EOPNOTSUPP;
655
656 len = data->block[0];
657
658 if (read_write == I2C_SMBUS_WRITE) {
659 outb_p(len, SMBHSTDAT0(priv));
660 outb_p(data->block[1], SMBBLKDAT(priv));
661 }
662
663 if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
664 read_write == I2C_SMBUS_READ)
665 smbcmd = I801_I2C_BLOCK_DATA;
666 else
667 smbcmd = I801_BLOCK_DATA;
668
669 if (priv->features & FEATURE_IRQ) {
670 priv->is_read = (read_write == I2C_SMBUS_READ);
671 if (len == 1 && priv->is_read)
672 smbcmd |= SMBHSTCNT_LAST_BYTE;
673 priv->cmd = smbcmd | SMBHSTCNT_INTREN;
674 priv->len = len;
675 priv->count = 0;
676 priv->data = &data->block[1];
677
678 reinit_completion(&priv->done);
679 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
680 result = wait_for_completion_timeout(&priv->done, adap->timeout);
681 return result ? priv->status : -ETIMEDOUT;
682 }
683
684 if (len == 1 && read_write == I2C_SMBUS_READ)
685 smbcmd |= SMBHSTCNT_LAST_BYTE;
686 outb_p(smbcmd | SMBHSTCNT_START, SMBHSTCNT(priv));
687
688 for (i = 1; i <= len; i++) {
689 status = i801_wait_byte_done(priv);
690 if (status)
691 return status;
692
693 if (i == 1 && read_write == I2C_SMBUS_READ
694 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
695 len = inb_p(SMBHSTDAT0(priv));
696 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
697 dev_err(&priv->pci_dev->dev,
698 "Illegal SMBus block read size %d\n",
699 len);
700 /* Recover */
701 while (inb_p(SMBHSTSTS(priv)) &
702 SMBHSTSTS_HOST_BUSY)
703 outb_p(SMBHSTSTS_BYTE_DONE,
704 SMBHSTSTS(priv));
705 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
706 return -EPROTO;
707 }
708 data->block[0] = len;
709 }
710
711 if (read_write == I2C_SMBUS_READ) {
712 data->block[i] = inb_p(SMBBLKDAT(priv));
713 if (i == len - 1)
714 outb_p(smbcmd | SMBHSTCNT_LAST_BYTE, SMBHSTCNT(priv));
715 }
716
717 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
718 outb_p(data->block[i+1], SMBBLKDAT(priv));
719
720 /* signals SMBBLKDAT ready */
721 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
722 }
723
724 return i801_wait_intr(priv);
725 }
726
i801_set_hstadd(struct i801_priv * priv,u8 addr,char read_write)727 static void i801_set_hstadd(struct i801_priv *priv, u8 addr, char read_write)
728 {
729 outb_p((addr << 1) | (read_write & 0x01), SMBHSTADD(priv));
730 }
731
732 /* Single value transaction function */
i801_simple_transaction(struct i801_priv * priv,union i2c_smbus_data * data,u8 addr,u8 hstcmd,char read_write,int command)733 static int i801_simple_transaction(struct i801_priv *priv, union i2c_smbus_data *data,
734 u8 addr, u8 hstcmd, char read_write, int command)
735 {
736 int xact, ret;
737
738 switch (command) {
739 case I2C_SMBUS_QUICK:
740 i801_set_hstadd(priv, addr, read_write);
741 xact = I801_QUICK;
742 break;
743 case I2C_SMBUS_BYTE:
744 i801_set_hstadd(priv, addr, read_write);
745 if (read_write == I2C_SMBUS_WRITE)
746 outb_p(hstcmd, SMBHSTCMD(priv));
747 xact = I801_BYTE;
748 break;
749 case I2C_SMBUS_BYTE_DATA:
750 i801_set_hstadd(priv, addr, read_write);
751 if (read_write == I2C_SMBUS_WRITE)
752 outb_p(data->byte, SMBHSTDAT0(priv));
753 outb_p(hstcmd, SMBHSTCMD(priv));
754 xact = I801_BYTE_DATA;
755 break;
756 case I2C_SMBUS_WORD_DATA:
757 i801_set_hstadd(priv, addr, read_write);
758 if (read_write == I2C_SMBUS_WRITE) {
759 outb_p(data->word & 0xff, SMBHSTDAT0(priv));
760 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
761 }
762 outb_p(hstcmd, SMBHSTCMD(priv));
763 xact = I801_WORD_DATA;
764 break;
765 case I2C_SMBUS_PROC_CALL:
766 i801_set_hstadd(priv, addr, I2C_SMBUS_WRITE);
767 outb_p(data->word & 0xff, SMBHSTDAT0(priv));
768 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
769 outb_p(hstcmd, SMBHSTCMD(priv));
770 read_write = I2C_SMBUS_READ;
771 xact = I801_PROC_CALL;
772 break;
773 default:
774 pci_err(priv->pci_dev, "Unsupported transaction %d\n", command);
775 return -EOPNOTSUPP;
776 }
777
778 ret = i801_transaction(priv, xact);
779 if (ret || read_write == I2C_SMBUS_WRITE)
780 return ret;
781
782 switch (command) {
783 case I2C_SMBUS_BYTE:
784 case I2C_SMBUS_BYTE_DATA:
785 data->byte = inb_p(SMBHSTDAT0(priv));
786 break;
787 case I2C_SMBUS_WORD_DATA:
788 case I2C_SMBUS_PROC_CALL:
789 data->word = inb_p(SMBHSTDAT0(priv)) +
790 (inb_p(SMBHSTDAT1(priv)) << 8);
791 break;
792 }
793
794 return 0;
795 }
796
797 /* Block transaction function */
i801_block_transaction(struct i801_priv * priv,union i2c_smbus_data * data,u8 addr,u8 hstcmd,char read_write,int command)798 static int i801_block_transaction(struct i801_priv *priv, union i2c_smbus_data *data,
799 u8 addr, u8 hstcmd, char read_write, int command)
800 {
801 int result = 0;
802 unsigned char hostc;
803
804 if (read_write == I2C_SMBUS_READ && command == I2C_SMBUS_BLOCK_DATA)
805 data->block[0] = I2C_SMBUS_BLOCK_MAX;
806 else if (data->block[0] < 1 || data->block[0] > I2C_SMBUS_BLOCK_MAX)
807 return -EPROTO;
808
809 switch (command) {
810 case I2C_SMBUS_BLOCK_DATA:
811 i801_set_hstadd(priv, addr, read_write);
812 outb_p(hstcmd, SMBHSTCMD(priv));
813 break;
814 case I2C_SMBUS_I2C_BLOCK_DATA:
815 /*
816 * NB: page 240 of ICH5 datasheet shows that the R/#W
817 * bit should be cleared here, even when reading.
818 * However if SPD Write Disable is set (Lynx Point and later),
819 * the read will fail if we don't set the R/#W bit.
820 */
821 i801_set_hstadd(priv, addr,
822 priv->original_hstcfg & SMBHSTCFG_SPD_WD ?
823 read_write : I2C_SMBUS_WRITE);
824 if (read_write == I2C_SMBUS_READ) {
825 /* NB: page 240 of ICH5 datasheet also shows
826 * that DATA1 is the cmd field when reading
827 */
828 outb_p(hstcmd, SMBHSTDAT1(priv));
829 } else
830 outb_p(hstcmd, SMBHSTCMD(priv));
831
832 if (read_write == I2C_SMBUS_WRITE) {
833 /* set I2C_EN bit in configuration register */
834 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
835 pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
836 hostc | SMBHSTCFG_I2C_EN);
837 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
838 dev_err(&priv->pci_dev->dev,
839 "I2C block read is unsupported!\n");
840 return -EOPNOTSUPP;
841 }
842 break;
843 case I2C_SMBUS_BLOCK_PROC_CALL:
844 /* Needs to be flagged as write transaction */
845 i801_set_hstadd(priv, addr, I2C_SMBUS_WRITE);
846 outb_p(hstcmd, SMBHSTCMD(priv));
847 break;
848 }
849
850 /* Experience has shown that the block buffer can only be used for
851 SMBus (not I2C) block transactions, even though the datasheet
852 doesn't mention this limitation. */
853 if ((priv->features & FEATURE_BLOCK_BUFFER) &&
854 command != I2C_SMBUS_I2C_BLOCK_DATA)
855 result = i801_block_transaction_by_block(priv, data,
856 read_write,
857 command);
858 else
859 result = i801_block_transaction_byte_by_byte(priv, data,
860 read_write,
861 command);
862
863 if (command == I2C_SMBUS_I2C_BLOCK_DATA
864 && read_write == I2C_SMBUS_WRITE) {
865 /* restore saved configuration register value */
866 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
867 }
868 return result;
869 }
870
871 /* Return negative errno on error. */
i801_access(struct i2c_adapter * adap,u16 addr,unsigned short flags,char read_write,u8 command,int size,union i2c_smbus_data * data)872 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
873 unsigned short flags, char read_write, u8 command,
874 int size, union i2c_smbus_data *data)
875 {
876 int hwpec, ret;
877 struct i801_priv *priv = i2c_get_adapdata(adap);
878
879 mutex_lock(&priv->acpi_lock);
880 if (priv->acpi_reserved) {
881 mutex_unlock(&priv->acpi_lock);
882 return -EBUSY;
883 }
884
885 pm_runtime_get_sync(&priv->pci_dev->dev);
886
887 ret = i801_check_pre(priv);
888 if (ret)
889 goto out;
890
891 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
892 && size != I2C_SMBUS_QUICK
893 && size != I2C_SMBUS_I2C_BLOCK_DATA;
894
895 if (hwpec) /* enable/disable hardware PEC */
896 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
897 else
898 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
899 SMBAUXCTL(priv));
900
901 if (size == I2C_SMBUS_BLOCK_DATA ||
902 size == I2C_SMBUS_I2C_BLOCK_DATA ||
903 size == I2C_SMBUS_BLOCK_PROC_CALL)
904 ret = i801_block_transaction(priv, data, addr, command, read_write, size);
905 else
906 ret = i801_simple_transaction(priv, data, addr, command, read_write, size);
907
908 ret = i801_check_post(priv, ret);
909
910 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
911 * time, so we forcibly disable it after every transaction.
912 */
913 if (hwpec)
914 outb_p(inb_p(SMBAUXCTL(priv)) & ~SMBAUXCTL_CRC, SMBAUXCTL(priv));
915 out:
916 /*
917 * Unlock the SMBus device for use by BIOS/ACPI,
918 * and clear status flags if not done already.
919 */
920 outb_p(SMBHSTSTS_INUSE_STS | STATUS_FLAGS, SMBHSTSTS(priv));
921
922 pm_runtime_mark_last_busy(&priv->pci_dev->dev);
923 pm_runtime_put_autosuspend(&priv->pci_dev->dev);
924 mutex_unlock(&priv->acpi_lock);
925 return ret;
926 }
927
928
i801_func(struct i2c_adapter * adapter)929 static u32 i801_func(struct i2c_adapter *adapter)
930 {
931 struct i801_priv *priv = i2c_get_adapdata(adapter);
932
933 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
934 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
935 I2C_FUNC_SMBUS_PROC_CALL |
936 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
937 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
938 ((priv->features & FEATURE_BLOCK_PROC) ?
939 I2C_FUNC_SMBUS_BLOCK_PROC_CALL : 0) |
940 ((priv->features & FEATURE_I2C_BLOCK_READ) ?
941 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) |
942 ((priv->features & FEATURE_HOST_NOTIFY) ?
943 I2C_FUNC_SMBUS_HOST_NOTIFY : 0);
944 }
945
i801_enable_host_notify(struct i2c_adapter * adapter)946 static void i801_enable_host_notify(struct i2c_adapter *adapter)
947 {
948 struct i801_priv *priv = i2c_get_adapdata(adapter);
949
950 if (!(priv->features & FEATURE_HOST_NOTIFY))
951 return;
952
953 /*
954 * Enable host notify interrupt and block the generation of interrupt
955 * from the SMB_ALERT signal because the driver does not support
956 * SMBus Alert.
957 */
958 outb_p(SMBSLVCMD_HST_NTFY_INTREN | SMBSLVCMD_SMBALERT_DISABLE |
959 priv->original_slvcmd, SMBSLVCMD(priv));
960
961 /* clear Host Notify bit to allow a new notification */
962 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
963 }
964
i801_disable_host_notify(struct i801_priv * priv)965 static void i801_disable_host_notify(struct i801_priv *priv)
966 {
967 if (!(priv->features & FEATURE_HOST_NOTIFY))
968 return;
969
970 outb_p(priv->original_slvcmd, SMBSLVCMD(priv));
971 }
972
973 static const struct i2c_algorithm smbus_algorithm = {
974 .smbus_xfer = i801_access,
975 .functionality = i801_func,
976 };
977
978 #define FEATURES_ICH5 (FEATURE_BLOCK_PROC | FEATURE_I2C_BLOCK_READ | \
979 FEATURE_IRQ | FEATURE_SMBUS_PEC | \
980 FEATURE_BLOCK_BUFFER | FEATURE_HOST_NOTIFY)
981 #define FEATURES_ICH4 (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER | \
982 FEATURE_HOST_NOTIFY)
983
984 static const struct pci_device_id i801_ids[] = {
985 { PCI_DEVICE_DATA(INTEL, 82801AA_3, 0) },
986 { PCI_DEVICE_DATA(INTEL, 82801AB_3, 0) },
987 { PCI_DEVICE_DATA(INTEL, 82801BA_2, 0) },
988 { PCI_DEVICE_DATA(INTEL, 82801CA_3, FEATURE_HOST_NOTIFY) },
989 { PCI_DEVICE_DATA(INTEL, 82801DB_3, FEATURES_ICH4) },
990 { PCI_DEVICE_DATA(INTEL, 82801EB_3, FEATURES_ICH5) },
991 { PCI_DEVICE_DATA(INTEL, ESB_4, FEATURES_ICH5) },
992 { PCI_DEVICE_DATA(INTEL, ICH6_16, FEATURES_ICH5) },
993 { PCI_DEVICE_DATA(INTEL, ICH7_17, FEATURES_ICH5) },
994 { PCI_DEVICE_DATA(INTEL, ESB2_17, FEATURES_ICH5) },
995 { PCI_DEVICE_DATA(INTEL, ICH8_5, FEATURES_ICH5) },
996 { PCI_DEVICE_DATA(INTEL, ICH9_6, FEATURES_ICH5) },
997 { PCI_DEVICE_DATA(INTEL, EP80579_1, FEATURES_ICH5) },
998 { PCI_DEVICE_DATA(INTEL, ICH10_4, FEATURES_ICH5) },
999 { PCI_DEVICE_DATA(INTEL, ICH10_5, FEATURES_ICH5) },
1000 { PCI_DEVICE_DATA(INTEL, 5_3400_SERIES_SMBUS, FEATURES_ICH5) },
1001 { PCI_DEVICE_DATA(INTEL, COUGARPOINT_SMBUS, FEATURES_ICH5) },
1002 { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS, FEATURES_ICH5) },
1003 { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF0, FEATURES_ICH5 | FEATURE_IDF) },
1004 { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF1, FEATURES_ICH5 | FEATURE_IDF) },
1005 { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF2, FEATURES_ICH5 | FEATURE_IDF) },
1006 { PCI_DEVICE_DATA(INTEL, DH89XXCC_SMBUS, FEATURES_ICH5) },
1007 { PCI_DEVICE_DATA(INTEL, PANTHERPOINT_SMBUS, FEATURES_ICH5) },
1008 { PCI_DEVICE_DATA(INTEL, LYNXPOINT_SMBUS, FEATURES_ICH5) },
1009 { PCI_DEVICE_DATA(INTEL, LYNXPOINT_LP_SMBUS, FEATURES_ICH5) },
1010 { PCI_DEVICE_DATA(INTEL, AVOTON_SMBUS, FEATURES_ICH5) },
1011 { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS, FEATURES_ICH5) },
1012 { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS0, FEATURES_ICH5 | FEATURE_IDF) },
1013 { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS1, FEATURES_ICH5 | FEATURE_IDF) },
1014 { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS2, FEATURES_ICH5 | FEATURE_IDF) },
1015 { PCI_DEVICE_DATA(INTEL, COLETOCREEK_SMBUS, FEATURES_ICH5) },
1016 { PCI_DEVICE_DATA(INTEL, GEMINILAKE_SMBUS, FEATURES_ICH5) },
1017 { PCI_DEVICE_DATA(INTEL, WILDCATPOINT_SMBUS, FEATURES_ICH5) },
1018 { PCI_DEVICE_DATA(INTEL, WILDCATPOINT_LP_SMBUS, FEATURES_ICH5) },
1019 { PCI_DEVICE_DATA(INTEL, BAYTRAIL_SMBUS, FEATURES_ICH5) },
1020 { PCI_DEVICE_DATA(INTEL, BRASWELL_SMBUS, FEATURES_ICH5) },
1021 { PCI_DEVICE_DATA(INTEL, SUNRISEPOINT_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
1022 { PCI_DEVICE_DATA(INTEL, SUNRISEPOINT_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
1023 { PCI_DEVICE_DATA(INTEL, CDF_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1024 { PCI_DEVICE_DATA(INTEL, DNV_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
1025 { PCI_DEVICE_DATA(INTEL, EBG_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1026 { PCI_DEVICE_DATA(INTEL, BROXTON_SMBUS, FEATURES_ICH5) },
1027 { PCI_DEVICE_DATA(INTEL, LEWISBURG_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
1028 { PCI_DEVICE_DATA(INTEL, LEWISBURG_SSKU_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
1029 { PCI_DEVICE_DATA(INTEL, KABYLAKE_PCH_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
1030 { PCI_DEVICE_DATA(INTEL, CANNONLAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1031 { PCI_DEVICE_DATA(INTEL, CANNONLAKE_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1032 { PCI_DEVICE_DATA(INTEL, ICELAKE_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1033 { PCI_DEVICE_DATA(INTEL, ICELAKE_N_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1034 { PCI_DEVICE_DATA(INTEL, COMETLAKE_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1035 { PCI_DEVICE_DATA(INTEL, COMETLAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1036 { PCI_DEVICE_DATA(INTEL, COMETLAKE_V_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
1037 { PCI_DEVICE_DATA(INTEL, ELKHART_LAKE_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1038 { PCI_DEVICE_DATA(INTEL, TIGERLAKE_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1039 { PCI_DEVICE_DATA(INTEL, TIGERLAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1040 { PCI_DEVICE_DATA(INTEL, JASPER_LAKE_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1041 { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1042 { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_P_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1043 { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_M_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1044 { PCI_DEVICE_DATA(INTEL, RAPTOR_LAKE_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1045 { PCI_DEVICE_DATA(INTEL, METEOR_LAKE_P_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1046 { PCI_DEVICE_DATA(INTEL, METEOR_LAKE_SOC_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1047 { PCI_DEVICE_DATA(INTEL, METEOR_LAKE_PCH_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1048 { PCI_DEVICE_DATA(INTEL, BIRCH_STREAM_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1049 { 0, }
1050 };
1051
1052 MODULE_DEVICE_TABLE(pci, i801_ids);
1053
1054 #if defined CONFIG_X86 && defined CONFIG_DMI
1055 static unsigned char apanel_addr __ro_after_init;
1056
1057 /* Scan the system ROM for the signature "FJKEYINF" */
bios_signature(const void __iomem * bios)1058 static __init const void __iomem *bios_signature(const void __iomem *bios)
1059 {
1060 ssize_t offset;
1061 const unsigned char signature[] = "FJKEYINF";
1062
1063 for (offset = 0; offset < 0x10000; offset += 0x10) {
1064 if (check_signature(bios + offset, signature,
1065 sizeof(signature)-1))
1066 return bios + offset;
1067 }
1068 return NULL;
1069 }
1070
input_apanel_init(void)1071 static void __init input_apanel_init(void)
1072 {
1073 void __iomem *bios;
1074 const void __iomem *p;
1075
1076 bios = ioremap(0xF0000, 0x10000); /* Can't fail */
1077 p = bios_signature(bios);
1078 if (p) {
1079 /* just use the first address */
1080 apanel_addr = readb(p + 8 + 3) >> 1;
1081 }
1082 iounmap(bios);
1083 }
1084
1085 struct dmi_onboard_device_info {
1086 const char *name;
1087 u8 type;
1088 unsigned short i2c_addr;
1089 const char *i2c_type;
1090 };
1091
1092 static const struct dmi_onboard_device_info dmi_devices[] = {
1093 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
1094 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
1095 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
1096 };
1097
dmi_check_onboard_device(u8 type,const char * name,struct i2c_adapter * adap)1098 static void dmi_check_onboard_device(u8 type, const char *name,
1099 struct i2c_adapter *adap)
1100 {
1101 int i;
1102 struct i2c_board_info info;
1103
1104 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
1105 /* & ~0x80, ignore enabled/disabled bit */
1106 if ((type & ~0x80) != dmi_devices[i].type)
1107 continue;
1108 if (strcasecmp(name, dmi_devices[i].name))
1109 continue;
1110
1111 memset(&info, 0, sizeof(struct i2c_board_info));
1112 info.addr = dmi_devices[i].i2c_addr;
1113 strscpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
1114 i2c_new_client_device(adap, &info);
1115 break;
1116 }
1117 }
1118
1119 /* We use our own function to check for onboard devices instead of
1120 dmi_find_device() as some buggy BIOS's have the devices we are interested
1121 in marked as disabled */
dmi_check_onboard_devices(const struct dmi_header * dm,void * adap)1122 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
1123 {
1124 int i, count;
1125
1126 if (dm->type != 10)
1127 return;
1128
1129 count = (dm->length - sizeof(struct dmi_header)) / 2;
1130 for (i = 0; i < count; i++) {
1131 const u8 *d = (char *)(dm + 1) + (i * 2);
1132 const char *name = ((char *) dm) + dm->length;
1133 u8 type = d[0];
1134 u8 s = d[1];
1135
1136 if (!s)
1137 continue;
1138 s--;
1139 while (s > 0 && name[0]) {
1140 name += strlen(name) + 1;
1141 s--;
1142 }
1143 if (name[0] == 0) /* Bogus string reference */
1144 continue;
1145
1146 dmi_check_onboard_device(type, name, adap);
1147 }
1148 }
1149
1150 /* NOTE: Keep this list in sync with drivers/platform/x86/dell-smo8800.c */
1151 static const char *const acpi_smo8800_ids[] = {
1152 "SMO8800",
1153 "SMO8801",
1154 "SMO8810",
1155 "SMO8811",
1156 "SMO8820",
1157 "SMO8821",
1158 "SMO8830",
1159 "SMO8831",
1160 };
1161
check_acpi_smo88xx_device(acpi_handle obj_handle,u32 nesting_level,void * context,void ** return_value)1162 static acpi_status check_acpi_smo88xx_device(acpi_handle obj_handle,
1163 u32 nesting_level,
1164 void *context,
1165 void **return_value)
1166 {
1167 struct acpi_device_info *info;
1168 acpi_status status;
1169 char *hid;
1170 int i;
1171
1172 status = acpi_get_object_info(obj_handle, &info);
1173 if (ACPI_FAILURE(status))
1174 return AE_OK;
1175
1176 if (!(info->valid & ACPI_VALID_HID))
1177 goto smo88xx_not_found;
1178
1179 hid = info->hardware_id.string;
1180 if (!hid)
1181 goto smo88xx_not_found;
1182
1183 i = match_string(acpi_smo8800_ids, ARRAY_SIZE(acpi_smo8800_ids), hid);
1184 if (i < 0)
1185 goto smo88xx_not_found;
1186
1187 kfree(info);
1188
1189 *return_value = NULL;
1190 return AE_CTRL_TERMINATE;
1191
1192 smo88xx_not_found:
1193 kfree(info);
1194 return AE_OK;
1195 }
1196
is_dell_system_with_lis3lv02d(void)1197 static bool is_dell_system_with_lis3lv02d(void)
1198 {
1199 void *err = ERR_PTR(-ENOENT);
1200
1201 if (!dmi_match(DMI_SYS_VENDOR, "Dell Inc."))
1202 return false;
1203
1204 /*
1205 * Check that ACPI device SMO88xx is present and is functioning.
1206 * Function acpi_get_devices() already filters all ACPI devices
1207 * which are not present or are not functioning.
1208 * ACPI device SMO88xx represents our ST microelectronics lis3lv02d
1209 * accelerometer but unfortunately ACPI does not provide any other
1210 * information (like I2C address).
1211 */
1212 acpi_get_devices(NULL, check_acpi_smo88xx_device, NULL, &err);
1213
1214 return !IS_ERR(err);
1215 }
1216
1217 /*
1218 * Accelerometer's I2C address is not specified in DMI nor ACPI,
1219 * so it is needed to define mapping table based on DMI product names.
1220 */
1221 static const struct {
1222 const char *dmi_product_name;
1223 unsigned short i2c_addr;
1224 } dell_lis3lv02d_devices[] = {
1225 /*
1226 * Dell platform team told us that these Latitude devices have
1227 * ST microelectronics accelerometer at I2C address 0x29.
1228 */
1229 { "Latitude E5250", 0x29 },
1230 { "Latitude E5450", 0x29 },
1231 { "Latitude E5550", 0x29 },
1232 { "Latitude E6440", 0x29 },
1233 { "Latitude E6440 ATG", 0x29 },
1234 { "Latitude E6540", 0x29 },
1235 /*
1236 * Additional individual entries were added after verification.
1237 */
1238 { "Latitude 5480", 0x29 },
1239 { "Vostro V131", 0x1d },
1240 { "Vostro 5568", 0x29 },
1241 };
1242
register_dell_lis3lv02d_i2c_device(struct i801_priv * priv)1243 static void register_dell_lis3lv02d_i2c_device(struct i801_priv *priv)
1244 {
1245 struct i2c_board_info info;
1246 const char *dmi_product_name;
1247 int i;
1248
1249 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
1250 for (i = 0; i < ARRAY_SIZE(dell_lis3lv02d_devices); ++i) {
1251 if (strcmp(dmi_product_name,
1252 dell_lis3lv02d_devices[i].dmi_product_name) == 0)
1253 break;
1254 }
1255
1256 if (i == ARRAY_SIZE(dell_lis3lv02d_devices)) {
1257 dev_warn(&priv->pci_dev->dev,
1258 "Accelerometer lis3lv02d is present on SMBus but its"
1259 " address is unknown, skipping registration\n");
1260 return;
1261 }
1262
1263 memset(&info, 0, sizeof(struct i2c_board_info));
1264 info.addr = dell_lis3lv02d_devices[i].i2c_addr;
1265 strscpy(info.type, "lis3lv02d", I2C_NAME_SIZE);
1266 i2c_new_client_device(&priv->adapter, &info);
1267 }
1268
1269 /* Register optional slaves */
i801_probe_optional_slaves(struct i801_priv * priv)1270 static void i801_probe_optional_slaves(struct i801_priv *priv)
1271 {
1272 /* Only register slaves on main SMBus channel */
1273 if (priv->features & FEATURE_IDF)
1274 return;
1275
1276 if (apanel_addr) {
1277 struct i2c_board_info info = {
1278 .addr = apanel_addr,
1279 .type = "fujitsu_apanel",
1280 };
1281
1282 i2c_new_client_device(&priv->adapter, &info);
1283 }
1284
1285 if (dmi_name_in_vendors("FUJITSU"))
1286 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
1287
1288 if (is_dell_system_with_lis3lv02d())
1289 register_dell_lis3lv02d_i2c_device(priv);
1290
1291 /* Instantiate SPD EEPROMs unless the SMBus is multiplexed */
1292 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO)
1293 if (!priv->mux_drvdata)
1294 #endif
1295 i2c_register_spd(&priv->adapter);
1296 }
1297 #else
input_apanel_init(void)1298 static void __init input_apanel_init(void) {}
i801_probe_optional_slaves(struct i801_priv * priv)1299 static void i801_probe_optional_slaves(struct i801_priv *priv) {}
1300 #endif /* CONFIG_X86 && CONFIG_DMI */
1301
1302 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
1303 static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
1304 .gpio_chip = "gpio_ich",
1305 .values = { 0x02, 0x03 },
1306 .n_values = 2,
1307 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD },
1308 .gpios = { 52, 53 },
1309 .n_gpios = 2,
1310 };
1311
1312 static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
1313 .gpio_chip = "gpio_ich",
1314 .values = { 0x02, 0x03, 0x01 },
1315 .n_values = 3,
1316 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD },
1317 .gpios = { 52, 53 },
1318 .n_gpios = 2,
1319 };
1320
1321 static const struct dmi_system_id mux_dmi_table[] = {
1322 {
1323 .matches = {
1324 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1325 DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
1326 },
1327 .driver_data = &i801_mux_config_asus_z8_d12,
1328 },
1329 {
1330 .matches = {
1331 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1332 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
1333 },
1334 .driver_data = &i801_mux_config_asus_z8_d12,
1335 },
1336 {
1337 .matches = {
1338 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1339 DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
1340 },
1341 .driver_data = &i801_mux_config_asus_z8_d12,
1342 },
1343 {
1344 .matches = {
1345 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1346 DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
1347 },
1348 .driver_data = &i801_mux_config_asus_z8_d12,
1349 },
1350 {
1351 .matches = {
1352 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1353 DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
1354 },
1355 .driver_data = &i801_mux_config_asus_z8_d12,
1356 },
1357 {
1358 .matches = {
1359 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1360 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1361 },
1362 .driver_data = &i801_mux_config_asus_z8_d12,
1363 },
1364 {
1365 .matches = {
1366 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1367 DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1368 },
1369 .driver_data = &i801_mux_config_asus_z8_d18,
1370 },
1371 {
1372 .matches = {
1373 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1374 DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1375 },
1376 .driver_data = &i801_mux_config_asus_z8_d18,
1377 },
1378 {
1379 .matches = {
1380 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1381 DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1382 },
1383 .driver_data = &i801_mux_config_asus_z8_d12,
1384 },
1385 { }
1386 };
1387
1388 /* Setup multiplexing if needed */
i801_add_mux(struct i801_priv * priv)1389 static void i801_add_mux(struct i801_priv *priv)
1390 {
1391 struct device *dev = &priv->adapter.dev;
1392 const struct i801_mux_config *mux_config;
1393 struct i2c_mux_gpio_platform_data gpio_data;
1394 struct gpiod_lookup_table *lookup;
1395 int i;
1396
1397 if (!priv->mux_drvdata)
1398 return;
1399 mux_config = priv->mux_drvdata;
1400
1401 /* Prepare the platform data */
1402 memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1403 gpio_data.parent = priv->adapter.nr;
1404 gpio_data.values = mux_config->values;
1405 gpio_data.n_values = mux_config->n_values;
1406 gpio_data.classes = mux_config->classes;
1407 gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1408
1409 /* Register GPIO descriptor lookup table */
1410 lookup = devm_kzalloc(dev,
1411 struct_size(lookup, table, mux_config->n_gpios + 1),
1412 GFP_KERNEL);
1413 if (!lookup)
1414 return;
1415 lookup->dev_id = "i2c-mux-gpio";
1416 for (i = 0; i < mux_config->n_gpios; i++)
1417 lookup->table[i] = GPIO_LOOKUP(mux_config->gpio_chip,
1418 mux_config->gpios[i], "mux", 0);
1419 gpiod_add_lookup_table(lookup);
1420
1421 /*
1422 * Register the mux device, we use PLATFORM_DEVID_NONE here
1423 * because since we are referring to the GPIO chip by name we are
1424 * anyways in deep trouble if there is more than one of these
1425 * devices, and there should likely only be one platform controller
1426 * hub.
1427 */
1428 priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1429 PLATFORM_DEVID_NONE, &gpio_data,
1430 sizeof(struct i2c_mux_gpio_platform_data));
1431 if (IS_ERR(priv->mux_pdev)) {
1432 gpiod_remove_lookup_table(lookup);
1433 devm_kfree(dev, lookup);
1434 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1435 } else {
1436 priv->lookup = lookup;
1437 }
1438 }
1439
i801_del_mux(struct i801_priv * priv)1440 static void i801_del_mux(struct i801_priv *priv)
1441 {
1442 platform_device_unregister(priv->mux_pdev);
1443 gpiod_remove_lookup_table(priv->lookup);
1444 }
1445
i801_get_adapter_class(struct i801_priv * priv)1446 static unsigned int i801_get_adapter_class(struct i801_priv *priv)
1447 {
1448 const struct dmi_system_id *id;
1449 const struct i801_mux_config *mux_config;
1450 unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1451 int i;
1452
1453 id = dmi_first_match(mux_dmi_table);
1454 if (id) {
1455 /* Remove branch classes from trunk */
1456 mux_config = id->driver_data;
1457 for (i = 0; i < mux_config->n_values; i++)
1458 class &= ~mux_config->classes[i];
1459
1460 /* Remember for later */
1461 priv->mux_drvdata = mux_config;
1462 }
1463
1464 return class;
1465 }
1466 #else
i801_add_mux(struct i801_priv * priv)1467 static inline void i801_add_mux(struct i801_priv *priv) { }
i801_del_mux(struct i801_priv * priv)1468 static inline void i801_del_mux(struct i801_priv *priv) { }
1469
i801_get_adapter_class(struct i801_priv * priv)1470 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv)
1471 {
1472 return I2C_CLASS_HWMON | I2C_CLASS_SPD;
1473 }
1474 #endif
1475
1476 static struct platform_device *
i801_add_tco_spt(struct i801_priv * priv,struct pci_dev * pci_dev,struct resource * tco_res)1477 i801_add_tco_spt(struct i801_priv *priv, struct pci_dev *pci_dev,
1478 struct resource *tco_res)
1479 {
1480 static const struct itco_wdt_platform_data pldata = {
1481 .name = "Intel PCH",
1482 .version = 4,
1483 };
1484 struct resource *res;
1485 int ret;
1486
1487 /*
1488 * We must access the NO_REBOOT bit over the Primary to Sideband
1489 * (P2SB) bridge.
1490 */
1491
1492 res = &tco_res[1];
1493 ret = p2sb_bar(pci_dev->bus, 0, res);
1494 if (ret)
1495 return ERR_PTR(ret);
1496
1497 if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS)
1498 res->start += SBREG_SMBCTRL_DNV;
1499 else
1500 res->start += SBREG_SMBCTRL;
1501
1502 res->end = res->start + 3;
1503
1504 return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1505 tco_res, 2, &pldata, sizeof(pldata));
1506 }
1507
1508 static struct platform_device *
i801_add_tco_cnl(struct i801_priv * priv,struct pci_dev * pci_dev,struct resource * tco_res)1509 i801_add_tco_cnl(struct i801_priv *priv, struct pci_dev *pci_dev,
1510 struct resource *tco_res)
1511 {
1512 static const struct itco_wdt_platform_data pldata = {
1513 .name = "Intel PCH",
1514 .version = 6,
1515 };
1516
1517 return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1518 tco_res, 1, &pldata, sizeof(pldata));
1519 }
1520
i801_add_tco(struct i801_priv * priv)1521 static void i801_add_tco(struct i801_priv *priv)
1522 {
1523 struct pci_dev *pci_dev = priv->pci_dev;
1524 struct resource tco_res[2], *res;
1525 u32 tco_base, tco_ctl;
1526
1527 /* If we have ACPI based watchdog use that instead */
1528 if (acpi_has_watchdog())
1529 return;
1530
1531 if (!(priv->features & (FEATURE_TCO_SPT | FEATURE_TCO_CNL)))
1532 return;
1533
1534 pci_read_config_dword(pci_dev, TCOBASE, &tco_base);
1535 pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl);
1536 if (!(tco_ctl & TCOCTL_EN))
1537 return;
1538
1539 memset(tco_res, 0, sizeof(tco_res));
1540 /*
1541 * Always populate the main iTCO IO resource here. The second entry
1542 * for NO_REBOOT MMIO is filled by the SPT specific function.
1543 */
1544 res = &tco_res[0];
1545 res->start = tco_base & ~1;
1546 res->end = res->start + 32 - 1;
1547 res->flags = IORESOURCE_IO;
1548
1549 if (priv->features & FEATURE_TCO_CNL)
1550 priv->tco_pdev = i801_add_tco_cnl(priv, pci_dev, tco_res);
1551 else
1552 priv->tco_pdev = i801_add_tco_spt(priv, pci_dev, tco_res);
1553
1554 if (IS_ERR(priv->tco_pdev))
1555 dev_warn(&pci_dev->dev, "failed to create iTCO device\n");
1556 }
1557
1558 #ifdef CONFIG_ACPI
i801_acpi_is_smbus_ioport(const struct i801_priv * priv,acpi_physical_address address)1559 static bool i801_acpi_is_smbus_ioport(const struct i801_priv *priv,
1560 acpi_physical_address address)
1561 {
1562 return address >= priv->smba &&
1563 address <= pci_resource_end(priv->pci_dev, SMBBAR);
1564 }
1565
1566 static acpi_status
i801_acpi_io_handler(u32 function,acpi_physical_address address,u32 bits,u64 * value,void * handler_context,void * region_context)1567 i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits,
1568 u64 *value, void *handler_context, void *region_context)
1569 {
1570 struct i801_priv *priv = handler_context;
1571 struct pci_dev *pdev = priv->pci_dev;
1572 acpi_status status;
1573
1574 /*
1575 * Once BIOS AML code touches the OpRegion we warn and inhibit any
1576 * further access from the driver itself. This device is now owned
1577 * by the system firmware.
1578 */
1579 mutex_lock(&priv->acpi_lock);
1580
1581 if (!priv->acpi_reserved && i801_acpi_is_smbus_ioport(priv, address)) {
1582 priv->acpi_reserved = true;
1583
1584 dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n");
1585 dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n");
1586
1587 /*
1588 * BIOS is accessing the host controller so prevent it from
1589 * suspending automatically from now on.
1590 */
1591 pm_runtime_get_sync(&pdev->dev);
1592 }
1593
1594 if ((function & ACPI_IO_MASK) == ACPI_READ)
1595 status = acpi_os_read_port(address, (u32 *)value, bits);
1596 else
1597 status = acpi_os_write_port(address, (u32)*value, bits);
1598
1599 mutex_unlock(&priv->acpi_lock);
1600
1601 return status;
1602 }
1603
i801_acpi_probe(struct i801_priv * priv)1604 static int i801_acpi_probe(struct i801_priv *priv)
1605 {
1606 acpi_handle ah = ACPI_HANDLE(&priv->pci_dev->dev);
1607 acpi_status status;
1608
1609 status = acpi_install_address_space_handler(ah, ACPI_ADR_SPACE_SYSTEM_IO,
1610 i801_acpi_io_handler, NULL, priv);
1611 if (ACPI_SUCCESS(status))
1612 return 0;
1613
1614 return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]);
1615 }
1616
i801_acpi_remove(struct i801_priv * priv)1617 static void i801_acpi_remove(struct i801_priv *priv)
1618 {
1619 acpi_handle ah = ACPI_HANDLE(&priv->pci_dev->dev);
1620
1621 acpi_remove_address_space_handler(ah, ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler);
1622 }
1623 #else
i801_acpi_probe(struct i801_priv * priv)1624 static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; }
i801_acpi_remove(struct i801_priv * priv)1625 static inline void i801_acpi_remove(struct i801_priv *priv) { }
1626 #endif
1627
i801_setup_hstcfg(struct i801_priv * priv)1628 static void i801_setup_hstcfg(struct i801_priv *priv)
1629 {
1630 unsigned char hstcfg = priv->original_hstcfg;
1631
1632 hstcfg &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
1633 hstcfg |= SMBHSTCFG_HST_EN;
1634 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hstcfg);
1635 }
1636
i801_probe(struct pci_dev * dev,const struct pci_device_id * id)1637 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1638 {
1639 int err, i;
1640 struct i801_priv *priv;
1641
1642 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
1643 if (!priv)
1644 return -ENOMEM;
1645
1646 i2c_set_adapdata(&priv->adapter, priv);
1647 priv->adapter.owner = THIS_MODULE;
1648 priv->adapter.class = i801_get_adapter_class(priv);
1649 priv->adapter.algo = &smbus_algorithm;
1650 priv->adapter.dev.parent = &dev->dev;
1651 ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev));
1652 priv->adapter.retries = 3;
1653 mutex_init(&priv->acpi_lock);
1654
1655 priv->pci_dev = dev;
1656 priv->features = id->driver_data;
1657
1658 /* Disable features on user request */
1659 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1660 if (priv->features & disable_features & (1 << i))
1661 dev_notice(&dev->dev, "%s disabled by user\n",
1662 i801_feature_names[i]);
1663 }
1664 priv->features &= ~disable_features;
1665
1666 /* The block process call uses block buffer mode */
1667 if (!(priv->features & FEATURE_BLOCK_BUFFER))
1668 priv->features &= ~FEATURE_BLOCK_PROC;
1669
1670 err = pcim_enable_device(dev);
1671 if (err) {
1672 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1673 err);
1674 return err;
1675 }
1676 pcim_pin_device(dev);
1677
1678 /* Determine the address of the SMBus area */
1679 priv->smba = pci_resource_start(dev, SMBBAR);
1680 if (!priv->smba) {
1681 dev_err(&dev->dev,
1682 "SMBus base address uninitialized, upgrade BIOS\n");
1683 return -ENODEV;
1684 }
1685
1686 if (i801_acpi_probe(priv))
1687 return -ENODEV;
1688
1689 err = pcim_iomap_regions(dev, 1 << SMBBAR, DRV_NAME);
1690 if (err) {
1691 dev_err(&dev->dev,
1692 "Failed to request SMBus region 0x%lx-0x%Lx\n",
1693 priv->smba,
1694 (unsigned long long)pci_resource_end(dev, SMBBAR));
1695 i801_acpi_remove(priv);
1696 return err;
1697 }
1698
1699 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &priv->original_hstcfg);
1700 i801_setup_hstcfg(priv);
1701 if (!(priv->original_hstcfg & SMBHSTCFG_HST_EN))
1702 dev_info(&dev->dev, "Enabling SMBus device\n");
1703
1704 if (priv->original_hstcfg & SMBHSTCFG_SMB_SMI_EN) {
1705 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
1706 /* Disable SMBus interrupt feature if SMBus using SMI# */
1707 priv->features &= ~FEATURE_IRQ;
1708 }
1709 if (priv->original_hstcfg & SMBHSTCFG_SPD_WD)
1710 dev_info(&dev->dev, "SPD Write Disable is set\n");
1711
1712 /* Clear special mode bits */
1713 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1714 outb_p(inb_p(SMBAUXCTL(priv)) &
1715 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1716
1717 /* Default timeout in interrupt mode: 200 ms */
1718 priv->adapter.timeout = HZ / 5;
1719
1720 if (dev->irq == IRQ_NOTCONNECTED)
1721 priv->features &= ~FEATURE_IRQ;
1722
1723 if (priv->features & FEATURE_IRQ) {
1724 u16 pcists;
1725
1726 /* Complain if an interrupt is already pending */
1727 pci_read_config_word(priv->pci_dev, PCI_STATUS, &pcists);
1728 if (pcists & PCI_STATUS_INTERRUPT)
1729 dev_warn(&dev->dev, "An interrupt is pending!\n");
1730 }
1731
1732 if (priv->features & FEATURE_IRQ) {
1733 init_completion(&priv->done);
1734
1735 err = devm_request_irq(&dev->dev, dev->irq, i801_isr,
1736 IRQF_SHARED, DRV_NAME, priv);
1737 if (err) {
1738 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1739 dev->irq, err);
1740 priv->features &= ~FEATURE_IRQ;
1741 }
1742 }
1743 dev_info(&dev->dev, "SMBus using %s\n",
1744 priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling");
1745
1746 /* Host notification uses an interrupt */
1747 if (!(priv->features & FEATURE_IRQ))
1748 priv->features &= ~FEATURE_HOST_NOTIFY;
1749
1750 /* Remember original Interrupt and Host Notify settings */
1751 priv->original_hstcnt = inb_p(SMBHSTCNT(priv)) & ~SMBHSTCNT_KILL;
1752 if (priv->features & FEATURE_HOST_NOTIFY)
1753 priv->original_slvcmd = inb_p(SMBSLVCMD(priv));
1754
1755 i801_add_tco(priv);
1756
1757 /*
1758 * adapter.name is used by platform code to find the main I801 adapter
1759 * to instantiante i2c_clients, do not change.
1760 */
1761 snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1762 "SMBus %s adapter at %04lx",
1763 (priv->features & FEATURE_IDF) ? "I801 IDF" : "I801",
1764 priv->smba);
1765
1766 err = i2c_add_adapter(&priv->adapter);
1767 if (err) {
1768 platform_device_unregister(priv->tco_pdev);
1769 i801_acpi_remove(priv);
1770 return err;
1771 }
1772
1773 i801_enable_host_notify(&priv->adapter);
1774
1775 i801_probe_optional_slaves(priv);
1776 /* We ignore errors - multiplexing is optional */
1777 i801_add_mux(priv);
1778
1779 pci_set_drvdata(dev, priv);
1780
1781 dev_pm_set_driver_flags(&dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
1782 pm_runtime_set_autosuspend_delay(&dev->dev, 1000);
1783 pm_runtime_use_autosuspend(&dev->dev);
1784 pm_runtime_put_autosuspend(&dev->dev);
1785 pm_runtime_allow(&dev->dev);
1786
1787 return 0;
1788 }
1789
i801_remove(struct pci_dev * dev)1790 static void i801_remove(struct pci_dev *dev)
1791 {
1792 struct i801_priv *priv = pci_get_drvdata(dev);
1793
1794 outb_p(priv->original_hstcnt, SMBHSTCNT(priv));
1795 i801_disable_host_notify(priv);
1796 i801_del_mux(priv);
1797 i2c_del_adapter(&priv->adapter);
1798 i801_acpi_remove(priv);
1799 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1800
1801 platform_device_unregister(priv->tco_pdev);
1802
1803 /* if acpi_reserved is set then usage_count is incremented already */
1804 if (!priv->acpi_reserved)
1805 pm_runtime_get_noresume(&dev->dev);
1806
1807 /*
1808 * do not call pci_disable_device(dev) since it can cause hard hangs on
1809 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1810 */
1811 }
1812
i801_shutdown(struct pci_dev * dev)1813 static void i801_shutdown(struct pci_dev *dev)
1814 {
1815 struct i801_priv *priv = pci_get_drvdata(dev);
1816
1817 /* Restore config registers to avoid hard hang on some systems */
1818 outb_p(priv->original_hstcnt, SMBHSTCNT(priv));
1819 i801_disable_host_notify(priv);
1820 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1821 }
1822
i801_suspend(struct device * dev)1823 static int i801_suspend(struct device *dev)
1824 {
1825 struct i801_priv *priv = dev_get_drvdata(dev);
1826
1827 outb_p(priv->original_hstcnt, SMBHSTCNT(priv));
1828 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, priv->original_hstcfg);
1829 return 0;
1830 }
1831
i801_resume(struct device * dev)1832 static int i801_resume(struct device *dev)
1833 {
1834 struct i801_priv *priv = dev_get_drvdata(dev);
1835
1836 i801_setup_hstcfg(priv);
1837 i801_enable_host_notify(&priv->adapter);
1838
1839 return 0;
1840 }
1841
1842 static DEFINE_SIMPLE_DEV_PM_OPS(i801_pm_ops, i801_suspend, i801_resume);
1843
1844 static struct pci_driver i801_driver = {
1845 .name = DRV_NAME,
1846 .id_table = i801_ids,
1847 .probe = i801_probe,
1848 .remove = i801_remove,
1849 .shutdown = i801_shutdown,
1850 .driver = {
1851 .pm = pm_sleep_ptr(&i801_pm_ops),
1852 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1853 },
1854 };
1855
i2c_i801_init(void)1856 static int __init i2c_i801_init(void)
1857 {
1858 if (dmi_name_in_vendors("FUJITSU"))
1859 input_apanel_init();
1860 return pci_register_driver(&i801_driver);
1861 }
1862
i2c_i801_exit(void)1863 static void __exit i2c_i801_exit(void)
1864 {
1865 pci_unregister_driver(&i801_driver);
1866 }
1867
1868 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>");
1869 MODULE_AUTHOR("Jean Delvare <jdelvare@suse.de>");
1870 MODULE_DESCRIPTION("I801 SMBus driver");
1871 MODULE_LICENSE("GPL");
1872
1873 module_init(i2c_i801_init);
1874 module_exit(i2c_i801_exit);
1875