xref: /openbmc/linux/sound/soc/intel/avs/registers.h (revision 85ac9c8c)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright(c) 2021-2022 Intel Corporation. All rights reserved.
4  *
5  * Authors: Cezary Rojewski <cezary.rojewski@intel.com>
6  *          Amadeusz Slawinski <amadeuszx.slawinski@linux.intel.com>
7  */
8 
9 #ifndef __SOUND_SOC_INTEL_AVS_REGS_H
10 #define __SOUND_SOC_INTEL_AVS_REGS_H
11 
12 #define AZX_PCIREG_PGCTL		0x44
13 #define AZX_PCIREG_CGCTL		0x48
14 #define AZX_PGCTL_LSRMD_MASK		BIT(4)
15 #define AZX_CGCTL_MISCBDCGE_MASK	BIT(6)
16 #define AZX_VS_EM2_L1SEN		BIT(13)
17 #define AZX_VS_EM2_DUM			BIT(23)
18 
19 /* Intel HD Audio General DSP Registers */
20 #define AVS_ADSP_GEN_BASE		0x0
21 #define AVS_ADSP_REG_ADSPCS		(AVS_ADSP_GEN_BASE + 0x04)
22 #define AVS_ADSP_REG_ADSPIC		(AVS_ADSP_GEN_BASE + 0x08)
23 #define AVS_ADSP_REG_ADSPIS		(AVS_ADSP_GEN_BASE + 0x0C)
24 
25 #define AVS_ADSP_ADSPIC_IPC		BIT(0)
26 #define AVS_ADSP_ADSPIC_CLDMA		BIT(1)
27 #define AVS_ADSP_ADSPIS_IPC		BIT(0)
28 #define AVS_ADSP_ADSPIS_CLDMA		BIT(1)
29 
30 #define AVS_ADSPCS_CRST_MASK(cm)	(cm)
31 #define AVS_ADSPCS_CSTALL_MASK(cm)	((cm) << 8)
32 #define AVS_ADSPCS_SPA_MASK(cm)		((cm) << 16)
33 #define AVS_ADSPCS_CPA_MASK(cm)		((cm) << 24)
34 #define AVS_MAIN_CORE_MASK		BIT(0)
35 
36 #define AVS_ADSP_HIPCCTL_BUSY		BIT(0)
37 #define AVS_ADSP_HIPCCTL_DONE		BIT(1)
38 
39 /* SKL Intel HD Audio Inter-Processor Communication Registers */
40 #define SKL_ADSP_IPC_BASE		0x40
41 #define SKL_ADSP_REG_HIPCT		(SKL_ADSP_IPC_BASE + 0x00)
42 #define SKL_ADSP_REG_HIPCTE		(SKL_ADSP_IPC_BASE + 0x04)
43 #define SKL_ADSP_REG_HIPCI		(SKL_ADSP_IPC_BASE + 0x08)
44 #define SKL_ADSP_REG_HIPCIE		(SKL_ADSP_IPC_BASE + 0x0C)
45 #define SKL_ADSP_REG_HIPCCTL		(SKL_ADSP_IPC_BASE + 0x10)
46 
47 #define SKL_ADSP_HIPCI_BUSY		BIT(31)
48 #define SKL_ADSP_HIPCIE_DONE		BIT(30)
49 #define SKL_ADSP_HIPCT_BUSY		BIT(31)
50 
51 /* Intel HD Audio SRAM windows base addresses */
52 #define SKL_ADSP_SRAM_BASE_OFFSET	0x8000
53 #define SKL_ADSP_SRAM_WINDOW_SIZE	0x2000
54 #define APL_ADSP_SRAM_BASE_OFFSET	0x80000
55 #define APL_ADSP_SRAM_WINDOW_SIZE	0x20000
56 
57 /* Constants used when accessing SRAM, space shared with firmware */
58 #define AVS_FW_REG_BASE(adev)		((adev)->spec->sram_base_offset)
59 #define AVS_FW_REG_STATUS(adev)		(AVS_FW_REG_BASE(adev) + 0x0)
60 #define AVS_FW_REG_ERROR_CODE(adev)	(AVS_FW_REG_BASE(adev) + 0x4)
61 
62 #define AVS_WINDOW_CHUNK_SIZE		PAGE_SIZE
63 #define AVS_FW_REGS_SIZE		AVS_WINDOW_CHUNK_SIZE
64 #define AVS_FW_REGS_WINDOW		0
65 /* DSP -> HOST communication window */
66 #define AVS_UPLINK_WINDOW		AVS_FW_REGS_WINDOW
67 /* HOST -> DSP communication window */
68 #define AVS_DOWNLINK_WINDOW		1
69 #define AVS_DEBUG_WINDOW		2
70 
71 /* registry I/O helpers */
72 #define avs_sram_offset(adev, window_idx) \
73 	((adev)->spec->sram_base_offset + \
74 	 (adev)->spec->sram_window_size * (window_idx))
75 
76 #define avs_sram_addr(adev, window_idx) \
77 	((adev)->dsp_ba + avs_sram_offset(adev, window_idx))
78 
79 #define avs_uplink_addr(adev) \
80 	(avs_sram_addr(adev, AVS_UPLINK_WINDOW) + AVS_FW_REGS_SIZE)
81 #define avs_downlink_addr(adev) \
82 	avs_sram_addr(adev, AVS_DOWNLINK_WINDOW)
83 
84 #endif /* __SOUND_SOC_INTEL_AVS_REGS_H */
85