xref: /openbmc/u-boot/include/mpc8xx_irq.h (revision 156feb90)
1 #ifndef _MPC8XX_IRQ_H
2 #define _MPC8XX_IRQ_H
3 
4 /* The MPC8xx cores have 16 possible interrupts.  There are eight
5  * possible level sensitive interrupts assigned and generated internally
6  * from such devices as CPM, PCMCIA, RTC, PIT, TimeBase and Decrementer.
7  * There are eight external interrupts (IRQs) that can be configured
8  * as either level or edge sensitive.
9  *
10  * On some implementations, there is also the possibility of an 8259
11  * through the PCI and PCI-ISA bridges.
12  *
13  * We don't support the 8259 (yet).
14  */
15 #define NR_SIU_INTS	16
16 #define	NR_8259_INTS	0
17 
18 #define NR_IRQS	(NR_SIU_INTS + NR_8259_INTS)
19 
20 /* These values must be zero-based and map 1:1 with the SIU configuration.
21  * They are used throughout the 8xx I/O subsystem to generate
22  * interrupt masks, flags, and other control patterns.  This is why the
23  * current kernel assumption of the 8259 as the base controller is such
24  * a pain in the butt.
25  */
26 #define	SIU_IRQ0	(0)	/* Highest priority */
27 #define	SIU_LEVEL0	(1)
28 #define	SIU_IRQ1	(2)
29 #define	SIU_LEVEL1	(3)
30 #define	SIU_IRQ2	(4)
31 #define	SIU_LEVEL2	(5)
32 #define	SIU_IRQ3	(6)
33 #define	SIU_LEVEL3	(7)
34 #define	SIU_IRQ4	(8)
35 #define	SIU_LEVEL4	(9)
36 #define	SIU_IRQ5	(10)
37 #define	SIU_LEVEL5	(11)
38 #define	SIU_IRQ6	(12)
39 #define	SIU_LEVEL6	(13)
40 #define	SIU_IRQ7	(14)
41 #define	SIU_LEVEL7	(15)
42 
43 /* The internal interrupts we can configure as we see fit.
44  * My personal preference is CPM at level 2, which puts it above the
45  * MBX PCI/ISA/IDE interrupts.
46  */
47 
48 #ifdef CONFIG_SYS_CPM_INTERRUPT
49 # define CPM_INTERRUPT		CONFIG_SYS_CPM_INTERRUPT
50 #else
51 # define CPM_INTERRUPT		SIU_LEVEL2
52 #endif
53 
54 /* Some internal interrupt registers use an 8-bit mask for the interrupt
55  * level instead of a number.
56  */
57 #define	mk_int_int_mask(IL) (1 << (7 - (IL/2)))
58 
59 #endif /* _MPC8XX_IRQ_H */
60