1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2015, Freescale Semiconductor, Inc.
4  */
5 
6 #ifndef __ARCH_ARM_MACH_S32V234_SIUL_H__
7 #define __ARCH_ARM_MACH_S32V234_SIUL_H__
8 
9 #include "ddr.h"
10 
11 #define SIUL2_MIDR1				(SIUL2_BASE_ADDR + 0x00000004)
12 #define SIUL2_MIDR2				(SIUL2_BASE_ADDR + 0x00000008)
13 #define SIUL2_DISR0				(SIUL2_BASE_ADDR + 0x00000010)
14 #define SIUL2_DIRER0				(SIUL2_BASE_ADDR + 0x00000018)
15 #define SIUL2_DIRSR0				(SIUL2_BASE_ADDR + 0x00000020)
16 #define SIUL2_IREER0				(SIUL2_BASE_ADDR + 0x00000028)
17 #define SIUL2_IFEER0				(SIUL2_BASE_ADDR + 0x00000030)
18 #define SIUL2_IFER0				(SIUL2_BASE_ADDR + 0x00000038)
19 
20 #define SIUL2_IFMCR_BASE			(SIUL2_BASE_ADDR + 0x00000040)
21 #define SIUL2_IFMCRn(i)				(SIUL2_IFMCR_BASE + 4 * (i))
22 
23 #define SIUL2_IFCPR				(SIUL2_BASE_ADDR + 0x000000C0)
24 
25 /* SIUL2_MSCR specifications as stated in Reference Manual:
26  * 0 - 359 Output Multiplexed Signal Configuration Registers
27  * 512- 1023 Input Multiplexed Signal Configuration Registers */
28 #define SIUL2_MSCR_BASE				(SIUL2_BASE_ADDR + 0x00000240)
29 #define SIUL2_MSCRn(i)				(SIUL2_MSCR_BASE + 4 * (i))
30 
31 #define SIUL2_IMCR_BASE				(SIUL2_BASE_ADDR + 0x00000A40)
32 #define SIUL2_IMCRn(i)				(SIUL2_IMCR_BASE +  4 * (i))
33 
34 #define SIUL2_GPDO_BASE				(SIUL2_BASE_ADDR + 0x00001300)
35 #define SIUL2_GPDOn(i)				(SIUL2_GPDO_BASE + 4 * (i))
36 
37 #define SIUL2_GPDI_BASE				(SIUL2_BASE_ADDR + 0x00001500)
38 #define SIUL2_GPDIn(i)				(SIUL2_GPDI_BASE + 4 * (i))
39 
40 #define SIUL2_PGPDO_BASE			(SIUL2_BASE_ADDR + 0x00001700)
41 #define SIUL2_PGPDOn(i)				(SIUL2_PGPDO_BASE +  2 * (i))
42 
43 #define SIUL2_PGPDI_BASE			(SIUL2_BASE_ADDR + 0x00001740)
44 #define SIUL2_PGPDIn(i)				(SIUL2_PGPDI_BASE + 2 * (i))
45 
46 #define SIUL2_MPGPDO_BASE			(SIUL2_BASE_ADDR + 0x00001780)
47 #define SIUL2_MPGPDOn(i)			(SIUL2_MPGPDO_BASE + 4 * (i))
48 
49 /* SIUL2_MSCR masks */
50 #define SIUL2_MSCR_DDR_DO_TRIM(v)	((v) & 0xC0000000)
51 #define SIUL2_MSCR_DDR_DO_TRIM_MIN	(0 << 30)
52 #define SIUL2_MSCR_DDR_DO_TRIM_50PS	(1 << 30)
53 #define SIUL2_MSCR_DDR_DO_TRIM_100PS	(2 << 30)
54 #define SIUL2_MSCR_DDR_DO_TRIM_150PS	(3 << 30)
55 
56 #define SIUL2_MSCR_DDR_INPUT(v)		((v) & 0x20000000)
57 #define SIUL2_MSCR_DDR_INPUT_CMOS	(0 << 29)
58 #define SIUL2_MSCR_DDR_INPUT_DIFF_DDR	(1 << 29)
59 
60 #define SIUL2_MSCR_DDR_SEL(v)		((v) & 0x18000000)
61 #define SIUL2_MSCR_DDR_SEL_DDR3		(0 << 27)
62 #define SIUL2_MSCR_DDR_SEL_LPDDR2	(2 << 27)
63 
64 #define SIUL2_MSCR_DDR_ODT(v)		((v) & 0x07000000)
65 #define SIUL2_MSCR_DDR_ODT_120ohm	(1 << 24)
66 #define SIUL2_MSCR_DDR_ODT_60ohm	(2 << 24)
67 #define SIUL2_MSCR_DDR_ODT_40ohm	(3 << 24)
68 #define SIUL2_MSCR_DDR_ODT_30ohm	(4 << 24)
69 #define SIUL2_MSCR_DDR_ODT_24ohm	(5 << 24)
70 #define SIUL2_MSCR_DDR_ODT_20ohm	(6 << 24)
71 #define SIUL2_MSCR_DDR_ODT_17ohm	(7 << 24)
72 
73 #define SIUL2_MSCR_DCYCLE_TRIM(v)	((v) & 0x00C00000)
74 #define SIUL2_MSCR_DCYCLE_TRIM_NONE	(0 << 22)
75 #define SIUL2_MSCR_DCYCLE_TRIM_LEFT	(1 << 22)
76 #define SIUL2_MSCR_DCYCLE_TRIM_RIGHT	(2 << 22)
77 
78 #define SIUL2_MSCR_OBE(v)		((v) & 0x00200000)
79 #define SIUL2_MSCR_OBE_EN		(1 << 21)
80 
81 #define SIUL2_MSCR_ODE(v)		((v) & 0x00100000)
82 #define SIUL2_MSCR_ODE_EN		(1 << 20)
83 
84 #define SIUL2_MSCR_IBE(v)		((v) & 0x00010000)
85 #define SIUL2_MSCR_IBE_EN		(1 << 19)
86 
87 #define SIUL2_MSCR_HYS(v)		((v) & 0x00400000)
88 #define SIUL2_MSCR_HYS_EN		(1 << 18)
89 
90 #define SIUL2_MSCR_INV(v)		((v) & 0x00020000)
91 #define SIUL2_MSCR_INV_EN		(1 << 17)
92 
93 #define SIUL2_MSCR_PKE(v)		((v) & 0x00010000)
94 #define SIUL2_MSCR_PKE_EN		(1 << 16)
95 
96 #define SIUL2_MSCR_SRE(v)		((v) & 0x0000C000)
97 #define SIUL2_MSCR_SRE_SPEED_LOW_50	(0 << 14)
98 #define SIUL2_MSCR_SRE_SPEED_LOW_100	(1 << 14)
99 #define SIUL2_MSCR_SRE_SPEED_HIGH_100	(2 << 14)
100 #define SIUL2_MSCR_SRE_SPEED_HIGH_200	(3 << 14)
101 
102 #define SIUL2_MSCR_PUE(v)		((v) & 0x00002000)
103 #define SIUL2_MSCR_PUE_EN		(1 << 13)
104 
105 #define SIUL2_MSCR_PUS(v)		((v) & 0x00001800)
106 #define SIUL2_MSCR_PUS_100K_DOWN	(0 << 11)
107 #define SIUL2_MSCR_PUS_50K_DOWN		(1 << 11)
108 #define SIUL2_MSCR_PUS_100K_UP		(2 << 11)
109 #define SIUL2_MSCR_PUS_33K_UP		(3 << 11)
110 
111 #define SIUL2_MSCR_DSE(v)		((v) & 0x00000700)
112 #define SIUL2_MSCR_DSE_240ohm		(1 << 8)
113 #define SIUL2_MSCR_DSE_120ohm		(2 << 8)
114 #define SIUL2_MSCR_DSE_80ohm		(3 << 8)
115 #define SIUL2_MSCR_DSE_60ohm		(4 << 8)
116 #define SIUL2_MSCR_DSE_48ohm		(5 << 8)
117 #define SIUL2_MSCR_DSE_40ohm		(6 << 8)
118 #define SIUL2_MSCR_DSE_34ohm		(7 << 8)
119 
120 #define SIUL2_MSCR_CRPOINT_TRIM(v)	((v) & 0x000000C0)
121 #define SIUL2_MSCR_CRPOINT_TRIM_1	(1 << 6)
122 
123 #define SIUL2_MSCR_SMC(v)		((v) & 0x00000020)
124 #define SIUL2_MSCR_MUX_MODE(v)		((v) & 0x0000000f)
125 #define SIUL2_MSCR_MUX_MODE_ALT1	(0x1)
126 #define SIUL2_MSCR_MUX_MODE_ALT2	(0x2)
127 #define SIUL2_MSCR_MUX_MODE_ALT3	(0x3)
128 
129 /* UART settings */
130 #define SIUL2_UART0_TXD_PAD	12
131 #define SIUL2_UART_TXD		(SIUL2_MSCR_OBE_EN | SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_DSE_60ohm |	\
132 				SIUL2_MSCR_SRE_SPEED_LOW_100 | SIUL2_MSCR_MUX_MODE_ALT1)
133 
134 #define SIUL2_UART0_MSCR_RXD_PAD	11
135 #define SIUL2_UART0_IMCR_RXD_PAD	200
136 
137 #define SIUL2_UART_MSCR_RXD	(SIUL2_MSCR_PUE_EN | SIUL2_MSCR_IBE_EN | SIUL2_MSCR_DCYCLE_TRIM_RIGHT)
138 #define SIUL2_UART_IMCR_RXD	(SIUL2_MSCR_MUX_MODE_ALT2)
139 
140 /* uSDHC settings */
141 #define SIUL2_USDHC_PAD_CTRL_BASE	(SIUL2_MSCR_SRE_SPEED_HIGH_200 | SIUL2_MSCR_OBE_EN |	\
142 						SIUL2_MSCR_DSE_34ohm | SIUL2_MSCR_PKE_EN | SIUL2_MSCR_IBE_EN |		\
143 						SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_PUE_EN )
144 #define SIUL2_USDHC_PAD_CTRL_CMD	(SIUL2_USDHC_PAD_CTRL_BASE | SIUL2_MSCR_MUX_MODE_ALT1)
145 #define SIUL2_USDHC_PAD_CTRL_CLK	(SIUL2_USDHC_PAD_CTRL_BASE | SIUL2_MSCR_MUX_MODE_ALT2)
146 #define SIUL2_USDHC_PAD_CTRL_DAT0_3	(SIUL2_USDHC_PAD_CTRL_BASE | SIUL2_MSCR_MUX_MODE_ALT2)
147 #define SIUL2_USDHC_PAD_CTRL_DAT4_7	(SIUL2_USDHC_PAD_CTRL_BASE | SIUL2_MSCR_MUX_MODE_ALT3)
148 
149 #endif /*__ARCH_ARM_MACH_S32V234_SIUL_H__ */
150