1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
4 */
5
6 #include <common.h>
7 #include <dm.h>
8 #include <errno.h>
9 #include <pci.h>
10 #include <smsc_sio1007.h>
11 #include <asm/ibmpc.h>
12 #include <asm/lpc_common.h>
13 #include <asm/pci.h>
14 #include <asm/arch/pch.h>
15
16 #define SIO1007_RUNTIME_IOPORT 0x180
17
board_early_init_f(void)18 int board_early_init_f(void)
19 {
20 struct udevice *pch;
21 int ret;
22
23 ret = uclass_first_device(UCLASS_PCH, &pch);
24 if (ret)
25 return ret;
26 if (!pch)
27 return -ENODEV;
28
29 /* Initialize LPC interface to turn on superio chipset decode range */
30 dm_pci_write_config16(pch, LPC_IO_DEC, COMA_DEC_RANGE | COMB_DEC_RANGE);
31 dm_pci_write_config16(pch, LPC_EN, KBC_LPC_EN | COMA_LPC_EN);
32 dm_pci_write_config32(pch, LPC_GEN1_DEC, GEN_DEC_RANGE_256B |
33 (SIO1007_IOPORT3 & 0xff00) | GEN_DEC_RANGE_EN);
34 dm_pci_write_config32(pch, LPC_GEN2_DEC, GEN_DEC_RANGE_16B |
35 SIO1007_RUNTIME_IOPORT | GEN_DEC_RANGE_EN);
36
37 /* Enable legacy serial port at 0x3f8 */
38 sio1007_enable_serial(SIO1007_IOPORT3, 0, UART0_BASE, UART0_IRQ);
39
40 /* Enable SIO1007 runtime I/O port at 0x180 */
41 sio1007_enable_runtime(SIO1007_IOPORT3, SIO1007_RUNTIME_IOPORT);
42
43 /*
44 * On Cougar Canyon 2 board, the RS232 transiver connected to serial
45 * port 0 (0x3f8) is controlled by a GPIO pin (GPIO10) on the SIO1007.
46 * Set the pin value to 1 to enable the RS232 transiver.
47 */
48 sio1007_gpio_config(SIO1007_IOPORT3, 0, GPIO_DIR_OUTPUT,
49 GPIO_POL_NO_INVERT, GPIO_TYPE_PUSH_PULL);
50 sio1007_gpio_set_value(SIO1007_RUNTIME_IOPORT, 0, 1);
51
52 return 0;
53 }
54