xref: /openbmc/linux/arch/sh/kernel/cpu/sh2a/setup-mxg.c (revision c95baf12f5077419db01313ab61c2aac007d40cd)
1  // SPDX-License-Identifier: GPL-2.0
2  /*
3   * Renesas MX-G (R8A03022BG) Setup
4   *
5   *  Copyright (C) 2008, 2009  Paul Mundt
6   */
7  #include <linux/platform_device.h>
8  #include <linux/init.h>
9  #include <linux/serial.h>
10  #include <linux/serial_sci.h>
11  #include <linux/sh_timer.h>
12  #include <asm/platform_early.h>
13  
14  enum {
15  	UNUSED = 0,
16  
17  	/* interrupt sources */
18  	IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
19  	IRQ8, IRQ9, IRQ10, IRQ11, IRQ12, IRQ13, IRQ14, IRQ15,
20  
21  	PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
22  	SINT8, SINT7, SINT6, SINT5, SINT4, SINT3, SINT2, SINT1,
23  
24  	SCIF0, SCIF1,
25  
26  	MTU2_GROUP1, MTU2_GROUP2, MTU2_GROUP3, MTU2_GROUP4, MTU2_GROUP5,
27  	MTU2_TGI3B, MTU2_TGI3C,
28  
29  	/* interrupt groups */
30  	PINT,
31  };
32  
33  static struct intc_vect vectors[] __initdata = {
34  	INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
35  	INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
36  	INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
37  	INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
38  	INTC_IRQ(IRQ8, 72), INTC_IRQ(IRQ9, 73),
39  	INTC_IRQ(IRQ10, 74), INTC_IRQ(IRQ11, 75),
40  	INTC_IRQ(IRQ12, 76), INTC_IRQ(IRQ13, 77),
41  	INTC_IRQ(IRQ14, 78), INTC_IRQ(IRQ15, 79),
42  
43  	INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
44  	INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
45  	INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
46  	INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
47  
48  	INTC_IRQ(SINT8, 94), INTC_IRQ(SINT7, 95),
49  	INTC_IRQ(SINT6, 96), INTC_IRQ(SINT5, 97),
50  	INTC_IRQ(SINT4, 98), INTC_IRQ(SINT3, 99),
51  	INTC_IRQ(SINT2, 100), INTC_IRQ(SINT1, 101),
52  
53  	INTC_IRQ(SCIF0, 220), INTC_IRQ(SCIF0, 221),
54  	INTC_IRQ(SCIF0, 222), INTC_IRQ(SCIF0, 223),
55  	INTC_IRQ(SCIF1, 224), INTC_IRQ(SCIF1, 225),
56  	INTC_IRQ(SCIF1, 226), INTC_IRQ(SCIF1, 227),
57  
58  	INTC_IRQ(MTU2_GROUP1, 228), INTC_IRQ(MTU2_GROUP1, 229),
59  	INTC_IRQ(MTU2_GROUP1, 230), INTC_IRQ(MTU2_GROUP1, 231),
60  	INTC_IRQ(MTU2_GROUP1, 232), INTC_IRQ(MTU2_GROUP1, 233),
61  
62  	INTC_IRQ(MTU2_GROUP2, 234), INTC_IRQ(MTU2_GROUP2, 235),
63  	INTC_IRQ(MTU2_GROUP2, 236), INTC_IRQ(MTU2_GROUP2, 237),
64  	INTC_IRQ(MTU2_GROUP2, 238), INTC_IRQ(MTU2_GROUP2, 239),
65  
66  	INTC_IRQ(MTU2_GROUP3, 240), INTC_IRQ(MTU2_GROUP3, 241),
67  	INTC_IRQ(MTU2_GROUP3, 242), INTC_IRQ(MTU2_GROUP3, 243),
68  
69  	INTC_IRQ(MTU2_TGI3B, 244),
70  	INTC_IRQ(MTU2_TGI3C, 245),
71  
72  	INTC_IRQ(MTU2_GROUP4, 246), INTC_IRQ(MTU2_GROUP4, 247),
73  	INTC_IRQ(MTU2_GROUP4, 248), INTC_IRQ(MTU2_GROUP4, 249),
74  	INTC_IRQ(MTU2_GROUP4, 250), INTC_IRQ(MTU2_GROUP4, 251),
75  
76  	INTC_IRQ(MTU2_GROUP5, 252), INTC_IRQ(MTU2_GROUP5, 253),
77  	INTC_IRQ(MTU2_GROUP5, 254), INTC_IRQ(MTU2_GROUP5, 255),
78  };
79  
80  static struct intc_group groups[] __initdata = {
81  	INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
82  		   PINT4, PINT5, PINT6, PINT7),
83  };
84  
85  static struct intc_prio_reg prio_registers[] __initdata = {
86  	{ 0xfffd9418, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
87  	{ 0xfffd941a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
88  	{ 0xfffd941c, 0, 16, 4, /* IPR03 */ { IRQ8, IRQ9, IRQ10, IRQ11 } },
89  	{ 0xfffd941e, 0, 16, 4, /* IPR04 */ { IRQ12, IRQ13, IRQ14, IRQ15 } },
90  	{ 0xfffd9420, 0, 16, 4, /* IPR05 */ { PINT, 0, 0, 0 } },
91  	{ 0xfffd9800, 0, 16, 4, /* IPR06 */ { } },
92  	{ 0xfffd9802, 0, 16, 4, /* IPR07 */ { } },
93  	{ 0xfffd9804, 0, 16, 4, /* IPR08 */ { } },
94  	{ 0xfffd9806, 0, 16, 4, /* IPR09 */ { } },
95  	{ 0xfffd9808, 0, 16, 4, /* IPR10 */ { } },
96  	{ 0xfffd980a, 0, 16, 4, /* IPR11 */ { } },
97  	{ 0xfffd980c, 0, 16, 4, /* IPR12 */ { } },
98  	{ 0xfffd980e, 0, 16, 4, /* IPR13 */ { } },
99  	{ 0xfffd9810, 0, 16, 4, /* IPR14 */ { 0, 0, 0, SCIF0 } },
100  	{ 0xfffd9812, 0, 16, 4, /* IPR15 */
101  		{ SCIF1, MTU2_GROUP1, MTU2_GROUP2, MTU2_GROUP3 } },
102  	{ 0xfffd9814, 0, 16, 4, /* IPR16 */
103  		{ MTU2_TGI3B, MTU2_TGI3C, MTU2_GROUP4, MTU2_GROUP5 } },
104  };
105  
106  static struct intc_mask_reg mask_registers[] __initdata = {
107  	{ 0xfffd9408, 0, 16, /* PINTER */
108  	  { 0, 0, 0, 0, 0, 0, 0, 0,
109  	    PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
110  };
111  
112  static DECLARE_INTC_DESC(intc_desc, "mxg", vectors, groups,
113  			 mask_registers, prio_registers, NULL);
114  
115  static struct resource mtu2_resources[] = {
116  	DEFINE_RES_MEM(0xff801000, 0x400),
117  	DEFINE_RES_IRQ_NAMED(228, "tgi0a"),
118  	DEFINE_RES_IRQ_NAMED(234, "tgi1a"),
119  	DEFINE_RES_IRQ_NAMED(240, "tgi2a"),
120  };
121  
122  static struct platform_device mtu2_device = {
123  	.name		= "sh-mtu2",
124  	.id		= -1,
125  	.resource	= mtu2_resources,
126  	.num_resources	= ARRAY_SIZE(mtu2_resources),
127  };
128  
129  static struct plat_sci_port scif0_platform_data = {
130  	.scscr		= SCSCR_REIE,
131  	.type		= PORT_SCIF,
132  };
133  
134  static struct resource scif0_resources[] = {
135  	DEFINE_RES_MEM(0xff804000, 0x100),
136  	DEFINE_RES_IRQ(220),
137  };
138  
139  static struct platform_device scif0_device = {
140  	.name		= "sh-sci",
141  	.id		= 0,
142  	.resource	= scif0_resources,
143  	.num_resources	= ARRAY_SIZE(scif0_resources),
144  	.dev		= {
145  		.platform_data	= &scif0_platform_data,
146  	},
147  };
148  
149  static struct platform_device *mxg_devices[] __initdata = {
150  	&scif0_device,
151  	&mtu2_device,
152  };
153  
mxg_devices_setup(void)154  static int __init mxg_devices_setup(void)
155  {
156  	return platform_add_devices(mxg_devices,
157  				    ARRAY_SIZE(mxg_devices));
158  }
159  arch_initcall(mxg_devices_setup);
160  
plat_irq_setup(void)161  void __init plat_irq_setup(void)
162  {
163  	register_intc_controller(&intc_desc);
164  }
165  
166  static struct platform_device *mxg_early_devices[] __initdata = {
167  	&scif0_device,
168  	&mtu2_device,
169  };
170  
plat_early_device_setup(void)171  void __init plat_early_device_setup(void)
172  {
173  	sh_early_platform_add_devices(mxg_early_devices,
174  				   ARRAY_SIZE(mxg_early_devices));
175  }
176