xref: /openbmc/linux/sound/soc/codecs/ab8500-codec.c (revision bb426d37)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) ST-Ericsson SA 2012
4  *
5  * Author: Ola Lilja <ola.o.lilja@stericsson.com>,
6  *         Kristoffer Karlsson <kristoffer.karlsson@stericsson.com>,
7  *         Roger Nilsson <roger.xr.nilsson@stericsson.com>,
8  *         for ST-Ericsson.
9  *
10  *         Based on the early work done by:
11  *         Mikko J. Lehto <mikko.lehto@symbio.com>,
12  *         Mikko Sarmanne <mikko.sarmanne@symbio.com>,
13  *         Jarmo K. Kuronen <jarmo.kuronen@symbio.com>,
14  *         for ST-Ericsson.
15  */
16 
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/device.h>
20 #include <linux/slab.h>
21 #include <linux/moduleparam.h>
22 #include <linux/init.h>
23 #include <linux/delay.h>
24 #include <linux/pm.h>
25 #include <linux/platform_device.h>
26 #include <linux/mutex.h>
27 #include <linux/mfd/abx500/ab8500.h>
28 #include <linux/mfd/abx500.h>
29 #include <linux/mfd/abx500/ab8500-sysctrl.h>
30 #include <linux/mfd/abx500/ab8500-codec.h>
31 #include <linux/regulator/consumer.h>
32 #include <linux/of.h>
33 
34 #include <sound/core.h>
35 #include <sound/pcm.h>
36 #include <sound/pcm_params.h>
37 #include <sound/initval.h>
38 #include <sound/soc.h>
39 #include <sound/soc-dapm.h>
40 #include <sound/tlv.h>
41 
42 #include "ab8500-codec.h"
43 
44 /* Macrocell value definitions */
45 #define CLK_32K_OUT2_DISABLE			0x01
46 #define INACTIVE_RESET_AUDIO			0x02
47 #define ENABLE_AUDIO_CLK_TO_AUDIO_BLK		0x10
48 #define ENABLE_VINTCORE12_SUPPLY		0x04
49 #define GPIO27_DIR_OUTPUT			0x04
50 #define GPIO29_DIR_OUTPUT			0x10
51 #define GPIO31_DIR_OUTPUT			0x40
52 
53 /* Macrocell register definitions */
54 #define AB8500_GPIO_DIR4_REG			0x13 /* Bank AB8500_MISC */
55 
56 /* Nr of FIR/IIR-coeff banks in ANC-block */
57 #define AB8500_NR_OF_ANC_COEFF_BANKS		2
58 
59 /* Minimum duration to keep ANC IIR Init bit high or
60 low before proceeding with the configuration sequence */
61 #define AB8500_ANC_SM_DELAY			2000
62 
63 #define AB8500_FILTER_CONTROL(xname, xcount, xmin, xmax) \
64 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
65 	.info = filter_control_info, \
66 	.get = filter_control_get, .put = filter_control_put, \
67 	.private_value = (unsigned long)&(struct filter_control) \
68 		{.count = xcount, .min = xmin, .max = xmax} }
69 
70 struct filter_control {
71 	long min, max;
72 	unsigned int count;
73 	long value[128];
74 };
75 
76 /* Sidetone states */
77 static const char * const enum_sid_state[] = {
78 	"Unconfigured",
79 	"Apply FIR",
80 	"FIR is configured",
81 };
82 enum sid_state {
83 	SID_UNCONFIGURED = 0,
84 	SID_APPLY_FIR = 1,
85 	SID_FIR_CONFIGURED = 2,
86 };
87 
88 static const char * const enum_anc_state[] = {
89 	"Unconfigured",
90 	"Apply FIR and IIR",
91 	"FIR and IIR are configured",
92 	"Apply FIR",
93 	"FIR is configured",
94 	"Apply IIR",
95 	"IIR is configured"
96 };
97 enum anc_state {
98 	ANC_UNCONFIGURED = 0,
99 	ANC_APPLY_FIR_IIR = 1,
100 	ANC_FIR_IIR_CONFIGURED = 2,
101 	ANC_APPLY_FIR = 3,
102 	ANC_FIR_CONFIGURED = 4,
103 	ANC_APPLY_IIR = 5,
104 	ANC_IIR_CONFIGURED = 6
105 };
106 
107 /* Analog microphones */
108 enum amic_idx {
109 	AMIC_IDX_1A,
110 	AMIC_IDX_1B,
111 	AMIC_IDX_2
112 };
113 
114 /* Private data for AB8500 device-driver */
115 struct ab8500_codec_drvdata {
116 	struct regmap *regmap;
117 	struct mutex ctrl_lock;
118 
119 	/* Sidetone */
120 	long *sid_fir_values;
121 	enum sid_state sid_status;
122 
123 	/* ANC */
124 	long *anc_fir_values;
125 	long *anc_iir_values;
126 	enum anc_state anc_status;
127 };
128 
amic_micbias_str(enum amic_micbias micbias)129 static inline const char *amic_micbias_str(enum amic_micbias micbias)
130 {
131 	switch (micbias) {
132 	case AMIC_MICBIAS_VAMIC1:
133 		return "VAMIC1";
134 	case AMIC_MICBIAS_VAMIC2:
135 		return "VAMIC2";
136 	default:
137 		return "Unknown";
138 	}
139 }
140 
amic_type_str(enum amic_type type)141 static inline const char *amic_type_str(enum amic_type type)
142 {
143 	switch (type) {
144 	case AMIC_TYPE_DIFFERENTIAL:
145 		return "DIFFERENTIAL";
146 	case AMIC_TYPE_SINGLE_ENDED:
147 		return "SINGLE ENDED";
148 	default:
149 		return "Unknown";
150 	}
151 }
152 
153 /*
154  * Read'n'write functions
155  */
156 
157 /* Read a register from the audio-bank of AB8500 */
ab8500_codec_read_reg(void * context,unsigned int reg,unsigned int * value)158 static int ab8500_codec_read_reg(void *context, unsigned int reg,
159 				 unsigned int *value)
160 {
161 	struct device *dev = context;
162 	int status;
163 
164 	u8 value8;
165 	status = abx500_get_register_interruptible(dev, AB8500_AUDIO,
166 						   reg, &value8);
167 	*value = (unsigned int)value8;
168 
169 	return status;
170 }
171 
172 /* Write to a register in the audio-bank of AB8500 */
ab8500_codec_write_reg(void * context,unsigned int reg,unsigned int value)173 static int ab8500_codec_write_reg(void *context, unsigned int reg,
174 				  unsigned int value)
175 {
176 	struct device *dev = context;
177 
178 	return abx500_set_register_interruptible(dev, AB8500_AUDIO,
179 						 reg, value);
180 }
181 
182 static const struct regmap_config ab8500_codec_regmap = {
183 	.reg_read = ab8500_codec_read_reg,
184 	.reg_write = ab8500_codec_write_reg,
185 };
186 
187 /*
188  * Controls - DAPM
189  */
190 
191 /* Earpiece */
192 
193 /* Earpiece source selector */
194 static const char * const enum_ear_lineout_source[] = {"Headset Left",
195 						"Speaker Left"};
196 static SOC_ENUM_SINGLE_DECL(dapm_enum_ear_lineout_source, AB8500_DMICFILTCONF,
197 			AB8500_DMICFILTCONF_DA3TOEAR, enum_ear_lineout_source);
198 static const struct snd_kcontrol_new dapm_ear_lineout_source =
199 	SOC_DAPM_ENUM("Earpiece or LineOut Mono Source",
200 		dapm_enum_ear_lineout_source);
201 
202 /* LineOut */
203 
204 /* LineOut source selector */
205 static const char * const enum_lineout_source[] = {"Mono Path", "Stereo Path"};
206 static SOC_ENUM_DOUBLE_DECL(dapm_enum_lineout_source, AB8500_ANACONF5,
207 			AB8500_ANACONF5_HSLDACTOLOL,
208 			AB8500_ANACONF5_HSRDACTOLOR, enum_lineout_source);
209 static const struct snd_kcontrol_new dapm_lineout_source[] = {
210 	SOC_DAPM_ENUM("LineOut Source", dapm_enum_lineout_source),
211 };
212 
213 /* Handsfree */
214 
215 /* Speaker Left - ANC selector */
216 static const char * const enum_HFx_sel[] = {"Audio Path", "ANC"};
217 static SOC_ENUM_SINGLE_DECL(dapm_enum_HFl_sel, AB8500_DIGMULTCONF2,
218 			AB8500_DIGMULTCONF2_HFLSEL, enum_HFx_sel);
219 static const struct snd_kcontrol_new dapm_HFl_select[] = {
220 	SOC_DAPM_ENUM("Speaker Left Source", dapm_enum_HFl_sel),
221 };
222 
223 /* Speaker Right - ANC selector */
224 static SOC_ENUM_SINGLE_DECL(dapm_enum_HFr_sel, AB8500_DIGMULTCONF2,
225 			AB8500_DIGMULTCONF2_HFRSEL, enum_HFx_sel);
226 static const struct snd_kcontrol_new dapm_HFr_select[] = {
227 	SOC_DAPM_ENUM("Speaker Right Source", dapm_enum_HFr_sel),
228 };
229 
230 /* Mic 1 */
231 
232 /* Mic 1 - Mic 1a or 1b selector */
233 static const char * const enum_mic1ab_sel[] = {"Mic 1b", "Mic 1a"};
234 static SOC_ENUM_SINGLE_DECL(dapm_enum_mic1ab_sel, AB8500_ANACONF3,
235 			AB8500_ANACONF3_MIC1SEL, enum_mic1ab_sel);
236 static const struct snd_kcontrol_new dapm_mic1ab_mux[] = {
237 	SOC_DAPM_ENUM("Mic 1a or 1b Select", dapm_enum_mic1ab_sel),
238 };
239 
240 /* Mic 1 - AD3 - Mic 1 or DMic 3 selector */
241 static const char * const enum_ad3_sel[] = {"Mic 1", "DMic 3"};
242 static SOC_ENUM_SINGLE_DECL(dapm_enum_ad3_sel, AB8500_DIGMULTCONF1,
243 			AB8500_DIGMULTCONF1_AD3SEL, enum_ad3_sel);
244 static const struct snd_kcontrol_new dapm_ad3_select[] = {
245 	SOC_DAPM_ENUM("AD3 Source Select", dapm_enum_ad3_sel),
246 };
247 
248 /* Mic 1 - AD6 - Mic 1 or DMic 6 selector */
249 static const char * const enum_ad6_sel[] = {"Mic 1", "DMic 6"};
250 static SOC_ENUM_SINGLE_DECL(dapm_enum_ad6_sel, AB8500_DIGMULTCONF1,
251 			AB8500_DIGMULTCONF1_AD6SEL, enum_ad6_sel);
252 static const struct snd_kcontrol_new dapm_ad6_select[] = {
253 	SOC_DAPM_ENUM("AD6 Source Select", dapm_enum_ad6_sel),
254 };
255 
256 /* Mic 2 */
257 
258 /* Mic 2 - AD5 - Mic 2 or DMic 5 selector */
259 static const char * const enum_ad5_sel[] = {"Mic 2", "DMic 5"};
260 static SOC_ENUM_SINGLE_DECL(dapm_enum_ad5_sel, AB8500_DIGMULTCONF1,
261 			AB8500_DIGMULTCONF1_AD5SEL, enum_ad5_sel);
262 static const struct snd_kcontrol_new dapm_ad5_select[] = {
263 	SOC_DAPM_ENUM("AD5 Source Select", dapm_enum_ad5_sel),
264 };
265 
266 /* LineIn */
267 
268 /* LineIn left - AD1 - LineIn Left or DMic 1 selector */
269 static const char * const enum_ad1_sel[] = {"LineIn Left", "DMic 1"};
270 static SOC_ENUM_SINGLE_DECL(dapm_enum_ad1_sel, AB8500_DIGMULTCONF1,
271 			AB8500_DIGMULTCONF1_AD1SEL, enum_ad1_sel);
272 static const struct snd_kcontrol_new dapm_ad1_select[] = {
273 	SOC_DAPM_ENUM("AD1 Source Select", dapm_enum_ad1_sel),
274 };
275 
276 /* LineIn right - Mic 2 or LineIn Right selector */
277 static const char * const enum_mic2lr_sel[] = {"Mic 2", "LineIn Right"};
278 static SOC_ENUM_SINGLE_DECL(dapm_enum_mic2lr_sel, AB8500_ANACONF3,
279 			AB8500_ANACONF3_LINRSEL, enum_mic2lr_sel);
280 static const struct snd_kcontrol_new dapm_mic2lr_select[] = {
281 	SOC_DAPM_ENUM("Mic 2 or LINR Select", dapm_enum_mic2lr_sel),
282 };
283 
284 /* LineIn right - AD2 - LineIn Right or DMic2 selector */
285 static const char * const enum_ad2_sel[] = {"LineIn Right", "DMic 2"};
286 static SOC_ENUM_SINGLE_DECL(dapm_enum_ad2_sel, AB8500_DIGMULTCONF1,
287 			AB8500_DIGMULTCONF1_AD2SEL, enum_ad2_sel);
288 static const struct snd_kcontrol_new dapm_ad2_select[] = {
289 	SOC_DAPM_ENUM("AD2 Source Select", dapm_enum_ad2_sel),
290 };
291 
292 
293 /* ANC */
294 
295 static const char * const enum_anc_in_sel[] = {"Mic 1 / DMic 6",
296 					"Mic 2 / DMic 5"};
297 static SOC_ENUM_SINGLE_DECL(dapm_enum_anc_in_sel, AB8500_DMICFILTCONF,
298 			AB8500_DMICFILTCONF_ANCINSEL, enum_anc_in_sel);
299 static const struct snd_kcontrol_new dapm_anc_in_select[] = {
300 	SOC_DAPM_ENUM("ANC Source", dapm_enum_anc_in_sel),
301 };
302 
303 /* ANC - Enable/Disable */
304 static const struct snd_kcontrol_new dapm_anc_enable[] = {
305 	SOC_DAPM_SINGLE("Switch", AB8500_ANCCONF1,
306 			AB8500_ANCCONF1_ENANC, 0, 0),
307 };
308 
309 /* ANC to Earpiece - Mute */
310 static const struct snd_kcontrol_new dapm_anc_ear_mute[] = {
311 	SOC_DAPM_SINGLE("Switch", AB8500_DIGMULTCONF1,
312 			AB8500_DIGMULTCONF1_ANCSEL, 1, 0),
313 };
314 
315 
316 
317 /* Sidetone left */
318 
319 /* Sidetone left - Input selector */
320 static const char * const enum_stfir1_in_sel[] = {
321 	"LineIn Left", "LineIn Right", "Mic 1", "Headset Left"
322 };
323 static SOC_ENUM_SINGLE_DECL(dapm_enum_stfir1_in_sel, AB8500_DIGMULTCONF2,
324 			AB8500_DIGMULTCONF2_FIRSID1SEL, enum_stfir1_in_sel);
325 static const struct snd_kcontrol_new dapm_stfir1_in_select[] = {
326 	SOC_DAPM_ENUM("Sidetone Left Source", dapm_enum_stfir1_in_sel),
327 };
328 
329 /* Sidetone right path */
330 
331 /* Sidetone right - Input selector */
332 static const char * const enum_stfir2_in_sel[] = {
333 	"LineIn Right", "Mic 1", "DMic 4", "Headset Right"
334 };
335 static SOC_ENUM_SINGLE_DECL(dapm_enum_stfir2_in_sel, AB8500_DIGMULTCONF2,
336 			AB8500_DIGMULTCONF2_FIRSID2SEL, enum_stfir2_in_sel);
337 static const struct snd_kcontrol_new dapm_stfir2_in_select[] = {
338 	SOC_DAPM_ENUM("Sidetone Right Source", dapm_enum_stfir2_in_sel),
339 };
340 
341 /* Vibra */
342 
343 static const char * const enum_pwm2vibx[] = {"Audio Path", "PWM Generator"};
344 
345 static SOC_ENUM_SINGLE_DECL(dapm_enum_pwm2vib1, AB8500_PWMGENCONF1,
346 			AB8500_PWMGENCONF1_PWMTOVIB1, enum_pwm2vibx);
347 
348 static const struct snd_kcontrol_new dapm_pwm2vib1[] = {
349 	SOC_DAPM_ENUM("Vibra 1 Controller", dapm_enum_pwm2vib1),
350 };
351 
352 static SOC_ENUM_SINGLE_DECL(dapm_enum_pwm2vib2, AB8500_PWMGENCONF1,
353 			AB8500_PWMGENCONF1_PWMTOVIB2, enum_pwm2vibx);
354 
355 static const struct snd_kcontrol_new dapm_pwm2vib2[] = {
356 	SOC_DAPM_ENUM("Vibra 2 Controller", dapm_enum_pwm2vib2),
357 };
358 
359 /*
360  * DAPM-widgets
361  */
362 
363 static const struct snd_soc_dapm_widget ab8500_dapm_widgets[] = {
364 
365 	/* Clocks */
366 	SND_SOC_DAPM_CLOCK_SUPPLY("audioclk"),
367 
368 	/* Regulators */
369 	SND_SOC_DAPM_REGULATOR_SUPPLY("V-AUD", 0, 0),
370 	SND_SOC_DAPM_REGULATOR_SUPPLY("V-AMIC1", 0, 0),
371 	SND_SOC_DAPM_REGULATOR_SUPPLY("V-AMIC2", 0, 0),
372 	SND_SOC_DAPM_REGULATOR_SUPPLY("V-DMIC", 0, 0),
373 
374 	/* Power */
375 	SND_SOC_DAPM_SUPPLY("Audio Power",
376 			AB8500_POWERUP, AB8500_POWERUP_POWERUP, 0,
377 			NULL, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
378 	SND_SOC_DAPM_SUPPLY("Audio Analog Power",
379 			AB8500_POWERUP, AB8500_POWERUP_ENANA, 0,
380 			NULL, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
381 
382 	/* Main supply node */
383 	SND_SOC_DAPM_SUPPLY("Main Supply", SND_SOC_NOPM, 0, 0,
384 			NULL, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
385 
386 	/* DA/AD */
387 
388 	SND_SOC_DAPM_INPUT("ADC Input"),
389 	SND_SOC_DAPM_ADC("ADC", "ab8500_0c", SND_SOC_NOPM, 0, 0),
390 
391 	SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0),
392 	SND_SOC_DAPM_OUTPUT("DAC Output"),
393 
394 	SND_SOC_DAPM_AIF_IN("DA_IN1", NULL, 0, SND_SOC_NOPM, 0, 0),
395 	SND_SOC_DAPM_AIF_IN("DA_IN2", NULL, 0, SND_SOC_NOPM, 0, 0),
396 	SND_SOC_DAPM_AIF_IN("DA_IN3", NULL, 0, SND_SOC_NOPM, 0, 0),
397 	SND_SOC_DAPM_AIF_IN("DA_IN4", NULL, 0, SND_SOC_NOPM, 0, 0),
398 	SND_SOC_DAPM_AIF_IN("DA_IN5", NULL, 0, SND_SOC_NOPM, 0, 0),
399 	SND_SOC_DAPM_AIF_IN("DA_IN6", NULL, 0, SND_SOC_NOPM, 0, 0),
400 	SND_SOC_DAPM_AIF_OUT("AD_OUT1", NULL, 0, SND_SOC_NOPM, 0, 0),
401 	SND_SOC_DAPM_AIF_OUT("AD_OUT2", NULL, 0, SND_SOC_NOPM, 0, 0),
402 	SND_SOC_DAPM_AIF_OUT("AD_OUT3", NULL, 0, SND_SOC_NOPM, 0, 0),
403 	SND_SOC_DAPM_AIF_OUT("AD_OUT4", NULL, 0, SND_SOC_NOPM, 0, 0),
404 	SND_SOC_DAPM_AIF_OUT("AD_OUT57", NULL, 0, SND_SOC_NOPM, 0, 0),
405 	SND_SOC_DAPM_AIF_OUT("AD_OUT68", NULL, 0, SND_SOC_NOPM, 0, 0),
406 
407 	/* Headset path */
408 
409 	SND_SOC_DAPM_SUPPLY("Charge Pump", AB8500_ANACONF5,
410 			AB8500_ANACONF5_ENCPHS, 0, NULL, 0),
411 
412 	SND_SOC_DAPM_DAC("DA1 Enable", "ab8500_0p",
413 			AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA1, 0),
414 	SND_SOC_DAPM_DAC("DA2 Enable", "ab8500_0p",
415 			AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA2, 0),
416 
417 	SND_SOC_DAPM_PGA("HSL Digital Volume", SND_SOC_NOPM, 0, 0,
418 			NULL, 0),
419 	SND_SOC_DAPM_PGA("HSR Digital Volume", SND_SOC_NOPM, 0, 0,
420 			NULL, 0),
421 
422 	SND_SOC_DAPM_DAC("HSL DAC", "ab8500_0p",
423 			AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACHSL, 0),
424 	SND_SOC_DAPM_DAC("HSR DAC", "ab8500_0p",
425 			AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACHSR, 0),
426 	SND_SOC_DAPM_MIXER("HSL DAC Mute", AB8500_MUTECONF,
427 			AB8500_MUTECONF_MUTDACHSL, 1,
428 			NULL, 0),
429 	SND_SOC_DAPM_MIXER("HSR DAC Mute", AB8500_MUTECONF,
430 			AB8500_MUTECONF_MUTDACHSR, 1,
431 			NULL, 0),
432 	SND_SOC_DAPM_DAC("HSL DAC Driver", "ab8500_0p",
433 			AB8500_ANACONF3, AB8500_ANACONF3_ENDRVHSL, 0),
434 	SND_SOC_DAPM_DAC("HSR DAC Driver", "ab8500_0p",
435 			AB8500_ANACONF3, AB8500_ANACONF3_ENDRVHSR, 0),
436 
437 	SND_SOC_DAPM_MIXER("HSL Mute",
438 			AB8500_MUTECONF, AB8500_MUTECONF_MUTHSL, 1,
439 			NULL, 0),
440 	SND_SOC_DAPM_MIXER("HSR Mute",
441 			AB8500_MUTECONF, AB8500_MUTECONF_MUTHSR, 1,
442 			NULL, 0),
443 	SND_SOC_DAPM_MIXER("HSL Enable",
444 			AB8500_ANACONF4, AB8500_ANACONF4_ENHSL, 0,
445 			NULL, 0),
446 	SND_SOC_DAPM_MIXER("HSR Enable",
447 			AB8500_ANACONF4, AB8500_ANACONF4_ENHSR, 0,
448 			NULL, 0),
449 	SND_SOC_DAPM_PGA("HSL Volume",
450 			SND_SOC_NOPM, 0, 0,
451 			NULL, 0),
452 	SND_SOC_DAPM_PGA("HSR Volume",
453 			SND_SOC_NOPM, 0, 0,
454 			NULL, 0),
455 
456 	SND_SOC_DAPM_OUTPUT("Headset Left"),
457 	SND_SOC_DAPM_OUTPUT("Headset Right"),
458 
459 	/* LineOut path */
460 
461 	SND_SOC_DAPM_MUX("LineOut Source",
462 			SND_SOC_NOPM, 0, 0, dapm_lineout_source),
463 
464 	SND_SOC_DAPM_MIXER("LOL Disable HFL",
465 			AB8500_ANACONF4, AB8500_ANACONF4_ENHFL, 1,
466 			NULL, 0),
467 	SND_SOC_DAPM_MIXER("LOR Disable HFR",
468 			AB8500_ANACONF4, AB8500_ANACONF4_ENHFR, 1,
469 			NULL, 0),
470 
471 	SND_SOC_DAPM_MIXER("LOL Enable",
472 			AB8500_ANACONF5, AB8500_ANACONF5_ENLOL, 0,
473 			NULL, 0),
474 	SND_SOC_DAPM_MIXER("LOR Enable",
475 			AB8500_ANACONF5, AB8500_ANACONF5_ENLOR, 0,
476 			NULL, 0),
477 
478 	SND_SOC_DAPM_OUTPUT("LineOut Left"),
479 	SND_SOC_DAPM_OUTPUT("LineOut Right"),
480 
481 	/* Earpiece path */
482 
483 	SND_SOC_DAPM_MUX("Earpiece or LineOut Mono Source",
484 			SND_SOC_NOPM, 0, 0, &dapm_ear_lineout_source),
485 	SND_SOC_DAPM_MIXER("EAR DAC",
486 			AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACEAR, 0,
487 			NULL, 0),
488 	SND_SOC_DAPM_MIXER("EAR Mute",
489 			AB8500_MUTECONF, AB8500_MUTECONF_MUTEAR, 1,
490 			NULL, 0),
491 	SND_SOC_DAPM_MIXER("EAR Enable",
492 			AB8500_ANACONF4, AB8500_ANACONF4_ENEAR, 0,
493 			NULL, 0),
494 
495 	SND_SOC_DAPM_OUTPUT("Earpiece"),
496 
497 	/* Handsfree path */
498 
499 	SND_SOC_DAPM_MIXER("DA3 Channel Volume",
500 			AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA3, 0,
501 			NULL, 0),
502 	SND_SOC_DAPM_MIXER("DA4 Channel Volume",
503 			AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA4, 0,
504 			NULL, 0),
505 	SND_SOC_DAPM_MUX("Speaker Left Source",
506 			SND_SOC_NOPM, 0, 0, dapm_HFl_select),
507 	SND_SOC_DAPM_MUX("Speaker Right Source",
508 			SND_SOC_NOPM, 0, 0, dapm_HFr_select),
509 	SND_SOC_DAPM_MIXER("HFL DAC", AB8500_DAPATHCONF,
510 			AB8500_DAPATHCONF_ENDACHFL, 0,
511 			NULL, 0),
512 	SND_SOC_DAPM_MIXER("HFR DAC",
513 			AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACHFR, 0,
514 			NULL, 0),
515 	SND_SOC_DAPM_MIXER("DA4 or ANC path to HfR",
516 			AB8500_DIGMULTCONF2, AB8500_DIGMULTCONF2_DATOHFREN, 0,
517 			NULL, 0),
518 	SND_SOC_DAPM_MIXER("DA3 or ANC path to HfL",
519 			AB8500_DIGMULTCONF2, AB8500_DIGMULTCONF2_DATOHFLEN, 0,
520 			NULL, 0),
521 	SND_SOC_DAPM_MIXER("HFL Enable",
522 			AB8500_ANACONF4, AB8500_ANACONF4_ENHFL, 0,
523 			NULL, 0),
524 	SND_SOC_DAPM_MIXER("HFR Enable",
525 			AB8500_ANACONF4, AB8500_ANACONF4_ENHFR, 0,
526 			NULL, 0),
527 
528 	SND_SOC_DAPM_OUTPUT("Speaker Left"),
529 	SND_SOC_DAPM_OUTPUT("Speaker Right"),
530 
531 	/* Vibrator path */
532 
533 	SND_SOC_DAPM_INPUT("PWMGEN1"),
534 	SND_SOC_DAPM_INPUT("PWMGEN2"),
535 
536 	SND_SOC_DAPM_MIXER("DA5 Channel Volume",
537 			AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA5, 0,
538 			NULL, 0),
539 	SND_SOC_DAPM_MIXER("DA6 Channel Volume",
540 			AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA6, 0,
541 			NULL, 0),
542 	SND_SOC_DAPM_MIXER("VIB1 DAC",
543 			AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACVIB1, 0,
544 			NULL, 0),
545 	SND_SOC_DAPM_MIXER("VIB2 DAC",
546 			AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACVIB2, 0,
547 			NULL, 0),
548 	SND_SOC_DAPM_MUX("Vibra 1 Controller",
549 			SND_SOC_NOPM, 0, 0, dapm_pwm2vib1),
550 	SND_SOC_DAPM_MUX("Vibra 2 Controller",
551 			SND_SOC_NOPM, 0, 0, dapm_pwm2vib2),
552 	SND_SOC_DAPM_MIXER("VIB1 Enable",
553 			AB8500_ANACONF4, AB8500_ANACONF4_ENVIB1, 0,
554 			NULL, 0),
555 	SND_SOC_DAPM_MIXER("VIB2 Enable",
556 			AB8500_ANACONF4, AB8500_ANACONF4_ENVIB2, 0,
557 			NULL, 0),
558 
559 	SND_SOC_DAPM_OUTPUT("Vibra 1"),
560 	SND_SOC_DAPM_OUTPUT("Vibra 2"),
561 
562 	/* Mic 1 */
563 
564 	SND_SOC_DAPM_INPUT("Mic 1"),
565 
566 	SND_SOC_DAPM_MUX("Mic 1a or 1b Select",
567 			SND_SOC_NOPM, 0, 0, dapm_mic1ab_mux),
568 	SND_SOC_DAPM_MIXER("MIC1 Mute",
569 			AB8500_ANACONF2, AB8500_ANACONF2_MUTMIC1, 1,
570 			NULL, 0),
571 	SND_SOC_DAPM_MIXER("MIC1A V-AMICx Enable",
572 			AB8500_ANACONF2, AB8500_ANACONF2_ENMIC1, 0,
573 			NULL, 0),
574 	SND_SOC_DAPM_MIXER("MIC1B V-AMICx Enable",
575 			AB8500_ANACONF2, AB8500_ANACONF2_ENMIC1, 0,
576 			NULL, 0),
577 	SND_SOC_DAPM_MIXER("MIC1 ADC",
578 			AB8500_ANACONF3, AB8500_ANACONF3_ENADCMIC, 0,
579 			NULL, 0),
580 	SND_SOC_DAPM_MUX("AD3 Source Select",
581 			SND_SOC_NOPM, 0, 0, dapm_ad3_select),
582 	SND_SOC_DAPM_MIXER("AD3 Channel Volume",
583 			SND_SOC_NOPM, 0, 0,
584 			NULL, 0),
585 	SND_SOC_DAPM_MIXER("AD3 Enable",
586 			AB8500_ADPATHENA, AB8500_ADPATHENA_ENAD34, 0,
587 			NULL, 0),
588 
589 	/* Mic 2 */
590 
591 	SND_SOC_DAPM_INPUT("Mic 2"),
592 
593 	SND_SOC_DAPM_MIXER("MIC2 Mute",
594 			AB8500_ANACONF2, AB8500_ANACONF2_MUTMIC2, 1,
595 			NULL, 0),
596 	SND_SOC_DAPM_MIXER("MIC2 V-AMICx Enable", AB8500_ANACONF2,
597 			AB8500_ANACONF2_ENMIC2, 0,
598 			NULL, 0),
599 
600 	/* LineIn */
601 
602 	SND_SOC_DAPM_INPUT("LineIn Left"),
603 	SND_SOC_DAPM_INPUT("LineIn Right"),
604 
605 	SND_SOC_DAPM_MIXER("LINL Mute",
606 			AB8500_ANACONF2, AB8500_ANACONF2_MUTLINL, 1,
607 			NULL, 0),
608 	SND_SOC_DAPM_MIXER("LINR Mute",
609 			AB8500_ANACONF2, AB8500_ANACONF2_MUTLINR, 1,
610 			NULL, 0),
611 	SND_SOC_DAPM_MIXER("LINL Enable", AB8500_ANACONF2,
612 			AB8500_ANACONF2_ENLINL, 0,
613 			NULL, 0),
614 	SND_SOC_DAPM_MIXER("LINR Enable", AB8500_ANACONF2,
615 			AB8500_ANACONF2_ENLINR, 0,
616 			NULL, 0),
617 
618 	/* LineIn Bypass path */
619 	SND_SOC_DAPM_MIXER("LINL to HSL Volume",
620 			SND_SOC_NOPM, 0, 0,
621 			NULL, 0),
622 	SND_SOC_DAPM_MIXER("LINR to HSR Volume",
623 			SND_SOC_NOPM, 0, 0,
624 			NULL, 0),
625 
626 	/* LineIn, Mic 2 */
627 	SND_SOC_DAPM_MUX("Mic 2 or LINR Select",
628 			SND_SOC_NOPM, 0, 0, dapm_mic2lr_select),
629 	SND_SOC_DAPM_MIXER("LINL ADC", AB8500_ANACONF3,
630 			AB8500_ANACONF3_ENADCLINL, 0,
631 			NULL, 0),
632 	SND_SOC_DAPM_MIXER("LINR ADC", AB8500_ANACONF3,
633 			AB8500_ANACONF3_ENADCLINR, 0,
634 			NULL, 0),
635 	SND_SOC_DAPM_MUX("AD1 Source Select",
636 			SND_SOC_NOPM, 0, 0, dapm_ad1_select),
637 	SND_SOC_DAPM_MUX("AD2 Source Select",
638 			SND_SOC_NOPM, 0, 0, dapm_ad2_select),
639 	SND_SOC_DAPM_MIXER("AD1 Channel Volume",
640 			SND_SOC_NOPM, 0, 0,
641 			NULL, 0),
642 	SND_SOC_DAPM_MIXER("AD2 Channel Volume",
643 			SND_SOC_NOPM, 0, 0,
644 			NULL, 0),
645 
646 	SND_SOC_DAPM_MIXER("AD12 Enable",
647 			AB8500_ADPATHENA, AB8500_ADPATHENA_ENAD12, 0,
648 			NULL, 0),
649 
650 	/* HD Capture path */
651 
652 	SND_SOC_DAPM_MUX("AD5 Source Select",
653 			SND_SOC_NOPM, 0, 0, dapm_ad5_select),
654 	SND_SOC_DAPM_MUX("AD6 Source Select",
655 			SND_SOC_NOPM, 0, 0, dapm_ad6_select),
656 	SND_SOC_DAPM_MIXER("AD5 Channel Volume",
657 			SND_SOC_NOPM, 0, 0,
658 			NULL, 0),
659 	SND_SOC_DAPM_MIXER("AD6 Channel Volume",
660 			SND_SOC_NOPM, 0, 0,
661 			NULL, 0),
662 	SND_SOC_DAPM_MIXER("AD57 Enable",
663 			AB8500_ADPATHENA, AB8500_ADPATHENA_ENAD5768, 0,
664 			NULL, 0),
665 	SND_SOC_DAPM_MIXER("AD68 Enable",
666 			AB8500_ADPATHENA, AB8500_ADPATHENA_ENAD5768, 0,
667 			NULL, 0),
668 
669 	/* Digital Microphone path */
670 
671 	SND_SOC_DAPM_INPUT("DMic 1"),
672 	SND_SOC_DAPM_INPUT("DMic 2"),
673 	SND_SOC_DAPM_INPUT("DMic 3"),
674 	SND_SOC_DAPM_INPUT("DMic 4"),
675 	SND_SOC_DAPM_INPUT("DMic 5"),
676 	SND_SOC_DAPM_INPUT("DMic 6"),
677 
678 	SND_SOC_DAPM_MIXER("DMIC1",
679 			AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC1, 0,
680 			NULL, 0),
681 	SND_SOC_DAPM_MIXER("DMIC2",
682 			AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC2, 0,
683 			NULL, 0),
684 	SND_SOC_DAPM_MIXER("DMIC3",
685 			AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC3, 0,
686 			NULL, 0),
687 	SND_SOC_DAPM_MIXER("DMIC4",
688 			AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC4, 0,
689 			NULL, 0),
690 	SND_SOC_DAPM_MIXER("DMIC5",
691 			AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC5, 0,
692 			NULL, 0),
693 	SND_SOC_DAPM_MIXER("DMIC6",
694 			AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC6, 0,
695 			NULL, 0),
696 	SND_SOC_DAPM_MIXER("AD4 Channel Volume",
697 			SND_SOC_NOPM, 0, 0,
698 			NULL, 0),
699 	SND_SOC_DAPM_MIXER("AD4 Enable",
700 			AB8500_ADPATHENA, AB8500_ADPATHENA_ENAD34,
701 			0, NULL, 0),
702 
703 	/* Acoustical Noise Cancellation path */
704 
705 	SND_SOC_DAPM_INPUT("ANC Configure Input"),
706 	SND_SOC_DAPM_OUTPUT("ANC Configure Output"),
707 
708 	SND_SOC_DAPM_MUX("ANC Source",
709 			SND_SOC_NOPM, 0, 0,
710 			dapm_anc_in_select),
711 	SND_SOC_DAPM_SWITCH("ANC",
712 			SND_SOC_NOPM, 0, 0,
713 			dapm_anc_enable),
714 	SND_SOC_DAPM_SWITCH("ANC to Earpiece",
715 			SND_SOC_NOPM, 0, 0,
716 			dapm_anc_ear_mute),
717 
718 	/* Sidetone Filter path */
719 
720 	SND_SOC_DAPM_MUX("Sidetone Left Source",
721 			SND_SOC_NOPM, 0, 0,
722 			dapm_stfir1_in_select),
723 	SND_SOC_DAPM_MUX("Sidetone Right Source",
724 			SND_SOC_NOPM, 0, 0,
725 			dapm_stfir2_in_select),
726 	SND_SOC_DAPM_MIXER("STFIR1 Control",
727 			SND_SOC_NOPM, 0, 0,
728 			NULL, 0),
729 	SND_SOC_DAPM_MIXER("STFIR2 Control",
730 			SND_SOC_NOPM, 0, 0,
731 			NULL, 0),
732 	SND_SOC_DAPM_MIXER("STFIR1 Volume",
733 			SND_SOC_NOPM, 0, 0,
734 			NULL, 0),
735 	SND_SOC_DAPM_MIXER("STFIR2 Volume",
736 			SND_SOC_NOPM, 0, 0,
737 			NULL, 0),
738 };
739 
740 /*
741  * DAPM-routes
742  */
743 static const struct snd_soc_dapm_route ab8500_dapm_routes[] = {
744 	/* Power AB8500 audio-block when AD/DA is active */
745 	{"Main Supply", NULL, "V-AUD"},
746 	{"Main Supply", NULL, "audioclk"},
747 	{"Main Supply", NULL, "Audio Power"},
748 	{"Main Supply", NULL, "Audio Analog Power"},
749 
750 	{"DAC", NULL, "ab8500_0p"},
751 	{"DAC", NULL, "Main Supply"},
752 	{"ADC", NULL, "ab8500_0c"},
753 	{"ADC", NULL, "Main Supply"},
754 
755 	/* ANC Configure */
756 	{"ANC Configure Input", NULL, "Main Supply"},
757 	{"ANC Configure Output", NULL, "ANC Configure Input"},
758 
759 	/* AD/DA */
760 	{"ADC", NULL, "ADC Input"},
761 	{"DAC Output", NULL, "DAC"},
762 
763 	/* Powerup charge pump if DA1/2 is in use */
764 
765 	{"DA_IN1", NULL, "ab8500_0p"},
766 	{"DA_IN1", NULL, "Charge Pump"},
767 	{"DA_IN2", NULL, "ab8500_0p"},
768 	{"DA_IN2", NULL, "Charge Pump"},
769 
770 	/* Headset path */
771 
772 	{"DA1 Enable", NULL, "DA_IN1"},
773 	{"DA2 Enable", NULL, "DA_IN2"},
774 
775 	{"HSL Digital Volume", NULL, "DA1 Enable"},
776 	{"HSR Digital Volume", NULL, "DA2 Enable"},
777 
778 	{"HSL DAC", NULL, "HSL Digital Volume"},
779 	{"HSR DAC", NULL, "HSR Digital Volume"},
780 
781 	{"HSL DAC Mute", NULL, "HSL DAC"},
782 	{"HSR DAC Mute", NULL, "HSR DAC"},
783 
784 	{"HSL DAC Driver", NULL, "HSL DAC Mute"},
785 	{"HSR DAC Driver", NULL, "HSR DAC Mute"},
786 
787 	{"HSL Mute", NULL, "HSL DAC Driver"},
788 	{"HSR Mute", NULL, "HSR DAC Driver"},
789 
790 	{"HSL Enable", NULL, "HSL Mute"},
791 	{"HSR Enable", NULL, "HSR Mute"},
792 
793 	{"HSL Volume", NULL, "HSL Enable"},
794 	{"HSR Volume", NULL, "HSR Enable"},
795 
796 	{"Headset Left", NULL, "HSL Volume"},
797 	{"Headset Right", NULL, "HSR Volume"},
798 
799 	/* HF or LineOut path */
800 
801 	{"DA_IN3", NULL, "ab8500_0p"},
802 	{"DA3 Channel Volume", NULL, "DA_IN3"},
803 	{"DA_IN4", NULL, "ab8500_0p"},
804 	{"DA4 Channel Volume", NULL, "DA_IN4"},
805 
806 	{"Speaker Left Source", "Audio Path", "DA3 Channel Volume"},
807 	{"Speaker Right Source", "Audio Path", "DA4 Channel Volume"},
808 
809 	{"DA3 or ANC path to HfL", NULL, "Speaker Left Source"},
810 	{"DA4 or ANC path to HfR", NULL, "Speaker Right Source"},
811 
812 	/* HF path */
813 
814 	{"HFL DAC", NULL, "DA3 or ANC path to HfL"},
815 	{"HFR DAC", NULL, "DA4 or ANC path to HfR"},
816 
817 	{"HFL Enable", NULL, "HFL DAC"},
818 	{"HFR Enable", NULL, "HFR DAC"},
819 
820 	{"Speaker Left", NULL, "HFL Enable"},
821 	{"Speaker Right", NULL, "HFR Enable"},
822 
823 	/* Earpiece path */
824 
825 	{"Earpiece or LineOut Mono Source", "Headset Left",
826 		"HSL Digital Volume"},
827 	{"Earpiece or LineOut Mono Source", "Speaker Left",
828 		"DA3 or ANC path to HfL"},
829 
830 	{"EAR DAC", NULL, "Earpiece or LineOut Mono Source"},
831 
832 	{"EAR Mute", NULL, "EAR DAC"},
833 
834 	{"EAR Enable", NULL, "EAR Mute"},
835 
836 	{"Earpiece", NULL, "EAR Enable"},
837 
838 	/* LineOut path stereo */
839 
840 	{"LineOut Source", "Stereo Path", "HSL DAC Driver"},
841 	{"LineOut Source", "Stereo Path", "HSR DAC Driver"},
842 
843 	/* LineOut path mono */
844 
845 	{"LineOut Source", "Mono Path", "EAR DAC"},
846 
847 	/* LineOut path */
848 
849 	{"LOL Disable HFL", NULL, "LineOut Source"},
850 	{"LOR Disable HFR", NULL, "LineOut Source"},
851 
852 	{"LOL Enable", NULL, "LOL Disable HFL"},
853 	{"LOR Enable", NULL, "LOR Disable HFR"},
854 
855 	{"LineOut Left", NULL, "LOL Enable"},
856 	{"LineOut Right", NULL, "LOR Enable"},
857 
858 	/* Vibrator path */
859 
860 	{"DA_IN5", NULL, "ab8500_0p"},
861 	{"DA5 Channel Volume", NULL, "DA_IN5"},
862 	{"DA_IN6", NULL, "ab8500_0p"},
863 	{"DA6 Channel Volume", NULL, "DA_IN6"},
864 
865 	{"VIB1 DAC", NULL, "DA5 Channel Volume"},
866 	{"VIB2 DAC", NULL, "DA6 Channel Volume"},
867 
868 	{"Vibra 1 Controller", "Audio Path", "VIB1 DAC"},
869 	{"Vibra 2 Controller", "Audio Path", "VIB2 DAC"},
870 	{"Vibra 1 Controller", "PWM Generator", "PWMGEN1"},
871 	{"Vibra 2 Controller", "PWM Generator", "PWMGEN2"},
872 
873 	{"VIB1 Enable", NULL, "Vibra 1 Controller"},
874 	{"VIB2 Enable", NULL, "Vibra 2 Controller"},
875 
876 	{"Vibra 1", NULL, "VIB1 Enable"},
877 	{"Vibra 2", NULL, "VIB2 Enable"},
878 
879 
880 	/* Mic 2 */
881 
882 	{"MIC2 V-AMICx Enable", NULL, "Mic 2"},
883 
884 	/* LineIn */
885 	{"LINL Mute", NULL, "LineIn Left"},
886 	{"LINR Mute", NULL, "LineIn Right"},
887 
888 	{"LINL Enable", NULL, "LINL Mute"},
889 	{"LINR Enable", NULL, "LINR Mute"},
890 
891 	/* LineIn, Mic 2 */
892 	{"Mic 2 or LINR Select", "LineIn Right", "LINR Enable"},
893 	{"Mic 2 or LINR Select", "Mic 2", "MIC2 V-AMICx Enable"},
894 
895 	{"LINL ADC", NULL, "LINL Enable"},
896 	{"LINR ADC", NULL, "Mic 2 or LINR Select"},
897 
898 	{"AD1 Source Select", "LineIn Left", "LINL ADC"},
899 	{"AD2 Source Select", "LineIn Right", "LINR ADC"},
900 
901 	{"AD1 Channel Volume", NULL, "AD1 Source Select"},
902 	{"AD2 Channel Volume", NULL, "AD2 Source Select"},
903 
904 	{"AD12 Enable", NULL, "AD1 Channel Volume"},
905 	{"AD12 Enable", NULL, "AD2 Channel Volume"},
906 
907 	{"AD_OUT1", NULL, "ab8500_0c"},
908 	{"AD_OUT1", NULL, "AD12 Enable"},
909 	{"AD_OUT2", NULL, "ab8500_0c"},
910 	{"AD_OUT2", NULL, "AD12 Enable"},
911 
912 	/* Mic 1 */
913 
914 	{"MIC1 Mute", NULL, "Mic 1"},
915 
916 	{"MIC1A V-AMICx Enable", NULL, "MIC1 Mute"},
917 	{"MIC1B V-AMICx Enable", NULL, "MIC1 Mute"},
918 
919 	{"Mic 1a or 1b Select", "Mic 1a", "MIC1A V-AMICx Enable"},
920 	{"Mic 1a or 1b Select", "Mic 1b", "MIC1B V-AMICx Enable"},
921 
922 	{"MIC1 ADC", NULL, "Mic 1a or 1b Select"},
923 
924 	{"AD3 Source Select", "Mic 1", "MIC1 ADC"},
925 
926 	{"AD3 Channel Volume", NULL, "AD3 Source Select"},
927 
928 	{"AD3 Enable", NULL, "AD3 Channel Volume"},
929 
930 	{"AD_OUT3", NULL, "ab8500_0c"},
931 	{"AD_OUT3", NULL, "AD3 Enable"},
932 
933 	/* HD Capture path */
934 
935 	{"AD5 Source Select", "Mic 2", "LINR ADC"},
936 	{"AD6 Source Select", "Mic 1", "MIC1 ADC"},
937 
938 	{"AD5 Channel Volume", NULL, "AD5 Source Select"},
939 	{"AD6 Channel Volume", NULL, "AD6 Source Select"},
940 
941 	{"AD57 Enable", NULL, "AD5 Channel Volume"},
942 	{"AD68 Enable", NULL, "AD6 Channel Volume"},
943 
944 	{"AD_OUT57", NULL, "ab8500_0c"},
945 	{"AD_OUT57", NULL, "AD57 Enable"},
946 	{"AD_OUT68", NULL, "ab8500_0c"},
947 	{"AD_OUT68", NULL, "AD68 Enable"},
948 
949 	/* Digital Microphone path */
950 
951 	{"DMic 1", NULL, "V-DMIC"},
952 	{"DMic 2", NULL, "V-DMIC"},
953 	{"DMic 3", NULL, "V-DMIC"},
954 	{"DMic 4", NULL, "V-DMIC"},
955 	{"DMic 5", NULL, "V-DMIC"},
956 	{"DMic 6", NULL, "V-DMIC"},
957 
958 	{"AD1 Source Select", NULL, "DMic 1"},
959 	{"AD2 Source Select", NULL, "DMic 2"},
960 	{"AD3 Source Select", NULL, "DMic 3"},
961 	{"AD5 Source Select", NULL, "DMic 5"},
962 	{"AD6 Source Select", NULL, "DMic 6"},
963 
964 	{"AD4 Channel Volume", NULL, "DMic 4"},
965 	{"AD4 Enable", NULL, "AD4 Channel Volume"},
966 
967 	{"AD_OUT4", NULL, "ab8500_0c"},
968 	{"AD_OUT4", NULL, "AD4 Enable"},
969 
970 	/* LineIn Bypass path */
971 
972 	{"LINL to HSL Volume", NULL, "LINL Enable"},
973 	{"LINR to HSR Volume", NULL, "LINR Enable"},
974 
975 	{"HSL DAC Driver", NULL, "LINL to HSL Volume"},
976 	{"HSR DAC Driver", NULL, "LINR to HSR Volume"},
977 
978 	/* ANC path (Acoustic Noise Cancellation) */
979 
980 	{"ANC Source", "Mic 2 / DMic 5", "AD5 Channel Volume"},
981 	{"ANC Source", "Mic 1 / DMic 6", "AD6 Channel Volume"},
982 
983 	{"ANC", "Switch", "ANC Source"},
984 
985 	{"Speaker Left Source", "ANC", "ANC"},
986 	{"Speaker Right Source", "ANC", "ANC"},
987 	{"ANC to Earpiece", "Switch", "ANC"},
988 
989 	{"HSL Digital Volume", NULL, "ANC to Earpiece"},
990 
991 	/* Sidetone Filter path */
992 
993 	{"Sidetone Left Source", "LineIn Left", "AD12 Enable"},
994 	{"Sidetone Left Source", "LineIn Right", "AD12 Enable"},
995 	{"Sidetone Left Source", "Mic 1", "AD3 Enable"},
996 	{"Sidetone Left Source", "Headset Left", "DA_IN1"},
997 	{"Sidetone Right Source", "LineIn Right", "AD12 Enable"},
998 	{"Sidetone Right Source", "Mic 1", "AD3 Enable"},
999 	{"Sidetone Right Source", "DMic 4", "AD4 Enable"},
1000 	{"Sidetone Right Source", "Headset Right", "DA_IN2"},
1001 
1002 	{"STFIR1 Control", NULL, "Sidetone Left Source"},
1003 	{"STFIR2 Control", NULL, "Sidetone Right Source"},
1004 
1005 	{"STFIR1 Volume", NULL, "STFIR1 Control"},
1006 	{"STFIR2 Volume", NULL, "STFIR2 Control"},
1007 
1008 	{"DA1 Enable", NULL, "STFIR1 Volume"},
1009 	{"DA2 Enable", NULL, "STFIR2 Volume"},
1010 };
1011 
1012 static const struct snd_soc_dapm_route ab8500_dapm_routes_mic1a_vamicx[] = {
1013 	{"MIC1A V-AMICx Enable", NULL, "V-AMIC1"},
1014 	{"MIC1A V-AMICx Enable", NULL, "V-AMIC2"},
1015 };
1016 
1017 static const struct snd_soc_dapm_route ab8500_dapm_routes_mic1b_vamicx[] = {
1018 	{"MIC1B V-AMICx Enable", NULL, "V-AMIC1"},
1019 	{"MIC1B V-AMICx Enable", NULL, "V-AMIC2"},
1020 };
1021 
1022 static const struct snd_soc_dapm_route ab8500_dapm_routes_mic2_vamicx[] = {
1023 	{"MIC2 V-AMICx Enable", NULL, "V-AMIC1"},
1024 	{"MIC2 V-AMICx Enable", NULL, "V-AMIC2"},
1025 };
1026 
1027 /* ANC FIR-coefficients configuration sequence */
anc_fir(struct snd_soc_component * component,unsigned int bnk,unsigned int par,unsigned int val)1028 static void anc_fir(struct snd_soc_component *component,
1029 		unsigned int bnk, unsigned int par, unsigned int val)
1030 {
1031 	if (par == 0 && bnk == 0)
1032 		snd_soc_component_update_bits(component, AB8500_ANCCONF1,
1033 			BIT(AB8500_ANCCONF1_ANCFIRUPDATE),
1034 			BIT(AB8500_ANCCONF1_ANCFIRUPDATE));
1035 
1036 	snd_soc_component_write(component, AB8500_ANCCONF5, val >> 8 & 0xff);
1037 	snd_soc_component_write(component, AB8500_ANCCONF6, val &  0xff);
1038 
1039 	if (par == AB8500_ANC_FIR_COEFFS - 1 && bnk == 1)
1040 		snd_soc_component_update_bits(component, AB8500_ANCCONF1,
1041 			BIT(AB8500_ANCCONF1_ANCFIRUPDATE), 0);
1042 }
1043 
1044 /* ANC IIR-coefficients configuration sequence */
anc_iir(struct snd_soc_component * component,unsigned int bnk,unsigned int par,unsigned int val)1045 static void anc_iir(struct snd_soc_component *component, unsigned int bnk,
1046 		unsigned int par, unsigned int val)
1047 {
1048 	if (par == 0) {
1049 		if (bnk == 0) {
1050 			snd_soc_component_update_bits(component, AB8500_ANCCONF1,
1051 					BIT(AB8500_ANCCONF1_ANCIIRINIT),
1052 					BIT(AB8500_ANCCONF1_ANCIIRINIT));
1053 			usleep_range(AB8500_ANC_SM_DELAY, AB8500_ANC_SM_DELAY*2);
1054 			snd_soc_component_update_bits(component, AB8500_ANCCONF1,
1055 					BIT(AB8500_ANCCONF1_ANCIIRINIT), 0);
1056 			usleep_range(AB8500_ANC_SM_DELAY, AB8500_ANC_SM_DELAY*2);
1057 		} else {
1058 			snd_soc_component_update_bits(component, AB8500_ANCCONF1,
1059 					BIT(AB8500_ANCCONF1_ANCIIRUPDATE),
1060 					BIT(AB8500_ANCCONF1_ANCIIRUPDATE));
1061 		}
1062 	} else if (par > 3) {
1063 		snd_soc_component_write(component, AB8500_ANCCONF7, 0);
1064 		snd_soc_component_write(component, AB8500_ANCCONF8, val >> 16 & 0xff);
1065 	}
1066 
1067 	snd_soc_component_write(component, AB8500_ANCCONF7, val >> 8 & 0xff);
1068 	snd_soc_component_write(component, AB8500_ANCCONF8, val & 0xff);
1069 
1070 	if (par == AB8500_ANC_IIR_COEFFS - 1 && bnk == 1)
1071 		snd_soc_component_update_bits(component, AB8500_ANCCONF1,
1072 			BIT(AB8500_ANCCONF1_ANCIIRUPDATE), 0);
1073 }
1074 
1075 /* ANC IIR-/FIR-coefficients configuration sequence */
anc_configure(struct snd_soc_component * component,bool apply_fir,bool apply_iir)1076 static void anc_configure(struct snd_soc_component *component,
1077 			bool apply_fir, bool apply_iir)
1078 {
1079 	struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(component->dev);
1080 	unsigned int bnk, par, val;
1081 
1082 	dev_dbg(component->dev, "%s: Enter.\n", __func__);
1083 
1084 	if (apply_fir)
1085 		snd_soc_component_update_bits(component, AB8500_ANCCONF1,
1086 			BIT(AB8500_ANCCONF1_ENANC), 0);
1087 
1088 	snd_soc_component_update_bits(component, AB8500_ANCCONF1,
1089 		BIT(AB8500_ANCCONF1_ENANC), BIT(AB8500_ANCCONF1_ENANC));
1090 
1091 	if (apply_fir)
1092 		for (bnk = 0; bnk < AB8500_NR_OF_ANC_COEFF_BANKS; bnk++)
1093 			for (par = 0; par < AB8500_ANC_FIR_COEFFS; par++) {
1094 				val = snd_soc_component_read(component,
1095 						drvdata->anc_fir_values[par]);
1096 				anc_fir(component, bnk, par, val);
1097 			}
1098 
1099 	if (apply_iir)
1100 		for (bnk = 0; bnk < AB8500_NR_OF_ANC_COEFF_BANKS; bnk++)
1101 			for (par = 0; par < AB8500_ANC_IIR_COEFFS; par++) {
1102 				val = snd_soc_component_read(component,
1103 						drvdata->anc_iir_values[par]);
1104 				anc_iir(component, bnk, par, val);
1105 			}
1106 
1107 	dev_dbg(component->dev, "%s: Exit.\n", __func__);
1108 }
1109 
1110 /*
1111  * Control-events
1112  */
1113 
sid_status_control_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1114 static int sid_status_control_get(struct snd_kcontrol *kcontrol,
1115 		struct snd_ctl_elem_value *ucontrol)
1116 {
1117 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1118 	struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(component->dev);
1119 
1120 	mutex_lock(&drvdata->ctrl_lock);
1121 	ucontrol->value.enumerated.item[0] = drvdata->sid_status;
1122 	mutex_unlock(&drvdata->ctrl_lock);
1123 
1124 	return 0;
1125 }
1126 
1127 /* Write sidetone FIR-coefficients configuration sequence */
sid_status_control_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1128 static int sid_status_control_put(struct snd_kcontrol *kcontrol,
1129 				struct snd_ctl_elem_value *ucontrol)
1130 {
1131 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1132 	struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(component->dev);
1133 	unsigned int param, sidconf, val;
1134 	int status = 1;
1135 
1136 	dev_dbg(component->dev, "%s: Enter\n", __func__);
1137 
1138 	if (ucontrol->value.enumerated.item[0] != SID_APPLY_FIR) {
1139 		dev_err(component->dev,
1140 			"%s: ERROR: This control supports '%s' only!\n",
1141 			__func__, enum_sid_state[SID_APPLY_FIR]);
1142 		return -EIO;
1143 	}
1144 
1145 	mutex_lock(&drvdata->ctrl_lock);
1146 
1147 	sidconf = snd_soc_component_read(component, AB8500_SIDFIRCONF);
1148 	if (((sidconf & BIT(AB8500_SIDFIRCONF_FIRSIDBUSY)) != 0)) {
1149 		if ((sidconf & BIT(AB8500_SIDFIRCONF_ENFIRSIDS)) == 0) {
1150 			dev_err(component->dev, "%s: Sidetone busy while off!\n",
1151 				__func__);
1152 			status = -EPERM;
1153 		} else {
1154 			status = -EBUSY;
1155 		}
1156 		goto out;
1157 	}
1158 
1159 	snd_soc_component_write(component, AB8500_SIDFIRADR, 0);
1160 
1161 	for (param = 0; param < AB8500_SID_FIR_COEFFS; param++) {
1162 		val = snd_soc_component_read(component, drvdata->sid_fir_values[param]);
1163 		snd_soc_component_write(component, AB8500_SIDFIRCOEF1, val >> 8 & 0xff);
1164 		snd_soc_component_write(component, AB8500_SIDFIRCOEF2, val & 0xff);
1165 	}
1166 
1167 	snd_soc_component_update_bits(component, AB8500_SIDFIRADR,
1168 		BIT(AB8500_SIDFIRADR_FIRSIDSET),
1169 		BIT(AB8500_SIDFIRADR_FIRSIDSET));
1170 	snd_soc_component_update_bits(component, AB8500_SIDFIRADR,
1171 		BIT(AB8500_SIDFIRADR_FIRSIDSET), 0);
1172 
1173 	drvdata->sid_status = SID_FIR_CONFIGURED;
1174 
1175 out:
1176 	mutex_unlock(&drvdata->ctrl_lock);
1177 
1178 	dev_dbg(component->dev, "%s: Exit\n", __func__);
1179 
1180 	return status;
1181 }
1182 
anc_status_control_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1183 static int anc_status_control_get(struct snd_kcontrol *kcontrol,
1184 				struct snd_ctl_elem_value *ucontrol)
1185 {
1186 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1187 	struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(component->dev);
1188 
1189 	mutex_lock(&drvdata->ctrl_lock);
1190 	ucontrol->value.enumerated.item[0] = drvdata->anc_status;
1191 	mutex_unlock(&drvdata->ctrl_lock);
1192 
1193 	return 0;
1194 }
1195 
anc_status_control_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1196 static int anc_status_control_put(struct snd_kcontrol *kcontrol,
1197 				struct snd_ctl_elem_value *ucontrol)
1198 {
1199 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1200 	struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
1201 	struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(component->dev);
1202 	struct device *dev = component->dev;
1203 	bool apply_fir, apply_iir;
1204 	unsigned int req;
1205 	int status;
1206 
1207 	dev_dbg(dev, "%s: Enter.\n", __func__);
1208 
1209 	mutex_lock(&drvdata->ctrl_lock);
1210 
1211 	req = ucontrol->value.enumerated.item[0];
1212 	if (req >= ARRAY_SIZE(enum_anc_state)) {
1213 		status = -EINVAL;
1214 		goto cleanup;
1215 	}
1216 	if (req != ANC_APPLY_FIR_IIR && req != ANC_APPLY_FIR &&
1217 		req != ANC_APPLY_IIR) {
1218 		dev_err(dev, "%s: ERROR: Unsupported status to set '%s'!\n",
1219 			__func__, enum_anc_state[req]);
1220 		status = -EINVAL;
1221 		goto cleanup;
1222 	}
1223 	apply_fir = req == ANC_APPLY_FIR || req == ANC_APPLY_FIR_IIR;
1224 	apply_iir = req == ANC_APPLY_IIR || req == ANC_APPLY_FIR_IIR;
1225 
1226 	status = snd_soc_dapm_force_enable_pin(dapm, "ANC Configure Input");
1227 	if (status < 0) {
1228 		dev_err(dev,
1229 			"%s: ERROR: Failed to enable power (status = %d)!\n",
1230 			__func__, status);
1231 		goto cleanup;
1232 	}
1233 	snd_soc_dapm_sync(dapm);
1234 
1235 	anc_configure(component, apply_fir, apply_iir);
1236 
1237 	if (apply_fir) {
1238 		if (drvdata->anc_status == ANC_IIR_CONFIGURED)
1239 			drvdata->anc_status = ANC_FIR_IIR_CONFIGURED;
1240 		else if (drvdata->anc_status != ANC_FIR_IIR_CONFIGURED)
1241 			drvdata->anc_status =  ANC_FIR_CONFIGURED;
1242 	}
1243 	if (apply_iir) {
1244 		if (drvdata->anc_status == ANC_FIR_CONFIGURED)
1245 			drvdata->anc_status = ANC_FIR_IIR_CONFIGURED;
1246 		else if (drvdata->anc_status != ANC_FIR_IIR_CONFIGURED)
1247 			drvdata->anc_status =  ANC_IIR_CONFIGURED;
1248 	}
1249 
1250 	status = snd_soc_dapm_disable_pin(dapm, "ANC Configure Input");
1251 	snd_soc_dapm_sync(dapm);
1252 
1253 cleanup:
1254 	mutex_unlock(&drvdata->ctrl_lock);
1255 
1256 	if (status < 0)
1257 		dev_err(dev, "%s: Unable to configure ANC! (status = %d)\n",
1258 			__func__, status);
1259 
1260 	dev_dbg(dev, "%s: Exit.\n", __func__);
1261 
1262 	return (status < 0) ? status : 1;
1263 }
1264 
filter_control_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)1265 static int filter_control_info(struct snd_kcontrol *kcontrol,
1266 			struct snd_ctl_elem_info *uinfo)
1267 {
1268 	struct filter_control *fc =
1269 			(struct filter_control *)kcontrol->private_value;
1270 
1271 	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1272 	uinfo->count = fc->count;
1273 	uinfo->value.integer.min = fc->min;
1274 	uinfo->value.integer.max = fc->max;
1275 
1276 	return 0;
1277 }
1278 
filter_control_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1279 static int filter_control_get(struct snd_kcontrol *kcontrol,
1280 			struct snd_ctl_elem_value *ucontrol)
1281 {
1282 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1283 	struct ab8500_codec_drvdata *drvdata = snd_soc_component_get_drvdata(component);
1284 	struct filter_control *fc =
1285 			(struct filter_control *)kcontrol->private_value;
1286 	unsigned int i;
1287 
1288 	mutex_lock(&drvdata->ctrl_lock);
1289 	for (i = 0; i < fc->count; i++)
1290 		ucontrol->value.integer.value[i] = fc->value[i];
1291 	mutex_unlock(&drvdata->ctrl_lock);
1292 
1293 	return 0;
1294 }
1295 
filter_control_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1296 static int filter_control_put(struct snd_kcontrol *kcontrol,
1297 		struct snd_ctl_elem_value *ucontrol)
1298 {
1299 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1300 	struct ab8500_codec_drvdata *drvdata = snd_soc_component_get_drvdata(component);
1301 	struct filter_control *fc =
1302 			(struct filter_control *)kcontrol->private_value;
1303 	unsigned int i;
1304 
1305 	mutex_lock(&drvdata->ctrl_lock);
1306 	for (i = 0; i < fc->count; i++)
1307 		fc->value[i] = ucontrol->value.integer.value[i];
1308 	mutex_unlock(&drvdata->ctrl_lock);
1309 
1310 	return 0;
1311 }
1312 
1313 /*
1314  * Controls - Non-DAPM ASoC
1315  */
1316 
1317 static DECLARE_TLV_DB_SCALE(adx_dig_gain_tlv, -3200, 100, 1);
1318 /* -32dB = Mute */
1319 
1320 static DECLARE_TLV_DB_SCALE(dax_dig_gain_tlv, -6300, 100, 1);
1321 /* -63dB = Mute */
1322 
1323 static DECLARE_TLV_DB_SCALE(hs_ear_dig_gain_tlv, -100, 100, 1);
1324 /* -1dB = Mute */
1325 
1326 static const DECLARE_TLV_DB_RANGE(hs_gain_tlv,
1327 	0, 3, TLV_DB_SCALE_ITEM(-3200, 400, 0),
1328 	4, 15, TLV_DB_SCALE_ITEM(-1800, 200, 0)
1329 );
1330 
1331 static DECLARE_TLV_DB_SCALE(mic_gain_tlv, 0, 100, 0);
1332 
1333 static DECLARE_TLV_DB_SCALE(lin_gain_tlv, -1000, 200, 0);
1334 
1335 static DECLARE_TLV_DB_SCALE(lin2hs_gain_tlv, -3800, 200, 1);
1336 /* -38dB = Mute */
1337 
1338 static const char * const enum_hsfadspeed[] = {"2ms", "0.5ms", "10.6ms",
1339 					"5ms"};
1340 static SOC_ENUM_SINGLE_DECL(soc_enum_hsfadspeed,
1341 	AB8500_DIGMICCONF, AB8500_DIGMICCONF_HSFADSPEED, enum_hsfadspeed);
1342 
1343 static const char * const enum_envdetthre[] = {
1344 	"250mV", "300mV", "350mV", "400mV",
1345 	"450mV", "500mV", "550mV", "600mV",
1346 	"650mV", "700mV", "750mV", "800mV",
1347 	"850mV", "900mV", "950mV", "1.00V" };
1348 static SOC_ENUM_SINGLE_DECL(soc_enum_envdeththre,
1349 	AB8500_ENVCPCONF, AB8500_ENVCPCONF_ENVDETHTHRE, enum_envdetthre);
1350 static SOC_ENUM_SINGLE_DECL(soc_enum_envdetlthre,
1351 	AB8500_ENVCPCONF, AB8500_ENVCPCONF_ENVDETLTHRE, enum_envdetthre);
1352 static const char * const enum_envdettime[] = {
1353 	"26.6us", "53.2us", "106us",  "213us",
1354 	"426us",  "851us",  "1.70ms", "3.40ms",
1355 	"6.81ms", "13.6ms", "27.2ms", "54.5ms",
1356 	"109ms",  "218ms",  "436ms",  "872ms" };
1357 static SOC_ENUM_SINGLE_DECL(soc_enum_envdettime,
1358 	AB8500_SIGENVCONF, AB8500_SIGENVCONF_ENVDETTIME, enum_envdettime);
1359 
1360 static const char * const enum_sinc31[] = {"Sinc 3", "Sinc 1"};
1361 static SOC_ENUM_SINGLE_DECL(soc_enum_hsesinc, AB8500_HSLEARDIGGAIN,
1362 			AB8500_HSLEARDIGGAIN_HSSINC1, enum_sinc31);
1363 
1364 static const char * const enum_fadespeed[] = {"1ms", "4ms", "8ms", "16ms"};
1365 static SOC_ENUM_SINGLE_DECL(soc_enum_fadespeed, AB8500_HSRDIGGAIN,
1366 			AB8500_HSRDIGGAIN_FADESPEED, enum_fadespeed);
1367 
1368 /* Earpiece */
1369 
1370 static const char * const enum_lowpow[] = {"Normal", "Low Power"};
1371 static SOC_ENUM_SINGLE_DECL(soc_enum_eardaclowpow, AB8500_ANACONF1,
1372 			AB8500_ANACONF1_EARDACLOWPOW, enum_lowpow);
1373 static SOC_ENUM_SINGLE_DECL(soc_enum_eardrvlowpow, AB8500_ANACONF1,
1374 			AB8500_ANACONF1_EARDRVLOWPOW, enum_lowpow);
1375 
1376 static const char * const enum_av_mode[] = {"Audio", "Voice"};
1377 static SOC_ENUM_DOUBLE_DECL(soc_enum_ad12voice, AB8500_ADFILTCONF,
1378 	AB8500_ADFILTCONF_AD1VOICE, AB8500_ADFILTCONF_AD2VOICE, enum_av_mode);
1379 static SOC_ENUM_DOUBLE_DECL(soc_enum_ad34voice, AB8500_ADFILTCONF,
1380 	AB8500_ADFILTCONF_AD3VOICE, AB8500_ADFILTCONF_AD4VOICE, enum_av_mode);
1381 
1382 /* DA */
1383 
1384 static SOC_ENUM_SINGLE_DECL(soc_enum_da12voice,
1385 			AB8500_DASLOTCONF1, AB8500_DASLOTCONF1_DA12VOICE,
1386 			enum_av_mode);
1387 static SOC_ENUM_SINGLE_DECL(soc_enum_da34voice,
1388 			AB8500_DASLOTCONF3, AB8500_DASLOTCONF3_DA34VOICE,
1389 			enum_av_mode);
1390 static SOC_ENUM_SINGLE_DECL(soc_enum_da56voice,
1391 			AB8500_DASLOTCONF5, AB8500_DASLOTCONF5_DA56VOICE,
1392 			enum_av_mode);
1393 
1394 static const char * const enum_da2hslr[] = {"Sidetone", "Audio Path"};
1395 static SOC_ENUM_DOUBLE_DECL(soc_enum_da2hslr, AB8500_DIGMULTCONF1,
1396 			AB8500_DIGMULTCONF1_DATOHSLEN,
1397 			AB8500_DIGMULTCONF1_DATOHSREN, enum_da2hslr);
1398 
1399 static const char * const enum_sinc53[] = {"Sinc 5", "Sinc 3"};
1400 static SOC_ENUM_DOUBLE_DECL(soc_enum_dmic12sinc, AB8500_DMICFILTCONF,
1401 			AB8500_DMICFILTCONF_DMIC1SINC3,
1402 			AB8500_DMICFILTCONF_DMIC2SINC3, enum_sinc53);
1403 static SOC_ENUM_DOUBLE_DECL(soc_enum_dmic34sinc, AB8500_DMICFILTCONF,
1404 			AB8500_DMICFILTCONF_DMIC3SINC3,
1405 			AB8500_DMICFILTCONF_DMIC4SINC3, enum_sinc53);
1406 static SOC_ENUM_DOUBLE_DECL(soc_enum_dmic56sinc, AB8500_DMICFILTCONF,
1407 			AB8500_DMICFILTCONF_DMIC5SINC3,
1408 			AB8500_DMICFILTCONF_DMIC6SINC3, enum_sinc53);
1409 
1410 /* Digital interface - DA from slot mapping */
1411 static const char * const enum_da_from_slot_map[] = {"SLOT0",
1412 					"SLOT1",
1413 					"SLOT2",
1414 					"SLOT3",
1415 					"SLOT4",
1416 					"SLOT5",
1417 					"SLOT6",
1418 					"SLOT7",
1419 					"SLOT8",
1420 					"SLOT9",
1421 					"SLOT10",
1422 					"SLOT11",
1423 					"SLOT12",
1424 					"SLOT13",
1425 					"SLOT14",
1426 					"SLOT15",
1427 					"SLOT16",
1428 					"SLOT17",
1429 					"SLOT18",
1430 					"SLOT19",
1431 					"SLOT20",
1432 					"SLOT21",
1433 					"SLOT22",
1434 					"SLOT23",
1435 					"SLOT24",
1436 					"SLOT25",
1437 					"SLOT26",
1438 					"SLOT27",
1439 					"SLOT28",
1440 					"SLOT29",
1441 					"SLOT30",
1442 					"SLOT31"};
1443 static SOC_ENUM_SINGLE_DECL(soc_enum_da1slotmap,
1444 			AB8500_DASLOTCONF1, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1445 			enum_da_from_slot_map);
1446 static SOC_ENUM_SINGLE_DECL(soc_enum_da2slotmap,
1447 			AB8500_DASLOTCONF2, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1448 			enum_da_from_slot_map);
1449 static SOC_ENUM_SINGLE_DECL(soc_enum_da3slotmap,
1450 			AB8500_DASLOTCONF3, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1451 			enum_da_from_slot_map);
1452 static SOC_ENUM_SINGLE_DECL(soc_enum_da4slotmap,
1453 			AB8500_DASLOTCONF4, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1454 			enum_da_from_slot_map);
1455 static SOC_ENUM_SINGLE_DECL(soc_enum_da5slotmap,
1456 			AB8500_DASLOTCONF5, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1457 			enum_da_from_slot_map);
1458 static SOC_ENUM_SINGLE_DECL(soc_enum_da6slotmap,
1459 			AB8500_DASLOTCONF6, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1460 			enum_da_from_slot_map);
1461 static SOC_ENUM_SINGLE_DECL(soc_enum_da7slotmap,
1462 			AB8500_DASLOTCONF7, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1463 			enum_da_from_slot_map);
1464 static SOC_ENUM_SINGLE_DECL(soc_enum_da8slotmap,
1465 			AB8500_DASLOTCONF8, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1466 			enum_da_from_slot_map);
1467 
1468 /* Digital interface - AD to slot mapping */
1469 static const char * const enum_ad_to_slot_map[] = {"AD_OUT1",
1470 					"AD_OUT2",
1471 					"AD_OUT3",
1472 					"AD_OUT4",
1473 					"AD_OUT5",
1474 					"AD_OUT6",
1475 					"AD_OUT7",
1476 					"AD_OUT8",
1477 					"zeroes",
1478 					"zeroes",
1479 					"zeroes",
1480 					"zeroes",
1481 					"tristate",
1482 					"tristate",
1483 					"tristate",
1484 					"tristate"};
1485 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot0map,
1486 			AB8500_ADSLOTSEL1, AB8500_ADSLOTSELX_EVEN_SHIFT,
1487 			enum_ad_to_slot_map);
1488 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot1map,
1489 			AB8500_ADSLOTSEL1, AB8500_ADSLOTSELX_ODD_SHIFT,
1490 			enum_ad_to_slot_map);
1491 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot2map,
1492 			AB8500_ADSLOTSEL2, AB8500_ADSLOTSELX_EVEN_SHIFT,
1493 			enum_ad_to_slot_map);
1494 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot3map,
1495 			AB8500_ADSLOTSEL2, AB8500_ADSLOTSELX_ODD_SHIFT,
1496 			enum_ad_to_slot_map);
1497 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot4map,
1498 			AB8500_ADSLOTSEL3, AB8500_ADSLOTSELX_EVEN_SHIFT,
1499 			enum_ad_to_slot_map);
1500 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot5map,
1501 			AB8500_ADSLOTSEL3, AB8500_ADSLOTSELX_ODD_SHIFT,
1502 			enum_ad_to_slot_map);
1503 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot6map,
1504 			AB8500_ADSLOTSEL4, AB8500_ADSLOTSELX_EVEN_SHIFT,
1505 			enum_ad_to_slot_map);
1506 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot7map,
1507 			AB8500_ADSLOTSEL4, AB8500_ADSLOTSELX_ODD_SHIFT,
1508 			enum_ad_to_slot_map);
1509 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot8map,
1510 			AB8500_ADSLOTSEL5, AB8500_ADSLOTSELX_EVEN_SHIFT,
1511 			enum_ad_to_slot_map);
1512 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot9map,
1513 			AB8500_ADSLOTSEL5, AB8500_ADSLOTSELX_ODD_SHIFT,
1514 			enum_ad_to_slot_map);
1515 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot10map,
1516 			AB8500_ADSLOTSEL6, AB8500_ADSLOTSELX_EVEN_SHIFT,
1517 			enum_ad_to_slot_map);
1518 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot11map,
1519 			AB8500_ADSLOTSEL6, AB8500_ADSLOTSELX_ODD_SHIFT,
1520 			enum_ad_to_slot_map);
1521 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot12map,
1522 			AB8500_ADSLOTSEL7, AB8500_ADSLOTSELX_EVEN_SHIFT,
1523 			enum_ad_to_slot_map);
1524 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot13map,
1525 			AB8500_ADSLOTSEL7, AB8500_ADSLOTSELX_ODD_SHIFT,
1526 			enum_ad_to_slot_map);
1527 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot14map,
1528 			AB8500_ADSLOTSEL8, AB8500_ADSLOTSELX_EVEN_SHIFT,
1529 			enum_ad_to_slot_map);
1530 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot15map,
1531 			AB8500_ADSLOTSEL8, AB8500_ADSLOTSELX_ODD_SHIFT,
1532 			enum_ad_to_slot_map);
1533 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot16map,
1534 			AB8500_ADSLOTSEL9, AB8500_ADSLOTSELX_EVEN_SHIFT,
1535 			enum_ad_to_slot_map);
1536 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot17map,
1537 			AB8500_ADSLOTSEL9, AB8500_ADSLOTSELX_ODD_SHIFT,
1538 			enum_ad_to_slot_map);
1539 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot18map,
1540 			AB8500_ADSLOTSEL10, AB8500_ADSLOTSELX_EVEN_SHIFT,
1541 			enum_ad_to_slot_map);
1542 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot19map,
1543 			AB8500_ADSLOTSEL10, AB8500_ADSLOTSELX_ODD_SHIFT,
1544 			enum_ad_to_slot_map);
1545 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot20map,
1546 			AB8500_ADSLOTSEL11, AB8500_ADSLOTSELX_EVEN_SHIFT,
1547 			enum_ad_to_slot_map);
1548 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot21map,
1549 			AB8500_ADSLOTSEL11, AB8500_ADSLOTSELX_ODD_SHIFT,
1550 			enum_ad_to_slot_map);
1551 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot22map,
1552 			AB8500_ADSLOTSEL12, AB8500_ADSLOTSELX_EVEN_SHIFT,
1553 			enum_ad_to_slot_map);
1554 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot23map,
1555 			AB8500_ADSLOTSEL12, AB8500_ADSLOTSELX_ODD_SHIFT,
1556 			enum_ad_to_slot_map);
1557 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot24map,
1558 			AB8500_ADSLOTSEL13, AB8500_ADSLOTSELX_EVEN_SHIFT,
1559 			enum_ad_to_slot_map);
1560 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot25map,
1561 			AB8500_ADSLOTSEL13, AB8500_ADSLOTSELX_ODD_SHIFT,
1562 			enum_ad_to_slot_map);
1563 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot26map,
1564 			AB8500_ADSLOTSEL14, AB8500_ADSLOTSELX_EVEN_SHIFT,
1565 			enum_ad_to_slot_map);
1566 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot27map,
1567 			AB8500_ADSLOTSEL14, AB8500_ADSLOTSELX_ODD_SHIFT,
1568 			enum_ad_to_slot_map);
1569 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot28map,
1570 			AB8500_ADSLOTSEL15, AB8500_ADSLOTSELX_EVEN_SHIFT,
1571 			enum_ad_to_slot_map);
1572 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot29map,
1573 			AB8500_ADSLOTSEL15, AB8500_ADSLOTSELX_ODD_SHIFT,
1574 			enum_ad_to_slot_map);
1575 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot30map,
1576 			AB8500_ADSLOTSEL16, AB8500_ADSLOTSELX_EVEN_SHIFT,
1577 			enum_ad_to_slot_map);
1578 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot31map,
1579 			AB8500_ADSLOTSEL16, AB8500_ADSLOTSELX_ODD_SHIFT,
1580 			enum_ad_to_slot_map);
1581 
1582 /* Digital interface - Burst mode */
1583 static const char * const enum_mask[] = {"Unmasked", "Masked"};
1584 static SOC_ENUM_SINGLE_DECL(soc_enum_bfifomask,
1585 			AB8500_FIFOCONF1, AB8500_FIFOCONF1_BFIFOMASK,
1586 			enum_mask);
1587 static const char * const enum_bitclk0[] = {"19_2_MHz", "38_4_MHz"};
1588 static SOC_ENUM_SINGLE_DECL(soc_enum_bfifo19m2,
1589 			AB8500_FIFOCONF1, AB8500_FIFOCONF1_BFIFO19M2,
1590 			enum_bitclk0);
1591 static const char * const enum_slavemaster[] = {"Slave", "Master"};
1592 static SOC_ENUM_SINGLE_DECL(soc_enum_bfifomast,
1593 			AB8500_FIFOCONF3, AB8500_FIFOCONF3_BFIFOMAST_SHIFT,
1594 			enum_slavemaster);
1595 
1596 /* Sidetone */
1597 static SOC_ENUM_SINGLE_EXT_DECL(soc_enum_sidstate, enum_sid_state);
1598 
1599 /* ANC */
1600 static SOC_ENUM_SINGLE_EXT_DECL(soc_enum_ancstate, enum_anc_state);
1601 
1602 static struct snd_kcontrol_new ab8500_ctrls[] = {
1603 	/* Charge pump */
1604 	SOC_ENUM("Charge Pump High Threshold For Low Voltage",
1605 		soc_enum_envdeththre),
1606 	SOC_ENUM("Charge Pump Low Threshold For Low Voltage",
1607 		soc_enum_envdetlthre),
1608 	SOC_SINGLE("Charge Pump Envelope Detection Switch",
1609 		AB8500_SIGENVCONF, AB8500_SIGENVCONF_ENVDETCPEN,
1610 		1, 0),
1611 	SOC_ENUM("Charge Pump Envelope Detection Decay Time",
1612 		soc_enum_envdettime),
1613 
1614 	/* Headset */
1615 	SOC_ENUM("Headset Mode", soc_enum_da12voice),
1616 	SOC_SINGLE("Headset High Pass Switch",
1617 		AB8500_ANACONF1, AB8500_ANACONF1_HSHPEN,
1618 		1, 0),
1619 	SOC_SINGLE("Headset Low Power Switch",
1620 		AB8500_ANACONF1, AB8500_ANACONF1_HSLOWPOW,
1621 		1, 0),
1622 	SOC_SINGLE("Headset DAC Low Power Switch",
1623 		AB8500_ANACONF1, AB8500_ANACONF1_DACLOWPOW1,
1624 		1, 0),
1625 	SOC_SINGLE("Headset DAC Drv Low Power Switch",
1626 		AB8500_ANACONF1, AB8500_ANACONF1_DACLOWPOW0,
1627 		1, 0),
1628 	SOC_ENUM("Headset Fade Speed", soc_enum_hsfadspeed),
1629 	SOC_ENUM("Headset Source", soc_enum_da2hslr),
1630 	SOC_ENUM("Headset Filter", soc_enum_hsesinc),
1631 	SOC_DOUBLE_R_TLV("Headset Master Volume",
1632 		AB8500_DADIGGAIN1, AB8500_DADIGGAIN2,
1633 		0, AB8500_DADIGGAINX_DAXGAIN_MAX, 1, dax_dig_gain_tlv),
1634 	SOC_DOUBLE_R_TLV("Headset Digital Volume",
1635 		AB8500_HSLEARDIGGAIN, AB8500_HSRDIGGAIN,
1636 		0, AB8500_HSLEARDIGGAIN_HSLDGAIN_MAX, 1, hs_ear_dig_gain_tlv),
1637 	SOC_DOUBLE_TLV("Headset Volume",
1638 		AB8500_ANAGAIN3,
1639 		AB8500_ANAGAIN3_HSLGAIN, AB8500_ANAGAIN3_HSRGAIN,
1640 		AB8500_ANAGAIN3_HSXGAIN_MAX, 1, hs_gain_tlv),
1641 
1642 	/* Earpiece */
1643 	SOC_ENUM("Earpiece DAC Mode",
1644 		soc_enum_eardaclowpow),
1645 	SOC_ENUM("Earpiece DAC Drv Mode",
1646 		soc_enum_eardrvlowpow),
1647 
1648 	/* HandsFree */
1649 	SOC_ENUM("HF Mode", soc_enum_da34voice),
1650 	SOC_SINGLE("HF and Headset Swap Switch",
1651 		AB8500_DASLOTCONF1, AB8500_DASLOTCONF1_SWAPDA12_34,
1652 		1, 0),
1653 	SOC_DOUBLE("HF Low EMI Mode Switch",
1654 		AB8500_CLASSDCONF1,
1655 		AB8500_CLASSDCONF1_HFLSWAPEN, AB8500_CLASSDCONF1_HFRSWAPEN,
1656 		1, 0),
1657 	SOC_DOUBLE("HF FIR Bypass Switch",
1658 		AB8500_CLASSDCONF2,
1659 		AB8500_CLASSDCONF2_FIRBYP0, AB8500_CLASSDCONF2_FIRBYP1,
1660 		1, 0),
1661 	SOC_DOUBLE("HF High Volume Switch",
1662 		AB8500_CLASSDCONF2,
1663 		AB8500_CLASSDCONF2_HIGHVOLEN0, AB8500_CLASSDCONF2_HIGHVOLEN1,
1664 		1, 0),
1665 	SOC_SINGLE("HF L and R Bridge Switch",
1666 		AB8500_CLASSDCONF1, AB8500_CLASSDCONF1_PARLHF,
1667 		1, 0),
1668 	SOC_DOUBLE_R_TLV("HF Master Volume",
1669 		AB8500_DADIGGAIN3, AB8500_DADIGGAIN4,
1670 		0, AB8500_DADIGGAINX_DAXGAIN_MAX, 1, dax_dig_gain_tlv),
1671 
1672 	/* Vibra */
1673 	SOC_DOUBLE("Vibra High Volume Switch",
1674 		AB8500_CLASSDCONF2,
1675 		AB8500_CLASSDCONF2_HIGHVOLEN2, AB8500_CLASSDCONF2_HIGHVOLEN3,
1676 		1, 0),
1677 	SOC_DOUBLE("Vibra Low EMI Mode Switch",
1678 		AB8500_CLASSDCONF1,
1679 		AB8500_CLASSDCONF1_VIB1SWAPEN, AB8500_CLASSDCONF1_VIB2SWAPEN,
1680 		1, 0),
1681 	SOC_DOUBLE("Vibra FIR Bypass Switch",
1682 		AB8500_CLASSDCONF2,
1683 		AB8500_CLASSDCONF2_FIRBYP2, AB8500_CLASSDCONF2_FIRBYP3,
1684 		1, 0),
1685 	SOC_ENUM("Vibra Mode", soc_enum_da56voice),
1686 	SOC_DOUBLE_R("Vibra PWM Duty Cycle N",
1687 		AB8500_PWMGENCONF3, AB8500_PWMGENCONF5,
1688 		AB8500_PWMGENCONFX_PWMVIBXDUTCYC,
1689 		AB8500_PWMGENCONFX_PWMVIBXDUTCYC_MAX, 0),
1690 	SOC_DOUBLE_R("Vibra PWM Duty Cycle P",
1691 		AB8500_PWMGENCONF2, AB8500_PWMGENCONF4,
1692 		AB8500_PWMGENCONFX_PWMVIBXDUTCYC,
1693 		AB8500_PWMGENCONFX_PWMVIBXDUTCYC_MAX, 0),
1694 	SOC_SINGLE("Vibra 1 and 2 Bridge Switch",
1695 		AB8500_CLASSDCONF1, AB8500_CLASSDCONF1_PARLVIB,
1696 		1, 0),
1697 	SOC_DOUBLE_R_TLV("Vibra Master Volume",
1698 		AB8500_DADIGGAIN5, AB8500_DADIGGAIN6,
1699 		0, AB8500_DADIGGAINX_DAXGAIN_MAX, 1, dax_dig_gain_tlv),
1700 
1701 	/* HandsFree, Vibra */
1702 	SOC_SINGLE("ClassD High Pass Volume",
1703 		AB8500_CLASSDCONF3, AB8500_CLASSDCONF3_DITHHPGAIN,
1704 		AB8500_CLASSDCONF3_DITHHPGAIN_MAX, 0),
1705 	SOC_SINGLE("ClassD White Volume",
1706 		AB8500_CLASSDCONF3, AB8500_CLASSDCONF3_DITHWGAIN,
1707 		AB8500_CLASSDCONF3_DITHWGAIN_MAX, 0),
1708 
1709 	/* Mic 1, Mic 2, LineIn */
1710 	SOC_DOUBLE_R_TLV("Mic Master Volume",
1711 		AB8500_ADDIGGAIN3, AB8500_ADDIGGAIN4,
1712 		0, AB8500_ADDIGGAINX_ADXGAIN_MAX, 1, adx_dig_gain_tlv),
1713 
1714 	/* Mic 1 */
1715 	SOC_SINGLE_TLV("Mic 1",
1716 		AB8500_ANAGAIN1,
1717 		AB8500_ANAGAINX_MICXGAIN,
1718 		AB8500_ANAGAINX_MICXGAIN_MAX, 0, mic_gain_tlv),
1719 	SOC_SINGLE("Mic 1 Low Power Switch",
1720 		AB8500_ANAGAIN1, AB8500_ANAGAINX_LOWPOWMICX,
1721 		1, 0),
1722 
1723 	/* Mic 2 */
1724 	SOC_DOUBLE("Mic High Pass Switch",
1725 		AB8500_ADFILTCONF,
1726 		AB8500_ADFILTCONF_AD3NH, AB8500_ADFILTCONF_AD4NH,
1727 		1, 1),
1728 	SOC_ENUM("Mic Mode", soc_enum_ad34voice),
1729 	SOC_ENUM("Mic Filter", soc_enum_dmic34sinc),
1730 	SOC_SINGLE_TLV("Mic 2",
1731 		AB8500_ANAGAIN2,
1732 		AB8500_ANAGAINX_MICXGAIN,
1733 		AB8500_ANAGAINX_MICXGAIN_MAX, 0, mic_gain_tlv),
1734 	SOC_SINGLE("Mic 2 Low Power Switch",
1735 		AB8500_ANAGAIN2, AB8500_ANAGAINX_LOWPOWMICX,
1736 		1, 0),
1737 
1738 	/* LineIn */
1739 	SOC_DOUBLE("LineIn High Pass Switch",
1740 		AB8500_ADFILTCONF,
1741 		AB8500_ADFILTCONF_AD1NH, AB8500_ADFILTCONF_AD2NH,
1742 		1, 1),
1743 	SOC_ENUM("LineIn Filter", soc_enum_dmic12sinc),
1744 	SOC_ENUM("LineIn Mode", soc_enum_ad12voice),
1745 	SOC_DOUBLE_R_TLV("LineIn Master Volume",
1746 		AB8500_ADDIGGAIN1, AB8500_ADDIGGAIN2,
1747 		0, AB8500_ADDIGGAINX_ADXGAIN_MAX, 1, adx_dig_gain_tlv),
1748 	SOC_DOUBLE_TLV("LineIn",
1749 		AB8500_ANAGAIN4,
1750 		AB8500_ANAGAIN4_LINLGAIN, AB8500_ANAGAIN4_LINRGAIN,
1751 		AB8500_ANAGAIN4_LINXGAIN_MAX, 0, lin_gain_tlv),
1752 	SOC_DOUBLE_R_TLV("LineIn to Headset Volume",
1753 		AB8500_DIGLINHSLGAIN, AB8500_DIGLINHSRGAIN,
1754 		AB8500_DIGLINHSXGAIN_LINTOHSXGAIN,
1755 		AB8500_DIGLINHSXGAIN_LINTOHSXGAIN_MAX,
1756 		1, lin2hs_gain_tlv),
1757 
1758 	/* DMic */
1759 	SOC_ENUM("DMic Filter", soc_enum_dmic56sinc),
1760 	SOC_DOUBLE_R_TLV("DMic Master Volume",
1761 		AB8500_ADDIGGAIN5, AB8500_ADDIGGAIN6,
1762 		0, AB8500_ADDIGGAINX_ADXGAIN_MAX, 1, adx_dig_gain_tlv),
1763 
1764 	/* Digital gains */
1765 	SOC_ENUM("Digital Gain Fade Speed", soc_enum_fadespeed),
1766 
1767 	/* Analog loopback */
1768 	SOC_DOUBLE_R_TLV("Analog Loopback Volume",
1769 		AB8500_ADDIGLOOPGAIN1, AB8500_ADDIGLOOPGAIN2,
1770 		0, AB8500_ADDIGLOOPGAINX_ADXLBGAIN_MAX, 1, dax_dig_gain_tlv),
1771 
1772 	/* Digital interface - DA from slot mapping */
1773 	SOC_ENUM("Digital Interface DA 1 From Slot Map", soc_enum_da1slotmap),
1774 	SOC_ENUM("Digital Interface DA 2 From Slot Map", soc_enum_da2slotmap),
1775 	SOC_ENUM("Digital Interface DA 3 From Slot Map", soc_enum_da3slotmap),
1776 	SOC_ENUM("Digital Interface DA 4 From Slot Map", soc_enum_da4slotmap),
1777 	SOC_ENUM("Digital Interface DA 5 From Slot Map", soc_enum_da5slotmap),
1778 	SOC_ENUM("Digital Interface DA 6 From Slot Map", soc_enum_da6slotmap),
1779 	SOC_ENUM("Digital Interface DA 7 From Slot Map", soc_enum_da7slotmap),
1780 	SOC_ENUM("Digital Interface DA 8 From Slot Map", soc_enum_da8slotmap),
1781 
1782 	/* Digital interface - AD to slot mapping */
1783 	SOC_ENUM("Digital Interface AD To Slot 0 Map", soc_enum_adslot0map),
1784 	SOC_ENUM("Digital Interface AD To Slot 1 Map", soc_enum_adslot1map),
1785 	SOC_ENUM("Digital Interface AD To Slot 2 Map", soc_enum_adslot2map),
1786 	SOC_ENUM("Digital Interface AD To Slot 3 Map", soc_enum_adslot3map),
1787 	SOC_ENUM("Digital Interface AD To Slot 4 Map", soc_enum_adslot4map),
1788 	SOC_ENUM("Digital Interface AD To Slot 5 Map", soc_enum_adslot5map),
1789 	SOC_ENUM("Digital Interface AD To Slot 6 Map", soc_enum_adslot6map),
1790 	SOC_ENUM("Digital Interface AD To Slot 7 Map", soc_enum_adslot7map),
1791 	SOC_ENUM("Digital Interface AD To Slot 8 Map", soc_enum_adslot8map),
1792 	SOC_ENUM("Digital Interface AD To Slot 9 Map", soc_enum_adslot9map),
1793 	SOC_ENUM("Digital Interface AD To Slot 10 Map", soc_enum_adslot10map),
1794 	SOC_ENUM("Digital Interface AD To Slot 11 Map", soc_enum_adslot11map),
1795 	SOC_ENUM("Digital Interface AD To Slot 12 Map", soc_enum_adslot12map),
1796 	SOC_ENUM("Digital Interface AD To Slot 13 Map", soc_enum_adslot13map),
1797 	SOC_ENUM("Digital Interface AD To Slot 14 Map", soc_enum_adslot14map),
1798 	SOC_ENUM("Digital Interface AD To Slot 15 Map", soc_enum_adslot15map),
1799 	SOC_ENUM("Digital Interface AD To Slot 16 Map", soc_enum_adslot16map),
1800 	SOC_ENUM("Digital Interface AD To Slot 17 Map", soc_enum_adslot17map),
1801 	SOC_ENUM("Digital Interface AD To Slot 18 Map", soc_enum_adslot18map),
1802 	SOC_ENUM("Digital Interface AD To Slot 19 Map", soc_enum_adslot19map),
1803 	SOC_ENUM("Digital Interface AD To Slot 20 Map", soc_enum_adslot20map),
1804 	SOC_ENUM("Digital Interface AD To Slot 21 Map", soc_enum_adslot21map),
1805 	SOC_ENUM("Digital Interface AD To Slot 22 Map", soc_enum_adslot22map),
1806 	SOC_ENUM("Digital Interface AD To Slot 23 Map", soc_enum_adslot23map),
1807 	SOC_ENUM("Digital Interface AD To Slot 24 Map", soc_enum_adslot24map),
1808 	SOC_ENUM("Digital Interface AD To Slot 25 Map", soc_enum_adslot25map),
1809 	SOC_ENUM("Digital Interface AD To Slot 26 Map", soc_enum_adslot26map),
1810 	SOC_ENUM("Digital Interface AD To Slot 27 Map", soc_enum_adslot27map),
1811 	SOC_ENUM("Digital Interface AD To Slot 28 Map", soc_enum_adslot28map),
1812 	SOC_ENUM("Digital Interface AD To Slot 29 Map", soc_enum_adslot29map),
1813 	SOC_ENUM("Digital Interface AD To Slot 30 Map", soc_enum_adslot30map),
1814 	SOC_ENUM("Digital Interface AD To Slot 31 Map", soc_enum_adslot31map),
1815 
1816 	/* Digital interface - Loopback */
1817 	SOC_SINGLE("Digital Interface AD 1 Loopback Switch",
1818 		AB8500_DASLOTCONF1, AB8500_DASLOTCONF1_DAI7TOADO1,
1819 		1, 0),
1820 	SOC_SINGLE("Digital Interface AD 2 Loopback Switch",
1821 		AB8500_DASLOTCONF2, AB8500_DASLOTCONF2_DAI8TOADO2,
1822 		1, 0),
1823 	SOC_SINGLE("Digital Interface AD 3 Loopback Switch",
1824 		AB8500_DASLOTCONF3, AB8500_DASLOTCONF3_DAI7TOADO3,
1825 		1, 0),
1826 	SOC_SINGLE("Digital Interface AD 4 Loopback Switch",
1827 		AB8500_DASLOTCONF4, AB8500_DASLOTCONF4_DAI8TOADO4,
1828 		1, 0),
1829 	SOC_SINGLE("Digital Interface AD 5 Loopback Switch",
1830 		AB8500_DASLOTCONF5, AB8500_DASLOTCONF5_DAI7TOADO5,
1831 		1, 0),
1832 	SOC_SINGLE("Digital Interface AD 6 Loopback Switch",
1833 		AB8500_DASLOTCONF6, AB8500_DASLOTCONF6_DAI8TOADO6,
1834 		1, 0),
1835 	SOC_SINGLE("Digital Interface AD 7 Loopback Switch",
1836 		AB8500_DASLOTCONF7, AB8500_DASLOTCONF7_DAI8TOADO7,
1837 		1, 0),
1838 	SOC_SINGLE("Digital Interface AD 8 Loopback Switch",
1839 		AB8500_DASLOTCONF8, AB8500_DASLOTCONF8_DAI7TOADO8,
1840 		1, 0),
1841 
1842 	/* Digital interface - Burst FIFO */
1843 	SOC_SINGLE("Digital Interface 0 FIFO Enable Switch",
1844 		AB8500_DIGIFCONF3, AB8500_DIGIFCONF3_IF0BFIFOEN,
1845 		1, 0),
1846 	SOC_ENUM("Burst FIFO Mask", soc_enum_bfifomask),
1847 	SOC_ENUM("Burst FIFO Bit-clock Frequency", soc_enum_bfifo19m2),
1848 	SOC_SINGLE("Burst FIFO Threshold",
1849 		AB8500_FIFOCONF1, AB8500_FIFOCONF1_BFIFOINT_SHIFT,
1850 		AB8500_FIFOCONF1_BFIFOINT_MAX, 0),
1851 	SOC_SINGLE("Burst FIFO Length",
1852 		AB8500_FIFOCONF2, AB8500_FIFOCONF2_BFIFOTX_SHIFT,
1853 		AB8500_FIFOCONF2_BFIFOTX_MAX, 0),
1854 	SOC_SINGLE("Burst FIFO EOS Extra Slots",
1855 		AB8500_FIFOCONF3, AB8500_FIFOCONF3_BFIFOEXSL_SHIFT,
1856 		AB8500_FIFOCONF3_BFIFOEXSL_MAX, 0),
1857 	SOC_SINGLE("Burst FIFO FS Extra Bit-clocks",
1858 		AB8500_FIFOCONF3, AB8500_FIFOCONF3_PREBITCLK0_SHIFT,
1859 		AB8500_FIFOCONF3_PREBITCLK0_MAX, 0),
1860 	SOC_ENUM("Burst FIFO Interface Mode", soc_enum_bfifomast),
1861 
1862 	SOC_SINGLE("Burst FIFO Interface Switch",
1863 		AB8500_FIFOCONF3, AB8500_FIFOCONF3_BFIFORUN_SHIFT,
1864 		1, 0),
1865 	SOC_SINGLE("Burst FIFO Switch Frame Number",
1866 		AB8500_FIFOCONF4, AB8500_FIFOCONF4_BFIFOFRAMSW_SHIFT,
1867 		AB8500_FIFOCONF4_BFIFOFRAMSW_MAX, 0),
1868 	SOC_SINGLE("Burst FIFO Wake Up Delay",
1869 		AB8500_FIFOCONF5, AB8500_FIFOCONF5_BFIFOWAKEUP_SHIFT,
1870 		AB8500_FIFOCONF5_BFIFOWAKEUP_MAX, 0),
1871 	SOC_SINGLE("Burst FIFO Samples In FIFO",
1872 		AB8500_FIFOCONF6, AB8500_FIFOCONF6_BFIFOSAMPLE_SHIFT,
1873 		AB8500_FIFOCONF6_BFIFOSAMPLE_MAX, 0),
1874 
1875 	/* ANC */
1876 	SOC_ENUM_EXT("ANC Status", soc_enum_ancstate,
1877 		anc_status_control_get, anc_status_control_put),
1878 	SOC_SINGLE_XR_SX("ANC Warp Delay Shift",
1879 		AB8500_ANCCONF2, 1, AB8500_ANCCONF2_SHIFT,
1880 		AB8500_ANCCONF2_MIN, AB8500_ANCCONF2_MAX, 0),
1881 	SOC_SINGLE_XR_SX("ANC FIR Output Shift",
1882 		AB8500_ANCCONF3, 1, AB8500_ANCCONF3_SHIFT,
1883 		AB8500_ANCCONF3_MIN, AB8500_ANCCONF3_MAX, 0),
1884 	SOC_SINGLE_XR_SX("ANC IIR Output Shift",
1885 		AB8500_ANCCONF4, 1, AB8500_ANCCONF4_SHIFT,
1886 		AB8500_ANCCONF4_MIN, AB8500_ANCCONF4_MAX, 0),
1887 	SOC_SINGLE_XR_SX("ANC Warp Delay",
1888 		AB8500_ANCCONF9, 2, AB8500_ANC_WARP_DELAY_SHIFT,
1889 		AB8500_ANC_WARP_DELAY_MIN, AB8500_ANC_WARP_DELAY_MAX, 0),
1890 
1891 	/* Sidetone */
1892 	SOC_ENUM_EXT("Sidetone Status", soc_enum_sidstate,
1893 		sid_status_control_get, sid_status_control_put),
1894 	SOC_SINGLE_STROBE("Sidetone Reset",
1895 		AB8500_SIDFIRADR, AB8500_SIDFIRADR_FIRSIDSET, 0),
1896 };
1897 
1898 static struct snd_kcontrol_new ab8500_filter_controls[] = {
1899 	AB8500_FILTER_CONTROL("ANC FIR Coefficients", AB8500_ANC_FIR_COEFFS,
1900 		AB8500_ANC_FIR_COEFF_MIN, AB8500_ANC_FIR_COEFF_MAX),
1901 	AB8500_FILTER_CONTROL("ANC IIR Coefficients", AB8500_ANC_IIR_COEFFS,
1902 		AB8500_ANC_IIR_COEFF_MIN, AB8500_ANC_IIR_COEFF_MAX),
1903 	AB8500_FILTER_CONTROL("Sidetone FIR Coefficients",
1904 			AB8500_SID_FIR_COEFFS, AB8500_SID_FIR_COEFF_MIN,
1905 			AB8500_SID_FIR_COEFF_MAX)
1906 };
1907 enum ab8500_filter {
1908 	AB8500_FILTER_ANC_FIR = 0,
1909 	AB8500_FILTER_ANC_IIR = 1,
1910 	AB8500_FILTER_SID_FIR = 2,
1911 };
1912 
1913 /*
1914  * Extended interface for codec-driver
1915  */
1916 
ab8500_audio_init_audioblock(struct snd_soc_component * component)1917 static int ab8500_audio_init_audioblock(struct snd_soc_component *component)
1918 {
1919 	int status;
1920 
1921 	dev_dbg(component->dev, "%s: Enter.\n", __func__);
1922 
1923 	/* Reset audio-registers and disable 32kHz-clock output 2 */
1924 	status = ab8500_sysctrl_write(AB8500_STW4500CTRL3,
1925 				AB8500_STW4500CTRL3_CLK32KOUT2DIS |
1926 					AB8500_STW4500CTRL3_RESETAUDN,
1927 				AB8500_STW4500CTRL3_RESETAUDN);
1928 	if (status < 0)
1929 		return status;
1930 
1931 	return 0;
1932 }
1933 
ab8500_audio_setup_mics(struct snd_soc_component * component,struct amic_settings * amics)1934 static int ab8500_audio_setup_mics(struct snd_soc_component *component,
1935 			struct amic_settings *amics)
1936 {
1937 	struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
1938 	u8 value8;
1939 	unsigned int value;
1940 	int status;
1941 	const struct snd_soc_dapm_route *route;
1942 
1943 	dev_dbg(component->dev, "%s: Enter.\n", __func__);
1944 
1945 	/* Set DMic-clocks to outputs */
1946 	status = abx500_get_register_interruptible(component->dev, AB8500_MISC,
1947 						AB8500_GPIO_DIR4_REG,
1948 						&value8);
1949 	if (status < 0)
1950 		return status;
1951 	value = value8 | GPIO27_DIR_OUTPUT | GPIO29_DIR_OUTPUT |
1952 		GPIO31_DIR_OUTPUT;
1953 	status = abx500_set_register_interruptible(component->dev,
1954 						AB8500_MISC,
1955 						AB8500_GPIO_DIR4_REG,
1956 						value);
1957 	if (status < 0)
1958 		return status;
1959 
1960 	/* Attach regulators to AMic DAPM-paths */
1961 	dev_dbg(component->dev, "%s: Mic 1a regulator: %s\n", __func__,
1962 		amic_micbias_str(amics->mic1a_micbias));
1963 	route = &ab8500_dapm_routes_mic1a_vamicx[amics->mic1a_micbias];
1964 	status = snd_soc_dapm_add_routes(dapm, route, 1);
1965 	dev_dbg(component->dev, "%s: Mic 1b regulator: %s\n", __func__,
1966 		amic_micbias_str(amics->mic1b_micbias));
1967 	route = &ab8500_dapm_routes_mic1b_vamicx[amics->mic1b_micbias];
1968 	status |= snd_soc_dapm_add_routes(dapm, route, 1);
1969 	dev_dbg(component->dev, "%s: Mic 2 regulator: %s\n", __func__,
1970 		amic_micbias_str(amics->mic2_micbias));
1971 	route = &ab8500_dapm_routes_mic2_vamicx[amics->mic2_micbias];
1972 	status |= snd_soc_dapm_add_routes(dapm, route, 1);
1973 	if (status < 0) {
1974 		dev_err(component->dev,
1975 			"%s: Failed to add AMic-regulator DAPM-routes (%d).\n",
1976 			__func__, status);
1977 		return status;
1978 	}
1979 
1980 	/* Set AMic-configuration */
1981 	dev_dbg(component->dev, "%s: Mic 1 mic-type: %s\n", __func__,
1982 		amic_type_str(amics->mic1_type));
1983 	snd_soc_component_update_bits(component, AB8500_ANAGAIN1, AB8500_ANAGAINX_ENSEMICX,
1984 			amics->mic1_type == AMIC_TYPE_DIFFERENTIAL ?
1985 				0 : AB8500_ANAGAINX_ENSEMICX);
1986 	dev_dbg(component->dev, "%s: Mic 2 mic-type: %s\n", __func__,
1987 		amic_type_str(amics->mic2_type));
1988 	snd_soc_component_update_bits(component, AB8500_ANAGAIN2, AB8500_ANAGAINX_ENSEMICX,
1989 			amics->mic2_type == AMIC_TYPE_DIFFERENTIAL ?
1990 				0 : AB8500_ANAGAINX_ENSEMICX);
1991 
1992 	return 0;
1993 }
1994 
ab8500_audio_set_ear_cmv(struct snd_soc_component * component,enum ear_cm_voltage ear_cmv)1995 static int ab8500_audio_set_ear_cmv(struct snd_soc_component *component,
1996 				enum ear_cm_voltage ear_cmv)
1997 {
1998 	char *cmv_str;
1999 
2000 	switch (ear_cmv) {
2001 	case EAR_CMV_0_95V:
2002 		cmv_str = "0.95V";
2003 		break;
2004 	case EAR_CMV_1_10V:
2005 		cmv_str = "1.10V";
2006 		break;
2007 	case EAR_CMV_1_27V:
2008 		cmv_str = "1.27V";
2009 		break;
2010 	case EAR_CMV_1_58V:
2011 		cmv_str = "1.58V";
2012 		break;
2013 	default:
2014 		dev_err(component->dev,
2015 			"%s: Unknown earpiece CM-voltage (%d)!\n",
2016 			__func__, (int)ear_cmv);
2017 		return -EINVAL;
2018 	}
2019 	dev_dbg(component->dev, "%s: Earpiece CM-voltage: %s\n", __func__,
2020 		cmv_str);
2021 	snd_soc_component_update_bits(component, AB8500_ANACONF1, AB8500_ANACONF1_EARSELCM,
2022 			ear_cmv);
2023 
2024 	return 0;
2025 }
2026 
ab8500_audio_set_bit_delay(struct snd_soc_dai * dai,unsigned int delay)2027 static int ab8500_audio_set_bit_delay(struct snd_soc_dai *dai,
2028 				unsigned int delay)
2029 {
2030 	unsigned int mask, val;
2031 	struct snd_soc_component *component = dai->component;
2032 
2033 	mask = BIT(AB8500_DIGIFCONF2_IF0DEL);
2034 	val = 0;
2035 
2036 	switch (delay) {
2037 	case 0:
2038 		break;
2039 	case 1:
2040 		val |= BIT(AB8500_DIGIFCONF2_IF0DEL);
2041 		break;
2042 	default:
2043 		dev_err(dai->component->dev,
2044 			"%s: ERROR: Unsupported bit-delay (0x%x)!\n",
2045 			__func__, delay);
2046 		return -EINVAL;
2047 	}
2048 
2049 	dev_dbg(dai->component->dev, "%s: IF0 Bit-delay: %d bits.\n",
2050 		__func__, delay);
2051 	snd_soc_component_update_bits(component, AB8500_DIGIFCONF2, mask, val);
2052 
2053 	return 0;
2054 }
2055 
2056 /* Gates clocking according format mask */
ab8500_codec_set_dai_clock_gate(struct snd_soc_component * component,unsigned int fmt)2057 static int ab8500_codec_set_dai_clock_gate(struct snd_soc_component *component,
2058 					unsigned int fmt)
2059 {
2060 	unsigned int mask;
2061 	unsigned int val;
2062 
2063 	mask = BIT(AB8500_DIGIFCONF1_ENMASTGEN) |
2064 			BIT(AB8500_DIGIFCONF1_ENFSBITCLK0);
2065 
2066 	val = BIT(AB8500_DIGIFCONF1_ENMASTGEN);
2067 
2068 	switch (fmt & SND_SOC_DAIFMT_CLOCK_MASK) {
2069 	case SND_SOC_DAIFMT_CONT: /* continuous clock */
2070 		dev_dbg(component->dev, "%s: IF0 Clock is continuous.\n",
2071 			__func__);
2072 		val |= BIT(AB8500_DIGIFCONF1_ENFSBITCLK0);
2073 		break;
2074 	case SND_SOC_DAIFMT_GATED: /* clock is gated */
2075 		dev_dbg(component->dev, "%s: IF0 Clock is gated.\n",
2076 			__func__);
2077 		break;
2078 	default:
2079 		dev_err(component->dev,
2080 			"%s: ERROR: Unsupported clock mask (0x%x)!\n",
2081 			__func__, fmt & SND_SOC_DAIFMT_CLOCK_MASK);
2082 		return -EINVAL;
2083 	}
2084 
2085 	snd_soc_component_update_bits(component, AB8500_DIGIFCONF1, mask, val);
2086 
2087 	return 0;
2088 }
2089 
ab8500_codec_set_dai_fmt(struct snd_soc_dai * dai,unsigned int fmt)2090 static int ab8500_codec_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2091 {
2092 	unsigned int mask;
2093 	unsigned int val;
2094 	struct snd_soc_component *component = dai->component;
2095 	int status;
2096 
2097 	dev_dbg(component->dev, "%s: Enter (fmt = 0x%x)\n", __func__, fmt);
2098 
2099 	mask = BIT(AB8500_DIGIFCONF3_IF1DATOIF0AD) |
2100 			BIT(AB8500_DIGIFCONF3_IF1CLKTOIF0CLK) |
2101 			BIT(AB8500_DIGIFCONF3_IF0BFIFOEN) |
2102 			BIT(AB8500_DIGIFCONF3_IF0MASTER);
2103 	val = 0;
2104 
2105 	switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
2106 	case SND_SOC_DAIFMT_CBP_CFP:
2107 		dev_dbg(dai->component->dev,
2108 			"%s: IF0 Master-mode: AB8500 provider.\n", __func__);
2109 		val |= BIT(AB8500_DIGIFCONF3_IF0MASTER);
2110 		break;
2111 	case SND_SOC_DAIFMT_CBC_CFC:
2112 		dev_dbg(dai->component->dev,
2113 			"%s: IF0 Master-mode: AB8500 consumer.\n", __func__);
2114 		break;
2115 	case SND_SOC_DAIFMT_CBC_CFP:
2116 	case SND_SOC_DAIFMT_CBP_CFC:
2117 		dev_err(dai->component->dev,
2118 			"%s: ERROR: The device is either a provider or a consumer.\n",
2119 			__func__);
2120 		fallthrough;
2121 	default:
2122 		dev_err(dai->component->dev,
2123 			"%s: ERROR: Unsupporter clocking mask 0x%x\n",
2124 			__func__, fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK);
2125 		return -EINVAL;
2126 	}
2127 
2128 	snd_soc_component_update_bits(component, AB8500_DIGIFCONF3, mask, val);
2129 
2130 	/* Set clock gating */
2131 	status = ab8500_codec_set_dai_clock_gate(component, fmt);
2132 	if (status) {
2133 		dev_err(dai->component->dev,
2134 			"%s: ERROR: Failed to set clock gate (%d).\n",
2135 			__func__, status);
2136 		return status;
2137 	}
2138 
2139 	/* Setting data transfer format */
2140 
2141 	mask = BIT(AB8500_DIGIFCONF2_IF0FORMAT0) |
2142 		BIT(AB8500_DIGIFCONF2_IF0FORMAT1) |
2143 		BIT(AB8500_DIGIFCONF2_FSYNC0P) |
2144 		BIT(AB8500_DIGIFCONF2_BITCLK0P);
2145 	val = 0;
2146 
2147 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2148 	case SND_SOC_DAIFMT_I2S: /* I2S mode */
2149 		dev_dbg(dai->component->dev, "%s: IF0 Protocol: I2S\n", __func__);
2150 		val |= BIT(AB8500_DIGIFCONF2_IF0FORMAT1);
2151 		ab8500_audio_set_bit_delay(dai, 0);
2152 		break;
2153 
2154 	case SND_SOC_DAIFMT_DSP_A: /* L data MSB after FRM LRC */
2155 		dev_dbg(dai->component->dev,
2156 			"%s: IF0 Protocol: DSP A (TDM)\n", __func__);
2157 		val |= BIT(AB8500_DIGIFCONF2_IF0FORMAT0);
2158 		ab8500_audio_set_bit_delay(dai, 1);
2159 		break;
2160 
2161 	case SND_SOC_DAIFMT_DSP_B: /* L data MSB during FRM LRC */
2162 		dev_dbg(dai->component->dev,
2163 			"%s: IF0 Protocol: DSP B (TDM)\n", __func__);
2164 		val |= BIT(AB8500_DIGIFCONF2_IF0FORMAT0);
2165 		ab8500_audio_set_bit_delay(dai, 0);
2166 		break;
2167 
2168 	default:
2169 		dev_err(dai->component->dev,
2170 			"%s: ERROR: Unsupported format (0x%x)!\n",
2171 			__func__, fmt & SND_SOC_DAIFMT_FORMAT_MASK);
2172 		return -EINVAL;
2173 	}
2174 
2175 	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2176 	case SND_SOC_DAIFMT_NB_NF: /* normal bit clock + frame */
2177 		dev_dbg(dai->component->dev,
2178 			"%s: IF0: Normal bit clock, normal frame\n",
2179 			__func__);
2180 		break;
2181 	case SND_SOC_DAIFMT_NB_IF: /* normal BCLK + inv FRM */
2182 		dev_dbg(dai->component->dev,
2183 			"%s: IF0: Normal bit clock, inverted frame\n",
2184 			__func__);
2185 		val |= BIT(AB8500_DIGIFCONF2_FSYNC0P);
2186 		break;
2187 	case SND_SOC_DAIFMT_IB_NF: /* invert BCLK + nor FRM */
2188 		dev_dbg(dai->component->dev,
2189 			"%s: IF0: Inverted bit clock, normal frame\n",
2190 			__func__);
2191 		val |= BIT(AB8500_DIGIFCONF2_BITCLK0P);
2192 		break;
2193 	case SND_SOC_DAIFMT_IB_IF: /* invert BCLK + FRM */
2194 		dev_dbg(dai->component->dev,
2195 			"%s: IF0: Inverted bit clock, inverted frame\n",
2196 			__func__);
2197 		val |= BIT(AB8500_DIGIFCONF2_FSYNC0P);
2198 		val |= BIT(AB8500_DIGIFCONF2_BITCLK0P);
2199 		break;
2200 	default:
2201 		dev_err(dai->component->dev,
2202 			"%s: ERROR: Unsupported INV mask 0x%x\n",
2203 			__func__, fmt & SND_SOC_DAIFMT_INV_MASK);
2204 		return -EINVAL;
2205 	}
2206 
2207 	snd_soc_component_update_bits(component, AB8500_DIGIFCONF2, mask, val);
2208 
2209 	return 0;
2210 }
2211 
ab8500_codec_set_dai_tdm_slot(struct snd_soc_dai * dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int slot_width)2212 static int ab8500_codec_set_dai_tdm_slot(struct snd_soc_dai *dai,
2213 		unsigned int tx_mask, unsigned int rx_mask,
2214 		int slots, int slot_width)
2215 {
2216 	struct snd_soc_component *component = dai->component;
2217 	unsigned int val, mask, slot, slots_active;
2218 
2219 	mask = BIT(AB8500_DIGIFCONF2_IF0WL0) |
2220 		BIT(AB8500_DIGIFCONF2_IF0WL1);
2221 	val = 0;
2222 
2223 	switch (slot_width) {
2224 	case 16:
2225 		break;
2226 	case 20:
2227 		val |= BIT(AB8500_DIGIFCONF2_IF0WL0);
2228 		break;
2229 	case 24:
2230 		val |= BIT(AB8500_DIGIFCONF2_IF0WL1);
2231 		break;
2232 	case 32:
2233 		val |= BIT(AB8500_DIGIFCONF2_IF0WL1) |
2234 			BIT(AB8500_DIGIFCONF2_IF0WL0);
2235 		break;
2236 	default:
2237 		dev_err(dai->component->dev, "%s: Unsupported slot-width 0x%x\n",
2238 			__func__, slot_width);
2239 		return -EINVAL;
2240 	}
2241 
2242 	dev_dbg(dai->component->dev, "%s: IF0 slot-width: %d bits.\n",
2243 		__func__, slot_width);
2244 	snd_soc_component_update_bits(component, AB8500_DIGIFCONF2, mask, val);
2245 
2246 	/* Setup TDM clocking according to slot count */
2247 	dev_dbg(dai->component->dev, "%s: Slots, total: %d\n", __func__, slots);
2248 	mask = BIT(AB8500_DIGIFCONF1_IF0BITCLKOS0) |
2249 			BIT(AB8500_DIGIFCONF1_IF0BITCLKOS1);
2250 	switch (slots) {
2251 	case 2:
2252 		val = AB8500_MASK_NONE;
2253 		break;
2254 	case 4:
2255 		val = BIT(AB8500_DIGIFCONF1_IF0BITCLKOS0);
2256 		break;
2257 	case 8:
2258 		val = BIT(AB8500_DIGIFCONF1_IF0BITCLKOS1);
2259 		break;
2260 	case 16:
2261 		val = BIT(AB8500_DIGIFCONF1_IF0BITCLKOS0) |
2262 			BIT(AB8500_DIGIFCONF1_IF0BITCLKOS1);
2263 		break;
2264 	default:
2265 		dev_err(dai->component->dev,
2266 			"%s: ERROR: Unsupported number of slots (%d)!\n",
2267 			__func__, slots);
2268 		return -EINVAL;
2269 	}
2270 	snd_soc_component_update_bits(component, AB8500_DIGIFCONF1, mask, val);
2271 
2272 	/* Setup TDM DA according to active tx slots */
2273 
2274 	if (tx_mask & ~0xff)
2275 		return -EINVAL;
2276 
2277 	mask = AB8500_DASLOTCONFX_SLTODAX_MASK;
2278 	tx_mask = tx_mask << AB8500_DA_DATA0_OFFSET;
2279 	slots_active = hweight32(tx_mask);
2280 
2281 	dev_dbg(dai->component->dev, "%s: Slots, active, TX: %d\n", __func__,
2282 		slots_active);
2283 
2284 	switch (slots_active) {
2285 	case 0:
2286 		break;
2287 	case 1:
2288 		slot = ffs(tx_mask);
2289 		snd_soc_component_update_bits(component, AB8500_DASLOTCONF1, mask, slot);
2290 		snd_soc_component_update_bits(component, AB8500_DASLOTCONF3, mask, slot);
2291 		snd_soc_component_update_bits(component, AB8500_DASLOTCONF2, mask, slot);
2292 		snd_soc_component_update_bits(component, AB8500_DASLOTCONF4, mask, slot);
2293 		break;
2294 	case 2:
2295 		slot = ffs(tx_mask);
2296 		snd_soc_component_update_bits(component, AB8500_DASLOTCONF1, mask, slot);
2297 		snd_soc_component_update_bits(component, AB8500_DASLOTCONF3, mask, slot);
2298 		slot = fls(tx_mask);
2299 		snd_soc_component_update_bits(component, AB8500_DASLOTCONF2, mask, slot);
2300 		snd_soc_component_update_bits(component, AB8500_DASLOTCONF4, mask, slot);
2301 		break;
2302 	case 8:
2303 		dev_dbg(dai->component->dev,
2304 			"%s: In 8-channel mode DA-from-slot mapping is set manually.",
2305 			__func__);
2306 		break;
2307 	default:
2308 		dev_err(dai->component->dev,
2309 			"%s: Unsupported number of active TX-slots (%d)!\n",
2310 			__func__, slots_active);
2311 		return -EINVAL;
2312 	}
2313 
2314 	/* Setup TDM AD according to active RX-slots */
2315 
2316 	if (rx_mask & ~0xff)
2317 		return -EINVAL;
2318 
2319 	rx_mask = rx_mask << AB8500_AD_DATA0_OFFSET;
2320 	slots_active = hweight32(rx_mask);
2321 
2322 	dev_dbg(dai->component->dev, "%s: Slots, active, RX: %d\n", __func__,
2323 		slots_active);
2324 
2325 	switch (slots_active) {
2326 	case 0:
2327 		break;
2328 	case 1:
2329 		slot = ffs(rx_mask);
2330 		snd_soc_component_update_bits(component, AB8500_ADSLOTSEL(slot),
2331 				AB8500_MASK_SLOT(slot),
2332 				AB8500_ADSLOTSELX_AD_OUT_TO_SLOT(AB8500_AD_OUT3, slot));
2333 		break;
2334 	case 2:
2335 		slot = ffs(rx_mask);
2336 		snd_soc_component_update_bits(component,
2337 				AB8500_ADSLOTSEL(slot),
2338 				AB8500_MASK_SLOT(slot),
2339 				AB8500_ADSLOTSELX_AD_OUT_TO_SLOT(AB8500_AD_OUT3, slot));
2340 		slot = fls(rx_mask);
2341 		snd_soc_component_update_bits(component,
2342 				AB8500_ADSLOTSEL(slot),
2343 				AB8500_MASK_SLOT(slot),
2344 				AB8500_ADSLOTSELX_AD_OUT_TO_SLOT(AB8500_AD_OUT2, slot));
2345 		break;
2346 	case 8:
2347 		dev_dbg(dai->component->dev,
2348 			"%s: In 8-channel mode AD-to-slot mapping is set manually.",
2349 			__func__);
2350 		break;
2351 	default:
2352 		dev_err(dai->component->dev,
2353 			"%s: Unsupported number of active RX-slots (%d)!\n",
2354 			__func__, slots_active);
2355 		return -EINVAL;
2356 	}
2357 
2358 	return 0;
2359 }
2360 
2361 static const struct snd_soc_dai_ops ab8500_codec_ops = {
2362 	.set_fmt = ab8500_codec_set_dai_fmt,
2363 	.set_tdm_slot = ab8500_codec_set_dai_tdm_slot,
2364 };
2365 
2366 static struct snd_soc_dai_driver ab8500_codec_dai[] = {
2367 	{
2368 		.name = "ab8500-codec-dai.0",
2369 		.id = 0,
2370 		.playback = {
2371 			.stream_name = "ab8500_0p",
2372 			.channels_min = 1,
2373 			.channels_max = 8,
2374 			.rates = AB8500_SUPPORTED_RATE,
2375 			.formats = AB8500_SUPPORTED_FMT,
2376 		},
2377 		.ops = &ab8500_codec_ops,
2378 		.symmetric_rate = 1
2379 	},
2380 	{
2381 		.name = "ab8500-codec-dai.1",
2382 		.id = 1,
2383 		.capture = {
2384 			.stream_name = "ab8500_0c",
2385 			.channels_min = 1,
2386 			.channels_max = 8,
2387 			.rates = AB8500_SUPPORTED_RATE,
2388 			.formats = AB8500_SUPPORTED_FMT,
2389 		},
2390 		.ops = &ab8500_codec_ops,
2391 		.symmetric_rate = 1
2392 	}
2393 };
2394 
ab8500_codec_of_probe(struct device * dev,struct device_node * np,struct ab8500_codec_platform_data * codec)2395 static void ab8500_codec_of_probe(struct device *dev, struct device_node *np,
2396 				struct ab8500_codec_platform_data *codec)
2397 {
2398 	u32 value;
2399 
2400 	if (of_property_read_bool(np, "stericsson,amic1-type-single-ended"))
2401 		codec->amics.mic1_type = AMIC_TYPE_SINGLE_ENDED;
2402 	else
2403 		codec->amics.mic1_type = AMIC_TYPE_DIFFERENTIAL;
2404 
2405 	if (of_property_read_bool(np, "stericsson,amic2-type-single-ended"))
2406 		codec->amics.mic2_type = AMIC_TYPE_SINGLE_ENDED;
2407 	else
2408 		codec->amics.mic2_type = AMIC_TYPE_DIFFERENTIAL;
2409 
2410 	/* Has a non-standard Vamic been requested? */
2411 	if (of_property_read_bool(np, "stericsson,amic1a-bias-vamic2"))
2412 		codec->amics.mic1a_micbias = AMIC_MICBIAS_VAMIC2;
2413 	else
2414 		codec->amics.mic1a_micbias = AMIC_MICBIAS_VAMIC1;
2415 
2416 	if (of_property_read_bool(np, "stericsson,amic1b-bias-vamic2"))
2417 		codec->amics.mic1b_micbias = AMIC_MICBIAS_VAMIC2;
2418 	else
2419 		codec->amics.mic1b_micbias = AMIC_MICBIAS_VAMIC1;
2420 
2421 	if (of_property_read_bool(np, "stericsson,amic2-bias-vamic1"))
2422 		codec->amics.mic2_micbias = AMIC_MICBIAS_VAMIC1;
2423 	else
2424 		codec->amics.mic2_micbias = AMIC_MICBIAS_VAMIC2;
2425 
2426 	if (!of_property_read_u32(np, "stericsson,earpeice-cmv", &value)) {
2427 		switch (value) {
2428 		case 950 :
2429 			codec->ear_cmv = EAR_CMV_0_95V;
2430 			break;
2431 		case 1100 :
2432 			codec->ear_cmv = EAR_CMV_1_10V;
2433 			break;
2434 		case 1270 :
2435 			codec->ear_cmv = EAR_CMV_1_27V;
2436 			break;
2437 		case 1580 :
2438 			codec->ear_cmv = EAR_CMV_1_58V;
2439 			break;
2440 		default :
2441 			codec->ear_cmv = EAR_CMV_UNKNOWN;
2442 			dev_err(dev, "Unsuitable earpiece voltage found in DT\n");
2443 		}
2444 	} else {
2445 		dev_warn(dev, "No earpiece voltage found in DT - using default\n");
2446 		codec->ear_cmv = EAR_CMV_0_95V;
2447 	}
2448 }
2449 
ab8500_codec_probe(struct snd_soc_component * component)2450 static int ab8500_codec_probe(struct snd_soc_component *component)
2451 {
2452 	struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
2453 	struct device *dev = component->dev;
2454 	struct device_node *np = dev->of_node;
2455 	struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(dev);
2456 	struct ab8500_codec_platform_data codec_pdata;
2457 	struct filter_control *fc;
2458 	int status;
2459 
2460 	dev_dbg(dev, "%s: Enter.\n", __func__);
2461 
2462 	ab8500_codec_of_probe(dev, np, &codec_pdata);
2463 
2464 	status = ab8500_audio_setup_mics(component, &codec_pdata.amics);
2465 	if (status < 0) {
2466 		pr_err("%s: Failed to setup mics (%d)!\n", __func__, status);
2467 		return status;
2468 	}
2469 	status = ab8500_audio_set_ear_cmv(component, codec_pdata.ear_cmv);
2470 	if (status < 0) {
2471 		pr_err("%s: Failed to set earpiece CM-voltage (%d)!\n",
2472 			__func__, status);
2473 		return status;
2474 	}
2475 
2476 	status = ab8500_audio_init_audioblock(component);
2477 	if (status < 0) {
2478 		dev_err(dev, "%s: failed to init audio-block (%d)!\n",
2479 			__func__, status);
2480 		return status;
2481 	}
2482 
2483 	/* Override HW-defaults */
2484 	snd_soc_component_write(component, AB8500_ANACONF5,
2485 		      BIT(AB8500_ANACONF5_HSAUTOEN));
2486 	snd_soc_component_write(component, AB8500_SHORTCIRCONF,
2487 		      BIT(AB8500_SHORTCIRCONF_HSZCDDIS));
2488 
2489 	/* Add filter controls */
2490 	status = snd_soc_add_component_controls(component, ab8500_filter_controls,
2491 				ARRAY_SIZE(ab8500_filter_controls));
2492 	if (status < 0) {
2493 		dev_err(dev,
2494 			"%s: failed to add ab8500 filter controls (%d).\n",
2495 			__func__, status);
2496 		return status;
2497 	}
2498 	fc = (struct filter_control *)
2499 		&ab8500_filter_controls[AB8500_FILTER_ANC_FIR].private_value;
2500 	drvdata->anc_fir_values = (long *)fc->value;
2501 	fc = (struct filter_control *)
2502 		&ab8500_filter_controls[AB8500_FILTER_ANC_IIR].private_value;
2503 	drvdata->anc_iir_values = (long *)fc->value;
2504 	fc = (struct filter_control *)
2505 		&ab8500_filter_controls[AB8500_FILTER_SID_FIR].private_value;
2506 	drvdata->sid_fir_values = (long *)fc->value;
2507 
2508 	snd_soc_dapm_disable_pin(dapm, "ANC Configure Input");
2509 
2510 	mutex_init(&drvdata->ctrl_lock);
2511 
2512 	return status;
2513 }
2514 
2515 static const struct snd_soc_component_driver ab8500_component_driver = {
2516 	.probe			= ab8500_codec_probe,
2517 	.controls		= ab8500_ctrls,
2518 	.num_controls		= ARRAY_SIZE(ab8500_ctrls),
2519 	.dapm_widgets		= ab8500_dapm_widgets,
2520 	.num_dapm_widgets	= ARRAY_SIZE(ab8500_dapm_widgets),
2521 	.dapm_routes		= ab8500_dapm_routes,
2522 	.num_dapm_routes	= ARRAY_SIZE(ab8500_dapm_routes),
2523 	.idle_bias_on		= 1,
2524 	.use_pmdown_time	= 1,
2525 	.endianness		= 1,
2526 };
2527 
ab8500_codec_driver_probe(struct platform_device * pdev)2528 static int ab8500_codec_driver_probe(struct platform_device *pdev)
2529 {
2530 	int status;
2531 	struct ab8500_codec_drvdata *drvdata;
2532 
2533 	dev_dbg(&pdev->dev, "%s: Enter.\n", __func__);
2534 
2535 	/* Create driver private-data struct */
2536 	drvdata = devm_kzalloc(&pdev->dev, sizeof(struct ab8500_codec_drvdata),
2537 			GFP_KERNEL);
2538 	if (!drvdata)
2539 		return -ENOMEM;
2540 	drvdata->sid_status = SID_UNCONFIGURED;
2541 	drvdata->anc_status = ANC_UNCONFIGURED;
2542 	dev_set_drvdata(&pdev->dev, drvdata);
2543 
2544 	drvdata->regmap = devm_regmap_init(&pdev->dev, NULL, &pdev->dev,
2545 					   &ab8500_codec_regmap);
2546 	if (IS_ERR(drvdata->regmap)) {
2547 		status = PTR_ERR(drvdata->regmap);
2548 		dev_err(&pdev->dev, "%s: Failed to allocate regmap: %d\n",
2549 			__func__, status);
2550 		return status;
2551 	}
2552 
2553 	dev_dbg(&pdev->dev, "%s: Register codec.\n", __func__);
2554 	status = devm_snd_soc_register_component(&pdev->dev,
2555 				&ab8500_component_driver,
2556 				ab8500_codec_dai,
2557 				ARRAY_SIZE(ab8500_codec_dai));
2558 	if (status < 0)
2559 		dev_err(&pdev->dev,
2560 			"%s: Error: Failed to register codec (%d).\n",
2561 			__func__, status);
2562 
2563 	return status;
2564 }
2565 
2566 static struct platform_driver ab8500_codec_platform_driver = {
2567 	.driver	= {
2568 		.name	= "ab8500-codec",
2569 	},
2570 	.probe		= ab8500_codec_driver_probe,
2571 };
2572 module_platform_driver(ab8500_codec_platform_driver);
2573 
2574 MODULE_LICENSE("GPL v2");
2575