1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * (C) Copyright 2000
4 * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
5 */
6
7 #ifndef _NS87308_H_
8 #define _NS87308_H_
9
10 #include <asm/pci_io.h>
11
12 /* Note: I couldn't find a full data sheet for the ns87308, but the ns87307 seems to be pretty
13 functionally- (and pin-) equivalent to the 87308, but the 308 has better ir support. */
14
15 void initialise_ns87308(void);
16
17 /*
18 * The following struct represents the GPIO registers on the NS87308/NS97307
19 */
20 struct GPIO
21 {
22 unsigned char dta1; /* 0 data port 1 */
23 unsigned char dir1; /* 1 direction port 1 */
24 unsigned char out1; /* 2 output type port 1 */
25 unsigned char puc1; /* 3 pull-up control port 1 */
26 unsigned char dta2; /* 4 data port 2 */
27 unsigned char dir2; /* 5 direction port 2 */
28 unsigned char out2; /* 6 output type port 2 */
29 unsigned char puc2; /* 7 pull-up control port 2 */
30 };
31
32 /*
33 * The following represents the power management registers on the NS87308/NS97307
34 */
35 #define PWM_FER1 0 /* 0 function enable reg. 1 */
36 #define PWM_FER2 1 /* 1 function enable reg. 2 */
37 #define PWM_PMC1 2 /* 2 power mgmt. control 1 */
38 #define PWM_PMC2 3 /* 3 power mgmt. control 2 */
39 #define PWM_PMC3 4 /* 4 power mgmt. control 3 */
40 #define PWM_WDTO 5 /* 5 watchdog time-out */
41 #define PWM_WDCF 6 /* 6 watchdog config. */
42 #define PWM_WDST 7 /* 7 watchdog status */
43
44 /*PNP config registers:
45 * these depend on the stated of BADDR1 and BADDR0 on startup
46 * so there's three versions here with the last two digits indicating
47 * for which configuration their valid
48 * the 1st of the two digits indicates the state of BADDR1
49 * the 2st of the two digits indicates the state of BADDR0
50 */
51
52
53 #define IO_INDEX_OFFSET_0x 0x0279 /* full PnP isa Mode */
54 #define IO_INDEX_OFFSET_10 0x015C /* PnP motherboard mode */
55 #define IO_INDEX_OFFSET_11 0x002E /* PnP motherboard mode */
56 #define IO_DATA_OFFSET_0x 0x0A79 /* full PnP isa Mode */
57 #define IO_DATA_OFFSET_10 0x015D /* PnP motherboard mode */
58 #define IO_DATA_OFFSET_11 0x002F /* PnP motherboard mode */
59
60 #if defined(CONFIG_SYS_NS87308_BADDR_0x)
61 #define IO_INDEX (CONFIG_SYS_ISA_IO + IO_INDEX_OFFSET_0x)
62 #define IO_DATA (CONFIG_SYS_ISA_IO + IO_DATA_OFFSET_0x)
63 #elif defined(CONFIG_SYS_NS87308_BADDR_10)
64 #define IO_INDEX (CONFIG_SYS_ISA_IO + IO_INDEX_OFFSET_10)
65 #define IO_DATA (CONFIG_SYS_ISA_IO + IO_DATA_OFFSET_10)
66 #elif defined(CONFIG_SYS_NS87308_BADDR_11)
67 #define IO_INDEX (CONFIG_SYS_ISA_IO + IO_INDEX_OFFSET_11)
68 #define IO_DATA (CONFIG_SYS_ISA_IO + IO_DATA_OFFSET_11)
69 #endif
70
71 /* PnP register definitions */
72
73 #define SET_RD_DATA_PORT 0x00
74 #define SERIAL_ISOLATION 0x01
75 #define CONFIG_CONTROL 0x02
76 #define WAKE_CSN 0x03
77 #define RES_DATA 0x04
78 #define STATUS 0x05
79 #define SET_CSN 0x06
80 #define LOGICAL_DEVICE 0x07
81
82 /*vendor defined values */
83 #define SID_REG 0x20
84 #define SUPOERIO_CONF1 0x21
85 #define SUPOERIO_CONF2 0x22
86 #define PGCS_INDEX 0x23
87 #define PGCS_DATA 0x24
88
89 /* values above 30 are different for each logical device
90 but I can't be arsed to enter them all. the ones here
91 are pretty consistent between all logical devices
92 feel free to correct the situation if you want.. ;)
93 */
94 #define ACTIVATE 0x30
95 #define ACTIVATE_OFF 0x00
96 #define ACTIVATE_ON 0x01
97
98 #define BASE_ADDR_HIGH 0x60
99 #define BASE_ADDR_LOW 0x61
100 #define LUN_CONFIG_REG 0xF0
101 #define DBASE_HIGH 0x60 /* SIO KBC data base address, 15:8 */
102 #define DBASE_LOW 0x61 /* SIO KBC data base address, 7:0 */
103 #define CBASE_HIGH 0x62 /* SIO KBC command base addr, 15:8 */
104 #define CBASE_LOW 0x63 /* SIO KBC command base addr, 7:0 */
105
106 /* the logical devices*/
107 #define LDEV_KBC1 0x00 /* 2 devices for keyboard and mouse controller*/
108 #define LDEV_KBC2 0x01
109 #define LDEV_MOUSE 0x01
110 #define LDEV_RTC_APC 0x02 /*Real Time Clock and Advanced Power Control*/
111 #define LDEV_FDC 0x03 /*floppy disk controller*/
112 #define LDEV_PARP 0x04 /*Parallel port*/
113 #define LDEV_UART2 0x05
114 #define LDEV_UART1 0x06
115 #define LDEV_GPIO 0x07 /*General Purpose IO and chip select output signals*/
116 #define LDEV_POWRMAN 0x08 /*Power Managment*/
117
118 #define CONFIG_SYS_NS87308_KBC1 (1 << LDEV_KBC1)
119 #define CONFIG_SYS_NS87308_KBC2 (1 << LDEV_KBC2)
120 #define CONFIG_SYS_NS87308_MOUSE (1 << LDEV_MOUSE)
121 #define CONFIG_SYS_NS87308_RTC_APC (1 << LDEV_RTC_APC)
122 #define CONFIG_SYS_NS87308_FDC (1 << LDEV_FDC)
123 #define CONFIG_SYS_NS87308_PARP (1 << LDEV_PARP)
124 #define CONFIG_SYS_NS87308_UART2 (1 << LDEV_UART2)
125 #define CONFIG_SYS_NS87308_UART1 (1 << LDEV_UART1)
126 #define CONFIG_SYS_NS87308_GPIO (1 << LDEV_GPIO)
127 #define CONFIG_SYS_NS87308_POWRMAN (1 << LDEV_POWRMAN)
128
129 /*some functions and macro's for doing configuration */
130
read_pnp_config(unsigned char index,unsigned char * data)131 static inline void read_pnp_config(unsigned char index, unsigned char *data)
132 {
133 pci_writeb(index,IO_INDEX);
134 pci_readb(IO_DATA, *data);
135 }
136
write_pnp_config(unsigned char index,unsigned char data)137 static inline void write_pnp_config(unsigned char index, unsigned char data)
138 {
139 pci_writeb(index,IO_INDEX);
140 pci_writeb(data, IO_DATA);
141 }
142
pnp_set_device(unsigned char dev)143 static inline void pnp_set_device(unsigned char dev)
144 {
145 write_pnp_config(LOGICAL_DEVICE, dev);
146 }
147
write_pm_reg(unsigned short base,unsigned char index,unsigned char data)148 static inline void write_pm_reg(unsigned short base, unsigned char index, unsigned char data)
149 {
150 pci_writeb(index, CONFIG_SYS_ISA_IO + base);
151 eieio();
152 pci_writeb(data, CONFIG_SYS_ISA_IO + base + 1);
153 }
154
155 /*void write_pnp_config(unsigned char index, unsigned char data);
156 void pnp_set_device(unsigned char dev);
157 */
158
159 #define PNP_SET_DEVICE_BASE(dev,base) \
160 pnp_set_device(dev); \
161 write_pnp_config(ACTIVATE, ACTIVATE_OFF); \
162 write_pnp_config(BASE_ADDR_HIGH, ((base) >> 8) & 0xff ); \
163 write_pnp_config(BASE_ADDR_LOW, (base) &0xff); \
164 write_pnp_config(ACTIVATE, ACTIVATE_ON);
165
166 #define PNP_ACTIVATE_DEVICE(dev) \
167 pnp_set_device(dev); \
168 write_pnp_config(ACTIVATE, ACTIVATE_ON);
169
170 #define PNP_DEACTIVATE_DEVICE(dev) \
171 pnp_set_device(dev); \
172 write_pnp_config(ACTIVATE, ACTIVATE_OFF);
173
174
write_pgcs_config(unsigned char index,unsigned char data)175 static inline void write_pgcs_config(unsigned char index, unsigned char data)
176 {
177 write_pnp_config(PGCS_INDEX, index);
178 write_pnp_config(PGCS_DATA, data);
179 }
180
181 /* these macrose configure the 3 CS lines
182 on the sandpoint board these controll NVRAM
183 CS0 is connected to NVRAMCS
184 CS1 is connected to NVRAMAS0
185 CS2 is connected to NVRAMAS1
186 */
187 #define PGCS_CS_ASSERT_ON_WRITE 0x10
188 #define PGCS_CS_ASSERT_ON_READ 0x20
189
190 #define PNP_PGCS_CSLINE_BASE(cs, base) \
191 write_pgcs_config((cs) << 2, ((base) >> 8) & 0xff ); \
192 write_pgcs_config(((cs) << 2) + 1, (base) & 0xff );
193
194 #define PNP_PGCS_CSLINE_CONF(cs, conf) \
195 write_pgcs_config(((cs) << 2) + 2, (conf) );
196
197
198 /* The following sections are for 87308 extensions to the standard compoents it emulates */
199
200 /* extensions to 16550*/
201
202 #define MCR_MDSL_MSK 0xe0 /*mode select mask*/
203 #define MCR_MDSL_UART 0x00 /*uart, default*/
204 #define MCR_MDSL_SHRPIR 0x02 /*Sharp IR*/
205 #define MCR_MDSL_SIR 0x03 /*SIR*/
206 #define MCR_MDSL_CIR 0x06 /*Consumer IR*/
207
208 #define FCR_TXFTH0 0x10 /* these bits control threshod of data level in fifo */
209 #define FCR_TXFTH1 0x20 /* for interrupt trigger */
210
211 /*
212 * Default NS87308 configuration
213 */
214 #ifndef CONFIG_SYS_NS87308_KBC1_BASE
215 #define CONFIG_SYS_NS87308_KBC1_BASE 0x0060
216 #endif
217 #ifndef CONFIG_SYS_NS87308_RTC_BASE
218 #define CONFIG_SYS_NS87308_RTC_BASE 0x0070
219 #endif
220 #ifndef CONFIG_SYS_NS87308_FDC_BASE
221 #define CONFIG_SYS_NS87308_FDC_BASE 0x03F0
222 #endif
223 #ifndef CONFIG_SYS_NS87308_LPT_BASE
224 #define CONFIG_SYS_NS87308_LPT_BASE 0x0278
225 #endif
226 #ifndef CONFIG_SYS_NS87308_UART1_BASE
227 #define CONFIG_SYS_NS87308_UART1_BASE 0x03F8
228 #endif
229 #ifndef CONFIG_SYS_NS87308_UART2_BASE
230 #define CONFIG_SYS_NS87308_UART2_BASE 0x02F8
231 #endif
232
233 #endif /*_NS87308_H_*/
234