xref: /openbmc/linux/drivers/net/ethernet/renesas/ravb.h (revision 4f2c0a4acffbec01079c28f839422e64ddeff004) 
1  /* SPDX-License-Identifier: GPL-2.0 */
2  /* Renesas Ethernet AVB device driver
3   *
4   * Copyright (C) 2014-2015 Renesas Electronics Corporation
5   * Copyright (C) 2015 Renesas Solutions Corp.
6   * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com>
7   *
8   * Based on the SuperH Ethernet driver
9   */
10  
11  #ifndef __RAVB_H__
12  #define __RAVB_H__
13  
14  #include <linux/interrupt.h>
15  #include <linux/io.h>
16  #include <linux/kernel.h>
17  #include <linux/mdio-bitbang.h>
18  #include <linux/netdevice.h>
19  #include <linux/phy.h>
20  #include <linux/platform_device.h>
21  #include <linux/ptp_clock_kernel.h>
22  
23  #define BE_TX_RING_SIZE	64	/* TX ring size for Best Effort */
24  #define BE_RX_RING_SIZE	1024	/* RX ring size for Best Effort */
25  #define NC_TX_RING_SIZE	64	/* TX ring size for Network Control */
26  #define NC_RX_RING_SIZE	64	/* RX ring size for Network Control */
27  #define BE_TX_RING_MIN	64
28  #define BE_RX_RING_MIN	64
29  #define BE_TX_RING_MAX	1024
30  #define BE_RX_RING_MAX	2048
31  
32  #define PKT_BUF_SZ	1538
33  
34  /* Driver's parameters */
35  #define RAVB_ALIGN	128
36  
37  /* Hardware time stamp */
38  #define RAVB_TXTSTAMP_VALID	0x00000001	/* TX timestamp valid */
39  #define RAVB_TXTSTAMP_ENABLED	0x00000010	/* Enable TX timestamping */
40  
41  #define RAVB_RXTSTAMP_VALID	0x00000001	/* RX timestamp valid */
42  #define RAVB_RXTSTAMP_TYPE	0x00000006	/* RX type mask */
43  #define RAVB_RXTSTAMP_TYPE_V2_L2_EVENT 0x00000002
44  #define RAVB_RXTSTAMP_TYPE_ALL	0x00000006
45  #define RAVB_RXTSTAMP_ENABLED	0x00000010	/* Enable RX timestamping */
46  
47  enum ravb_reg {
48  	/* AVB-DMAC registers */
49  	CCC	= 0x0000,
50  	DBAT	= 0x0004,
51  	DLR	= 0x0008,
52  	CSR	= 0x000C,
53  	CDAR0	= 0x0010,
54  	CDAR1	= 0x0014,
55  	CDAR2	= 0x0018,
56  	CDAR3	= 0x001C,
57  	CDAR4	= 0x0020,
58  	CDAR5	= 0x0024,
59  	CDAR6	= 0x0028,
60  	CDAR7	= 0x002C,
61  	CDAR8	= 0x0030,
62  	CDAR9	= 0x0034,
63  	CDAR10	= 0x0038,
64  	CDAR11	= 0x003C,
65  	CDAR12	= 0x0040,
66  	CDAR13	= 0x0044,
67  	CDAR14	= 0x0048,
68  	CDAR15	= 0x004C,
69  	CDAR16	= 0x0050,
70  	CDAR17	= 0x0054,
71  	CDAR18	= 0x0058,
72  	CDAR19	= 0x005C,
73  	CDAR20	= 0x0060,
74  	CDAR21	= 0x0064,
75  	ESR	= 0x0088,
76  	APSR	= 0x008C,	/* R-Car Gen3 only */
77  	RCR	= 0x0090,
78  	RQC0	= 0x0094,
79  	RQC1	= 0x0098,
80  	RQC2	= 0x009C,
81  	RQC3	= 0x00A0,
82  	RQC4	= 0x00A4,
83  	RPC	= 0x00B0,
84  	RTC	= 0x00B4,	/* R-Car Gen3 and RZ/G2L only */
85  	UFCW	= 0x00BC,
86  	UFCS	= 0x00C0,
87  	UFCV0	= 0x00C4,
88  	UFCV1	= 0x00C8,
89  	UFCV2	= 0x00CC,
90  	UFCV3	= 0x00D0,
91  	UFCV4	= 0x00D4,
92  	UFCD0	= 0x00E0,
93  	UFCD1	= 0x00E4,
94  	UFCD2	= 0x00E8,
95  	UFCD3	= 0x00EC,
96  	UFCD4	= 0x00F0,
97  	SFO	= 0x00FC,
98  	SFP0	= 0x0100,
99  	SFP1	= 0x0104,
100  	SFP2	= 0x0108,
101  	SFP3	= 0x010C,
102  	SFP4	= 0x0110,
103  	SFP5	= 0x0114,
104  	SFP6	= 0x0118,
105  	SFP7	= 0x011C,
106  	SFP8	= 0x0120,
107  	SFP9	= 0x0124,
108  	SFP10	= 0x0128,
109  	SFP11	= 0x012C,
110  	SFP12	= 0x0130,
111  	SFP13	= 0x0134,
112  	SFP14	= 0x0138,
113  	SFP15	= 0x013C,
114  	SFP16	= 0x0140,
115  	SFP17	= 0x0144,
116  	SFP18	= 0x0148,
117  	SFP19	= 0x014C,
118  	SFP20	= 0x0150,
119  	SFP21	= 0x0154,
120  	SFP22	= 0x0158,
121  	SFP23	= 0x015C,
122  	SFP24	= 0x0160,
123  	SFP25	= 0x0164,
124  	SFP26	= 0x0168,
125  	SFP27	= 0x016C,
126  	SFP28	= 0x0170,
127  	SFP29	= 0x0174,
128  	SFP30	= 0x0178,
129  	SFP31	= 0x017C,
130  	SFM0	= 0x01C0,
131  	SFM1	= 0x01C4,
132  	TGC	= 0x0300,
133  	TCCR	= 0x0304,
134  	TSR	= 0x0308,
135  	TFA0	= 0x0310,
136  	TFA1	= 0x0314,
137  	TFA2	= 0x0318,
138  	CIVR0	= 0x0320,
139  	CIVR1	= 0x0324,
140  	CDVR0	= 0x0328,
141  	CDVR1	= 0x032C,
142  	CUL0	= 0x0330,
143  	CUL1	= 0x0334,
144  	CLL0	= 0x0338,
145  	CLL1	= 0x033C,
146  	DIC	= 0x0350,
147  	DIS	= 0x0354,
148  	EIC	= 0x0358,
149  	EIS	= 0x035C,
150  	RIC0	= 0x0360,
151  	RIS0	= 0x0364,
152  	RIC1	= 0x0368,
153  	RIS1	= 0x036C,
154  	RIC2	= 0x0370,
155  	RIS2	= 0x0374,
156  	TIC	= 0x0378,
157  	TIS	= 0x037C,
158  	ISS	= 0x0380,
159  	CIE	= 0x0384,	/* R-Car Gen3 only */
160  	GCCR	= 0x0390,
161  	GMTT	= 0x0394,
162  	GPTC	= 0x0398,
163  	GTI	= 0x039C,
164  	GTO0	= 0x03A0,
165  	GTO1	= 0x03A4,
166  	GTO2	= 0x03A8,
167  	GIC	= 0x03AC,
168  	GIS	= 0x03B0,
169  	GCPT	= 0x03B4,	/* Documented for R-Car Gen3 only */
170  	GCT0	= 0x03B8,
171  	GCT1	= 0x03BC,
172  	GCT2	= 0x03C0,
173  	GIE	= 0x03CC,	/* R-Car Gen3 only */
174  	GID	= 0x03D0,	/* R-Car Gen3 only */
175  	DIL	= 0x0440,	/* R-Car Gen3 only */
176  	RIE0	= 0x0460,	/* R-Car Gen3 only */
177  	RID0	= 0x0464,	/* R-Car Gen3 only */
178  	RIE2	= 0x0470,	/* R-Car Gen3 only */
179  	RID2	= 0x0474,	/* R-Car Gen3 only */
180  	TIE	= 0x0478,	/* R-Car Gen3 only */
181  	TID	= 0x047c,	/* R-Car Gen3 only */
182  
183  	/* E-MAC registers */
184  	ECMR	= 0x0500,
185  	RFLR	= 0x0508,
186  	ECSR	= 0x0510,
187  	ECSIPR	= 0x0518,
188  	PIR	= 0x0520,
189  	PSR	= 0x0528,
190  	PIPR	= 0x052c,
191  	CXR31	= 0x0530,	/* RZ/G2L only */
192  	CXR35	= 0x0540,	/* RZ/G2L only */
193  	MPR	= 0x0558,
194  	PFTCR	= 0x055c,
195  	PFRCR	= 0x0560,
196  	GECMR	= 0x05b0,
197  	MAHR	= 0x05c0,
198  	MALR	= 0x05c8,
199  	TROCR	= 0x0700,	/* R-Car Gen3 and RZ/G2L only */
200  	CXR41	= 0x0708,	/* RZ/G2L only */
201  	CXR42	= 0x0710,	/* RZ/G2L only */
202  	CEFCR	= 0x0740,
203  	FRECR	= 0x0748,
204  	TSFRCR	= 0x0750,
205  	TLFRCR	= 0x0758,
206  	RFCR	= 0x0760,
207  	MAFCR	= 0x0778,
208  	CSR0    = 0x0800,	/* RZ/G2L only */
209  };
210  
211  
212  /* Register bits of the Ethernet AVB */
213  /* CCC */
214  enum CCC_BIT {
215  	CCC_OPC		= 0x00000003,
216  	CCC_OPC_RESET	= 0x00000000,
217  	CCC_OPC_CONFIG	= 0x00000001,
218  	CCC_OPC_OPERATION = 0x00000002,
219  	CCC_GAC		= 0x00000080,
220  	CCC_DTSR	= 0x00000100,
221  	CCC_CSEL	= 0x00030000,
222  	CCC_CSEL_HPB	= 0x00010000,
223  	CCC_CSEL_ETH_TX	= 0x00020000,
224  	CCC_CSEL_GMII_REF = 0x00030000,
225  	CCC_LBME	= 0x01000000,
226  };
227  
228  /* CSR */
229  enum CSR_BIT {
230  	CSR_OPS		= 0x0000000F,
231  	CSR_OPS_RESET	= 0x00000001,
232  	CSR_OPS_CONFIG	= 0x00000002,
233  	CSR_OPS_OPERATION = 0x00000004,
234  	CSR_OPS_STANDBY	= 0x00000008,	/* Documented for R-Car Gen3 only */
235  	CSR_DTS		= 0x00000100,
236  	CSR_TPO0	= 0x00010000,
237  	CSR_TPO1	= 0x00020000,
238  	CSR_TPO2	= 0x00040000,
239  	CSR_TPO3	= 0x00080000,
240  	CSR_RPO		= 0x00100000,
241  };
242  
243  /* ESR */
244  enum ESR_BIT {
245  	ESR_EQN		= 0x0000001F,
246  	ESR_ET		= 0x00000F00,
247  	ESR_EIL		= 0x00001000,
248  };
249  
250  /* APSR (R-Car Gen3 only) */
251  enum APSR_BIT {
252  	APSR_MEMS	= 0x00000002,	/* Undocumented */
253  	APSR_CMSW	= 0x00000010,
254  	APSR_RDM	= 0x00002000,
255  	APSR_TDM	= 0x00004000,
256  };
257  
258  /* RCR */
259  enum RCR_BIT {
260  	RCR_EFFS	= 0x00000001,
261  	RCR_ENCF	= 0x00000002,
262  	RCR_ESF		= 0x0000000C,
263  	RCR_ETS0	= 0x00000010,
264  	RCR_ETS2	= 0x00000020,
265  	RCR_RFCL	= 0x1FFF0000,
266  };
267  
268  /* RQC0/1/2/3/4 */
269  enum RQC_BIT {
270  	RQC_RSM0	= 0x00000003,
271  	RQC_UFCC0	= 0x00000030,
272  	RQC_RSM1	= 0x00000300,
273  	RQC_UFCC1	= 0x00003000,
274  	RQC_RSM2	= 0x00030000,
275  	RQC_UFCC2	= 0x00300000,
276  	RQC_RSM3	= 0x03000000,
277  	RQC_UFCC3	= 0x30000000,
278  };
279  
280  /* RPC */
281  enum RPC_BIT {
282  	RPC_PCNT	= 0x00000700,
283  	RPC_DCNT	= 0x00FF0000,
284  };
285  
286  /* UFCW */
287  enum UFCW_BIT {
288  	UFCW_WL0	= 0x0000003F,
289  	UFCW_WL1	= 0x00003F00,
290  	UFCW_WL2	= 0x003F0000,
291  	UFCW_WL3	= 0x3F000000,
292  };
293  
294  /* UFCS */
295  enum UFCS_BIT {
296  	UFCS_SL0	= 0x0000003F,
297  	UFCS_SL1	= 0x00003F00,
298  	UFCS_SL2	= 0x003F0000,
299  	UFCS_SL3	= 0x3F000000,
300  };
301  
302  /* UFCV0/1/2/3/4 */
303  enum UFCV_BIT {
304  	UFCV_CV0	= 0x0000003F,
305  	UFCV_CV1	= 0x00003F00,
306  	UFCV_CV2	= 0x003F0000,
307  	UFCV_CV3	= 0x3F000000,
308  };
309  
310  /* UFCD0/1/2/3/4 */
311  enum UFCD_BIT {
312  	UFCD_DV0	= 0x0000003F,
313  	UFCD_DV1	= 0x00003F00,
314  	UFCD_DV2	= 0x003F0000,
315  	UFCD_DV3	= 0x3F000000,
316  };
317  
318  /* SFO */
319  enum SFO_BIT {
320  	SFO_FBP		= 0x0000003F,
321  };
322  
323  /* RTC */
324  enum RTC_BIT {
325  	RTC_MFL0	= 0x00000FFF,
326  	RTC_MFL1	= 0x0FFF0000,
327  };
328  
329  /* TGC */
330  enum TGC_BIT {
331  	TGC_TSM0	= 0x00000001,
332  	TGC_TSM1	= 0x00000002,
333  	TGC_TSM2	= 0x00000004,
334  	TGC_TSM3	= 0x00000008,
335  	TGC_TQP		= 0x00000030,
336  	TGC_TQP_NONAVB	= 0x00000000,
337  	TGC_TQP_AVBMODE1 = 0x00000010,
338  	TGC_TQP_AVBMODE2 = 0x00000030,
339  	TGC_TBD0	= 0x00000300,
340  	TGC_TBD1	= 0x00003000,
341  	TGC_TBD2	= 0x00030000,
342  	TGC_TBD3	= 0x00300000,
343  };
344  
345  /* TCCR */
346  enum TCCR_BIT {
347  	TCCR_TSRQ0	= 0x00000001,
348  	TCCR_TSRQ1	= 0x00000002,
349  	TCCR_TSRQ2	= 0x00000004,
350  	TCCR_TSRQ3	= 0x00000008,
351  	TCCR_TFEN	= 0x00000100,
352  	TCCR_TFR	= 0x00000200,
353  };
354  
355  /* TSR */
356  enum TSR_BIT {
357  	TSR_CCS0	= 0x00000003,
358  	TSR_CCS1	= 0x0000000C,
359  	TSR_TFFL	= 0x00000700,
360  };
361  
362  /* TFA2 */
363  enum TFA2_BIT {
364  	TFA2_TSV	= 0x0000FFFF,
365  	TFA2_TST	= 0x03FF0000,
366  };
367  
368  /* DIC */
369  enum DIC_BIT {
370  	DIC_DPE1	= 0x00000002,
371  	DIC_DPE2	= 0x00000004,
372  	DIC_DPE3	= 0x00000008,
373  	DIC_DPE4	= 0x00000010,
374  	DIC_DPE5	= 0x00000020,
375  	DIC_DPE6	= 0x00000040,
376  	DIC_DPE7	= 0x00000080,
377  	DIC_DPE8	= 0x00000100,
378  	DIC_DPE9	= 0x00000200,
379  	DIC_DPE10	= 0x00000400,
380  	DIC_DPE11	= 0x00000800,
381  	DIC_DPE12	= 0x00001000,
382  	DIC_DPE13	= 0x00002000,
383  	DIC_DPE14	= 0x00004000,
384  	DIC_DPE15	= 0x00008000,
385  };
386  
387  /* DIS */
388  enum DIS_BIT {
389  	DIS_DPF1	= 0x00000002,
390  	DIS_DPF2	= 0x00000004,
391  	DIS_DPF3	= 0x00000008,
392  	DIS_DPF4	= 0x00000010,
393  	DIS_DPF5	= 0x00000020,
394  	DIS_DPF6	= 0x00000040,
395  	DIS_DPF7	= 0x00000080,
396  	DIS_DPF8	= 0x00000100,
397  	DIS_DPF9	= 0x00000200,
398  	DIS_DPF10	= 0x00000400,
399  	DIS_DPF11	= 0x00000800,
400  	DIS_DPF12	= 0x00001000,
401  	DIS_DPF13	= 0x00002000,
402  	DIS_DPF14	= 0x00004000,
403  	DIS_DPF15	= 0x00008000,
404  };
405  
406  /* EIC */
407  enum EIC_BIT {
408  	EIC_MREE	= 0x00000001,
409  	EIC_MTEE	= 0x00000002,
410  	EIC_QEE		= 0x00000004,
411  	EIC_SEE		= 0x00000008,
412  	EIC_CLLE0	= 0x00000010,
413  	EIC_CLLE1	= 0x00000020,
414  	EIC_CULE0	= 0x00000040,
415  	EIC_CULE1	= 0x00000080,
416  	EIC_TFFE	= 0x00000100,
417  };
418  
419  /* EIS */
420  enum EIS_BIT {
421  	EIS_MREF	= 0x00000001,
422  	EIS_MTEF	= 0x00000002,
423  	EIS_QEF		= 0x00000004,
424  	EIS_SEF		= 0x00000008,
425  	EIS_CLLF0	= 0x00000010,
426  	EIS_CLLF1	= 0x00000020,
427  	EIS_CULF0	= 0x00000040,
428  	EIS_CULF1	= 0x00000080,
429  	EIS_TFFF	= 0x00000100,
430  	EIS_QFS		= 0x00010000,
431  	EIS_RESERVED	= (GENMASK(31, 17) | GENMASK(15, 11)),
432  };
433  
434  /* RIC0 */
435  enum RIC0_BIT {
436  	RIC0_FRE0	= 0x00000001,
437  	RIC0_FRE1	= 0x00000002,
438  	RIC0_FRE2	= 0x00000004,
439  	RIC0_FRE3	= 0x00000008,
440  	RIC0_FRE4	= 0x00000010,
441  	RIC0_FRE5	= 0x00000020,
442  	RIC0_FRE6	= 0x00000040,
443  	RIC0_FRE7	= 0x00000080,
444  	RIC0_FRE8	= 0x00000100,
445  	RIC0_FRE9	= 0x00000200,
446  	RIC0_FRE10	= 0x00000400,
447  	RIC0_FRE11	= 0x00000800,
448  	RIC0_FRE12	= 0x00001000,
449  	RIC0_FRE13	= 0x00002000,
450  	RIC0_FRE14	= 0x00004000,
451  	RIC0_FRE15	= 0x00008000,
452  	RIC0_FRE16	= 0x00010000,
453  	RIC0_FRE17	= 0x00020000,
454  };
455  
456  /* RIC0 */
457  enum RIS0_BIT {
458  	RIS0_FRF0	= 0x00000001,
459  	RIS0_FRF1	= 0x00000002,
460  	RIS0_FRF2	= 0x00000004,
461  	RIS0_FRF3	= 0x00000008,
462  	RIS0_FRF4	= 0x00000010,
463  	RIS0_FRF5	= 0x00000020,
464  	RIS0_FRF6	= 0x00000040,
465  	RIS0_FRF7	= 0x00000080,
466  	RIS0_FRF8	= 0x00000100,
467  	RIS0_FRF9	= 0x00000200,
468  	RIS0_FRF10	= 0x00000400,
469  	RIS0_FRF11	= 0x00000800,
470  	RIS0_FRF12	= 0x00001000,
471  	RIS0_FRF13	= 0x00002000,
472  	RIS0_FRF14	= 0x00004000,
473  	RIS0_FRF15	= 0x00008000,
474  	RIS0_FRF16	= 0x00010000,
475  	RIS0_FRF17	= 0x00020000,
476  	RIS0_RESERVED	= GENMASK(31, 18),
477  };
478  
479  /* RIC1 */
480  enum RIC1_BIT {
481  	RIC1_RFWE	= 0x80000000,
482  };
483  
484  /* RIS1 */
485  enum RIS1_BIT {
486  	RIS1_RFWF	= 0x80000000,
487  };
488  
489  /* RIC2 */
490  enum RIC2_BIT {
491  	RIC2_QFE0	= 0x00000001,
492  	RIC2_QFE1	= 0x00000002,
493  	RIC2_QFE2	= 0x00000004,
494  	RIC2_QFE3	= 0x00000008,
495  	RIC2_QFE4	= 0x00000010,
496  	RIC2_QFE5	= 0x00000020,
497  	RIC2_QFE6	= 0x00000040,
498  	RIC2_QFE7	= 0x00000080,
499  	RIC2_QFE8	= 0x00000100,
500  	RIC2_QFE9	= 0x00000200,
501  	RIC2_QFE10	= 0x00000400,
502  	RIC2_QFE11	= 0x00000800,
503  	RIC2_QFE12	= 0x00001000,
504  	RIC2_QFE13	= 0x00002000,
505  	RIC2_QFE14	= 0x00004000,
506  	RIC2_QFE15	= 0x00008000,
507  	RIC2_QFE16	= 0x00010000,
508  	RIC2_QFE17	= 0x00020000,
509  	RIC2_RFFE	= 0x80000000,
510  };
511  
512  /* RIS2 */
513  enum RIS2_BIT {
514  	RIS2_QFF0	= 0x00000001,
515  	RIS2_QFF1	= 0x00000002,
516  	RIS2_QFF2	= 0x00000004,
517  	RIS2_QFF3	= 0x00000008,
518  	RIS2_QFF4	= 0x00000010,
519  	RIS2_QFF5	= 0x00000020,
520  	RIS2_QFF6	= 0x00000040,
521  	RIS2_QFF7	= 0x00000080,
522  	RIS2_QFF8	= 0x00000100,
523  	RIS2_QFF9	= 0x00000200,
524  	RIS2_QFF10	= 0x00000400,
525  	RIS2_QFF11	= 0x00000800,
526  	RIS2_QFF12	= 0x00001000,
527  	RIS2_QFF13	= 0x00002000,
528  	RIS2_QFF14	= 0x00004000,
529  	RIS2_QFF15	= 0x00008000,
530  	RIS2_QFF16	= 0x00010000,
531  	RIS2_QFF17	= 0x00020000,
532  	RIS2_RFFF	= 0x80000000,
533  	RIS2_RESERVED	= GENMASK(30, 18),
534  };
535  
536  /* TIC */
537  enum TIC_BIT {
538  	TIC_FTE0	= 0x00000001,	/* Documented for R-Car Gen3 only */
539  	TIC_FTE1	= 0x00000002,	/* Documented for R-Car Gen3 only */
540  	TIC_TFUE	= 0x00000100,
541  	TIC_TFWE	= 0x00000200,
542  };
543  
544  /* TIS */
545  enum TIS_BIT {
546  	TIS_FTF0	= 0x00000001,	/* Documented for R-Car Gen3 only */
547  	TIS_FTF1	= 0x00000002,	/* Documented for R-Car Gen3 only */
548  	TIS_TFUF	= 0x00000100,
549  	TIS_TFWF	= 0x00000200,
550  	TIS_RESERVED	= (GENMASK(31, 20) | GENMASK(15, 12) | GENMASK(7, 4))
551  };
552  
553  /* ISS */
554  enum ISS_BIT {
555  	ISS_FRS		= 0x00000001,	/* Documented for R-Car Gen3 only */
556  	ISS_FTS		= 0x00000004,	/* Documented for R-Car Gen3 only */
557  	ISS_ES		= 0x00000040,
558  	ISS_MS		= 0x00000080,
559  	ISS_TFUS	= 0x00000100,
560  	ISS_TFWS	= 0x00000200,
561  	ISS_RFWS	= 0x00001000,
562  	ISS_CGIS	= 0x00002000,
563  	ISS_DPS1	= 0x00020000,
564  	ISS_DPS2	= 0x00040000,
565  	ISS_DPS3	= 0x00080000,
566  	ISS_DPS4	= 0x00100000,
567  	ISS_DPS5	= 0x00200000,
568  	ISS_DPS6	= 0x00400000,
569  	ISS_DPS7	= 0x00800000,
570  	ISS_DPS8	= 0x01000000,
571  	ISS_DPS9	= 0x02000000,
572  	ISS_DPS10	= 0x04000000,
573  	ISS_DPS11	= 0x08000000,
574  	ISS_DPS12	= 0x10000000,
575  	ISS_DPS13	= 0x20000000,
576  	ISS_DPS14	= 0x40000000,
577  	ISS_DPS15	= 0x80000000,
578  };
579  
580  /* CIE (R-Car Gen3 only) */
581  enum CIE_BIT {
582  	CIE_CRIE	= 0x00000001,
583  	CIE_CTIE	= 0x00000100,
584  	CIE_RQFM	= 0x00010000,
585  	CIE_CL0M	= 0x00020000,
586  	CIE_RFWL	= 0x00040000,
587  	CIE_RFFL	= 0x00080000,
588  };
589  
590  /* GCCR */
591  enum GCCR_BIT {
592  	GCCR_TCR	= 0x00000003,
593  	GCCR_TCR_NOREQ	= 0x00000000, /* No request */
594  	GCCR_TCR_RESET	= 0x00000001, /* gPTP/AVTP presentation timer reset */
595  	GCCR_TCR_CAPTURE = 0x00000003, /* Capture value set in GCCR.TCSS */
596  	GCCR_LTO	= 0x00000004,
597  	GCCR_LTI	= 0x00000008,
598  	GCCR_LPTC	= 0x00000010,
599  	GCCR_LMTT	= 0x00000020,
600  	GCCR_TCSS	= 0x00000300,
601  	GCCR_TCSS_GPTP	= 0x00000000,	/* gPTP timer value */
602  	GCCR_TCSS_ADJGPTP = 0x00000100, /* Adjusted gPTP timer value */
603  	GCCR_TCSS_AVTP	= 0x00000200,	/* AVTP presentation time value */
604  };
605  
606  /* GTI */
607  enum GTI_BIT {
608  	GTI_TIV		= 0x0FFFFFFF,
609  };
610  
611  #define GTI_TIV_MAX	GTI_TIV
612  #define GTI_TIV_MIN	0x20
613  
614  /* GIC */
615  enum GIC_BIT {
616  	GIC_PTCE	= 0x00000001,	/* Documented for R-Car Gen3 only */
617  	GIC_PTME	= 0x00000004,
618  };
619  
620  /* GIS */
621  enum GIS_BIT {
622  	GIS_PTCF	= 0x00000001,	/* Documented for R-Car Gen3 only */
623  	GIS_PTMF	= 0x00000004,
624  	GIS_RESERVED	= GENMASK(15, 10),
625  };
626  
627  /* GIE (R-Car Gen3 only) */
628  enum GIE_BIT {
629  	GIE_PTCS	= 0x00000001,
630  	GIE_PTOS	= 0x00000002,
631  	GIE_PTMS0	= 0x00000004,
632  	GIE_PTMS1	= 0x00000008,
633  	GIE_PTMS2	= 0x00000010,
634  	GIE_PTMS3	= 0x00000020,
635  	GIE_PTMS4	= 0x00000040,
636  	GIE_PTMS5	= 0x00000080,
637  	GIE_PTMS6	= 0x00000100,
638  	GIE_PTMS7	= 0x00000200,
639  	GIE_ATCS0	= 0x00010000,
640  	GIE_ATCS1	= 0x00020000,
641  	GIE_ATCS2	= 0x00040000,
642  	GIE_ATCS3	= 0x00080000,
643  	GIE_ATCS4	= 0x00100000,
644  	GIE_ATCS5	= 0x00200000,
645  	GIE_ATCS6	= 0x00400000,
646  	GIE_ATCS7	= 0x00800000,
647  	GIE_ATCS8	= 0x01000000,
648  	GIE_ATCS9	= 0x02000000,
649  	GIE_ATCS10	= 0x04000000,
650  	GIE_ATCS11	= 0x08000000,
651  	GIE_ATCS12	= 0x10000000,
652  	GIE_ATCS13	= 0x20000000,
653  	GIE_ATCS14	= 0x40000000,
654  	GIE_ATCS15	= 0x80000000,
655  };
656  
657  /* GID (R-Car Gen3 only) */
658  enum GID_BIT {
659  	GID_PTCD	= 0x00000001,
660  	GID_PTOD	= 0x00000002,
661  	GID_PTMD0	= 0x00000004,
662  	GID_PTMD1	= 0x00000008,
663  	GID_PTMD2	= 0x00000010,
664  	GID_PTMD3	= 0x00000020,
665  	GID_PTMD4	= 0x00000040,
666  	GID_PTMD5	= 0x00000080,
667  	GID_PTMD6	= 0x00000100,
668  	GID_PTMD7	= 0x00000200,
669  	GID_ATCD0	= 0x00010000,
670  	GID_ATCD1	= 0x00020000,
671  	GID_ATCD2	= 0x00040000,
672  	GID_ATCD3	= 0x00080000,
673  	GID_ATCD4	= 0x00100000,
674  	GID_ATCD5	= 0x00200000,
675  	GID_ATCD6	= 0x00400000,
676  	GID_ATCD7	= 0x00800000,
677  	GID_ATCD8	= 0x01000000,
678  	GID_ATCD9	= 0x02000000,
679  	GID_ATCD10	= 0x04000000,
680  	GID_ATCD11	= 0x08000000,
681  	GID_ATCD12	= 0x10000000,
682  	GID_ATCD13	= 0x20000000,
683  	GID_ATCD14	= 0x40000000,
684  	GID_ATCD15	= 0x80000000,
685  };
686  
687  /* RIE0 (R-Car Gen3 only) */
688  enum RIE0_BIT {
689  	RIE0_FRS0	= 0x00000001,
690  	RIE0_FRS1	= 0x00000002,
691  	RIE0_FRS2	= 0x00000004,
692  	RIE0_FRS3	= 0x00000008,
693  	RIE0_FRS4	= 0x00000010,
694  	RIE0_FRS5	= 0x00000020,
695  	RIE0_FRS6	= 0x00000040,
696  	RIE0_FRS7	= 0x00000080,
697  	RIE0_FRS8	= 0x00000100,
698  	RIE0_FRS9	= 0x00000200,
699  	RIE0_FRS10	= 0x00000400,
700  	RIE0_FRS11	= 0x00000800,
701  	RIE0_FRS12	= 0x00001000,
702  	RIE0_FRS13	= 0x00002000,
703  	RIE0_FRS14	= 0x00004000,
704  	RIE0_FRS15	= 0x00008000,
705  	RIE0_FRS16	= 0x00010000,
706  	RIE0_FRS17	= 0x00020000,
707  };
708  
709  /* RID0 (R-Car Gen3 only) */
710  enum RID0_BIT {
711  	RID0_FRD0	= 0x00000001,
712  	RID0_FRD1	= 0x00000002,
713  	RID0_FRD2	= 0x00000004,
714  	RID0_FRD3	= 0x00000008,
715  	RID0_FRD4	= 0x00000010,
716  	RID0_FRD5	= 0x00000020,
717  	RID0_FRD6	= 0x00000040,
718  	RID0_FRD7	= 0x00000080,
719  	RID0_FRD8	= 0x00000100,
720  	RID0_FRD9	= 0x00000200,
721  	RID0_FRD10	= 0x00000400,
722  	RID0_FRD11	= 0x00000800,
723  	RID0_FRD12	= 0x00001000,
724  	RID0_FRD13	= 0x00002000,
725  	RID0_FRD14	= 0x00004000,
726  	RID0_FRD15	= 0x00008000,
727  	RID0_FRD16	= 0x00010000,
728  	RID0_FRD17	= 0x00020000,
729  };
730  
731  /* RIE2 (R-Car Gen3 only) */
732  enum RIE2_BIT {
733  	RIE2_QFS0	= 0x00000001,
734  	RIE2_QFS1	= 0x00000002,
735  	RIE2_QFS2	= 0x00000004,
736  	RIE2_QFS3	= 0x00000008,
737  	RIE2_QFS4	= 0x00000010,
738  	RIE2_QFS5	= 0x00000020,
739  	RIE2_QFS6	= 0x00000040,
740  	RIE2_QFS7	= 0x00000080,
741  	RIE2_QFS8	= 0x00000100,
742  	RIE2_QFS9	= 0x00000200,
743  	RIE2_QFS10	= 0x00000400,
744  	RIE2_QFS11	= 0x00000800,
745  	RIE2_QFS12	= 0x00001000,
746  	RIE2_QFS13	= 0x00002000,
747  	RIE2_QFS14	= 0x00004000,
748  	RIE2_QFS15	= 0x00008000,
749  	RIE2_QFS16	= 0x00010000,
750  	RIE2_QFS17	= 0x00020000,
751  	RIE2_RFFS	= 0x80000000,
752  };
753  
754  /* RID2 (R-Car Gen3 only) */
755  enum RID2_BIT {
756  	RID2_QFD0	= 0x00000001,
757  	RID2_QFD1	= 0x00000002,
758  	RID2_QFD2	= 0x00000004,
759  	RID2_QFD3	= 0x00000008,
760  	RID2_QFD4	= 0x00000010,
761  	RID2_QFD5	= 0x00000020,
762  	RID2_QFD6	= 0x00000040,
763  	RID2_QFD7	= 0x00000080,
764  	RID2_QFD8	= 0x00000100,
765  	RID2_QFD9	= 0x00000200,
766  	RID2_QFD10	= 0x00000400,
767  	RID2_QFD11	= 0x00000800,
768  	RID2_QFD12	= 0x00001000,
769  	RID2_QFD13	= 0x00002000,
770  	RID2_QFD14	= 0x00004000,
771  	RID2_QFD15	= 0x00008000,
772  	RID2_QFD16	= 0x00010000,
773  	RID2_QFD17	= 0x00020000,
774  	RID2_RFFD	= 0x80000000,
775  };
776  
777  /* TIE (R-Car Gen3 only) */
778  enum TIE_BIT {
779  	TIE_FTS0	= 0x00000001,
780  	TIE_FTS1	= 0x00000002,
781  	TIE_FTS2	= 0x00000004,
782  	TIE_FTS3	= 0x00000008,
783  	TIE_TFUS	= 0x00000100,
784  	TIE_TFWS	= 0x00000200,
785  	TIE_MFUS	= 0x00000400,
786  	TIE_MFWS	= 0x00000800,
787  	TIE_TDPS0	= 0x00010000,
788  	TIE_TDPS1	= 0x00020000,
789  	TIE_TDPS2	= 0x00040000,
790  	TIE_TDPS3	= 0x00080000,
791  };
792  
793  /* TID (R-Car Gen3 only) */
794  enum TID_BIT {
795  	TID_FTD0	= 0x00000001,
796  	TID_FTD1	= 0x00000002,
797  	TID_FTD2	= 0x00000004,
798  	TID_FTD3	= 0x00000008,
799  	TID_TFUD	= 0x00000100,
800  	TID_TFWD	= 0x00000200,
801  	TID_MFUD	= 0x00000400,
802  	TID_MFWD	= 0x00000800,
803  	TID_TDPD0	= 0x00010000,
804  	TID_TDPD1	= 0x00020000,
805  	TID_TDPD2	= 0x00040000,
806  	TID_TDPD3	= 0x00080000,
807  };
808  
809  /* ECMR */
810  enum ECMR_BIT {
811  	ECMR_PRM	= 0x00000001,
812  	ECMR_DM		= 0x00000002,
813  	ECMR_TE		= 0x00000020,
814  	ECMR_RE		= 0x00000040,
815  	ECMR_MPDE	= 0x00000200,
816  	ECMR_TXF	= 0x00010000,	/* Documented for R-Car Gen3 only */
817  	ECMR_RXF	= 0x00020000,
818  	ECMR_PFR	= 0x00040000,
819  	ECMR_ZPF	= 0x00080000,	/* Documented for R-Car Gen3 and RZ/G2L */
820  	ECMR_RZPF	= 0x00100000,
821  	ECMR_DPAD	= 0x00200000,
822  	ECMR_RCSC	= 0x00800000,
823  	ECMR_RCPT	= 0x02000000,	/* Documented for RZ/G2L only */
824  	ECMR_TRCCM	= 0x04000000,
825  };
826  
827  /* ECSR */
828  enum ECSR_BIT {
829  	ECSR_ICD	= 0x00000001,
830  	ECSR_MPD	= 0x00000002,
831  	ECSR_LCHNG	= 0x00000004,
832  	ECSR_PHYI	= 0x00000008,
833  	ECSR_PFRI	= 0x00000010,	/* Documented for R-Car Gen3 and RZ/G2L */
834  };
835  
836  /* ECSIPR */
837  enum ECSIPR_BIT {
838  	ECSIPR_ICDIP	= 0x00000001,
839  	ECSIPR_MPDIP	= 0x00000002,
840  	ECSIPR_LCHNGIP	= 0x00000004,
841  };
842  
843  /* PIR */
844  enum PIR_BIT {
845  	PIR_MDC		= 0x00000001,
846  	PIR_MMD		= 0x00000002,
847  	PIR_MDO		= 0x00000004,
848  	PIR_MDI		= 0x00000008,
849  };
850  
851  /* PSR */
852  enum PSR_BIT {
853  	PSR_LMON	= 0x00000001,
854  };
855  
856  /* PIPR */
857  enum PIPR_BIT {
858  	PIPR_PHYIP	= 0x00000001,
859  };
860  
861  /* MPR */
862  enum MPR_BIT {
863  	MPR_MP		= 0x0000ffff,
864  };
865  
866  /* GECMR */
867  enum GECMR_BIT {
868  	GECMR_SPEED		= 0x00000001,
869  	GECMR_SPEED_100		= 0x00000000,
870  	GECMR_SPEED_1000	= 0x00000001,
871  	GBETH_GECMR_SPEED	= 0x00000030,
872  	GBETH_GECMR_SPEED_10	= 0x00000000,
873  	GBETH_GECMR_SPEED_100	= 0x00000010,
874  	GBETH_GECMR_SPEED_1000	= 0x00000020,
875  };
876  
877  /* The Ethernet AVB descriptor definitions. */
878  struct ravb_desc {
879  	__le16 ds;	/* Descriptor size */
880  	u8 cc;		/* Content control MSBs (reserved) */
881  	u8 die_dt;	/* Descriptor interrupt enable and type */
882  	__le32 dptr;	/* Descriptor pointer */
883  };
884  
885  #define DPTR_ALIGN	4	/* Required descriptor pointer alignment */
886  
887  enum DIE_DT {
888  	/* Frame data */
889  	DT_FMID		= 0x40,
890  	DT_FSTART	= 0x50,
891  	DT_FEND		= 0x60,
892  	DT_FSINGLE	= 0x70,
893  	/* Chain control */
894  	DT_LINK		= 0x80,
895  	DT_LINKFIX	= 0x90,
896  	DT_EOS		= 0xa0,
897  	/* HW/SW arbitration */
898  	DT_FEMPTY	= 0xc0,
899  	DT_FEMPTY_IS	= 0xd0,
900  	DT_FEMPTY_IC	= 0xe0,
901  	DT_FEMPTY_ND	= 0xf0,
902  	DT_LEMPTY	= 0x20,
903  	DT_EEMPTY	= 0x30,
904  };
905  
906  struct ravb_rx_desc {
907  	__le16 ds_cc;	/* Descriptor size and content control LSBs */
908  	u8 msc;		/* MAC status code */
909  	u8 die_dt;	/* Descriptor interrupt enable and type */
910  	__le32 dptr;	/* Descpriptor pointer */
911  };
912  
913  struct ravb_ex_rx_desc {
914  	__le16 ds_cc;	/* Descriptor size and content control lower bits */
915  	u8 msc;		/* MAC status code */
916  	u8 die_dt;	/* Descriptor interrupt enable and type */
917  	__le32 dptr;	/* Descpriptor pointer */
918  	__le32 ts_n;	/* Timestampe nsec */
919  	__le32 ts_sl;	/* Timestamp low */
920  	__le16 ts_sh;	/* Timestamp high */
921  	__le16 res;	/* Reserved bits */
922  };
923  
924  enum RX_DS_CC_BIT {
925  	RX_DS		= 0x0fff, /* Data size */
926  	RX_TR		= 0x1000, /* Truncation indication */
927  	RX_EI		= 0x2000, /* Error indication */
928  	RX_PS		= 0xc000, /* Padding selection */
929  };
930  
931  /* E-MAC status code */
932  enum MSC_BIT {
933  	MSC_CRC		= 0x01, /* Frame CRC error */
934  	MSC_RFE		= 0x02, /* Frame reception error (flagged by PHY) */
935  	MSC_RTSF	= 0x04, /* Frame length error (frame too short) */
936  	MSC_RTLF	= 0x08, /* Frame length error (frame too long) */
937  	MSC_FRE		= 0x10, /* Fraction error (not a multiple of 8 bits) */
938  	MSC_CRL		= 0x20, /* Carrier lost */
939  	MSC_CEEF	= 0x40, /* Carrier extension error */
940  	MSC_MC		= 0x80, /* Multicast frame reception */
941  };
942  
943  struct ravb_tx_desc {
944  	__le16 ds_tagl;	/* Descriptor size and frame tag LSBs */
945  	u8 tagh_tsr;	/* Frame tag MSBs and timestamp storage request bit */
946  	u8 die_dt;	/* Descriptor interrupt enable and type */
947  	__le32 dptr;	/* Descpriptor pointer */
948  };
949  
950  enum TX_DS_TAGL_BIT {
951  	TX_DS		= 0x0fff, /* Data size */
952  	TX_TAGL		= 0xf000, /* Frame tag LSBs */
953  };
954  
955  enum TX_TAGH_TSR_BIT {
956  	TX_TAGH		= 0x3f, /* Frame tag MSBs */
957  	TX_TSR		= 0x40, /* Timestamp storage request */
958  };
959  enum RAVB_QUEUE {
960  	RAVB_BE = 0,	/* Best Effort Queue */
961  	RAVB_NC,	/* Network Control Queue */
962  };
963  
964  enum CXR31_BIT {
965  	CXR31_SEL_LINK0	= 0x00000001,
966  	CXR31_SEL_LINK1	= 0x00000008,
967  };
968  
969  enum CXR35_BIT {
970  	CXR35_SEL_XMII		= 0x00000003,
971  	CXR35_SEL_XMII_RGMII	= 0x00000000,
972  	CXR35_SEL_XMII_MII	= 0x00000002,
973  	CXR35_HALFCYC_CLKSW	= 0xffff0000,
974  };
975  
976  enum CSR0_BIT {
977  	CSR0_TPE	= 0x00000010,
978  	CSR0_RPE	= 0x00000020,
979  };
980  
981  #define DBAT_ENTRY_NUM	22
982  #define RX_QUEUE_OFFSET	4
983  #define NUM_RX_QUEUE	2
984  #define NUM_TX_QUEUE	2
985  
986  #define RX_BUF_SZ	(2048 - ETH_FCS_LEN + sizeof(__sum16))
987  
988  #define GBETH_RX_BUFF_MAX 8192
989  #define GBETH_RX_DESC_DATA_SIZE 4080
990  
991  struct ravb_tstamp_skb {
992  	struct list_head list;
993  	struct sk_buff *skb;
994  	u16 tag;
995  };
996  
997  struct ravb_ptp_perout {
998  	u32 target;
999  	u32 period;
1000  };
1001  
1002  #define N_EXT_TS	1
1003  #define N_PER_OUT	1
1004  
1005  struct ravb_ptp {
1006  	struct ptp_clock *clock;
1007  	struct ptp_clock_info info;
1008  	u32 default_addend;
1009  	u32 current_addend;
1010  	int extts[N_EXT_TS];
1011  	struct ravb_ptp_perout perout[N_PER_OUT];
1012  };
1013  
1014  struct ravb_hw_info {
1015  	void (*rx_ring_free)(struct net_device *ndev, int q);
1016  	void (*rx_ring_format)(struct net_device *ndev, int q);
1017  	void *(*alloc_rx_desc)(struct net_device *ndev, int q);
1018  	bool (*receive)(struct net_device *ndev, int *quota, int q);
1019  	void (*set_rate)(struct net_device *ndev);
1020  	int (*set_feature)(struct net_device *ndev, netdev_features_t features);
1021  	int (*dmac_init)(struct net_device *ndev);
1022  	void (*emac_init)(struct net_device *ndev);
1023  	const char (*gstrings_stats)[ETH_GSTRING_LEN];
1024  	size_t gstrings_size;
1025  	netdev_features_t net_hw_features;
1026  	netdev_features_t net_features;
1027  	int stats_len;
1028  	size_t max_rx_len;
1029  	u32 tccr_mask;
1030  	u32 rx_max_buf_size;
1031  	unsigned aligned_tx: 1;
1032  
1033  	/* hardware features */
1034  	unsigned internal_delay:1;	/* AVB-DMAC has internal delays */
1035  	unsigned tx_counters:1;		/* E-MAC has TX counters */
1036  	unsigned carrier_counters:1;	/* E-MAC has carrier counters */
1037  	unsigned multi_irqs:1;		/* AVB-DMAC and E-MAC has multiple irqs */
1038  	unsigned irq_en_dis:1;		/* Has separate irq enable and disable regs */
1039  	unsigned err_mgmt_irqs:1;	/* Line1 (Err) and Line2 (Mgmt) irqs are separate */
1040  	unsigned gptp:1;		/* AVB-DMAC has gPTP support */
1041  	unsigned ccc_gac:1;		/* AVB-DMAC has gPTP support active in config mode */
1042  	unsigned gptp_ref_clk:1;	/* gPTP has separate reference clock */
1043  	unsigned nc_queues:1;		/* AVB-DMAC has RX and TX NC queues */
1044  	unsigned magic_pkt:1;		/* E-MAC supports magic packet detection */
1045  	unsigned half_duplex:1;		/* E-MAC supports half duplex mode */
1046  };
1047  
1048  struct ravb_private {
1049  	struct net_device *ndev;
1050  	struct platform_device *pdev;
1051  	void __iomem *addr;
1052  	struct clk *clk;
1053  	struct clk *refclk;
1054  	struct clk *gptp_clk;
1055  	struct mdiobb_ctrl mdiobb;
1056  	u32 num_rx_ring[NUM_RX_QUEUE];
1057  	u32 num_tx_ring[NUM_TX_QUEUE];
1058  	u32 desc_bat_size;
1059  	dma_addr_t desc_bat_dma;
1060  	struct ravb_desc *desc_bat;
1061  	dma_addr_t rx_desc_dma[NUM_RX_QUEUE];
1062  	dma_addr_t tx_desc_dma[NUM_TX_QUEUE];
1063  	struct ravb_rx_desc *gbeth_rx_ring;
1064  	struct ravb_ex_rx_desc *rx_ring[NUM_RX_QUEUE];
1065  	struct ravb_tx_desc *tx_ring[NUM_TX_QUEUE];
1066  	void *tx_align[NUM_TX_QUEUE];
1067  	struct sk_buff *rx_1st_skb;
1068  	struct sk_buff **rx_skb[NUM_RX_QUEUE];
1069  	struct sk_buff **tx_skb[NUM_TX_QUEUE];
1070  	u32 rx_over_errors;
1071  	u32 rx_fifo_errors;
1072  	struct net_device_stats stats[NUM_RX_QUEUE];
1073  	u32 tstamp_tx_ctrl;
1074  	u32 tstamp_rx_ctrl;
1075  	struct list_head ts_skb_list;
1076  	u32 ts_skb_tag;
1077  	struct ravb_ptp ptp;
1078  	spinlock_t lock;		/* Register access lock */
1079  	u32 cur_rx[NUM_RX_QUEUE];	/* Consumer ring indices */
1080  	u32 dirty_rx[NUM_RX_QUEUE];	/* Producer ring indices */
1081  	u32 cur_tx[NUM_TX_QUEUE];
1082  	u32 dirty_tx[NUM_TX_QUEUE];
1083  	struct napi_struct napi[NUM_RX_QUEUE];
1084  	struct work_struct work;
1085  	/* MII transceiver section. */
1086  	struct mii_bus *mii_bus;	/* MDIO bus control */
1087  	int link;
1088  	phy_interface_t phy_interface;
1089  	int msg_enable;
1090  	int speed;
1091  	int emac_irq;
1092  	int erra_irq;
1093  	int mgmta_irq;
1094  	int rx_irqs[NUM_RX_QUEUE];
1095  	int tx_irqs[NUM_TX_QUEUE];
1096  
1097  	unsigned no_avb_link:1;
1098  	unsigned avb_link_active_low:1;
1099  	unsigned wol_enabled:1;
1100  	unsigned rxcidm:1;		/* RX Clock Internal Delay Mode */
1101  	unsigned txcidm:1;		/* TX Clock Internal Delay Mode */
1102  	unsigned rgmii_override:1;	/* Deprecated rgmii-*id behavior */
1103  	unsigned int num_tx_desc;	/* TX descriptors per packet */
1104  
1105  	int duplex;
1106  
1107  	const struct ravb_hw_info *info;
1108  	struct reset_control *rstc;
1109  };
1110  
ravb_read(struct net_device * ndev,enum ravb_reg reg)1111  static inline u32 ravb_read(struct net_device *ndev, enum ravb_reg reg)
1112  {
1113  	struct ravb_private *priv = netdev_priv(ndev);
1114  
1115  	return ioread32(priv->addr + reg);
1116  }
1117  
ravb_write(struct net_device * ndev,u32 data,enum ravb_reg reg)1118  static inline void ravb_write(struct net_device *ndev, u32 data,
1119  			      enum ravb_reg reg)
1120  {
1121  	struct ravb_private *priv = netdev_priv(ndev);
1122  
1123  	iowrite32(data, priv->addr + reg);
1124  }
1125  
1126  void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear,
1127  		 u32 set);
1128  int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value);
1129  
1130  void ravb_ptp_interrupt(struct net_device *ndev);
1131  void ravb_ptp_init(struct net_device *ndev, struct platform_device *pdev);
1132  void ravb_ptp_stop(struct net_device *ndev);
1133  
1134  #endif	/* #ifndef __RAVB_H__ */
1135