xref: /openbmc/linux/arch/parisc/kernel/perf_asm.S (revision 75bf465f0bc33e9b776a46d6a1b9b990f5fb7c37) 
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 /*    low-level asm for "intrigue" (PA8500-8700 CPU perf counters)
4  *
5  *    Copyright (C) 2001 Randolph Chung <tausq at parisc-linux.org>
6  *    Copyright (C) 2001 Hewlett-Packard (Grant Grundler)
7  */
8 
9 #include <asm/assembly.h>
10 
11 #include <linux/init.h>
12 #include <linux/linkage.h>
13 
14 #ifdef CONFIG_64BIT
15 	.level		2.0w
16 #endif /* CONFIG_64BIT */
17 
18 #define MTDIAG_1(gr)    .word 0x14201840 + gr*0x10000
19 #define MTDIAG_2(gr)    .word 0x14401840 + gr*0x10000
20 #define MFDIAG_1(gr)    .word 0x142008A0 + gr
21 #define MFDIAG_2(gr)    .word 0x144008A0 + gr
22 #define STDIAG(dr)      .word 0x14000AA0 + dr*0x200000
23 #define SFDIAG(dr)      .word 0x14000BA0 + dr*0x200000
24 #define DR2_SLOW_RET    53
25 
26 
27 ;
28 ; Enable the performance counters
29 ;
30 ; The coprocessor only needs to be enabled when
31 ; starting/stopping the coprocessor with the pmenb/pmdis.
32 ;
33 	.text
34 
35 ENTRY(perf_intrigue_enable_perf_counters)
36 	.proc
37 	.callinfo  frame=0,NO_CALLS
38 	.entry
39 
40 	ldi     0x20,%r25                ; load up perfmon bit
41 	mfctl   ccr,%r26                 ; get coprocessor register
42 	or      %r25,%r26,%r26             ; set bit
43 	mtctl   %r26,ccr                 ; turn on performance coprocessor
44 	pmenb                           ; enable performance monitor
45 	ssm     0,0                     ; dummy op to ensure completion
46 	sync                            ; follow ERS
47 	andcm   %r26,%r25,%r26             ; clear bit now
48 	mtctl   %r26,ccr                 ; turn off performance coprocessor
49 	nop                             ; NOPs as specified in ERS
50 	nop
51 	nop
52 	nop
53 	nop
54 	nop
55 	nop
56 	bve    (%r2)
57 	nop
58 	.exit
59 	.procend
60 ENDPROC(perf_intrigue_enable_perf_counters)
61 
62 ENTRY(perf_intrigue_disable_perf_counters)
63 	.proc
64 	.callinfo  frame=0,NO_CALLS
65 	.entry
66 	ldi     0x20,%r25                ; load up perfmon bit
67 	mfctl   ccr,%r26                 ; get coprocessor register
68 	or      %r25,%r26,%r26             ; set bit
69 	mtctl   %r26,ccr                 ; turn on performance coprocessor
70 	pmdis                           ; disable performance monitor
71 	ssm     0,0                     ; dummy op to ensure completion
72 	andcm   %r26,%r25,%r26             ; clear bit now
73 	bve    (%r2)
74 	mtctl   %r26,ccr                 ; turn off performance coprocessor
75 	.exit
76 	.procend
77 ENDPROC(perf_intrigue_disable_perf_counters)
78 
79 ;***********************************************************************
80 ;*
81 ;* Name: perf_rdr_shift_in_W
82 ;*
83 ;* Description:
84 ;*	This routine shifts data in from the RDR in arg0 and returns
85 ;*	the result in ret0.  If the RDR is <= 64 bits in length, it
86 ;*	is shifted shifted backup immediately.  This is to compensate
87 ;*	for RDR10 which has bits that preclude PDC stack operations
88 ;*	when they are in the wrong state.
89 ;*
90 ;* Arguments:
91 ;*	arg0 : rdr to be read
92 ;*	arg1 : bit length of rdr
93 ;*
94 ;* Returns:
95 ;*	ret0 = next 64 bits of rdr data from staging register
96 ;*
97 ;* Register usage:
98 ;*	arg0 : rdr to be read
99 ;*	arg1 : bit length of rdr
100 ;*	%r24  - original DR2 value
101 ;*	%r1   - scratch
102 ;*  %r29  - scratch
103 ;*
104 ;* Returns:
105 ;*	ret0 = RDR data (right justified)
106 ;*
107 ;***********************************************************************
108 
109 ENTRY(perf_rdr_shift_in_W)
110 	.proc
111 	.callinfo frame=0,NO_CALLS
112 	.entry
113 ;
114 ; read(shift in) the RDR.
115 ;
116 
117 ; NOTE: The PCX-W ERS states that DR2_SLOW_RET must be set before any
118 ; shifting is done, from or to, remote diagnose registers.
119 ;
120 
121 	depdi,z		1,DR2_SLOW_RET,1,%r29
122 	MFDIAG_2	(24)
123 	or		    %r24,%r29,%r29
124 	MTDIAG_2	(29)			; set DR2_SLOW_RET
125 
126 	nop
127 	nop
128 	nop
129 	nop
130 
131 ;
132 ; Cacheline start (32-byte cacheline)
133 ;
134 	nop
135 	nop
136 	nop
137 	extrd,u		arg1,63,6,%r1	; setup shift amount by bits to move
138 
139 	mtsar		%r1
140 	shladd		arg0,2,%r0,%r1	; %r1 = 4 * RDR number
141 	blr  		%r1,%r0		; branch to 8-instruction sequence
142 	nop
143 
144 ;
145 ; Cacheline start (32-byte cacheline)
146 ;
147 
148 	;
149 	; RDR 0 sequence
150 	;
151 	SFDIAG		(0)
152 	ssm		    0,0
153 	MFDIAG_1	(28)
154 	shrpd		ret0,%r0,%sar,%r1
155 	MTDIAG_1	(1)			; mtdiag %dr1, %r1
156 	STDIAG		(0)
157 	ssm		    0,0
158 	b,n         perf_rdr_shift_in_W_leave
159 
160 	;
161 	; RDR 1 sequence
162 	;
163 	sync
164 	ssm		    0,0
165 	SFDIAG		(1)
166 	ssm		    0,0
167 	MFDIAG_1	(28)
168 	ssm		    0,0
169 	b,n         perf_rdr_shift_in_W_leave
170 	nop
171 
172 	;
173 	; RDR 2 read sequence
174 	;
175 	SFDIAG		(2)
176 	ssm		    0,0
177 	MFDIAG_1	(28)
178 	shrpd		ret0,%r0,%sar,%r1
179 	MTDIAG_1	(1)
180 	STDIAG		(2)
181 	ssm		    0,0
182 	b,n         perf_rdr_shift_in_W_leave
183 
184 	;
185 	; RDR 3 read sequence
186 	;
187 	b,n         perf_rdr_shift_in_W_leave
188 	nop
189 	nop
190 	nop
191 	nop
192 	nop
193 	nop
194 	nop
195 
196 	;
197 	; RDR 4 read sequence
198 	;
199 	sync
200 	ssm		0,0
201 	SFDIAG		(4)
202 	ssm		0,0
203 	MFDIAG_1	(28)
204 	b,n         perf_rdr_shift_in_W_leave
205 	ssm		0,0
206 	nop
207 
208 	;
209 	; RDR 5 read sequence
210 	;
211 	sync
212 	ssm		0,0
213 	SFDIAG		(5)
214 	ssm		0,0
215 	MFDIAG_1	(28)
216 	b,n         perf_rdr_shift_in_W_leave
217 	ssm		0,0
218 	nop
219 
220 	;
221 	; RDR 6 read sequence
222 	;
223 	sync
224 	ssm		0,0
225 	SFDIAG		(6)
226 	ssm		0,0
227 	MFDIAG_1	(28)
228 	b,n         perf_rdr_shift_in_W_leave
229 	ssm		0,0
230 	nop
231 
232 	;
233 	; RDR 7 read sequence
234 	;
235 	b,n         perf_rdr_shift_in_W_leave
236 	nop
237 	nop
238 	nop
239 	nop
240 	nop
241 	nop
242 	nop
243 
244 	;
245 	; RDR 8 read sequence
246 	;
247 	b,n         perf_rdr_shift_in_W_leave
248 	nop
249 	nop
250 	nop
251 	nop
252 	nop
253 	nop
254 	nop
255 
256 	;
257 	; RDR 9 read sequence
258 	;
259 	b,n         perf_rdr_shift_in_W_leave
260 	nop
261 	nop
262 	nop
263 	nop
264 	nop
265 	nop
266 	nop
267 
268 	;
269 	; RDR 10 read sequence
270 	;
271 	SFDIAG		(10)
272 	ssm		0,0
273 	MFDIAG_1	(28)
274 	shrpd		ret0,%r0,%sar,%r1
275 	MTDIAG_1	(1)
276 	STDIAG		(10)
277 	ssm		0,0
278 	b,n         perf_rdr_shift_in_W_leave
279 
280 	;
281 	; RDR 11 read sequence
282 	;
283 	SFDIAG		(11)
284 	ssm		0,0
285 	MFDIAG_1	(28)
286 	shrpd		ret0,%r0,%sar,%r1
287 	MTDIAG_1	(1)
288 	STDIAG		(11)
289 	ssm		0,0
290 	b,n         perf_rdr_shift_in_W_leave
291 
292 	;
293 	; RDR 12 read sequence
294 	;
295 	b,n         perf_rdr_shift_in_W_leave
296 	nop
297 	nop
298 	nop
299 	nop
300 	nop
301 	nop
302 	nop
303 
304 	;
305 	; RDR 13 read sequence
306 	;
307 	sync
308 	ssm		0,0
309 	SFDIAG		(13)
310 	ssm		0,0
311 	MFDIAG_1	(28)
312 	b,n         perf_rdr_shift_in_W_leave
313 	ssm		0,0
314 	nop
315 
316 	;
317 	; RDR 14 read sequence
318 	;
319 	SFDIAG		(14)
320 	ssm		0,0
321 	MFDIAG_1	(28)
322 	shrpd		ret0,%r0,%sar,%r1
323 	MTDIAG_1	(1)
324 	STDIAG		(14)
325 	ssm		0,0
326 	b,n         perf_rdr_shift_in_W_leave
327 
328 	;
329 	; RDR 15 read sequence
330 	;
331 	sync
332 	ssm		0,0
333 	SFDIAG		(15)
334 	ssm		0,0
335 	MFDIAG_1	(28)
336 	ssm		0,0
337 	b,n         perf_rdr_shift_in_W_leave
338 	nop
339 
340 	;
341 	; RDR 16 read sequence
342 	;
343 	sync
344 	ssm		0,0
345 	SFDIAG		(16)
346 	ssm		0,0
347 	MFDIAG_1	(28)
348 	b,n         perf_rdr_shift_in_W_leave
349 	ssm		0,0
350 	nop
351 
352 	;
353 	; RDR 17 read sequence
354 	;
355 	SFDIAG		(17)
356 	ssm		0,0
357 	MFDIAG_1	(28)
358 	shrpd		ret0,%r0,%sar,%r1
359 	MTDIAG_1	(1)
360 	STDIAG		(17)
361 	ssm		0,0
362 	b,n         perf_rdr_shift_in_W_leave
363 
364 	;
365 	; RDR 18 read sequence
366 	;
367 	SFDIAG		(18)
368 	ssm		0,0
369 	MFDIAG_1	(28)
370 	shrpd		ret0,%r0,%sar,%r1
371 	MTDIAG_1	(1)
372 	STDIAG		(18)
373 	ssm		0,0
374 	b,n         perf_rdr_shift_in_W_leave
375 
376 	;
377 	; RDR 19 read sequence
378 	;
379 	b,n         perf_rdr_shift_in_W_leave
380 	nop
381 	nop
382 	nop
383 	nop
384 	nop
385 	nop
386 	nop
387 
388 	;
389 	; RDR 20 read sequence
390 	;
391 	sync
392 	ssm		0,0
393 	SFDIAG		(20)
394 	ssm		0,0
395 	MFDIAG_1	(28)
396 	b,n         perf_rdr_shift_in_W_leave
397 	ssm		0,0
398 	nop
399 
400 	;
401 	; RDR 21 read sequence
402 	;
403 	sync
404 	ssm		0,0
405 	SFDIAG		(21)
406 	ssm		0,0
407 	MFDIAG_1	(28)
408 	b,n         perf_rdr_shift_in_W_leave
409 	ssm		0,0
410 	nop
411 
412 	;
413 	; RDR 22 read sequence
414 	;
415 	sync
416 	ssm		0,0
417 	SFDIAG		(22)
418 	ssm		0,0
419 	MFDIAG_1	(28)
420 	b,n         perf_rdr_shift_in_W_leave
421 	ssm		0,0
422 	nop
423 
424 	;
425 	; RDR 23 read sequence
426 	;
427 	sync
428 	ssm		0,0
429 	SFDIAG		(23)
430 	ssm		0,0
431 	MFDIAG_1	(28)
432 	b,n         perf_rdr_shift_in_W_leave
433 	ssm		0,0
434 	nop
435 
436 	;
437 	; RDR 24 read sequence
438 	;
439 	sync
440 	ssm		0,0
441 	SFDIAG		(24)
442 	ssm		0,0
443 	MFDIAG_1	(28)
444 	b,n         perf_rdr_shift_in_W_leave
445 	ssm		0,0
446 	nop
447 
448 	;
449 	; RDR 25 read sequence
450 	;
451 	sync
452 	ssm		0,0
453 	SFDIAG		(25)
454 	ssm		0,0
455 	MFDIAG_1	(28)
456 	b,n         perf_rdr_shift_in_W_leave
457 	ssm		0,0
458 	nop
459 
460 	;
461 	; RDR 26 read sequence
462 	;
463 	SFDIAG		(26)
464 	ssm		0,0
465 	MFDIAG_1	(28)
466 	shrpd		ret0,%r0,%sar,%r1
467 	MTDIAG_1	(1)
468 	STDIAG		(26)
469 	ssm		0,0
470 	b,n         perf_rdr_shift_in_W_leave
471 
472 	;
473 	; RDR 27 read sequence
474 	;
475 	SFDIAG		(27)
476 	ssm		0,0
477 	MFDIAG_1	(28)
478 	shrpd		ret0,%r0,%sar,%r1
479 	MTDIAG_1	(1)
480 	STDIAG		(27)
481 	ssm		0,0
482 	b,n         perf_rdr_shift_in_W_leave
483 
484 	;
485 	; RDR 28 read sequence
486 	;
487 	sync
488 	ssm		0,0
489 	SFDIAG		(28)
490 	ssm		0,0
491 	MFDIAG_1	(28)
492 	b,n         perf_rdr_shift_in_W_leave
493 	ssm		0,0
494 	nop
495 
496 	;
497 	; RDR 29 read sequence
498 	;
499 	sync
500 	ssm		0,0
501 	SFDIAG		(29)
502 	ssm		0,0
503 	MFDIAG_1	(28)
504 	b,n         perf_rdr_shift_in_W_leave
505 	ssm		0,0
506 	nop
507 
508 	;
509 	; RDR 30 read sequence
510 	;
511 	SFDIAG		(30)
512 	ssm		0,0
513 	MFDIAG_1	(28)
514 	shrpd		ret0,%r0,%sar,%r1
515 	MTDIAG_1	(1)
516 	STDIAG		(30)
517 	ssm		0,0
518 	b,n         perf_rdr_shift_in_W_leave
519 
520 	;
521 	; RDR 31 read sequence
522 	;
523 	sync
524 	ssm		0,0
525 	SFDIAG		(31)
526 	ssm		0,0
527 	MFDIAG_1	(28)
528 	nop
529 	ssm		0,0
530 	nop
531 
532 	;
533 	; Fallthrough
534 	;
535 
536 perf_rdr_shift_in_W_leave:
537 	bve		    (%r2)
538 	.exit
539 	MTDIAG_2	(24)			; restore DR2
540 	.procend
541 ENDPROC(perf_rdr_shift_in_W)
542 
543 
544 ;***********************************************************************
545 ;*
546 ;* Name: perf_rdr_shift_out_W
547 ;*
548 ;* Description:
549 ;*	This routine moves data to the RDR's.  The double-word that
550 ;*	arg1 points to is loaded and moved into the staging register.
551 ;*	Then the STDIAG instruction for the RDR # in arg0 is called
552 ;*	to move the data to the RDR.
553 ;*
554 ;* Arguments:
555 ;*	arg0 = rdr number
556 ;*	arg1 = 64-bit value to write
557 ;*	%r24 - DR2 | DR2_SLOW_RET
558 ;*	%r23 - original DR2 value
559 ;*
560 ;* Returns:
561 ;*	None
562 ;*
563 ;* Register usage:
564 ;*
565 ;***********************************************************************
566 
567 ENTRY(perf_rdr_shift_out_W)
568 	.proc
569 	.callinfo frame=0,NO_CALLS
570 	.entry
571 ;
572 ; NOTE: The PCX-W ERS states that DR2_SLOW_RET must be set before any
573 ; shifting is done, from or to, the remote diagnose registers.
574 ;
575 
576 	depdi,z		1,DR2_SLOW_RET,1,%r24
577 	MFDIAG_2	(23)
578 	or		%r24,%r23,%r24
579 	MTDIAG_2	(24)		; set DR2_SLOW_RET
580 	MTDIAG_1	(25)		; data to the staging register
581 	shladd		arg0,2,%r0,%r1	; %r1 = 4 * RDR number
582 	blr		    %r1,%r0	; branch to 8-instruction sequence
583 	nop
584 
585 	;
586 	; RDR 0 write sequence
587 	;
588 	sync				; RDR 0 write sequence
589 	ssm		0,0
590 	STDIAG		(0)
591 	ssm		0,0
592 	b,n         perf_rdr_shift_out_W_leave
593 	nop
594 	ssm		0,0
595 	nop
596 
597 	;
598 	; RDR 1 write sequence
599 	;
600 	sync
601 	ssm		0,0
602 	STDIAG		(1)
603 	ssm		0,0
604 	b,n         perf_rdr_shift_out_W_leave
605 	nop
606 	ssm		0,0
607 	nop
608 
609 	;
610 	; RDR 2 write sequence
611 	;
612 	sync
613 	ssm		0,0
614 	STDIAG		(2)
615 	ssm		0,0
616 	b,n         perf_rdr_shift_out_W_leave
617 	nop
618 	ssm		0,0
619 	nop
620 
621 	;
622 	; RDR 3 write sequence
623 	;
624 	sync
625 	ssm		0,0
626 	STDIAG		(3)
627 	ssm		0,0
628 	b,n         perf_rdr_shift_out_W_leave
629 	nop
630 	ssm		0,0
631 	nop
632 
633 	;
634 	; RDR 4 write sequence
635 	;
636 	sync
637 	ssm		0,0
638 	STDIAG		(4)
639 	ssm		0,0
640 	b,n         perf_rdr_shift_out_W_leave
641 	nop
642 	ssm		0,0
643 	nop
644 
645 	;
646 	; RDR 5 write sequence
647 	;
648 	sync
649 	ssm		0,0
650 	STDIAG		(5)
651 	ssm		0,0
652 	b,n         perf_rdr_shift_out_W_leave
653 	nop
654 	ssm		0,0
655 	nop
656 
657 	;
658 	; RDR 6 write sequence
659 	;
660 	sync
661 	ssm		0,0
662 	STDIAG		(6)
663 	ssm		0,0
664 	b,n         perf_rdr_shift_out_W_leave
665 	nop
666 	ssm		0,0
667 	nop
668 
669 	;
670 	; RDR 7 write sequence
671 	;
672 	sync
673 	ssm		0,0
674 	STDIAG		(7)
675 	ssm		0,0
676 	b,n         perf_rdr_shift_out_W_leave
677 	nop
678 	ssm		0,0
679 	nop
680 
681 	;
682 	; RDR 8 write sequence
683 	;
684 	sync
685 	ssm		0,0
686 	STDIAG		(8)
687 	ssm		0,0
688 	b,n         perf_rdr_shift_out_W_leave
689 	nop
690 	ssm		0,0
691 	nop
692 
693 	;
694 	; RDR 9 write sequence
695 	;
696 	sync
697 	ssm		0,0
698 	STDIAG		(9)
699 	ssm		0,0
700 	b,n         perf_rdr_shift_out_W_leave
701 	nop
702 	ssm		0,0
703 	nop
704 
705 	;
706 	; RDR 10 write sequence
707 	;
708 	sync
709 	ssm		0,0
710 	STDIAG		(10)
711 	STDIAG		(26)
712 	ssm		0,0
713 	b,n         perf_rdr_shift_out_W_leave
714 	ssm		0,0
715 	nop
716 
717 	;
718 	; RDR 11 write sequence
719 	;
720 	sync
721 	ssm		0,0
722 	STDIAG		(11)
723 	STDIAG		(27)
724 	ssm		0,0
725 	b,n         perf_rdr_shift_out_W_leave
726 	ssm		0,0
727 	nop
728 
729 	;
730 	; RDR 12 write sequence
731 	;
732 	sync
733 	ssm		0,0
734 	STDIAG		(12)
735 	ssm		0,0
736 	b,n         perf_rdr_shift_out_W_leave
737 	nop
738 	ssm		0,0
739 	nop
740 
741 	;
742 	; RDR 13 write sequence
743 	;
744 	sync
745 	ssm		0,0
746 	STDIAG		(13)
747 	ssm		0,0
748 	b,n         perf_rdr_shift_out_W_leave
749 	nop
750 	ssm		0,0
751 	nop
752 
753 	;
754 	; RDR 14 write sequence
755 	;
756 	sync
757 	ssm		0,0
758 	STDIAG		(14)
759 	ssm		0,0
760 	b,n         perf_rdr_shift_out_W_leave
761 	nop
762 	ssm		0,0
763 	nop
764 
765 	;
766 	; RDR 15 write sequence
767 	;
768 	sync
769 	ssm		0,0
770 	STDIAG		(15)
771 	ssm		0,0
772 	b,n         perf_rdr_shift_out_W_leave
773 	nop
774 	ssm		0,0
775 	nop
776 
777 	;
778 	; RDR 16 write sequence
779 	;
780 	sync
781 	ssm		0,0
782 	STDIAG		(16)
783 	ssm		0,0
784 	b,n         perf_rdr_shift_out_W_leave
785 	nop
786 	ssm		0,0
787 	nop
788 
789 	;
790 	; RDR 17 write sequence
791 	;
792 	sync
793 	ssm		0,0
794 	STDIAG		(17)
795 	ssm		0,0
796 	b,n         perf_rdr_shift_out_W_leave
797 	nop
798 	ssm		0,0
799 	nop
800 
801 	;
802 	; RDR 18 write sequence
803 	;
804 	sync
805 	ssm		0,0
806 	STDIAG		(18)
807 	ssm		0,0
808 	b,n         perf_rdr_shift_out_W_leave
809 	nop
810 	ssm		0,0
811 	nop
812 
813 	;
814 	; RDR 19 write sequence
815 	;
816 	sync
817 	ssm		0,0
818 	STDIAG		(19)
819 	ssm		0,0
820 	b,n         perf_rdr_shift_out_W_leave
821 	nop
822 	ssm		0,0
823 	nop
824 
825 	;
826 	; RDR 20 write sequence
827 	;
828 	sync
829 	ssm		0,0
830 	STDIAG		(20)
831 	ssm		0,0
832 	b,n         perf_rdr_shift_out_W_leave
833 	nop
834 	ssm		0,0
835 	nop
836 
837 	;
838 	; RDR 21 write sequence
839 	;
840 	sync
841 	ssm		0,0
842 	STDIAG		(21)
843 	ssm		0,0
844 	b,n         perf_rdr_shift_out_W_leave
845 	nop
846 	ssm		0,0
847 	nop
848 
849 	;
850 	; RDR 22 write sequence
851 	;
852 	sync
853 	ssm		0,0
854 	STDIAG		(22)
855 	ssm		0,0
856 	b,n         perf_rdr_shift_out_W_leave
857 	nop
858 	ssm		0,0
859 	nop
860 
861 	;
862 	; RDR 23 write sequence
863 	;
864 	sync
865 	ssm		0,0
866 	STDIAG		(23)
867 	ssm		0,0
868 	b,n         perf_rdr_shift_out_W_leave
869 	nop
870 	ssm		0,0
871 	nop
872 
873 	;
874 	; RDR 24 write sequence
875 	;
876 	sync
877 	ssm		0,0
878 	STDIAG		(24)
879 	ssm		0,0
880 	b,n         perf_rdr_shift_out_W_leave
881 	nop
882 	ssm		0,0
883 	nop
884 
885 	;
886 	; RDR 25 write sequence
887 	;
888 	sync
889 	ssm		0,0
890 	STDIAG		(25)
891 	ssm		0,0
892 	b,n         perf_rdr_shift_out_W_leave
893 	nop
894 	ssm		0,0
895 	nop
896 
897 	;
898 	; RDR 26 write sequence
899 	;
900 	sync
901 	ssm		0,0
902 	STDIAG		(10)
903 	STDIAG		(26)
904 	ssm		0,0
905 	b,n         perf_rdr_shift_out_W_leave
906 	ssm		0,0
907 	nop
908 
909 	;
910 	; RDR 27 write sequence
911 	;
912 	sync
913 	ssm		0,0
914 	STDIAG		(11)
915 	STDIAG		(27)
916 	ssm		0,0
917 	b,n         perf_rdr_shift_out_W_leave
918 	ssm		0,0
919 	nop
920 
921 	;
922 	; RDR 28 write sequence
923 	;
924 	sync
925 	ssm		0,0
926 	STDIAG		(28)
927 	ssm		0,0
928 	b,n         perf_rdr_shift_out_W_leave
929 	nop
930 	ssm		0,0
931 	nop
932 
933 	;
934 	; RDR 29 write sequence
935 	;
936 	sync
937 	ssm		0,0
938 	STDIAG		(29)
939 	ssm		0,0
940 	b,n         perf_rdr_shift_out_W_leave
941 	nop
942 	ssm		0,0
943 	nop
944 
945 	;
946 	; RDR 30 write sequence
947 	;
948 	sync
949 	ssm		0,0
950 	STDIAG		(30)
951 	ssm		0,0
952 	b,n         perf_rdr_shift_out_W_leave
953 	nop
954 	ssm		0,0
955 	nop
956 
957 	;
958 	; RDR 31 write sequence
959 	;
960 	sync
961 	ssm		0,0
962 	STDIAG		(31)
963 	ssm		0,0
964 	b,n         perf_rdr_shift_out_W_leave
965 	nop
966 	ssm		0,0
967 	nop
968 
969 perf_rdr_shift_out_W_leave:
970 	bve		(%r2)
971 	.exit
972 	MTDIAG_2	(23)			; restore DR2
973 	.procend
974 ENDPROC(perf_rdr_shift_out_W)
975 
976 
977 ;***********************************************************************
978 ;*
979 ;* Name: rdr_shift_in_U
980 ;*
981 ;* Description:
982 ;*	This routine shifts data in from the RDR in arg0 and returns
983 ;*	the result in ret0.  If the RDR is <= 64 bits in length, it
984 ;*	is shifted shifted backup immediately.  This is to compensate
985 ;*	for RDR10 which has bits that preclude PDC stack operations
986 ;*	when they are in the wrong state.
987 ;*
988 ;* Arguments:
989 ;*	arg0 : rdr to be read
990 ;*	arg1 : bit length of rdr
991 ;*
992 ;* Returns:
993 ;*	ret0 = next 64 bits of rdr data from staging register
994 ;*
995 ;* Register usage:
996 ;*	arg0 : rdr to be read
997 ;*	arg1 : bit length of rdr
998 ;*	%r24 - original DR2 value
999 ;*	%r23 - DR2 | DR2_SLOW_RET
1000 ;*	%r1  - scratch
1001 ;*
1002 ;***********************************************************************
1003 
1004 ENTRY(perf_rdr_shift_in_U)
1005 	.proc
1006 	.callinfo frame=0,NO_CALLS
1007 	.entry
1008 
1009 ; read(shift in) the RDR.
1010 ;
1011 ; NOTE: The PCX-U ERS states that DR2_SLOW_RET must be set before any
1012 ; shifting is done, from or to, remote diagnose registers.
1013 
1014 	depdi,z		1,DR2_SLOW_RET,1,%r29
1015 	MFDIAG_2	(24)
1016 	or			%r24,%r29,%r29
1017 	MTDIAG_2	(29)			; set DR2_SLOW_RET
1018 
1019 	nop
1020 	nop
1021 	nop
1022 	nop
1023 
1024 ;
1025 ; Start of next 32-byte cacheline
1026 ;
1027 	nop
1028 	nop
1029 	nop
1030 	extrd,u		arg1,63,6,%r1
1031 
1032 	mtsar		%r1
1033 	shladd		arg0,2,%r0,%r1	; %r1 = 4 * RDR number
1034 	blr 		%r1,%r0		; branch to 8-instruction sequence
1035 	nop
1036 
1037 ;
1038 ; Start of next 32-byte cacheline
1039 ;
1040 	SFDIAG		(0)		; RDR 0 read sequence
1041 	ssm		0,0
1042 	MFDIAG_1	(28)
1043 	shrpd		ret0,%r0,%sar,%r1
1044 	MTDIAG_1	(1)
1045 	STDIAG		(0)
1046 	ssm		0,0
1047 	b,n         perf_rdr_shift_in_U_leave
1048 
1049 	SFDIAG		(1)		; RDR 1 read sequence
1050 	ssm		0,0
1051 	MFDIAG_1	(28)
1052 	shrpd		ret0,%r0,%sar,%r1
1053 	MTDIAG_1	(1)
1054 	STDIAG		(1)
1055 	ssm		0,0
1056 	b,n         perf_rdr_shift_in_U_leave
1057 
1058 	sync				; RDR 2 read sequence
1059 	ssm		0,0
1060 	SFDIAG		(4)
1061 	ssm		0,0
1062 	MFDIAG_1	(28)
1063 	b,n         perf_rdr_shift_in_U_leave
1064 	ssm		0,0
1065 	nop
1066 
1067 	sync				; RDR 3 read sequence
1068 	ssm		0,0
1069 	SFDIAG		(3)
1070 	ssm		0,0
1071 	MFDIAG_1	(28)
1072 	b,n         perf_rdr_shift_in_U_leave
1073 	ssm		0,0
1074 	nop
1075 
1076 	sync				; RDR 4 read sequence
1077 	ssm		0,0
1078 	SFDIAG		(4)
1079 	ssm		0,0
1080 	MFDIAG_1	(28)
1081 	b,n         perf_rdr_shift_in_U_leave
1082 	ssm		0,0
1083 	nop
1084 
1085 	sync				; RDR 5 read sequence
1086 	ssm		0,0
1087 	SFDIAG		(5)
1088 	ssm		0,0
1089 	MFDIAG_1	(28)
1090 	b,n         perf_rdr_shift_in_U_leave
1091 	ssm		0,0
1092 	nop
1093 
1094 	sync				; RDR 6 read sequence
1095 	ssm		0,0
1096 	SFDIAG		(6)
1097 	ssm		0,0
1098 	MFDIAG_1	(28)
1099 	b,n         perf_rdr_shift_in_U_leave
1100 	ssm		0,0
1101 	nop
1102 
1103 	sync				; RDR 7 read sequence
1104 	ssm		0,0
1105 	SFDIAG		(7)
1106 	ssm		0,0
1107 	MFDIAG_1	(28)
1108 	b,n         perf_rdr_shift_in_U_leave
1109 	ssm		0,0
1110 	nop
1111 
1112 	b,n         perf_rdr_shift_in_U_leave
1113 	nop
1114 	nop
1115 	nop
1116 	nop
1117 	nop
1118 	nop
1119 	nop
1120 
1121 	SFDIAG		(9)		; RDR 9 read sequence
1122 	ssm		0,0
1123 	MFDIAG_1	(28)
1124 	shrpd		ret0,%r0,%sar,%r1
1125 	MTDIAG_1	(1)
1126 	STDIAG		(9)
1127 	ssm		0,0
1128 	b,n         perf_rdr_shift_in_U_leave
1129 
1130 	SFDIAG		(10)		; RDR 10 read sequence
1131 	ssm		0,0
1132 	MFDIAG_1	(28)
1133 	shrpd		ret0,%r0,%sar,%r1
1134 	MTDIAG_1	(1)
1135 	STDIAG		(10)
1136 	ssm		0,0
1137 	b,n         perf_rdr_shift_in_U_leave
1138 
1139 	SFDIAG		(11)		; RDR 11 read sequence
1140 	ssm		0,0
1141 	MFDIAG_1	(28)
1142 	shrpd		ret0,%r0,%sar,%r1
1143 	MTDIAG_1	(1)
1144 	STDIAG		(11)
1145 	ssm		0,0
1146 	b,n         perf_rdr_shift_in_U_leave
1147 
1148 	SFDIAG		(12)		; RDR 12 read sequence
1149 	ssm		0,0
1150 	MFDIAG_1	(28)
1151 	shrpd		ret0,%r0,%sar,%r1
1152 	MTDIAG_1	(1)
1153 	STDIAG		(12)
1154 	ssm		0,0
1155 	b,n         perf_rdr_shift_in_U_leave
1156 
1157 	SFDIAG		(13)		; RDR 13 read sequence
1158 	ssm		0,0
1159 	MFDIAG_1	(28)
1160 	shrpd		ret0,%r0,%sar,%r1
1161 	MTDIAG_1	(1)
1162 	STDIAG		(13)
1163 	ssm		0,0
1164 	b,n         perf_rdr_shift_in_U_leave
1165 
1166 	SFDIAG		(14)		; RDR 14 read sequence
1167 	ssm		0,0
1168 	MFDIAG_1	(28)
1169 	shrpd		ret0,%r0,%sar,%r1
1170 	MTDIAG_1	(1)
1171 	STDIAG		(14)
1172 	ssm		0,0
1173 	b,n         perf_rdr_shift_in_U_leave
1174 
1175 	SFDIAG		(15)		; RDR 15 read sequence
1176 	ssm		0,0
1177 	MFDIAG_1	(28)
1178 	shrpd		ret0,%r0,%sar,%r1
1179 	MTDIAG_1	(1)
1180 	STDIAG		(15)
1181 	ssm		0,0
1182 	b,n         perf_rdr_shift_in_U_leave
1183 
1184 	sync				; RDR 16 read sequence
1185 	ssm		0,0
1186 	SFDIAG		(16)
1187 	ssm		0,0
1188 	MFDIAG_1	(28)
1189 	b,n         perf_rdr_shift_in_U_leave
1190 	ssm		0,0
1191 	nop
1192 
1193 	SFDIAG		(17)		; RDR 17 read sequence
1194 	ssm		0,0
1195 	MFDIAG_1	(28)
1196 	shrpd		ret0,%r0,%sar,%r1
1197 	MTDIAG_1	(1)
1198 	STDIAG		(17)
1199 	ssm		0,0
1200 	b,n         perf_rdr_shift_in_U_leave
1201 
1202 	SFDIAG		(18)		; RDR 18 read sequence
1203 	ssm		0,0
1204 	MFDIAG_1	(28)
1205 	shrpd		ret0,%r0,%sar,%r1
1206 	MTDIAG_1	(1)
1207 	STDIAG		(18)
1208 	ssm		0,0
1209 	b,n         perf_rdr_shift_in_U_leave
1210 
1211 	b,n         perf_rdr_shift_in_U_leave
1212 	nop
1213 	nop
1214 	nop
1215 	nop
1216 	nop
1217 	nop
1218 	nop
1219 
1220 	sync				; RDR 20 read sequence
1221 	ssm		0,0
1222 	SFDIAG		(20)
1223 	ssm		0,0
1224 	MFDIAG_1	(28)
1225 	b,n         perf_rdr_shift_in_U_leave
1226 	ssm		0,0
1227 	nop
1228 
1229 	sync				; RDR 21 read sequence
1230 	ssm		0,0
1231 	SFDIAG		(21)
1232 	ssm		0,0
1233 	MFDIAG_1	(28)
1234 	b,n         perf_rdr_shift_in_U_leave
1235 	ssm		0,0
1236 	nop
1237 
1238 	sync				; RDR 22 read sequence
1239 	ssm		0,0
1240 	SFDIAG		(22)
1241 	ssm		0,0
1242 	MFDIAG_1	(28)
1243 	b,n         perf_rdr_shift_in_U_leave
1244 	ssm		0,0
1245 	nop
1246 
1247 	sync				; RDR 23 read sequence
1248 	ssm		0,0
1249 	SFDIAG		(23)
1250 	ssm		0,0
1251 	MFDIAG_1	(28)
1252 	b,n         perf_rdr_shift_in_U_leave
1253 	ssm		0,0
1254 	nop
1255 
1256 	sync				; RDR 24 read sequence
1257 	ssm		0,0
1258 	SFDIAG		(24)
1259 	ssm		0,0
1260 	MFDIAG_1	(28)
1261 	b,n         perf_rdr_shift_in_U_leave
1262 	ssm		0,0
1263 	nop
1264 
1265 	sync				; RDR 25 read sequence
1266 	ssm		0,0
1267 	SFDIAG		(25)
1268 	ssm		0,0
1269 	MFDIAG_1	(28)
1270 	b,n         perf_rdr_shift_in_U_leave
1271 	ssm		0,0
1272 	nop
1273 
1274 	SFDIAG		(26)		; RDR 26 read sequence
1275 	ssm		0,0
1276 	MFDIAG_1	(28)
1277 	shrpd		ret0,%r0,%sar,%r1
1278 	MTDIAG_1	(1)
1279 	STDIAG		(26)
1280 	ssm		0,0
1281 	b,n         perf_rdr_shift_in_U_leave
1282 
1283 	SFDIAG		(27)		; RDR 27 read sequence
1284 	ssm		0,0
1285 	MFDIAG_1	(28)
1286 	shrpd		ret0,%r0,%sar,%r1
1287 	MTDIAG_1	(1)
1288 	STDIAG		(27)
1289 	ssm		0,0
1290 	b,n         perf_rdr_shift_in_U_leave
1291 
1292 	sync				; RDR 28 read sequence
1293 	ssm		0,0
1294 	SFDIAG		(28)
1295 	ssm		0,0
1296 	MFDIAG_1	(28)
1297 	b,n         perf_rdr_shift_in_U_leave
1298 	ssm		0,0
1299 	nop
1300 
1301 	b,n         perf_rdr_shift_in_U_leave
1302 	nop
1303 	nop
1304 	nop
1305 	nop
1306 	nop
1307 	nop
1308 	nop
1309 
1310 	SFDIAG		(30)		; RDR 30 read sequence
1311 	ssm		0,0
1312 	MFDIAG_1	(28)
1313 	shrpd		ret0,%r0,%sar,%r1
1314 	MTDIAG_1	(1)
1315 	STDIAG		(30)
1316 	ssm		0,0
1317 	b,n         perf_rdr_shift_in_U_leave
1318 
1319 	SFDIAG		(31)		; RDR 31 read sequence
1320 	ssm		0,0
1321 	MFDIAG_1	(28)
1322 	shrpd		ret0,%r0,%sar,%r1
1323 	MTDIAG_1	(1)
1324 	STDIAG		(31)
1325 	ssm		0,0
1326 	b,n         perf_rdr_shift_in_U_leave
1327 	nop
1328 
1329 perf_rdr_shift_in_U_leave:
1330 	bve		    (%r2)
1331 	.exit
1332 	MTDIAG_2	(24)			; restore DR2
1333 	.procend
1334 ENDPROC(perf_rdr_shift_in_U)
1335 
1336 ;***********************************************************************
1337 ;*
1338 ;* Name: rdr_shift_out_U
1339 ;*
1340 ;* Description:
1341 ;*	This routine moves data to the RDR's.  The double-word that
1342 ;*	arg1 points to is loaded and moved into the staging register.
1343 ;*	Then the STDIAG instruction for the RDR # in arg0 is called
1344 ;*	to move the data to the RDR.
1345 ;*
1346 ;* Arguments:
1347 ;*	arg0 = rdr target
1348 ;*	arg1 = buffer pointer
1349 ;*
1350 ;* Returns:
1351 ;*	None
1352 ;*
1353 ;* Register usage:
1354 ;*	arg0 = rdr target
1355 ;*	arg1 = buffer pointer
1356 ;*	%r24 - DR2 | DR2_SLOW_RET
1357 ;*	%r23 - original DR2 value
1358 ;*
1359 ;***********************************************************************
1360 
1361 ENTRY(perf_rdr_shift_out_U)
1362 	.proc
1363 	.callinfo frame=0,NO_CALLS
1364 	.entry
1365 
1366 ;
1367 ; NOTE: The PCX-U ERS states that DR2_SLOW_RET must be set before any
1368 ; shifting is done, from or to, the remote diagnose registers.
1369 ;
1370 
1371 	depdi,z		1,DR2_SLOW_RET,1,%r24
1372 	MFDIAG_2	(23)
1373 	or		%r24,%r23,%r24
1374 	MTDIAG_2	(24)		; set DR2_SLOW_RET
1375 
1376 	MTDIAG_1	(25)		; data to the staging register
1377 	shladd		arg0,2,%r0,%r1	; %r1 = 4 * RDR number
1378 	blr		%r1,%r0		; branch to 8-instruction sequence
1379 	nop
1380 
1381 ;
1382 ; 32-byte cachline aligned
1383 ;
1384 
1385 	sync				; RDR 0 write sequence
1386 	ssm		0,0
1387 	STDIAG		(0)
1388 	ssm		0,0
1389 	b,n         perf_rdr_shift_out_U_leave
1390 	nop
1391 	ssm		0,0
1392 	nop
1393 
1394 	sync				; RDR 1 write sequence
1395 	ssm		0,0
1396 	STDIAG		(1)
1397 	ssm		0,0
1398 	b,n         perf_rdr_shift_out_U_leave
1399 	nop
1400 	ssm		0,0
1401 	nop
1402 
1403 	sync				; RDR 2 write sequence
1404 	ssm		0,0
1405 	STDIAG		(2)
1406 	ssm		0,0
1407 	b,n         perf_rdr_shift_out_U_leave
1408 	nop
1409 	ssm		0,0
1410 	nop
1411 
1412 	sync				; RDR 3 write sequence
1413 	ssm		0,0
1414 	STDIAG		(3)
1415 	ssm		0,0
1416 	b,n         perf_rdr_shift_out_U_leave
1417 	nop
1418 	ssm		0,0
1419 	nop
1420 
1421 	sync				; RDR 4 write sequence
1422 	ssm		0,0
1423 	STDIAG		(4)
1424 	ssm		0,0
1425 	b,n         perf_rdr_shift_out_U_leave
1426 	nop
1427 	ssm		0,0
1428 	nop
1429 
1430 	sync				; RDR 5 write sequence
1431 	ssm		0,0
1432 	STDIAG		(5)
1433 	ssm		0,0
1434 	b,n         perf_rdr_shift_out_U_leave
1435 	nop
1436 	ssm		0,0
1437 	nop
1438 
1439 	sync				; RDR 6 write sequence
1440 	ssm		0,0
1441 	STDIAG		(6)
1442 	ssm		0,0
1443 	b,n         perf_rdr_shift_out_U_leave
1444 	nop
1445 	ssm		0,0
1446 	nop
1447 
1448 	sync				; RDR 7 write sequence
1449 	ssm		0,0
1450 	STDIAG		(7)
1451 	ssm		0,0
1452 	b,n         perf_rdr_shift_out_U_leave
1453 	nop
1454 	ssm		0,0
1455 	nop
1456 
1457 	sync				; RDR 8 write sequence
1458 	ssm		0,0
1459 	STDIAG		(8)
1460 	ssm		0,0
1461 	b,n         perf_rdr_shift_out_U_leave
1462 	nop
1463 	ssm		0,0
1464 	nop
1465 
1466 	sync				; RDR 9 write sequence
1467 	ssm		0,0
1468 	STDIAG		(9)
1469 	ssm		0,0
1470 	b,n         perf_rdr_shift_out_U_leave
1471 	nop
1472 	ssm		0,0
1473 	nop
1474 
1475 	sync				; RDR 10 write sequence
1476 	ssm		0,0
1477 	STDIAG		(10)
1478 	ssm		0,0
1479 	b,n         perf_rdr_shift_out_U_leave
1480 	nop
1481 	ssm		0,0
1482 	nop
1483 
1484 	sync				; RDR 11 write sequence
1485 	ssm		0,0
1486 	STDIAG		(11)
1487 	ssm		0,0
1488 	b,n         perf_rdr_shift_out_U_leave
1489 	nop
1490 	ssm		0,0
1491 	nop
1492 
1493 	sync				; RDR 12 write sequence
1494 	ssm		0,0
1495 	STDIAG		(12)
1496 	ssm		0,0
1497 	b,n         perf_rdr_shift_out_U_leave
1498 	nop
1499 	ssm		0,0
1500 	nop
1501 
1502 	sync				; RDR 13 write sequence
1503 	ssm		0,0
1504 	STDIAG		(13)
1505 	ssm		0,0
1506 	b,n         perf_rdr_shift_out_U_leave
1507 	nop
1508 	ssm		0,0
1509 	nop
1510 
1511 	sync				; RDR 14 write sequence
1512 	ssm		0,0
1513 	STDIAG		(14)
1514 	ssm		0,0
1515 	b,n         perf_rdr_shift_out_U_leave
1516 	nop
1517 	ssm		0,0
1518 	nop
1519 
1520 	sync				; RDR 15 write sequence
1521 	ssm		0,0
1522 	STDIAG		(15)
1523 	ssm		0,0
1524 	b,n         perf_rdr_shift_out_U_leave
1525 	nop
1526 	ssm		0,0
1527 	nop
1528 
1529 	sync				; RDR 16 write sequence
1530 	ssm		0,0
1531 	STDIAG		(16)
1532 	ssm		0,0
1533 	b,n         perf_rdr_shift_out_U_leave
1534 	nop
1535 	ssm		0,0
1536 	nop
1537 
1538 	sync				; RDR 17 write sequence
1539 	ssm		0,0
1540 	STDIAG		(17)
1541 	ssm		0,0
1542 	b,n         perf_rdr_shift_out_U_leave
1543 	nop
1544 	ssm		0,0
1545 	nop
1546 
1547 	sync				; RDR 18 write sequence
1548 	ssm		0,0
1549 	STDIAG		(18)
1550 	ssm		0,0
1551 	b,n         perf_rdr_shift_out_U_leave
1552 	nop
1553 	ssm		0,0
1554 	nop
1555 
1556 	sync				; RDR 19 write sequence
1557 	ssm		0,0
1558 	STDIAG		(19)
1559 	ssm		0,0
1560 	b,n         perf_rdr_shift_out_U_leave
1561 	nop
1562 	ssm		0,0
1563 	nop
1564 
1565 	sync				; RDR 20 write sequence
1566 	ssm		0,0
1567 	STDIAG		(20)
1568 	ssm		0,0
1569 	b,n         perf_rdr_shift_out_U_leave
1570 	nop
1571 	ssm		0,0
1572 	nop
1573 
1574 	sync				; RDR 21 write sequence
1575 	ssm		0,0
1576 	STDIAG		(21)
1577 	ssm		0,0
1578 	b,n         perf_rdr_shift_out_U_leave
1579 	nop
1580 	ssm		0,0
1581 	nop
1582 
1583 	sync				; RDR 22 write sequence
1584 	ssm		0,0
1585 	STDIAG		(22)
1586 	ssm		0,0
1587 	b,n         perf_rdr_shift_out_U_leave
1588 	nop
1589 	ssm		0,0
1590 	nop
1591 
1592 	sync				; RDR 23 write sequence
1593 	ssm		0,0
1594 	STDIAG		(23)
1595 	ssm		0,0
1596 	b,n         perf_rdr_shift_out_U_leave
1597 	nop
1598 	ssm		0,0
1599 	nop
1600 
1601 	sync				; RDR 24 write sequence
1602 	ssm		0,0
1603 	STDIAG		(24)
1604 	ssm		0,0
1605 	b,n         perf_rdr_shift_out_U_leave
1606 	nop
1607 	ssm		0,0
1608 	nop
1609 
1610 	sync				; RDR 25 write sequence
1611 	ssm		0,0
1612 	STDIAG		(25)
1613 	ssm		0,0
1614 	b,n         perf_rdr_shift_out_U_leave
1615 	nop
1616 	ssm		0,0
1617 	nop
1618 
1619 	sync				; RDR 26 write sequence
1620 	ssm		0,0
1621 	STDIAG		(26)
1622 	ssm		0,0
1623 	b,n         perf_rdr_shift_out_U_leave
1624 	nop
1625 	ssm		0,0
1626 	nop
1627 
1628 	sync				; RDR 27 write sequence
1629 	ssm		0,0
1630 	STDIAG		(27)
1631 	ssm		0,0
1632 	b,n         perf_rdr_shift_out_U_leave
1633 	nop
1634 	ssm		0,0
1635 	nop
1636 
1637 	sync				; RDR 28 write sequence
1638 	ssm		0,0
1639 	STDIAG		(28)
1640 	ssm		0,0
1641 	b,n         perf_rdr_shift_out_U_leave
1642 	nop
1643 	ssm		0,0
1644 	nop
1645 
1646 	sync				; RDR 29 write sequence
1647 	ssm		0,0
1648 	STDIAG		(29)
1649 	ssm		0,0
1650 	b,n         perf_rdr_shift_out_U_leave
1651 	nop
1652 	ssm		0,0
1653 	nop
1654 
1655 	sync				; RDR 30 write sequence
1656 	ssm		0,0
1657 	STDIAG		(30)
1658 	ssm		0,0
1659 	b,n         perf_rdr_shift_out_U_leave
1660 	nop
1661 	ssm		0,0
1662 	nop
1663 
1664 	sync				; RDR 31 write sequence
1665 	ssm		0,0
1666 	STDIAG		(31)
1667 	ssm		0,0
1668 	b,n         perf_rdr_shift_out_U_leave
1669 	nop
1670 	ssm		0,0
1671 	nop
1672 
1673 perf_rdr_shift_out_U_leave:
1674 	bve		(%r2)
1675 	.exit
1676 	MTDIAG_2	(23)			; restore DR2
1677 	.procend
1678 ENDPROC(perf_rdr_shift_out_U)
1679 
1680