1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2018-2019  Realtek Corporation
3  */
4 
5 #ifndef __RTW_FW_H_
6 #define __RTW_FW_H_
7 
8 #define H2C_PKT_SIZE		32
9 #define H2C_PKT_HDR_SIZE	8
10 
11 /* FW bin information */
12 #define FW_HDR_SIZE			64
13 #define FW_HDR_CHKSUM_SIZE		8
14 
15 #define FW_NLO_INFO_CHECK_SIZE		4
16 
17 #define FIFO_PAGE_SIZE_SHIFT		12
18 #define FIFO_PAGE_SIZE			4096
19 #define FIFO_DUMP_ADDR			0x8000
20 
21 #define DLFW_PAGE_SIZE_SHIFT_LEGACY	12
22 #define DLFW_PAGE_SIZE_LEGACY		0x1000
23 #define DLFW_BLK_SIZE_SHIFT_LEGACY	2
24 #define DLFW_BLK_SIZE_LEGACY		4
25 #define FW_START_ADDR_LEGACY		0x1000
26 
27 #define BCN_LOSS_CNT			10
28 #define BCN_FILTER_NOTIFY_SIGNAL_CHANGE	0
29 #define BCN_FILTER_CONNECTION_LOSS	1
30 #define BCN_FILTER_CONNECTED		2
31 #define BCN_FILTER_NOTIFY_BEACON_LOSS	3
32 
33 #define SCAN_NOTIFY_TIMEOUT  msecs_to_jiffies(10)
34 
35 #define RTW_CHANNEL_TIME		45
36 #define RTW_OFF_CHAN_TIME		100
37 #define RTW_PASS_CHAN_TIME		105
38 #define RTW_DFS_CHAN_TIME		20
39 #define RTW_CH_INFO_SIZE		4
40 #define RTW_EX_CH_INFO_SIZE		3
41 #define RTW_EX_CH_INFO_HDR_SIZE		2
42 #define RTW_SCAN_WIDTH			0
43 #define RTW_PRI_CH_IDX			1
44 #define RTW_OLD_PROBE_PG_CNT		2
45 #define RTW_PROBE_PG_CNT		4
46 
47 enum rtw_c2h_cmd_id {
48 	C2H_CCX_TX_RPT = 0x03,
49 	C2H_BT_INFO = 0x09,
50 	C2H_BT_MP_INFO = 0x0b,
51 	C2H_BT_HID_INFO = 0x45,
52 	C2H_RA_RPT = 0x0c,
53 	C2H_HW_FEATURE_REPORT = 0x19,
54 	C2H_WLAN_INFO = 0x27,
55 	C2H_WLAN_RFON = 0x32,
56 	C2H_BCN_FILTER_NOTIFY = 0x36,
57 	C2H_ADAPTIVITY = 0x37,
58 	C2H_SCAN_RESULT = 0x38,
59 	C2H_HW_FEATURE_DUMP = 0xfd,
60 	C2H_HALMAC = 0xff,
61 };
62 
63 enum rtw_c2h_cmd_id_ext {
64 	C2H_SCAN_STATUS_RPT = 0x3,
65 	C2H_CCX_RPT = 0x0f,
66 	C2H_CHAN_SWITCH = 0x22,
67 };
68 
69 struct rtw_c2h_cmd {
70 	u8 id;
71 	u8 seq;
72 	u8 payload[];
73 } __packed;
74 
75 struct rtw_c2h_adaptivity {
76 	u8 density;
77 	u8 igi;
78 	u8 l2h_th_init;
79 	u8 l2h;
80 	u8 h2l;
81 	u8 option;
82 } __packed;
83 
84 struct rtw_h2c_register {
85 	u32 w0;
86 	u32 w1;
87 } __packed;
88 
89 #define RTW_H2C_W0_CMDID		GENMASK(7, 0)
90 
91 /* H2C_CMD_DEFAULT_PORT command */
92 #define RTW_H2C_DEFAULT_PORT_W0_PORTID	GENMASK(15, 8)
93 #define RTW_H2C_DEFAULT_PORT_W0_MACID	GENMASK(23, 16)
94 
95 struct rtw_h2c_cmd {
96 	__le32 msg;
97 	__le32 msg_ext;
98 } __packed;
99 
100 enum rtw_rsvd_packet_type {
101 	RSVD_BEACON,
102 	RSVD_DUMMY,
103 	RSVD_PS_POLL,
104 	RSVD_PROBE_RESP,
105 	RSVD_NULL,
106 	RSVD_QOS_NULL,
107 	RSVD_LPS_PG_DPK,
108 	RSVD_LPS_PG_INFO,
109 	RSVD_PROBE_REQ,
110 	RSVD_NLO_INFO,
111 	RSVD_CH_INFO,
112 };
113 
114 enum rtw_fw_rf_type {
115 	FW_RF_1T2R = 0,
116 	FW_RF_2T4R = 1,
117 	FW_RF_2T2R = 2,
118 	FW_RF_2T3R = 3,
119 	FW_RF_1T1R = 4,
120 	FW_RF_2T2R_GREEN = 5,
121 	FW_RF_3T3R = 6,
122 	FW_RF_3T4R = 7,
123 	FW_RF_4T4R = 8,
124 	FW_RF_MAX_TYPE = 0xF,
125 };
126 
127 enum rtw_fw_feature {
128 	FW_FEATURE_SIG = BIT(0),
129 	FW_FEATURE_LPS_C2H = BIT(1),
130 	FW_FEATURE_LCLK = BIT(2),
131 	FW_FEATURE_PG = BIT(3),
132 	FW_FEATURE_TX_WAKE = BIT(4),
133 	FW_FEATURE_BCN_FILTER = BIT(5),
134 	FW_FEATURE_NOTIFY_SCAN = BIT(6),
135 	FW_FEATURE_ADAPTIVITY = BIT(7),
136 	FW_FEATURE_SCAN_OFFLOAD = BIT(8),
137 	FW_FEATURE_MAX = BIT(31),
138 };
139 
140 enum rtw_fw_feature_ext {
141 	FW_FEATURE_EXT_OLD_PAGE_NUM = BIT(0),
142 };
143 
144 enum rtw_beacon_filter_offload_mode {
145 	BCN_FILTER_OFFLOAD_MODE_0 = 0,
146 	BCN_FILTER_OFFLOAD_MODE_1,
147 	BCN_FILTER_OFFLOAD_MODE_2,
148 	BCN_FILTER_OFFLOAD_MODE_3,
149 
150 	BCN_FILTER_OFFLOAD_MODE_DEFAULT = BCN_FILTER_OFFLOAD_MODE_0,
151 };
152 
153 struct rtw_coex_info_req {
154 	u8 seq;
155 	u8 op_code;
156 	u8 para1;
157 	u8 para2;
158 	u8 para3;
159 };
160 
161 struct rtw_iqk_para {
162 	u8 clear;
163 	u8 segment_iqk;
164 };
165 
166 struct rtw_lps_pg_dpk_hdr {
167 	u16 dpk_path_ok;
168 	u8 dpk_txagc[2];
169 	u16 dpk_gs[2];
170 	u32 coef[2][20];
171 	u8 dpk_ch;
172 } __packed;
173 
174 struct rtw_lps_pg_info_hdr {
175 	u8 macid;
176 	u8 mbssid;
177 	u8 pattern_count;
178 	u8 mu_tab_group_id;
179 	u8 sec_cam_count;
180 	u8 tx_bu_page_count;
181 	u16 rsvd;
182 	u8 sec_cam[MAX_PG_CAM_BACKUP_NUM];
183 } __packed;
184 
185 struct rtw_rsvd_page {
186 	/* associated with each vif */
187 	struct list_head vif_list;
188 	struct rtw_vif *rtwvif;
189 
190 	/* associated when build rsvd page */
191 	struct list_head build_list;
192 
193 	struct sk_buff *skb;
194 	enum rtw_rsvd_packet_type type;
195 	u8 page;
196 	u16 tim_offset;
197 	bool add_txdesc;
198 	struct cfg80211_ssid *ssid;
199 	u16 probe_req_size;
200 };
201 
202 enum rtw_keep_alive_pkt_type {
203 	KEEP_ALIVE_NULL_PKT = 0,
204 	KEEP_ALIVE_ARP_RSP = 1,
205 };
206 
207 struct rtw_nlo_info_hdr {
208 	u8 nlo_count;
209 	u8 hidden_ap_count;
210 	u8 rsvd1[2];
211 	u8 pattern_check[FW_NLO_INFO_CHECK_SIZE];
212 	u8 rsvd2[8];
213 	u8 ssid_len[16];
214 	u8 chiper[16];
215 	u8 rsvd3[16];
216 	u8 location[8];
217 } __packed;
218 
219 enum rtw_packet_type {
220 	RTW_PACKET_PROBE_REQ = 0x00,
221 
222 	RTW_PACKET_UNDEFINE = 0x7FFFFFFF,
223 };
224 
225 struct rtw_fw_wow_keep_alive_para {
226 	bool adopt;
227 	u8 pkt_type;
228 	u8 period;		/* unit: sec */
229 };
230 
231 struct rtw_fw_wow_disconnect_para {
232 	bool adopt;
233 	u8 period;		/* unit: sec */
234 	u8 retry_count;
235 };
236 
237 enum rtw_channel_type {
238 	RTW_CHANNEL_PASSIVE,
239 	RTW_CHANNEL_ACTIVE,
240 	RTW_CHANNEL_RADAR,
241 };
242 
243 enum rtw_scan_extra_id {
244 	RTW_SCAN_EXTRA_ID_DFS,
245 };
246 
247 enum rtw_scan_extra_info {
248 	RTW_SCAN_EXTRA_ACTION_SCAN,
249 };
250 
251 enum rtw_scan_report_code {
252 	RTW_SCAN_REPORT_SUCCESS = 0x00,
253 	RTW_SCAN_REPORT_ERR_PHYDM = 0x01,
254 	RTW_SCAN_REPORT_ERR_ID = 0x02,
255 	RTW_SCAN_REPORT_ERR_TX = 0x03,
256 	RTW_SCAN_REPORT_CANCELED = 0x10,
257 	RTW_SCAN_REPORT_CANCELED_EXT = 0x11,
258 	RTW_SCAN_REPORT_FW_DISABLED = 0xF0,
259 };
260 
261 enum rtw_scan_notify_id {
262 	RTW_SCAN_NOTIFY_ID_PRESWITCH = 0x00,
263 	RTW_SCAN_NOTIFY_ID_POSTSWITCH = 0x01,
264 	RTW_SCAN_NOTIFY_ID_PROBE_PRETX = 0x02,
265 	RTW_SCAN_NOTIFY_ID_PROBE_ISSUETX = 0x03,
266 	RTW_SCAN_NOTIFY_ID_NULL0_PRETX = 0x04,
267 	RTW_SCAN_NOTIFY_ID_NULL0_ISSUETX = 0x05,
268 	RTW_SCAN_NOTIFY_ID_NULL0_POSTTX = 0x06,
269 	RTW_SCAN_NOTIFY_ID_NULL1_PRETX = 0x07,
270 	RTW_SCAN_NOTIFY_ID_NULL1_ISSUETX = 0x08,
271 	RTW_SCAN_NOTIFY_ID_NULL1_POSTTX = 0x09,
272 	RTW_SCAN_NOTIFY_ID_DWELLEXT = 0x0A,
273 };
274 
275 enum rtw_scan_notify_status {
276 	RTW_SCAN_NOTIFY_STATUS_SUCCESS = 0x00,
277 	RTW_SCAN_NOTIFY_STATUS_FAILURE = 0x01,
278 	RTW_SCAN_NOTIFY_STATUS_RESOURCE = 0x02,
279 	RTW_SCAN_NOTIFY_STATUS_TIMEOUT = 0x03,
280 };
281 
282 struct rtw_ch_switch_option {
283 	u8 periodic_option;
284 	u32 tsf_high;
285 	u32 tsf_low;
286 	u8 dest_ch_en;
287 	u8 absolute_time_en;
288 	u8 dest_ch;
289 	u8 normal_period;
290 	u8 normal_period_sel;
291 	u8 normal_cycle;
292 	u8 slow_period;
293 	u8 slow_period_sel;
294 	u8 nlo_en;
295 	bool switch_en;
296 	bool back_op_en;
297 };
298 
299 struct rtw_fw_hdr {
300 	__le16 signature;
301 	u8 category;
302 	u8 function;
303 	__le16 version;		/* 0x04 */
304 	u8 subversion;
305 	u8 subindex;
306 	__le32 rsvd;		/* 0x08 */
307 	__le32 feature;		/* 0x0C */
308 	u8 month;		/* 0x10 */
309 	u8 day;
310 	u8 hour;
311 	u8 min;
312 	__le16 year;		/* 0x14 */
313 	__le16 rsvd3;
314 	u8 mem_usage;		/* 0x18 */
315 	u8 rsvd4[3];
316 	__le16 h2c_fmt_ver;	/* 0x1C */
317 	__le16 rsvd5;
318 	__le32 dmem_addr;	/* 0x20 */
319 	__le32 dmem_size;
320 	__le32 rsvd6;
321 	__le32 rsvd7;
322 	__le32 imem_size;	/* 0x30 */
323 	__le32 emem_size;
324 	__le32 emem_addr;
325 	__le32 imem_addr;
326 } __packed;
327 
328 struct rtw_fw_hdr_legacy {
329 	__le16 signature;
330 	u8 category;
331 	u8 function;
332 	__le16 version;	/* 0x04 */
333 	u8 subversion1;
334 	u8 subversion2;
335 	u8 month;	/* 0x08 */
336 	u8 day;
337 	u8 hour;
338 	u8 minute;
339 	__le16 size;
340 	__le16 rsvd2;
341 	__le32 idx;	/* 0x10 */
342 	__le32 rsvd3;
343 	__le32 rsvd4;	/* 0x18 */
344 	__le32 rsvd5;
345 } __packed;
346 
347 #define RTW_FW_VER_CODE(ver, sub_ver, idx)	\
348 	(((ver) << 16) | ((sub_ver) << 8) | (idx))
349 #define RTW_FW_SUIT_VER_CODE(s)	\
350 	RTW_FW_VER_CODE((s).version, (s).sub_version, (s).sub_index)
351 
352 /* C2H */
353 #define GET_CCX_REPORT_SEQNUM_V0(c2h_payload)	(c2h_payload[6] & 0xfc)
354 #define GET_CCX_REPORT_STATUS_V0(c2h_payload)	(c2h_payload[0] & 0xc0)
355 #define GET_CCX_REPORT_SEQNUM_V1(c2h_payload)	(c2h_payload[8] & 0xfc)
356 #define GET_CCX_REPORT_STATUS_V1(c2h_payload)	(c2h_payload[9] & 0xc0)
357 
358 #define GET_SCAN_REPORT_RETURN_CODE(c2h_payload)	(c2h_payload[2] & 0xff)
359 
360 #define GET_CHAN_SWITCH_CENTRAL_CH(c2h_payload)	(c2h_payload[2])
361 #define GET_CHAN_SWITCH_ID(c2h_payload)		(c2h_payload[3])
362 #define GET_CHAN_SWITCH_STATUS(c2h_payload)	(c2h_payload[4])
363 #define GET_RA_REPORT_RATE(c2h_payload)		(c2h_payload[0] & 0x7f)
364 #define GET_RA_REPORT_SGI(c2h_payload)		((c2h_payload[0] & 0x80) >> 7)
365 #define GET_RA_REPORT_BW(c2h_payload)		(c2h_payload[6])
366 #define GET_RA_REPORT_MACID(c2h_payload)	(c2h_payload[1])
367 
368 #define GET_BCN_FILTER_NOTIFY_TYPE(c2h_payload)	(c2h_payload[1] & 0xf)
369 #define GET_BCN_FILTER_NOTIFY_EVENT(c2h_payload)	(c2h_payload[1] & 0x10)
370 #define GET_BCN_FILTER_NOTIFY_RSSI(c2h_payload)	(c2h_payload[2] - 100)
371 
372 /* PKT H2C */
373 #define H2C_PKT_CMD_ID 0xFF
374 #define H2C_PKT_CATEGORY 0x01
375 
376 #define H2C_PKT_GENERAL_INFO 0x0D
377 #define H2C_PKT_PHYDM_INFO 0x11
378 #define H2C_PKT_IQK 0x0E
379 
380 #define H2C_PKT_CH_SWITCH 0x02
381 #define H2C_PKT_UPDATE_PKT 0x0C
382 #define H2C_PKT_SCAN_OFFLOAD 0x19
383 
384 #define H2C_PKT_CH_SWITCH_LEN 0x20
385 #define H2C_PKT_UPDATE_PKT_LEN 0x4
386 
387 #define SET_PKT_H2C_CATEGORY(h2c_pkt, value)                                   \
388 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(6, 0))
389 #define SET_PKT_H2C_CMD_ID(h2c_pkt, value)                                     \
390 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
391 #define SET_PKT_H2C_SUB_CMD_ID(h2c_pkt, value)                                 \
392 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 16))
393 #define SET_PKT_H2C_TOTAL_LEN(h2c_pkt, value)                                  \
394 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 0))
395 
rtw_h2c_pkt_set_header(u8 * h2c_pkt,u8 sub_id)396 static inline void rtw_h2c_pkt_set_header(u8 *h2c_pkt, u8 sub_id)
397 {
398 	SET_PKT_H2C_CATEGORY(h2c_pkt, H2C_PKT_CATEGORY);
399 	SET_PKT_H2C_CMD_ID(h2c_pkt, H2C_PKT_CMD_ID);
400 	SET_PKT_H2C_SUB_CMD_ID(h2c_pkt, sub_id);
401 }
402 
403 #define FW_OFFLOAD_H2C_SET_SEQ_NUM(h2c_pkt, value)                             \
404 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(31, 16))
405 #define GENERAL_INFO_SET_FW_TX_BOUNDARY(h2c_pkt, value)                        \
406 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16))
407 
408 #define PHYDM_INFO_SET_REF_TYPE(h2c_pkt, value)                                \
409 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(7, 0))
410 #define PHYDM_INFO_SET_RF_TYPE(h2c_pkt, value)                                 \
411 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(15, 8))
412 #define PHYDM_INFO_SET_CUT_VER(h2c_pkt, value)                                 \
413 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16))
414 #define PHYDM_INFO_SET_RX_ANT_STATUS(h2c_pkt, value)                           \
415 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(27, 24))
416 #define PHYDM_INFO_SET_TX_ANT_STATUS(h2c_pkt, value)                           \
417 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(31, 28))
418 #define IQK_SET_CLEAR(h2c_pkt, value)                                          \
419 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(0))
420 #define IQK_SET_SEGMENT_IQK(h2c_pkt, value)                                    \
421 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(1))
422 
423 #define CHSW_INFO_SET_CH(pkt, value)					       \
424 	le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(7, 0))
425 #define CHSW_INFO_SET_PRI_CH_IDX(pkt, value)				       \
426 	le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(11, 8))
427 #define CHSW_INFO_SET_BW(pkt, value)					       \
428 	le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(15, 12))
429 #define CHSW_INFO_SET_TIMEOUT(pkt, value)				       \
430 	le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(23, 16))
431 #define CHSW_INFO_SET_ACTION_ID(pkt, value)				       \
432 	le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(30, 24))
433 #define CHSW_INFO_SET_EXTRA_INFO(pkt, value)				       \
434 	le32p_replace_bits((__le32 *)(pkt) + 0x00, value, BIT(31))
435 
436 #define CH_INFO_SET_CH(pkt, value)					       \
437 	u8p_replace_bits((u8 *)(pkt) + 0x00, value, GENMASK(7, 0))
438 #define CH_INFO_SET_PRI_CH_IDX(pkt, value)				       \
439 	u8p_replace_bits((u8 *)(pkt) + 0x01, value, GENMASK(3, 0))
440 #define CH_INFO_SET_BW(pkt, value)					       \
441 	u8p_replace_bits((u8 *)(pkt) + 0x01, value, GENMASK(7, 4))
442 #define CH_INFO_SET_TIMEOUT(pkt, value)					       \
443 	u8p_replace_bits((u8 *)(pkt) + 0x02, value, GENMASK(7, 0))
444 #define CH_INFO_SET_ACTION_ID(pkt, value)				       \
445 	u8p_replace_bits((u8 *)(pkt) + 0x03, value, GENMASK(6, 0))
446 #define CH_INFO_SET_EXTRA_INFO(pkt, value)				       \
447 	u8p_replace_bits((u8 *)(pkt) + 0x03, value, BIT(7))
448 
449 #define EXTRA_CH_INFO_SET_ID(pkt, value)				       \
450 	u8p_replace_bits((u8 *)(pkt) + 0x04, value, GENMASK(6, 0))
451 #define EXTRA_CH_INFO_SET_INFO(pkt, value)				       \
452 	u8p_replace_bits((u8 *)(pkt) + 0x04, value, BIT(7))
453 #define EXTRA_CH_INFO_SET_SIZE(pkt, value)				       \
454 	u8p_replace_bits((u8 *)(pkt) + 0x05, value, GENMASK(7, 0))
455 #define EXTRA_CH_INFO_SET_DFS_EXT_TIME(pkt, value)			       \
456 	u8p_replace_bits((u8 *)(pkt) + 0x06, value, GENMASK(7, 0))
457 
458 #define UPDATE_PKT_SET_SIZE(h2c_pkt, value)				       \
459 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(15, 0))
460 #define UPDATE_PKT_SET_PKT_ID(h2c_pkt, value)				       \
461 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16))
462 #define UPDATE_PKT_SET_LOCATION(h2c_pkt, value)				       \
463 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(31, 24))
464 
465 #define CH_SWITCH_SET_START(h2c_pkt, value)				       \
466 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(0))
467 #define CH_SWITCH_SET_DEST_CH_EN(h2c_pkt, value)			       \
468 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(1))
469 #define CH_SWITCH_SET_ABSOLUTE_TIME(h2c_pkt, value)			       \
470 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(2))
471 #define CH_SWITCH_SET_PERIODIC_OPT(h2c_pkt, value)			       \
472 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(4, 3))
473 #define CH_SWITCH_SET_SCAN_MODE(h2c_pkt, value)				       \
474 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(5))
475 #define CH_SWITCH_SET_BACK_OP_EN(h2c_pkt, value)			       \
476 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(6))
477 #define CH_SWITCH_SET_INFO_LOC(h2c_pkt, value)				       \
478 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(15, 8))
479 #define CH_SWITCH_SET_CH_NUM(h2c_pkt, value)				       \
480 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16))
481 #define CH_SWITCH_SET_PRI_CH_IDX(h2c_pkt, value)			       \
482 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(27, 24))
483 #define CH_SWITCH_SET_DEST_BW(h2c_pkt, value)				       \
484 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(31, 28))
485 #define CH_SWITCH_SET_DEST_CH(h2c_pkt, value)				       \
486 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(7, 0))
487 #define CH_SWITCH_SET_NORMAL_PERIOD(h2c_pkt, value)			       \
488 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(13, 8))
489 #define CH_SWITCH_SET_NORMAL_PERIOD_SEL(h2c_pkt, value)			       \
490 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(15, 14))
491 #define CH_SWITCH_SET_SLOW_PERIOD(h2c_pkt, value)			       \
492 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(21, 16))
493 #define CH_SWITCH_SET_SLOW_PERIOD_SEL(h2c_pkt, value)			       \
494 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(23, 22))
495 #define CH_SWITCH_SET_NORMAL_CYCLE(h2c_pkt, value)			       \
496 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(31, 24))
497 #define CH_SWITCH_SET_TSF_HIGH(h2c_pkt, value)				       \
498 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x04, value, GENMASK(31, 0))
499 #define CH_SWITCH_SET_TSF_LOW(h2c_pkt, value)				       \
500 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x05, value, GENMASK(31, 0))
501 #define CH_SWITCH_SET_INFO_SIZE(h2c_pkt, value)				       \
502 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x06, value, GENMASK(15, 0))
503 
504 #define SCAN_OFFLOAD_SET_START(h2c_pkt, value)				       \
505 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(0))
506 #define SCAN_OFFLOAD_SET_BACK_OP_EN(h2c_pkt, value)			       \
507 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(1))
508 #define SCAN_OFFLOAD_SET_RANDOM_SEQ_EN(h2c_pkt, value)			       \
509 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(2))
510 #define SCAN_OFFLOAD_SET_NO_CCK_EN(h2c_pkt, value)			       \
511 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(3))
512 #define SCAN_OFFLOAD_SET_VERBOSE(h2c_pkt, value)			       \
513 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(4))
514 #define SCAN_OFFLOAD_SET_CH_NUM(h2c_pkt, value)				       \
515 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(15, 8))
516 #define SCAN_OFFLOAD_SET_CH_INFO_SIZE(h2c_pkt, value)			       \
517 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(31, 16))
518 #define SCAN_OFFLOAD_SET_CH_INFO_LOC(h2c_pkt, value)			       \
519 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(7, 0))
520 #define SCAN_OFFLOAD_SET_OP_CH(h2c_pkt, value)				       \
521 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(15, 8))
522 #define SCAN_OFFLOAD_SET_OP_PRI_CH_IDX(h2c_pkt, value)			       \
523 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(19, 16))
524 #define SCAN_OFFLOAD_SET_OP_BW(h2c_pkt, value)				       \
525 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(23, 20))
526 #define SCAN_OFFLOAD_SET_OP_PORT_ID(h2c_pkt, value)			       \
527 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(26, 24))
528 #define SCAN_OFFLOAD_SET_OP_DWELL_TIME(h2c_pkt, value)			       \
529 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x04, value, GENMASK(15, 0))
530 #define SCAN_OFFLOAD_SET_OP_GAP_TIME(h2c_pkt, value)			       \
531 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x04, value, GENMASK(31, 16))
532 #define SCAN_OFFLOAD_SET_MODE(h2c_pkt, value)				       \
533 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x05, value, GENMASK(3, 0))
534 #define SCAN_OFFLOAD_SET_SSID_NUM(h2c_pkt, value)			       \
535 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x05, value, GENMASK(7, 4))
536 #define SCAN_OFFLOAD_SET_PKT_LOC(h2c_pkt, value)			       \
537 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x05, value, GENMASK(15, 8))
538 
539 /* Command H2C */
540 #define H2C_CMD_RSVD_PAGE		0x0
541 #define H2C_CMD_MEDIA_STATUS_RPT	0x01
542 #define H2C_CMD_SET_PWR_MODE		0x20
543 #define H2C_CMD_LPS_PG_INFO		0x2b
544 #define H2C_CMD_DEFAULT_PORT		0x2c
545 #define H2C_CMD_RA_INFO			0x40
546 #define H2C_CMD_RSSI_MONITOR		0x42
547 #define H2C_CMD_BCN_FILTER_OFFLOAD_P0	0x56
548 #define H2C_CMD_BCN_FILTER_OFFLOAD_P1	0x57
549 #define H2C_CMD_WL_PHY_INFO		0x58
550 #define H2C_CMD_SCAN			0x59
551 #define H2C_CMD_ADAPTIVITY		0x5A
552 
553 #define H2C_CMD_COEX_TDMA_TYPE		0x60
554 #define H2C_CMD_QUERY_BT_INFO		0x61
555 #define H2C_CMD_FORCE_BT_TX_POWER	0x62
556 #define H2C_CMD_IGNORE_WLAN_ACTION	0x63
557 #define H2C_CMD_WL_CH_INFO		0x66
558 #define H2C_CMD_QUERY_BT_MP_INFO	0x67
559 #define H2C_CMD_BT_WIFI_CONTROL		0x69
560 #define H2C_CMD_WIFI_CALIBRATION	0x6d
561 #define H2C_CMD_QUERY_BT_HID_INFO	0x73
562 
563 #define H2C_CMD_KEEP_ALIVE		0x03
564 #define H2C_CMD_DISCONNECT_DECISION	0x04
565 #define H2C_CMD_WOWLAN			0x80
566 #define H2C_CMD_REMOTE_WAKE_CTRL	0x81
567 #define H2C_CMD_AOAC_GLOBAL_INFO	0x82
568 #define H2C_CMD_NLO_INFO		0x8C
569 
570 #define H2C_CMD_RECOVER_BT_DEV		0xD1
571 
572 #define SET_H2C_CMD_ID_CLASS(h2c_pkt, value)				       \
573 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(7, 0))
574 
575 #define MEDIA_STATUS_RPT_SET_OP_MODE(h2c_pkt, value)                           \
576 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
577 #define MEDIA_STATUS_RPT_SET_MACID(h2c_pkt, value)                             \
578 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
579 
580 #define SET_WL_PHY_INFO_TX_TP(h2c_pkt, value)				       \
581 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(17, 8))
582 #define SET_WL_PHY_INFO_RX_TP(h2c_pkt, value)				       \
583 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(27, 18))
584 #define SET_WL_PHY_INFO_TX_RATE_DESC(h2c_pkt, value)			       \
585 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0))
586 #define SET_WL_PHY_INFO_RX_RATE_DESC(h2c_pkt, value)			       \
587 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8))
588 #define SET_WL_PHY_INFO_RX_EVM(h2c_pkt, value)				       \
589 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(23, 16))
590 #define SET_BCN_FILTER_OFFLOAD_P1_MACID(h2c_pkt, value)			       \
591 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
592 #define SET_BCN_FILTER_OFFLOAD_P1_ENABLE(h2c_pkt, value)		       \
593 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(16))
594 #define SET_BCN_FILTER_OFFLOAD_P1_HYST(h2c_pkt, value)			       \
595 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(20, 17))
596 #define SET_BCN_FILTER_OFFLOAD_P1_OFFLOAD_MODE(h2c_pkt, value)		       \
597 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 21))
598 #define SET_BCN_FILTER_OFFLOAD_P1_THRESHOLD(h2c_pkt, value)		       \
599 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
600 #define SET_BCN_FILTER_OFFLOAD_P1_BCN_LOSS_CNT(h2c_pkt, value)		       \
601 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(3, 0))
602 #define SET_BCN_FILTER_OFFLOAD_P1_BCN_INTERVAL(h2c_pkt, value)		       \
603 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(13, 4))
604 
605 #define SET_SCAN_START(h2c_pkt, value)					       \
606 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
607 
608 #define SET_ADAPTIVITY_MODE(h2c_pkt, value)				       \
609 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(11, 8))
610 #define SET_ADAPTIVITY_OPTION(h2c_pkt, value)				       \
611 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 12))
612 #define SET_ADAPTIVITY_IGI(h2c_pkt, value)				       \
613 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
614 #define SET_ADAPTIVITY_L2H(h2c_pkt, value)				       \
615 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
616 #define SET_ADAPTIVITY_DENSITY(h2c_pkt, value)				       \
617 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0))
618 
619 #define SET_PWR_MODE_SET_MODE(h2c_pkt, value)                                  \
620 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(14, 8))
621 #define SET_PWR_MODE_SET_RLBM(h2c_pkt, value)                                  \
622 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(19, 16))
623 #define SET_PWR_MODE_SET_SMART_PS(h2c_pkt, value)                              \
624 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 20))
625 #define SET_PWR_MODE_SET_AWAKE_INTERVAL(h2c_pkt, value)                        \
626 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
627 #define SET_PWR_MODE_SET_PORT_ID(h2c_pkt, value)                               \
628 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 5))
629 #define SET_PWR_MODE_SET_PWR_STATE(h2c_pkt, value)                             \
630 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8))
631 #define LPS_PG_INFO_LOC(h2c_pkt, value)                                        \
632 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
633 #define LPS_PG_DPK_LOC(h2c_pkt, value)                                         \
634 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
635 #define LPS_PG_SEC_CAM_EN(h2c_pkt, value)                                      \
636 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
637 #define LPS_PG_PATTERN_CAM_EN(h2c_pkt, value)				       \
638 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(10))
639 #define SET_RSSI_INFO_MACID(h2c_pkt, value)                                    \
640 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
641 #define SET_RSSI_INFO_RSSI(h2c_pkt, value)                                     \
642 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
643 #define SET_RSSI_INFO_STBC(h2c_pkt, value)                                     \
644 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, BIT(1))
645 #define SET_RA_INFO_MACID(h2c_pkt, value)                                      \
646 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
647 #define SET_RA_INFO_RATE_ID(h2c_pkt, value)                                    \
648 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(20, 16))
649 #define SET_RA_INFO_INIT_RA_LVL(h2c_pkt, value)                                \
650 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(22, 21))
651 #define SET_RA_INFO_SGI_EN(h2c_pkt, value)                                     \
652 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(23))
653 #define SET_RA_INFO_BW_MODE(h2c_pkt, value)                                    \
654 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(25, 24))
655 #define SET_RA_INFO_LDPC(h2c_pkt, value)                                       \
656 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(26))
657 #define SET_RA_INFO_NO_UPDATE(h2c_pkt, value)                                  \
658 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(27))
659 #define SET_RA_INFO_VHT_EN(h2c_pkt, value)                                     \
660 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(29, 28))
661 #define SET_RA_INFO_DIS_PT(h2c_pkt, value)                                     \
662 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(30))
663 #define SET_RA_INFO_RA_MASK0(h2c_pkt, value)                                   \
664 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0))
665 #define SET_RA_INFO_RA_MASK1(h2c_pkt, value)                                   \
666 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8))
667 #define SET_RA_INFO_RA_MASK2(h2c_pkt, value)                                   \
668 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(23, 16))
669 #define SET_RA_INFO_RA_MASK3(h2c_pkt, value)                                   \
670 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(31, 24))
671 #define SET_QUERY_BT_INFO(h2c_pkt, value)                                      \
672 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
673 #define SET_WL_CH_INFO_LINK(h2c_pkt, value)                                    \
674 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
675 #define SET_WL_CH_INFO_CHNL(h2c_pkt, value)                                    \
676 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
677 #define SET_WL_CH_INFO_BW(h2c_pkt, value)                                      \
678 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
679 #define SET_BT_MP_INFO_SEQ(h2c_pkt, value)                                     \
680 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 12))
681 #define SET_BT_MP_INFO_OP_CODE(h2c_pkt, value)                                 \
682 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
683 #define SET_BT_MP_INFO_PARA1(h2c_pkt, value)                                   \
684 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
685 #define SET_BT_MP_INFO_PARA2(h2c_pkt, value)                                   \
686 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0))
687 #define SET_BT_MP_INFO_PARA3(h2c_pkt, value)                                   \
688 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8))
689 #define SET_BT_TX_POWER_INDEX(h2c_pkt, value)                                  \
690 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
691 #define SET_IGNORE_WLAN_ACTION_EN(h2c_pkt, value)                              \
692 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
693 #define SET_COEX_TDMA_TYPE_PARA1(h2c_pkt, value)                               \
694 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
695 #define SET_COEX_TDMA_TYPE_PARA2(h2c_pkt, value)                               \
696 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
697 #define SET_COEX_TDMA_TYPE_PARA3(h2c_pkt, value)                               \
698 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
699 #define SET_COEX_TDMA_TYPE_PARA4(h2c_pkt, value)                               \
700 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0))
701 #define SET_COEX_TDMA_TYPE_PARA5(h2c_pkt, value)                               \
702 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8))
703 #define SET_BT_WIFI_CONTROL_OP_CODE(h2c_pkt, value)                            \
704 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
705 #define SET_BT_WIFI_CONTROL_DATA1(h2c_pkt, value)                              \
706 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
707 #define SET_BT_WIFI_CONTROL_DATA2(h2c_pkt, value)                              \
708 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
709 #define SET_BT_WIFI_CONTROL_DATA3(h2c_pkt, value)                              \
710 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0))
711 #define SET_BT_WIFI_CONTROL_DATA4(h2c_pkt, value)                              \
712 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8))
713 #define SET_BT_WIFI_CONTROL_DATA5(h2c_pkt, value)                              \
714 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(23, 16))
715 
716 #define SET_COEX_QUERY_HID_INFO_SUBID(h2c_pkt, value)                          \
717 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
718 #define SET_COEX_QUERY_HID_INFO_DATA1(h2c_pkt, value)                          \
719 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
720 
721 #define SET_KEEP_ALIVE_ENABLE(h2c_pkt, value)				       \
722 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
723 #define SET_KEEP_ALIVE_ADOPT(h2c_pkt, value)				       \
724 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(9))
725 #define SET_KEEP_ALIVE_PKT_TYPE(h2c_pkt, value)				       \
726 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(10))
727 #define SET_KEEP_ALIVE_CHECK_PERIOD(h2c_pkt, value)			       \
728 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
729 
730 #define SET_DISCONNECT_DECISION_ENABLE(h2c_pkt, value)			       \
731 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
732 #define SET_DISCONNECT_DECISION_ADOPT(h2c_pkt, value)			       \
733 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(9))
734 #define SET_DISCONNECT_DECISION_CHECK_PERIOD(h2c_pkt, value)		       \
735 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
736 #define SET_DISCONNECT_DECISION_TRY_PKT_NUM(h2c_pkt, value)		       \
737 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
738 
739 #define SET_WOWLAN_FUNC_ENABLE(h2c_pkt, value)				       \
740 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
741 #define SET_WOWLAN_PATTERN_MATCH_ENABLE(h2c_pkt, value)			       \
742 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(9))
743 #define SET_WOWLAN_MAGIC_PKT_ENABLE(h2c_pkt, value)			       \
744 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(10))
745 #define SET_WOWLAN_UNICAST_PKT_ENABLE(h2c_pkt, value)			       \
746 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(11))
747 #define SET_WOWLAN_REKEY_WAKEUP_ENABLE(h2c_pkt, value)			       \
748 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(14))
749 #define SET_WOWLAN_DEAUTH_WAKEUP_ENABLE(h2c_pkt, value)			       \
750 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(15))
751 
752 #define SET_REMOTE_WAKECTRL_ENABLE(h2c_pkt, value)			       \
753 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
754 #define SET_REMOTE_WAKE_CTRL_NLO_OFFLOAD_EN(h2c_pkt, value)		       \
755 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(12))
756 
757 #define SET_AOAC_GLOBAL_INFO_PAIRWISE_ENC_ALG(h2c_pkt, value)		       \
758 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
759 #define SET_AOAC_GLOBAL_INFO_GROUP_ENC_ALG(h2c_pkt, value)		       \
760 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
761 
762 #define SET_NLO_FUN_EN(h2c_pkt, value)                                         \
763 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
764 #define SET_NLO_PS_32K(h2c_pkt, value)                                         \
765 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(9))
766 #define SET_NLO_IGNORE_SECURITY(h2c_pkt, value)                                \
767 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(10))
768 #define SET_NLO_LOC_NLO_INFO(h2c_pkt, value)                                   \
769 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
770 
771 #define SET_RECOVER_BT_DEV_EN(h2c_pkt, value)				       \
772 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
773 
774 #define GET_FW_DUMP_LEN(_header)					\
775 	le32_get_bits(*((__le32 *)(_header) + 0x00), GENMASK(15, 0))
776 #define GET_FW_DUMP_SEQ(_header)					\
777 	le32_get_bits(*((__le32 *)(_header) + 0x00), GENMASK(22, 16))
778 #define GET_FW_DUMP_MORE(_header)					\
779 	le32_get_bits(*((__le32 *)(_header) + 0x00), BIT(23))
780 #define GET_FW_DUMP_VERSION(_header)					\
781 	le32_get_bits(*((__le32 *)(_header) + 0x00), GENMASK(31, 24))
782 #define GET_FW_DUMP_TLV_TYPE(_header)					\
783 	le32_get_bits(*((__le32 *)(_header) + 0x01), GENMASK(15, 0))
784 #define GET_FW_DUMP_TLV_LEN(_header)					\
785 	le32_get_bits(*((__le32 *)(_header) + 0x01), GENMASK(31, 16))
786 #define GET_FW_DUMP_TLV_VAL(_header)					\
787 	le32_get_bits(*((__le32 *)(_header) + 0x02), GENMASK(31, 0))
788 
789 #define RFK_SET_INFORM_START(h2c_pkt, value)				\
790 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
get_c2h_from_skb(struct sk_buff * skb)791 static inline struct rtw_c2h_cmd *get_c2h_from_skb(struct sk_buff *skb)
792 {
793 	u32 pkt_offset;
794 
795 	pkt_offset = *((u32 *)skb->cb);
796 	return (struct rtw_c2h_cmd *)(skb->data + pkt_offset);
797 }
798 
rtw_fw_feature_check(struct rtw_fw_state * fw,enum rtw_fw_feature feature)799 static inline bool rtw_fw_feature_check(struct rtw_fw_state *fw,
800 					enum rtw_fw_feature feature)
801 {
802 	return !!(fw->feature & feature);
803 }
804 
rtw_fw_feature_ext_check(struct rtw_fw_state * fw,enum rtw_fw_feature_ext feature)805 static inline bool rtw_fw_feature_ext_check(struct rtw_fw_state *fw,
806 					    enum rtw_fw_feature_ext feature)
807 {
808 	return !!(fw->feature_ext & feature);
809 }
810 
811 void rtw_fw_c2h_cmd_rx_irqsafe(struct rtw_dev *rtwdev, u32 pkt_offset,
812 			       struct sk_buff *skb);
813 void rtw_fw_c2h_cmd_handle(struct rtw_dev *rtwdev, struct sk_buff *skb);
814 void rtw_fw_send_general_info(struct rtw_dev *rtwdev);
815 void rtw_fw_send_phydm_info(struct rtw_dev *rtwdev);
816 void rtw_fw_default_port(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif);
817 
818 void rtw_fw_do_iqk(struct rtw_dev *rtwdev, struct rtw_iqk_para *para);
819 void rtw_fw_inform_rfk_status(struct rtw_dev *rtwdev, bool start);
820 void rtw_fw_set_pwr_mode(struct rtw_dev *rtwdev);
821 void rtw_fw_set_pg_info(struct rtw_dev *rtwdev);
822 void rtw_fw_query_bt_info(struct rtw_dev *rtwdev);
823 void rtw_fw_wl_ch_info(struct rtw_dev *rtwdev, u8 link, u8 ch, u8 bw);
824 void rtw_fw_query_bt_mp_info(struct rtw_dev *rtwdev,
825 			     struct rtw_coex_info_req *req);
826 void rtw_fw_force_bt_tx_power(struct rtw_dev *rtwdev, u8 bt_pwr_dec_lvl);
827 void rtw_fw_bt_ignore_wlan_action(struct rtw_dev *rtwdev, bool enable);
828 void rtw_fw_coex_tdma_type(struct rtw_dev *rtwdev,
829 			   u8 para1, u8 para2, u8 para3, u8 para4, u8 para5);
830 void rtw_fw_coex_query_hid_info(struct rtw_dev *rtwdev, u8 sub_id, u8 data);
831 
832 void rtw_fw_bt_wifi_control(struct rtw_dev *rtwdev, u8 op_code, u8 *data);
833 void rtw_fw_send_rssi_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si);
834 void rtw_fw_send_ra_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si,
835 			 bool reset_ra_mask);
836 void rtw_fw_media_status_report(struct rtw_dev *rtwdev, u8 mac_id, bool conn);
837 void rtw_fw_update_wl_phy_info(struct rtw_dev *rtwdev);
838 void rtw_fw_beacon_filter_config(struct rtw_dev *rtwdev, bool connect,
839 				 struct ieee80211_vif *vif);
840 int rtw_fw_write_data_rsvd_page(struct rtw_dev *rtwdev, u16 pg_addr,
841 				u8 *buf, u32 size);
842 void rtw_remove_rsvd_page(struct rtw_dev *rtwdev,
843 			  struct rtw_vif *rtwvif);
844 void rtw_add_rsvd_page_bcn(struct rtw_dev *rtwdev,
845 			   struct rtw_vif *rtwvif);
846 void rtw_add_rsvd_page_pno(struct rtw_dev *rtwdev,
847 			   struct rtw_vif *rtwvif);
848 void rtw_add_rsvd_page_sta(struct rtw_dev *rtwdev,
849 			   struct rtw_vif *rtwvif);
850 int rtw_fw_download_rsvd_page(struct rtw_dev *rtwdev);
851 void rtw_fw_update_beacon_work(struct work_struct *work);
852 void rtw_send_rsvd_page_h2c(struct rtw_dev *rtwdev);
853 int rtw_dump_drv_rsvd_page(struct rtw_dev *rtwdev,
854 			   u32 offset, u32 size, u32 *buf);
855 void rtw_fw_set_remote_wake_ctrl_cmd(struct rtw_dev *rtwdev, bool enable);
856 void rtw_fw_set_wowlan_ctrl_cmd(struct rtw_dev *rtwdev, bool enable);
857 void rtw_fw_set_keep_alive_cmd(struct rtw_dev *rtwdev, bool enable);
858 void rtw_fw_set_disconnect_decision_cmd(struct rtw_dev *rtwdev, bool enable);
859 void rtw_fw_set_aoac_global_info_cmd(struct rtw_dev *rtwdev,
860 				     u8 pairwise_key_enc,
861 				     u8 group_key_enc);
862 
863 void rtw_fw_set_nlo_info(struct rtw_dev *rtwdev, bool enable);
864 void rtw_fw_set_recover_bt_device(struct rtw_dev *rtwdev);
865 void rtw_fw_update_pkt_probe_req(struct rtw_dev *rtwdev,
866 				 struct cfg80211_ssid *ssid);
867 void rtw_fw_channel_switch(struct rtw_dev *rtwdev, bool enable);
868 void rtw_fw_h2c_cmd_dbg(struct rtw_dev *rtwdev, u8 *h2c);
869 void rtw_fw_c2h_cmd_isr(struct rtw_dev *rtwdev);
870 int rtw_fw_dump_fifo(struct rtw_dev *rtwdev, u8 fifo_sel, u32 addr, u32 size,
871 		     u32 *buffer);
872 void rtw_fw_scan_notify(struct rtw_dev *rtwdev, bool start);
873 void rtw_fw_adaptivity(struct rtw_dev *rtwdev);
874 void rtw_store_op_chan(struct rtw_dev *rtwdev, bool backup);
875 void rtw_clear_op_chan(struct rtw_dev *rtwdev);
876 void rtw_hw_scan_start(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
877 		       struct ieee80211_scan_request *req);
878 void rtw_hw_scan_complete(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
879 			  bool aborted);
880 int rtw_hw_scan_offload(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
881 			bool enable);
882 void rtw_hw_scan_status_report(struct rtw_dev *rtwdev, struct sk_buff *skb);
883 void rtw_hw_scan_chan_switch(struct rtw_dev *rtwdev, struct sk_buff *skb);
884 void rtw_hw_scan_abort(struct rtw_dev *rtwdev);
885 #endif
886