xref: /openbmc/u-boot/drivers/spi/fsl_qspi.c (revision a1588ac8)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright 2013-2015 Freescale Semiconductor, Inc.
4  *
5  * Freescale Quad Serial Peripheral Interface (QSPI) driver
6  */
7 
8 #include <common.h>
9 #include <malloc.h>
10 #include <spi.h>
11 #include <asm/io.h>
12 #include <linux/sizes.h>
13 #include <dm.h>
14 #include <errno.h>
15 #include <watchdog.h>
16 #include <wait_bit.h>
17 #include "fsl_qspi.h"
18 
19 DECLARE_GLOBAL_DATA_PTR;
20 
21 #define RX_BUFFER_SIZE		0x80
22 #if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
23 	defined(CONFIG_MX6ULL) || defined(CONFIG_MX7D)
24 #define TX_BUFFER_SIZE		0x200
25 #else
26 #define TX_BUFFER_SIZE		0x40
27 #endif
28 
29 #define OFFSET_BITS_MASK	GENMASK(23, 0)
30 
31 #define FLASH_STATUS_WEL	0x02
32 
33 /* SEQID */
34 #define SEQID_WREN		1
35 #define SEQID_FAST_READ		2
36 #define SEQID_RDSR		3
37 #define SEQID_SE		4
38 #define SEQID_CHIP_ERASE	5
39 #define SEQID_PP		6
40 #define SEQID_RDID		7
41 #define SEQID_BE_4K		8
42 #ifdef CONFIG_SPI_FLASH_BAR
43 #define SEQID_BRRD		9
44 #define SEQID_BRWR		10
45 #define SEQID_RDEAR		11
46 #define SEQID_WREAR		12
47 #endif
48 #define SEQID_WRAR		13
49 #define SEQID_RDAR		14
50 
51 /* QSPI CMD */
52 #define QSPI_CMD_PP		0x02	/* Page program (up to 256 bytes) */
53 #define QSPI_CMD_RDSR		0x05	/* Read status register */
54 #define QSPI_CMD_WREN		0x06	/* Write enable */
55 #define QSPI_CMD_FAST_READ	0x0b	/* Read data bytes (high frequency) */
56 #define QSPI_CMD_BE_4K		0x20    /* 4K erase */
57 #define QSPI_CMD_CHIP_ERASE	0xc7	/* Erase whole flash chip */
58 #define QSPI_CMD_SE		0xd8	/* Sector erase (usually 64KiB) */
59 #define QSPI_CMD_RDID		0x9f	/* Read JEDEC ID */
60 
61 /* Used for Micron, winbond and Macronix flashes */
62 #define	QSPI_CMD_WREAR		0xc5	/* EAR register write */
63 #define	QSPI_CMD_RDEAR		0xc8	/* EAR reigster read */
64 
65 /* Used for Spansion flashes only. */
66 #define	QSPI_CMD_BRRD		0x16	/* Bank register read */
67 #define	QSPI_CMD_BRWR		0x17	/* Bank register write */
68 
69 /* Used for Spansion S25FS-S family flash only. */
70 #define QSPI_CMD_RDAR		0x65	/* Read any device register */
71 #define QSPI_CMD_WRAR		0x71	/* Write any device register */
72 
73 /* 4-byte address QSPI CMD - used on Spansion and some Macronix flashes */
74 #define QSPI_CMD_FAST_READ_4B	0x0c    /* Read data bytes (high frequency) */
75 #define QSPI_CMD_PP_4B		0x12    /* Page program (up to 256 bytes) */
76 #define QSPI_CMD_SE_4B		0xdc    /* Sector erase (usually 64KiB) */
77 
78 /* fsl_qspi_platdata flags */
79 #define QSPI_FLAG_REGMAP_ENDIAN_BIG	BIT(0)
80 
81 /* default SCK frequency, unit: HZ */
82 #define FSL_QSPI_DEFAULT_SCK_FREQ	50000000
83 
84 /* QSPI max chipselect signals number */
85 #define FSL_QSPI_MAX_CHIPSELECT_NUM     4
86 
87 /**
88  * struct fsl_qspi_platdata - platform data for Freescale QSPI
89  *
90  * @flags: Flags for QSPI QSPI_FLAG_...
91  * @speed_hz: Default SCK frequency
92  * @reg_base: Base address of QSPI registers
93  * @amba_base: Base address of QSPI memory mapping
94  * @amba_total_size: size of QSPI memory mapping
95  * @flash_num: Number of active slave devices
96  * @num_chipselect: Number of QSPI chipselect signals
97  */
98 struct fsl_qspi_platdata {
99 	u32 flags;
100 	u32 speed_hz;
101 	fdt_addr_t reg_base;
102 	fdt_addr_t amba_base;
103 	fdt_size_t amba_total_size;
104 	u32 flash_num;
105 	u32 num_chipselect;
106 };
107 
108 /**
109  * struct fsl_qspi_priv - private data for Freescale QSPI
110  *
111  * @flags: Flags for QSPI QSPI_FLAG_...
112  * @bus_clk: QSPI input clk frequency
113  * @speed_hz: Default SCK frequency
114  * @cur_seqid: current LUT table sequence id
115  * @sf_addr: flash access offset
116  * @amba_base: Base address of QSPI memory mapping of every CS
117  * @amba_total_size: size of QSPI memory mapping
118  * @cur_amba_base: Base address of QSPI memory mapping of current CS
119  * @flash_num: Number of active slave devices
120  * @num_chipselect: Number of QSPI chipselect signals
121  * @regs: Point to QSPI register structure for I/O access
122  */
123 struct fsl_qspi_priv {
124 	u32 flags;
125 	u32 bus_clk;
126 	u32 speed_hz;
127 	u32 cur_seqid;
128 	u32 sf_addr;
129 	u32 amba_base[FSL_QSPI_MAX_CHIPSELECT_NUM];
130 	u32 amba_total_size;
131 	u32 cur_amba_base;
132 	u32 flash_num;
133 	u32 num_chipselect;
134 	struct fsl_qspi_regs *regs;
135 };
136 
137 
qspi_read32(u32 flags,u32 * addr)138 static u32 qspi_read32(u32 flags, u32 *addr)
139 {
140 	return flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ?
141 		in_be32(addr) : in_le32(addr);
142 }
143 
qspi_write32(u32 flags,u32 * addr,u32 val)144 static void qspi_write32(u32 flags, u32 *addr, u32 val)
145 {
146 	flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ?
147 		out_be32(addr, val) : out_le32(addr, val);
148 }
149 
is_controller_busy(const struct fsl_qspi_priv * priv)150 static inline int is_controller_busy(const struct fsl_qspi_priv *priv)
151 {
152 	u32 val;
153 	const u32 mask = QSPI_SR_BUSY_MASK | QSPI_SR_AHB_ACC_MASK |
154 			 QSPI_SR_IP_ACC_MASK;
155 	unsigned int retry = 5;
156 
157 	do {
158 		val = qspi_read32(priv->flags, &priv->regs->sr);
159 
160 		if ((~val & mask) == mask)
161 			return 0;
162 
163 		udelay(1);
164 	} while (--retry);
165 
166 	return -ETIMEDOUT;
167 }
168 
169 /* QSPI support swapping the flash read/write data
170  * in hardware for LS102xA, but not for VF610 */
qspi_endian_xchg(u32 data)171 static inline u32 qspi_endian_xchg(u32 data)
172 {
173 #ifdef CONFIG_VF610
174 	return swab32(data);
175 #else
176 	return data;
177 #endif
178 }
179 
qspi_set_lut(struct fsl_qspi_priv * priv)180 static void qspi_set_lut(struct fsl_qspi_priv *priv)
181 {
182 	struct fsl_qspi_regs *regs = priv->regs;
183 	u32 lut_base;
184 
185 	/* Unlock the LUT */
186 	qspi_write32(priv->flags, &regs->lutkey, LUT_KEY_VALUE);
187 	qspi_write32(priv->flags, &regs->lckcr, QSPI_LCKCR_UNLOCK);
188 
189 	/* Write Enable */
190 	lut_base = SEQID_WREN * 4;
191 	qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_WREN) |
192 		PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
193 	qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
194 	qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
195 	qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
196 
197 	/* Fast Read */
198 	lut_base = SEQID_FAST_READ * 4;
199 #ifdef CONFIG_SPI_FLASH_BAR
200 	qspi_write32(priv->flags, &regs->lut[lut_base],
201 		     OPRND0(QSPI_CMD_FAST_READ) | PAD0(LUT_PAD1) |
202 		     INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
203 		     PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
204 #else
205 	if (FSL_QSPI_FLASH_SIZE  <= SZ_16M)
206 		qspi_write32(priv->flags, &regs->lut[lut_base],
207 			     OPRND0(QSPI_CMD_FAST_READ) | PAD0(LUT_PAD1) |
208 			     INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
209 			     PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
210 	else
211 		qspi_write32(priv->flags, &regs->lut[lut_base],
212 			     OPRND0(QSPI_CMD_FAST_READ_4B) |
213 			     PAD0(LUT_PAD1) | INSTR0(LUT_CMD) |
214 			     OPRND1(ADDR32BIT) | PAD1(LUT_PAD1) |
215 			     INSTR1(LUT_ADDR));
216 #endif
217 	qspi_write32(priv->flags, &regs->lut[lut_base + 1],
218 		     OPRND0(8) | PAD0(LUT_PAD1) | INSTR0(LUT_DUMMY) |
219 		     OPRND1(RX_BUFFER_SIZE) | PAD1(LUT_PAD1) |
220 		     INSTR1(LUT_READ));
221 	qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
222 	qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
223 
224 	/* Read Status */
225 	lut_base = SEQID_RDSR * 4;
226 	qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDSR) |
227 		PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
228 		PAD1(LUT_PAD1) | INSTR1(LUT_READ));
229 	qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
230 	qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
231 	qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
232 
233 	/* Erase a sector */
234 	lut_base = SEQID_SE * 4;
235 #ifdef CONFIG_SPI_FLASH_BAR
236 	qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_SE) |
237 		     PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
238 		     PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
239 #else
240 	if (FSL_QSPI_FLASH_SIZE  <= SZ_16M)
241 		qspi_write32(priv->flags, &regs->lut[lut_base],
242 			     OPRND0(QSPI_CMD_SE) | PAD0(LUT_PAD1) |
243 			     INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
244 			     PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
245 	else
246 		qspi_write32(priv->flags, &regs->lut[lut_base],
247 			     OPRND0(QSPI_CMD_SE_4B) | PAD0(LUT_PAD1) |
248 			     INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
249 			     PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
250 #endif
251 	qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
252 	qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
253 	qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
254 
255 	/* Erase the whole chip */
256 	lut_base = SEQID_CHIP_ERASE * 4;
257 	qspi_write32(priv->flags, &regs->lut[lut_base],
258 		     OPRND0(QSPI_CMD_CHIP_ERASE) |
259 		     PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
260 	qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
261 	qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
262 	qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
263 
264 	/* Page Program */
265 	lut_base = SEQID_PP * 4;
266 #ifdef CONFIG_SPI_FLASH_BAR
267 	qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_PP) |
268 		     PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
269 		     PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
270 #else
271 	if (FSL_QSPI_FLASH_SIZE  <= SZ_16M)
272 		qspi_write32(priv->flags, &regs->lut[lut_base],
273 			     OPRND0(QSPI_CMD_PP) | PAD0(LUT_PAD1) |
274 			     INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
275 			     PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
276 	else
277 		qspi_write32(priv->flags, &regs->lut[lut_base],
278 			     OPRND0(QSPI_CMD_PP_4B) | PAD0(LUT_PAD1) |
279 			     INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
280 			     PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
281 #endif
282 #if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
283 	defined(CONFIG_MX6ULL) || defined(CONFIG_MX7D)
284 	/*
285 	 * To MX6SX, OPRND0(TX_BUFFER_SIZE) can not work correctly.
286 	 * So, Use IDATSZ in IPCR to determine the size and here set 0.
287 	 */
288 	qspi_write32(priv->flags, &regs->lut[lut_base + 1], OPRND0(0) |
289 		     PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
290 #else
291 	qspi_write32(priv->flags, &regs->lut[lut_base + 1],
292 		     OPRND0(TX_BUFFER_SIZE) |
293 		     PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
294 #endif
295 	qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
296 	qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
297 
298 	/* READ ID */
299 	lut_base = SEQID_RDID * 4;
300 	qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDID) |
301 		PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(8) |
302 		PAD1(LUT_PAD1) | INSTR1(LUT_READ));
303 	qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
304 	qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
305 	qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
306 
307 	/* SUB SECTOR 4K ERASE */
308 	lut_base = SEQID_BE_4K * 4;
309 	qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BE_4K) |
310 		     PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
311 		     PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
312 
313 #ifdef CONFIG_SPI_FLASH_BAR
314 	/*
315 	 * BRRD BRWR RDEAR WREAR are all supported, because it is hard to
316 	 * dynamically check whether to set BRRD BRWR or RDEAR WREAR during
317 	 * initialization.
318 	 */
319 	lut_base = SEQID_BRRD * 4;
320 	qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BRRD) |
321 		     PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
322 		     PAD1(LUT_PAD1) | INSTR1(LUT_READ));
323 
324 	lut_base = SEQID_BRWR * 4;
325 	qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BRWR) |
326 		     PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
327 		     PAD1(LUT_PAD1) | INSTR1(LUT_WRITE));
328 
329 	lut_base = SEQID_RDEAR * 4;
330 	qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDEAR) |
331 		     PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
332 		     PAD1(LUT_PAD1) | INSTR1(LUT_READ));
333 
334 	lut_base = SEQID_WREAR * 4;
335 	qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_WREAR) |
336 		     PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
337 		     PAD1(LUT_PAD1) | INSTR1(LUT_WRITE));
338 #endif
339 
340 	/*
341 	 * Read any device register.
342 	 * Used for Spansion S25FS-S family flash only.
343 	 */
344 	lut_base = SEQID_RDAR * 4;
345 	qspi_write32(priv->flags, &regs->lut[lut_base],
346 		     OPRND0(QSPI_CMD_RDAR) | PAD0(LUT_PAD1) |
347 		     INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
348 		     PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
349 	qspi_write32(priv->flags, &regs->lut[lut_base + 1],
350 		     OPRND0(8) | PAD0(LUT_PAD1) | INSTR0(LUT_DUMMY) |
351 		     OPRND1(1) | PAD1(LUT_PAD1) |
352 		     INSTR1(LUT_READ));
353 
354 	/*
355 	 * Write any device register.
356 	 * Used for Spansion S25FS-S family flash only.
357 	 */
358 	lut_base = SEQID_WRAR * 4;
359 	qspi_write32(priv->flags, &regs->lut[lut_base],
360 		     OPRND0(QSPI_CMD_WRAR) | PAD0(LUT_PAD1) |
361 		     INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
362 		     PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
363 	qspi_write32(priv->flags, &regs->lut[lut_base + 1],
364 		     OPRND0(1) | PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
365 
366 	/* Lock the LUT */
367 	qspi_write32(priv->flags, &regs->lutkey, LUT_KEY_VALUE);
368 	qspi_write32(priv->flags, &regs->lckcr, QSPI_LCKCR_LOCK);
369 }
370 
371 #if defined(CONFIG_SYS_FSL_QSPI_AHB)
372 /*
373  * If we have changed the content of the flash by writing or erasing,
374  * we need to invalidate the AHB buffer. If we do not do so, we may read out
375  * the wrong data. The spec tells us reset the AHB domain and Serial Flash
376  * domain at the same time.
377  */
qspi_ahb_invalid(struct fsl_qspi_priv * priv)378 static inline void qspi_ahb_invalid(struct fsl_qspi_priv *priv)
379 {
380 	struct fsl_qspi_regs *regs = priv->regs;
381 	u32 reg;
382 
383 	reg = qspi_read32(priv->flags, &regs->mcr);
384 	reg |= QSPI_MCR_SWRSTHD_MASK | QSPI_MCR_SWRSTSD_MASK;
385 	qspi_write32(priv->flags, &regs->mcr, reg);
386 
387 	/*
388 	 * The minimum delay : 1 AHB + 2 SFCK clocks.
389 	 * Delay 1 us is enough.
390 	 */
391 	udelay(1);
392 
393 	reg &= ~(QSPI_MCR_SWRSTHD_MASK | QSPI_MCR_SWRSTSD_MASK);
394 	qspi_write32(priv->flags, &regs->mcr, reg);
395 }
396 
397 /* Read out the data from the AHB buffer. */
qspi_ahb_read(struct fsl_qspi_priv * priv,u8 * rxbuf,int len)398 static inline void qspi_ahb_read(struct fsl_qspi_priv *priv, u8 *rxbuf, int len)
399 {
400 	struct fsl_qspi_regs *regs = priv->regs;
401 	u32 mcr_reg;
402 	void *rx_addr;
403 
404 	mcr_reg = qspi_read32(priv->flags, &regs->mcr);
405 
406 	qspi_write32(priv->flags, &regs->mcr,
407 		     QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
408 		     QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
409 
410 	rx_addr = (void *)(uintptr_t)(priv->cur_amba_base + priv->sf_addr);
411 	/* Read out the data directly from the AHB buffer. */
412 	memcpy(rxbuf, rx_addr, len);
413 
414 	qspi_write32(priv->flags, &regs->mcr, mcr_reg);
415 }
416 
qspi_enable_ddr_mode(struct fsl_qspi_priv * priv)417 static void qspi_enable_ddr_mode(struct fsl_qspi_priv *priv)
418 {
419 	u32 reg, reg2;
420 	struct fsl_qspi_regs *regs = priv->regs;
421 
422 	reg = qspi_read32(priv->flags, &regs->mcr);
423 	/* Disable the module */
424 	qspi_write32(priv->flags, &regs->mcr, reg | QSPI_MCR_MDIS_MASK);
425 
426 	/* Set the Sampling Register for DDR */
427 	reg2 = qspi_read32(priv->flags, &regs->smpr);
428 	reg2 &= ~QSPI_SMPR_DDRSMP_MASK;
429 	reg2 |= (2 << QSPI_SMPR_DDRSMP_SHIFT);
430 	qspi_write32(priv->flags, &regs->smpr, reg2);
431 
432 	/* Enable the module again (enable the DDR too) */
433 	reg |= QSPI_MCR_DDR_EN_MASK;
434 	/* Enable bit 29 for imx6sx */
435 	reg |= BIT(29);
436 
437 	qspi_write32(priv->flags, &regs->mcr, reg);
438 }
439 
440 /*
441  * There are two different ways to read out the data from the flash:
442  *  the "IP Command Read" and the "AHB Command Read".
443  *
444  * The IC guy suggests we use the "AHB Command Read" which is faster
445  * then the "IP Command Read". (What's more is that there is a bug in
446  * the "IP Command Read" in the Vybrid.)
447  *
448  * After we set up the registers for the "AHB Command Read", we can use
449  * the memcpy to read the data directly. A "missed" access to the buffer
450  * causes the controller to clear the buffer, and use the sequence pointed
451  * by the QUADSPI_BFGENCR[SEQID] to initiate a read from the flash.
452  */
qspi_init_ahb_read(struct fsl_qspi_priv * priv)453 static void qspi_init_ahb_read(struct fsl_qspi_priv *priv)
454 {
455 	struct fsl_qspi_regs *regs = priv->regs;
456 
457 	/* AHB configuration for access buffer 0/1/2 .*/
458 	qspi_write32(priv->flags, &regs->buf0cr, QSPI_BUFXCR_INVALID_MSTRID);
459 	qspi_write32(priv->flags, &regs->buf1cr, QSPI_BUFXCR_INVALID_MSTRID);
460 	qspi_write32(priv->flags, &regs->buf2cr, QSPI_BUFXCR_INVALID_MSTRID);
461 	qspi_write32(priv->flags, &regs->buf3cr, QSPI_BUF3CR_ALLMST_MASK |
462 		     (0x80 << QSPI_BUF3CR_ADATSZ_SHIFT));
463 
464 	/* We only use the buffer3 */
465 	qspi_write32(priv->flags, &regs->buf0ind, 0);
466 	qspi_write32(priv->flags, &regs->buf1ind, 0);
467 	qspi_write32(priv->flags, &regs->buf2ind, 0);
468 
469 	/*
470 	 * Set the default lut sequence for AHB Read.
471 	 * Parallel mode is disabled.
472 	 */
473 	qspi_write32(priv->flags, &regs->bfgencr,
474 		     SEQID_FAST_READ << QSPI_BFGENCR_SEQID_SHIFT);
475 
476 	/*Enable DDR Mode*/
477 	qspi_enable_ddr_mode(priv);
478 }
479 #endif
480 
481 #ifdef CONFIG_SPI_FLASH_BAR
482 /* Bank register read/write, EAR register read/write */
qspi_op_rdbank(struct fsl_qspi_priv * priv,u8 * rxbuf,u32 len)483 static void qspi_op_rdbank(struct fsl_qspi_priv *priv, u8 *rxbuf, u32 len)
484 {
485 	struct fsl_qspi_regs *regs = priv->regs;
486 	u32 reg, mcr_reg, data, seqid;
487 
488 	mcr_reg = qspi_read32(priv->flags, &regs->mcr);
489 	qspi_write32(priv->flags, &regs->mcr,
490 		     QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
491 		     QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
492 	qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
493 
494 	qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);
495 
496 	if (priv->cur_seqid == QSPI_CMD_BRRD)
497 		seqid = SEQID_BRRD;
498 	else
499 		seqid = SEQID_RDEAR;
500 
501 	qspi_write32(priv->flags, &regs->ipcr,
502 		     (seqid << QSPI_IPCR_SEQID_SHIFT) | len);
503 
504 	/* Wait previous command complete */
505 	while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
506 		;
507 
508 	while (1) {
509 		WATCHDOG_RESET();
510 
511 		reg = qspi_read32(priv->flags, &regs->rbsr);
512 		if (reg & QSPI_RBSR_RDBFL_MASK) {
513 			data = qspi_read32(priv->flags, &regs->rbdr[0]);
514 			data = qspi_endian_xchg(data);
515 			memcpy(rxbuf, &data, len);
516 			qspi_write32(priv->flags, &regs->mcr,
517 				     qspi_read32(priv->flags, &regs->mcr) |
518 				     QSPI_MCR_CLR_RXF_MASK);
519 			break;
520 		}
521 	}
522 
523 	qspi_write32(priv->flags, &regs->mcr, mcr_reg);
524 }
525 #endif
526 
qspi_op_rdid(struct fsl_qspi_priv * priv,u32 * rxbuf,u32 len)527 static void qspi_op_rdid(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len)
528 {
529 	struct fsl_qspi_regs *regs = priv->regs;
530 	u32 mcr_reg, rbsr_reg, data, size;
531 	int i;
532 
533 	mcr_reg = qspi_read32(priv->flags, &regs->mcr);
534 	qspi_write32(priv->flags, &regs->mcr,
535 		     QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
536 		     QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
537 	qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
538 
539 	qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);
540 
541 	qspi_write32(priv->flags, &regs->ipcr,
542 		     (SEQID_RDID << QSPI_IPCR_SEQID_SHIFT) | 0);
543 	while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
544 		;
545 
546 	i = 0;
547 	while ((RX_BUFFER_SIZE >= len) && (len > 0)) {
548 		WATCHDOG_RESET();
549 
550 		rbsr_reg = qspi_read32(priv->flags, &regs->rbsr);
551 		if (rbsr_reg & QSPI_RBSR_RDBFL_MASK) {
552 			data = qspi_read32(priv->flags, &regs->rbdr[i]);
553 			data = qspi_endian_xchg(data);
554 			size = (len < 4) ? len : 4;
555 			memcpy(rxbuf, &data, size);
556 			len -= size;
557 			rxbuf++;
558 			i++;
559 		}
560 	}
561 
562 	qspi_write32(priv->flags, &regs->mcr, mcr_reg);
563 }
564 
565 /* If not use AHB read, read data from ip interface */
qspi_op_read(struct fsl_qspi_priv * priv,u32 * rxbuf,u32 len)566 static void qspi_op_read(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len)
567 {
568 	struct fsl_qspi_regs *regs = priv->regs;
569 	u32 mcr_reg, data;
570 	int i, size;
571 	u32 to_or_from;
572 	u32 seqid;
573 
574 	if (priv->cur_seqid == QSPI_CMD_RDAR)
575 		seqid = SEQID_RDAR;
576 	else
577 		seqid = SEQID_FAST_READ;
578 
579 	mcr_reg = qspi_read32(priv->flags, &regs->mcr);
580 	qspi_write32(priv->flags, &regs->mcr,
581 		     QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
582 		     QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
583 	qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
584 
585 	to_or_from = priv->sf_addr + priv->cur_amba_base;
586 
587 	while (len > 0) {
588 		WATCHDOG_RESET();
589 
590 		qspi_write32(priv->flags, &regs->sfar, to_or_from);
591 
592 		size = (len > RX_BUFFER_SIZE) ?
593 			RX_BUFFER_SIZE : len;
594 
595 		qspi_write32(priv->flags, &regs->ipcr,
596 			     (seqid << QSPI_IPCR_SEQID_SHIFT) |
597 			     size);
598 		while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
599 			;
600 
601 		to_or_from += size;
602 		len -= size;
603 
604 		i = 0;
605 		while ((RX_BUFFER_SIZE >= size) && (size > 0)) {
606 			data = qspi_read32(priv->flags, &regs->rbdr[i]);
607 			data = qspi_endian_xchg(data);
608 			if (size < 4)
609 				memcpy(rxbuf, &data, size);
610 			else
611 				memcpy(rxbuf, &data, 4);
612 			rxbuf++;
613 			size -= 4;
614 			i++;
615 		}
616 		qspi_write32(priv->flags, &regs->mcr,
617 			     qspi_read32(priv->flags, &regs->mcr) |
618 			     QSPI_MCR_CLR_RXF_MASK);
619 	}
620 
621 	qspi_write32(priv->flags, &regs->mcr, mcr_reg);
622 }
623 
qspi_op_write(struct fsl_qspi_priv * priv,u8 * txbuf,u32 len)624 static void qspi_op_write(struct fsl_qspi_priv *priv, u8 *txbuf, u32 len)
625 {
626 	struct fsl_qspi_regs *regs = priv->regs;
627 	u32 mcr_reg, data, reg, status_reg, seqid;
628 	int i, size, tx_size;
629 	u32 to_or_from = 0;
630 
631 	mcr_reg = qspi_read32(priv->flags, &regs->mcr);
632 	qspi_write32(priv->flags, &regs->mcr,
633 		     QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
634 		     QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
635 	qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
636 
637 	status_reg = 0;
638 	while ((status_reg & FLASH_STATUS_WEL) != FLASH_STATUS_WEL) {
639 		WATCHDOG_RESET();
640 
641 		qspi_write32(priv->flags, &regs->ipcr,
642 			     (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0);
643 		while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
644 			;
645 
646 		qspi_write32(priv->flags, &regs->ipcr,
647 			     (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 1);
648 		while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
649 			;
650 
651 		reg = qspi_read32(priv->flags, &regs->rbsr);
652 		if (reg & QSPI_RBSR_RDBFL_MASK) {
653 			status_reg = qspi_read32(priv->flags, &regs->rbdr[0]);
654 			status_reg = qspi_endian_xchg(status_reg);
655 		}
656 		qspi_write32(priv->flags, &regs->mcr,
657 			     qspi_read32(priv->flags, &regs->mcr) |
658 			     QSPI_MCR_CLR_RXF_MASK);
659 	}
660 
661 	/* Default is page programming */
662 	seqid = SEQID_PP;
663 	if (priv->cur_seqid == QSPI_CMD_WRAR)
664 		seqid = SEQID_WRAR;
665 #ifdef CONFIG_SPI_FLASH_BAR
666 	if (priv->cur_seqid == QSPI_CMD_BRWR)
667 		seqid = SEQID_BRWR;
668 	else if (priv->cur_seqid == QSPI_CMD_WREAR)
669 		seqid = SEQID_WREAR;
670 #endif
671 
672 	to_or_from = priv->sf_addr + priv->cur_amba_base;
673 
674 	qspi_write32(priv->flags, &regs->sfar, to_or_from);
675 
676 	tx_size = (len > TX_BUFFER_SIZE) ?
677 		TX_BUFFER_SIZE : len;
678 
679 	size = tx_size / 16;
680 	/*
681 	 * There must be atleast 128bit data
682 	 * available in TX FIFO for any pop operation
683 	 */
684 	if (tx_size % 16)
685 		size++;
686 	for (i = 0; i < size * 4; i++) {
687 		memcpy(&data, txbuf, 4);
688 		data = qspi_endian_xchg(data);
689 		qspi_write32(priv->flags, &regs->tbdr, data);
690 		txbuf += 4;
691 	}
692 
693 	qspi_write32(priv->flags, &regs->ipcr,
694 		     (seqid << QSPI_IPCR_SEQID_SHIFT) | tx_size);
695 	while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
696 		;
697 
698 	qspi_write32(priv->flags, &regs->mcr, mcr_reg);
699 }
700 
qspi_op_rdsr(struct fsl_qspi_priv * priv,void * rxbuf,u32 len)701 static void qspi_op_rdsr(struct fsl_qspi_priv *priv, void *rxbuf, u32 len)
702 {
703 	struct fsl_qspi_regs *regs = priv->regs;
704 	u32 mcr_reg, reg, data;
705 
706 	mcr_reg = qspi_read32(priv->flags, &regs->mcr);
707 	qspi_write32(priv->flags, &regs->mcr,
708 		     QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
709 		     QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
710 	qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
711 
712 	qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);
713 
714 	qspi_write32(priv->flags, &regs->ipcr,
715 		     (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 0);
716 	while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
717 		;
718 
719 	while (1) {
720 		WATCHDOG_RESET();
721 
722 		reg = qspi_read32(priv->flags, &regs->rbsr);
723 		if (reg & QSPI_RBSR_RDBFL_MASK) {
724 			data = qspi_read32(priv->flags, &regs->rbdr[0]);
725 			data = qspi_endian_xchg(data);
726 			memcpy(rxbuf, &data, len);
727 			qspi_write32(priv->flags, &regs->mcr,
728 				     qspi_read32(priv->flags, &regs->mcr) |
729 				     QSPI_MCR_CLR_RXF_MASK);
730 			break;
731 		}
732 	}
733 
734 	qspi_write32(priv->flags, &regs->mcr, mcr_reg);
735 }
736 
qspi_op_erase(struct fsl_qspi_priv * priv)737 static void qspi_op_erase(struct fsl_qspi_priv *priv)
738 {
739 	struct fsl_qspi_regs *regs = priv->regs;
740 	u32 mcr_reg;
741 	u32 to_or_from = 0;
742 
743 	mcr_reg = qspi_read32(priv->flags, &regs->mcr);
744 	qspi_write32(priv->flags, &regs->mcr,
745 		     QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
746 		     QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
747 	qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
748 
749 	to_or_from = priv->sf_addr + priv->cur_amba_base;
750 	qspi_write32(priv->flags, &regs->sfar, to_or_from);
751 
752 	qspi_write32(priv->flags, &regs->ipcr,
753 		     (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0);
754 	while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
755 		;
756 
757 	if (priv->cur_seqid == QSPI_CMD_SE) {
758 		qspi_write32(priv->flags, &regs->ipcr,
759 			     (SEQID_SE << QSPI_IPCR_SEQID_SHIFT) | 0);
760 	} else if (priv->cur_seqid == QSPI_CMD_BE_4K) {
761 		qspi_write32(priv->flags, &regs->ipcr,
762 			     (SEQID_BE_4K << QSPI_IPCR_SEQID_SHIFT) | 0);
763 	}
764 	while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
765 		;
766 
767 	qspi_write32(priv->flags, &regs->mcr, mcr_reg);
768 }
769 
qspi_xfer(struct fsl_qspi_priv * priv,unsigned int bitlen,const void * dout,void * din,unsigned long flags)770 int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int bitlen,
771 		const void *dout, void *din, unsigned long flags)
772 {
773 	u32 bytes = DIV_ROUND_UP(bitlen, 8);
774 	static u32 wr_sfaddr;
775 	u32 txbuf;
776 
777 	WATCHDOG_RESET();
778 
779 	if (dout) {
780 		if (flags & SPI_XFER_BEGIN) {
781 			priv->cur_seqid = *(u8 *)dout;
782 			memcpy(&txbuf, dout, 4);
783 		}
784 
785 		if (flags == SPI_XFER_END) {
786 			priv->sf_addr = wr_sfaddr;
787 			qspi_op_write(priv, (u8 *)dout, bytes);
788 			return 0;
789 		}
790 
791 		if (priv->cur_seqid == QSPI_CMD_FAST_READ ||
792 		    priv->cur_seqid == QSPI_CMD_RDAR) {
793 			priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
794 		} else if ((priv->cur_seqid == QSPI_CMD_SE) ||
795 			   (priv->cur_seqid == QSPI_CMD_BE_4K)) {
796 			priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
797 			qspi_op_erase(priv);
798 		} else if (priv->cur_seqid == QSPI_CMD_PP ||
799 			   priv->cur_seqid == QSPI_CMD_WRAR) {
800 			wr_sfaddr = swab32(txbuf) & OFFSET_BITS_MASK;
801 		} else if ((priv->cur_seqid == QSPI_CMD_BRWR) ||
802 			 (priv->cur_seqid == QSPI_CMD_WREAR)) {
803 #ifdef CONFIG_SPI_FLASH_BAR
804 			wr_sfaddr = 0;
805 #endif
806 		}
807 	}
808 
809 	if (din) {
810 		if (priv->cur_seqid == QSPI_CMD_FAST_READ) {
811 #ifdef CONFIG_SYS_FSL_QSPI_AHB
812 			qspi_ahb_read(priv, din, bytes);
813 #else
814 			qspi_op_read(priv, din, bytes);
815 #endif
816 		} else if (priv->cur_seqid == QSPI_CMD_RDAR) {
817 			qspi_op_read(priv, din, bytes);
818 		} else if (priv->cur_seqid == QSPI_CMD_RDID)
819 			qspi_op_rdid(priv, din, bytes);
820 		else if (priv->cur_seqid == QSPI_CMD_RDSR)
821 			qspi_op_rdsr(priv, din, bytes);
822 #ifdef CONFIG_SPI_FLASH_BAR
823 		else if ((priv->cur_seqid == QSPI_CMD_BRRD) ||
824 			 (priv->cur_seqid == QSPI_CMD_RDEAR)) {
825 			priv->sf_addr = 0;
826 			qspi_op_rdbank(priv, din, bytes);
827 		}
828 #endif
829 	}
830 
831 #ifdef CONFIG_SYS_FSL_QSPI_AHB
832 	if ((priv->cur_seqid == QSPI_CMD_SE) ||
833 	    (priv->cur_seqid == QSPI_CMD_PP) ||
834 	    (priv->cur_seqid == QSPI_CMD_BE_4K) ||
835 	    (priv->cur_seqid == QSPI_CMD_WREAR) ||
836 	    (priv->cur_seqid == QSPI_CMD_BRWR))
837 		qspi_ahb_invalid(priv);
838 #endif
839 
840 	return 0;
841 }
842 
qspi_module_disable(struct fsl_qspi_priv * priv,u8 disable)843 void qspi_module_disable(struct fsl_qspi_priv *priv, u8 disable)
844 {
845 	u32 mcr_val;
846 
847 	mcr_val = qspi_read32(priv->flags, &priv->regs->mcr);
848 	if (disable)
849 		mcr_val |= QSPI_MCR_MDIS_MASK;
850 	else
851 		mcr_val &= ~QSPI_MCR_MDIS_MASK;
852 	qspi_write32(priv->flags, &priv->regs->mcr, mcr_val);
853 }
854 
qspi_cfg_smpr(struct fsl_qspi_priv * priv,u32 clear_bits,u32 set_bits)855 void qspi_cfg_smpr(struct fsl_qspi_priv *priv, u32 clear_bits, u32 set_bits)
856 {
857 	u32 smpr_val;
858 
859 	smpr_val = qspi_read32(priv->flags, &priv->regs->smpr);
860 	smpr_val &= ~clear_bits;
861 	smpr_val |= set_bits;
862 	qspi_write32(priv->flags, &priv->regs->smpr, smpr_val);
863 }
864 
fsl_qspi_child_pre_probe(struct udevice * dev)865 static int fsl_qspi_child_pre_probe(struct udevice *dev)
866 {
867 	struct spi_slave *slave = dev_get_parent_priv(dev);
868 
869 	slave->max_write_size = TX_BUFFER_SIZE;
870 
871 	return 0;
872 }
873 
fsl_qspi_probe(struct udevice * bus)874 static int fsl_qspi_probe(struct udevice *bus)
875 {
876 	u32 mcr_val;
877 	u32 amba_size_per_chip;
878 	struct fsl_qspi_platdata *plat = dev_get_platdata(bus);
879 	struct fsl_qspi_priv *priv = dev_get_priv(bus);
880 	struct dm_spi_bus *dm_spi_bus;
881 	int i, ret;
882 
883 	dm_spi_bus = bus->uclass_priv;
884 
885 	dm_spi_bus->max_hz = plat->speed_hz;
886 
887 	priv->regs = (struct fsl_qspi_regs *)(uintptr_t)plat->reg_base;
888 	priv->flags = plat->flags;
889 
890 	priv->speed_hz = plat->speed_hz;
891 	/*
892 	 * QSPI SFADR width is 32bits, the max dest addr is 4GB-1.
893 	 * AMBA memory zone should be located on the 0~4GB space
894 	 * even on a 64bits cpu.
895 	 */
896 	priv->amba_base[0] = (u32)plat->amba_base;
897 	priv->amba_total_size = (u32)plat->amba_total_size;
898 	priv->flash_num = plat->flash_num;
899 	priv->num_chipselect = plat->num_chipselect;
900 
901 	/* make sure controller is not busy anywhere */
902 	ret = is_controller_busy(priv);
903 
904 	if (ret) {
905 		debug("ERROR : The controller is busy\n");
906 		return ret;
907 	}
908 
909 	mcr_val = qspi_read32(priv->flags, &priv->regs->mcr);
910 
911 	/* Set endianness to LE for i.mx */
912 	if (IS_ENABLED(CONFIG_MX6) || IS_ENABLED(CONFIG_MX7))
913 		mcr_val = QSPI_MCR_END_CFD_LE;
914 
915 	qspi_write32(priv->flags, &priv->regs->mcr,
916 		     QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK |
917 		     (mcr_val & QSPI_MCR_END_CFD_MASK));
918 
919 	qspi_cfg_smpr(priv, ~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK |
920 		QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK), 0);
921 
922 	/*
923 	 * Assign AMBA memory zone for every chipselect
924 	 * QuadSPI has two channels, every channel has two chipselects.
925 	 * If the property 'num-cs' in dts is 2, the AMBA memory will be divided
926 	 * into two parts and assign to every channel. This indicate that every
927 	 * channel only has one valid chipselect.
928 	 * If the property 'num-cs' in dts is 4, the AMBA memory will be divided
929 	 * into four parts and assign to every chipselect.
930 	 * Every channel will has two valid chipselects.
931 	 */
932 	amba_size_per_chip = priv->amba_total_size >>
933 			     (priv->num_chipselect >> 1);
934 	for (i = 1 ; i < priv->num_chipselect ; i++)
935 		priv->amba_base[i] =
936 			amba_size_per_chip + priv->amba_base[i - 1];
937 
938 	/*
939 	 * Any read access to non-implemented addresses will provide
940 	 * undefined results.
941 	 *
942 	 * In case single die flash devices, TOP_ADDR_MEMA2 and
943 	 * TOP_ADDR_MEMB2 should be initialized/programmed to
944 	 * TOP_ADDR_MEMA1 and TOP_ADDR_MEMB1 respectively - in effect,
945 	 * setting the size of these devices to 0.  This would ensure
946 	 * that the complete memory map is assigned to only one flash device.
947 	 */
948 	qspi_write32(priv->flags, &priv->regs->sfa1ad,
949 		     priv->amba_base[0] + amba_size_per_chip);
950 	switch (priv->num_chipselect) {
951 	case 1:
952 		break;
953 	case 2:
954 		qspi_write32(priv->flags, &priv->regs->sfa2ad,
955 			     priv->amba_base[1]);
956 		qspi_write32(priv->flags, &priv->regs->sfb1ad,
957 			     priv->amba_base[1] + amba_size_per_chip);
958 		qspi_write32(priv->flags, &priv->regs->sfb2ad,
959 			     priv->amba_base[1] + amba_size_per_chip);
960 		break;
961 	case 4:
962 		qspi_write32(priv->flags, &priv->regs->sfa2ad,
963 			     priv->amba_base[2]);
964 		qspi_write32(priv->flags, &priv->regs->sfb1ad,
965 			     priv->amba_base[3]);
966 		qspi_write32(priv->flags, &priv->regs->sfb2ad,
967 			     priv->amba_base[3] + amba_size_per_chip);
968 		break;
969 	default:
970 		debug("Error: Unsupported chipselect number %u!\n",
971 		      priv->num_chipselect);
972 		qspi_module_disable(priv, 1);
973 		return -EINVAL;
974 	}
975 
976 	qspi_set_lut(priv);
977 
978 #ifdef CONFIG_SYS_FSL_QSPI_AHB
979 	qspi_init_ahb_read(priv);
980 #endif
981 
982 	qspi_module_disable(priv, 0);
983 
984 	return 0;
985 }
986 
fsl_qspi_ofdata_to_platdata(struct udevice * bus)987 static int fsl_qspi_ofdata_to_platdata(struct udevice *bus)
988 {
989 	struct fdt_resource res_regs, res_mem;
990 	struct fsl_qspi_platdata *plat = bus->platdata;
991 	const void *blob = gd->fdt_blob;
992 	int node = dev_of_offset(bus);
993 	int ret, flash_num = 0, subnode;
994 
995 	if (fdtdec_get_bool(blob, node, "big-endian"))
996 		plat->flags |= QSPI_FLAG_REGMAP_ENDIAN_BIG;
997 
998 	ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
999 				     "QuadSPI", &res_regs);
1000 	if (ret) {
1001 		debug("Error: can't get regs base addresses(ret = %d)!\n", ret);
1002 		return -ENOMEM;
1003 	}
1004 	ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
1005 				     "QuadSPI-memory", &res_mem);
1006 	if (ret) {
1007 		debug("Error: can't get AMBA base addresses(ret = %d)!\n", ret);
1008 		return -ENOMEM;
1009 	}
1010 
1011 	/* Count flash numbers */
1012 	fdt_for_each_subnode(subnode, blob, node)
1013 		++flash_num;
1014 
1015 	if (flash_num == 0) {
1016 		debug("Error: Missing flashes!\n");
1017 		return -ENODEV;
1018 	}
1019 
1020 	plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
1021 					FSL_QSPI_DEFAULT_SCK_FREQ);
1022 	plat->num_chipselect = fdtdec_get_int(blob, node, "num-cs",
1023 					      FSL_QSPI_MAX_CHIPSELECT_NUM);
1024 
1025 	plat->reg_base = res_regs.start;
1026 	plat->amba_base = res_mem.start;
1027 	plat->amba_total_size = res_mem.end - res_mem.start + 1;
1028 	plat->flash_num = flash_num;
1029 
1030 	debug("%s: regs=<0x%llx> <0x%llx, 0x%llx>, max-frequency=%d, endianess=%s\n",
1031 	      __func__,
1032 	      (u64)plat->reg_base,
1033 	      (u64)plat->amba_base,
1034 	      (u64)plat->amba_total_size,
1035 	      plat->speed_hz,
1036 	      plat->flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le"
1037 	      );
1038 
1039 	return 0;
1040 }
1041 
fsl_qspi_xfer(struct udevice * dev,unsigned int bitlen,const void * dout,void * din,unsigned long flags)1042 static int fsl_qspi_xfer(struct udevice *dev, unsigned int bitlen,
1043 		const void *dout, void *din, unsigned long flags)
1044 {
1045 	struct fsl_qspi_priv *priv;
1046 	struct udevice *bus;
1047 
1048 	bus = dev->parent;
1049 	priv = dev_get_priv(bus);
1050 
1051 	return qspi_xfer(priv, bitlen, dout, din, flags);
1052 }
1053 
fsl_qspi_claim_bus(struct udevice * dev)1054 static int fsl_qspi_claim_bus(struct udevice *dev)
1055 {
1056 	struct fsl_qspi_priv *priv;
1057 	struct udevice *bus;
1058 	struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
1059 	int ret;
1060 
1061 	bus = dev->parent;
1062 	priv = dev_get_priv(bus);
1063 
1064 	/* make sure controller is not busy anywhere */
1065 	ret = is_controller_busy(priv);
1066 
1067 	if (ret) {
1068 		debug("ERROR : The controller is busy\n");
1069 		return ret;
1070 	}
1071 
1072 	priv->cur_amba_base = priv->amba_base[slave_plat->cs];
1073 
1074 	qspi_module_disable(priv, 0);
1075 
1076 	return 0;
1077 }
1078 
fsl_qspi_release_bus(struct udevice * dev)1079 static int fsl_qspi_release_bus(struct udevice *dev)
1080 {
1081 	struct fsl_qspi_priv *priv;
1082 	struct udevice *bus;
1083 
1084 	bus = dev->parent;
1085 	priv = dev_get_priv(bus);
1086 
1087 	qspi_module_disable(priv, 1);
1088 
1089 	return 0;
1090 }
1091 
fsl_qspi_set_speed(struct udevice * bus,uint speed)1092 static int fsl_qspi_set_speed(struct udevice *bus, uint speed)
1093 {
1094 	/* Nothing to do */
1095 	return 0;
1096 }
1097 
fsl_qspi_set_mode(struct udevice * bus,uint mode)1098 static int fsl_qspi_set_mode(struct udevice *bus, uint mode)
1099 {
1100 	/* Nothing to do */
1101 	return 0;
1102 }
1103 
1104 static const struct dm_spi_ops fsl_qspi_ops = {
1105 	.claim_bus	= fsl_qspi_claim_bus,
1106 	.release_bus	= fsl_qspi_release_bus,
1107 	.xfer		= fsl_qspi_xfer,
1108 	.set_speed	= fsl_qspi_set_speed,
1109 	.set_mode	= fsl_qspi_set_mode,
1110 };
1111 
1112 static const struct udevice_id fsl_qspi_ids[] = {
1113 	{ .compatible = "fsl,vf610-qspi" },
1114 	{ .compatible = "fsl,imx6sx-qspi" },
1115 	{ .compatible = "fsl,imx6ul-qspi" },
1116 	{ .compatible = "fsl,imx7d-qspi" },
1117 	{ }
1118 };
1119 
1120 U_BOOT_DRIVER(fsl_qspi) = {
1121 	.name	= "fsl_qspi",
1122 	.id	= UCLASS_SPI,
1123 	.of_match = fsl_qspi_ids,
1124 	.ops	= &fsl_qspi_ops,
1125 	.ofdata_to_platdata = fsl_qspi_ofdata_to_platdata,
1126 	.platdata_auto_alloc_size = sizeof(struct fsl_qspi_platdata),
1127 	.priv_auto_alloc_size = sizeof(struct fsl_qspi_priv),
1128 	.probe	= fsl_qspi_probe,
1129 	.child_pre_probe = fsl_qspi_child_pre_probe,
1130 };
1131