1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2012 Samsung Electronics
4 * R. Chandrasekar <rcsekar@samsung.com>
5 */
6 #include <common.h>
7 #include <audio_codec.h>
8 #include <dm.h>
9 #include <div64.h>
10 #include <fdtdec.h>
11 #include <i2c.h>
12 #include <i2s.h>
13 #include <sound.h>
14 #include <asm/gpio.h>
15 #include <asm/io.h>
16 #include <asm/arch/clk.h>
17 #include <asm/arch/cpu.h>
18 #include <asm/arch/sound.h>
19 #include "wm8994.h"
20 #include "wm8994_registers.h"
21
22 /* defines for wm8994 system clock selection */
23 #define SEL_MCLK1 0x00
24 #define SEL_MCLK2 0x08
25 #define SEL_FLL1 0x10
26 #define SEL_FLL2 0x18
27
28 /* fll config to configure fll */
29 struct wm8994_fll_config {
30 int src; /* Source */
31 int in; /* Input frequency in Hz */
32 int out; /* output frequency in Hz */
33 };
34
35 /* codec private data */
36 struct wm8994_priv {
37 enum wm8994_type type; /* codec type of wolfson */
38 int revision; /* Revision */
39 int sysclk[WM8994_MAX_AIF]; /* System clock frequency in Hz */
40 int mclk[WM8994_MAX_AIF]; /* master clock frequency in Hz */
41 int aifclk[WM8994_MAX_AIF]; /* audio interface clock in Hz */
42 struct wm8994_fll_config fll[2]; /* fll config to configure fll */
43 struct udevice *dev;
44 };
45
46 /* wm 8994 supported sampling rate values */
47 static unsigned int src_rate[] = {
48 8000, 11025, 12000, 16000, 22050, 24000,
49 32000, 44100, 48000, 88200, 96000
50 };
51
52 /* op clock divisions */
53 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
54
55 /* lr clock frame size ratio */
56 static int fs_ratios[] = {
57 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
58 };
59
60 /* bit clock divisors */
61 static int bclk_divs[] = {
62 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
63 640, 880, 960, 1280, 1760, 1920
64 };
65
66 /*
67 * Writes value to a device register through i2c
68 *
69 * @param priv Private data for driver
70 * @param reg reg number to be write
71 * @param data data to be writen to the above registor
72 *
73 * @return int value 1 for change, 0 for no change or negative error code.
74 */
wm8994_i2c_write(struct wm8994_priv * priv,unsigned int reg,unsigned short data)75 static int wm8994_i2c_write(struct wm8994_priv *priv, unsigned int reg,
76 unsigned short data)
77 {
78 unsigned char val[2];
79
80 val[0] = (unsigned char)((data >> 8) & 0xff);
81 val[1] = (unsigned char)(data & 0xff);
82 debug("Write Addr : 0x%04X, Data : 0x%04X\n", reg, data);
83
84 return dm_i2c_write(priv->dev, reg, val, 2);
85 }
86
87 /*
88 * Read a value from a device register through i2c
89 *
90 * @param priv Private data for driver
91 * @param reg reg number to be read
92 * @param data address of read data to be stored
93 *
94 * @return int value 0 for success, -1 in case of error.
95 */
wm8994_i2c_read(struct wm8994_priv * priv,unsigned int reg,unsigned short * data)96 static unsigned int wm8994_i2c_read(struct wm8994_priv *priv, unsigned int reg,
97 unsigned short *data)
98 {
99 unsigned char val[2];
100 int ret;
101
102 ret = dm_i2c_read(priv->dev, reg, val, 1);
103 if (ret != 0) {
104 debug("%s: Error while reading register %#04x\n",
105 __func__, reg);
106 return -1;
107 }
108
109 *data = val[0];
110 *data <<= 8;
111 *data |= val[1];
112
113 return 0;
114 }
115
116 /*
117 * update device register bits through i2c
118 *
119 * @param priv Private data for driver
120 * @param reg codec register
121 * @param mask register mask
122 * @param value new value
123 *
124 * @return int value 1 if change in the register value,
125 * 0 for no change or negative error code.
126 */
wm8994_bic_or(struct wm8994_priv * priv,unsigned int reg,unsigned short mask,unsigned short value)127 static int wm8994_bic_or(struct wm8994_priv *priv, unsigned int reg,
128 unsigned short mask, unsigned short value)
129 {
130 int change , ret = 0;
131 unsigned short old, new;
132
133 if (wm8994_i2c_read(priv, reg, &old) != 0)
134 return -1;
135 new = (old & ~mask) | (value & mask);
136 change = (old != new) ? 1 : 0;
137 if (change)
138 ret = wm8994_i2c_write(priv, reg, new);
139 if (ret < 0)
140 return ret;
141
142 return change;
143 }
144
145 /*
146 * Sets i2s set format
147 *
148 * @param priv wm8994 information
149 * @param aif_id Interface ID
150 * @param fmt i2S format
151 *
152 * @return -1 for error and 0 Success.
153 */
wm8994_set_fmt(struct wm8994_priv * priv,int aif_id,uint fmt)154 static int wm8994_set_fmt(struct wm8994_priv *priv, int aif_id, uint fmt)
155 {
156 int ms_reg;
157 int aif_reg;
158 int ms = 0;
159 int aif = 0;
160 int aif_clk = 0;
161 int error = 0;
162
163 switch (aif_id) {
164 case 1:
165 ms_reg = WM8994_AIF1_MASTER_SLAVE;
166 aif_reg = WM8994_AIF1_CONTROL_1;
167 aif_clk = WM8994_AIF1_CLOCKING_1;
168 break;
169 case 2:
170 ms_reg = WM8994_AIF2_MASTER_SLAVE;
171 aif_reg = WM8994_AIF2_CONTROL_1;
172 aif_clk = WM8994_AIF2_CLOCKING_1;
173 break;
174 default:
175 debug("%s: Invalid audio interface selection\n", __func__);
176 return -1;
177 }
178
179 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
180 case SND_SOC_DAIFMT_CBS_CFS:
181 break;
182 case SND_SOC_DAIFMT_CBM_CFM:
183 ms = WM8994_AIF1_MSTR;
184 break;
185 default:
186 debug("%s: Invalid i2s master selection\n", __func__);
187 return -1;
188 }
189
190 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
191 case SND_SOC_DAIFMT_DSP_B:
192 aif |= WM8994_AIF1_LRCLK_INV;
193 case SND_SOC_DAIFMT_DSP_A:
194 aif |= 0x18;
195 break;
196 case SND_SOC_DAIFMT_I2S:
197 aif |= 0x10;
198 break;
199 case SND_SOC_DAIFMT_RIGHT_J:
200 break;
201 case SND_SOC_DAIFMT_LEFT_J:
202 aif |= 0x8;
203 break;
204 default:
205 debug("%s: Invalid i2s format selection\n", __func__);
206 return -1;
207 }
208
209 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
210 case SND_SOC_DAIFMT_DSP_A:
211 case SND_SOC_DAIFMT_DSP_B:
212 /* frame inversion not valid for DSP modes */
213 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
214 case SND_SOC_DAIFMT_NB_NF:
215 break;
216 case SND_SOC_DAIFMT_IB_NF:
217 aif |= WM8994_AIF1_BCLK_INV;
218 break;
219 default:
220 debug("%s: Invalid i2s frame inverse selection\n",
221 __func__);
222 return -1;
223 }
224 break;
225
226 case SND_SOC_DAIFMT_I2S:
227 case SND_SOC_DAIFMT_RIGHT_J:
228 case SND_SOC_DAIFMT_LEFT_J:
229 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
230 case SND_SOC_DAIFMT_NB_NF:
231 break;
232 case SND_SOC_DAIFMT_IB_IF:
233 aif |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
234 break;
235 case SND_SOC_DAIFMT_IB_NF:
236 aif |= WM8994_AIF1_BCLK_INV;
237 break;
238 case SND_SOC_DAIFMT_NB_IF:
239 aif |= WM8994_AIF1_LRCLK_INV;
240 break;
241 default:
242 debug("%s: Invalid i2s clock polarity selection\n",
243 __func__);
244 return -1;
245 }
246 break;
247 default:
248 debug("%s: Invalid i2s format selection\n", __func__);
249 return -1;
250 }
251
252 error = wm8994_bic_or(priv, aif_reg, WM8994_AIF1_BCLK_INV |
253 WM8994_AIF1_LRCLK_INV_MASK |
254 WM8994_AIF1_FMT_MASK, aif);
255
256 error |= wm8994_bic_or(priv, ms_reg, WM8994_AIF1_MSTR_MASK, ms);
257 error |= wm8994_bic_or(priv, aif_clk, WM8994_AIF1CLK_ENA_MASK,
258 WM8994_AIF1CLK_ENA);
259 if (error < 0) {
260 debug("%s: codec register access error\n", __func__);
261 return -1;
262 }
263
264 return 0;
265 }
266
267 /*
268 * Sets hw params FOR WM8994
269 *
270 * @param priv wm8994 information pointer
271 * @param aif_id Audio interface ID
272 * @param sampling_rate Sampling rate
273 * @param bits_per_sample Bits per sample
274 * @param Channels Channels in the given audio input
275 *
276 * @return -1 for error and 0 Success.
277 */
wm8994_hw_params(struct wm8994_priv * priv,int aif_id,uint sampling_rate,uint bits_per_sample,uint channels)278 static int wm8994_hw_params(struct wm8994_priv *priv, int aif_id,
279 uint sampling_rate, uint bits_per_sample,
280 uint channels)
281 {
282 int aif1_reg;
283 int aif2_reg;
284 int bclk_reg;
285 int bclk = 0;
286 int rate_reg;
287 int aif1 = 0;
288 int aif2 = 0;
289 int rate_val = 0;
290 int id = aif_id - 1;
291 int i, cur_val, best_val, bclk_rate, best;
292 unsigned short reg_data;
293 int ret = 0;
294
295 switch (aif_id) {
296 case 1:
297 aif1_reg = WM8994_AIF1_CONTROL_1;
298 aif2_reg = WM8994_AIF1_CONTROL_2;
299 bclk_reg = WM8994_AIF1_BCLK;
300 rate_reg = WM8994_AIF1_RATE;
301 break;
302 case 2:
303 aif1_reg = WM8994_AIF2_CONTROL_1;
304 aif2_reg = WM8994_AIF2_CONTROL_2;
305 bclk_reg = WM8994_AIF2_BCLK;
306 rate_reg = WM8994_AIF2_RATE;
307 break;
308 default:
309 return -1;
310 }
311
312 bclk_rate = sampling_rate * 32;
313 switch (bits_per_sample) {
314 case 16:
315 bclk_rate *= 16;
316 break;
317 case 20:
318 bclk_rate *= 20;
319 aif1 |= 0x20;
320 break;
321 case 24:
322 bclk_rate *= 24;
323 aif1 |= 0x40;
324 break;
325 case 32:
326 bclk_rate *= 32;
327 aif1 |= 0x60;
328 break;
329 default:
330 return -1;
331 }
332
333 /* Try to find an appropriate sample rate; look for an exact match. */
334 for (i = 0; i < ARRAY_SIZE(src_rate); i++)
335 if (src_rate[i] == sampling_rate)
336 break;
337
338 if (i == ARRAY_SIZE(src_rate)) {
339 debug("%s: Could not get the best matching samplingrate\n",
340 __func__);
341 return -1;
342 }
343
344 rate_val |= i << WM8994_AIF1_SR_SHIFT;
345
346 /* AIFCLK/fs ratio; look for a close match in either direction */
347 best = 0;
348 best_val = abs((fs_ratios[0] * sampling_rate) - priv->aifclk[id]);
349
350 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
351 cur_val = abs(fs_ratios[i] * sampling_rate - priv->aifclk[id]);
352 if (cur_val >= best_val)
353 continue;
354 best = i;
355 best_val = cur_val;
356 }
357
358 rate_val |= best;
359
360 /*
361 * We may not get quite the right frequency if using
362 * approximate clocks so look for the closest match that is
363 * higher than the target (we need to ensure that there enough
364 * BCLKs to clock out the samples).
365 */
366 best = 0;
367 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
368 cur_val = (priv->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
369 if (cur_val < 0) /* BCLK table is sorted */
370 break;
371 best = i;
372 }
373
374 if (i == ARRAY_SIZE(bclk_divs)) {
375 debug("%s: Could not get the best matching bclk division\n",
376 __func__);
377 return -1;
378 }
379
380 bclk_rate = priv->aifclk[id] * 10 / bclk_divs[best];
381 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
382
383 if (wm8994_i2c_read(priv, aif1_reg, ®_data) != 0) {
384 debug("%s: AIF1 register read Failed\n", __func__);
385 return -1;
386 }
387
388 if ((channels == 1) && ((reg_data & 0x18) == 0x18))
389 aif2 |= WM8994_AIF1_MONO;
390
391 if (priv->aifclk[id] == 0) {
392 debug("%s:Audio interface clock not set\n", __func__);
393 return -1;
394 }
395
396 ret = wm8994_bic_or(priv, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
397 ret |= wm8994_bic_or(priv, aif2_reg, WM8994_AIF1_MONO, aif2);
398 ret |= wm8994_bic_or(priv, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK,
399 bclk);
400 ret |= wm8994_bic_or(priv, rate_reg, WM8994_AIF1_SR_MASK |
401 WM8994_AIF1CLK_RATE_MASK, rate_val);
402
403 debug("rate vale = %x , bclk val= %x\n", rate_val, bclk);
404
405 if (ret < 0) {
406 debug("%s: codec register access error\n", __func__);
407 return -1;
408 }
409
410 return 0;
411 }
412
413 /*
414 * Configures Audio interface Clock
415 *
416 * @param priv wm8994 information pointer
417 * @param aif Audio Interface ID
418 *
419 * @return -1 for error and 0 Success.
420 */
configure_aif_clock(struct wm8994_priv * priv,int aif)421 static int configure_aif_clock(struct wm8994_priv *priv, int aif)
422 {
423 int rate;
424 int reg1 = 0;
425 int offset;
426 int ret;
427
428 /* AIF(1/0) register adress offset calculated */
429 if (aif-1)
430 offset = 4;
431 else
432 offset = 0;
433
434 switch (priv->sysclk[aif - 1]) {
435 case WM8994_SYSCLK_MCLK1:
436 reg1 |= SEL_MCLK1;
437 rate = priv->mclk[0];
438 break;
439
440 case WM8994_SYSCLK_MCLK2:
441 reg1 |= SEL_MCLK2;
442 rate = priv->mclk[1];
443 break;
444
445 case WM8994_SYSCLK_FLL1:
446 reg1 |= SEL_FLL1;
447 rate = priv->fll[0].out;
448 break;
449
450 case WM8994_SYSCLK_FLL2:
451 reg1 |= SEL_FLL2;
452 rate = priv->fll[1].out;
453 break;
454
455 default:
456 debug("%s: Invalid input clock selection [%d]\n",
457 __func__, priv->sysclk[aif - 1]);
458 return -1;
459 }
460
461 /* if input clock frequenct is more than 135Mhz then divide */
462 if (rate >= WM8994_MAX_INPUT_CLK_FREQ) {
463 rate /= 2;
464 reg1 |= WM8994_AIF1CLK_DIV;
465 }
466
467 priv->aifclk[aif - 1] = rate;
468
469 ret = wm8994_bic_or(priv, WM8994_AIF1_CLOCKING_1 + offset,
470 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
471 reg1);
472
473 if (aif == WM8994_AIF1)
474 ret |= wm8994_bic_or(priv, WM8994_CLOCKING_1,
475 WM8994_AIF1DSPCLK_ENA_MASK | WM8994_SYSDSPCLK_ENA_MASK,
476 WM8994_AIF1DSPCLK_ENA | WM8994_SYSDSPCLK_ENA);
477 else if (aif == WM8994_AIF2)
478 ret |= wm8994_bic_or(priv, WM8994_CLOCKING_1,
479 WM8994_SYSCLK_SRC | WM8994_AIF2DSPCLK_ENA_MASK |
480 WM8994_SYSDSPCLK_ENA_MASK, WM8994_SYSCLK_SRC |
481 WM8994_AIF2DSPCLK_ENA | WM8994_SYSDSPCLK_ENA);
482
483 if (ret < 0) {
484 debug("%s: codec register access error\n", __func__);
485 return -1;
486 }
487
488 return 0;
489 }
490
491 /*
492 * Configures Audio interface for the given frequency
493 *
494 * @param priv wm8994 information
495 * @param aif_id Audio Interface
496 * @param clk_id Input Clock ID
497 * @param freq Sampling frequency in Hz
498 *
499 * @return -1 for error and 0 success.
500 */
wm8994_set_sysclk(struct wm8994_priv * priv,int aif_id,int clk_id,unsigned int freq)501 static int wm8994_set_sysclk(struct wm8994_priv *priv, int aif_id, int clk_id,
502 unsigned int freq)
503 {
504 int i;
505 int ret = 0;
506
507 priv->sysclk[aif_id - 1] = clk_id;
508
509 switch (clk_id) {
510 case WM8994_SYSCLK_MCLK1:
511 priv->mclk[0] = freq;
512 if (aif_id == 2) {
513 ret = wm8994_bic_or(priv, WM8994_AIF1_CLOCKING_2,
514 WM8994_AIF2DAC_DIV_MASK, 0);
515 }
516 break;
517
518 case WM8994_SYSCLK_MCLK2:
519 /* TODO: Set GPIO AF */
520 priv->mclk[1] = freq;
521 break;
522
523 case WM8994_SYSCLK_FLL1:
524 case WM8994_SYSCLK_FLL2:
525 break;
526
527 case WM8994_SYSCLK_OPCLK:
528 /*
529 * Special case - a division (times 10) is given and
530 * no effect on main clocking.
531 */
532 if (freq) {
533 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
534 if (opclk_divs[i] == freq)
535 break;
536 if (i == ARRAY_SIZE(opclk_divs)) {
537 debug("%s frequency divisor not found\n",
538 __func__);
539 return -1;
540 }
541 ret = wm8994_bic_or(priv, WM8994_CLOCKING_2,
542 WM8994_OPCLK_DIV_MASK, i);
543 ret |= wm8994_bic_or(priv, WM8994_POWER_MANAGEMENT_2,
544 WM8994_OPCLK_ENA,
545 WM8994_OPCLK_ENA);
546 } else {
547 ret |= wm8994_bic_or(priv, WM8994_POWER_MANAGEMENT_2,
548 WM8994_OPCLK_ENA, 0);
549 }
550
551 default:
552 debug("%s Invalid input clock selection [%d]\n",
553 __func__, clk_id);
554 return -1;
555 }
556
557 ret |= configure_aif_clock(priv, aif_id);
558
559 if (ret < 0) {
560 debug("%s: codec register access error\n", __func__);
561 return -1;
562 }
563
564 return 0;
565 }
566
567 /*
568 * Initializes Volume for AIF2 to HP path
569 *
570 * @param priv wm8994 information
571 * @returns -1 for error and 0 Success.
572 *
573 */
wm8994_init_volume_aif2_dac1(struct wm8994_priv * priv)574 static int wm8994_init_volume_aif2_dac1(struct wm8994_priv *priv)
575 {
576 int ret;
577
578 /* Unmute AIF2DAC */
579 ret = wm8994_bic_or(priv, WM8994_AIF2_DAC_FILTERS_1,
580 WM8994_AIF2DAC_MUTE_MASK, 0);
581
582
583 ret |= wm8994_bic_or(priv, WM8994_AIF2_DAC_LEFT_VOLUME,
584 WM8994_AIF2DAC_VU_MASK | WM8994_AIF2DACL_VOL_MASK,
585 WM8994_AIF2DAC_VU | 0xff);
586
587 ret |= wm8994_bic_or(priv, WM8994_AIF2_DAC_RIGHT_VOLUME,
588 WM8994_AIF2DAC_VU_MASK | WM8994_AIF2DACR_VOL_MASK,
589 WM8994_AIF2DAC_VU | 0xff);
590
591
592 ret |= wm8994_bic_or(priv, WM8994_DAC1_LEFT_VOLUME,
593 WM8994_DAC1_VU_MASK | WM8994_DAC1L_VOL_MASK |
594 WM8994_DAC1L_MUTE_MASK, WM8994_DAC1_VU | 0xc0);
595
596 ret |= wm8994_bic_or(priv, WM8994_DAC1_RIGHT_VOLUME,
597 WM8994_DAC1_VU_MASK | WM8994_DAC1R_VOL_MASK |
598 WM8994_DAC1R_MUTE_MASK, WM8994_DAC1_VU | 0xc0);
599 /* Head Phone Volume */
600 ret |= wm8994_i2c_write(priv, WM8994_LEFT_OUTPUT_VOLUME, 0x12D);
601 ret |= wm8994_i2c_write(priv, WM8994_RIGHT_OUTPUT_VOLUME, 0x12D);
602
603 if (ret < 0) {
604 debug("%s: codec register access error\n", __func__);
605 return -1;
606 }
607
608 return 0;
609 }
610
611 /*
612 * Initializes Volume for AIF1 to HP path
613 *
614 * @param priv wm8994 information
615 * @returns -1 for error and 0 Success.
616 *
617 */
wm8994_init_volume_aif1_dac1(struct wm8994_priv * priv)618 static int wm8994_init_volume_aif1_dac1(struct wm8994_priv *priv)
619 {
620 int ret = 0;
621
622 /* Unmute AIF1DAC */
623 ret |= wm8994_i2c_write(priv, WM8994_AIF1_DAC_FILTERS_1, 0x0000);
624
625 ret |= wm8994_bic_or(priv, WM8994_DAC1_LEFT_VOLUME,
626 WM8994_DAC1_VU_MASK | WM8994_DAC1L_VOL_MASK |
627 WM8994_DAC1L_MUTE_MASK, WM8994_DAC1_VU | 0xc0);
628
629 ret |= wm8994_bic_or(priv, WM8994_DAC1_RIGHT_VOLUME,
630 WM8994_DAC1_VU_MASK | WM8994_DAC1R_VOL_MASK |
631 WM8994_DAC1R_MUTE_MASK, WM8994_DAC1_VU | 0xc0);
632 /* Head Phone Volume */
633 ret |= wm8994_i2c_write(priv, WM8994_LEFT_OUTPUT_VOLUME, 0x12D);
634 ret |= wm8994_i2c_write(priv, WM8994_RIGHT_OUTPUT_VOLUME, 0x12D);
635
636 if (ret < 0) {
637 debug("%s: codec register access error\n", __func__);
638 return -1;
639 }
640
641 return 0;
642 }
643
644 /*
645 * Intialise wm8994 codec device
646 *
647 * @param priv wm8994 information
648 *
649 * @returns -1 for error and 0 Success.
650 */
wm8994_device_init(struct wm8994_priv * priv)651 static int wm8994_device_init(struct wm8994_priv *priv)
652 {
653 const char *devname;
654 unsigned short reg_data;
655 int ret;
656
657 wm8994_i2c_write(priv, WM8994_SOFTWARE_RESET, WM8994_SW_RESET);
658
659 ret = wm8994_i2c_read(priv, WM8994_SOFTWARE_RESET, ®_data);
660 if (ret < 0) {
661 debug("Failed to read ID register\n");
662 return ret;
663 }
664
665 if (reg_data == WM8994_ID) {
666 devname = "WM8994";
667 debug("Device registered as type %d\n", priv->type);
668 priv->type = WM8994;
669 } else {
670 debug("Device is not a WM8994, ID is %x\n", ret);
671 return -ENXIO;
672 }
673
674 ret = wm8994_i2c_read(priv, WM8994_CHIP_REVISION, ®_data);
675 if (ret < 0) {
676 debug("Failed to read revision register: %d\n", ret);
677 return ret;
678 }
679 priv->revision = reg_data;
680 debug("%s revision %c\n", devname, 'A' + priv->revision);
681
682 return 0;
683 }
684
wm8994_setup_interface(struct wm8994_priv * priv,enum en_audio_interface aif_id)685 static int wm8994_setup_interface(struct wm8994_priv *priv,
686 enum en_audio_interface aif_id)
687 {
688 int ret;
689
690 /* VMID Selection */
691 ret = wm8994_bic_or(priv, WM8994_POWER_MANAGEMENT_1,
692 WM8994_VMID_SEL_MASK | WM8994_BIAS_ENA_MASK, 0x3);
693
694 /* Charge Pump Enable */
695 ret |= wm8994_bic_or(priv, WM8994_CHARGE_PUMP_1, WM8994_CP_ENA_MASK,
696 WM8994_CP_ENA);
697
698 /* Head Phone Power Enable */
699 ret |= wm8994_bic_or(priv, WM8994_POWER_MANAGEMENT_1,
700 WM8994_HPOUT1L_ENA_MASK, WM8994_HPOUT1L_ENA);
701
702 ret |= wm8994_bic_or(priv, WM8994_POWER_MANAGEMENT_1,
703 WM8994_HPOUT1R_ENA_MASK, WM8994_HPOUT1R_ENA);
704
705 if (aif_id == WM8994_AIF1) {
706 ret |= wm8994_i2c_write(priv, WM8994_POWER_MANAGEMENT_2,
707 WM8994_TSHUT_ENA | WM8994_MIXINL_ENA |
708 WM8994_MIXINR_ENA | WM8994_IN2L_ENA |
709 WM8994_IN2R_ENA);
710
711 ret |= wm8994_i2c_write(priv, WM8994_POWER_MANAGEMENT_4,
712 WM8994_ADCL_ENA | WM8994_ADCR_ENA |
713 WM8994_AIF1ADC1R_ENA |
714 WM8994_AIF1ADC1L_ENA);
715
716 /* Power enable for AIF1 and DAC1 */
717 ret |= wm8994_i2c_write(priv, WM8994_POWER_MANAGEMENT_5,
718 WM8994_AIF1DACL_ENA |
719 WM8994_AIF1DACR_ENA |
720 WM8994_DAC1L_ENA | WM8994_DAC1R_ENA);
721 } else if (aif_id == WM8994_AIF2) {
722 /* Power enable for AIF2 and DAC1 */
723 ret |= wm8994_bic_or(priv, WM8994_POWER_MANAGEMENT_5,
724 WM8994_AIF2DACL_ENA_MASK | WM8994_AIF2DACR_ENA_MASK |
725 WM8994_DAC1L_ENA_MASK | WM8994_DAC1R_ENA_MASK,
726 WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA |
727 WM8994_DAC1L_ENA | WM8994_DAC1R_ENA);
728 }
729 /* Head Phone Initialisation */
730 ret |= wm8994_bic_or(priv, WM8994_ANALOGUE_HP_1,
731 WM8994_HPOUT1L_DLY_MASK | WM8994_HPOUT1R_DLY_MASK,
732 WM8994_HPOUT1L_DLY | WM8994_HPOUT1R_DLY);
733
734 ret |= wm8994_bic_or(priv, WM8994_DC_SERVO_1,
735 WM8994_DCS_ENA_CHAN_0_MASK |
736 WM8994_DCS_ENA_CHAN_1_MASK , WM8994_DCS_ENA_CHAN_0 |
737 WM8994_DCS_ENA_CHAN_1);
738
739 ret |= wm8994_bic_or(priv, WM8994_ANALOGUE_HP_1,
740 WM8994_HPOUT1L_DLY_MASK |
741 WM8994_HPOUT1R_DLY_MASK | WM8994_HPOUT1L_OUTP_MASK |
742 WM8994_HPOUT1R_OUTP_MASK |
743 WM8994_HPOUT1L_RMV_SHORT_MASK |
744 WM8994_HPOUT1R_RMV_SHORT_MASK, WM8994_HPOUT1L_DLY |
745 WM8994_HPOUT1R_DLY | WM8994_HPOUT1L_OUTP |
746 WM8994_HPOUT1R_OUTP | WM8994_HPOUT1L_RMV_SHORT |
747 WM8994_HPOUT1R_RMV_SHORT);
748
749 /* MIXER Config DAC1 to HP */
750 ret |= wm8994_bic_or(priv, WM8994_OUTPUT_MIXER_1,
751 WM8994_DAC1L_TO_HPOUT1L_MASK,
752 WM8994_DAC1L_TO_HPOUT1L);
753
754 ret |= wm8994_bic_or(priv, WM8994_OUTPUT_MIXER_2,
755 WM8994_DAC1R_TO_HPOUT1R_MASK,
756 WM8994_DAC1R_TO_HPOUT1R);
757
758 if (aif_id == WM8994_AIF1) {
759 /* Routing AIF1 to DAC1 */
760 ret |= wm8994_i2c_write(priv, WM8994_DAC1_LEFT_MIXER_ROUTING,
761 WM8994_AIF1DAC1L_TO_DAC1L);
762
763 ret |= wm8994_i2c_write(priv, WM8994_DAC1_RIGHT_MIXER_ROUTING,
764 WM8994_AIF1DAC1R_TO_DAC1R);
765
766 /* GPIO Settings for AIF1 */
767 ret |= wm8994_i2c_write(priv, WM8994_GPIO_1,
768 WM8994_GPIO_DIR_OUTPUT |
769 WM8994_GPIO_FUNCTION_I2S_CLK |
770 WM8994_GPIO_INPUT_DEBOUNCE);
771
772 ret |= wm8994_init_volume_aif1_dac1(priv);
773 } else if (aif_id == WM8994_AIF2) {
774 /* Routing AIF2 to DAC1 */
775 ret |= wm8994_bic_or(priv, WM8994_DAC1_LEFT_MIXER_ROUTING,
776 WM8994_AIF2DACL_TO_DAC1L_MASK,
777 WM8994_AIF2DACL_TO_DAC1L);
778
779 ret |= wm8994_bic_or(priv, WM8994_DAC1_RIGHT_MIXER_ROUTING,
780 WM8994_AIF2DACR_TO_DAC1R_MASK,
781 WM8994_AIF2DACR_TO_DAC1R);
782
783 /* GPIO Settings for AIF2 */
784 /* B CLK */
785 ret |= wm8994_bic_or(priv, WM8994_GPIO_3, WM8994_GPIO_DIR_MASK |
786 WM8994_GPIO_FUNCTION_MASK,
787 WM8994_GPIO_DIR_OUTPUT);
788
789 /* LR CLK */
790 ret |= wm8994_bic_or(priv, WM8994_GPIO_4, WM8994_GPIO_DIR_MASK |
791 WM8994_GPIO_FUNCTION_MASK,
792 WM8994_GPIO_DIR_OUTPUT);
793
794 /* DATA */
795 ret |= wm8994_bic_or(priv, WM8994_GPIO_5, WM8994_GPIO_DIR_MASK |
796 WM8994_GPIO_FUNCTION_MASK,
797 WM8994_GPIO_DIR_OUTPUT);
798
799 ret |= wm8994_init_volume_aif2_dac1(priv);
800 }
801
802 if (ret < 0)
803 goto err;
804
805 debug("%s: Codec chip setup ok\n", __func__);
806 return 0;
807 err:
808 debug("%s: Codec chip setup error\n", __func__);
809 return -1;
810 }
811
_wm8994_init(struct wm8994_priv * priv,enum en_audio_interface aif_id,int sampling_rate,int mclk_freq,int bits_per_sample,unsigned int channels)812 static int _wm8994_init(struct wm8994_priv *priv,
813 enum en_audio_interface aif_id, int sampling_rate,
814 int mclk_freq, int bits_per_sample,
815 unsigned int channels)
816 {
817 int ret;
818
819 ret = wm8994_setup_interface(priv, aif_id);
820 if (ret < 0) {
821 debug("%s: wm8994 codec chip init failed\n", __func__);
822 return ret;
823 }
824
825 ret = wm8994_set_sysclk(priv, aif_id, WM8994_SYSCLK_MCLK1, mclk_freq);
826 if (ret < 0) {
827 debug("%s: wm8994 codec set sys clock failed\n", __func__);
828 return ret;
829 }
830
831 ret = wm8994_hw_params(priv, aif_id, sampling_rate, bits_per_sample,
832 channels);
833
834 if (ret == 0) {
835 ret = wm8994_set_fmt(priv, aif_id, SND_SOC_DAIFMT_I2S |
836 SND_SOC_DAIFMT_NB_NF |
837 SND_SOC_DAIFMT_CBS_CFS);
838 }
839
840 return ret;
841 }
842
wm8994_set_params(struct udevice * dev,int interface,int rate,int mclk_freq,int bits_per_sample,uint channels)843 static int wm8994_set_params(struct udevice *dev, int interface, int rate,
844 int mclk_freq, int bits_per_sample, uint channels)
845 {
846 struct wm8994_priv *priv = dev_get_priv(dev);
847
848 return _wm8994_init(priv, interface, rate, mclk_freq, bits_per_sample,
849 channels);
850 }
851
wm8994_probe(struct udevice * dev)852 static int wm8994_probe(struct udevice *dev)
853 {
854 struct wm8994_priv *priv = dev_get_priv(dev);
855
856 priv->dev = dev;
857 return wm8994_device_init(priv);
858 }
859
860 static const struct audio_codec_ops wm8994_ops = {
861 .set_params = wm8994_set_params,
862 };
863
864 static const struct udevice_id wm8994_ids[] = {
865 { .compatible = "wolfson,wm8994" },
866 { }
867 };
868
869 U_BOOT_DRIVER(wm8994) = {
870 .name = "wm8994",
871 .id = UCLASS_AUDIO_CODEC,
872 .of_match = wm8994_ids,
873 .probe = wm8994_probe,
874 .ops = &wm8994_ops,
875 .priv_auto_alloc_size = sizeof(struct wm8994_priv),
876 };
877