xref: /openbmc/linux/arch/sh/include/mach-se/mach/se7722.h (revision 6a0abce4)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __ASM_SH_SE7722_H
3 #define __ASM_SH_SE7722_H
4 
5 /*
6  * linux/include/asm-sh/se7722.h
7  *
8  * Copyright (C) 2007  Nobuhiro Iwamatsu
9  *
10  * Hitachi UL SolutionEngine 7722 Support.
11  */
12 #include <linux/sh_intc.h>
13 #include <asm/addrspace.h>
14 
15 /* Box specific addresses.  */
16 #define SE_AREA0_WIDTH	4		/* Area0: 32bit */
17 #define PA_ROM		0xa0000000	/* EPROM */
18 #define PA_ROM_SIZE	0x00200000	/* EPROM size 2M byte */
19 #define PA_FROM		0xa1000000	/* Flash-ROM */
20 #define PA_FROM_SIZE	0x01000000	/* Flash-ROM size 16M byte */
21 #define PA_EXT1		0xa4000000
22 #define PA_EXT1_SIZE	0x04000000
23 #define PA_SDRAM	0xaC000000	/* DDR-SDRAM(Area3) 64MB */
24 #define PA_SDRAM_SIZE	0x04000000
25 
26 #define PA_EXT4		0xb0000000
27 #define PA_EXT4_SIZE	0x04000000
28 
29 #define PA_PERIPHERAL	0xB0000000
30 
31 #define PA_PCIC         PA_PERIPHERAL		/* MR-SHPC-01 PCMCIA */
32 #define PA_MRSHPC       (PA_PERIPHERAL + 0x003fffe0)    /* MR-SHPC-01 PCMCIA controller */
33 #define PA_MRSHPC_MW1   (PA_PERIPHERAL + 0x00400000)    /* MR-SHPC-01 memory window base */
34 #define PA_MRSHPC_MW2   (PA_PERIPHERAL + 0x00500000)    /* MR-SHPC-01 attribute window base */
35 #define PA_MRSHPC_IO    (PA_PERIPHERAL + 0x00600000)    /* MR-SHPC-01 I/O window base */
36 #define MRSHPC_OPTION   (PA_MRSHPC + 6)
37 #define MRSHPC_CSR      (PA_MRSHPC + 8)
38 #define MRSHPC_ISR      (PA_MRSHPC + 10)
39 #define MRSHPC_ICR      (PA_MRSHPC + 12)
40 #define MRSHPC_CPWCR    (PA_MRSHPC + 14)
41 #define MRSHPC_MW0CR1   (PA_MRSHPC + 16)
42 #define MRSHPC_MW1CR1   (PA_MRSHPC + 18)
43 #define MRSHPC_IOWCR1   (PA_MRSHPC + 20)
44 #define MRSHPC_MW0CR2   (PA_MRSHPC + 22)
45 #define MRSHPC_MW1CR2   (PA_MRSHPC + 24)
46 #define MRSHPC_IOWCR2   (PA_MRSHPC + 26)
47 #define MRSHPC_CDCR     (PA_MRSHPC + 28)
48 #define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
49 
50 #define PA_LED		(PA_PERIPHERAL + 0x00800000)	/* 8bit LED */
51 #define PA_FPGA		(PA_PERIPHERAL + 0x01800000)	/* FPGA base address */
52 
53 #define PA_LAN		(PA_AREA6_IO + 0)		/* SMC LAN91C111 */
54 /* GPIO */
55 #define FPGA_IN         0xb1840000UL
56 #define FPGA_OUT        0xb1840004UL
57 
58 #define PORT_PECR       0xA4050108UL
59 #define PORT_PJCR       0xA4050110UL
60 #define PORT_PSELD      0xA4050154UL
61 #define PORT_PSELB      0xA4050150UL
62 
63 #define PORT_PSELC      0xA4050152UL
64 #define PORT_PKCR       0xA4050112UL
65 #define PORT_PHCR       0xA405010EUL
66 #define PORT_PLCR       0xA4050114UL
67 #define PORT_PMCR       0xA4050116UL
68 #define PORT_PRCR       0xA405011CUL
69 #define PORT_PXCR       0xA4050148UL
70 #define PORT_PSELA      0xA405014EUL
71 #define PORT_PYCR       0xA405014AUL
72 #define PORT_PZCR       0xA405014CUL
73 #define PORT_HIZCRA     0xA4050158UL
74 #define PORT_HIZCRC     0xA405015CUL
75 
76 /* IRQ */
77 #define IRQ0_IRQ        evt2irq(0x600)
78 #define IRQ1_IRQ        evt2irq(0x620)
79 
80 #define SE7722_FPGA_IRQ_USB	0 /* IRQ0 */
81 #define SE7722_FPGA_IRQ_SMC	1 /* IRQ0 */
82 #define SE7722_FPGA_IRQ_MRSHPC0	2 /* IRQ1 */
83 #define SE7722_FPGA_IRQ_MRSHPC1	3 /* IRQ1 */
84 #define SE7722_FPGA_IRQ_MRSHPC2	4 /* IRQ1 */
85 #define SE7722_FPGA_IRQ_MRSHPC3	5 /* IRQ1 */
86 #define SE7722_FPGA_IRQ_NR	6
87 
88 struct irq_domain;
89 
90 /* arch/sh/boards/se/7722/irq.c */
91 extern struct irq_domain *se7722_irq_domain;
92 
93 void init_se7722_IRQ(void);
94 
95 #define __IO_PREFIX		se7722
96 #include <asm/io_generic.h>
97 
98 #endif  /* __ASM_SH_SE7722_H */
99