1 /*
2 * Allwinner (sun4i and above) SD Host Controller emulation
3 *
4 * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
5 *
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu/log.h"
22 #include "qemu/module.h"
23 #include "qemu/units.h"
24 #include "qapi/error.h"
25 #include "system/blockdev.h"
26 #include "system/dma.h"
27 #include "hw/qdev-properties.h"
28 #include "hw/irq.h"
29 #include "hw/sd/allwinner-sdhost.h"
30 #include "migration/vmstate.h"
31 #include "trace.h"
32 #include "qom/object.h"
33
34 #define TYPE_AW_SDHOST_BUS "allwinner-sdhost-bus"
35 /* This is reusing the SDBus typedef from SD_BUS */
36 DECLARE_INSTANCE_CHECKER(SDBus, AW_SDHOST_BUS,
37 TYPE_AW_SDHOST_BUS)
38
39 /* SD Host register offsets */
40 enum {
41 REG_SD_GCTL = 0x00, /* Global Control */
42 REG_SD_CKCR = 0x04, /* Clock Control */
43 REG_SD_TMOR = 0x08, /* Timeout */
44 REG_SD_BWDR = 0x0C, /* Bus Width */
45 REG_SD_BKSR = 0x10, /* Block Size */
46 REG_SD_BYCR = 0x14, /* Byte Count */
47 REG_SD_CMDR = 0x18, /* Command */
48 REG_SD_CAGR = 0x1C, /* Command Argument */
49 REG_SD_RESP0 = 0x20, /* Response Zero */
50 REG_SD_RESP1 = 0x24, /* Response One */
51 REG_SD_RESP2 = 0x28, /* Response Two */
52 REG_SD_RESP3 = 0x2C, /* Response Three */
53 REG_SD_IMKR = 0x30, /* Interrupt Mask */
54 REG_SD_MISR = 0x34, /* Masked Interrupt Status */
55 REG_SD_RISR = 0x38, /* Raw Interrupt Status */
56 REG_SD_STAR = 0x3C, /* Status */
57 REG_SD_FWLR = 0x40, /* FIFO Water Level */
58 REG_SD_FUNS = 0x44, /* FIFO Function Select */
59 REG_SD_DBGC = 0x50, /* Debug Enable */
60 REG_SD_A12A = 0x58, /* Auto command 12 argument */
61 REG_SD_NTSR = 0x5C, /* SD NewTiming Set */
62 REG_SD_SDBG = 0x60, /* SD newTiming Set Debug */
63 REG_SD_HWRST = 0x78, /* Hardware Reset Register */
64 REG_SD_DMAC = 0x80, /* Internal DMA Controller Control */
65 REG_SD_DLBA = 0x84, /* Descriptor List Base Address */
66 REG_SD_IDST = 0x88, /* Internal DMA Controller Status */
67 REG_SD_IDIE = 0x8C, /* Internal DMA Controller IRQ Enable */
68 REG_SD_THLDC = 0x100, /* Card Threshold Control / FIFO (sun4i only)*/
69 REG_SD_DSBD = 0x10C, /* eMMC DDR Start Bit Detection Control */
70 REG_SD_RES_CRC = 0x110, /* Response CRC from card/eMMC */
71 REG_SD_DATA7_CRC = 0x114, /* CRC Data 7 from card/eMMC */
72 REG_SD_DATA6_CRC = 0x118, /* CRC Data 6 from card/eMMC */
73 REG_SD_DATA5_CRC = 0x11C, /* CRC Data 5 from card/eMMC */
74 REG_SD_DATA4_CRC = 0x120, /* CRC Data 4 from card/eMMC */
75 REG_SD_DATA3_CRC = 0x124, /* CRC Data 3 from card/eMMC */
76 REG_SD_DATA2_CRC = 0x128, /* CRC Data 2 from card/eMMC */
77 REG_SD_DATA1_CRC = 0x12C, /* CRC Data 1 from card/eMMC */
78 REG_SD_DATA0_CRC = 0x130, /* CRC Data 0 from card/eMMC */
79 REG_SD_CRC_STA = 0x134, /* CRC status from card/eMMC during write */
80 REG_SD_SAMP_DL = 0x144, /* Sample Delay Control (sun50i-a64) */
81 REG_SD_FIFO = 0x200, /* Read/Write FIFO */
82 };
83
84 /* SD Host register flags */
85 enum {
86 SD_GCTL_FIFO_AC_MOD = (1 << 31),
87 SD_GCTL_DDR_MOD_SEL = (1 << 10),
88 SD_GCTL_CD_DBC_ENB = (1 << 8),
89 SD_GCTL_DMA_ENB = (1 << 5),
90 SD_GCTL_INT_ENB = (1 << 4),
91 SD_GCTL_DMA_RST = (1 << 2),
92 SD_GCTL_FIFO_RST = (1 << 1),
93 SD_GCTL_SOFT_RST = (1 << 0),
94 };
95
96 enum {
97 SD_CMDR_LOAD = (1 << 31),
98 SD_CMDR_CLKCHANGE = (1 << 21),
99 SD_CMDR_WRITE = (1 << 10),
100 SD_CMDR_AUTOSTOP = (1 << 12),
101 SD_CMDR_DATA = (1 << 9),
102 SD_CMDR_RESPONSE_LONG = (1 << 7),
103 SD_CMDR_RESPONSE = (1 << 6),
104 SD_CMDR_CMDID_MASK = (0x3f),
105 };
106
107 enum {
108 SD_RISR_CARD_REMOVE = (1 << 31),
109 SD_RISR_CARD_INSERT = (1 << 30),
110 SD_RISR_SDIO_INTR = (1 << 16),
111 SD_RISR_AUTOCMD_DONE = (1 << 14),
112 SD_RISR_DATA_COMPLETE = (1 << 3),
113 SD_RISR_CMD_COMPLETE = (1 << 2),
114 SD_RISR_NO_RESPONSE = (1 << 1),
115 };
116
117 enum {
118 SD_STAR_FIFO_EMPTY = (1 << 2),
119 SD_STAR_CARD_PRESENT = (1 << 8),
120 SD_STAR_FIFO_LEVEL_1 = (1 << 17),
121 };
122
123 enum {
124 SD_IDST_INT_SUMMARY = (1 << 8),
125 SD_IDST_RECEIVE_IRQ = (1 << 1),
126 SD_IDST_TRANSMIT_IRQ = (1 << 0),
127 SD_IDST_IRQ_MASK = (1 << 1) | (1 << 0) | (1 << 8),
128 SD_IDST_WR_MASK = (0x3ff),
129 };
130
131 /* SD Host register reset values */
132 enum {
133 REG_SD_GCTL_RST = 0x00000300,
134 REG_SD_CKCR_RST = 0x0,
135 REG_SD_TMOR_RST = 0xFFFFFF40,
136 REG_SD_BWDR_RST = 0x0,
137 REG_SD_BKSR_RST = 0x00000200,
138 REG_SD_BYCR_RST = 0x00000200,
139 REG_SD_CMDR_RST = 0x0,
140 REG_SD_CAGR_RST = 0x0,
141 REG_SD_RESP_RST = 0x0,
142 REG_SD_IMKR_RST = 0x0,
143 REG_SD_MISR_RST = 0x0,
144 REG_SD_RISR_RST = 0x0,
145 REG_SD_STAR_RST = 0x00000100,
146 REG_SD_FWLR_RST = 0x000F0000,
147 REG_SD_FUNS_RST = 0x0,
148 REG_SD_DBGC_RST = 0x0,
149 REG_SD_A12A_RST = 0x0000FFFF,
150 REG_SD_NTSR_RST = 0x00000001,
151 REG_SD_SDBG_RST = 0x0,
152 REG_SD_HWRST_RST = 0x00000001,
153 REG_SD_DMAC_RST = 0x0,
154 REG_SD_DLBA_RST = 0x0,
155 REG_SD_IDST_RST = 0x0,
156 REG_SD_IDIE_RST = 0x0,
157 REG_SD_THLDC_RST = 0x0,
158 REG_SD_DSBD_RST = 0x0,
159 REG_SD_RES_CRC_RST = 0x0,
160 REG_SD_DATA_CRC_RST = 0x0,
161 REG_SD_CRC_STA_RST = 0x0,
162 REG_SD_SAMPLE_DL_RST = 0x00002000,
163 REG_SD_FIFO_RST = 0x0,
164 };
165
166 /* Data transfer descriptor for DMA */
167 typedef struct TransferDescriptor {
168 uint32_t status; /* Status flags */
169 uint32_t size; /* Data buffer size */
170 uint32_t addr; /* Data buffer address */
171 uint32_t next; /* Physical address of next descriptor */
172 } TransferDescriptor;
173
174 /* Data transfer descriptor flags */
175 enum {
176 DESC_STATUS_HOLD = (1 << 31), /* Set when descriptor is in use by DMA */
177 DESC_STATUS_ERROR = (1 << 30), /* Set when DMA transfer error occurred */
178 DESC_STATUS_CHAIN = (1 << 4), /* Indicates chained descriptor. */
179 DESC_STATUS_FIRST = (1 << 3), /* Set on the first descriptor */
180 DESC_STATUS_LAST = (1 << 2), /* Set on the last descriptor */
181 DESC_STATUS_NOIRQ = (1 << 1), /* Skip raising interrupt after transfer */
182 DESC_SIZE_MASK = (0xfffffffc)
183 };
184
allwinner_sdhost_update_irq(AwSdHostState * s)185 static void allwinner_sdhost_update_irq(AwSdHostState *s)
186 {
187 uint32_t irq;
188
189 if (s->global_ctl & SD_GCTL_INT_ENB) {
190 irq = s->irq_status & s->irq_mask;
191 } else {
192 irq = 0;
193 }
194
195 trace_allwinner_sdhost_update_irq(irq);
196 qemu_set_irq(s->irq, !!irq);
197 }
198
allwinner_sdhost_update_transfer_cnt(AwSdHostState * s,uint32_t bytes)199 static void allwinner_sdhost_update_transfer_cnt(AwSdHostState *s,
200 uint32_t bytes)
201 {
202 if (s->transfer_cnt > bytes) {
203 s->transfer_cnt -= bytes;
204 } else {
205 s->transfer_cnt = 0;
206 }
207
208 if (!s->transfer_cnt) {
209 s->irq_status |= SD_RISR_DATA_COMPLETE;
210 }
211 }
212
allwinner_sdhost_set_inserted(DeviceState * dev,bool inserted)213 static void allwinner_sdhost_set_inserted(DeviceState *dev, bool inserted)
214 {
215 AwSdHostState *s = AW_SDHOST(dev);
216
217 trace_allwinner_sdhost_set_inserted(inserted);
218
219 if (inserted) {
220 s->irq_status |= SD_RISR_CARD_INSERT;
221 s->irq_status &= ~SD_RISR_CARD_REMOVE;
222 s->status |= SD_STAR_CARD_PRESENT;
223 } else {
224 s->irq_status &= ~SD_RISR_CARD_INSERT;
225 s->irq_status |= SD_RISR_CARD_REMOVE;
226 s->status &= ~SD_STAR_CARD_PRESENT;
227 }
228
229 allwinner_sdhost_update_irq(s);
230 }
231
allwinner_sdhost_send_command(AwSdHostState * s)232 static void allwinner_sdhost_send_command(AwSdHostState *s)
233 {
234 SDRequest request;
235 uint8_t resp[16];
236 size_t rlen;
237
238 /* Auto clear load flag */
239 s->command &= ~SD_CMDR_LOAD;
240
241 /* Clock change does not actually interact with the SD bus */
242 if (!(s->command & SD_CMDR_CLKCHANGE)) {
243
244 /* Prepare request */
245 request.cmd = s->command & SD_CMDR_CMDID_MASK;
246 request.arg = s->command_arg;
247
248 /* Send request to SD bus */
249 rlen = sdbus_do_command(&s->sdbus, &request, resp, sizeof(resp));
250
251 /* If the command has a response, store it in the response registers */
252 if ((s->command & SD_CMDR_RESPONSE)) {
253 if (rlen == 4 && !(s->command & SD_CMDR_RESPONSE_LONG)) {
254 s->response[0] = ldl_be_p(&resp[0]);
255 s->response[1] = s->response[2] = s->response[3] = 0;
256
257 } else if (rlen == 16 && (s->command & SD_CMDR_RESPONSE_LONG)) {
258 s->response[0] = ldl_be_p(&resp[12]);
259 s->response[1] = ldl_be_p(&resp[8]);
260 s->response[2] = ldl_be_p(&resp[4]);
261 s->response[3] = ldl_be_p(&resp[0]);
262 } else {
263 goto error;
264 }
265 }
266 }
267
268 /* Set interrupt status bits */
269 s->irq_status |= SD_RISR_CMD_COMPLETE;
270 return;
271
272 error:
273 s->irq_status |= SD_RISR_NO_RESPONSE;
274 }
275
allwinner_sdhost_auto_stop(AwSdHostState * s)276 static void allwinner_sdhost_auto_stop(AwSdHostState *s)
277 {
278 /*
279 * The stop command (CMD12) ensures the SD bus
280 * returns to the transfer state.
281 */
282 if ((s->command & SD_CMDR_AUTOSTOP) && (s->transfer_cnt == 0)) {
283 /* First save current command registers */
284 uint32_t saved_cmd = s->command;
285 uint32_t saved_arg = s->command_arg;
286
287 /* Prepare stop command (CMD12) */
288 s->command &= ~SD_CMDR_CMDID_MASK;
289 s->command |= 12; /* CMD12 */
290 s->command_arg = 0;
291
292 /* Put the command on SD bus */
293 allwinner_sdhost_send_command(s);
294
295 /* Restore command values */
296 s->command = saved_cmd;
297 s->command_arg = saved_arg;
298
299 /* Set IRQ status bit for automatic stop done */
300 s->irq_status |= SD_RISR_AUTOCMD_DONE;
301 }
302 }
303
read_descriptor(AwSdHostState * s,hwaddr desc_addr,TransferDescriptor * desc)304 static void read_descriptor(AwSdHostState *s, hwaddr desc_addr,
305 TransferDescriptor *desc)
306 {
307 uint32_t desc_words[4];
308 dma_memory_read(&s->dma_as, desc_addr, &desc_words, sizeof(desc_words),
309 MEMTXATTRS_UNSPECIFIED);
310 desc->status = le32_to_cpu(desc_words[0]);
311 desc->size = le32_to_cpu(desc_words[1]);
312 desc->addr = le32_to_cpu(desc_words[2]);
313 desc->next = le32_to_cpu(desc_words[3]);
314 }
315
write_descriptor(AwSdHostState * s,hwaddr desc_addr,const TransferDescriptor * desc)316 static void write_descriptor(AwSdHostState *s, hwaddr desc_addr,
317 const TransferDescriptor *desc)
318 {
319 uint32_t desc_words[4];
320 desc_words[0] = cpu_to_le32(desc->status);
321 desc_words[1] = cpu_to_le32(desc->size);
322 desc_words[2] = cpu_to_le32(desc->addr);
323 desc_words[3] = cpu_to_le32(desc->next);
324 dma_memory_write(&s->dma_as, desc_addr, &desc_words, sizeof(desc_words),
325 MEMTXATTRS_UNSPECIFIED);
326 }
327
allwinner_sdhost_process_desc(AwSdHostState * s,hwaddr desc_addr,TransferDescriptor * desc,bool is_write,uint32_t max_bytes)328 static uint32_t allwinner_sdhost_process_desc(AwSdHostState *s,
329 hwaddr desc_addr,
330 TransferDescriptor *desc,
331 bool is_write, uint32_t max_bytes)
332 {
333 AwSdHostClass *klass = AW_SDHOST_GET_CLASS(s);
334 uint32_t num_done = 0;
335 uint32_t num_bytes = max_bytes;
336 uint8_t buf[1024];
337
338 read_descriptor(s, desc_addr, desc);
339 if (desc->size == 0) {
340 desc->size = klass->max_desc_size;
341 } else if (desc->size > klass->max_desc_size) {
342 qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA descriptor buffer size "
343 " is out-of-bounds: %" PRIu32 " > %zu",
344 __func__, desc->size, klass->max_desc_size);
345 desc->size = klass->max_desc_size;
346 }
347 if (desc->size < num_bytes) {
348 num_bytes = desc->size;
349 }
350
351 trace_allwinner_sdhost_process_desc(desc_addr, desc->size,
352 is_write, max_bytes);
353
354 while (num_done < num_bytes) {
355 /* Try to completely fill the local buffer */
356 uint32_t buf_bytes = num_bytes - num_done;
357 if (buf_bytes > sizeof(buf)) {
358 buf_bytes = sizeof(buf);
359 }
360
361 /* Write to SD bus */
362 if (is_write) {
363 dma_memory_read(&s->dma_as,
364 (desc->addr & DESC_SIZE_MASK) + num_done, buf,
365 buf_bytes, MEMTXATTRS_UNSPECIFIED);
366 sdbus_write_data(&s->sdbus, buf, buf_bytes);
367
368 /* Read from SD bus */
369 } else {
370 sdbus_read_data(&s->sdbus, buf, buf_bytes);
371 dma_memory_write(&s->dma_as,
372 (desc->addr & DESC_SIZE_MASK) + num_done, buf,
373 buf_bytes, MEMTXATTRS_UNSPECIFIED);
374 }
375 num_done += buf_bytes;
376 }
377
378 /* Clear hold flag and flush descriptor */
379 desc->status &= ~DESC_STATUS_HOLD;
380 write_descriptor(s, desc_addr, desc);
381
382 return num_done;
383 }
384
allwinner_sdhost_dma(AwSdHostState * s)385 static void allwinner_sdhost_dma(AwSdHostState *s)
386 {
387 TransferDescriptor desc;
388 hwaddr desc_addr = s->desc_base;
389 bool is_write = (s->command & SD_CMDR_WRITE);
390 uint32_t bytes_done = 0;
391
392 /* Check if DMA can be performed */
393 if (s->byte_count == 0 || s->block_size == 0 ||
394 !(s->global_ctl & SD_GCTL_DMA_ENB)) {
395 return;
396 }
397
398 /*
399 * For read operations, data must be available on the SD bus
400 * If not, it is an error and we should not act at all
401 */
402 if (!is_write && !sdbus_data_ready(&s->sdbus)) {
403 return;
404 }
405
406 /* Process the DMA descriptors until all data is copied */
407 while (s->byte_count > 0) {
408 bytes_done = allwinner_sdhost_process_desc(s, desc_addr, &desc,
409 is_write, s->byte_count);
410 allwinner_sdhost_update_transfer_cnt(s, bytes_done);
411
412 if (bytes_done <= s->byte_count) {
413 s->byte_count -= bytes_done;
414 } else {
415 s->byte_count = 0;
416 }
417
418 if (desc.status & DESC_STATUS_LAST) {
419 break;
420 } else {
421 desc_addr = desc.next;
422 }
423 }
424
425 /* Raise IRQ to signal DMA is completed */
426 s->irq_status |= SD_RISR_DATA_COMPLETE | SD_RISR_SDIO_INTR;
427
428 /* Update DMAC bits */
429 s->dmac_status |= SD_IDST_INT_SUMMARY;
430
431 if (is_write) {
432 s->dmac_status |= SD_IDST_TRANSMIT_IRQ;
433 } else {
434 s->dmac_status |= SD_IDST_RECEIVE_IRQ;
435 }
436 }
437
allwinner_sdhost_fifo_read(AwSdHostState * s)438 static uint32_t allwinner_sdhost_fifo_read(AwSdHostState *s)
439 {
440 uint32_t res = 0;
441
442 if (sdbus_data_ready(&s->sdbus)) {
443 sdbus_read_data(&s->sdbus, &res, sizeof(uint32_t));
444 le32_to_cpus(&res);
445 allwinner_sdhost_update_transfer_cnt(s, sizeof(uint32_t));
446 allwinner_sdhost_auto_stop(s);
447 allwinner_sdhost_update_irq(s);
448 } else {
449 qemu_log_mask(LOG_GUEST_ERROR, "%s: no data ready on SD bus\n",
450 __func__);
451 }
452
453 return res;
454 }
455
allwinner_sdhost_read(void * opaque,hwaddr offset,unsigned size)456 static uint64_t allwinner_sdhost_read(void *opaque, hwaddr offset,
457 unsigned size)
458 {
459 AwSdHostState *s = AW_SDHOST(opaque);
460 AwSdHostClass *sc = AW_SDHOST_GET_CLASS(s);
461 bool out_of_bounds = false;
462 uint32_t res = 0;
463
464 switch (offset) {
465 case REG_SD_GCTL: /* Global Control */
466 res = s->global_ctl;
467 break;
468 case REG_SD_CKCR: /* Clock Control */
469 res = s->clock_ctl;
470 break;
471 case REG_SD_TMOR: /* Timeout */
472 res = s->timeout;
473 break;
474 case REG_SD_BWDR: /* Bus Width */
475 res = s->bus_width;
476 break;
477 case REG_SD_BKSR: /* Block Size */
478 res = s->block_size;
479 break;
480 case REG_SD_BYCR: /* Byte Count */
481 res = s->byte_count;
482 break;
483 case REG_SD_CMDR: /* Command */
484 res = s->command;
485 break;
486 case REG_SD_CAGR: /* Command Argument */
487 res = s->command_arg;
488 break;
489 case REG_SD_RESP0: /* Response Zero */
490 res = s->response[0];
491 break;
492 case REG_SD_RESP1: /* Response One */
493 res = s->response[1];
494 break;
495 case REG_SD_RESP2: /* Response Two */
496 res = s->response[2];
497 break;
498 case REG_SD_RESP3: /* Response Three */
499 res = s->response[3];
500 break;
501 case REG_SD_IMKR: /* Interrupt Mask */
502 res = s->irq_mask;
503 break;
504 case REG_SD_MISR: /* Masked Interrupt Status */
505 res = s->irq_status & s->irq_mask;
506 break;
507 case REG_SD_RISR: /* Raw Interrupt Status */
508 res = s->irq_status;
509 break;
510 case REG_SD_STAR: /* Status */
511 res = s->status;
512 if (sdbus_data_ready(&s->sdbus)) {
513 res |= SD_STAR_FIFO_LEVEL_1;
514 } else {
515 res |= SD_STAR_FIFO_EMPTY;
516 }
517 break;
518 case REG_SD_FWLR: /* FIFO Water Level */
519 res = s->fifo_wlevel;
520 break;
521 case REG_SD_FUNS: /* FIFO Function Select */
522 res = s->fifo_func_sel;
523 break;
524 case REG_SD_DBGC: /* Debug Enable */
525 res = s->debug_enable;
526 break;
527 case REG_SD_A12A: /* Auto command 12 argument */
528 res = s->auto12_arg;
529 break;
530 case REG_SD_NTSR: /* SD NewTiming Set */
531 res = s->newtiming_set;
532 break;
533 case REG_SD_SDBG: /* SD newTiming Set Debug */
534 res = s->newtiming_debug;
535 break;
536 case REG_SD_HWRST: /* Hardware Reset Register */
537 res = s->hardware_rst;
538 break;
539 case REG_SD_DMAC: /* Internal DMA Controller Control */
540 res = s->dmac;
541 break;
542 case REG_SD_DLBA: /* Descriptor List Base Address */
543 res = s->desc_base;
544 break;
545 case REG_SD_IDST: /* Internal DMA Controller Status */
546 res = s->dmac_status;
547 break;
548 case REG_SD_IDIE: /* Internal DMA Controller Interrupt Enable */
549 res = s->dmac_irq;
550 break;
551 case REG_SD_THLDC: /* Card Threshold Control or FIFO register (sun4i) */
552 if (sc->is_sun4i) {
553 res = allwinner_sdhost_fifo_read(s);
554 } else {
555 res = s->card_threshold;
556 }
557 break;
558 case REG_SD_DSBD: /* eMMC DDR Start Bit Detection Control */
559 res = s->startbit_detect;
560 break;
561 case REG_SD_RES_CRC: /* Response CRC from card/eMMC */
562 res = s->response_crc;
563 break;
564 case REG_SD_DATA7_CRC: /* CRC Data 7 from card/eMMC */
565 case REG_SD_DATA6_CRC: /* CRC Data 6 from card/eMMC */
566 case REG_SD_DATA5_CRC: /* CRC Data 5 from card/eMMC */
567 case REG_SD_DATA4_CRC: /* CRC Data 4 from card/eMMC */
568 case REG_SD_DATA3_CRC: /* CRC Data 3 from card/eMMC */
569 case REG_SD_DATA2_CRC: /* CRC Data 2 from card/eMMC */
570 case REG_SD_DATA1_CRC: /* CRC Data 1 from card/eMMC */
571 case REG_SD_DATA0_CRC: /* CRC Data 0 from card/eMMC */
572 res = s->data_crc[((offset - REG_SD_DATA7_CRC) / sizeof(uint32_t))];
573 break;
574 case REG_SD_CRC_STA: /* CRC status from card/eMMC in write operation */
575 res = s->status_crc;
576 break;
577 case REG_SD_FIFO: /* Read/Write FIFO */
578 res = allwinner_sdhost_fifo_read(s);
579 break;
580 case REG_SD_SAMP_DL: /* Sample Delay */
581 if (sc->can_calibrate) {
582 res = s->sample_delay;
583 } else {
584 out_of_bounds = true;
585 }
586 break;
587 default:
588 out_of_bounds = true;
589 res = 0;
590 break;
591 }
592
593 if (out_of_bounds) {
594 qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset %"
595 HWADDR_PRIx"\n", __func__, offset);
596 }
597
598 trace_allwinner_sdhost_read(offset, res, size);
599 return res;
600 }
601
allwinner_sdhost_fifo_write(AwSdHostState * s,uint64_t value)602 static void allwinner_sdhost_fifo_write(AwSdHostState *s, uint64_t value)
603 {
604 uint32_t u32 = cpu_to_le32(value);
605 sdbus_write_data(&s->sdbus, &u32, sizeof(u32));
606 allwinner_sdhost_update_transfer_cnt(s, sizeof(u32));
607 allwinner_sdhost_auto_stop(s);
608 allwinner_sdhost_update_irq(s);
609 }
610
allwinner_sdhost_write(void * opaque,hwaddr offset,uint64_t value,unsigned size)611 static void allwinner_sdhost_write(void *opaque, hwaddr offset,
612 uint64_t value, unsigned size)
613 {
614 AwSdHostState *s = AW_SDHOST(opaque);
615 AwSdHostClass *sc = AW_SDHOST_GET_CLASS(s);
616 bool out_of_bounds = false;
617
618 trace_allwinner_sdhost_write(offset, value, size);
619
620 switch (offset) {
621 case REG_SD_GCTL: /* Global Control */
622 s->global_ctl = value;
623 s->global_ctl &= ~(SD_GCTL_DMA_RST | SD_GCTL_FIFO_RST |
624 SD_GCTL_SOFT_RST);
625 allwinner_sdhost_update_irq(s);
626 break;
627 case REG_SD_CKCR: /* Clock Control */
628 s->clock_ctl = value;
629 break;
630 case REG_SD_TMOR: /* Timeout */
631 s->timeout = value;
632 break;
633 case REG_SD_BWDR: /* Bus Width */
634 s->bus_width = value;
635 break;
636 case REG_SD_BKSR: /* Block Size */
637 s->block_size = value;
638 break;
639 case REG_SD_BYCR: /* Byte Count */
640 s->byte_count = value;
641 s->transfer_cnt = value;
642 break;
643 case REG_SD_CMDR: /* Command */
644 s->command = value;
645 if (value & SD_CMDR_LOAD) {
646 allwinner_sdhost_send_command(s);
647 allwinner_sdhost_dma(s);
648 allwinner_sdhost_auto_stop(s);
649 }
650 allwinner_sdhost_update_irq(s);
651 break;
652 case REG_SD_CAGR: /* Command Argument */
653 s->command_arg = value;
654 break;
655 case REG_SD_RESP0: /* Response Zero */
656 s->response[0] = value;
657 break;
658 case REG_SD_RESP1: /* Response One */
659 s->response[1] = value;
660 break;
661 case REG_SD_RESP2: /* Response Two */
662 s->response[2] = value;
663 break;
664 case REG_SD_RESP3: /* Response Three */
665 s->response[3] = value;
666 break;
667 case REG_SD_IMKR: /* Interrupt Mask */
668 s->irq_mask = value;
669 allwinner_sdhost_update_irq(s);
670 break;
671 case REG_SD_MISR: /* Masked Interrupt Status */
672 case REG_SD_RISR: /* Raw Interrupt Status */
673 s->irq_status &= ~value;
674 allwinner_sdhost_update_irq(s);
675 break;
676 case REG_SD_STAR: /* Status */
677 s->status &= ~value;
678 allwinner_sdhost_update_irq(s);
679 break;
680 case REG_SD_FWLR: /* FIFO Water Level */
681 s->fifo_wlevel = value;
682 break;
683 case REG_SD_FUNS: /* FIFO Function Select */
684 s->fifo_func_sel = value;
685 break;
686 case REG_SD_DBGC: /* Debug Enable */
687 s->debug_enable = value;
688 break;
689 case REG_SD_A12A: /* Auto command 12 argument */
690 s->auto12_arg = value;
691 break;
692 case REG_SD_NTSR: /* SD NewTiming Set */
693 s->newtiming_set = value;
694 break;
695 case REG_SD_SDBG: /* SD newTiming Set Debug */
696 s->newtiming_debug = value;
697 break;
698 case REG_SD_HWRST: /* Hardware Reset Register */
699 s->hardware_rst = value;
700 break;
701 case REG_SD_DMAC: /* Internal DMA Controller Control */
702 s->dmac = value;
703 allwinner_sdhost_update_irq(s);
704 break;
705 case REG_SD_DLBA: /* Descriptor List Base Address */
706 s->desc_base = value;
707 break;
708 case REG_SD_IDST: /* Internal DMA Controller Status */
709 s->dmac_status &= (~SD_IDST_WR_MASK) | (~value & SD_IDST_WR_MASK);
710 allwinner_sdhost_update_irq(s);
711 break;
712 case REG_SD_IDIE: /* Internal DMA Controller Interrupt Enable */
713 s->dmac_irq = value;
714 allwinner_sdhost_update_irq(s);
715 break;
716 case REG_SD_THLDC: /* Card Threshold Control or FIFO (sun4i) */
717 if (sc->is_sun4i) {
718 allwinner_sdhost_fifo_write(s, value);
719 } else {
720 s->card_threshold = value;
721 }
722 break;
723 case REG_SD_DSBD: /* eMMC DDR Start Bit Detection Control */
724 s->startbit_detect = value;
725 break;
726 case REG_SD_FIFO: /* Read/Write FIFO */
727 allwinner_sdhost_fifo_write(s, value);
728 break;
729 case REG_SD_RES_CRC: /* Response CRC from card/eMMC */
730 case REG_SD_DATA7_CRC: /* CRC Data 7 from card/eMMC */
731 case REG_SD_DATA6_CRC: /* CRC Data 6 from card/eMMC */
732 case REG_SD_DATA5_CRC: /* CRC Data 5 from card/eMMC */
733 case REG_SD_DATA4_CRC: /* CRC Data 4 from card/eMMC */
734 case REG_SD_DATA3_CRC: /* CRC Data 3 from card/eMMC */
735 case REG_SD_DATA2_CRC: /* CRC Data 2 from card/eMMC */
736 case REG_SD_DATA1_CRC: /* CRC Data 1 from card/eMMC */
737 case REG_SD_DATA0_CRC: /* CRC Data 0 from card/eMMC */
738 case REG_SD_CRC_STA: /* CRC status from card/eMMC in write operation */
739 break;
740 case REG_SD_SAMP_DL: /* Sample delay control */
741 if (sc->can_calibrate) {
742 s->sample_delay = value;
743 } else {
744 out_of_bounds = true;
745 }
746 break;
747 default:
748 out_of_bounds = true;
749 break;
750 }
751
752 if (out_of_bounds) {
753 qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset %"
754 HWADDR_PRIx"\n", __func__, offset);
755 }
756 }
757
758 static const MemoryRegionOps allwinner_sdhost_ops = {
759 .read = allwinner_sdhost_read,
760 .write = allwinner_sdhost_write,
761 .endianness = DEVICE_LITTLE_ENDIAN,
762 .valid = {
763 .min_access_size = 4,
764 .max_access_size = 4,
765 },
766 .impl.min_access_size = 4,
767 };
768
769 static const VMStateDescription vmstate_allwinner_sdhost = {
770 .name = "allwinner-sdhost",
771 .version_id = 1,
772 .minimum_version_id = 1,
773 .fields = (const VMStateField[]) {
774 VMSTATE_UINT32(global_ctl, AwSdHostState),
775 VMSTATE_UINT32(clock_ctl, AwSdHostState),
776 VMSTATE_UINT32(timeout, AwSdHostState),
777 VMSTATE_UINT32(bus_width, AwSdHostState),
778 VMSTATE_UINT32(block_size, AwSdHostState),
779 VMSTATE_UINT32(byte_count, AwSdHostState),
780 VMSTATE_UINT32(transfer_cnt, AwSdHostState),
781 VMSTATE_UINT32(command, AwSdHostState),
782 VMSTATE_UINT32(command_arg, AwSdHostState),
783 VMSTATE_UINT32_ARRAY(response, AwSdHostState, 4),
784 VMSTATE_UINT32(irq_mask, AwSdHostState),
785 VMSTATE_UINT32(irq_status, AwSdHostState),
786 VMSTATE_UINT32(status, AwSdHostState),
787 VMSTATE_UINT32(fifo_wlevel, AwSdHostState),
788 VMSTATE_UINT32(fifo_func_sel, AwSdHostState),
789 VMSTATE_UINT32(debug_enable, AwSdHostState),
790 VMSTATE_UINT32(auto12_arg, AwSdHostState),
791 VMSTATE_UINT32(newtiming_set, AwSdHostState),
792 VMSTATE_UINT32(newtiming_debug, AwSdHostState),
793 VMSTATE_UINT32(hardware_rst, AwSdHostState),
794 VMSTATE_UINT32(dmac, AwSdHostState),
795 VMSTATE_UINT32(desc_base, AwSdHostState),
796 VMSTATE_UINT32(dmac_status, AwSdHostState),
797 VMSTATE_UINT32(dmac_irq, AwSdHostState),
798 VMSTATE_UINT32(card_threshold, AwSdHostState),
799 VMSTATE_UINT32(startbit_detect, AwSdHostState),
800 VMSTATE_UINT32(response_crc, AwSdHostState),
801 VMSTATE_UINT32_ARRAY(data_crc, AwSdHostState, 8),
802 VMSTATE_UINT32(status_crc, AwSdHostState),
803 VMSTATE_UINT32(sample_delay, AwSdHostState),
804 VMSTATE_END_OF_LIST()
805 }
806 };
807
808 static const Property allwinner_sdhost_properties[] = {
809 DEFINE_PROP_LINK("dma-memory", AwSdHostState, dma_mr,
810 TYPE_MEMORY_REGION, MemoryRegion *),
811 };
812
allwinner_sdhost_init(Object * obj)813 static void allwinner_sdhost_init(Object *obj)
814 {
815 AwSdHostState *s = AW_SDHOST(obj);
816
817 qbus_init(&s->sdbus, sizeof(s->sdbus),
818 TYPE_AW_SDHOST_BUS, DEVICE(s), "sd-bus");
819
820 memory_region_init_io(&s->iomem, obj, &allwinner_sdhost_ops, s,
821 TYPE_AW_SDHOST, 4 * KiB);
822 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
823 sysbus_init_irq(SYS_BUS_DEVICE(s), &s->irq);
824 }
825
allwinner_sdhost_realize(DeviceState * dev,Error ** errp)826 static void allwinner_sdhost_realize(DeviceState *dev, Error **errp)
827 {
828 AwSdHostState *s = AW_SDHOST(dev);
829
830 if (!s->dma_mr) {
831 error_setg(errp, TYPE_AW_SDHOST " 'dma-memory' link not set");
832 return;
833 }
834
835 address_space_init(&s->dma_as, s->dma_mr, "sdhost-dma");
836 }
837
allwinner_sdhost_reset(DeviceState * dev)838 static void allwinner_sdhost_reset(DeviceState *dev)
839 {
840 AwSdHostState *s = AW_SDHOST(dev);
841 AwSdHostClass *sc = AW_SDHOST_GET_CLASS(s);
842
843 s->global_ctl = REG_SD_GCTL_RST;
844 s->clock_ctl = REG_SD_CKCR_RST;
845 s->timeout = REG_SD_TMOR_RST;
846 s->bus_width = REG_SD_BWDR_RST;
847 s->block_size = REG_SD_BKSR_RST;
848 s->byte_count = REG_SD_BYCR_RST;
849 s->transfer_cnt = 0;
850
851 s->command = REG_SD_CMDR_RST;
852 s->command_arg = REG_SD_CAGR_RST;
853
854 for (int i = 0; i < ARRAY_SIZE(s->response); i++) {
855 s->response[i] = REG_SD_RESP_RST;
856 }
857
858 s->irq_mask = REG_SD_IMKR_RST;
859 s->irq_status = REG_SD_RISR_RST;
860 s->status = REG_SD_STAR_RST;
861
862 s->fifo_wlevel = REG_SD_FWLR_RST;
863 s->fifo_func_sel = REG_SD_FUNS_RST;
864 s->debug_enable = REG_SD_DBGC_RST;
865 s->auto12_arg = REG_SD_A12A_RST;
866 s->newtiming_set = REG_SD_NTSR_RST;
867 s->newtiming_debug = REG_SD_SDBG_RST;
868 s->hardware_rst = REG_SD_HWRST_RST;
869 s->dmac = REG_SD_DMAC_RST;
870 s->desc_base = REG_SD_DLBA_RST;
871 s->dmac_status = REG_SD_IDST_RST;
872 s->dmac_irq = REG_SD_IDIE_RST;
873 s->card_threshold = REG_SD_THLDC_RST;
874 s->startbit_detect = REG_SD_DSBD_RST;
875 s->response_crc = REG_SD_RES_CRC_RST;
876
877 for (int i = 0; i < ARRAY_SIZE(s->data_crc); i++) {
878 s->data_crc[i] = REG_SD_DATA_CRC_RST;
879 }
880
881 s->status_crc = REG_SD_CRC_STA_RST;
882
883 if (sc->can_calibrate) {
884 s->sample_delay = REG_SD_SAMPLE_DL_RST;
885 }
886 }
887
allwinner_sdhost_bus_class_init(ObjectClass * klass,const void * data)888 static void allwinner_sdhost_bus_class_init(ObjectClass *klass,
889 const void *data)
890 {
891 SDBusClass *sbc = SD_BUS_CLASS(klass);
892
893 sbc->set_inserted = allwinner_sdhost_set_inserted;
894 }
895
allwinner_sdhost_class_init(ObjectClass * klass,const void * data)896 static void allwinner_sdhost_class_init(ObjectClass *klass, const void *data)
897 {
898 DeviceClass *dc = DEVICE_CLASS(klass);
899
900 device_class_set_legacy_reset(dc, allwinner_sdhost_reset);
901 dc->vmsd = &vmstate_allwinner_sdhost;
902 dc->realize = allwinner_sdhost_realize;
903 device_class_set_props(dc, allwinner_sdhost_properties);
904 }
905
allwinner_sdhost_sun4i_class_init(ObjectClass * klass,const void * data)906 static void allwinner_sdhost_sun4i_class_init(ObjectClass *klass,
907 const void *data)
908 {
909 AwSdHostClass *sc = AW_SDHOST_CLASS(klass);
910 sc->max_desc_size = 8 * KiB;
911 sc->is_sun4i = true;
912 sc->can_calibrate = false;
913 }
914
allwinner_sdhost_sun5i_class_init(ObjectClass * klass,const void * data)915 static void allwinner_sdhost_sun5i_class_init(ObjectClass *klass,
916 const void *data)
917 {
918 AwSdHostClass *sc = AW_SDHOST_CLASS(klass);
919 sc->max_desc_size = 64 * KiB;
920 sc->is_sun4i = false;
921 sc->can_calibrate = false;
922 }
923
allwinner_sdhost_sun50i_a64_class_init(ObjectClass * klass,const void * data)924 static void allwinner_sdhost_sun50i_a64_class_init(ObjectClass *klass,
925 const void *data)
926 {
927 AwSdHostClass *sc = AW_SDHOST_CLASS(klass);
928 sc->max_desc_size = 64 * KiB;
929 sc->is_sun4i = false;
930 sc->can_calibrate = true;
931 }
932
allwinner_sdhost_sun50i_a64_emmc_class_init(ObjectClass * klass,const void * data)933 static void allwinner_sdhost_sun50i_a64_emmc_class_init(ObjectClass *klass,
934 const void *data)
935 {
936 AwSdHostClass *sc = AW_SDHOST_CLASS(klass);
937 sc->max_desc_size = 8 * KiB;
938 sc->is_sun4i = false;
939 sc->can_calibrate = true;
940 }
941
942 static const TypeInfo allwinner_sdhost_info = {
943 .name = TYPE_AW_SDHOST,
944 .parent = TYPE_SYS_BUS_DEVICE,
945 .instance_init = allwinner_sdhost_init,
946 .instance_size = sizeof(AwSdHostState),
947 .class_init = allwinner_sdhost_class_init,
948 .class_size = sizeof(AwSdHostClass),
949 .abstract = true,
950 };
951
952 static const TypeInfo allwinner_sdhost_sun4i_info = {
953 .name = TYPE_AW_SDHOST_SUN4I,
954 .parent = TYPE_AW_SDHOST,
955 .class_init = allwinner_sdhost_sun4i_class_init,
956 };
957
958 static const TypeInfo allwinner_sdhost_sun5i_info = {
959 .name = TYPE_AW_SDHOST_SUN5I,
960 .parent = TYPE_AW_SDHOST,
961 .class_init = allwinner_sdhost_sun5i_class_init,
962 };
963
964 static const TypeInfo allwinner_sdhost_sun50i_a64_info = {
965 .name = TYPE_AW_SDHOST_SUN50I_A64,
966 .parent = TYPE_AW_SDHOST,
967 .class_init = allwinner_sdhost_sun50i_a64_class_init,
968 };
969
970 static const TypeInfo allwinner_sdhost_sun50i_a64_emmc_info = {
971 .name = TYPE_AW_SDHOST_SUN50I_A64_EMMC,
972 .parent = TYPE_AW_SDHOST,
973 .class_init = allwinner_sdhost_sun50i_a64_emmc_class_init,
974 };
975
976 static const TypeInfo allwinner_sdhost_bus_info = {
977 .name = TYPE_AW_SDHOST_BUS,
978 .parent = TYPE_SD_BUS,
979 .instance_size = sizeof(SDBus),
980 .class_init = allwinner_sdhost_bus_class_init,
981 };
982
allwinner_sdhost_register_types(void)983 static void allwinner_sdhost_register_types(void)
984 {
985 type_register_static(&allwinner_sdhost_info);
986 type_register_static(&allwinner_sdhost_sun4i_info);
987 type_register_static(&allwinner_sdhost_sun5i_info);
988 type_register_static(&allwinner_sdhost_sun50i_a64_info);
989 type_register_static(&allwinner_sdhost_sun50i_a64_emmc_info);
990 type_register_static(&allwinner_sdhost_bus_info);
991 }
992
993 type_init(allwinner_sdhost_register_types)
994