1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2 /* Copyright(c) 2015-17 Intel Corporation. */
3
4 #ifndef __SOUNDWIRE_H
5 #define __SOUNDWIRE_H
6
7 #include <linux/bug.h>
8 #include <linux/lockdep_types.h>
9 #include <linux/irq.h>
10 #include <linux/irqdomain.h>
11 #include <linux/mod_devicetable.h>
12 #include <linux/bitfield.h>
13
14 struct sdw_bus;
15 struct sdw_slave;
16
17 /* SDW spec defines and enums, as defined by MIPI 1.1. Spec */
18
19 /* SDW Broadcast Device Number */
20 #define SDW_BROADCAST_DEV_NUM 15
21
22 /* SDW Enumeration Device Number */
23 #define SDW_ENUM_DEV_NUM 0
24
25 /* SDW Group Device Numbers */
26 #define SDW_GROUP12_DEV_NUM 12
27 #define SDW_GROUP13_DEV_NUM 13
28
29 /* SDW Master Device Number, not supported yet */
30 #define SDW_MASTER_DEV_NUM 14
31
32 #define SDW_NUM_DEV_ID_REGISTERS 6
33 /* frame shape defines */
34
35 /*
36 * Note: The maximum row define in SoundWire spec 1.1 is 23. In order to
37 * fill hole with 0, one more dummy entry is added
38 */
39 #define SDW_FRAME_ROWS 24
40 #define SDW_FRAME_COLS 8
41 #define SDW_FRAME_ROW_COLS (SDW_FRAME_ROWS * SDW_FRAME_COLS)
42
43 #define SDW_FRAME_CTRL_BITS 48
44 #define SDW_MAX_DEVICES 11
45
46 #define SDW_MAX_PORTS 15
47 #define SDW_VALID_PORT_RANGE(n) ((n) < SDW_MAX_PORTS && (n) >= 1)
48
49 enum {
50 SDW_PORT_DIRN_SINK = 0,
51 SDW_PORT_DIRN_SOURCE,
52 SDW_PORT_DIRN_MAX,
53 };
54
55 /*
56 * constants for flow control, ports and transport
57 *
58 * these are bit masks as devices can have multiple capabilities
59 */
60
61 /*
62 * flow modes for SDW port. These can be isochronous, tx controlled,
63 * rx controlled or async
64 */
65 #define SDW_PORT_FLOW_MODE_ISOCH 0
66 #define SDW_PORT_FLOW_MODE_TX_CNTRL BIT(0)
67 #define SDW_PORT_FLOW_MODE_RX_CNTRL BIT(1)
68 #define SDW_PORT_FLOW_MODE_ASYNC GENMASK(1, 0)
69
70 /* sample packaging for block. It can be per port or per channel */
71 #define SDW_BLOCK_PACKG_PER_PORT BIT(0)
72 #define SDW_BLOCK_PACKG_PER_CH BIT(1)
73
74 /**
75 * enum sdw_slave_status - Slave status
76 * @SDW_SLAVE_UNATTACHED: Slave is not attached with the bus.
77 * @SDW_SLAVE_ATTACHED: Slave is attached with bus.
78 * @SDW_SLAVE_ALERT: Some alert condition on the Slave
79 * @SDW_SLAVE_RESERVED: Reserved for future use
80 */
81 enum sdw_slave_status {
82 SDW_SLAVE_UNATTACHED = 0,
83 SDW_SLAVE_ATTACHED = 1,
84 SDW_SLAVE_ALERT = 2,
85 SDW_SLAVE_RESERVED = 3,
86 };
87
88 /**
89 * enum sdw_clk_stop_type: clock stop operations
90 *
91 * @SDW_CLK_PRE_PREPARE: pre clock stop prepare
92 * @SDW_CLK_POST_PREPARE: post clock stop prepare
93 * @SDW_CLK_PRE_DEPREPARE: pre clock stop de-prepare
94 * @SDW_CLK_POST_DEPREPARE: post clock stop de-prepare
95 */
96 enum sdw_clk_stop_type {
97 SDW_CLK_PRE_PREPARE = 0,
98 SDW_CLK_POST_PREPARE,
99 SDW_CLK_PRE_DEPREPARE,
100 SDW_CLK_POST_DEPREPARE,
101 };
102
103 /**
104 * enum sdw_command_response - Command response as defined by SDW spec
105 * @SDW_CMD_OK: cmd was successful
106 * @SDW_CMD_IGNORED: cmd was ignored
107 * @SDW_CMD_FAIL: cmd was NACKed
108 * @SDW_CMD_TIMEOUT: cmd timedout
109 * @SDW_CMD_FAIL_OTHER: cmd failed due to other reason than above
110 *
111 * NOTE: The enum is different than actual Spec as response in the Spec is
112 * combination of ACK/NAK bits
113 *
114 * SDW_CMD_TIMEOUT/FAIL_OTHER is defined for SW use, not in spec
115 */
116 enum sdw_command_response {
117 SDW_CMD_OK = 0,
118 SDW_CMD_IGNORED = 1,
119 SDW_CMD_FAIL = 2,
120 SDW_CMD_TIMEOUT = 3,
121 SDW_CMD_FAIL_OTHER = 4,
122 };
123
124 /* block group count enum */
125 enum sdw_dpn_grouping {
126 SDW_BLK_GRP_CNT_1 = 0,
127 SDW_BLK_GRP_CNT_2 = 1,
128 SDW_BLK_GRP_CNT_3 = 2,
129 SDW_BLK_GRP_CNT_4 = 3,
130 };
131
132 /* block packing mode enum */
133 enum sdw_dpn_pkg_mode {
134 SDW_BLK_PKG_PER_PORT = 0,
135 SDW_BLK_PKG_PER_CHANNEL = 1
136 };
137
138 /**
139 * enum sdw_stream_type: data stream type
140 *
141 * @SDW_STREAM_PCM: PCM data stream
142 * @SDW_STREAM_PDM: PDM data stream
143 *
144 * spec doesn't define this, but is used in implementation
145 */
146 enum sdw_stream_type {
147 SDW_STREAM_PCM = 0,
148 SDW_STREAM_PDM = 1,
149 };
150
151 /**
152 * enum sdw_data_direction: Data direction
153 *
154 * @SDW_DATA_DIR_RX: Data into Port
155 * @SDW_DATA_DIR_TX: Data out of Port
156 */
157 enum sdw_data_direction {
158 SDW_DATA_DIR_RX = 0,
159 SDW_DATA_DIR_TX = 1,
160 };
161
162 /**
163 * enum sdw_port_data_mode: Data Port mode
164 *
165 * @SDW_PORT_DATA_MODE_NORMAL: Normal data mode where audio data is received
166 * and transmitted.
167 * @SDW_PORT_DATA_MODE_PRBS: Test mode which uses a PRBS generator to produce
168 * a pseudo random data pattern that is transferred
169 * @SDW_PORT_DATA_MODE_STATIC_0: Simple test mode which uses static value of
170 * logic 0. The encoding will result in no signal transitions
171 * @SDW_PORT_DATA_MODE_STATIC_1: Simple test mode which uses static value of
172 * logic 1. The encoding will result in signal transitions at every bitslot
173 * owned by this Port
174 */
175 enum sdw_port_data_mode {
176 SDW_PORT_DATA_MODE_NORMAL = 0,
177 SDW_PORT_DATA_MODE_PRBS = 1,
178 SDW_PORT_DATA_MODE_STATIC_0 = 2,
179 SDW_PORT_DATA_MODE_STATIC_1 = 3,
180 };
181
182 /*
183 * SDW properties, defined in MIPI DisCo spec v1.0
184 */
185 enum sdw_clk_stop_reset_behave {
186 SDW_CLK_STOP_KEEP_STATUS = 1,
187 };
188
189 /**
190 * enum sdw_p15_behave - Slave Port 15 behaviour when the Master attempts a
191 * read
192 * @SDW_P15_READ_IGNORED: Read is ignored
193 * @SDW_P15_CMD_OK: Command is ok
194 */
195 enum sdw_p15_behave {
196 SDW_P15_READ_IGNORED = 0,
197 SDW_P15_CMD_OK = 1,
198 };
199
200 /**
201 * enum sdw_dpn_type - Data port types
202 * @SDW_DPN_FULL: Full Data Port is supported
203 * @SDW_DPN_SIMPLE: Simplified Data Port as defined in spec.
204 * DPN_SampleCtrl2, DPN_OffsetCtrl2, DPN_HCtrl and DPN_BlockCtrl3
205 * are not implemented.
206 * @SDW_DPN_REDUCED: Reduced Data Port as defined in spec.
207 * DPN_SampleCtrl2, DPN_HCtrl are not implemented.
208 */
209 enum sdw_dpn_type {
210 SDW_DPN_FULL = 0,
211 SDW_DPN_SIMPLE = 1,
212 SDW_DPN_REDUCED = 2,
213 };
214
215 /**
216 * enum sdw_clk_stop_mode - Clock Stop modes
217 * @SDW_CLK_STOP_MODE0: Slave can continue operation seamlessly on clock
218 * restart
219 * @SDW_CLK_STOP_MODE1: Slave may have entered a deeper power-saving mode,
220 * not capable of continuing operation seamlessly when the clock restarts
221 */
222 enum sdw_clk_stop_mode {
223 SDW_CLK_STOP_MODE0 = 0,
224 SDW_CLK_STOP_MODE1 = 1,
225 };
226
227 /**
228 * struct sdw_dp0_prop - DP0 properties
229 * @max_word: Maximum number of bits in a Payload Channel Sample, 1 to 64
230 * (inclusive)
231 * @min_word: Minimum number of bits in a Payload Channel Sample, 1 to 64
232 * (inclusive)
233 * @num_words: number of wordlengths supported
234 * @words: wordlengths supported
235 * @BRA_flow_controlled: Slave implementation results in an OK_NotReady
236 * response
237 * @simple_ch_prep_sm: If channel prepare sequence is required
238 * @imp_def_interrupts: If set, each bit corresponds to support for
239 * implementation-defined interrupts
240 *
241 * The wordlengths are specified by Spec as max, min AND number of
242 * discrete values, implementation can define based on the wordlengths they
243 * support
244 */
245 struct sdw_dp0_prop {
246 u32 max_word;
247 u32 min_word;
248 u32 num_words;
249 u32 *words;
250 bool BRA_flow_controlled;
251 bool simple_ch_prep_sm;
252 bool imp_def_interrupts;
253 };
254
255 /**
256 * struct sdw_dpn_audio_mode - Audio mode properties for DPn
257 * @bus_min_freq: Minimum bus frequency, in Hz
258 * @bus_max_freq: Maximum bus frequency, in Hz
259 * @bus_num_freq: Number of discrete frequencies supported
260 * @bus_freq: Discrete bus frequencies, in Hz
261 * @min_freq: Minimum sampling frequency, in Hz
262 * @max_freq: Maximum sampling bus frequency, in Hz
263 * @num_freq: Number of discrete sampling frequency supported
264 * @freq: Discrete sampling frequencies, in Hz
265 * @prep_ch_behave: Specifies the dependencies between Channel Prepare
266 * sequence and bus clock configuration
267 * If 0, Channel Prepare can happen at any Bus clock rate
268 * If 1, Channel Prepare sequence shall happen only after Bus clock is
269 * changed to a frequency supported by this mode or compatible modes
270 * described by the next field
271 * @glitchless: Bitmap describing possible glitchless transitions from this
272 * Audio Mode to other Audio Modes
273 */
274 struct sdw_dpn_audio_mode {
275 u32 bus_min_freq;
276 u32 bus_max_freq;
277 u32 bus_num_freq;
278 u32 *bus_freq;
279 u32 max_freq;
280 u32 min_freq;
281 u32 num_freq;
282 u32 *freq;
283 u32 prep_ch_behave;
284 u32 glitchless;
285 };
286
287 /**
288 * struct sdw_dpn_prop - Data Port DPn properties
289 * @num: port number
290 * @max_word: Maximum number of bits in a Payload Channel Sample, 1 to 64
291 * (inclusive)
292 * @min_word: Minimum number of bits in a Payload Channel Sample, 1 to 64
293 * (inclusive)
294 * @num_words: Number of discrete supported wordlengths
295 * @words: Discrete supported wordlength
296 * @type: Data port type. Full, Simplified or Reduced
297 * @max_grouping: Maximum number of samples that can be grouped together for
298 * a full data port
299 * @simple_ch_prep_sm: If the port supports simplified channel prepare state
300 * machine
301 * @ch_prep_timeout: Port-specific timeout value, in milliseconds
302 * @imp_def_interrupts: If set, each bit corresponds to support for
303 * implementation-defined interrupts
304 * @max_ch: Maximum channels supported
305 * @min_ch: Minimum channels supported
306 * @num_channels: Number of discrete channels supported
307 * @channels: Discrete channels supported
308 * @num_ch_combinations: Number of channel combinations supported
309 * @ch_combinations: Channel combinations supported
310 * @modes: SDW mode supported
311 * @max_async_buffer: Number of samples that this port can buffer in
312 * asynchronous modes
313 * @block_pack_mode: Type of block port mode supported
314 * @read_only_wordlength: Read Only wordlength field in DPN_BlockCtrl1 register
315 * @port_encoding: Payload Channel Sample encoding schemes supported
316 * @audio_modes: Audio modes supported
317 */
318 struct sdw_dpn_prop {
319 u32 num;
320 u32 max_word;
321 u32 min_word;
322 u32 num_words;
323 u32 *words;
324 enum sdw_dpn_type type;
325 u32 max_grouping;
326 bool simple_ch_prep_sm;
327 u32 ch_prep_timeout;
328 u32 imp_def_interrupts;
329 u32 max_ch;
330 u32 min_ch;
331 u32 num_channels;
332 u32 *channels;
333 u32 num_ch_combinations;
334 u32 *ch_combinations;
335 u32 modes;
336 u32 max_async_buffer;
337 bool block_pack_mode;
338 bool read_only_wordlength;
339 u32 port_encoding;
340 struct sdw_dpn_audio_mode *audio_modes;
341 };
342
343 /**
344 * struct sdw_slave_prop - SoundWire Slave properties
345 * @mipi_revision: Spec version of the implementation
346 * @wake_capable: Wake-up events are supported
347 * @test_mode_capable: If test mode is supported
348 * @clk_stop_mode1: Clock-Stop Mode 1 is supported
349 * @simple_clk_stop_capable: Simple clock mode is supported
350 * @clk_stop_timeout: Worst-case latency of the Clock Stop Prepare State
351 * Machine transitions, in milliseconds
352 * @ch_prep_timeout: Worst-case latency of the Channel Prepare State Machine
353 * transitions, in milliseconds
354 * @reset_behave: Slave keeps the status of the SlaveStopClockPrepare
355 * state machine (P=1 SCSP_SM) after exit from clock-stop mode1
356 * @high_PHY_capable: Slave is HighPHY capable
357 * @paging_support: Slave implements paging registers SCP_AddrPage1 and
358 * SCP_AddrPage2
359 * @bank_delay_support: Slave implements bank delay/bridge support registers
360 * SCP_BankDelay and SCP_NextFrame
361 * @p15_behave: Slave behavior when the Master attempts a read to the Port15
362 * alias
363 * @lane_control_support: Slave supports lane control
364 * @master_count: Number of Masters present on this Slave
365 * @source_ports: Bitmap identifying source ports
366 * @sink_ports: Bitmap identifying sink ports
367 * @dp0_prop: Data Port 0 properties
368 * @src_dpn_prop: Source Data Port N properties
369 * @sink_dpn_prop: Sink Data Port N properties
370 * @scp_int1_mask: SCP_INT1_MASK desired settings
371 * @quirks: bitmask identifying deltas from the MIPI specification
372 * @clock_reg_supported: the Peripheral implements the clock base and scale
373 * registers introduced with the SoundWire 1.2 specification. SDCA devices
374 * do not need to set this boolean property as the registers are required.
375 * @use_domain_irq: call actual IRQ handler on slave, as well as callback
376 */
377 struct sdw_slave_prop {
378 u32 mipi_revision;
379 bool wake_capable;
380 bool test_mode_capable;
381 bool clk_stop_mode1;
382 bool simple_clk_stop_capable;
383 u32 clk_stop_timeout;
384 u32 ch_prep_timeout;
385 enum sdw_clk_stop_reset_behave reset_behave;
386 bool high_PHY_capable;
387 bool paging_support;
388 bool bank_delay_support;
389 enum sdw_p15_behave p15_behave;
390 bool lane_control_support;
391 u32 master_count;
392 u32 source_ports;
393 u32 sink_ports;
394 struct sdw_dp0_prop *dp0_prop;
395 struct sdw_dpn_prop *src_dpn_prop;
396 struct sdw_dpn_prop *sink_dpn_prop;
397 u8 scp_int1_mask;
398 u32 quirks;
399 bool clock_reg_supported;
400 bool use_domain_irq;
401 };
402
403 #define SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY BIT(0)
404
405 /**
406 * struct sdw_master_prop - Master properties
407 * @revision: MIPI spec version of the implementation
408 * @clk_stop_modes: Bitmap, bit N set when clock-stop-modeN supported
409 * @max_clk_freq: Maximum Bus clock frequency, in Hz
410 * @num_clk_gears: Number of clock gears supported
411 * @clk_gears: Clock gears supported
412 * @num_clk_freq: Number of clock frequencies supported, in Hz
413 * @clk_freq: Clock frequencies supported, in Hz
414 * @default_frame_rate: Controller default Frame rate, in Hz
415 * @default_row: Number of rows
416 * @default_col: Number of columns
417 * @dynamic_frame: Dynamic frame shape supported
418 * @err_threshold: Number of times that software may retry sending a single
419 * command
420 * @mclk_freq: clock reference passed to SoundWire Master, in Hz.
421 * @hw_disabled: if true, the Master is not functional, typically due to pin-mux
422 * @quirks: bitmask identifying optional behavior beyond the scope of the MIPI specification
423 */
424 struct sdw_master_prop {
425 u32 revision;
426 u32 clk_stop_modes;
427 u32 max_clk_freq;
428 u32 num_clk_gears;
429 u32 *clk_gears;
430 u32 num_clk_freq;
431 u32 *clk_freq;
432 u32 default_frame_rate;
433 u32 default_row;
434 u32 default_col;
435 bool dynamic_frame;
436 u32 err_threshold;
437 u32 mclk_freq;
438 bool hw_disabled;
439 u64 quirks;
440 };
441
442 /* Definitions for Master quirks */
443
444 /*
445 * In a number of platforms bus clashes are reported after a hardware
446 * reset but without any explanations or evidence of a real problem.
447 * The following quirk will discard all initial bus clash interrupts
448 * but will leave the detection on should real bus clashes happen
449 */
450 #define SDW_MASTER_QUIRKS_CLEAR_INITIAL_CLASH BIT(0)
451
452 /*
453 * Some Slave devices have known issues with incorrect parity errors
454 * reported after a hardware reset. However during integration unexplained
455 * parity errors can be reported by Slave devices, possibly due to electrical
456 * issues at the Master level.
457 * The following quirk will discard all initial parity errors but will leave
458 * the detection on should real parity errors happen.
459 */
460 #define SDW_MASTER_QUIRKS_CLEAR_INITIAL_PARITY BIT(1)
461
462 int sdw_master_read_prop(struct sdw_bus *bus);
463 int sdw_slave_read_prop(struct sdw_slave *slave);
464
465 /*
466 * SDW Slave Structures and APIs
467 */
468
469 #define SDW_IGNORED_UNIQUE_ID 0xFF
470
471 /**
472 * struct sdw_slave_id - Slave ID
473 * @mfg_id: MIPI Manufacturer ID
474 * @part_id: Device Part ID
475 * @class_id: MIPI Class ID (defined starting with SoundWire 1.2 spec)
476 * @unique_id: Device unique ID
477 * @sdw_version: SDW version implemented
478 *
479 * The order of the IDs here does not follow the DisCo spec definitions
480 */
481 struct sdw_slave_id {
482 __u16 mfg_id;
483 __u16 part_id;
484 __u8 class_id;
485 __u8 unique_id;
486 __u8 sdw_version:4;
487 };
488
489 struct sdw_extended_slave_id {
490 int link_id;
491 struct sdw_slave_id id;
492 };
493
494 /*
495 * Helper macros to extract the MIPI-defined IDs
496 *
497 * Spec definition
498 * Register Bit Contents
499 * DevId_0 [7:4] 47:44 sdw_version
500 * DevId_0 [3:0] 43:40 unique_id
501 * DevId_1 39:32 mfg_id [15:8]
502 * DevId_2 31:24 mfg_id [7:0]
503 * DevId_3 23:16 part_id [15:8]
504 * DevId_4 15:08 part_id [7:0]
505 * DevId_5 07:00 class_id
506 *
507 * The MIPI DisCo for SoundWire defines in addition the link_id as bits 51:48
508 */
509 #define SDW_DISCO_LINK_ID_MASK GENMASK_ULL(51, 48)
510 #define SDW_VERSION_MASK GENMASK_ULL(47, 44)
511 #define SDW_UNIQUE_ID_MASK GENMASK_ULL(43, 40)
512 #define SDW_MFG_ID_MASK GENMASK_ULL(39, 24)
513 #define SDW_PART_ID_MASK GENMASK_ULL(23, 8)
514 #define SDW_CLASS_ID_MASK GENMASK_ULL(7, 0)
515
516 #define SDW_DISCO_LINK_ID(addr) FIELD_GET(SDW_DISCO_LINK_ID_MASK, addr)
517 #define SDW_VERSION(addr) FIELD_GET(SDW_VERSION_MASK, addr)
518 #define SDW_UNIQUE_ID(addr) FIELD_GET(SDW_UNIQUE_ID_MASK, addr)
519 #define SDW_MFG_ID(addr) FIELD_GET(SDW_MFG_ID_MASK, addr)
520 #define SDW_PART_ID(addr) FIELD_GET(SDW_PART_ID_MASK, addr)
521 #define SDW_CLASS_ID(addr) FIELD_GET(SDW_CLASS_ID_MASK, addr)
522
523 /**
524 * struct sdw_slave_intr_status - Slave interrupt status
525 * @sdca_cascade: set if the Slave device reports an SDCA interrupt
526 * @control_port: control port status
527 * @port: data port status
528 */
529 struct sdw_slave_intr_status {
530 bool sdca_cascade;
531 u8 control_port;
532 u8 port[15];
533 };
534
535 /**
536 * sdw_reg_bank - SoundWire register banks
537 * @SDW_BANK0: Soundwire register bank 0
538 * @SDW_BANK1: Soundwire register bank 1
539 */
540 enum sdw_reg_bank {
541 SDW_BANK0,
542 SDW_BANK1,
543 };
544
545 /**
546 * struct sdw_bus_conf: Bus configuration
547 *
548 * @clk_freq: Clock frequency, in Hz
549 * @num_rows: Number of rows in frame
550 * @num_cols: Number of columns in frame
551 * @bank: Next register bank
552 */
553 struct sdw_bus_conf {
554 unsigned int clk_freq;
555 unsigned int num_rows;
556 unsigned int num_cols;
557 unsigned int bank;
558 };
559
560 /**
561 * struct sdw_prepare_ch: Prepare/De-prepare Data Port channel
562 *
563 * @num: Port number
564 * @ch_mask: Active channel mask
565 * @prepare: Prepare (true) /de-prepare (false) channel
566 * @bank: Register bank, which bank Slave/Master driver should program for
567 * implementation defined registers. This is always updated to next_bank
568 * value read from bus params.
569 *
570 */
571 struct sdw_prepare_ch {
572 unsigned int num;
573 unsigned int ch_mask;
574 bool prepare;
575 unsigned int bank;
576 };
577
578 /**
579 * enum sdw_port_prep_ops: Prepare operations for Data Port
580 *
581 * @SDW_OPS_PORT_PRE_PREP: Pre prepare operation for the Port
582 * @SDW_OPS_PORT_PRE_DEPREP: Pre deprepare operation for the Port
583 * @SDW_OPS_PORT_POST_PREP: Post prepare operation for the Port
584 * @SDW_OPS_PORT_POST_DEPREP: Post deprepare operation for the Port
585 */
586 enum sdw_port_prep_ops {
587 SDW_OPS_PORT_PRE_PREP = 0,
588 SDW_OPS_PORT_PRE_DEPREP,
589 SDW_OPS_PORT_POST_PREP,
590 SDW_OPS_PORT_POST_DEPREP,
591 };
592
593 /**
594 * struct sdw_bus_params: Structure holding bus configuration
595 *
596 * @curr_bank: Current bank in use (BANK0/BANK1)
597 * @next_bank: Next bank to use (BANK0/BANK1). next_bank will always be
598 * set to !curr_bank
599 * @max_dr_freq: Maximum double rate clock frequency supported, in Hz
600 * @curr_dr_freq: Current double rate clock frequency, in Hz
601 * @bandwidth: Current bandwidth
602 * @col: Active columns
603 * @row: Active rows
604 * @s_data_mode: NORMAL, STATIC or PRBS mode for all Slave ports
605 * @m_data_mode: NORMAL, STATIC or PRBS mode for all Master ports. The value
606 * should be the same to detect transmission issues, but can be different to
607 * test the interrupt reports
608 */
609 struct sdw_bus_params {
610 enum sdw_reg_bank curr_bank;
611 enum sdw_reg_bank next_bank;
612 unsigned int max_dr_freq;
613 unsigned int curr_dr_freq;
614 unsigned int bandwidth;
615 unsigned int col;
616 unsigned int row;
617 int s_data_mode;
618 int m_data_mode;
619 };
620
621 /**
622 * struct sdw_slave_ops: Slave driver callback ops
623 *
624 * @read_prop: Read Slave properties
625 * @interrupt_callback: Device interrupt notification (invoked in thread
626 * context)
627 * @update_status: Update Slave status
628 * @bus_config: Update the bus config for Slave
629 * @port_prep: Prepare the port with parameters
630 * @clk_stop: handle imp-def sequences before and after prepare and de-prepare
631 */
632 struct sdw_slave_ops {
633 int (*read_prop)(struct sdw_slave *sdw);
634 int (*interrupt_callback)(struct sdw_slave *slave,
635 struct sdw_slave_intr_status *status);
636 int (*update_status)(struct sdw_slave *slave,
637 enum sdw_slave_status status);
638 int (*bus_config)(struct sdw_slave *slave,
639 struct sdw_bus_params *params);
640 int (*port_prep)(struct sdw_slave *slave,
641 struct sdw_prepare_ch *prepare_ch,
642 enum sdw_port_prep_ops pre_ops);
643 int (*clk_stop)(struct sdw_slave *slave,
644 enum sdw_clk_stop_mode mode,
645 enum sdw_clk_stop_type type);
646
647 };
648
649 /**
650 * struct sdw_slave - SoundWire Slave
651 * @id: MIPI device ID
652 * @dev: Linux device
653 * @irq: IRQ number
654 * @status: Status reported by the Slave
655 * @bus: Bus handle
656 * @prop: Slave properties
657 * @debugfs: Slave debugfs
658 * @node: node for bus list
659 * @port_ready: Port ready completion flag for each Slave port
660 * @m_port_map: static Master port map for each Slave port
661 * @dev_num: Current Device Number, values can be 0 or dev_num_sticky
662 * @dev_num_sticky: one-time static Device Number assigned by Bus
663 * @probed: boolean tracking driver state
664 * @enumeration_complete: completion utility to control potential races
665 * on startup between device enumeration and read/write access to the
666 * Slave device
667 * @initialization_complete: completion utility to control potential races
668 * on startup between device enumeration and settings being restored
669 * @unattach_request: mask field to keep track why the Slave re-attached and
670 * was re-initialized. This is useful to deal with potential race conditions
671 * between the Master suspending and the codec resuming, and make sure that
672 * when the Master triggered a reset the Slave is properly enumerated and
673 * initialized
674 * @first_interrupt_done: status flag tracking if the interrupt handling
675 * for a Slave happens for the first time after enumeration
676 * @is_mockup_device: status flag used to squelch errors in the command/control
677 * protocol for SoundWire mockup devices
678 * @sdw_dev_lock: mutex used to protect callbacks/remove races
679 */
680 struct sdw_slave {
681 struct sdw_slave_id id;
682 struct device dev;
683 int irq;
684 enum sdw_slave_status status;
685 struct sdw_bus *bus;
686 struct sdw_slave_prop prop;
687 #ifdef CONFIG_DEBUG_FS
688 struct dentry *debugfs;
689 #endif
690 struct list_head node;
691 struct completion port_ready[SDW_MAX_PORTS];
692 unsigned int m_port_map[SDW_MAX_PORTS];
693 u16 dev_num;
694 u16 dev_num_sticky;
695 bool probed;
696 struct completion enumeration_complete;
697 struct completion initialization_complete;
698 u32 unattach_request;
699 bool first_interrupt_done;
700 bool is_mockup_device;
701 struct mutex sdw_dev_lock; /* protect callbacks/remove races */
702 };
703
704 #define dev_to_sdw_dev(_dev) container_of(_dev, struct sdw_slave, dev)
705
706 /**
707 * struct sdw_master_device - SoundWire 'Master Device' representation
708 * @dev: Linux device for this Master
709 * @bus: Bus handle shortcut
710 */
711 struct sdw_master_device {
712 struct device dev;
713 struct sdw_bus *bus;
714 };
715
716 #define dev_to_sdw_master_device(d) \
717 container_of(d, struct sdw_master_device, dev)
718
719 struct sdw_driver {
720 const char *name;
721
722 int (*probe)(struct sdw_slave *sdw,
723 const struct sdw_device_id *id);
724 int (*remove)(struct sdw_slave *sdw);
725 void (*shutdown)(struct sdw_slave *sdw);
726
727 const struct sdw_device_id *id_table;
728 const struct sdw_slave_ops *ops;
729
730 struct device_driver driver;
731 };
732
733 #define SDW_SLAVE_ENTRY_EXT(_mfg_id, _part_id, _version, _c_id, _drv_data) \
734 { .mfg_id = (_mfg_id), .part_id = (_part_id), \
735 .sdw_version = (_version), .class_id = (_c_id), \
736 .driver_data = (unsigned long)(_drv_data) }
737
738 #define SDW_SLAVE_ENTRY(_mfg_id, _part_id, _drv_data) \
739 SDW_SLAVE_ENTRY_EXT((_mfg_id), (_part_id), 0, 0, (_drv_data))
740
741 int sdw_handle_slave_status(struct sdw_bus *bus,
742 enum sdw_slave_status status[]);
743
744 /*
745 * SDW master structures and APIs
746 */
747
748 /**
749 * struct sdw_port_params: Data Port parameters
750 *
751 * @num: Port number
752 * @bps: Word length of the Port
753 * @flow_mode: Port Data flow mode
754 * @data_mode: Test modes or normal mode
755 *
756 * This is used to program the Data Port based on Data Port stream
757 * parameters.
758 */
759 struct sdw_port_params {
760 unsigned int num;
761 unsigned int bps;
762 unsigned int flow_mode;
763 unsigned int data_mode;
764 };
765
766 /**
767 * struct sdw_transport_params: Data Port Transport Parameters
768 *
769 * @blk_grp_ctrl_valid: Port implements block group control
770 * @num: Port number
771 * @blk_grp_ctrl: Block group control value
772 * @sample_interval: Sample interval
773 * @offset1: Blockoffset of the payload data
774 * @offset2: Blockoffset of the payload data
775 * @hstart: Horizontal start of the payload data
776 * @hstop: Horizontal stop of the payload data
777 * @blk_pkg_mode: Block per channel or block per port
778 * @lane_ctrl: Data lane Port uses for Data transfer. Currently only single
779 * data lane is supported in bus
780 *
781 * This is used to program the Data Port based on Data Port transport
782 * parameters. All these parameters are banked and can be modified
783 * during a bank switch without any artifacts in audio stream.
784 */
785 struct sdw_transport_params {
786 bool blk_grp_ctrl_valid;
787 unsigned int port_num;
788 unsigned int blk_grp_ctrl;
789 unsigned int sample_interval;
790 unsigned int offset1;
791 unsigned int offset2;
792 unsigned int hstart;
793 unsigned int hstop;
794 unsigned int blk_pkg_mode;
795 unsigned int lane_ctrl;
796 };
797
798 /**
799 * struct sdw_enable_ch: Enable/disable Data Port channel
800 *
801 * @num: Port number
802 * @ch_mask: Active channel mask
803 * @enable: Enable (true) /disable (false) channel
804 */
805 struct sdw_enable_ch {
806 unsigned int port_num;
807 unsigned int ch_mask;
808 bool enable;
809 };
810
811 /**
812 * struct sdw_master_port_ops: Callback functions from bus to Master
813 * driver to set Master Data ports.
814 *
815 * @dpn_set_port_params: Set the Port parameters for the Master Port.
816 * Mandatory callback
817 * @dpn_set_port_transport_params: Set transport parameters for the Master
818 * Port. Mandatory callback
819 * @dpn_port_prep: Port prepare operations for the Master Data Port.
820 * @dpn_port_enable_ch: Enable the channels of Master Port.
821 */
822 struct sdw_master_port_ops {
823 int (*dpn_set_port_params)(struct sdw_bus *bus,
824 struct sdw_port_params *port_params,
825 unsigned int bank);
826 int (*dpn_set_port_transport_params)(struct sdw_bus *bus,
827 struct sdw_transport_params *transport_params,
828 enum sdw_reg_bank bank);
829 int (*dpn_port_prep)(struct sdw_bus *bus,
830 struct sdw_prepare_ch *prepare_ch);
831 int (*dpn_port_enable_ch)(struct sdw_bus *bus,
832 struct sdw_enable_ch *enable_ch, unsigned int bank);
833 };
834
835 struct sdw_msg;
836
837 /**
838 * struct sdw_defer - SDW deffered message
839 * @length: message length
840 * @complete: message completion
841 * @msg: SDW message
842 */
843 struct sdw_defer {
844 int length;
845 struct completion complete;
846 struct sdw_msg *msg;
847 };
848
849 /**
850 * struct sdw_master_ops - Master driver ops
851 * @read_prop: Read Master properties
852 * @override_adr: Override value read from firmware (quirk for buggy firmware)
853 * @xfer_msg: Transfer message callback
854 * @xfer_msg_defer: Defer version of transfer message callback. The message is handled with the
855 * bus struct @sdw_defer
856 * @set_bus_conf: Set the bus configuration
857 * @pre_bank_switch: Callback for pre bank switch
858 * @post_bank_switch: Callback for post bank switch
859 * @read_ping_status: Read status from PING frames, reported with two bits per Device.
860 * Bits 31:24 are reserved.
861 * @get_device_num: Callback for vendor-specific device_number allocation
862 * @put_device_num: Callback for vendor-specific device_number release
863 * @new_peripheral_assigned: Callback to handle enumeration of new peripheral.
864 */
865 struct sdw_master_ops {
866 int (*read_prop)(struct sdw_bus *bus);
867 u64 (*override_adr)
868 (struct sdw_bus *bus, u64 addr);
869 enum sdw_command_response (*xfer_msg)
870 (struct sdw_bus *bus, struct sdw_msg *msg);
871 enum sdw_command_response (*xfer_msg_defer)
872 (struct sdw_bus *bus);
873 int (*set_bus_conf)(struct sdw_bus *bus,
874 struct sdw_bus_params *params);
875 int (*pre_bank_switch)(struct sdw_bus *bus);
876 int (*post_bank_switch)(struct sdw_bus *bus);
877 u32 (*read_ping_status)(struct sdw_bus *bus);
878 int (*get_device_num)(struct sdw_bus *bus, struct sdw_slave *slave);
879 void (*put_device_num)(struct sdw_bus *bus, struct sdw_slave *slave);
880 void (*new_peripheral_assigned)(struct sdw_bus *bus,
881 struct sdw_slave *slave,
882 int dev_num);
883 };
884
885 /**
886 * struct sdw_bus - SoundWire bus
887 * @dev: Shortcut to &bus->md->dev to avoid changing the entire code.
888 * @md: Master device
889 * @controller_id: system-unique controller ID. If set to -1, the bus @id will be used.
890 * @link_id: Link id number, can be 0 to N, unique for each Controller
891 * @id: bus system-wide unique id
892 * @slaves: list of Slaves on this bus
893 * @assigned: Bitmap for Slave device numbers.
894 * Bit set implies used number, bit clear implies unused number.
895 * @bus_lock: bus lock
896 * @msg_lock: message lock
897 * @compute_params: points to Bus resource management implementation
898 * @ops: Master callback ops
899 * @port_ops: Master port callback ops
900 * @params: Current bus parameters
901 * @prop: Master properties
902 * @m_rt_list: List of Master instance of all stream(s) running on Bus. This
903 * is used to compute and program bus bandwidth, clock, frame shape,
904 * transport and port parameters
905 * @debugfs: Bus debugfs
906 * @domain: IRQ domain
907 * @defer_msg: Defer message
908 * @clk_stop_timeout: Clock stop timeout computed
909 * @bank_switch_timeout: Bank switch timeout computed
910 * @multi_link: Store bus property that indicates if multi links
911 * are supported. This flag is populated by drivers after reading
912 * appropriate firmware (ACPI/DT).
913 * @hw_sync_min_links: Number of links used by a stream above which
914 * hardware-based synchronization is required. This value is only
915 * meaningful if multi_link is set. If set to 1, hardware-based
916 * synchronization will be used even if a stream only uses a single
917 * SoundWire segment.
918 */
919 struct sdw_bus {
920 struct device *dev;
921 struct sdw_master_device *md;
922 int controller_id;
923 unsigned int link_id;
924 int id;
925 struct list_head slaves;
926 DECLARE_BITMAP(assigned, SDW_MAX_DEVICES);
927 struct mutex bus_lock;
928 struct lock_class_key bus_lock_key;
929 struct mutex msg_lock;
930 struct lock_class_key msg_lock_key;
931 int (*compute_params)(struct sdw_bus *bus);
932 const struct sdw_master_ops *ops;
933 const struct sdw_master_port_ops *port_ops;
934 struct sdw_bus_params params;
935 struct sdw_master_prop prop;
936 struct list_head m_rt_list;
937 #ifdef CONFIG_DEBUG_FS
938 struct dentry *debugfs;
939 #endif
940 struct irq_chip irq_chip;
941 struct irq_domain *domain;
942 struct sdw_defer defer_msg;
943 unsigned int clk_stop_timeout;
944 u32 bank_switch_timeout;
945 bool multi_link;
946 int hw_sync_min_links;
947 };
948
949 int sdw_bus_master_add(struct sdw_bus *bus, struct device *parent,
950 struct fwnode_handle *fwnode);
951 void sdw_bus_master_delete(struct sdw_bus *bus);
952
953 void sdw_show_ping_status(struct sdw_bus *bus, bool sync_delay);
954
955 /**
956 * sdw_port_config: Master or Slave Port configuration
957 *
958 * @num: Port number
959 * @ch_mask: channels mask for port
960 */
961 struct sdw_port_config {
962 unsigned int num;
963 unsigned int ch_mask;
964 };
965
966 /**
967 * sdw_stream_config: Master or Slave stream configuration
968 *
969 * @frame_rate: Audio frame rate of the stream, in Hz
970 * @ch_count: Channel count of the stream
971 * @bps: Number of bits per audio sample
972 * @direction: Data direction
973 * @type: Stream type PCM or PDM
974 */
975 struct sdw_stream_config {
976 unsigned int frame_rate;
977 unsigned int ch_count;
978 unsigned int bps;
979 enum sdw_data_direction direction;
980 enum sdw_stream_type type;
981 };
982
983 /**
984 * sdw_stream_state: Stream states
985 *
986 * @SDW_STREAM_ALLOCATED: New stream allocated.
987 * @SDW_STREAM_CONFIGURED: Stream configured
988 * @SDW_STREAM_PREPARED: Stream prepared
989 * @SDW_STREAM_ENABLED: Stream enabled
990 * @SDW_STREAM_DISABLED: Stream disabled
991 * @SDW_STREAM_DEPREPARED: Stream de-prepared
992 * @SDW_STREAM_RELEASED: Stream released
993 */
994 enum sdw_stream_state {
995 SDW_STREAM_ALLOCATED = 0,
996 SDW_STREAM_CONFIGURED = 1,
997 SDW_STREAM_PREPARED = 2,
998 SDW_STREAM_ENABLED = 3,
999 SDW_STREAM_DISABLED = 4,
1000 SDW_STREAM_DEPREPARED = 5,
1001 SDW_STREAM_RELEASED = 6,
1002 };
1003
1004 /**
1005 * sdw_stream_params: Stream parameters
1006 *
1007 * @rate: Sampling frequency, in Hz
1008 * @ch_count: Number of channels
1009 * @bps: bits per channel sample
1010 */
1011 struct sdw_stream_params {
1012 unsigned int rate;
1013 unsigned int ch_count;
1014 unsigned int bps;
1015 };
1016
1017 /**
1018 * sdw_stream_runtime: Runtime stream parameters
1019 *
1020 * @name: SoundWire stream name
1021 * @params: Stream parameters
1022 * @state: Current state of the stream
1023 * @type: Stream type PCM or PDM
1024 * @master_list: List of Master runtime(s) in this stream.
1025 * master_list can contain only one m_rt per Master instance
1026 * for a stream
1027 * @m_rt_count: Count of Master runtime(s) in this stream
1028 */
1029 struct sdw_stream_runtime {
1030 const char *name;
1031 struct sdw_stream_params params;
1032 enum sdw_stream_state state;
1033 enum sdw_stream_type type;
1034 struct list_head master_list;
1035 int m_rt_count;
1036 };
1037
1038 struct sdw_stream_runtime *sdw_alloc_stream(const char *stream_name);
1039 void sdw_release_stream(struct sdw_stream_runtime *stream);
1040
1041 int sdw_compute_params(struct sdw_bus *bus);
1042
1043 int sdw_stream_add_master(struct sdw_bus *bus,
1044 struct sdw_stream_config *stream_config,
1045 struct sdw_port_config *port_config,
1046 unsigned int num_ports,
1047 struct sdw_stream_runtime *stream);
1048 int sdw_stream_remove_master(struct sdw_bus *bus,
1049 struct sdw_stream_runtime *stream);
1050 int sdw_startup_stream(void *sdw_substream);
1051 int sdw_prepare_stream(struct sdw_stream_runtime *stream);
1052 int sdw_enable_stream(struct sdw_stream_runtime *stream);
1053 int sdw_disable_stream(struct sdw_stream_runtime *stream);
1054 int sdw_deprepare_stream(struct sdw_stream_runtime *stream);
1055 void sdw_shutdown_stream(void *sdw_substream);
1056 int sdw_bus_prep_clk_stop(struct sdw_bus *bus);
1057 int sdw_bus_clk_stop(struct sdw_bus *bus);
1058 int sdw_bus_exit_clk_stop(struct sdw_bus *bus);
1059
1060 int sdw_compare_devid(struct sdw_slave *slave, struct sdw_slave_id id);
1061 void sdw_extract_slave_id(struct sdw_bus *bus, u64 addr, struct sdw_slave_id *id);
1062
1063 #if IS_ENABLED(CONFIG_SOUNDWIRE)
1064
1065 int sdw_stream_add_slave(struct sdw_slave *slave,
1066 struct sdw_stream_config *stream_config,
1067 struct sdw_port_config *port_config,
1068 unsigned int num_ports,
1069 struct sdw_stream_runtime *stream);
1070 int sdw_stream_remove_slave(struct sdw_slave *slave,
1071 struct sdw_stream_runtime *stream);
1072
1073 /* messaging and data APIs */
1074 int sdw_read(struct sdw_slave *slave, u32 addr);
1075 int sdw_write(struct sdw_slave *slave, u32 addr, u8 value);
1076 int sdw_write_no_pm(struct sdw_slave *slave, u32 addr, u8 value);
1077 int sdw_read_no_pm(struct sdw_slave *slave, u32 addr);
1078 int sdw_nread(struct sdw_slave *slave, u32 addr, size_t count, u8 *val);
1079 int sdw_nread_no_pm(struct sdw_slave *slave, u32 addr, size_t count, u8 *val);
1080 int sdw_nwrite(struct sdw_slave *slave, u32 addr, size_t count, const u8 *val);
1081 int sdw_nwrite_no_pm(struct sdw_slave *slave, u32 addr, size_t count, const u8 *val);
1082 int sdw_update(struct sdw_slave *slave, u32 addr, u8 mask, u8 val);
1083 int sdw_update_no_pm(struct sdw_slave *slave, u32 addr, u8 mask, u8 val);
1084
1085 #else
1086
sdw_stream_add_slave(struct sdw_slave * slave,struct sdw_stream_config * stream_config,struct sdw_port_config * port_config,unsigned int num_ports,struct sdw_stream_runtime * stream)1087 static inline int sdw_stream_add_slave(struct sdw_slave *slave,
1088 struct sdw_stream_config *stream_config,
1089 struct sdw_port_config *port_config,
1090 unsigned int num_ports,
1091 struct sdw_stream_runtime *stream)
1092 {
1093 WARN_ONCE(1, "SoundWire API is disabled");
1094 return -EINVAL;
1095 }
1096
sdw_stream_remove_slave(struct sdw_slave * slave,struct sdw_stream_runtime * stream)1097 static inline int sdw_stream_remove_slave(struct sdw_slave *slave,
1098 struct sdw_stream_runtime *stream)
1099 {
1100 WARN_ONCE(1, "SoundWire API is disabled");
1101 return -EINVAL;
1102 }
1103
1104 /* messaging and data APIs */
sdw_read(struct sdw_slave * slave,u32 addr)1105 static inline int sdw_read(struct sdw_slave *slave, u32 addr)
1106 {
1107 WARN_ONCE(1, "SoundWire API is disabled");
1108 return -EINVAL;
1109 }
1110
sdw_write(struct sdw_slave * slave,u32 addr,u8 value)1111 static inline int sdw_write(struct sdw_slave *slave, u32 addr, u8 value)
1112 {
1113 WARN_ONCE(1, "SoundWire API is disabled");
1114 return -EINVAL;
1115 }
1116
sdw_write_no_pm(struct sdw_slave * slave,u32 addr,u8 value)1117 static inline int sdw_write_no_pm(struct sdw_slave *slave, u32 addr, u8 value)
1118 {
1119 WARN_ONCE(1, "SoundWire API is disabled");
1120 return -EINVAL;
1121 }
1122
sdw_read_no_pm(struct sdw_slave * slave,u32 addr)1123 static inline int sdw_read_no_pm(struct sdw_slave *slave, u32 addr)
1124 {
1125 WARN_ONCE(1, "SoundWire API is disabled");
1126 return -EINVAL;
1127 }
1128
sdw_nread(struct sdw_slave * slave,u32 addr,size_t count,u8 * val)1129 static inline int sdw_nread(struct sdw_slave *slave, u32 addr, size_t count, u8 *val)
1130 {
1131 WARN_ONCE(1, "SoundWire API is disabled");
1132 return -EINVAL;
1133 }
1134
sdw_nread_no_pm(struct sdw_slave * slave,u32 addr,size_t count,u8 * val)1135 static inline int sdw_nread_no_pm(struct sdw_slave *slave, u32 addr, size_t count, u8 *val)
1136 {
1137 WARN_ONCE(1, "SoundWire API is disabled");
1138 return -EINVAL;
1139 }
1140
sdw_nwrite(struct sdw_slave * slave,u32 addr,size_t count,const u8 * val)1141 static inline int sdw_nwrite(struct sdw_slave *slave, u32 addr, size_t count, const u8 *val)
1142 {
1143 WARN_ONCE(1, "SoundWire API is disabled");
1144 return -EINVAL;
1145 }
1146
sdw_nwrite_no_pm(struct sdw_slave * slave,u32 addr,size_t count,const u8 * val)1147 static inline int sdw_nwrite_no_pm(struct sdw_slave *slave, u32 addr, size_t count, const u8 *val)
1148 {
1149 WARN_ONCE(1, "SoundWire API is disabled");
1150 return -EINVAL;
1151 }
1152
sdw_update(struct sdw_slave * slave,u32 addr,u8 mask,u8 val)1153 static inline int sdw_update(struct sdw_slave *slave, u32 addr, u8 mask, u8 val)
1154 {
1155 WARN_ONCE(1, "SoundWire API is disabled");
1156 return -EINVAL;
1157 }
1158
sdw_update_no_pm(struct sdw_slave * slave,u32 addr,u8 mask,u8 val)1159 static inline int sdw_update_no_pm(struct sdw_slave *slave, u32 addr, u8 mask, u8 val)
1160 {
1161 WARN_ONCE(1, "SoundWire API is disabled");
1162 return -EINVAL;
1163 }
1164
1165 #endif /* CONFIG_SOUNDWIRE */
1166
1167 #endif /* __SOUNDWIRE_H */
1168