xref: /openbmc/qemu/hw/sd/sdhci-internal.h (revision c0a55a0c)
1 /*
2  * SD Association Host Standard Specification v2.0 controller emulation
3  *
4  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5  * Mitsyanko Igor <i.mitsyanko@samsung.com>
6  * Peter A.G. Crosthwaite <peter.crosthwaite@petalogix.com>
7  *
8  * Based on MMC controller for Samsung S5PC1xx-based board emulation
9  * by Alexey Merkulov and Vladimir Monakhov.
10  *
11  * This program is free software; you can redistribute it and/or modify it
12  * under the terms of the GNU General Public License as published by the
13  * Free Software Foundation; either version 2 of the License, or (at your
14  * option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
19  * See the GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License along
22  * with this program; if not, see <http://www.gnu.org/licenses/>.
23  */
24 #ifndef SDHCI_INTERNAL_H
25 #define SDHCI_INTERNAL_H
26 
27 #include "hw/registerfields.h"
28 
29 /* R/W SDMA System Address register 0x0 */
30 #define SDHC_SYSAD                     0x00
31 
32 /* R/W Host DMA Buffer Boundary and Transfer Block Size Register 0x0 */
33 #define SDHC_BLKSIZE                   0x04
34 
35 /* R/W Blocks count for current transfer 0x0 */
36 #define SDHC_BLKCNT                    0x06
37 
38 /* R/W Command Argument Register 0x0 */
39 #define SDHC_ARGUMENT                  0x08
40 
41 /* R/W Transfer Mode Setting Register 0x0 */
42 #define SDHC_TRNMOD                    0x0C
43 #define SDHC_TRNS_DMA                  0x0001
44 #define SDHC_TRNS_BLK_CNT_EN           0x0002
45 #define SDHC_TRNS_ACMD12               0x0004
46 #define SDHC_TRNS_ACMD23               0x0008 /* since v3 */
47 #define SDHC_TRNS_READ                 0x0010
48 #define SDHC_TRNS_MULTI                0x0020
49 #define SDHC_TRNMOD_MASK               0x0037
50 
51 /* R/W Command Register 0x0 */
52 #define SDHC_CMDREG                    0x0E
53 #define SDHC_CMD_RSP_WITH_BUSY         (3 << 0)
54 #define SDHC_CMD_DATA_PRESENT          (1 << 5)
55 #define SDHC_CMD_SUSPEND               (1 << 6)
56 #define SDHC_CMD_RESUME                (1 << 7)
57 #define SDHC_CMD_ABORT                 ((1 << 6)|(1 << 7))
58 #define SDHC_CMD_TYPE_MASK             ((1 << 6)|(1 << 7))
59 #define SDHC_COMMAND_TYPE(x)           ((x) & SDHC_CMD_TYPE_MASK)
60 
61 /* ROC Response Register 0 0x0 */
62 #define SDHC_RSPREG0                   0x10
63 /* ROC Response Register 1 0x0 */
64 #define SDHC_RSPREG1                   0x14
65 /* ROC Response Register 2 0x0 */
66 #define SDHC_RSPREG2                   0x18
67 /* ROC Response Register 3 0x0 */
68 #define SDHC_RSPREG3                   0x1C
69 
70 /* R/W Buffer Data Register 0x0 */
71 #define SDHC_BDATA                     0x20
72 
73 /* R/ROC Present State Register 0x000A0000 */
74 #define SDHC_PRNSTS                    0x24
75 #define SDHC_CMD_INHIBIT               0x00000001
76 #define SDHC_DATA_INHIBIT              0x00000002
77 #define SDHC_DAT_LINE_ACTIVE           0x00000004
78 #define SDHC_IMX_CLOCK_GATE_OFF        0x00000080
79 #define SDHC_DOING_WRITE               0x00000100
80 #define SDHC_DOING_READ                0x00000200
81 #define SDHC_SPACE_AVAILABLE           0x00000400
82 #define SDHC_DATA_AVAILABLE            0x00000800
83 #define SDHC_CARD_PRESENT              0x00010000
84 #define SDHC_CARD_DETECT               0x00040000
85 #define SDHC_WRITE_PROTECT             0x00080000
86 FIELD(SDHC_PRNSTS, DAT_LVL,            20, 4);
87 FIELD(SDHC_PRNSTS, CMD_LVL,            24, 1);
88 #define TRANSFERRING_DATA(x)           \
89     ((x) & (SDHC_DOING_READ | SDHC_DOING_WRITE))
90 
91 /* R/W Host control Register 0x0 */
92 #define SDHC_HOSTCTL                   0x28
93 #define SDHC_CTRL_LED                  0x01
94 #define SDHC_CTRL_DATATRANSFERWIDTH    0x02 /* SD mode only */
95 #define SDHC_CTRL_HIGH_SPEED           0x04
96 #define SDHC_CTRL_DMA_CHECK_MASK       0x18
97 #define SDHC_CTRL_SDMA                 0x00
98 #define SDHC_CTRL_ADMA1_32             0x08 /* NOT ALLOWED since v2 */
99 #define SDHC_CTRL_ADMA2_32             0x10
100 #define SDHC_CTRL_ADMA2_64             0x18
101 #define SDHC_DMA_TYPE(x)               ((x) & SDHC_CTRL_DMA_CHECK_MASK)
102 #define SDHC_CTRL_4BITBUS              0x02
103 #define SDHC_CTRL_8BITBUS              0x20
104 #define SDHC_CTRL_CDTEST_INS           0x40
105 #define SDHC_CTRL_CDTEST_EN            0x80
106 
107 /* R/W Power Control Register 0x0 */
108 #define SDHC_PWRCON                    0x29
109 #define SDHC_POWER_ON                  (1 << 0)
110 FIELD(SDHC_PWRCON, BUS_VOLTAGE,        1, 3);
111 
112 /* R/W Block Gap Control Register 0x0 */
113 #define SDHC_BLKGAP                    0x2A
114 #define SDHC_STOP_AT_GAP_REQ           0x01
115 #define SDHC_CONTINUE_REQ              0x02
116 
117 /* R/W WakeUp Control Register 0x0 */
118 #define SDHC_WAKCON                    0x2B
119 #define SDHC_WKUP_ON_INS               (1 << 1)
120 #define SDHC_WKUP_ON_RMV               (1 << 2)
121 
122 /* CLKCON */
123 #define SDHC_CLKCON                    0x2C
124 #define SDHC_CLOCK_INT_STABLE          0x0002
125 #define SDHC_CLOCK_INT_EN              0x0001
126 #define SDHC_CLOCK_SDCLK_EN            (1 << 2)
127 #define SDHC_CLOCK_CHK_MASK            0x0007
128 #define SDHC_CLOCK_IS_ON(x)            \
129     (((x) & SDHC_CLOCK_CHK_MASK) == SDHC_CLOCK_CHK_MASK)
130 
131 /* R/W Timeout Control Register 0x0 */
132 #define SDHC_TIMEOUTCON                0x2E
133 FIELD(SDHC_TIMEOUTCON, COUNTER,        0, 4);
134 
135 /* R/W Software Reset Register 0x0 */
136 #define SDHC_SWRST                     0x2F
137 #define SDHC_RESET_ALL                 0x01
138 #define SDHC_RESET_CMD                 0x02
139 #define SDHC_RESET_DATA                0x04
140 
141 /* ROC/RW1C Normal Interrupt Status Register 0x0 */
142 #define SDHC_NORINTSTS                 0x30
143 #define SDHC_NIS_ERR                   0x8000
144 #define SDHC_NIS_CMDCMP                0x0001
145 #define SDHC_NIS_TRSCMP                0x0002
146 #define SDHC_NIS_BLKGAP                0x0004
147 #define SDHC_NIS_DMA                   0x0008
148 #define SDHC_NIS_WBUFRDY               0x0010
149 #define SDHC_NIS_RBUFRDY               0x0020
150 #define SDHC_NIS_INSERT                0x0040
151 #define SDHC_NIS_REMOVE                0x0080
152 #define SDHC_NIS_CARDINT               0x0100
153 
154 /* ROC/RW1C Error Interrupt Status Register 0x0 */
155 #define SDHC_ERRINTSTS                 0x32
156 #define SDHC_EIS_CMDTIMEOUT            0x0001
157 #define SDHC_EIS_BLKGAP                0x0004
158 #define SDHC_EIS_CMDIDX                0x0008
159 #define SDHC_EIS_CMD12ERR              0x0100
160 #define SDHC_EIS_ADMAERR               0x0200
161 
162 /* R/W Normal Interrupt Status Enable Register 0x0 */
163 #define SDHC_NORINTSTSEN               0x34
164 #define SDHC_NISEN_CMDCMP              0x0001
165 #define SDHC_NISEN_TRSCMP              0x0002
166 #define SDHC_NISEN_DMA                 0x0008
167 #define SDHC_NISEN_WBUFRDY             0x0010
168 #define SDHC_NISEN_RBUFRDY             0x0020
169 #define SDHC_NISEN_INSERT              0x0040
170 #define SDHC_NISEN_REMOVE              0x0080
171 #define SDHC_NISEN_CARDINT             0x0100
172 
173 /* R/W Error Interrupt Status Enable Register 0x0 */
174 #define SDHC_ERRINTSTSEN               0x36
175 #define SDHC_EISEN_CMDTIMEOUT          0x0001
176 #define SDHC_EISEN_BLKGAP              0x0004
177 #define SDHC_EISEN_CMDIDX              0x0008
178 #define SDHC_EISEN_ADMAERR             0x0200
179 
180 /* R/W Normal Interrupt Signal Enable Register 0x0 */
181 #define SDHC_NORINTSIGEN               0x38
182 #define SDHC_NORINTSIG_INSERT          (1 << 6)
183 #define SDHC_NORINTSIG_REMOVE          (1 << 7)
184 
185 /* R/W Error Interrupt Signal Enable Register 0x0 */
186 #define SDHC_ERRINTSIGEN               0x3A
187 
188 /* ROC Auto CMD12 error status register 0x0 */
189 #define SDHC_ACMD12ERRSTS              0x3C
190 FIELD(SDHC_ACMD12ERRSTS, TIMEOUT_ERR,  1, 1);
191 FIELD(SDHC_ACMD12ERRSTS, CRC_ERR,      2, 1);
192 FIELD(SDHC_ACMD12ERRSTS, INDEX_ERR,    4, 1);
193 
194 /* Host Control Register 2 (since v3) */
195 #define SDHC_HOSTCTL2                  0x3E
196 FIELD(SDHC_HOSTCTL2, UHS_MODE_SEL,     0, 3);
197 FIELD(SDHC_HOSTCTL2, V18_ENA,          3, 1); /* UHS-I only */
198 FIELD(SDHC_HOSTCTL2, DRIVER_STRENGTH,  4, 2); /* UHS-I only */
199 FIELD(SDHC_HOSTCTL2, EXECUTE_TUNING,   6, 1); /* UHS-I only */
200 FIELD(SDHC_HOSTCTL2, SAMPLING_CLKSEL,  7, 1); /* UHS-I only */
201 FIELD(SDHC_HOSTCTL2, UHS_II_ENA,       8, 1); /* since v4 */
202 FIELD(SDHC_HOSTCTL2, ADMA2_LENGTH,    10, 1); /* since v4 */
203 FIELD(SDHC_HOSTCTL2, CMD23_ENA,       11, 1); /* since v4 */
204 FIELD(SDHC_HOSTCTL2, VERSION4,        12, 1); /* since v4 */
205 FIELD(SDHC_HOSTCTL2, ASYNC_INT,       14, 1);
206 FIELD(SDHC_HOSTCTL2, PRESET_ENA,      15, 1);
207 
208 /* HWInit Capabilities Register 0x05E80080 */
209 #define SDHC_CAPAB                     0x40
210 FIELD(SDHC_CAPAB, TOCLKFREQ,           0, 6);
211 FIELD(SDHC_CAPAB, TOUNIT,              7, 1);
212 FIELD(SDHC_CAPAB, BASECLKFREQ,         8, 8);
213 FIELD(SDHC_CAPAB, MAXBLOCKLENGTH,     16, 2);
214 FIELD(SDHC_CAPAB, EMBEDDED_8BIT,      18, 1); /* since v3 */
215 FIELD(SDHC_CAPAB, ADMA2,              19, 1); /* since v2 */
216 FIELD(SDHC_CAPAB, ADMA1,              20, 1); /* v1 only? */
217 FIELD(SDHC_CAPAB, HIGHSPEED,          21, 1);
218 FIELD(SDHC_CAPAB, SDMA,               22, 1);
219 FIELD(SDHC_CAPAB, SUSPRESUME,         23, 1);
220 FIELD(SDHC_CAPAB, V33,                24, 1);
221 FIELD(SDHC_CAPAB, V30,                25, 1);
222 FIELD(SDHC_CAPAB, V18,                26, 1);
223 FIELD(SDHC_CAPAB, BUS64BIT_V4,        27, 1); /* since v4.10 */
224 FIELD(SDHC_CAPAB, BUS64BIT,           28, 1); /* since v2 */
225 FIELD(SDHC_CAPAB, ASYNC_INT,          29, 1); /* since v3 */
226 FIELD(SDHC_CAPAB, SLOT_TYPE,          30, 2); /* since v3 */
227 FIELD(SDHC_CAPAB, BUS_SPEED,          32, 3); /* since v3 */
228 FIELD(SDHC_CAPAB, UHS_II,             35, 8); /* since v4.20 */
229 FIELD(SDHC_CAPAB, DRIVER_STRENGTH,    36, 3); /* since v3 */
230 FIELD(SDHC_CAPAB, DRIVER_TYPE_A,      36, 1); /* since v3 */
231 FIELD(SDHC_CAPAB, DRIVER_TYPE_C,      37, 1); /* since v3 */
232 FIELD(SDHC_CAPAB, DRIVER_TYPE_D,      38, 1); /* since v3 */
233 FIELD(SDHC_CAPAB, TIMER_RETUNING,     40, 4); /* since v3 */
234 FIELD(SDHC_CAPAB, SDR50_TUNING,       45, 1); /* since v3 */
235 FIELD(SDHC_CAPAB, RETUNING_MODE,      46, 2); /* since v3 */
236 FIELD(SDHC_CAPAB, CLOCK_MULT,         48, 8); /* since v3 */
237 FIELD(SDHC_CAPAB, ADMA3,              59, 1); /* since v4.20 */
238 FIELD(SDHC_CAPAB, V18_VDD2,           60, 1); /* since v4.20 */
239 
240 /* HWInit Maximum Current Capabilities Register 0x0 */
241 #define SDHC_MAXCURR                   0x48
242 FIELD(SDHC_MAXCURR, V33_VDD1,          0, 8);
243 FIELD(SDHC_MAXCURR, V30_VDD1,          8, 8);
244 FIELD(SDHC_MAXCURR, V18_VDD1,         16, 8);
245 FIELD(SDHC_MAXCURR, V18_VDD2,         32, 8); /* since v4.20 */
246 
247 /* W Force Event Auto CMD12 Error Interrupt Register 0x0000 */
248 #define SDHC_FEAER                     0x50
249 /* W Force Event Error Interrupt Register Error Interrupt 0x0000 */
250 #define SDHC_FEERR                     0x52
251 
252 /* R/W ADMA Error Status Register 0x00 */
253 #define SDHC_ADMAERR                   0x54
254 #define SDHC_ADMAERR_LENGTH_MISMATCH   (1 << 2)
255 #define SDHC_ADMAERR_STATE_ST_STOP     (0 << 0)
256 #define SDHC_ADMAERR_STATE_ST_FDS      (1 << 0)
257 #define SDHC_ADMAERR_STATE_ST_TFR      (3 << 0)
258 #define SDHC_ADMAERR_STATE_MASK        (3 << 0)
259 
260 /* R/W ADMA System Address Register 0x00 */
261 #define SDHC_ADMASYSADDR               0x58
262 #define SDHC_ADMA_ATTR_SET_LEN         (1 << 4)
263 #define SDHC_ADMA_ATTR_ACT_TRAN        (1 << 5)
264 #define SDHC_ADMA_ATTR_ACT_LINK        (3 << 4)
265 #define SDHC_ADMA_ATTR_INT             (1 << 2)
266 #define SDHC_ADMA_ATTR_END             (1 << 1)
267 #define SDHC_ADMA_ATTR_VALID           (1 << 0)
268 #define SDHC_ADMA_ATTR_ACT_MASK        ((1 << 4)|(1 << 5))
269 
270 /* Slot interrupt status */
271 #define SDHC_SLOT_INT_STATUS            0xFC
272 
273 /* HWInit Host Controller Version Register */
274 #define SDHC_HCVER                      0xFE
275 #define SDHC_HCVER_VENDOR               0x24
276 
277 #define SDHC_REGISTERS_MAP_SIZE         0x100
278 #define SDHC_INSERTION_DELAY            (NANOSECONDS_PER_SECOND)
279 #define SDHC_TRANSFER_DELAY             100
280 #define SDHC_ADMA_DESCS_PER_DELAY       5
281 #define SDHC_CMD_RESPONSE               (3 << 0)
282 
283 enum {
284     sdhc_not_stopped = 0, /* normal SDHC state */
285     sdhc_gap_read   = 1,  /* SDHC stopped at block gap during read operation */
286     sdhc_gap_write  = 2   /* SDHC stopped at block gap during write operation */
287 };
288 
289 extern const VMStateDescription sdhci_vmstate;
290 
291 /*
292  * Default SD/MMC host controller features information, which will be
293  * presented in CAPABILITIES register of generic SD host controller at reset.
294  *
295  * support:
296  * - 3.3v and 1.8v voltages
297  * - SDMA/ADMA1/ADMA2
298  * - high-speed
299  * max host controller R/W buffers size: 512B
300  * max clock frequency for SDclock: 52 MHz
301  * timeout clock frequency: 52 MHz
302  *
303  * does not support:
304  * - 3.0v voltage
305  * - 64-bit system bus
306  * - suspend/resume
307  */
308 #define SDHC_CAPAB_REG_DEFAULT 0x057834b4
309 
310 #define DEFINE_SDHCI_COMMON_PROPERTIES(_state) \
311     DEFINE_PROP_UINT8("endianness", _state, endianness, DEVICE_LITTLE_ENDIAN), \
312     DEFINE_PROP_UINT8("sd-spec-version", _state, sd_spec_version, 2), \
313     DEFINE_PROP_UINT8("uhs", _state, uhs_mode, UHS_NOT_SUPPORTED), \
314     DEFINE_PROP_UINT8("vendor", _state, vendor, SDHCI_VENDOR_NONE), \
315     \
316     /* Capabilities registers provide information on supported
317      * features of this specific host controller implementation */ \
318     DEFINE_PROP_UINT64("capareg", _state, capareg, SDHC_CAPAB_REG_DEFAULT), \
319     DEFINE_PROP_UINT64("maxcurr", _state, maxcurr, 0)
320 
321 void sdhci_initfn(SDHCIState *s);
322 void sdhci_uninitfn(SDHCIState *s);
323 void sdhci_common_realize(SDHCIState *s, Error **errp);
324 void sdhci_common_unrealize(SDHCIState *s);
325 void sdhci_common_class_init(ObjectClass *klass, void *data);
326 
327 #endif
328