xref: /openbmc/linux/drivers/tty/serial/sh-sci.h (revision d61ae331)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 #include <linux/bitops.h>
3 #include <linux/serial_core.h>
4 #include <linux/io.h>
5 
6 #define SCI_MAJOR		204
7 #define SCI_MINOR_START		8
8 
9 
10 /*
11  * SCI register subset common for all port types.
12  * Not all registers will exist on all parts.
13  */
14 enum {
15 	SCSMR,				/* Serial Mode Register */
16 	SCBRR,				/* Bit Rate Register */
17 	SCSCR,				/* Serial Control Register */
18 	SCxSR,				/* Serial Status Register */
19 	SCFCR,				/* FIFO Control Register */
20 	SCFDR,				/* FIFO Data Count Register */
21 	SCxTDR,				/* Transmit (FIFO) Data Register */
22 	SCxRDR,				/* Receive (FIFO) Data Register */
23 	SCLSR,				/* Line Status Register */
24 	SCTFDR,				/* Transmit FIFO Data Count Register */
25 	SCRFDR,				/* Receive FIFO Data Count Register */
26 	SCSPTR,				/* Serial Port Register */
27 	HSSRR,				/* Sampling Rate Register */
28 	SCPCR,				/* Serial Port Control Register */
29 	SCPDR,				/* Serial Port Data Register */
30 	SCDL,				/* BRG Frequency Division Register */
31 	SCCKS,				/* BRG Clock Select Register */
32 	HSRTRGR,			/* Rx FIFO Data Count Trigger Register */
33 	HSTTRGR,			/* Tx FIFO Data Count Trigger Register */
34 	SEMR,				/* Serial extended mode register */
35 
36 	SCIx_NR_REGS,
37 };
38 
39 
40 /* SCSMR (Serial Mode Register) */
41 #define SCSMR_C_A	BIT(7)	/* Communication Mode */
42 #define SCSMR_CSYNC	BIT(7)	/*   - Clocked synchronous mode */
43 #define SCSMR_ASYNC	0	/*   - Asynchronous mode */
44 #define SCSMR_CHR	BIT(6)	/* 7-bit Character Length */
45 #define SCSMR_PE	BIT(5)	/* Parity Enable */
46 #define SCSMR_ODD	BIT(4)	/* Odd Parity */
47 #define SCSMR_STOP	BIT(3)	/* Stop Bit Length */
48 #define SCSMR_CKS	0x0003	/* Clock Select */
49 
50 /* Serial Mode Register, SCIFA/SCIFB only bits */
51 #define SCSMR_CKEDG	BIT(12)	/* Transmit/Receive Clock Edge Select */
52 #define SCSMR_SRC_MASK	0x0700	/* Sampling Control */
53 #define SCSMR_SRC_16	0x0000	/* Sampling rate 1/16 */
54 #define SCSMR_SRC_5	0x0100	/* Sampling rate 1/5 */
55 #define SCSMR_SRC_7	0x0200	/* Sampling rate 1/7 */
56 #define SCSMR_SRC_11	0x0300	/* Sampling rate 1/11 */
57 #define SCSMR_SRC_13	0x0400	/* Sampling rate 1/13 */
58 #define SCSMR_SRC_17	0x0500	/* Sampling rate 1/17 */
59 #define SCSMR_SRC_19	0x0600	/* Sampling rate 1/19 */
60 #define SCSMR_SRC_27	0x0700	/* Sampling rate 1/27 */
61 
62 /* Serial Control Register, SCI only bits */
63 #define SCSCR_TEIE	BIT(2)  /* Transmit End Interrupt Enable */
64 
65 /* Serial Control Register, SCIFA/SCIFB only bits */
66 #define SCSCR_TDRQE	BIT(15)	/* Tx Data Transfer Request Enable */
67 #define SCSCR_RDRQE	BIT(14)	/* Rx Data Transfer Request Enable */
68 
69 /* Serial Control Register, HSCIF-only bits */
70 #define HSSCR_TOT_SHIFT	14
71 
72 /* SCxSR (Serial Status Register) on SCI */
73 #define SCI_TDRE	BIT(7)	/* Transmit Data Register Empty */
74 #define SCI_RDRF	BIT(6)	/* Receive Data Register Full */
75 #define SCI_ORER	BIT(5)	/* Overrun Error */
76 #define SCI_FER		BIT(4)	/* Framing Error */
77 #define SCI_PER		BIT(3)	/* Parity Error */
78 #define SCI_TEND	BIT(2)	/* Transmit End */
79 #define SCI_RESERVED	0x03	/* All reserved bits */
80 
81 #define SCI_DEFAULT_ERROR_MASK (SCI_PER | SCI_FER)
82 
83 #define SCI_RDxF_CLEAR	(u32)(~(SCI_RESERVED | SCI_RDRF))
84 #define SCI_ERROR_CLEAR	(u32)(~(SCI_RESERVED | SCI_PER | SCI_FER | SCI_ORER))
85 #define SCI_TDxE_CLEAR	(u32)(~(SCI_RESERVED | SCI_TEND | SCI_TDRE))
86 #define SCI_BREAK_CLEAR	(u32)(~(SCI_RESERVED | SCI_PER | SCI_FER | SCI_ORER))
87 
88 /* SCxSR (Serial Status Register) on SCIF, SCIFA, SCIFB, HSCIF */
89 #define SCIF_ER		BIT(7)	/* Receive Error */
90 #define SCIF_TEND	BIT(6)	/* Transmission End */
91 #define SCIF_TDFE	BIT(5)	/* Transmit FIFO Data Empty */
92 #define SCIF_BRK	BIT(4)	/* Break Detect */
93 #define SCIF_FER	BIT(3)	/* Framing Error */
94 #define SCIF_PER	BIT(2)	/* Parity Error */
95 #define SCIF_RDF	BIT(1)	/* Receive FIFO Data Full */
96 #define SCIF_DR		BIT(0)	/* Receive Data Ready */
97 /* SCIF only (optional) */
98 #define SCIF_PERC	0xf000	/* Number of Parity Errors */
99 #define SCIF_FERC	0x0f00	/* Number of Framing Errors */
100 /*SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 only */
101 #define SCIFA_ORER	BIT(9)	/* Overrun Error */
102 
103 #define SCIF_DEFAULT_ERROR_MASK (SCIF_PER | SCIF_FER | SCIF_BRK | SCIF_ER)
104 
105 #define SCIF_RDxF_CLEAR		(u32)(~(SCIF_DR | SCIF_RDF))
106 #define SCIF_ERROR_CLEAR	(u32)(~(SCIF_PER | SCIF_FER | SCIF_ER))
107 #define SCIF_TDxE_CLEAR		(u32)(~(SCIF_TDFE))
108 #define SCIF_BREAK_CLEAR	(u32)(~(SCIF_PER | SCIF_FER | SCIF_BRK))
109 
110 /* SCFCR (FIFO Control Register) */
111 #define SCFCR_RTRG1	BIT(7)	/* Receive FIFO Data Count Trigger */
112 #define SCFCR_RTRG0	BIT(6)
113 #define SCFCR_TTRG1	BIT(5)	/* Transmit FIFO Data Count Trigger */
114 #define SCFCR_TTRG0	BIT(4)
115 #define SCFCR_MCE	BIT(3)	/* Modem Control Enable */
116 #define SCFCR_TFRST	BIT(2)	/* Transmit FIFO Data Register Reset */
117 #define SCFCR_RFRST	BIT(1)	/* Receive FIFO Data Register Reset */
118 #define SCFCR_LOOP	BIT(0)	/* Loopback Test */
119 
120 /* SCLSR (Line Status Register) on (H)SCIF */
121 #define SCLSR_TO	BIT(2)	/* Timeout */
122 #define SCLSR_ORER	BIT(0)	/* Overrun Error */
123 
124 /* SCSPTR (Serial Port Register), optional */
125 #define SCSPTR_RTSIO	BIT(7)	/* Serial Port RTS# Pin Input/Output */
126 #define SCSPTR_RTSDT	BIT(6)	/* Serial Port RTS# Pin Data */
127 #define SCSPTR_CTSIO	BIT(5)	/* Serial Port CTS# Pin Input/Output */
128 #define SCSPTR_CTSDT	BIT(4)	/* Serial Port CTS# Pin Data */
129 #define SCSPTR_SCKIO	BIT(3)	/* Serial Port Clock Pin Input/Output */
130 #define SCSPTR_SCKDT	BIT(2)	/* Serial Port Clock Pin Data */
131 #define SCSPTR_SPB2IO	BIT(1)	/* Serial Port Break Input/Output */
132 #define SCSPTR_SPB2DT	BIT(0)	/* Serial Port Break Data */
133 
134 /* HSSRR HSCIF */
135 #define HSCIF_SRE	BIT(15)	/* Sampling Rate Register Enable */
136 #define HSCIF_SRDE	BIT(14) /* Sampling Point Register Enable */
137 
138 #define HSCIF_SRHP_SHIFT	8
139 #define HSCIF_SRHP_MASK		0x0f00
140 
141 /* SCPCR (Serial Port Control Register), SCIFA/SCIFB only */
142 #define SCPCR_RTSC	BIT(4)	/* Serial Port RTS# Pin / Output Pin */
143 #define SCPCR_CTSC	BIT(3)	/* Serial Port CTS# Pin / Input Pin */
144 #define SCPCR_SCKC	BIT(2)	/* Serial Port SCK Pin / Output Pin */
145 #define SCPCR_RXDC	BIT(1)	/* Serial Port RXD Pin / Input Pin */
146 #define SCPCR_TXDC	BIT(0)	/* Serial Port TXD Pin / Output Pin */
147 
148 /* SCPDR (Serial Port Data Register), SCIFA/SCIFB only */
149 #define SCPDR_RTSD	BIT(4)	/* Serial Port RTS# Output Pin Data */
150 #define SCPDR_CTSD	BIT(3)	/* Serial Port CTS# Input Pin Data */
151 #define SCPDR_SCKD	BIT(2)	/* Serial Port SCK Output Pin Data */
152 #define SCPDR_RXDD	BIT(1)	/* Serial Port RXD Input Pin Data */
153 #define SCPDR_TXDD	BIT(0)	/* Serial Port TXD Output Pin Data */
154 
155 /*
156  * BRG Clock Select Register (Some SCIF and HSCIF)
157  * The Baud Rate Generator for external clock can provide a clock source for
158  * the sampling clock. It outputs either its frequency divided clock, or the
159  * (undivided) (H)SCK external clock.
160  */
161 #define SCCKS_CKS	BIT(15)	/* Select (H)SCK (1) or divided SC_CLK (0) */
162 #define SCCKS_XIN	BIT(14)	/* SC_CLK uses bus clock (1) or SCIF_CLK (0) */
163 
164 #define SCxSR_TEND(port)	(((port)->type == PORT_SCI) ? SCI_TEND   : SCIF_TEND)
165 #define SCxSR_RDxF(port)	(((port)->type == PORT_SCI) ? SCI_RDRF   : SCIF_DR | SCIF_RDF)
166 #define SCxSR_TDxE(port)	(((port)->type == PORT_SCI) ? SCI_TDRE   : SCIF_TDFE)
167 #define SCxSR_FER(port)		(((port)->type == PORT_SCI) ? SCI_FER    : SCIF_FER)
168 #define SCxSR_PER(port)		(((port)->type == PORT_SCI) ? SCI_PER    : SCIF_PER)
169 #define SCxSR_BRK(port)		(((port)->type == PORT_SCI) ? 0x00       : SCIF_BRK)
170 
171 #define SCxSR_ERRORS(port)	(to_sci_port(port)->params->error_mask)
172 
173 #define SCxSR_RDxF_CLEAR(port) \
174 	(((port)->type == PORT_SCI) ? SCI_RDxF_CLEAR : SCIF_RDxF_CLEAR)
175 #define SCxSR_ERROR_CLEAR(port) \
176 	(to_sci_port(port)->params->error_clear)
177 #define SCxSR_TDxE_CLEAR(port) \
178 	(((port)->type == PORT_SCI) ? SCI_TDxE_CLEAR : SCIF_TDxE_CLEAR)
179 #define SCxSR_BREAK_CLEAR(port) \
180 	(((port)->type == PORT_SCI) ? SCI_BREAK_CLEAR : SCIF_BREAK_CLEAR)
181