xref: /openbmc/linux/drivers/scsi/pm8001/pm80xx_hwi.h (revision 54543295)
1 /*
2  * PMC-Sierra SPCv/ve 8088/8089 SAS/SATA based host adapters driver
3  *
4  * Copyright (c) 2008-2009 USI Co., Ltd.
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *	notice, this list of conditions, and the following disclaimer,
12  *	without modification.
13  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14  *	substantially similar to the "NO WARRANTY" disclaimer below
15  *	("Disclaimer") and any redistribution must be conditioned upon
16  *	including a substantially similar Disclaimer requirement for further
17  *	binary redistribution.
18  * 3. Neither the names of the above-listed copyright holders nor the names
19  *	of any contributors may be used to endorse or promote products derived
20  *	from this software without specific prior written permission.
21  *
22  * Alternatively, this software may be distributed under the terms of the
23  * GNU General Public License ("GPL") version 2 as published by the Free
24  * Software Foundation.
25  *
26  * NO WARRANTY
27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37  * POSSIBILITY OF SUCH DAMAGES.
38  *
39  */
40 
41 #ifndef _PMC8001_REG_H_
42 #define _PMC8001_REG_H_
43 
44 #include <linux/types.h>
45 #include <scsi/libsas.h>
46 
47 /* for Request Opcode of IOMB */
48 #define OPC_INB_ECHO				1	/* 0x000 */
49 #define OPC_INB_PHYSTART			4	/* 0x004 */
50 #define OPC_INB_PHYSTOP				5	/* 0x005 */
51 #define OPC_INB_SSPINIIOSTART			6	/* 0x006 */
52 #define OPC_INB_SSPINITMSTART			7	/* 0x007 */
53 /* 0x8 RESV IN SPCv */
54 #define OPC_INB_RSVD				8	/* 0x008 */
55 #define OPC_INB_DEV_HANDLE_ACCEPT		9	/* 0x009 */
56 #define OPC_INB_SSPTGTIOSTART			10	/* 0x00A */
57 #define OPC_INB_SSPTGTRSPSTART			11	/* 0x00B */
58 /* 0xC, 0xD, 0xE removed in SPCv */
59 #define OPC_INB_SSP_ABORT			15	/* 0x00F */
60 #define OPC_INB_DEREG_DEV_HANDLE		16	/* 0x010 */
61 #define OPC_INB_GET_DEV_HANDLE			17	/* 0x011 */
62 #define OPC_INB_SMP_REQUEST			18	/* 0x012 */
63 /* 0x13 SMP_RESPONSE is removed in SPCv */
64 #define OPC_INB_SMP_ABORT			20	/* 0x014 */
65 /* 0x16 RESV IN SPCv */
66 #define OPC_INB_RSVD1				22	/* 0x016 */
67 #define OPC_INB_SATA_HOST_OPSTART		23	/* 0x017 */
68 #define OPC_INB_SATA_ABORT			24	/* 0x018 */
69 #define OPC_INB_LOCAL_PHY_CONTROL		25	/* 0x019 */
70 /* 0x1A RESV IN SPCv */
71 #define OPC_INB_RSVD2				26	/* 0x01A */
72 #define OPC_INB_FW_FLASH_UPDATE			32	/* 0x020 */
73 #define OPC_INB_GPIO				34	/* 0x022 */
74 #define OPC_INB_SAS_DIAG_MODE_START_END		35	/* 0x023 */
75 #define OPC_INB_SAS_DIAG_EXECUTE		36	/* 0x024 */
76 /* 0x25 RESV IN SPCv */
77 #define OPC_INB_RSVD3				37	/* 0x025 */
78 #define OPC_INB_GET_TIME_STAMP			38	/* 0x026 */
79 #define OPC_INB_PORT_CONTROL			39	/* 0x027 */
80 #define OPC_INB_GET_NVMD_DATA			40	/* 0x028 */
81 #define OPC_INB_SET_NVMD_DATA			41	/* 0x029 */
82 #define OPC_INB_SET_DEVICE_STATE		42	/* 0x02A */
83 #define OPC_INB_GET_DEVICE_STATE		43	/* 0x02B */
84 #define OPC_INB_SET_DEV_INFO			44	/* 0x02C */
85 /* 0x2D RESV IN SPCv */
86 #define OPC_INB_RSVD4				45	/* 0x02D */
87 #define OPC_INB_SGPIO_REGISTER			46	/* 0x02E */
88 #define OPC_INB_PCIE_DIAG_EXEC			47	/* 0x02F */
89 #define OPC_INB_SET_CONTROLLER_CONFIG		48	/* 0x030 */
90 #define OPC_INB_GET_CONTROLLER_CONFIG		49	/* 0x031 */
91 #define OPC_INB_REG_DEV				50	/* 0x032 */
92 #define OPC_INB_SAS_HW_EVENT_ACK		51	/* 0x033 */
93 #define OPC_INB_GET_DEVICE_INFO			52	/* 0x034 */
94 #define OPC_INB_GET_PHY_PROFILE			53	/* 0x035 */
95 #define OPC_INB_FLASH_OP_EXT			54	/* 0x036 */
96 #define OPC_INB_SET_PHY_PROFILE			55	/* 0x037 */
97 #define OPC_INB_KEK_MANAGEMENT			256	/* 0x100 */
98 #define OPC_INB_DEK_MANAGEMENT			257	/* 0x101 */
99 #define OPC_INB_SSP_INI_DIF_ENC_IO		258	/* 0x102 */
100 #define OPC_INB_SATA_DIF_ENC_IO			259	/* 0x103 */
101 
102 /* for Response Opcode of IOMB */
103 #define OPC_OUB_ECHO					1	/* 0x001 */
104 #define OPC_OUB_RSVD					4	/* 0x004 */
105 #define OPC_OUB_SSP_COMP				5	/* 0x005 */
106 #define OPC_OUB_SMP_COMP				6	/* 0x006 */
107 #define OPC_OUB_LOCAL_PHY_CNTRL				7	/* 0x007 */
108 #define OPC_OUB_RSVD1					10	/* 0x00A */
109 #define OPC_OUB_DEREG_DEV				11	/* 0x00B */
110 #define OPC_OUB_GET_DEV_HANDLE				12	/* 0x00C */
111 #define OPC_OUB_SATA_COMP				13	/* 0x00D */
112 #define OPC_OUB_SATA_EVENT				14	/* 0x00E */
113 #define OPC_OUB_SSP_EVENT				15	/* 0x00F */
114 #define OPC_OUB_RSVD2					16	/* 0x010 */
115 /* 0x11 - SMP_RECEIVED Notification removed in SPCv*/
116 #define OPC_OUB_SSP_RECV_EVENT				18	/* 0x012 */
117 #define OPC_OUB_RSVD3					19	/* 0x013 */
118 #define OPC_OUB_FW_FLASH_UPDATE				20	/* 0x014 */
119 #define OPC_OUB_GPIO_RESPONSE				22	/* 0x016 */
120 #define OPC_OUB_GPIO_EVENT				23	/* 0x017 */
121 #define OPC_OUB_GENERAL_EVENT				24	/* 0x018 */
122 #define OPC_OUB_SSP_ABORT_RSP				26	/* 0x01A */
123 #define OPC_OUB_SATA_ABORT_RSP				27	/* 0x01B */
124 #define OPC_OUB_SAS_DIAG_MODE_START_END			28	/* 0x01C */
125 #define OPC_OUB_SAS_DIAG_EXECUTE			29	/* 0x01D */
126 #define OPC_OUB_GET_TIME_STAMP				30	/* 0x01E */
127 #define OPC_OUB_RSVD4					31	/* 0x01F */
128 #define OPC_OUB_PORT_CONTROL				32	/* 0x020 */
129 #define OPC_OUB_SKIP_ENTRY				33	/* 0x021 */
130 #define OPC_OUB_SMP_ABORT_RSP				34	/* 0x022 */
131 #define OPC_OUB_GET_NVMD_DATA				35	/* 0x023 */
132 #define OPC_OUB_SET_NVMD_DATA				36	/* 0x024 */
133 #define OPC_OUB_DEVICE_HANDLE_REMOVAL			37	/* 0x025 */
134 #define OPC_OUB_SET_DEVICE_STATE			38	/* 0x026 */
135 #define OPC_OUB_GET_DEVICE_STATE			39	/* 0x027 */
136 #define OPC_OUB_SET_DEV_INFO				40	/* 0x028 */
137 #define OPC_OUB_RSVD5					41	/* 0x029 */
138 #define OPC_OUB_HW_EVENT				1792	/* 0x700 */
139 #define OPC_OUB_DEV_HANDLE_ARRIV			1824	/* 0x720 */
140 #define OPC_OUB_THERM_HW_EVENT				1840	/* 0x730 */
141 #define OPC_OUB_SGPIO_RESP				2094	/* 0x82E */
142 #define OPC_OUB_PCIE_DIAG_EXECUTE			2095	/* 0x82F */
143 #define OPC_OUB_DEV_REGIST				2098	/* 0x832 */
144 #define OPC_OUB_SAS_HW_EVENT_ACK			2099	/* 0x833 */
145 #define OPC_OUB_GET_DEVICE_INFO				2100	/* 0x834 */
146 /* spcv specific commands */
147 #define OPC_OUB_PHY_START_RESP				2052	/* 0x804 */
148 #define OPC_OUB_PHY_STOP_RESP				2053	/* 0x805 */
149 #define OPC_OUB_SET_CONTROLLER_CONFIG			2096	/* 0x830 */
150 #define OPC_OUB_GET_CONTROLLER_CONFIG			2097	/* 0x831 */
151 #define OPC_OUB_GET_PHY_PROFILE				2101	/* 0x835 */
152 #define OPC_OUB_FLASH_OP_EXT				2102	/* 0x836 */
153 #define OPC_OUB_SET_PHY_PROFILE				2103	/* 0x837 */
154 #define OPC_OUB_KEK_MANAGEMENT_RESP			2304	/* 0x900 */
155 #define OPC_OUB_DEK_MANAGEMENT_RESP			2305	/* 0x901 */
156 #define OPC_OUB_SSP_COALESCED_COMP_RESP			2306	/* 0x902 */
157 
158 /* for phy start*/
159 #define SSC_DISABLE_15			(0x01 << 16)
160 #define SSC_DISABLE_30			(0x02 << 16)
161 #define SSC_DISABLE_60			(0x04 << 16)
162 #define SAS_ASE				(0x01 << 15)
163 #define SPINHOLD_DISABLE		(0x00 << 14)
164 #define SPINHOLD_ENABLE			(0x01 << 14)
165 #define LINKMODE_SAS			(0x01 << 12)
166 #define LINKMODE_DSATA			(0x02 << 12)
167 #define LINKMODE_AUTO			(0x03 << 12)
168 #define LINKRATE_15			(0x01 << 8)
169 #define LINKRATE_30			(0x02 << 8)
170 #define LINKRATE_60			(0x04 << 8)
171 #define LINKRATE_120			(0x08 << 8)
172 
173 /*phy_stop*/
174 #define PHY_STOP_SUCCESS		0x00
175 #define PHY_STOP_ERR_DEVICE_ATTACHED	0x1046
176 
177 /* phy_profile */
178 #define SAS_PHY_ANALOG_SETTINGS_PAGE	0x04
179 #define PHY_DWORD_LENGTH		0xC
180 
181 /* Thermal related */
182 #define	THERMAL_ENABLE			0x1
183 #define	THERMAL_LOG_ENABLE		0x1
184 #define THERMAL_PAGE_CODE_7H		0x6
185 #define THERMAL_PAGE_CODE_8H		0x7
186 #define LTEMPHIL			 70
187 #define RTEMPHIL			100
188 
189 /* Encryption info */
190 #define SCRATCH_PAD3_ENC_DISABLED	0x00000000
191 #define SCRATCH_PAD3_ENC_DIS_ERR	0x00000001
192 #define SCRATCH_PAD3_ENC_ENA_ERR	0x00000002
193 #define SCRATCH_PAD3_ENC_READY		0x00000003
194 #define SCRATCH_PAD3_ENC_MASK		SCRATCH_PAD3_ENC_READY
195 
196 #define SCRATCH_PAD3_XTS_ENABLED		(1 << 14)
197 #define SCRATCH_PAD3_SMA_ENABLED		(1 << 4)
198 #define SCRATCH_PAD3_SMB_ENABLED		(1 << 5)
199 #define SCRATCH_PAD3_SMF_ENABLED		0
200 #define SCRATCH_PAD3_SM_MASK			0x000000F0
201 #define SCRATCH_PAD3_ERR_CODE			0x00FF0000
202 
203 #define SEC_MODE_SMF				0x0
204 #define SEC_MODE_SMA				0x100
205 #define SEC_MODE_SMB				0x200
206 #define CIPHER_MODE_ECB				0x00000001
207 #define CIPHER_MODE_XTS				0x00000002
208 #define KEK_MGMT_SUBOP_KEYCARDUPDATE		0x4
209 
210 /* SAS protocol timer configuration page */
211 #define SAS_PROTOCOL_TIMER_CONFIG_PAGE  0x04
212 #define STP_MCT_TMO                     32
213 #define SSP_MCT_TMO                     32
214 #define SAS_MAX_OPEN_TIME				5
215 #define SMP_MAX_CONN_TIMER              0xFF
216 #define STP_FRM_TIMER                   0
217 #define STP_IDLE_TIME                   5 /* 5 us; controller default */
218 #define SAS_MFD                         0
219 #define SAS_OPNRJT_RTRY_INTVL           2
220 #define SAS_DOPNRJT_RTRY_TMO            128
221 #define SAS_COPNRJT_RTRY_TMO            128
222 
223 #define SPCV_DOORBELL_CLEAR_TIMEOUT	(30 * 50) /* 30 sec */
224 #define SPC_DOORBELL_CLEAR_TIMEOUT	(15 * 50) /* 15 sec */
225 
226 /*
227   Making ORR bigger than IT NEXUS LOSS which is 2000000us = 2 second.
228   Assuming a bigger value 3 second, 3000000/128 = 23437.5 where 128
229   is DOPNRJT_RTRY_TMO
230 */
231 #define SAS_DOPNRJT_RTRY_THR            23438
232 #define SAS_COPNRJT_RTRY_THR            23438
233 #define SAS_MAX_AIP                     0x200000
234 #define IT_NEXUS_TIMEOUT       0x7D0
235 #define PORT_RECOVERY_TIMEOUT  ((IT_NEXUS_TIMEOUT/100) + 30)
236 /* Port recovery timeout, 10000 ms for PM8006 controller */
237 #define CHIP_8006_PORT_RECOVERY_TIMEOUT 0x640000
238 
239 #ifdef __LITTLE_ENDIAN_BITFIELD
240 struct sas_identify_frame_local {
241 	/* Byte 0 */
242 	u8  frame_type:4;
243 	u8  dev_type:3;
244 	u8  _un0:1;
245 
246 	/* Byte 1 */
247 	u8  _un1;
248 
249 	/* Byte 2 */
250 	union {
251 		struct {
252 			u8  _un20:1;
253 			u8  smp_iport:1;
254 			u8  stp_iport:1;
255 			u8  ssp_iport:1;
256 			u8  _un247:4;
257 		};
258 		u8 initiator_bits;
259 	};
260 
261 	/* Byte 3 */
262 	union {
263 		struct {
264 			u8  _un30:1;
265 			u8 smp_tport:1;
266 			u8 stp_tport:1;
267 			u8 ssp_tport:1;
268 			u8 _un347:4;
269 		};
270 		u8 target_bits;
271 	};
272 
273 	/* Byte 4 - 11 */
274 	u8 _un4_11[8];
275 
276 	/* Byte 12 - 19 */
277 	u8 sas_addr[SAS_ADDR_SIZE];
278 
279 	/* Byte 20 */
280 	u8 phy_id;
281 
282 	u8 _un21_27[7];
283 
284 } __packed;
285 
286 #elif defined(__BIG_ENDIAN_BITFIELD)
287 struct sas_identify_frame_local {
288 	/* Byte 0 */
289 	u8  _un0:1;
290 	u8  dev_type:3;
291 	u8  frame_type:4;
292 
293 	/* Byte 1 */
294 	u8  _un1;
295 
296 	/* Byte 2 */
297 	union {
298 		struct {
299 			u8  _un247:4;
300 			u8  ssp_iport:1;
301 			u8  stp_iport:1;
302 			u8  smp_iport:1;
303 			u8  _un20:1;
304 		};
305 		u8 initiator_bits;
306 	};
307 
308 	/* Byte 3 */
309 	union {
310 		struct {
311 			u8 _un347:4;
312 			u8 ssp_tport:1;
313 			u8 stp_tport:1;
314 			u8 smp_tport:1;
315 			u8 _un30:1;
316 		};
317 		u8 target_bits;
318 	};
319 
320 	/* Byte 4 - 11 */
321 	u8 _un4_11[8];
322 
323 	/* Byte 12 - 19 */
324 	u8 sas_addr[SAS_ADDR_SIZE];
325 
326 	/* Byte 20 */
327 	u8 phy_id;
328 
329 	u8 _un21_27[7];
330 } __packed;
331 #else
332 #error "Bitfield order not defined!"
333 #endif
334 
335 struct mpi_msg_hdr {
336 	__le32	header;	/* Bits [11:0] - Message operation code */
337 	/* Bits [15:12] - Message Category */
338 	/* Bits [21:16] - Outboundqueue ID for the
339 	operation completion message */
340 	/* Bits [23:22] - Reserved */
341 	/* Bits [28:24] - Buffer Count, indicates how
342 	many buffer are allocated for the massage */
343 	/* Bits [30:29] - Reserved */
344 	/* Bits [31] - Message Valid bit */
345 } __attribute__((packed, aligned(4)));
346 
347 /*
348  * brief the data structure of PHY Start Command
349  * use to describe enable the phy (128 bytes)
350  */
351 struct phy_start_req {
352 	__le32	tag;
353 	__le32	ase_sh_lm_slr_phyid;
354 	struct sas_identify_frame_local sas_identify; /* 28 Bytes */
355 	__le32 spasti;
356 	u32	reserved[21];
357 } __attribute__((packed, aligned(4)));
358 
359 /*
360  * brief the data structure of PHY Start Command
361  * use to disable the phy (128 bytes)
362  */
363 struct phy_stop_req {
364 	__le32	tag;
365 	__le32	phy_id;
366 	u32	reserved[29];
367 } __attribute__((packed, aligned(4)));
368 
369 /* set device bits fis - device to host */
370 struct set_dev_bits_fis {
371 	u8	fis_type;	/* 0xA1*/
372 	u8	n_i_pmport;
373 	/* b7 : n Bit. Notification bit. If set device needs attention. */
374 	/* b6 : i Bit. Interrupt Bit */
375 	/* b5-b4: reserved2 */
376 	/* b3-b0: PM Port */
377 	u8	status;
378 	u8	error;
379 	u32	_r_a;
380 } __attribute__ ((packed));
381 /* PIO setup FIS - device to host */
382 struct pio_setup_fis {
383 	u8	fis_type;	/* 0x5f */
384 	u8	i_d_pmPort;
385 	/* b7 : reserved */
386 	/* b6 : i bit. Interrupt bit */
387 	/* b5 : d bit. data transfer direction. set to 1 for device to host
388 	xfer */
389 	/* b4 : reserved */
390 	/* b3-b0: PM Port */
391 	u8	status;
392 	u8	error;
393 	u8	lbal;
394 	u8	lbam;
395 	u8	lbah;
396 	u8	device;
397 	u8	lbal_exp;
398 	u8	lbam_exp;
399 	u8	lbah_exp;
400 	u8	_r_a;
401 	u8	sector_count;
402 	u8	sector_count_exp;
403 	u8	_r_b;
404 	u8	e_status;
405 	u8	_r_c[2];
406 	u8	transfer_count;
407 } __attribute__ ((packed));
408 
409 /*
410  * brief the data structure of SATA Completion Response
411  * use to describe the sata task response (64 bytes)
412  */
413 struct sata_completion_resp {
414 	__le32	tag;
415 	__le32	status;
416 	__le32	param;
417 	u32	sata_resp[12];
418 } __attribute__((packed, aligned(4)));
419 
420 /*
421  * brief the data structure of SAS HW Event Notification
422  * use to alert the host about the hardware event(64 bytes)
423  */
424 /* updated outbound struct for spcv */
425 
426 struct hw_event_resp {
427 	__le32	lr_status_evt_portid;
428 	__le32	evt_param;
429 	__le32	phyid_npip_portstate;
430 	struct sas_identify_frame	sas_identify;
431 	struct dev_to_host_fis	sata_fis;
432 } __attribute__((packed, aligned(4)));
433 
434 /*
435  * brief the data structure for thermal event notification
436  */
437 
438 struct thermal_hw_event {
439 	__le32	thermal_event;
440 	__le32	rht_lht;
441 } __attribute__((packed, aligned(4)));
442 
443 /*
444  * brief the data structure of REGISTER DEVICE Command
445  * use to describe MPI REGISTER DEVICE Command (64 bytes)
446  */
447 
448 struct reg_dev_req {
449 	__le32	tag;
450 	__le32	phyid_portid;
451 	__le32	dtype_dlr_mcn_ir_retry;
452 	__le32	firstburstsize_ITNexustimeout;
453 	u8	sas_addr[SAS_ADDR_SIZE];
454 	__le32	upper_device_id;
455 	u32	reserved[24];
456 } __attribute__((packed, aligned(4)));
457 
458 /*
459  * brief the data structure of DEREGISTER DEVICE Command
460  * use to request spc to remove all internal resources associated
461  * with the device id (64 bytes)
462  */
463 
464 struct dereg_dev_req {
465 	__le32	tag;
466 	__le32	device_id;
467 	u32	reserved[29];
468 } __attribute__((packed, aligned(4)));
469 
470 /*
471  * brief the data structure of DEVICE_REGISTRATION Response
472  * use to notify the completion of the device registration (64 bytes)
473  */
474 struct dev_reg_resp {
475 	__le32	tag;
476 	__le32	status;
477 	__le32	device_id;
478 	u32	reserved[12];
479 } __attribute__((packed, aligned(4)));
480 
481 /*
482  * brief the data structure of Local PHY Control Command
483  * use to issue PHY CONTROL to local phy (64 bytes)
484  */
485 struct local_phy_ctl_req {
486 	__le32	tag;
487 	__le32	phyop_phyid;
488 	u32	reserved1[29];
489 } __attribute__((packed, aligned(4)));
490 
491 /**
492  * brief the data structure of Local Phy Control Response
493  * use to describe MPI Local Phy Control Response (64 bytes)
494  */
495  struct local_phy_ctl_resp {
496 	__le32	tag;
497 	__le32	phyop_phyid;
498 	__le32	status;
499 	u32	reserved[12];
500 } __attribute__((packed, aligned(4)));
501 
502 #define OP_BITS 0x0000FF00
503 #define ID_BITS 0x000000FF
504 
505 /*
506  * brief the data structure of PORT Control Command
507  * use to control port properties (64 bytes)
508  */
509 
510 struct port_ctl_req {
511 	__le32	tag;
512 	__le32	portop_portid;
513 	__le32	param0;
514 	__le32	param1;
515 	u32	reserved1[27];
516 } __attribute__((packed, aligned(4)));
517 
518 /*
519  * brief the data structure of HW Event Ack Command
520  * use to acknowledge receive HW event (64 bytes)
521  */
522 struct hw_event_ack_req {
523 	__le32	tag;
524 	__le32	phyid_sea_portid;
525 	__le32	param0;
526 	__le32	param1;
527 	u32	reserved1[27];
528 } __attribute__((packed, aligned(4)));
529 
530 /*
531  * brief the data structure of PHY_START Response Command
532  * indicates the completion of PHY_START command (64 bytes)
533  */
534 struct phy_start_resp {
535 	__le32	tag;
536 	__le32	status;
537 	__le32	phyid;
538 	u32	reserved[12];
539 } __attribute__((packed, aligned(4)));
540 
541 /*
542  * brief the data structure of PHY_STOP Response Command
543  * indicates the completion of PHY_STOP command (64 bytes)
544  */
545 struct phy_stop_resp {
546 	__le32	tag;
547 	__le32	status;
548 	__le32	phyid;
549 	u32	reserved[12];
550 } __attribute__((packed, aligned(4)));
551 
552 /*
553  * brief the data structure of SSP Completion Response
554  * use to indicate a SSP Completion (n bytes)
555  */
556 struct ssp_completion_resp {
557 	__le32	tag;
558 	__le32	status;
559 	__le32	param;
560 	__le32	ssptag_rescv_rescpad;
561 	struct ssp_response_iu ssp_resp_iu;
562 	__le32	residual_count;
563 } __attribute__((packed, aligned(4)));
564 
565 #define SSP_RESCV_BIT	0x00010000
566 
567 /*
568  * brief the data structure of SATA EVNET response
569  * use to indicate a SATA Completion (64 bytes)
570  */
571 struct sata_event_resp {
572 	__le32 tag;
573 	__le32 event;
574 	__le32 port_id;
575 	__le32 device_id;
576 	u32 reserved;
577 	__le32 event_param0;
578 	__le32 event_param1;
579 	__le32 sata_addr_h32;
580 	__le32 sata_addr_l32;
581 	__le32 e_udt1_udt0_crc;
582 	__le32 e_udt5_udt4_udt3_udt2;
583 	__le32 a_udt1_udt0_crc;
584 	__le32 a_udt5_udt4_udt3_udt2;
585 	__le32 hwdevid_diferr;
586 	__le32 err_framelen_byteoffset;
587 	__le32 err_dataframe;
588 } __attribute__((packed, aligned(4)));
589 
590 /*
591  * brief the data structure of SSP EVNET esponse
592  * use to indicate a SSP Completion (64 bytes)
593  */
594 struct ssp_event_resp {
595 	__le32 tag;
596 	__le32 event;
597 	__le32 port_id;
598 	__le32 device_id;
599 	__le32 ssp_tag;
600 	__le32 event_param0;
601 	__le32 event_param1;
602 	__le32 sas_addr_h32;
603 	__le32 sas_addr_l32;
604 	__le32 e_udt1_udt0_crc;
605 	__le32 e_udt5_udt4_udt3_udt2;
606 	__le32 a_udt1_udt0_crc;
607 	__le32 a_udt5_udt4_udt3_udt2;
608 	__le32 hwdevid_diferr;
609 	__le32 err_framelen_byteoffset;
610 	__le32 err_dataframe;
611 } __attribute__((packed, aligned(4)));
612 
613 /**
614  * brief the data structure of General Event Notification Response
615  * use to describe MPI General Event Notification Response (64 bytes)
616  */
617 struct general_event_resp {
618 	__le32	status;
619 	__le32	inb_IOMB_payload[14];
620 } __attribute__((packed, aligned(4)));
621 
622 #define GENERAL_EVENT_PAYLOAD	14
623 #define OPCODE_BITS	0x00000fff
624 
625 /*
626  * brief the data structure of SMP Request Command
627  * use to describe MPI SMP REQUEST Command (64 bytes)
628  */
629 struct smp_req {
630 	__le32	tag;
631 	__le32	device_id;
632 	__le32	len_ip_ir;
633 	/* Bits [0] - Indirect response */
634 	/* Bits [1] - Indirect Payload */
635 	/* Bits [15:2] - Reserved */
636 	/* Bits [23:16] - direct payload Len */
637 	/* Bits [31:24] - Reserved */
638 	u8	smp_req16[16];
639 	union {
640 		u8	smp_req[32];
641 		struct {
642 			__le64 long_req_addr;/* sg dma address, LE */
643 			__le32 long_req_size;/* LE */
644 			u32	_r_a;
645 			__le64 long_resp_addr;/* sg dma address, LE */
646 			__le32 long_resp_size;/* LE */
647 			u32	_r_b;
648 			} long_smp_req;/* sequencer extension */
649 	};
650 	__le32	rsvd[16];
651 } __attribute__((packed, aligned(4)));
652 /*
653  * brief the data structure of SMP Completion Response
654  * use to describe MPI SMP Completion Response (64 bytes)
655  */
656 struct smp_completion_resp {
657 	__le32	tag;
658 	__le32	status;
659 	__le32	param;
660 	u8	_r_a[252];
661 } __attribute__((packed, aligned(4)));
662 
663 /*
664  *brief the data structure of SSP SMP SATA Abort Command
665  * use to describe MPI SSP SMP & SATA Abort Command (64 bytes)
666  */
667 struct task_abort_req {
668 	__le32	tag;
669 	__le32	device_id;
670 	__le32	tag_to_abort;
671 	__le32	abort_all;
672 	u32	reserved[27];
673 } __attribute__((packed, aligned(4)));
674 
675 /**
676  * brief the data structure of SSP SATA SMP Abort Response
677  * use to describe SSP SMP & SATA Abort Response ( 64 bytes)
678  */
679 struct task_abort_resp {
680 	__le32	tag;
681 	__le32	status;
682 	__le32	scp;
683 	u32	reserved[12];
684 } __attribute__((packed, aligned(4)));
685 
686 /**
687  * brief the data structure of SAS Diagnostic Start/End Command
688  * use to describe MPI SAS Diagnostic Start/End Command (64 bytes)
689  */
690 struct sas_diag_start_end_req {
691 	__le32	tag;
692 	__le32	operation_phyid;
693 	u32	reserved[29];
694 } __attribute__((packed, aligned(4)));
695 
696 /**
697  * brief the data structure of SAS Diagnostic Execute Command
698  * use to describe MPI SAS Diagnostic Execute Command (64 bytes)
699  */
700 struct sas_diag_execute_req {
701 	__le32	tag;
702 	__le32	cmdtype_cmddesc_phyid;
703 	__le32	pat1_pat2;
704 	__le32	threshold;
705 	__le32	codepat_errmsk;
706 	__le32	pmon;
707 	__le32	pERF1CTL;
708 	u32	reserved[24];
709 } __attribute__((packed, aligned(4)));
710 
711 #define SAS_DIAG_PARAM_BYTES 24
712 
713 /*
714  * brief the data structure of Set Device State Command
715  * use to describe MPI Set Device State Command (64 bytes)
716  */
717 struct set_dev_state_req {
718 	__le32	tag;
719 	__le32	device_id;
720 	__le32	nds;
721 	u32	reserved[28];
722 } __attribute__((packed, aligned(4)));
723 
724 /*
725  * brief the data structure of SATA Start Command
726  * use to describe MPI SATA IO Start Command (64 bytes)
727  * Note: This structure is common for normal / encryption I/O
728  */
729 
730 struct sata_start_req {
731 	__le32	tag;
732 	__le32	device_id;
733 	__le32	data_len;
734 	__le32	retfis_ncqtag_atap_dir_m_dad;
735 	struct host_to_dev_fis	sata_fis;
736 	u32	reserved1;
737 	u32	reserved2;	/* dword 11. rsvd for normal I/O. */
738 				/* EPLE Descl for enc I/O */
739 	u32	addr_low;	/* dword 12. rsvd for enc I/O */
740 	u32	addr_high;	/* dword 13. reserved for enc I/O */
741 	__le32	len;		/* dword 14: length for normal I/O. */
742 				/* EPLE Desch for enc I/O */
743 	__le32	esgl;		/* dword 15. rsvd for enc I/O */
744 	__le32	atapi_scsi_cdb[4];	/* dword 16-19. rsvd for enc I/O */
745 	/* The below fields are reserved for normal I/O */
746 	__le32	key_index_mode;	/* dword 20 */
747 	__le32	sector_cnt_enss;/* dword 21 */
748 	__le32	keytagl;	/* dword 22 */
749 	__le32	keytagh;	/* dword 23 */
750 	__le32	twk_val0;	/* dword 24 */
751 	__le32	twk_val1;	/* dword 25 */
752 	__le32	twk_val2;	/* dword 26 */
753 	__le32	twk_val3;	/* dword 27 */
754 	__le32	enc_addr_low;	/* dword 28. Encryption SGL address high */
755 	__le32	enc_addr_high;	/* dword 29. Encryption SGL address low */
756 	__le32	enc_len;	/* dword 30. Encryption length */
757 	__le32	enc_esgl;	/* dword 31. Encryption esgl bit */
758 } __attribute__((packed, aligned(4)));
759 
760 /**
761  * brief the data structure of SSP INI TM Start Command
762  * use to describe MPI SSP INI TM Start Command (64 bytes)
763  */
764 struct ssp_ini_tm_start_req {
765 	__le32	tag;
766 	__le32	device_id;
767 	__le32	relate_tag;
768 	__le32	tmf;
769 	u8	lun[8];
770 	__le32	ds_ads_m;
771 	u32	reserved[24];
772 } __attribute__((packed, aligned(4)));
773 
774 struct ssp_info_unit {
775 	u8	lun[8];/* SCSI Logical Unit Number */
776 	u8	reserved1;/* reserved */
777 	u8	efb_prio_attr;
778 	/* B7 : enabledFirstBurst */
779 	/* B6-3 : taskPriority */
780 	/* B2-0 : taskAttribute */
781 	u8	reserved2;	/* reserved */
782 	u8	additional_cdb_len;
783 	/* B7-2 : additional_cdb_len */
784 	/* B1-0 : reserved */
785 	u8	cdb[16];/* The SCSI CDB up to 16 bytes length */
786 } __attribute__((packed, aligned(4)));
787 
788 /**
789  * brief the data structure of SSP INI IO Start Command
790  * use to describe MPI SSP INI IO Start Command (64 bytes)
791  * Note: This structure is common for normal / encryption I/O
792  */
793 struct ssp_ini_io_start_req {
794 	__le32	tag;
795 	__le32	device_id;
796 	__le32	data_len;
797 	__le32	dad_dir_m_tlr;
798 	struct ssp_info_unit	ssp_iu;
799 	__le32	addr_low;	/* dword 12: sgl low for normal I/O. */
800 				/* epl_descl for encryption I/O */
801 	__le32	addr_high;	/* dword 13: sgl hi for normal I/O */
802 				/* dpl_descl for encryption I/O */
803 	__le32	len;		/* dword 14: len for normal I/O. */
804 				/* edpl_desch for encryption I/O */
805 	__le32	esgl;		/* dword 15: ESGL bit for normal I/O. */
806 				/* user defined tag mask for enc I/O */
807 	/* The below fields are reserved for normal I/O */
808 	u8	udt[12];	/* dword 16-18 */
809 	__le32	sectcnt_ios;	/* dword 19 */
810 	__le32	key_cmode;	/* dword 20 */
811 	__le32	ks_enss;	/* dword 21 */
812 	__le32	keytagl;	/* dword 22 */
813 	__le32	keytagh;	/* dword 23 */
814 	__le32	twk_val0;	/* dword 24 */
815 	__le32	twk_val1;	/* dword 25 */
816 	__le32	twk_val2;	/* dword 26 */
817 	__le32	twk_val3;	/* dword 27 */
818 	__le32	enc_addr_low;	/* dword 28: Encryption sgl addr low */
819 	__le32	enc_addr_high;	/* dword 29: Encryption sgl addr hi */
820 	__le32	enc_len;	/* dword 30: Encryption length */
821 	__le32	enc_esgl;	/* dword 31: ESGL bit for encryption */
822 } __attribute__((packed, aligned(4)));
823 
824 /**
825  * brief the data structure for SSP_INI_DIF_ENC_IO COMMAND
826  * use to initiate SSP I/O operation with optional DIF/ENC
827  */
828 struct ssp_dif_enc_io_req {
829 	__le32	tag;
830 	__le32	device_id;
831 	__le32	data_len;
832 	__le32	dirMTlr;
833 	__le32	sspiu0;
834 	__le32	sspiu1;
835 	__le32	sspiu2;
836 	__le32	sspiu3;
837 	__le32	sspiu4;
838 	__le32	sspiu5;
839 	__le32	sspiu6;
840 	__le32	epl_des;
841 	__le32	dpl_desl_ndplr;
842 	__le32	dpl_desh;
843 	__le32	uum_uuv_bss_difbits;
844 	u8	udt[12];
845 	__le32	sectcnt_ios;
846 	__le32	key_cmode;
847 	__le32	ks_enss;
848 	__le32	keytagl;
849 	__le32	keytagh;
850 	__le32	twk_val0;
851 	__le32	twk_val1;
852 	__le32	twk_val2;
853 	__le32	twk_val3;
854 	__le32	addr_low;
855 	__le32	addr_high;
856 	__le32	len;
857 	__le32	esgl;
858 } __attribute__((packed, aligned(4)));
859 
860 /**
861  * brief the data structure of Firmware download
862  * use to describe MPI FW DOWNLOAD Command (64 bytes)
863  */
864 struct fw_flash_Update_req {
865 	__le32	tag;
866 	__le32	cur_image_offset;
867 	__le32	cur_image_len;
868 	__le32	total_image_len;
869 	u32	reserved0[7];
870 	__le32	sgl_addr_lo;
871 	__le32	sgl_addr_hi;
872 	__le32	len;
873 	__le32	ext_reserved;
874 	u32	reserved1[16];
875 } __attribute__((packed, aligned(4)));
876 
877 #define FWFLASH_IOMB_RESERVED_LEN 0x07
878 /**
879  * brief the data structure of FW_FLASH_UPDATE Response
880  * use to describe MPI FW_FLASH_UPDATE Response (64 bytes)
881  *
882  */
883  struct fw_flash_Update_resp {
884 	__le32	tag;
885 	__le32	status;
886 	u32	reserved[13];
887 } __attribute__((packed, aligned(4)));
888 
889 /**
890  * brief the data structure of Get NVM Data Command
891  * use to get data from NVM in HBA(64 bytes)
892  */
893 struct get_nvm_data_req {
894 	__le32	tag;
895 	__le32	len_ir_vpdd;
896 	__le32	vpd_offset;
897 	u32	reserved[8];
898 	__le32	resp_addr_lo;
899 	__le32	resp_addr_hi;
900 	__le32	resp_len;
901 	u32	reserved1[17];
902 } __attribute__((packed, aligned(4)));
903 
904 struct set_nvm_data_req {
905 	__le32	tag;
906 	__le32	len_ir_vpdd;
907 	__le32	vpd_offset;
908 	u32	reserved[8];
909 	__le32	resp_addr_lo;
910 	__le32	resp_addr_hi;
911 	__le32	resp_len;
912 	u32	reserved1[17];
913 } __attribute__((packed, aligned(4)));
914 
915 /**
916  * brief the data structure for SET CONTROLLER CONFIG COMMAND
917  * use to modify controller configuration
918  */
919 struct set_ctrl_cfg_req {
920 	__le32	tag;
921 	__le32	cfg_pg[14];
922 	u32	reserved[16];
923 } __attribute__((packed, aligned(4)));
924 
925 /**
926  * brief the data structure for GET CONTROLLER CONFIG COMMAND
927  * use to get controller configuration page
928  */
929 struct get_ctrl_cfg_req {
930 	__le32	tag;
931 	__le32	pgcd;
932 	__le32	int_vec;
933 	u32	reserved[28];
934 } __attribute__((packed, aligned(4)));
935 
936 /**
937  * brief the data structure for KEK_MANAGEMENT COMMAND
938  * use for KEK management
939  */
940 struct kek_mgmt_req {
941 	__le32	tag;
942 	__le32	new_curidx_ksop;
943 	u32	reserved;
944 	__le32	kblob[12];
945 	u32	reserved1[16];
946 } __attribute__((packed, aligned(4)));
947 
948 /**
949  * brief the data structure for DEK_MANAGEMENT COMMAND
950  * use for DEK management
951  */
952 struct dek_mgmt_req {
953 	__le32	tag;
954 	__le32	kidx_dsop;
955 	__le32	dekidx;
956 	__le32	addr_l;
957 	__le32	addr_h;
958 	__le32	nent;
959 	__le32	dbf_tblsize;
960 	u32	reserved[24];
961 } __attribute__((packed, aligned(4)));
962 
963 /**
964  * brief the data structure for SET PHY PROFILE COMMAND
965  * use to retrive phy specific information
966  */
967 struct set_phy_profile_req {
968 	__le32	tag;
969 	__le32	ppc_phyid;
970 	__le32	reserved[29];
971 } __attribute__((packed, aligned(4)));
972 
973 /**
974  * brief the data structure for GET PHY PROFILE COMMAND
975  * use to retrive phy specific information
976  */
977 struct get_phy_profile_req {
978 	__le32	tag;
979 	__le32	ppc_phyid;
980 	__le32	profile[29];
981 } __attribute__((packed, aligned(4)));
982 
983 /**
984  * brief the data structure for EXT FLASH PARTITION
985  * use to manage ext flash partition
986  */
987 struct ext_flash_partition_req {
988 	__le32	tag;
989 	__le32	cmd;
990 	__le32	offset;
991 	__le32	len;
992 	u32	reserved[7];
993 	__le32	addr_low;
994 	__le32	addr_high;
995 	__le32	len1;
996 	__le32	ext;
997 	u32	reserved1[16];
998 } __attribute__((packed, aligned(4)));
999 
1000 #define TWI_DEVICE	0x0
1001 #define C_SEEPROM	0x1
1002 #define VPD_FLASH	0x4
1003 #define AAP1_RDUMP	0x5
1004 #define IOP_RDUMP	0x6
1005 #define EXPAN_ROM	0x7
1006 
1007 #define IPMode		0x80000000
1008 #define NVMD_TYPE	0x0000000F
1009 #define NVMD_STAT	0x0000FFFF
1010 #define NVMD_LEN	0xFF000000
1011 /**
1012  * brief the data structure of Get NVMD Data Response
1013  * use to describe MPI Get NVMD Data Response (64 bytes)
1014  */
1015 struct get_nvm_data_resp {
1016 	__le32		tag;
1017 	__le32		ir_tda_bn_dps_das_nvm;
1018 	__le32		dlen_status;
1019 	__le32		nvm_data[12];
1020 } __attribute__((packed, aligned(4)));
1021 
1022 /**
1023  * brief the data structure of SAS Diagnostic Start/End Response
1024  * use to describe MPI SAS Diagnostic Start/End Response (64 bytes)
1025  *
1026  */
1027 struct sas_diag_start_end_resp {
1028 	__le32		tag;
1029 	__le32		status;
1030 	u32		reserved[13];
1031 } __attribute__((packed, aligned(4)));
1032 
1033 /**
1034  * brief the data structure of SAS Diagnostic Execute Response
1035  * use to describe MPI SAS Diagnostic Execute Response (64 bytes)
1036  *
1037  */
1038 struct sas_diag_execute_resp {
1039 	__le32		tag;
1040 	__le32		cmdtype_cmddesc_phyid;
1041 	__le32		Status;
1042 	__le32		ReportData;
1043 	u32		reserved[11];
1044 } __attribute__((packed, aligned(4)));
1045 
1046 /**
1047  * brief the data structure of Set Device State Response
1048  * use to describe MPI Set Device State Response (64 bytes)
1049  *
1050  */
1051 struct set_dev_state_resp {
1052 	__le32		tag;
1053 	__le32		status;
1054 	__le32		device_id;
1055 	__le32		pds_nds;
1056 	u32		reserved[11];
1057 } __attribute__((packed, aligned(4)));
1058 
1059 /* new outbound structure for spcv - begins */
1060 /**
1061  * brief the data structure for SET CONTROLLER CONFIG COMMAND
1062  * use to modify controller configuration
1063  */
1064 struct set_ctrl_cfg_resp {
1065 	__le32 tag;
1066 	__le32 status;
1067 	__le32 err_qlfr_pgcd;
1068 	u32 reserved[12];
1069 } __attribute__((packed, aligned(4)));
1070 
1071 struct get_ctrl_cfg_resp {
1072 	__le32 tag;
1073 	__le32 status;
1074 	__le32 err_qlfr;
1075 	__le32 confg_page[12];
1076 } __attribute__((packed, aligned(4)));
1077 
1078 struct kek_mgmt_resp {
1079 	__le32 tag;
1080 	__le32 status;
1081 	__le32 kidx_new_curr_ksop;
1082 	__le32 err_qlfr;
1083 	u32 reserved[11];
1084 } __attribute__((packed, aligned(4)));
1085 
1086 struct dek_mgmt_resp {
1087 	__le32 tag;
1088 	__le32 status;
1089 	__le32 kekidx_tbls_dsop;
1090 	__le32 dekidx;
1091 	__le32 err_qlfr;
1092 	u32 reserved[10];
1093 } __attribute__((packed, aligned(4)));
1094 
1095 struct get_phy_profile_resp {
1096 	__le32 tag;
1097 	__le32 status;
1098 	__le32 ppc_phyid;
1099 	__le32 ppc_specific_rsp[12];
1100 } __attribute__((packed, aligned(4)));
1101 
1102 struct flash_op_ext_resp {
1103 	__le32 tag;
1104 	__le32 cmd;
1105 	__le32 status;
1106 	__le32 epart_size;
1107 	__le32 epart_sect_size;
1108 	u32 reserved[10];
1109 } __attribute__((packed, aligned(4)));
1110 
1111 struct set_phy_profile_resp {
1112 	__le32 tag;
1113 	__le32 status;
1114 	__le32 ppc_phyid;
1115 	__le32 ppc_specific_rsp[12];
1116 } __attribute__((packed, aligned(4)));
1117 
1118 struct ssp_coalesced_comp_resp {
1119 	__le32 coal_cnt;
1120 	__le32 tag0;
1121 	__le32 ssp_tag0;
1122 	__le32 tag1;
1123 	__le32 ssp_tag1;
1124 	__le32 add_tag_ssp_tag[10];
1125 } __attribute__((packed, aligned(4)));
1126 
1127 /* new outbound structure for spcv - ends */
1128 
1129 /* brief data structure for SAS protocol timer configuration page.
1130  *
1131  */
1132 struct SASProtocolTimerConfig {
1133 	__le32 pageCode;			/* 0 */
1134 	__le32 MST_MSI;				/* 1 */
1135 	__le32 STP_SSP_MCT_TMO;			/* 2 */
1136 	__le32 STP_FRM_TMO;			/* 3 */
1137 	__le32 STP_IDLE_TMO;			/* 4 */
1138 	__le32 OPNRJT_RTRY_INTVL;		/* 5 */
1139 	__le32 Data_Cmd_OPNRJT_RTRY_TMO;	/* 6 */
1140 	__le32 Data_Cmd_OPNRJT_RTRY_THR;	/* 7 */
1141 	__le32 MAX_AIP;				/* 8 */
1142 } __attribute__((packed, aligned(4)));
1143 
1144 typedef struct SASProtocolTimerConfig SASProtocolTimerConfig_t;
1145 
1146 #define NDS_BITS 0x0F
1147 #define PDS_BITS 0xF0
1148 
1149 /*
1150  * HW Events type
1151  */
1152 
1153 #define HW_EVENT_RESET_START			0x01
1154 #define HW_EVENT_CHIP_RESET_COMPLETE		0x02
1155 #define HW_EVENT_PHY_STOP_STATUS		0x03
1156 #define HW_EVENT_SAS_PHY_UP			0x04
1157 #define HW_EVENT_SATA_PHY_UP			0x05
1158 #define HW_EVENT_SATA_SPINUP_HOLD		0x06
1159 #define HW_EVENT_PHY_DOWN			0x07
1160 #define HW_EVENT_PORT_INVALID			0x08
1161 #define HW_EVENT_BROADCAST_CHANGE		0x09
1162 #define HW_EVENT_PHY_ERROR			0x0A
1163 #define HW_EVENT_BROADCAST_SES			0x0B
1164 #define HW_EVENT_INBOUND_CRC_ERROR		0x0C
1165 #define HW_EVENT_HARD_RESET_RECEIVED		0x0D
1166 #define HW_EVENT_MALFUNCTION			0x0E
1167 #define HW_EVENT_ID_FRAME_TIMEOUT		0x0F
1168 #define HW_EVENT_BROADCAST_EXP			0x10
1169 #define HW_EVENT_PHY_START_STATUS		0x11
1170 #define HW_EVENT_LINK_ERR_INVALID_DWORD		0x12
1171 #define HW_EVENT_LINK_ERR_DISPARITY_ERROR	0x13
1172 #define HW_EVENT_LINK_ERR_CODE_VIOLATION	0x14
1173 #define HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH	0x15
1174 #define HW_EVENT_LINK_ERR_PHY_RESET_FAILED	0x16
1175 #define HW_EVENT_PORT_RECOVERY_TIMER_TMO	0x17
1176 #define HW_EVENT_PORT_RECOVER			0x18
1177 #define HW_EVENT_PORT_RESET_TIMER_TMO		0x19
1178 #define HW_EVENT_PORT_RESET_COMPLETE		0x20
1179 #define EVENT_BROADCAST_ASYNCH_EVENT		0x21
1180 
1181 /* port state */
1182 #define PORT_NOT_ESTABLISHED			0x00
1183 #define PORT_VALID				0x01
1184 #define PORT_LOSTCOMM				0x02
1185 #define PORT_IN_RESET				0x04
1186 #define PORT_3RD_PARTY_RESET			0x07
1187 #define PORT_INVALID				0x08
1188 
1189 /*
1190  * SSP/SMP/SATA IO Completion Status values
1191  */
1192 
1193 #define IO_SUCCESS				0x00
1194 #define IO_ABORTED				0x01
1195 #define IO_OVERFLOW				0x02
1196 #define IO_UNDERFLOW				0x03
1197 #define IO_FAILED				0x04
1198 #define IO_ABORT_RESET				0x05
1199 #define IO_NOT_VALID				0x06
1200 #define IO_NO_DEVICE				0x07
1201 #define IO_ILLEGAL_PARAMETER			0x08
1202 #define IO_LINK_FAILURE				0x09
1203 #define IO_PROG_ERROR				0x0A
1204 
1205 #define IO_EDC_IN_ERROR				0x0B
1206 #define IO_EDC_OUT_ERROR			0x0C
1207 #define IO_ERROR_HW_TIMEOUT			0x0D
1208 #define IO_XFER_ERROR_BREAK			0x0E
1209 #define IO_XFER_ERROR_PHY_NOT_READY		0x0F
1210 #define IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED	0x10
1211 #define IO_OPEN_CNX_ERROR_ZONE_VIOLATION		0x11
1212 #define IO_OPEN_CNX_ERROR_BREAK				0x12
1213 #define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS			0x13
1214 #define IO_OPEN_CNX_ERROR_BAD_DESTINATION		0x14
1215 #define IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED	0x15
1216 #define IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY		0x16
1217 #define IO_OPEN_CNX_ERROR_WRONG_DESTINATION		0x17
1218 /* This error code 0x18 is not used on SPCv */
1219 #define IO_OPEN_CNX_ERROR_UNKNOWN_ERROR			0x18
1220 #define IO_XFER_ERROR_NAK_RECEIVED			0x19
1221 #define IO_XFER_ERROR_ACK_NAK_TIMEOUT			0x1A
1222 #define IO_XFER_ERROR_PEER_ABORTED			0x1B
1223 #define IO_XFER_ERROR_RX_FRAME				0x1C
1224 #define IO_XFER_ERROR_DMA				0x1D
1225 #define IO_XFER_ERROR_CREDIT_TIMEOUT			0x1E
1226 #define IO_XFER_ERROR_SATA_LINK_TIMEOUT			0x1F
1227 #define IO_XFER_ERROR_SATA				0x20
1228 
1229 /* This error code 0x22 is not used on SPCv */
1230 #define IO_XFER_ERROR_ABORTED_DUE_TO_SRST		0x22
1231 #define IO_XFER_ERROR_REJECTED_NCQ_MODE			0x21
1232 #define IO_XFER_ERROR_ABORTED_NCQ_MODE			0x23
1233 #define IO_XFER_OPEN_RETRY_TIMEOUT			0x24
1234 /* This error code 0x25 is not used on SPCv */
1235 #define IO_XFER_SMP_RESP_CONNECTION_ERROR		0x25
1236 #define IO_XFER_ERROR_UNEXPECTED_PHASE			0x26
1237 #define IO_XFER_ERROR_XFER_RDY_OVERRUN			0x27
1238 #define IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED		0x28
1239 #define IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT		0x30
1240 
1241 /* The following error code 0x31 and 0x32 are not using (obsolete) */
1242 #define IO_XFER_ERROR_CMD_ISSUE_BREAK_BEFORE_ACK_NAK	0x31
1243 #define IO_XFER_ERROR_CMD_ISSUE_PHY_DOWN_BEFORE_ACK_NAK	0x32
1244 
1245 #define IO_XFER_ERROR_OFFSET_MISMATCH			0x34
1246 #define IO_XFER_ERROR_XFER_ZERO_DATA_LEN		0x35
1247 #define IO_XFER_CMD_FRAME_ISSUED			0x36
1248 #define IO_ERROR_INTERNAL_SMP_RESOURCE			0x37
1249 #define IO_PORT_IN_RESET				0x38
1250 #define IO_DS_NON_OPERATIONAL				0x39
1251 #define IO_DS_IN_RECOVERY				0x3A
1252 #define IO_TM_TAG_NOT_FOUND				0x3B
1253 #define IO_XFER_PIO_SETUP_ERROR				0x3C
1254 #define IO_SSP_EXT_IU_ZERO_LEN_ERROR			0x3D
1255 #define IO_DS_IN_ERROR					0x3E
1256 #define IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY		0x3F
1257 #define IO_ABORT_IN_PROGRESS				0x40
1258 #define IO_ABORT_DELAYED				0x41
1259 #define IO_INVALID_LENGTH				0x42
1260 
1261 /********** additional response event values *****************/
1262 
1263 #define IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY_ALT		0x43
1264 #define IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED	0x44
1265 #define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO	0x45
1266 #define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST		0x46
1267 #define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE	0x47
1268 #define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED	0x48
1269 #define IO_DS_INVALID					0x49
1270 #define IO_FATAL_ERROR					0x51
1271 /* WARNING: the value is not contiguous from here */
1272 #define IO_XFER_ERR_LAST_PIO_DATAIN_CRC_ERR	0x52
1273 #define IO_XFER_DMA_ACTIVATE_TIMEOUT		0x53
1274 #define IO_XFER_ERROR_INTERNAL_CRC_ERROR	0x54
1275 #define MPI_IO_RQE_BUSY_FULL			0x55
1276 #define IO_XFER_ERR_EOB_DATA_OVERRUN		0x56
1277 #define IO_XFER_ERROR_INVALID_SSP_RSP_FRAME	0x57
1278 #define IO_OPEN_CNX_ERROR_OPEN_PREEMPTED	0x58
1279 
1280 #define MPI_ERR_IO_RESOURCE_UNAVAILABLE		0x1004
1281 #define MPI_ERR_ATAPI_DEVICE_BUSY		0x1024
1282 
1283 #define IO_XFR_ERROR_DEK_KEY_CACHE_MISS		0x2040
1284 /*
1285  * An encryption IO request failed due to DEK Key Tag mismatch.
1286  * The key tag supplied in the encryption IOMB does not match with
1287  * the Key Tag in the referenced DEK Entry.
1288  */
1289 #define IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH	0x2041
1290 #define IO_XFR_ERROR_CIPHER_MODE_INVALID	0x2042
1291 /*
1292  * An encryption I/O request failed because the initial value (IV)
1293  * in the unwrapped DEK blob didn't match the IV used to unwrap it.
1294  */
1295 #define IO_XFR_ERROR_DEK_IV_MISMATCH		0x2043
1296 /* An encryption I/O request failed due to an internal RAM ECC or
1297  * interface error while unwrapping the DEK. */
1298 #define IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR	0x2044
1299 /* An encryption I/O request failed due to an internal RAM ECC or
1300  * interface error while unwrapping the DEK. */
1301 #define IO_XFR_ERROR_INTERNAL_RAM		0x2045
1302 /*
1303  * An encryption I/O request failed
1304  * because the DEK index specified in the I/O was outside the bounds of
1305  * the total number of entries in the host DEK table.
1306  */
1307 #define IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS0x2046
1308 
1309 /* define DIF IO response error status code */
1310 #define IO_XFR_ERROR_DIF_MISMATCH			0x3000
1311 #define IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH	0x3001
1312 #define IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH		0x3002
1313 #define IO_XFR_ERROR_DIF_CRC_MISMATCH			0x3003
1314 
1315 /* define operator management response status and error qualifier code */
1316 #define OPR_MGMT_OP_NOT_SUPPORTED			0x2060
1317 #define OPR_MGMT_MPI_ENC_ERR_OPR_PARAM_ILLEGAL		0x2061
1318 #define OPR_MGMT_MPI_ENC_ERR_OPR_ID_NOT_FOUND		0x2062
1319 #define OPR_MGMT_MPI_ENC_ERR_OPR_ROLE_NOT_MATCH		0x2063
1320 #define OPR_MGMT_MPI_ENC_ERR_OPR_MAX_NUM_EXCEEDED	0x2064
1321 #define OPR_MGMT_MPI_ENC_ERR_KEK_UNWRAP_FAIL		0x2022
1322 #define OPR_MGMT_MPI_ENC_ERR_NVRAM_OPERATION_FAILURE	0x2023
1323 /***************** additional response event values ***************/
1324 
1325 /* WARNING: This error code must always be the last number.
1326  * If you add error code, modify this code also
1327  * It is used as an index
1328  */
1329 #define IO_ERROR_UNKNOWN_GENERIC			0x2023
1330 
1331 /* MSGU CONFIGURATION TABLE*/
1332 
1333 #define SPCv_MSGU_CFG_TABLE_UPDATE		0x001
1334 #define SPCv_MSGU_CFG_TABLE_RESET		0x002
1335 #define SPCv_MSGU_CFG_TABLE_FREEZE		0x004
1336 #define SPCv_MSGU_CFG_TABLE_UNFREEZE		0x008
1337 #define MSGU_IBDB_SET				0x00
1338 #define MSGU_HOST_INT_STATUS			0x08
1339 #define MSGU_HOST_INT_MASK			0x0C
1340 #define MSGU_IOPIB_INT_STATUS			0x18
1341 #define MSGU_IOPIB_INT_MASK			0x1C
1342 #define MSGU_IBDB_CLEAR				0x20
1343 
1344 #define MSGU_MSGU_CONTROL			0x24
1345 #define MSGU_ODR				0x20
1346 #define MSGU_ODCR				0x28
1347 
1348 #define MSGU_ODMR				0x30
1349 #define MSGU_ODMR_U				0x34
1350 #define MSGU_ODMR_CLR				0x38
1351 #define MSGU_ODMR_CLR_U				0x3C
1352 #define MSGU_OD_RSVD				0x40
1353 
1354 #define MSGU_SCRATCH_PAD_0			0x44
1355 #define MSGU_SCRATCH_PAD_1			0x48
1356 #define MSGU_SCRATCH_PAD_2			0x4C
1357 #define MSGU_SCRATCH_PAD_3			0x50
1358 #define MSGU_HOST_SCRATCH_PAD_0			0x54
1359 #define MSGU_HOST_SCRATCH_PAD_1			0x58
1360 #define MSGU_HOST_SCRATCH_PAD_2			0x5C
1361 #define MSGU_HOST_SCRATCH_PAD_3			0x60
1362 #define MSGU_HOST_SCRATCH_PAD_4			0x64
1363 #define MSGU_HOST_SCRATCH_PAD_5			0x68
1364 #define MSGU_SCRATCH_PAD_RSVD_0			0x6C
1365 #define MSGU_SCRATCH_PAD_RSVD_1			0x70
1366 
1367 #define MSGU_SCRATCHPAD1_RAAE_STATE_ERR(x) ((x & 0x3) == 0x2)
1368 #define MSGU_SCRATCHPAD1_ILA_STATE_ERR(x) (((x >> 2) & 0x3) == 0x2)
1369 #define MSGU_SCRATCHPAD1_BOOTLDR_STATE_ERR(x) ((((x >> 4) & 0x7) == 0x7) || \
1370 						(((x >> 4) & 0x7) == 0x4))
1371 #define MSGU_SCRATCHPAD1_IOP0_STATE_ERR(x) (((x >> 10) & 0x3) == 0x2)
1372 #define MSGU_SCRATCHPAD1_IOP1_STATE_ERR(x) (((x >> 12) & 0x3) == 0x2)
1373 #define MSGU_SCRATCHPAD1_STATE_FATAL_ERROR(x)  \
1374 			(MSGU_SCRATCHPAD1_RAAE_STATE_ERR(x) ||      \
1375 			 MSGU_SCRATCHPAD1_ILA_STATE_ERR(x) ||       \
1376 			 MSGU_SCRATCHPAD1_BOOTLDR_STATE_ERR(x) ||   \
1377 			 MSGU_SCRATCHPAD1_IOP0_STATE_ERR(x) ||      \
1378 			 MSGU_SCRATCHPAD1_IOP1_STATE_ERR(x))
1379 
1380 /* bit definition for ODMR register */
1381 #define ODMR_MASK_ALL			0xFFFFFFFF/* mask all
1382 					interrupt vector */
1383 #define ODMR_CLEAR_ALL			0	/* clear all
1384 					interrupt vector */
1385 /* bit definition for ODCR register */
1386 #define ODCR_CLEAR_ALL			0xFFFFFFFF /* mask all
1387 					interrupt vector*/
1388 /* MSIX Interupts */
1389 #define MSIX_TABLE_OFFSET		0x2000
1390 #define MSIX_TABLE_ELEMENT_SIZE		0x10
1391 #define MSIX_INTERRUPT_CONTROL_OFFSET	0xC
1392 #define MSIX_TABLE_BASE			(MSIX_TABLE_OFFSET + \
1393 					MSIX_INTERRUPT_CONTROL_OFFSET)
1394 #define MSIX_INTERRUPT_DISABLE		0x1
1395 #define MSIX_INTERRUPT_ENABLE		0x0
1396 
1397 /* state definition for Scratch Pad1 register */
1398 #define SCRATCH_PAD_RAAE_READY		0x3
1399 #define SCRATCH_PAD_ILA_READY		0xC
1400 #define SCRATCH_PAD_BOOT_LOAD_SUCCESS	0x0
1401 #define SCRATCH_PAD_IOP0_READY		0xC00
1402 #define SCRATCH_PAD_IOP1_READY		0x3000
1403 #define SCRATCH_PAD_MIPSALL_READY_16PORT	(SCRATCH_PAD_IOP1_READY | \
1404 					SCRATCH_PAD_IOP0_READY | \
1405 					SCRATCH_PAD_ILA_READY | \
1406 					SCRATCH_PAD_RAAE_READY)
1407 #define SCRATCH_PAD_MIPSALL_READY_8PORT	(SCRATCH_PAD_IOP0_READY | \
1408 					SCRATCH_PAD_ILA_READY | \
1409 					SCRATCH_PAD_RAAE_READY)
1410 
1411 /* boot loader state */
1412 #define SCRATCH_PAD1_BOOTSTATE_MASK		0x70	/* Bit 4-6 */
1413 #define SCRATCH_PAD1_BOOTSTATE_SUCESS		0x0	/* Load successful */
1414 #define SCRATCH_PAD1_BOOTSTATE_HDA_SEEPROM	0x10	/* HDA SEEPROM */
1415 #define SCRATCH_PAD1_BOOTSTATE_HDA_BOOTSTRAP	0x20	/* HDA BootStrap Pins */
1416 #define SCRATCH_PAD1_BOOTSTATE_HDA_SOFTRESET	0x30	/* HDA Soft Reset */
1417 #define SCRATCH_PAD1_BOOTSTATE_CRIT_ERROR	0x40	/* HDA critical error */
1418 #define SCRATCH_PAD1_BOOTSTATE_R1		0x50	/* Reserved */
1419 #define SCRATCH_PAD1_BOOTSTATE_R2		0x60	/* Reserved */
1420 #define SCRATCH_PAD1_BOOTSTATE_FATAL		0x70	/* Fatal Error */
1421 
1422  /* state definition for Scratch Pad2 register */
1423 #define SCRATCH_PAD2_POR		0x00	/* power on state */
1424 #define SCRATCH_PAD2_SFR		0x01	/* soft reset state */
1425 #define SCRATCH_PAD2_ERR		0x02	/* error state */
1426 #define SCRATCH_PAD2_RDY		0x03	/* ready state */
1427 #define SCRATCH_PAD2_FWRDY_RST		0x04	/* FW rdy for soft reset flag */
1428 #define SCRATCH_PAD2_IOPRDY_RST		0x08	/* IOP ready for soft reset */
1429 #define SCRATCH_PAD2_STATE_MASK		0xFFFFFFF4 /* ScratchPad 2
1430  Mask, bit1-0 State */
1431 #define SCRATCH_PAD2_RESERVED		0x000003FC/* Scratch Pad1
1432  Reserved bit 2 to 9 */
1433 
1434 #define SCRATCH_PAD_ERROR_MASK		0xFFFFFC00 /* Error mask bits */
1435 #define SCRATCH_PAD_STATE_MASK		0x00000003 /* State Mask bits */
1436 
1437 /*state definition for Scratchpad Rsvd 0, Offset 0x6C, Non-fatal*/
1438 #define NON_FATAL_SPBC_LBUS_ECC_ERR	0x70000001
1439 #define NON_FATAL_BDMA_ERR		0xE0000001
1440 #define NON_FATAL_THERM_OVERTEMP_ERR	0x80000001
1441 
1442 /* main configuration offset - byte offset */
1443 #define MAIN_SIGNATURE_OFFSET		0x00 /* DWORD 0x00 */
1444 #define MAIN_INTERFACE_REVISION		0x04 /* DWORD 0x01 */
1445 #define MAIN_FW_REVISION		0x08 /* DWORD 0x02 */
1446 #define MAIN_MAX_OUTSTANDING_IO_OFFSET	0x0C /* DWORD 0x03 */
1447 #define MAIN_MAX_SGL_OFFSET		0x10 /* DWORD 0x04 */
1448 #define MAIN_CNTRL_CAP_OFFSET		0x14 /* DWORD 0x05 */
1449 #define MAIN_GST_OFFSET			0x18 /* DWORD 0x06 */
1450 #define MAIN_IBQ_OFFSET			0x1C /* DWORD 0x07 */
1451 #define MAIN_OBQ_OFFSET			0x20 /* DWORD 0x08 */
1452 #define MAIN_IQNPPD_HPPD_OFFSET		0x24 /* DWORD 0x09 */
1453 
1454 /* 0x28 - 0x4C - RSVD */
1455 #define MAIN_EVENT_CRC_CHECK		0x48 /* DWORD 0x12 */
1456 #define MAIN_EVENT_LOG_ADDR_HI		0x50 /* DWORD 0x14 */
1457 #define MAIN_EVENT_LOG_ADDR_LO		0x54 /* DWORD 0x15 */
1458 #define MAIN_EVENT_LOG_BUFF_SIZE	0x58 /* DWORD 0x16 */
1459 #define MAIN_EVENT_LOG_OPTION		0x5C /* DWORD 0x17 */
1460 #define MAIN_PCS_EVENT_LOG_ADDR_HI	0x60 /* DWORD 0x18 */
1461 #define MAIN_PCS_EVENT_LOG_ADDR_LO	0x64 /* DWORD 0x19 */
1462 #define MAIN_PCS_EVENT_LOG_BUFF_SIZE	0x68 /* DWORD 0x1A */
1463 #define MAIN_PCS_EVENT_LOG_OPTION	0x6C /* DWORD 0x1B */
1464 #define MAIN_FATAL_ERROR_INTERRUPT	0x70 /* DWORD 0x1C */
1465 #define MAIN_FATAL_ERROR_RDUMP0_OFFSET	0x74 /* DWORD 0x1D */
1466 #define MAIN_FATAL_ERROR_RDUMP0_LENGTH	0x78 /* DWORD 0x1E */
1467 #define MAIN_FATAL_ERROR_RDUMP1_OFFSET	0x7C /* DWORD 0x1F */
1468 #define MAIN_FATAL_ERROR_RDUMP1_LENGTH	0x80 /* DWORD 0x20 */
1469 #define MAIN_GPIO_LED_FLAGS_OFFSET	0x84 /* DWORD 0x21 */
1470 #define MAIN_ANALOG_SETUP_OFFSET	0x88 /* DWORD 0x22 */
1471 
1472 #define MAIN_INT_VECTOR_TABLE_OFFSET	0x8C /* DWORD 0x23 */
1473 #define MAIN_SAS_PHY_ATTR_TABLE_OFFSET	0x90 /* DWORD 0x24 */
1474 #define MAIN_PORT_RECOVERY_TIMER	0x94 /* DWORD 0x25 */
1475 #define MAIN_INT_REASSERTION_DELAY	0x98 /* DWORD 0x26 */
1476 #define MAIN_MPI_ILA_RELEASE_TYPE	0xA4 /* DWORD 0x29 */
1477 #define MAIN_MPI_INACTIVE_FW_VERSION	0XB0 /* DWORD 0x2C */
1478 
1479 /* Gereral Status Table offset - byte offset */
1480 #define GST_GSTLEN_MPIS_OFFSET		0x00
1481 #define GST_IQ_FREEZE_STATE0_OFFSET	0x04
1482 #define GST_IQ_FREEZE_STATE1_OFFSET	0x08
1483 #define GST_MSGUTCNT_OFFSET		0x0C
1484 #define GST_IOPTCNT_OFFSET		0x10
1485 /* 0x14 - 0x34 - RSVD */
1486 #define GST_GPIO_INPUT_VAL		0x38
1487 /* 0x3c - 0x40 - RSVD */
1488 #define GST_RERRINFO_OFFSET0		0x44
1489 #define GST_RERRINFO_OFFSET1		0x48
1490 #define GST_RERRINFO_OFFSET2		0x4c
1491 #define GST_RERRINFO_OFFSET3		0x50
1492 #define GST_RERRINFO_OFFSET4		0x54
1493 #define GST_RERRINFO_OFFSET5		0x58
1494 #define GST_RERRINFO_OFFSET6		0x5c
1495 #define GST_RERRINFO_OFFSET7		0x60
1496 
1497 /* General Status Table - MPI state */
1498 #define GST_MPI_STATE_UNINIT		0x00
1499 #define GST_MPI_STATE_INIT		0x01
1500 #define GST_MPI_STATE_TERMINATION	0x02
1501 #define GST_MPI_STATE_ERROR		0x03
1502 #define GST_MPI_STATE_MASK		0x07
1503 
1504 /* Per SAS PHY Attributes */
1505 
1506 #define PSPA_PHYSTATE0_OFFSET		0x00 /* Dword V */
1507 #define PSPA_OB_HW_EVENT_PID0_OFFSET	0x04 /* DWORD V+1 */
1508 #define PSPA_PHYSTATE1_OFFSET		0x08 /* Dword V+2 */
1509 #define PSPA_OB_HW_EVENT_PID1_OFFSET	0x0C /* DWORD V+3 */
1510 #define PSPA_PHYSTATE2_OFFSET		0x10 /* Dword V+4 */
1511 #define PSPA_OB_HW_EVENT_PID2_OFFSET	0x14 /* DWORD V+5 */
1512 #define PSPA_PHYSTATE3_OFFSET		0x18 /* Dword V+6 */
1513 #define PSPA_OB_HW_EVENT_PID3_OFFSET	0x1C /* DWORD V+7 */
1514 #define PSPA_PHYSTATE4_OFFSET		0x20 /* Dword V+8 */
1515 #define PSPA_OB_HW_EVENT_PID4_OFFSET	0x24 /* DWORD V+9 */
1516 #define PSPA_PHYSTATE5_OFFSET		0x28 /* Dword V+10 */
1517 #define PSPA_OB_HW_EVENT_PID5_OFFSET	0x2C /* DWORD V+11 */
1518 #define PSPA_PHYSTATE6_OFFSET		0x30 /* Dword V+12 */
1519 #define PSPA_OB_HW_EVENT_PID6_OFFSET	0x34 /* DWORD V+13 */
1520 #define PSPA_PHYSTATE7_OFFSET		0x38 /* Dword V+14 */
1521 #define PSPA_OB_HW_EVENT_PID7_OFFSET	0x3C /* DWORD V+15 */
1522 #define PSPA_PHYSTATE8_OFFSET		0x40 /* DWORD V+16 */
1523 #define PSPA_OB_HW_EVENT_PID8_OFFSET	0x44 /* DWORD V+17 */
1524 #define PSPA_PHYSTATE9_OFFSET		0x48 /* DWORD V+18 */
1525 #define PSPA_OB_HW_EVENT_PID9_OFFSET	0x4C /* DWORD V+19 */
1526 #define PSPA_PHYSTATE10_OFFSET		0x50 /* DWORD V+20 */
1527 #define PSPA_OB_HW_EVENT_PID10_OFFSET	0x54 /* DWORD V+21 */
1528 #define PSPA_PHYSTATE11_OFFSET		0x58 /* DWORD V+22 */
1529 #define PSPA_OB_HW_EVENT_PID11_OFFSET	0x5C /* DWORD V+23 */
1530 #define PSPA_PHYSTATE12_OFFSET		0x60 /* DWORD V+24 */
1531 #define PSPA_OB_HW_EVENT_PID12_OFFSET	0x64 /* DWORD V+25 */
1532 #define PSPA_PHYSTATE13_OFFSET		0x68 /* DWORD V+26 */
1533 #define PSPA_OB_HW_EVENT_PID13_OFFSET	0x6c /* DWORD V+27 */
1534 #define PSPA_PHYSTATE14_OFFSET		0x70 /* DWORD V+28 */
1535 #define PSPA_OB_HW_EVENT_PID14_OFFSET	0x74 /* DWORD V+29 */
1536 #define PSPA_PHYSTATE15_OFFSET		0x78 /* DWORD V+30 */
1537 #define PSPA_OB_HW_EVENT_PID15_OFFSET	0x7c /* DWORD V+31 */
1538 /* end PSPA */
1539 
1540 /* inbound queue configuration offset - byte offset */
1541 #define IB_PROPERITY_OFFSET		0x00
1542 #define IB_BASE_ADDR_HI_OFFSET		0x04
1543 #define IB_BASE_ADDR_LO_OFFSET		0x08
1544 #define IB_CI_BASE_ADDR_HI_OFFSET	0x0C
1545 #define IB_CI_BASE_ADDR_LO_OFFSET	0x10
1546 #define IB_PIPCI_BAR			0x14
1547 #define IB_PIPCI_BAR_OFFSET		0x18
1548 #define IB_RESERVED_OFFSET		0x1C
1549 
1550 /* outbound queue configuration offset - byte offset */
1551 #define OB_PROPERITY_OFFSET		0x00
1552 #define OB_BASE_ADDR_HI_OFFSET		0x04
1553 #define OB_BASE_ADDR_LO_OFFSET		0x08
1554 #define OB_PI_BASE_ADDR_HI_OFFSET	0x0C
1555 #define OB_PI_BASE_ADDR_LO_OFFSET	0x10
1556 #define OB_CIPCI_BAR			0x14
1557 #define OB_CIPCI_BAR_OFFSET		0x18
1558 #define OB_INTERRUPT_COALES_OFFSET	0x1C
1559 #define OB_DYNAMIC_COALES_OFFSET	0x20
1560 #define OB_PROPERTY_INT_ENABLE		0x40000000
1561 
1562 #define MBIC_NMI_ENABLE_VPE0_IOP	0x000418
1563 #define MBIC_NMI_ENABLE_VPE0_AAP1	0x000418
1564 /* PCIE registers - BAR2(0x18), BAR1(win) 0x010000 */
1565 #define PCIE_EVENT_INTERRUPT_ENABLE	0x003040
1566 #define PCIE_EVENT_INTERRUPT		0x003044
1567 #define PCIE_ERROR_INTERRUPT_ENABLE	0x003048
1568 #define PCIE_ERROR_INTERRUPT		0x00304C
1569 
1570 /* SPCV soft reset */
1571 #define SPC_REG_SOFT_RESET 0x00001000
1572 #define SPCv_NORMAL_RESET_VALUE		0x1
1573 
1574 #define SPCv_SOFT_RESET_READ_MASK		0xC0
1575 #define SPCv_SOFT_RESET_NO_RESET		0x0
1576 #define SPCv_SOFT_RESET_NORMAL_RESET_OCCURED	0x40
1577 #define SPCv_SOFT_RESET_HDA_MODE_OCCURED	0x80
1578 #define SPCv_SOFT_RESET_CHIP_RESET_OCCURED	0xC0
1579 
1580 /* signature definition for host scratch pad0 register */
1581 #define SPC_SOFT_RESET_SIGNATURE	0x252acbcd
1582 /* Signature for Soft Reset */
1583 
1584 /* SPC Reset register - BAR4(0x20), BAR2(win) (need dynamic mapping) */
1585 #define SPC_REG_RESET			0x000000/* reset register */
1586 
1587 /* bit definition for SPC_RESET register */
1588 #define SPC_REG_RESET_OSSP		0x00000001
1589 #define SPC_REG_RESET_RAAE		0x00000002
1590 #define SPC_REG_RESET_PCS_SPBC		0x00000004
1591 #define SPC_REG_RESET_PCS_IOP_SS	0x00000008
1592 #define SPC_REG_RESET_PCS_AAP1_SS	0x00000010
1593 #define SPC_REG_RESET_PCS_AAP2_SS	0x00000020
1594 #define SPC_REG_RESET_PCS_LM		0x00000040
1595 #define SPC_REG_RESET_PCS		0x00000080
1596 #define SPC_REG_RESET_GSM		0x00000100
1597 #define SPC_REG_RESET_DDR2		0x00010000
1598 #define SPC_REG_RESET_BDMA_CORE		0x00020000
1599 #define SPC_REG_RESET_BDMA_SXCBI	0x00040000
1600 #define SPC_REG_RESET_PCIE_AL_SXCBI	0x00080000
1601 #define SPC_REG_RESET_PCIE_PWR		0x00100000
1602 #define SPC_REG_RESET_PCIE_SFT		0x00200000
1603 #define SPC_REG_RESET_PCS_SXCBI		0x00400000
1604 #define SPC_REG_RESET_LMS_SXCBI		0x00800000
1605 #define SPC_REG_RESET_PMIC_SXCBI	0x01000000
1606 #define SPC_REG_RESET_PMIC_CORE		0x02000000
1607 #define SPC_REG_RESET_PCIE_PC_SXCBI	0x04000000
1608 #define SPC_REG_RESET_DEVICE		0x80000000
1609 
1610 /* registers for BAR Shifting - BAR2(0x18), BAR1(win) */
1611 #define SPCV_IBW_AXI_TRANSLATION_LOW	0x001010
1612 
1613 #define MBIC_AAP1_ADDR_BASE		0x060000
1614 #define MBIC_IOP_ADDR_BASE		0x070000
1615 #define GSM_ADDR_BASE			0x0700000
1616 /* Dynamic map through Bar4 - 0x00700000 */
1617 #define GSM_CONFIG_RESET		0x00000000
1618 #define RAM_ECC_DB_ERR			0x00000018
1619 #define GSM_READ_ADDR_PARITY_INDIC	0x00000058
1620 #define GSM_WRITE_ADDR_PARITY_INDIC	0x00000060
1621 #define GSM_WRITE_DATA_PARITY_INDIC	0x00000068
1622 #define GSM_READ_ADDR_PARITY_CHECK	0x00000038
1623 #define GSM_WRITE_ADDR_PARITY_CHECK	0x00000040
1624 #define GSM_WRITE_DATA_PARITY_CHECK	0x00000048
1625 
1626 #define RB6_ACCESS_REG			0x6A0000
1627 #define HDAC_EXEC_CMD			0x0002
1628 #define HDA_C_PA			0xcb
1629 #define HDA_SEQ_ID_BITS			0x00ff0000
1630 #define HDA_GSM_OFFSET_BITS		0x00FFFFFF
1631 #define HDA_GSM_CMD_OFFSET_BITS		0x42C0
1632 #define HDA_GSM_RSP_OFFSET_BITS		0x42E0
1633 
1634 #define MBIC_AAP1_ADDR_BASE		0x060000
1635 #define MBIC_IOP_ADDR_BASE		0x070000
1636 #define GSM_ADDR_BASE			0x0700000
1637 #define SPC_TOP_LEVEL_ADDR_BASE		0x000000
1638 #define GSM_CONFIG_RESET_VALUE		0x00003b00
1639 #define GPIO_ADDR_BASE			0x00090000
1640 #define GPIO_GPIO_0_0UTPUT_CTL_OFFSET	0x0000010c
1641 
1642 /* RB6 offset */
1643 #define SPC_RB6_OFFSET			0x80C0
1644 /* Magic number of soft reset for RB6 */
1645 #define RB6_MAGIC_NUMBER_RST		0x1234
1646 
1647 /* Device Register status */
1648 #define DEVREG_SUCCESS					0x00
1649 #define DEVREG_FAILURE_OUT_OF_RESOURCE			0x01
1650 #define DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED	0x02
1651 #define DEVREG_FAILURE_INVALID_PHY_ID			0x03
1652 #define DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED	0x04
1653 #define DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE		0x05
1654 #define DEVREG_FAILURE_PORT_NOT_VALID_STATE		0x06
1655 #define DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID		0x07
1656 
1657 
1658 #define MEMBASE_II_SHIFT_REGISTER       0x1010
1659 #endif
1660 
1661 /**
1662  * As we know sleep (1~20) ms may result in sleep longer than ~20 ms, hence we
1663  * choose 20 ms interval.
1664  */
1665 #define FW_READY_INTERVAL	20
1666