1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * r8a7779 processor support - PFC hardware block 4 * 5 * Copyright (C) 2011, 2013 Renesas Solutions Corp. 6 * Copyright (C) 2011 Magnus Damm 7 * Copyright (C) 2013 Cogent Embedded, Inc. 8 */ 9 10 #include <linux/kernel.h> 11 12 #include "sh_pfc.h" 13 14 #define CPU_ALL_GP(fn, sfx) \ 15 PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 16 PORT_GP_CFG_32(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 17 PORT_GP_CFG_1(2, 0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 18 PORT_GP_1(2, 1, fn, sfx), \ 19 PORT_GP_1(2, 2, fn, sfx), \ 20 PORT_GP_1(2, 3, fn, sfx), \ 21 PORT_GP_1(2, 4, fn, sfx), \ 22 PORT_GP_1(2, 5, fn, sfx), \ 23 PORT_GP_1(2, 6, fn, sfx), \ 24 PORT_GP_1(2, 7, fn, sfx), \ 25 PORT_GP_1(2, 8, fn, sfx), \ 26 PORT_GP_1(2, 9, fn, sfx), \ 27 PORT_GP_1(2, 10, fn, sfx), \ 28 PORT_GP_1(2, 11, fn, sfx), \ 29 PORT_GP_1(2, 12, fn, sfx), \ 30 PORT_GP_1(2, 13, fn, sfx), \ 31 PORT_GP_1(2, 14, fn, sfx), \ 32 PORT_GP_1(2, 15, fn, sfx), \ 33 PORT_GP_1(2, 16, fn, sfx), \ 34 PORT_GP_1(2, 17, fn, sfx), \ 35 PORT_GP_1(2, 18, fn, sfx), \ 36 PORT_GP_1(2, 19, fn, sfx), \ 37 PORT_GP_1(2, 20, fn, sfx), \ 38 PORT_GP_1(2, 21, fn, sfx), \ 39 PORT_GP_1(2, 22, fn, sfx), \ 40 PORT_GP_1(2, 23, fn, sfx), \ 41 PORT_GP_1(2, 24, fn, sfx), \ 42 PORT_GP_1(2, 25, fn, sfx), \ 43 PORT_GP_1(2, 26, fn, sfx), \ 44 PORT_GP_1(2, 27, fn, sfx), \ 45 PORT_GP_1(2, 28, fn, sfx), \ 46 PORT_GP_1(2, 29, fn, sfx), \ 47 PORT_GP_CFG_1(2, 30, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 48 PORT_GP_CFG_1(2, 31, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 49 PORT_GP_CFG_25(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 50 PORT_GP_1(3, 25, fn, sfx), \ 51 PORT_GP_1(3, 26, fn, sfx), \ 52 PORT_GP_1(3, 27, fn, sfx), \ 53 PORT_GP_CFG_1(3, 28, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 54 PORT_GP_CFG_1(3, 29, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 55 PORT_GP_CFG_1(3, 30, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 56 PORT_GP_CFG_1(3, 31, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 57 PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 58 PORT_GP_CFG_32(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 59 PORT_GP_CFG_9(6, fn, sfx, SH_PFC_PIN_CFG_PULL_UP) 60 61 #define CPU_ALL_NOGP(fn) \ 62 PIN_NOGP_CFG(ASEBRK_N_ACK, "ASEBRK#/ACK", fn, SH_PFC_PIN_CFG_PULL_UP), \ 63 PIN_NOGP_CFG(D0, "D0", fn, SH_PFC_PIN_CFG_PULL_UP), \ 64 PIN_NOGP_CFG(D1, "D1", fn, SH_PFC_PIN_CFG_PULL_UP), \ 65 PIN_NOGP_CFG(D2, "D2", fn, SH_PFC_PIN_CFG_PULL_UP), \ 66 PIN_NOGP_CFG(D3, "D3", fn, SH_PFC_PIN_CFG_PULL_UP), \ 67 PIN_NOGP_CFG(D4, "D4", fn, SH_PFC_PIN_CFG_PULL_UP), \ 68 PIN_NOGP_CFG(D5, "D5", fn, SH_PFC_PIN_CFG_PULL_UP), \ 69 PIN_NOGP_CFG(D6, "D6", fn, SH_PFC_PIN_CFG_PULL_UP), \ 70 PIN_NOGP_CFG(D7, "D7", fn, SH_PFC_PIN_CFG_PULL_UP), \ 71 PIN_NOGP_CFG(D8, "D8", fn, SH_PFC_PIN_CFG_PULL_UP), \ 72 PIN_NOGP_CFG(D9, "D9", fn, SH_PFC_PIN_CFG_PULL_UP), \ 73 PIN_NOGP_CFG(D10, "D10", fn, SH_PFC_PIN_CFG_PULL_UP), \ 74 PIN_NOGP_CFG(D11, "D11", fn, SH_PFC_PIN_CFG_PULL_UP), \ 75 PIN_NOGP_CFG(D12, "D12", fn, SH_PFC_PIN_CFG_PULL_UP), \ 76 PIN_NOGP_CFG(D13, "D13", fn, SH_PFC_PIN_CFG_PULL_UP), \ 77 PIN_NOGP_CFG(D14, "D14", fn, SH_PFC_PIN_CFG_PULL_UP), \ 78 PIN_NOGP_CFG(D15, "D15", fn, SH_PFC_PIN_CFG_PULL_UP), \ 79 PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP), \ 80 PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \ 81 PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \ 82 PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_PULL_UP), \ 83 PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \ 84 PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP) 85 86 enum { 87 PINMUX_RESERVED = 0, 88 89 PINMUX_DATA_BEGIN, 90 GP_ALL(DATA), /* GP_0_0_DATA -> GP_6_8_DATA */ 91 PINMUX_DATA_END, 92 93 PINMUX_FUNCTION_BEGIN, 94 GP_ALL(FN), /* GP_0_0_FN -> GP_6_8_FN */ 95 96 /* GPSR0 */ 97 FN_AVS1, FN_AVS2, FN_IP0_7_6, FN_A17, 98 FN_A18, FN_A19, FN_IP0_9_8, FN_IP0_11_10, 99 FN_IP0_13_12, FN_IP0_15_14, FN_IP0_18_16, FN_IP0_22_19, 100 FN_IP0_24_23, FN_IP0_25, FN_IP0_27_26, FN_IP1_1_0, 101 FN_IP1_3_2, FN_IP1_6_4, FN_IP1_10_7, FN_IP1_14_11, 102 FN_IP1_18_15, FN_IP0_5_3, FN_IP0_30_28, FN_IP2_18_16, 103 FN_IP2_21_19, FN_IP2_30_28, FN_IP3_2_0, FN_IP3_11_9, 104 FN_IP3_14_12, FN_IP3_22_21, FN_IP3_26_24, FN_IP3_31_29, 105 106 /* GPSR1 */ 107 FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5, FN_IP4_10_8, 108 FN_IP4_11, FN_IP4_12, FN_IP4_13, FN_IP4_14, 109 FN_IP4_15, FN_IP4_16, FN_IP4_19_17, FN_IP4_22_20, 110 FN_IP4_23, FN_IP4_24, FN_IP4_25, FN_IP4_26, 111 FN_IP4_27, FN_IP4_28, FN_IP4_31_29, FN_IP5_2_0, 112 FN_IP5_3, FN_IP5_4, FN_IP5_5, FN_IP5_6, 113 FN_IP5_7, FN_IP5_8, FN_IP5_10_9, FN_IP5_12_11, 114 FN_IP5_14_13, FN_IP5_16_15, FN_IP5_20_17, FN_IP5_23_21, 115 116 /* GPSR2 */ 117 FN_IP5_27_24, FN_IP8_20, FN_IP8_22_21, FN_IP8_24_23, 118 FN_IP8_27_25, FN_IP8_30_28, FN_IP9_1_0, FN_IP9_3_2, 119 FN_IP9_4, FN_IP9_5, FN_IP9_6, FN_IP9_7, 120 FN_IP9_9_8, FN_IP9_11_10, FN_IP9_13_12, FN_IP9_15_14, 121 FN_IP9_18_16, FN_IP9_21_19, FN_IP9_23_22, FN_IP9_25_24, 122 FN_IP9_27_26, FN_IP9_29_28, FN_IP10_2_0, FN_IP10_5_3, 123 FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_17_15, 124 FN_IP10_20_18, FN_IP10_23_21, FN_IP10_25_24, FN_IP10_28_26, 125 126 /* GPSR3 */ 127 FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6, 128 FN_IP11_11_9, FN_IP11_14_12, FN_IP11_17_15, FN_IP11_20_18, 129 FN_IP11_23_21, FN_IP11_26_24, FN_IP11_29_27, FN_IP12_2_0, 130 FN_IP12_5_3, FN_IP12_8_6, FN_IP12_11_9, FN_IP12_14_12, 131 FN_IP12_17_15, FN_IP7_16_15, FN_IP7_18_17, FN_IP7_28_27, 132 FN_IP7_30_29, FN_IP7_20_19, FN_IP7_22_21, FN_IP7_24_23, 133 FN_IP7_26_25, FN_IP1_20_19, FN_IP1_22_21, FN_IP1_24_23, 134 FN_IP5_28, FN_IP5_30_29, FN_IP6_1_0, FN_IP6_3_2, 135 136 /* GPSR4 */ 137 FN_IP6_5_4, FN_IP6_7_6, FN_IP6_8, FN_IP6_11_9, 138 FN_IP6_14_12, FN_IP6_17_15, FN_IP6_19_18, FN_IP6_22_20, 139 FN_IP6_24_23, FN_IP6_26_25, FN_IP6_30_29, FN_IP7_1_0, 140 FN_IP7_3_2, FN_IP7_6_4, FN_IP7_9_7, FN_IP7_12_10, 141 FN_IP7_14_13, FN_IP2_7_4, FN_IP2_11_8, FN_IP2_15_12, 142 FN_IP1_28_25, FN_IP2_3_0, FN_IP8_3_0, FN_IP8_7_4, 143 FN_IP8_11_8, FN_IP8_15_12, FN_USB_PENC0, FN_USB_PENC1, 144 FN_IP0_2_0, FN_IP8_17_16, FN_IP8_18, FN_IP8_19, 145 146 /* GPSR5 */ 147 FN_A1, FN_A2, FN_A3, FN_A4, 148 FN_A5, FN_A6, FN_A7, FN_A8, 149 FN_A9, FN_A10, FN_A11, FN_A12, 150 FN_A13, FN_A14, FN_A15, FN_A16, 151 FN_RD, FN_WE0, FN_WE1, FN_EX_WAIT0, 152 FN_IP3_23, FN_IP3_27, FN_IP3_28, FN_IP2_22, 153 FN_IP2_23, FN_IP2_24, FN_IP2_25, FN_IP2_26, 154 FN_IP2_27, FN_IP3_3, FN_IP3_4, FN_IP3_5, 155 156 /* GPSR6 */ 157 FN_IP3_6, FN_IP3_7, FN_IP3_8, FN_IP3_15, 158 FN_IP3_16, FN_IP3_17, FN_IP3_18, FN_IP3_19, 159 FN_IP3_20, 160 161 /* IPSR0 */ 162 FN_RD_WR, FN_FWE, FN_ATAG0, FN_VI1_R7, 163 FN_HRTS1, FN_RX4_C, 164 FN_CS1_A26, FN_HSPI_TX2, FN_SDSELF_B, 165 FN_CS0, FN_HSPI_CS2_B, 166 FN_CLKOUT, FN_TX3C_IRDA_TX_C, FN_PWM0_B, 167 FN_A25, FN_SD1_WP, FN_MMC0_D5, FN_FD5, 168 FN_HSPI_RX2, FN_VI1_R3, FN_TX5_B, FN_SSI_SDATA7_B, 169 FN_CTS0_B, 170 FN_A24, FN_SD1_CD, FN_MMC0_D4, FN_FD4, 171 FN_HSPI_CS2, FN_VI1_R2, FN_SSI_WS78_B, 172 FN_A23, FN_FCLE, FN_HSPI_CLK2, FN_VI1_R1, 173 FN_A22, FN_RX5_D, FN_HSPI_RX2_B, FN_VI1_R0, 174 FN_A21, FN_SCK5_D, FN_HSPI_CLK2_B, 175 FN_A20, FN_TX5_D, FN_HSPI_TX2_B, 176 FN_A0, FN_SD1_DAT3, FN_MMC0_D3, FN_FD3, 177 FN_BS, FN_SD1_DAT2, FN_MMC0_D2, FN_FD2, 178 FN_ATADIR0, FN_SDSELF, FN_HCTS1, FN_TX4_C, 179 FN_USB_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0, 180 FN_SCIF_CLK, FN_TCLK0_C, 181 182 /* IPSR1 */ 183 FN_EX_CS0, FN_RX3_C_IRDA_RX_C, FN_MMC0_D6, 184 FN_FD6, FN_EX_CS1, FN_MMC0_D7, FN_FD7, 185 FN_EX_CS2, FN_SD1_CLK, FN_MMC0_CLK, FN_FALE, 186 FN_ATACS00, FN_EX_CS3, FN_SD1_CMD, FN_MMC0_CMD, 187 FN_FRE, FN_ATACS10, FN_VI1_R4, FN_RX5_B, 188 FN_HSCK1, FN_SSI_SDATA8_B, FN_RTS0_B_TANS_B, FN_SSI_SDATA9, 189 FN_EX_CS4, FN_SD1_DAT0, FN_MMC0_D0, FN_FD0, 190 FN_ATARD0, FN_VI1_R5, FN_SCK5_B, FN_HTX1, 191 FN_TX2_E, FN_TX0_B, FN_SSI_SCK9, FN_EX_CS5, 192 FN_SD1_DAT1, FN_MMC0_D1, FN_FD1, FN_ATAWR0, 193 FN_VI1_R6, FN_HRX1, FN_RX2_E, FN_RX0_B, 194 FN_SSI_WS9, FN_MLB_CLK, FN_PWM2, FN_SCK4, 195 FN_MLB_SIG, FN_PWM3, FN_TX4, FN_MLB_DAT, 196 FN_PWM4, FN_RX4, FN_HTX0, FN_TX1, 197 FN_SDATA, FN_CTS0_C, FN_SUB_TCK, FN_CC5_STATE2, 198 FN_CC5_STATE10, FN_CC5_STATE18, FN_CC5_STATE26, FN_CC5_STATE34, 199 200 /* IPSR2 */ 201 FN_HRX0, FN_RX1, FN_SCKZ, FN_RTS0_C_TANS_C, 202 FN_SUB_TDI, FN_CC5_STATE3, FN_CC5_STATE11, FN_CC5_STATE19, 203 FN_CC5_STATE27, FN_CC5_STATE35, FN_HSCK0, FN_SCK1, 204 FN_MTS, FN_PWM5, FN_SCK0_C, FN_SSI_SDATA9_B, 205 FN_SUB_TDO, FN_CC5_STATE0, FN_CC5_STATE8, FN_CC5_STATE16, 206 FN_CC5_STATE24, FN_CC5_STATE32, FN_HCTS0, FN_CTS1, 207 FN_STM, FN_PWM0_D, FN_RX0_C, FN_SCIF_CLK_C, 208 FN_SUB_TRST, FN_TCLK1_B, FN_CC5_OSCOUT, FN_HRTS0, 209 FN_RTS1_TANS, FN_MDATA, FN_TX0_C, FN_SUB_TMS, 210 FN_CC5_STATE1, FN_CC5_STATE9, FN_CC5_STATE17, FN_CC5_STATE25, 211 FN_CC5_STATE33, FN_DU0_DR0, FN_LCDOUT0, FN_DREQ0, 212 FN_GPS_CLK_B, FN_AUDATA0, FN_TX5_C, FN_DU0_DR1, 213 FN_LCDOUT1, FN_DACK0, FN_DRACK0, FN_GPS_SIGN_B, 214 FN_AUDATA1, FN_RX5_C, FN_DU0_DR2, FN_LCDOUT2, 215 FN_DU0_DR3, FN_LCDOUT3, FN_DU0_DR4, FN_LCDOUT4, 216 FN_DU0_DR5, FN_LCDOUT5, FN_DU0_DR6, FN_LCDOUT6, 217 FN_DU0_DR7, FN_LCDOUT7, FN_DU0_DG0, FN_LCDOUT8, 218 FN_DREQ1, FN_SCL2, FN_AUDATA2, 219 220 /* IPSR3 */ 221 FN_DU0_DG1, FN_LCDOUT9, FN_DACK1, FN_SDA2, 222 FN_AUDATA3, FN_DU0_DG2, FN_LCDOUT10, FN_DU0_DG3, 223 FN_LCDOUT11, FN_DU0_DG4, FN_LCDOUT12, FN_DU0_DG5, 224 FN_LCDOUT13, FN_DU0_DG6, FN_LCDOUT14, FN_DU0_DG7, 225 FN_LCDOUT15, FN_DU0_DB0, FN_LCDOUT16, FN_EX_WAIT1, 226 FN_SCL1, FN_TCLK1, FN_AUDATA4, FN_DU0_DB1, 227 FN_LCDOUT17, FN_EX_WAIT2, FN_SDA1, FN_GPS_MAG_B, 228 FN_AUDATA5, FN_SCK5_C, FN_DU0_DB2, FN_LCDOUT18, 229 FN_DU0_DB3, FN_LCDOUT19, FN_DU0_DB4, FN_LCDOUT20, 230 FN_DU0_DB5, FN_LCDOUT21, FN_DU0_DB6, FN_LCDOUT22, 231 FN_DU0_DB7, FN_LCDOUT23, FN_DU0_DOTCLKIN, FN_QSTVA_QVS, 232 FN_TX3_D_IRDA_TX_D, FN_SCL3_B, FN_DU0_DOTCLKOUT0, FN_QCLK, 233 FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, FN_RX3_D_IRDA_RX_D, FN_SDA3_B, 234 FN_SDA2_C, FN_DACK0_B, FN_DRACK0_B, FN_DU0_EXHSYNC_DU0_HSYNC, 235 FN_QSTH_QHS, FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, 236 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CAN1_TX, 237 FN_TX2_C, FN_SCL2_C, FN_REMOCON, 238 239 /* IPSR4 */ 240 FN_DU0_DISP, FN_QPOLA, FN_CAN_CLK_C, FN_SCK2_C, 241 FN_DU0_CDE, FN_QPOLB, FN_CAN1_RX, FN_RX2_C, 242 FN_DREQ0_B, FN_SSI_SCK78_B, FN_SCK0_B, FN_DU1_DR0, 243 FN_VI2_DATA0_VI2_B0, FN_PWM6, FN_SD3_CLK, FN_TX3_E_IRDA_TX_E, 244 FN_AUDCK, FN_PWMFSW0_B, FN_DU1_DR1, FN_VI2_DATA1_VI2_B1, 245 FN_PWM0, FN_SD3_CMD, FN_RX3_E_IRDA_RX_E, FN_AUDSYNC, 246 FN_CTS0_D, FN_DU1_DR2, FN_VI2_G0, FN_DU1_DR3, 247 FN_VI2_G1, FN_DU1_DR4, FN_VI2_G2, FN_DU1_DR5, 248 FN_VI2_G3, FN_DU1_DR6, FN_VI2_G4, FN_DU1_DR7, 249 FN_VI2_G5, FN_DU1_DG0, FN_VI2_DATA2_VI2_B2, FN_SCL1_B, 250 FN_SD3_DAT2, FN_SCK3_E, FN_AUDATA6, FN_TX0_D, 251 FN_DU1_DG1, FN_VI2_DATA3_VI2_B3, FN_SDA1_B, FN_SD3_DAT3, 252 FN_SCK5, FN_AUDATA7, FN_RX0_D, FN_DU1_DG2, 253 FN_VI2_G6, FN_DU1_DG3, FN_VI2_G7, FN_DU1_DG4, 254 FN_VI2_R0, FN_DU1_DG5, FN_VI2_R1, FN_DU1_DG6, 255 FN_VI2_R2, FN_DU1_DG7, FN_VI2_R3, FN_DU1_DB0, 256 FN_VI2_DATA4_VI2_B4, FN_SCL2_B, FN_SD3_DAT0, FN_TX5, 257 FN_SCK0_D, 258 259 /* IPSR5 */ 260 FN_DU1_DB1, FN_VI2_DATA5_VI2_B5, FN_SDA2_B, FN_SD3_DAT1, 261 FN_RX5, FN_RTS0_D_TANS_D, FN_DU1_DB2, FN_VI2_R4, 262 FN_DU1_DB3, FN_VI2_R5, FN_DU1_DB4, FN_VI2_R6, 263 FN_DU1_DB5, FN_VI2_R7, FN_DU1_DB6, FN_SCL2_D, 264 FN_DU1_DB7, FN_SDA2_D, FN_DU1_DOTCLKIN, FN_VI2_CLKENB, 265 FN_HSPI_CS1, FN_SCL1_D, FN_DU1_DOTCLKOUT, FN_VI2_FIELD, 266 FN_SDA1_D, FN_DU1_EXHSYNC_DU1_HSYNC, FN_VI2_HSYNC, 267 FN_VI3_HSYNC, FN_DU1_EXVSYNC_DU1_VSYNC, FN_VI2_VSYNC, FN_VI3_VSYNC, 268 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_VI2_CLK, FN_TX3_B_IRDA_TX_B, 269 FN_SD3_CD, FN_HSPI_TX1, FN_VI1_CLKENB, FN_VI3_CLKENB, 270 FN_AUDIO_CLKC, FN_TX2_D, FN_SPEEDIN, FN_GPS_SIGN_D, 271 FN_DU1_DISP, FN_VI2_DATA6_VI2_B6, FN_TCLK0, FN_QSTVA_B_QVS_B, 272 FN_HSPI_CLK1, FN_SCK2_D, FN_AUDIO_CLKOUT_B, FN_GPS_MAG_D, 273 FN_DU1_CDE, FN_VI2_DATA7_VI2_B7, FN_RX3_B_IRDA_RX_B, 274 FN_SD3_WP, FN_HSPI_RX1, FN_VI1_FIELD, FN_VI3_FIELD, 275 FN_AUDIO_CLKOUT, FN_RX2_D, FN_GPS_CLK_C, FN_GPS_CLK_D, 276 FN_AUDIO_CLKA, FN_CAN_TXCLK, FN_AUDIO_CLKB, FN_USB_OVC2, 277 FN_CAN_DEBUGOUT0, FN_MOUT0, 278 279 /* IPSR6 */ 280 FN_SSI_SCK0129, FN_CAN_DEBUGOUT1, FN_MOUT1, FN_SSI_WS0129, 281 FN_CAN_DEBUGOUT2, FN_MOUT2, FN_SSI_SDATA0, FN_CAN_DEBUGOUT3, 282 FN_MOUT5, FN_SSI_SDATA1, FN_CAN_DEBUGOUT4, FN_MOUT6, 283 FN_SSI_SDATA2, FN_CAN_DEBUGOUT5, FN_SSI_SCK34, FN_CAN_DEBUGOUT6, 284 FN_CAN0_TX_B, FN_IERX, FN_SSI_SCK9_C, FN_SSI_WS34, 285 FN_CAN_DEBUGOUT7, FN_CAN0_RX_B, FN_IETX, FN_SSI_WS9_C, 286 FN_SSI_SDATA3, FN_PWM0_C, FN_CAN_DEBUGOUT8, FN_CAN_CLK_B, 287 FN_IECLK, FN_SCIF_CLK_B, FN_TCLK0_B, FN_SSI_SDATA4, 288 FN_CAN_DEBUGOUT9, FN_SSI_SDATA9_C, FN_SSI_SCK5, FN_ADICLK, 289 FN_CAN_DEBUGOUT10, FN_SCK3, FN_TCLK0_D, FN_SSI_WS5, 290 FN_ADICS_SAMP, FN_CAN_DEBUGOUT11, FN_TX3_IRDA_TX, FN_SSI_SDATA5, 291 FN_ADIDATA, FN_CAN_DEBUGOUT12, FN_RX3_IRDA_RX, FN_SSI_SCK6, 292 FN_ADICHS0, FN_CAN0_TX, FN_IERX_B, 293 294 /* IPSR7 */ 295 FN_SSI_WS6, FN_ADICHS1, FN_CAN0_RX, FN_IETX_B, 296 FN_SSI_SDATA6, FN_ADICHS2, FN_CAN_CLK, FN_IECLK_B, 297 FN_SSI_SCK78, FN_CAN_DEBUGOUT13, FN_IRQ0_B, FN_SSI_SCK9_B, 298 FN_HSPI_CLK1_C, FN_SSI_WS78, FN_CAN_DEBUGOUT14, FN_IRQ1_B, 299 FN_SSI_WS9_B, FN_HSPI_CS1_C, FN_SSI_SDATA7, FN_CAN_DEBUGOUT15, 300 FN_IRQ2_B, FN_TCLK1_C, FN_HSPI_TX1_C, FN_SSI_SDATA8, 301 FN_VSP, FN_IRQ3_B, FN_HSPI_RX1_C, FN_SD0_CLK, 302 FN_ATACS01, FN_SCK1_B, FN_SD0_CMD, FN_ATACS11, 303 FN_TX1_B, FN_CC5_TDO, FN_SD0_DAT0, FN_ATADIR1, 304 FN_RX1_B, FN_CC5_TRST, FN_SD0_DAT1, FN_ATAG1, 305 FN_SCK2_B, FN_CC5_TMS, FN_SD0_DAT2, FN_ATARD1, 306 FN_TX2_B, FN_CC5_TCK, FN_SD0_DAT3, FN_ATAWR1, 307 FN_RX2_B, FN_CC5_TDI, FN_SD0_CD, FN_DREQ2, 308 FN_RTS1_B_TANS_B, FN_SD0_WP, FN_DACK2, FN_CTS1_B, 309 310 /* IPSR8 */ 311 FN_HSPI_CLK0, FN_CTS0, FN_USB_OVC0, FN_AD_CLK, 312 FN_CC5_STATE4, FN_CC5_STATE12, FN_CC5_STATE20, FN_CC5_STATE28, 313 FN_CC5_STATE36, FN_HSPI_CS0, FN_RTS0_TANS, FN_USB_OVC1, 314 FN_AD_DI, FN_CC5_STATE5, FN_CC5_STATE13, FN_CC5_STATE21, 315 FN_CC5_STATE29, FN_CC5_STATE37, FN_HSPI_TX0, FN_TX0, 316 FN_CAN_DEBUG_HW_TRIGGER, FN_AD_DO, FN_CC5_STATE6, FN_CC5_STATE14, 317 FN_CC5_STATE22, FN_CC5_STATE30, FN_CC5_STATE38, FN_HSPI_RX0, 318 FN_RX0, FN_CAN_STEP0, FN_AD_NCS, FN_CC5_STATE7, 319 FN_CC5_STATE15, FN_CC5_STATE23, FN_CC5_STATE31, FN_CC5_STATE39, 320 FN_FMCLK, FN_RDS_CLK, FN_PCMOE, FN_BPFCLK, 321 FN_PCMWE, FN_FMIN, FN_RDS_DATA, FN_VI0_CLK, 322 FN_MMC1_CLK, FN_VI0_CLKENB, FN_TX1_C, FN_HTX1_B, 323 FN_MT1_SYNC, FN_VI0_FIELD, FN_RX1_C, FN_HRX1_B, 324 FN_VI0_HSYNC, FN_VI0_DATA0_B_VI0_B0_B, FN_CTS1_C, FN_TX4_D, 325 FN_MMC1_CMD, FN_HSCK1_B, FN_VI0_VSYNC, FN_VI0_DATA1_B_VI0_B1_B, 326 FN_RTS1_C_TANS_C, FN_RX4_D, FN_PWMFSW0_C, 327 328 /* IPSR9 */ 329 FN_VI0_DATA0_VI0_B0, FN_HRTS1_B, FN_MT1_VCXO, FN_VI0_DATA1_VI0_B1, 330 FN_HCTS1_B, FN_MT1_PWM, FN_VI0_DATA2_VI0_B2, FN_MMC1_D0, 331 FN_VI0_DATA3_VI0_B3, FN_MMC1_D1, FN_VI0_DATA4_VI0_B4, FN_MMC1_D2, 332 FN_VI0_DATA5_VI0_B5, FN_MMC1_D3, FN_VI0_DATA6_VI0_B6, FN_MMC1_D4, 333 FN_ARM_TRACEDATA_0, FN_VI0_DATA7_VI0_B7, FN_MMC1_D5, 334 FN_ARM_TRACEDATA_1, FN_VI0_G0, FN_SSI_SCK78_C, FN_IRQ0, 335 FN_ARM_TRACEDATA_2, FN_VI0_G1, FN_SSI_WS78_C, FN_IRQ1, 336 FN_ARM_TRACEDATA_3, FN_VI0_G2, FN_ETH_TXD1, FN_MMC1_D6, 337 FN_ARM_TRACEDATA_4, FN_TS_SPSYNC0, FN_VI0_G3, FN_ETH_CRS_DV, 338 FN_MMC1_D7, FN_ARM_TRACEDATA_5, FN_TS_SDAT0, FN_VI0_G4, 339 FN_ETH_TX_EN, FN_SD2_DAT0_B, FN_ARM_TRACEDATA_6, FN_VI0_G5, 340 FN_ETH_RX_ER, FN_SD2_DAT1_B, FN_ARM_TRACEDATA_7, FN_VI0_G6, 341 FN_ETH_RXD0, FN_SD2_DAT2_B, FN_ARM_TRACEDATA_8, FN_VI0_G7, 342 FN_ETH_RXD1, FN_SD2_DAT3_B, FN_ARM_TRACEDATA_9, 343 344 /* IPSR10 */ 345 FN_VI0_R0, FN_SSI_SDATA7_C, FN_SCK1_C, FN_DREQ1_B, 346 FN_ARM_TRACEDATA_10, FN_DREQ0_C, FN_VI0_R1, FN_SSI_SDATA8_C, 347 FN_DACK1_B, FN_ARM_TRACEDATA_11, FN_DACK0_C, FN_DRACK0_C, 348 FN_VI0_R2, FN_ETH_LINK, FN_SD2_CLK_B, FN_IRQ2, 349 FN_ARM_TRACEDATA_12, FN_VI0_R3, FN_ETH_MAGIC, FN_SD2_CMD_B, 350 FN_IRQ3, FN_ARM_TRACEDATA_13, FN_VI0_R4, FN_ETH_REFCLK, 351 FN_SD2_CD_B, FN_HSPI_CLK1_B, FN_ARM_TRACEDATA_14, FN_MT1_CLK, 352 FN_TS_SCK0, FN_VI0_R5, FN_ETH_TXD0, FN_SD2_WP_B, FN_HSPI_CS1_B, 353 FN_ARM_TRACEDATA_15, FN_MT1_D, FN_TS_SDEN0, FN_VI0_R6, 354 FN_ETH_MDC, FN_DREQ2_C, FN_HSPI_TX1_B, FN_TRACECLK, 355 FN_MT1_BEN, FN_PWMFSW0_D, FN_VI0_R7, FN_ETH_MDIO, 356 FN_DACK2_C, FN_HSPI_RX1_B, FN_SCIF_CLK_D, FN_TRACECTL, 357 FN_MT1_PEN, FN_VI1_CLK, FN_SIM_D, FN_SDA3, 358 FN_VI1_HSYNC, FN_VI3_CLK, FN_SSI_SCK4, FN_GPS_SIGN_C, 359 FN_PWMFSW0_E, FN_VI1_VSYNC, FN_AUDIO_CLKOUT_C, FN_SSI_WS4, 360 FN_SIM_CLK, FN_GPS_MAG_C, FN_SPV_TRST, FN_SCL3, 361 362 /* IPSR11 */ 363 FN_VI1_DATA0_VI1_B0, FN_SD2_DAT0, FN_SIM_RST, FN_SPV_TCK, 364 FN_ADICLK_B, FN_VI1_DATA1_VI1_B1, FN_SD2_DAT1, FN_MT0_CLK, 365 FN_SPV_TMS, FN_ADICS_B_SAMP_B, FN_VI1_DATA2_VI1_B2, FN_SD2_DAT2, 366 FN_MT0_D, FN_SPVTDI, FN_ADIDATA_B, FN_VI1_DATA3_VI1_B3, 367 FN_SD2_DAT3, FN_MT0_BEN, FN_SPV_TDO, FN_ADICHS0_B, 368 FN_VI1_DATA4_VI1_B4, FN_SD2_CLK, FN_MT0_PEN, FN_SPA_TRST, 369 FN_HSPI_CLK1_D, FN_ADICHS1_B, FN_VI1_DATA5_VI1_B5, FN_SD2_CMD, 370 FN_MT0_SYNC, FN_SPA_TCK, FN_HSPI_CS1_D, FN_ADICHS2_B, 371 FN_VI1_DATA6_VI1_B6, FN_SD2_CD, FN_MT0_VCXO, FN_SPA_TMS, 372 FN_HSPI_TX1_D, FN_VI1_DATA7_VI1_B7, FN_SD2_WP, FN_MT0_PWM, 373 FN_SPA_TDI, FN_HSPI_RX1_D, FN_VI1_G0, FN_VI3_DATA0, 374 FN_TS_SCK1, FN_DREQ2_B, FN_TX2, 375 FN_SPA_TDO, FN_HCTS0_B, FN_VI1_G1, FN_VI3_DATA1, 376 FN_SSI_SCK1, FN_TS_SDEN1, FN_DACK2_B, FN_RX2, FN_HRTS0_B, 377 378 /* IPSR12 */ 379 FN_VI1_G2, FN_VI3_DATA2, FN_SSI_WS1, FN_TS_SPSYNC1, 380 FN_SCK2, FN_HSCK0_B, FN_VI1_G3, FN_VI3_DATA3, 381 FN_SSI_SCK2, FN_TS_SDAT1, FN_SCL1_C, FN_HTX0_B, 382 FN_VI1_G4, FN_VI3_DATA4, FN_SSI_WS2, FN_SDA1_C, 383 FN_SIM_RST_B, FN_HRX0_B, FN_VI1_G5, FN_VI3_DATA5, 384 FN_GPS_CLK, FN_FSE, FN_TX4_B, FN_SIM_D_B, 385 FN_VI1_G6, FN_VI3_DATA6, FN_GPS_SIGN, FN_FRB, 386 FN_RX4_B, FN_SIM_CLK_B, FN_VI1_G7, FN_VI3_DATA7, 387 FN_GPS_MAG, FN_FCE, FN_SCK4_B, 388 389 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3, 390 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3, 391 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, 392 FN_SEL_SCIF3_3, FN_SEL_SCIF3_4, 393 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, 394 FN_SEL_SCIF2_3, FN_SEL_SCIF2_4, 395 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, 396 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3, 397 FN_SEL_SSI9_0, FN_SEL_SSI9_1, FN_SEL_SSI9_2, 398 FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 399 FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 400 FN_SEL_VI0_0, FN_SEL_VI0_1, 401 FN_SEL_SD2_0, FN_SEL_SD2_1, 402 FN_SEL_INT3_0, FN_SEL_INT3_1, 403 FN_SEL_INT2_0, FN_SEL_INT2_1, 404 FN_SEL_INT1_0, FN_SEL_INT1_1, 405 FN_SEL_INT0_0, FN_SEL_INT0_1, 406 FN_SEL_IE_0, FN_SEL_IE_1, 407 FN_SEL_EXBUS2_0, FN_SEL_EXBUS2_1, FN_SEL_EXBUS2_2, 408 FN_SEL_EXBUS1_0, FN_SEL_EXBUS1_1, 409 FN_SEL_EXBUS0_0, FN_SEL_EXBUS0_1, FN_SEL_EXBUS0_2, 410 411 FN_SEL_TMU1_0, FN_SEL_TMU1_1, FN_SEL_TMU1_2, 412 FN_SEL_TMU0_0, FN_SEL_TMU0_1, FN_SEL_TMU0_2, FN_SEL_TMU0_3, 413 FN_SEL_SCIF_0, FN_SEL_SCIF_1, FN_SEL_SCIF_2, FN_SEL_SCIF_3, 414 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, 415 FN_SEL_CAN0_0, FN_SEL_CAN0_1, 416 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, 417 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, 418 FN_SEL_PWMFSW_0, FN_SEL_PWMFSW_1, FN_SEL_PWMFSW_2, 419 FN_SEL_PWMFSW_3, FN_SEL_PWMFSW_4, 420 FN_SEL_ADI_0, FN_SEL_ADI_1, 421 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3, 422 FN_SEL_SIM_0, FN_SEL_SIM_1, 423 FN_SEL_HSPI2_0, FN_SEL_HSPI2_1, 424 FN_SEL_HSPI1_0, FN_SEL_HSPI1_1, FN_SEL_HSPI1_2, FN_SEL_HSPI1_3, 425 FN_SEL_I2C3_0, FN_SEL_I2C3_1, 426 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3, 427 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3, 428 PINMUX_FUNCTION_END, 429 430 PINMUX_MARK_BEGIN, 431 AVS1_MARK, AVS2_MARK, A17_MARK, A18_MARK, 432 A19_MARK, 433 434 RD_WR_MARK, FWE_MARK, ATAG0_MARK, VI1_R7_MARK, 435 HRTS1_MARK, RX4_C_MARK, 436 CS1_A26_MARK, HSPI_TX2_MARK, SDSELF_B_MARK, 437 CS0_MARK, HSPI_CS2_B_MARK, 438 CLKOUT_MARK, TX3C_IRDA_TX_C_MARK, PWM0_B_MARK, 439 A25_MARK, SD1_WP_MARK, MMC0_D5_MARK, FD5_MARK, 440 HSPI_RX2_MARK, VI1_R3_MARK, TX5_B_MARK, SSI_SDATA7_B_MARK, CTS0_B_MARK, 441 A24_MARK, SD1_CD_MARK, MMC0_D4_MARK, FD4_MARK, 442 HSPI_CS2_MARK, VI1_R2_MARK, SSI_WS78_B_MARK, 443 A23_MARK, FCLE_MARK, HSPI_CLK2_MARK, VI1_R1_MARK, 444 A22_MARK, RX5_D_MARK, HSPI_RX2_B_MARK, VI1_R0_MARK, 445 A21_MARK, SCK5_D_MARK, HSPI_CLK2_B_MARK, 446 A20_MARK, TX5_D_MARK, HSPI_TX2_B_MARK, 447 A0_MARK, SD1_DAT3_MARK, MMC0_D3_MARK, FD3_MARK, 448 BS_MARK, SD1_DAT2_MARK, MMC0_D2_MARK, FD2_MARK, 449 ATADIR0_MARK, SDSELF_MARK, HCTS1_MARK, TX4_C_MARK, 450 USB_PENC0_MARK, USB_PENC1_MARK, USB_PENC2_MARK, 451 SCK0_MARK, PWM1_MARK, PWMFSW0_MARK, 452 SCIF_CLK_MARK, TCLK0_C_MARK, 453 454 EX_CS0_MARK, RX3_C_IRDA_RX_C_MARK, MMC0_D6_MARK, 455 FD6_MARK, EX_CS1_MARK, MMC0_D7_MARK, FD7_MARK, 456 EX_CS2_MARK, SD1_CLK_MARK, MMC0_CLK_MARK, FALE_MARK, 457 ATACS00_MARK, EX_CS3_MARK, SD1_CMD_MARK, MMC0_CMD_MARK, 458 FRE_MARK, ATACS10_MARK, VI1_R4_MARK, RX5_B_MARK, 459 HSCK1_MARK, SSI_SDATA8_B_MARK, RTS0_B_TANS_B_MARK, SSI_SDATA9_MARK, 460 EX_CS4_MARK, SD1_DAT0_MARK, MMC0_D0_MARK, FD0_MARK, 461 ATARD0_MARK, VI1_R5_MARK, SCK5_B_MARK, HTX1_MARK, 462 TX2_E_MARK, TX0_B_MARK, SSI_SCK9_MARK, EX_CS5_MARK, 463 SD1_DAT1_MARK, MMC0_D1_MARK, FD1_MARK, ATAWR0_MARK, 464 VI1_R6_MARK, HRX1_MARK, RX2_E_MARK, RX0_B_MARK, 465 SSI_WS9_MARK, MLB_CLK_MARK, PWM2_MARK, SCK4_MARK, 466 MLB_SIG_MARK, PWM3_MARK, TX4_MARK, MLB_DAT_MARK, 467 PWM4_MARK, RX4_MARK, HTX0_MARK, TX1_MARK, 468 SDATA_MARK, CTS0_C_MARK, SUB_TCK_MARK, CC5_STATE2_MARK, 469 CC5_STATE10_MARK, CC5_STATE18_MARK, CC5_STATE26_MARK, CC5_STATE34_MARK, 470 471 HRX0_MARK, RX1_MARK, SCKZ_MARK, RTS0_C_TANS_C_MARK, 472 SUB_TDI_MARK, CC5_STATE3_MARK, CC5_STATE11_MARK, CC5_STATE19_MARK, 473 CC5_STATE27_MARK, CC5_STATE35_MARK, HSCK0_MARK, SCK1_MARK, 474 MTS_MARK, PWM5_MARK, SCK0_C_MARK, SSI_SDATA9_B_MARK, 475 SUB_TDO_MARK, CC5_STATE0_MARK, CC5_STATE8_MARK, CC5_STATE16_MARK, 476 CC5_STATE24_MARK, CC5_STATE32_MARK, HCTS0_MARK, CTS1_MARK, 477 STM_MARK, PWM0_D_MARK, RX0_C_MARK, SCIF_CLK_C_MARK, 478 SUB_TRST_MARK, TCLK1_B_MARK, CC5_OSCOUT_MARK, HRTS0_MARK, 479 RTS1_TANS_MARK, MDATA_MARK, TX0_C_MARK, SUB_TMS_MARK, 480 CC5_STATE1_MARK, CC5_STATE9_MARK, CC5_STATE17_MARK, CC5_STATE25_MARK, 481 CC5_STATE33_MARK, DU0_DR0_MARK, LCDOUT0_MARK, DREQ0_MARK, 482 GPS_CLK_B_MARK, AUDATA0_MARK, TX5_C_MARK, DU0_DR1_MARK, 483 LCDOUT1_MARK, DACK0_MARK, DRACK0_MARK, GPS_SIGN_B_MARK, 484 AUDATA1_MARK, RX5_C_MARK, DU0_DR2_MARK, LCDOUT2_MARK, 485 DU0_DR3_MARK, LCDOUT3_MARK, DU0_DR4_MARK, LCDOUT4_MARK, 486 DU0_DR5_MARK, LCDOUT5_MARK, DU0_DR6_MARK, LCDOUT6_MARK, 487 DU0_DR7_MARK, LCDOUT7_MARK, DU0_DG0_MARK, LCDOUT8_MARK, 488 DREQ1_MARK, SCL2_MARK, AUDATA2_MARK, 489 490 DU0_DG1_MARK, LCDOUT9_MARK, DACK1_MARK, SDA2_MARK, 491 AUDATA3_MARK, DU0_DG2_MARK, LCDOUT10_MARK, DU0_DG3_MARK, 492 LCDOUT11_MARK, DU0_DG4_MARK, LCDOUT12_MARK, DU0_DG5_MARK, 493 LCDOUT13_MARK, DU0_DG6_MARK, LCDOUT14_MARK, DU0_DG7_MARK, 494 LCDOUT15_MARK, DU0_DB0_MARK, LCDOUT16_MARK, EX_WAIT1_MARK, 495 SCL1_MARK, TCLK1_MARK, AUDATA4_MARK, DU0_DB1_MARK, 496 LCDOUT17_MARK, EX_WAIT2_MARK, SDA1_MARK, GPS_MAG_B_MARK, 497 AUDATA5_MARK, SCK5_C_MARK, DU0_DB2_MARK, LCDOUT18_MARK, 498 DU0_DB3_MARK, LCDOUT19_MARK, DU0_DB4_MARK, LCDOUT20_MARK, 499 DU0_DB5_MARK, LCDOUT21_MARK, DU0_DB6_MARK, LCDOUT22_MARK, 500 DU0_DB7_MARK, LCDOUT23_MARK, DU0_DOTCLKIN_MARK, QSTVA_QVS_MARK, 501 TX3_D_IRDA_TX_D_MARK, SCL3_B_MARK, DU0_DOTCLKOUT0_MARK, QCLK_MARK, 502 DU0_DOTCLKOUT1_MARK, QSTVB_QVE_MARK, RX3_D_IRDA_RX_D_MARK, SDA3_B_MARK, 503 SDA2_C_MARK, DACK0_B_MARK, DRACK0_B_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK, 504 QSTH_QHS_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK, 505 DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, CAN1_TX_MARK, 506 TX2_C_MARK, SCL2_C_MARK, REMOCON_MARK, 507 508 DU0_DISP_MARK, QPOLA_MARK, CAN_CLK_C_MARK, SCK2_C_MARK, 509 DU0_CDE_MARK, QPOLB_MARK, CAN1_RX_MARK, RX2_C_MARK, 510 DREQ0_B_MARK, SSI_SCK78_B_MARK, SCK0_B_MARK, DU1_DR0_MARK, 511 VI2_DATA0_VI2_B0_MARK, PWM6_MARK, SD3_CLK_MARK, TX3_E_IRDA_TX_E_MARK, 512 AUDCK_MARK, PWMFSW0_B_MARK, DU1_DR1_MARK, VI2_DATA1_VI2_B1_MARK, 513 PWM0_MARK, SD3_CMD_MARK, RX3_E_IRDA_RX_E_MARK, AUDSYNC_MARK, 514 CTS0_D_MARK, DU1_DR2_MARK, VI2_G0_MARK, DU1_DR3_MARK, 515 VI2_G1_MARK, DU1_DR4_MARK, VI2_G2_MARK, DU1_DR5_MARK, 516 VI2_G3_MARK, DU1_DR6_MARK, VI2_G4_MARK, DU1_DR7_MARK, 517 VI2_G5_MARK, DU1_DG0_MARK, VI2_DATA2_VI2_B2_MARK, SCL1_B_MARK, 518 SD3_DAT2_MARK, SCK3_E_MARK, AUDATA6_MARK, TX0_D_MARK, 519 DU1_DG1_MARK, VI2_DATA3_VI2_B3_MARK, SDA1_B_MARK, SD3_DAT3_MARK, 520 SCK5_MARK, AUDATA7_MARK, RX0_D_MARK, DU1_DG2_MARK, 521 VI2_G6_MARK, DU1_DG3_MARK, VI2_G7_MARK, DU1_DG4_MARK, 522 VI2_R0_MARK, DU1_DG5_MARK, VI2_R1_MARK, DU1_DG6_MARK, 523 VI2_R2_MARK, DU1_DG7_MARK, VI2_R3_MARK, DU1_DB0_MARK, 524 VI2_DATA4_VI2_B4_MARK, SCL2_B_MARK, SD3_DAT0_MARK, TX5_MARK, 525 SCK0_D_MARK, 526 527 DU1_DB1_MARK, VI2_DATA5_VI2_B5_MARK, SDA2_B_MARK, SD3_DAT1_MARK, 528 RX5_MARK, RTS0_D_TANS_D_MARK, DU1_DB2_MARK, VI2_R4_MARK, 529 DU1_DB3_MARK, VI2_R5_MARK, DU1_DB4_MARK, VI2_R6_MARK, 530 DU1_DB5_MARK, VI2_R7_MARK, DU1_DB6_MARK, SCL2_D_MARK, 531 DU1_DB7_MARK, SDA2_D_MARK, DU1_DOTCLKIN_MARK, VI2_CLKENB_MARK, 532 HSPI_CS1_MARK, SCL1_D_MARK, DU1_DOTCLKOUT_MARK, VI2_FIELD_MARK, 533 SDA1_D_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, VI2_HSYNC_MARK, 534 VI3_HSYNC_MARK, DU1_EXVSYNC_DU1_VSYNC_MARK, VI2_VSYNC_MARK, 535 VI3_VSYNC_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, VI2_CLK_MARK, 536 TX3_B_IRDA_TX_B_MARK, SD3_CD_MARK, HSPI_TX1_MARK, VI1_CLKENB_MARK, 537 VI3_CLKENB_MARK, AUDIO_CLKC_MARK, TX2_D_MARK, SPEEDIN_MARK, 538 GPS_SIGN_D_MARK, DU1_DISP_MARK, VI2_DATA6_VI2_B6_MARK, TCLK0_MARK, 539 QSTVA_B_QVS_B_MARK, HSPI_CLK1_MARK, SCK2_D_MARK, AUDIO_CLKOUT_B_MARK, 540 GPS_MAG_D_MARK, DU1_CDE_MARK, VI2_DATA7_VI2_B7_MARK, 541 RX3_B_IRDA_RX_B_MARK, SD3_WP_MARK, HSPI_RX1_MARK, VI1_FIELD_MARK, 542 VI3_FIELD_MARK, AUDIO_CLKOUT_MARK, RX2_D_MARK, GPS_CLK_C_MARK, 543 GPS_CLK_D_MARK, AUDIO_CLKA_MARK, CAN_TXCLK_MARK, AUDIO_CLKB_MARK, 544 USB_OVC2_MARK, CAN_DEBUGOUT0_MARK, MOUT0_MARK, 545 546 SSI_SCK0129_MARK, CAN_DEBUGOUT1_MARK, MOUT1_MARK, SSI_WS0129_MARK, 547 CAN_DEBUGOUT2_MARK, MOUT2_MARK, SSI_SDATA0_MARK, CAN_DEBUGOUT3_MARK, 548 MOUT5_MARK, SSI_SDATA1_MARK, CAN_DEBUGOUT4_MARK, MOUT6_MARK, 549 SSI_SDATA2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK34_MARK, 550 CAN_DEBUGOUT6_MARK, CAN0_TX_B_MARK, IERX_MARK, SSI_SCK9_C_MARK, 551 SSI_WS34_MARK, CAN_DEBUGOUT7_MARK, CAN0_RX_B_MARK, IETX_MARK, 552 SSI_WS9_C_MARK, SSI_SDATA3_MARK, PWM0_C_MARK, CAN_DEBUGOUT8_MARK, 553 CAN_CLK_B_MARK, IECLK_MARK, SCIF_CLK_B_MARK, TCLK0_B_MARK, 554 SSI_SDATA4_MARK, CAN_DEBUGOUT9_MARK, SSI_SDATA9_C_MARK, SSI_SCK5_MARK, 555 ADICLK_MARK, CAN_DEBUGOUT10_MARK, SCK3_MARK, TCLK0_D_MARK, 556 SSI_WS5_MARK, ADICS_SAMP_MARK, CAN_DEBUGOUT11_MARK, TX3_IRDA_TX_MARK, 557 SSI_SDATA5_MARK, ADIDATA_MARK, CAN_DEBUGOUT12_MARK, RX3_IRDA_RX_MARK, 558 SSI_SCK6_MARK, ADICHS0_MARK, CAN0_TX_MARK, IERX_B_MARK, 559 560 SSI_WS6_MARK, ADICHS1_MARK, CAN0_RX_MARK, IETX_B_MARK, 561 SSI_SDATA6_MARK, ADICHS2_MARK, CAN_CLK_MARK, IECLK_B_MARK, 562 SSI_SCK78_MARK, CAN_DEBUGOUT13_MARK, IRQ0_B_MARK, SSI_SCK9_B_MARK, 563 HSPI_CLK1_C_MARK, SSI_WS78_MARK, CAN_DEBUGOUT14_MARK, IRQ1_B_MARK, 564 SSI_WS9_B_MARK, HSPI_CS1_C_MARK, SSI_SDATA7_MARK, CAN_DEBUGOUT15_MARK, 565 IRQ2_B_MARK, TCLK1_C_MARK, HSPI_TX1_C_MARK, SSI_SDATA8_MARK, 566 VSP_MARK, IRQ3_B_MARK, HSPI_RX1_C_MARK, SD0_CLK_MARK, 567 ATACS01_MARK, SCK1_B_MARK, SD0_CMD_MARK, ATACS11_MARK, 568 TX1_B_MARK, CC5_TDO_MARK, SD0_DAT0_MARK, ATADIR1_MARK, 569 RX1_B_MARK, CC5_TRST_MARK, SD0_DAT1_MARK, ATAG1_MARK, 570 SCK2_B_MARK, CC5_TMS_MARK, SD0_DAT2_MARK, ATARD1_MARK, 571 TX2_B_MARK, CC5_TCK_MARK, SD0_DAT3_MARK, ATAWR1_MARK, 572 RX2_B_MARK, CC5_TDI_MARK, SD0_CD_MARK, DREQ2_MARK, 573 RTS1_B_TANS_B_MARK, SD0_WP_MARK, DACK2_MARK, CTS1_B_MARK, 574 575 HSPI_CLK0_MARK, CTS0_MARK, USB_OVC0_MARK, AD_CLK_MARK, 576 CC5_STATE4_MARK, CC5_STATE12_MARK, CC5_STATE20_MARK, CC5_STATE28_MARK, 577 CC5_STATE36_MARK, HSPI_CS0_MARK, RTS0_TANS_MARK, USB_OVC1_MARK, 578 AD_DI_MARK, CC5_STATE5_MARK, CC5_STATE13_MARK, CC5_STATE21_MARK, 579 CC5_STATE29_MARK, CC5_STATE37_MARK, HSPI_TX0_MARK, TX0_MARK, 580 CAN_DEBUG_HW_TRIGGER_MARK, AD_DO_MARK, CC5_STATE6_MARK, 581 CC5_STATE14_MARK, CC5_STATE22_MARK, CC5_STATE30_MARK, 582 CC5_STATE38_MARK, HSPI_RX0_MARK, RX0_MARK, CAN_STEP0_MARK, 583 AD_NCS_MARK, CC5_STATE7_MARK, CC5_STATE15_MARK, CC5_STATE23_MARK, 584 CC5_STATE31_MARK, CC5_STATE39_MARK, FMCLK_MARK, RDS_CLK_MARK, 585 PCMOE_MARK, BPFCLK_MARK, PCMWE_MARK, FMIN_MARK, RDS_DATA_MARK, 586 VI0_CLK_MARK, MMC1_CLK_MARK, VI0_CLKENB_MARK, TX1_C_MARK, HTX1_B_MARK, 587 MT1_SYNC_MARK, VI0_FIELD_MARK, RX1_C_MARK, HRX1_B_MARK, 588 VI0_HSYNC_MARK, VI0_DATA0_B_VI0_B0_B_MARK, CTS1_C_MARK, TX4_D_MARK, 589 MMC1_CMD_MARK, HSCK1_B_MARK, VI0_VSYNC_MARK, VI0_DATA1_B_VI0_B1_B_MARK, 590 RTS1_C_TANS_C_MARK, RX4_D_MARK, PWMFSW0_C_MARK, 591 592 VI0_DATA0_VI0_B0_MARK, HRTS1_B_MARK, MT1_VCXO_MARK, 593 VI0_DATA1_VI0_B1_MARK, HCTS1_B_MARK, MT1_PWM_MARK, 594 VI0_DATA2_VI0_B2_MARK, MMC1_D0_MARK, VI0_DATA3_VI0_B3_MARK, 595 MMC1_D1_MARK, VI0_DATA4_VI0_B4_MARK, MMC1_D2_MARK, 596 VI0_DATA5_VI0_B5_MARK, MMC1_D3_MARK, VI0_DATA6_VI0_B6_MARK, 597 MMC1_D4_MARK, ARM_TRACEDATA_0_MARK, VI0_DATA7_VI0_B7_MARK, 598 MMC1_D5_MARK, ARM_TRACEDATA_1_MARK, VI0_G0_MARK, SSI_SCK78_C_MARK, 599 IRQ0_MARK, ARM_TRACEDATA_2_MARK, VI0_G1_MARK, SSI_WS78_C_MARK, 600 IRQ1_MARK, ARM_TRACEDATA_3_MARK, VI0_G2_MARK, ETH_TXD1_MARK, 601 MMC1_D6_MARK, ARM_TRACEDATA_4_MARK, TS_SPSYNC0_MARK, VI0_G3_MARK, 602 ETH_CRS_DV_MARK, MMC1_D7_MARK, ARM_TRACEDATA_5_MARK, TS_SDAT0_MARK, 603 VI0_G4_MARK, ETH_TX_EN_MARK, SD2_DAT0_B_MARK, ARM_TRACEDATA_6_MARK, 604 VI0_G5_MARK, ETH_RX_ER_MARK, SD2_DAT1_B_MARK, ARM_TRACEDATA_7_MARK, 605 VI0_G6_MARK, ETH_RXD0_MARK, SD2_DAT2_B_MARK, ARM_TRACEDATA_8_MARK, 606 VI0_G7_MARK, ETH_RXD1_MARK, SD2_DAT3_B_MARK, ARM_TRACEDATA_9_MARK, 607 608 VI0_R0_MARK, SSI_SDATA7_C_MARK, SCK1_C_MARK, DREQ1_B_MARK, 609 ARM_TRACEDATA_10_MARK, DREQ0_C_MARK, VI0_R1_MARK, SSI_SDATA8_C_MARK, 610 DACK1_B_MARK, ARM_TRACEDATA_11_MARK, DACK0_C_MARK, DRACK0_C_MARK, 611 VI0_R2_MARK, ETH_LINK_MARK, SD2_CLK_B_MARK, IRQ2_MARK, 612 ARM_TRACEDATA_12_MARK, VI0_R3_MARK, ETH_MAGIC_MARK, SD2_CMD_B_MARK, 613 IRQ3_MARK, ARM_TRACEDATA_13_MARK, VI0_R4_MARK, ETH_REFCLK_MARK, 614 SD2_CD_B_MARK, HSPI_CLK1_B_MARK, ARM_TRACEDATA_14_MARK, MT1_CLK_MARK, 615 TS_SCK0_MARK, VI0_R5_MARK, ETH_TXD0_MARK, SD2_WP_B_MARK, 616 HSPI_CS1_B_MARK, ARM_TRACEDATA_15_MARK, MT1_D_MARK, TS_SDEN0_MARK, 617 VI0_R6_MARK, ETH_MDC_MARK, DREQ2_C_MARK, HSPI_TX1_B_MARK, 618 TRACECLK_MARK, MT1_BEN_MARK, PWMFSW0_D_MARK, VI0_R7_MARK, 619 ETH_MDIO_MARK, DACK2_C_MARK, HSPI_RX1_B_MARK, SCIF_CLK_D_MARK, 620 TRACECTL_MARK, MT1_PEN_MARK, VI1_CLK_MARK, SIM_D_MARK, SDA3_MARK, 621 VI1_HSYNC_MARK, VI3_CLK_MARK, SSI_SCK4_MARK, GPS_SIGN_C_MARK, 622 PWMFSW0_E_MARK, VI1_VSYNC_MARK, AUDIO_CLKOUT_C_MARK, SSI_WS4_MARK, 623 SIM_CLK_MARK, GPS_MAG_C_MARK, SPV_TRST_MARK, SCL3_MARK, 624 625 VI1_DATA0_VI1_B0_MARK, SD2_DAT0_MARK, SIM_RST_MARK, SPV_TCK_MARK, 626 ADICLK_B_MARK, VI1_DATA1_VI1_B1_MARK, SD2_DAT1_MARK, MT0_CLK_MARK, 627 SPV_TMS_MARK, ADICS_B_SAMP_B_MARK, VI1_DATA2_VI1_B2_MARK, 628 SD2_DAT2_MARK, MT0_D_MARK, SPVTDI_MARK, ADIDATA_B_MARK, 629 VI1_DATA3_VI1_B3_MARK, SD2_DAT3_MARK, MT0_BEN_MARK, SPV_TDO_MARK, 630 ADICHS0_B_MARK, VI1_DATA4_VI1_B4_MARK, SD2_CLK_MARK, MT0_PEN_MARK, 631 SPA_TRST_MARK, HSPI_CLK1_D_MARK, ADICHS1_B_MARK, 632 VI1_DATA5_VI1_B5_MARK, SD2_CMD_MARK, MT0_SYNC_MARK, SPA_TCK_MARK, 633 HSPI_CS1_D_MARK, ADICHS2_B_MARK, VI1_DATA6_VI1_B6_MARK, SD2_CD_MARK, 634 MT0_VCXO_MARK, SPA_TMS_MARK, HSPI_TX1_D_MARK, VI1_DATA7_VI1_B7_MARK, 635 SD2_WP_MARK, MT0_PWM_MARK, SPA_TDI_MARK, HSPI_RX1_D_MARK, 636 VI1_G0_MARK, VI3_DATA0_MARK, TS_SCK1_MARK, 637 DREQ2_B_MARK, TX2_MARK, SPA_TDO_MARK, HCTS0_B_MARK, 638 VI1_G1_MARK, VI3_DATA1_MARK, SSI_SCK1_MARK, TS_SDEN1_MARK, 639 DACK2_B_MARK, RX2_MARK, HRTS0_B_MARK, 640 641 VI1_G2_MARK, VI3_DATA2_MARK, SSI_WS1_MARK, TS_SPSYNC1_MARK, 642 SCK2_MARK, HSCK0_B_MARK, VI1_G3_MARK, VI3_DATA3_MARK, 643 SSI_SCK2_MARK, TS_SDAT1_MARK, SCL1_C_MARK, HTX0_B_MARK, 644 VI1_G4_MARK, VI3_DATA4_MARK, SSI_WS2_MARK, SDA1_C_MARK, 645 SIM_RST_B_MARK, HRX0_B_MARK, VI1_G5_MARK, VI3_DATA5_MARK, 646 GPS_CLK_MARK, FSE_MARK, TX4_B_MARK, SIM_D_B_MARK, 647 VI1_G6_MARK, VI3_DATA6_MARK, GPS_SIGN_MARK, FRB_MARK, 648 RX4_B_MARK, SIM_CLK_B_MARK, VI1_G7_MARK, VI3_DATA7_MARK, 649 GPS_MAG_MARK, FCE_MARK, SCK4_B_MARK, 650 PINMUX_MARK_END, 651 }; 652 653 static const u16 pinmux_data[] = { 654 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ 655 656 PINMUX_SINGLE(AVS1), 657 PINMUX_SINGLE(AVS1), 658 PINMUX_SINGLE(A17), 659 PINMUX_SINGLE(A18), 660 PINMUX_SINGLE(A19), 661 662 PINMUX_SINGLE(USB_PENC0), 663 PINMUX_SINGLE(USB_PENC1), 664 665 PINMUX_IPSR_GPSR(IP0_2_0, USB_PENC2), 666 PINMUX_IPSR_MSEL(IP0_2_0, SCK0, SEL_SCIF0_0), 667 PINMUX_IPSR_GPSR(IP0_2_0, PWM1), 668 PINMUX_IPSR_MSEL(IP0_2_0, PWMFSW0, SEL_PWMFSW_0), 669 PINMUX_IPSR_MSEL(IP0_2_0, SCIF_CLK, SEL_SCIF_0), 670 PINMUX_IPSR_MSEL(IP0_2_0, TCLK0_C, SEL_TMU0_2), 671 PINMUX_IPSR_GPSR(IP0_5_3, BS), 672 PINMUX_IPSR_GPSR(IP0_5_3, SD1_DAT2), 673 PINMUX_IPSR_GPSR(IP0_5_3, MMC0_D2), 674 PINMUX_IPSR_GPSR(IP0_5_3, FD2), 675 PINMUX_IPSR_GPSR(IP0_5_3, ATADIR0), 676 PINMUX_IPSR_GPSR(IP0_5_3, SDSELF), 677 PINMUX_IPSR_MSEL(IP0_5_3, HCTS1, SEL_HSCIF1_0), 678 PINMUX_IPSR_GPSR(IP0_5_3, TX4_C), 679 PINMUX_IPSR_GPSR(IP0_7_6, A0), 680 PINMUX_IPSR_GPSR(IP0_7_6, SD1_DAT3), 681 PINMUX_IPSR_GPSR(IP0_7_6, MMC0_D3), 682 PINMUX_IPSR_GPSR(IP0_7_6, FD3), 683 PINMUX_IPSR_GPSR(IP0_9_8, A20), 684 PINMUX_IPSR_GPSR(IP0_9_8, TX5_D), 685 PINMUX_IPSR_GPSR(IP0_9_8, HSPI_TX2_B), 686 PINMUX_IPSR_GPSR(IP0_11_10, A21), 687 PINMUX_IPSR_MSEL(IP0_11_10, SCK5_D, SEL_SCIF5_3), 688 PINMUX_IPSR_MSEL(IP0_11_10, HSPI_CLK2_B, SEL_HSPI2_1), 689 PINMUX_IPSR_GPSR(IP0_13_12, A22), 690 PINMUX_IPSR_MSEL(IP0_13_12, RX5_D, SEL_SCIF5_3), 691 PINMUX_IPSR_MSEL(IP0_13_12, HSPI_RX2_B, SEL_HSPI2_1), 692 PINMUX_IPSR_GPSR(IP0_13_12, VI1_R0), 693 PINMUX_IPSR_GPSR(IP0_15_14, A23), 694 PINMUX_IPSR_GPSR(IP0_15_14, FCLE), 695 PINMUX_IPSR_MSEL(IP0_15_14, HSPI_CLK2, SEL_HSPI2_0), 696 PINMUX_IPSR_GPSR(IP0_15_14, VI1_R1), 697 PINMUX_IPSR_GPSR(IP0_18_16, A24), 698 PINMUX_IPSR_GPSR(IP0_18_16, SD1_CD), 699 PINMUX_IPSR_GPSR(IP0_18_16, MMC0_D4), 700 PINMUX_IPSR_GPSR(IP0_18_16, FD4), 701 PINMUX_IPSR_MSEL(IP0_18_16, HSPI_CS2, SEL_HSPI2_0), 702 PINMUX_IPSR_GPSR(IP0_18_16, VI1_R2), 703 PINMUX_IPSR_MSEL(IP0_18_16, SSI_WS78_B, SEL_SSI7_1), 704 PINMUX_IPSR_GPSR(IP0_22_19, A25), 705 PINMUX_IPSR_GPSR(IP0_22_19, SD1_WP), 706 PINMUX_IPSR_GPSR(IP0_22_19, MMC0_D5), 707 PINMUX_IPSR_GPSR(IP0_22_19, FD5), 708 PINMUX_IPSR_MSEL(IP0_22_19, HSPI_RX2, SEL_HSPI2_0), 709 PINMUX_IPSR_GPSR(IP0_22_19, VI1_R3), 710 PINMUX_IPSR_GPSR(IP0_22_19, TX5_B), 711 PINMUX_IPSR_MSEL(IP0_22_19, SSI_SDATA7_B, SEL_SSI7_1), 712 PINMUX_IPSR_MSEL(IP0_22_19, CTS0_B, SEL_SCIF0_1), 713 PINMUX_IPSR_GPSR(IP0_24_23, CLKOUT), 714 PINMUX_IPSR_GPSR(IP0_24_23, TX3C_IRDA_TX_C), 715 PINMUX_IPSR_GPSR(IP0_24_23, PWM0_B), 716 PINMUX_IPSR_GPSR(IP0_25, CS0), 717 PINMUX_IPSR_MSEL(IP0_25, HSPI_CS2_B, SEL_HSPI2_1), 718 PINMUX_IPSR_GPSR(IP0_27_26, CS1_A26), 719 PINMUX_IPSR_GPSR(IP0_27_26, HSPI_TX2), 720 PINMUX_IPSR_GPSR(IP0_27_26, SDSELF_B), 721 PINMUX_IPSR_GPSR(IP0_30_28, RD_WR), 722 PINMUX_IPSR_GPSR(IP0_30_28, FWE), 723 PINMUX_IPSR_GPSR(IP0_30_28, ATAG0), 724 PINMUX_IPSR_GPSR(IP0_30_28, VI1_R7), 725 PINMUX_IPSR_MSEL(IP0_30_28, HRTS1, SEL_HSCIF1_0), 726 PINMUX_IPSR_MSEL(IP0_30_28, RX4_C, SEL_SCIF4_2), 727 728 PINMUX_IPSR_GPSR(IP1_1_0, EX_CS0), 729 PINMUX_IPSR_MSEL(IP1_1_0, RX3_C_IRDA_RX_C, SEL_SCIF3_2), 730 PINMUX_IPSR_GPSR(IP1_1_0, MMC0_D6), 731 PINMUX_IPSR_GPSR(IP1_1_0, FD6), 732 PINMUX_IPSR_GPSR(IP1_3_2, EX_CS1), 733 PINMUX_IPSR_GPSR(IP1_3_2, MMC0_D7), 734 PINMUX_IPSR_GPSR(IP1_3_2, FD7), 735 PINMUX_IPSR_GPSR(IP1_6_4, EX_CS2), 736 PINMUX_IPSR_GPSR(IP1_6_4, SD1_CLK), 737 PINMUX_IPSR_GPSR(IP1_6_4, MMC0_CLK), 738 PINMUX_IPSR_GPSR(IP1_6_4, FALE), 739 PINMUX_IPSR_GPSR(IP1_6_4, ATACS00), 740 PINMUX_IPSR_GPSR(IP1_10_7, EX_CS3), 741 PINMUX_IPSR_GPSR(IP1_10_7, SD1_CMD), 742 PINMUX_IPSR_GPSR(IP1_10_7, MMC0_CMD), 743 PINMUX_IPSR_GPSR(IP1_10_7, FRE), 744 PINMUX_IPSR_GPSR(IP1_10_7, ATACS10), 745 PINMUX_IPSR_GPSR(IP1_10_7, VI1_R4), 746 PINMUX_IPSR_MSEL(IP1_10_7, RX5_B, SEL_SCIF5_1), 747 PINMUX_IPSR_MSEL(IP1_10_7, HSCK1, SEL_HSCIF1_0), 748 PINMUX_IPSR_MSEL(IP1_10_7, SSI_SDATA8_B, SEL_SSI8_1), 749 PINMUX_IPSR_MSEL(IP1_10_7, RTS0_B_TANS_B, SEL_SCIF0_1), 750 PINMUX_IPSR_MSEL(IP1_10_7, SSI_SDATA9, SEL_SSI9_0), 751 PINMUX_IPSR_GPSR(IP1_14_11, EX_CS4), 752 PINMUX_IPSR_GPSR(IP1_14_11, SD1_DAT0), 753 PINMUX_IPSR_GPSR(IP1_14_11, MMC0_D0), 754 PINMUX_IPSR_GPSR(IP1_14_11, FD0), 755 PINMUX_IPSR_GPSR(IP1_14_11, ATARD0), 756 PINMUX_IPSR_GPSR(IP1_14_11, VI1_R5), 757 PINMUX_IPSR_MSEL(IP1_14_11, SCK5_B, SEL_SCIF5_1), 758 PINMUX_IPSR_GPSR(IP1_14_11, HTX1), 759 PINMUX_IPSR_GPSR(IP1_14_11, TX2_E), 760 PINMUX_IPSR_GPSR(IP1_14_11, TX0_B), 761 PINMUX_IPSR_MSEL(IP1_14_11, SSI_SCK9, SEL_SSI9_0), 762 PINMUX_IPSR_GPSR(IP1_18_15, EX_CS5), 763 PINMUX_IPSR_GPSR(IP1_18_15, SD1_DAT1), 764 PINMUX_IPSR_GPSR(IP1_18_15, MMC0_D1), 765 PINMUX_IPSR_GPSR(IP1_18_15, FD1), 766 PINMUX_IPSR_GPSR(IP1_18_15, ATAWR0), 767 PINMUX_IPSR_GPSR(IP1_18_15, VI1_R6), 768 PINMUX_IPSR_MSEL(IP1_18_15, HRX1, SEL_HSCIF1_0), 769 PINMUX_IPSR_MSEL(IP1_18_15, RX2_E, SEL_SCIF2_4), 770 PINMUX_IPSR_MSEL(IP1_18_15, RX0_B, SEL_SCIF0_1), 771 PINMUX_IPSR_MSEL(IP1_18_15, SSI_WS9, SEL_SSI9_0), 772 PINMUX_IPSR_GPSR(IP1_20_19, MLB_CLK), 773 PINMUX_IPSR_GPSR(IP1_20_19, PWM2), 774 PINMUX_IPSR_MSEL(IP1_20_19, SCK4, SEL_SCIF4_0), 775 PINMUX_IPSR_GPSR(IP1_22_21, MLB_SIG), 776 PINMUX_IPSR_GPSR(IP1_22_21, PWM3), 777 PINMUX_IPSR_GPSR(IP1_22_21, TX4), 778 PINMUX_IPSR_GPSR(IP1_24_23, MLB_DAT), 779 PINMUX_IPSR_GPSR(IP1_24_23, PWM4), 780 PINMUX_IPSR_MSEL(IP1_24_23, RX4, SEL_SCIF4_0), 781 PINMUX_IPSR_GPSR(IP1_28_25, HTX0), 782 PINMUX_IPSR_GPSR(IP1_28_25, TX1), 783 PINMUX_IPSR_GPSR(IP1_28_25, SDATA), 784 PINMUX_IPSR_MSEL(IP1_28_25, CTS0_C, SEL_SCIF0_2), 785 PINMUX_IPSR_GPSR(IP1_28_25, SUB_TCK), 786 PINMUX_IPSR_GPSR(IP1_28_25, CC5_STATE2), 787 PINMUX_IPSR_GPSR(IP1_28_25, CC5_STATE10), 788 PINMUX_IPSR_GPSR(IP1_28_25, CC5_STATE18), 789 PINMUX_IPSR_GPSR(IP1_28_25, CC5_STATE26), 790 PINMUX_IPSR_GPSR(IP1_28_25, CC5_STATE34), 791 792 PINMUX_IPSR_MSEL(IP2_3_0, HRX0, SEL_HSCIF0_0), 793 PINMUX_IPSR_MSEL(IP2_3_0, RX1, SEL_SCIF1_0), 794 PINMUX_IPSR_GPSR(IP2_3_0, SCKZ), 795 PINMUX_IPSR_MSEL(IP2_3_0, RTS0_C_TANS_C, SEL_SCIF0_2), 796 PINMUX_IPSR_GPSR(IP2_3_0, SUB_TDI), 797 PINMUX_IPSR_GPSR(IP2_3_0, CC5_STATE3), 798 PINMUX_IPSR_GPSR(IP2_3_0, CC5_STATE11), 799 PINMUX_IPSR_GPSR(IP2_3_0, CC5_STATE19), 800 PINMUX_IPSR_GPSR(IP2_3_0, CC5_STATE27), 801 PINMUX_IPSR_GPSR(IP2_3_0, CC5_STATE35), 802 PINMUX_IPSR_MSEL(IP2_7_4, HSCK0, SEL_HSCIF0_0), 803 PINMUX_IPSR_MSEL(IP2_7_4, SCK1, SEL_SCIF1_0), 804 PINMUX_IPSR_GPSR(IP2_7_4, MTS), 805 PINMUX_IPSR_GPSR(IP2_7_4, PWM5), 806 PINMUX_IPSR_MSEL(IP2_7_4, SCK0_C, SEL_SCIF0_2), 807 PINMUX_IPSR_MSEL(IP2_7_4, SSI_SDATA9_B, SEL_SSI9_1), 808 PINMUX_IPSR_GPSR(IP2_7_4, SUB_TDO), 809 PINMUX_IPSR_GPSR(IP2_7_4, CC5_STATE0), 810 PINMUX_IPSR_GPSR(IP2_7_4, CC5_STATE8), 811 PINMUX_IPSR_GPSR(IP2_7_4, CC5_STATE16), 812 PINMUX_IPSR_GPSR(IP2_7_4, CC5_STATE24), 813 PINMUX_IPSR_GPSR(IP2_7_4, CC5_STATE32), 814 PINMUX_IPSR_MSEL(IP2_11_8, HCTS0, SEL_HSCIF0_0), 815 PINMUX_IPSR_MSEL(IP2_11_8, CTS1, SEL_SCIF1_0), 816 PINMUX_IPSR_GPSR(IP2_11_8, STM), 817 PINMUX_IPSR_GPSR(IP2_11_8, PWM0_D), 818 PINMUX_IPSR_MSEL(IP2_11_8, RX0_C, SEL_SCIF0_2), 819 PINMUX_IPSR_MSEL(IP2_11_8, SCIF_CLK_C, SEL_SCIF_2), 820 PINMUX_IPSR_GPSR(IP2_11_8, SUB_TRST), 821 PINMUX_IPSR_MSEL(IP2_11_8, TCLK1_B, SEL_TMU1_1), 822 PINMUX_IPSR_GPSR(IP2_11_8, CC5_OSCOUT), 823 PINMUX_IPSR_MSEL(IP2_15_12, HRTS0, SEL_HSCIF0_0), 824 PINMUX_IPSR_MSEL(IP2_15_12, RTS1_TANS, SEL_SCIF1_0), 825 PINMUX_IPSR_GPSR(IP2_15_12, MDATA), 826 PINMUX_IPSR_GPSR(IP2_15_12, TX0_C), 827 PINMUX_IPSR_GPSR(IP2_15_12, SUB_TMS), 828 PINMUX_IPSR_GPSR(IP2_15_12, CC5_STATE1), 829 PINMUX_IPSR_GPSR(IP2_15_12, CC5_STATE9), 830 PINMUX_IPSR_GPSR(IP2_15_12, CC5_STATE17), 831 PINMUX_IPSR_GPSR(IP2_15_12, CC5_STATE25), 832 PINMUX_IPSR_GPSR(IP2_15_12, CC5_STATE33), 833 PINMUX_IPSR_GPSR(IP2_18_16, DU0_DR0), 834 PINMUX_IPSR_GPSR(IP2_18_16, LCDOUT0), 835 PINMUX_IPSR_MSEL(IP2_18_16, DREQ0, SEL_EXBUS0_0), 836 PINMUX_IPSR_MSEL(IP2_18_16, GPS_CLK_B, SEL_GPS_1), 837 PINMUX_IPSR_GPSR(IP2_18_16, AUDATA0), 838 PINMUX_IPSR_GPSR(IP2_18_16, TX5_C), 839 PINMUX_IPSR_GPSR(IP2_21_19, DU0_DR1), 840 PINMUX_IPSR_GPSR(IP2_21_19, LCDOUT1), 841 PINMUX_IPSR_GPSR(IP2_21_19, DACK0), 842 PINMUX_IPSR_GPSR(IP2_21_19, DRACK0), 843 PINMUX_IPSR_MSEL(IP2_21_19, GPS_SIGN_B, SEL_GPS_1), 844 PINMUX_IPSR_GPSR(IP2_21_19, AUDATA1), 845 PINMUX_IPSR_MSEL(IP2_21_19, RX5_C, SEL_SCIF5_2), 846 PINMUX_IPSR_GPSR(IP2_22, DU0_DR2), 847 PINMUX_IPSR_GPSR(IP2_22, LCDOUT2), 848 PINMUX_IPSR_GPSR(IP2_23, DU0_DR3), 849 PINMUX_IPSR_GPSR(IP2_23, LCDOUT3), 850 PINMUX_IPSR_GPSR(IP2_24, DU0_DR4), 851 PINMUX_IPSR_GPSR(IP2_24, LCDOUT4), 852 PINMUX_IPSR_GPSR(IP2_25, DU0_DR5), 853 PINMUX_IPSR_GPSR(IP2_25, LCDOUT5), 854 PINMUX_IPSR_GPSR(IP2_26, DU0_DR6), 855 PINMUX_IPSR_GPSR(IP2_26, LCDOUT6), 856 PINMUX_IPSR_GPSR(IP2_27, DU0_DR7), 857 PINMUX_IPSR_GPSR(IP2_27, LCDOUT7), 858 PINMUX_IPSR_GPSR(IP2_30_28, DU0_DG0), 859 PINMUX_IPSR_GPSR(IP2_30_28, LCDOUT8), 860 PINMUX_IPSR_MSEL(IP2_30_28, DREQ1, SEL_EXBUS1_0), 861 PINMUX_IPSR_MSEL(IP2_30_28, SCL2, SEL_I2C2_0), 862 PINMUX_IPSR_GPSR(IP2_30_28, AUDATA2), 863 864 PINMUX_IPSR_GPSR(IP3_2_0, DU0_DG1), 865 PINMUX_IPSR_GPSR(IP3_2_0, LCDOUT9), 866 PINMUX_IPSR_GPSR(IP3_2_0, DACK1), 867 PINMUX_IPSR_MSEL(IP3_2_0, SDA2, SEL_I2C2_0), 868 PINMUX_IPSR_GPSR(IP3_2_0, AUDATA3), 869 PINMUX_IPSR_GPSR(IP3_3, DU0_DG2), 870 PINMUX_IPSR_GPSR(IP3_3, LCDOUT10), 871 PINMUX_IPSR_GPSR(IP3_4, DU0_DG3), 872 PINMUX_IPSR_GPSR(IP3_4, LCDOUT11), 873 PINMUX_IPSR_GPSR(IP3_5, DU0_DG4), 874 PINMUX_IPSR_GPSR(IP3_5, LCDOUT12), 875 PINMUX_IPSR_GPSR(IP3_6, DU0_DG5), 876 PINMUX_IPSR_GPSR(IP3_6, LCDOUT13), 877 PINMUX_IPSR_GPSR(IP3_7, DU0_DG6), 878 PINMUX_IPSR_GPSR(IP3_7, LCDOUT14), 879 PINMUX_IPSR_GPSR(IP3_8, DU0_DG7), 880 PINMUX_IPSR_GPSR(IP3_8, LCDOUT15), 881 PINMUX_IPSR_GPSR(IP3_11_9, DU0_DB0), 882 PINMUX_IPSR_GPSR(IP3_11_9, LCDOUT16), 883 PINMUX_IPSR_GPSR(IP3_11_9, EX_WAIT1), 884 PINMUX_IPSR_MSEL(IP3_11_9, SCL1, SEL_I2C1_0), 885 PINMUX_IPSR_MSEL(IP3_11_9, TCLK1, SEL_TMU1_0), 886 PINMUX_IPSR_GPSR(IP3_11_9, AUDATA4), 887 PINMUX_IPSR_GPSR(IP3_14_12, DU0_DB1), 888 PINMUX_IPSR_GPSR(IP3_14_12, LCDOUT17), 889 PINMUX_IPSR_GPSR(IP3_14_12, EX_WAIT2), 890 PINMUX_IPSR_MSEL(IP3_14_12, SDA1, SEL_I2C1_0), 891 PINMUX_IPSR_MSEL(IP3_14_12, GPS_MAG_B, SEL_GPS_1), 892 PINMUX_IPSR_GPSR(IP3_14_12, AUDATA5), 893 PINMUX_IPSR_MSEL(IP3_14_12, SCK5_C, SEL_SCIF5_2), 894 PINMUX_IPSR_GPSR(IP3_15, DU0_DB2), 895 PINMUX_IPSR_GPSR(IP3_15, LCDOUT18), 896 PINMUX_IPSR_GPSR(IP3_16, DU0_DB3), 897 PINMUX_IPSR_GPSR(IP3_16, LCDOUT19), 898 PINMUX_IPSR_GPSR(IP3_17, DU0_DB4), 899 PINMUX_IPSR_GPSR(IP3_17, LCDOUT20), 900 PINMUX_IPSR_GPSR(IP3_18, DU0_DB5), 901 PINMUX_IPSR_GPSR(IP3_18, LCDOUT21), 902 PINMUX_IPSR_GPSR(IP3_19, DU0_DB6), 903 PINMUX_IPSR_GPSR(IP3_19, LCDOUT22), 904 PINMUX_IPSR_GPSR(IP3_20, DU0_DB7), 905 PINMUX_IPSR_GPSR(IP3_20, LCDOUT23), 906 PINMUX_IPSR_GPSR(IP3_22_21, DU0_DOTCLKIN), 907 PINMUX_IPSR_GPSR(IP3_22_21, QSTVA_QVS), 908 PINMUX_IPSR_GPSR(IP3_22_21, TX3_D_IRDA_TX_D), 909 PINMUX_IPSR_MSEL(IP3_22_21, SCL3_B, SEL_I2C3_1), 910 PINMUX_IPSR_GPSR(IP3_23, DU0_DOTCLKOUT0), 911 PINMUX_IPSR_GPSR(IP3_23, QCLK), 912 PINMUX_IPSR_GPSR(IP3_26_24, DU0_DOTCLKOUT1), 913 PINMUX_IPSR_GPSR(IP3_26_24, QSTVB_QVE), 914 PINMUX_IPSR_MSEL(IP3_26_24, RX3_D_IRDA_RX_D, SEL_SCIF3_3), 915 PINMUX_IPSR_MSEL(IP3_26_24, SDA3_B, SEL_I2C3_1), 916 PINMUX_IPSR_MSEL(IP3_26_24, SDA2_C, SEL_I2C2_2), 917 PINMUX_IPSR_GPSR(IP3_26_24, DACK0_B), 918 PINMUX_IPSR_GPSR(IP3_26_24, DRACK0_B), 919 PINMUX_IPSR_GPSR(IP3_27, DU0_EXHSYNC_DU0_HSYNC), 920 PINMUX_IPSR_GPSR(IP3_27, QSTH_QHS), 921 PINMUX_IPSR_GPSR(IP3_28, DU0_EXVSYNC_DU0_VSYNC), 922 PINMUX_IPSR_GPSR(IP3_28, QSTB_QHE), 923 PINMUX_IPSR_GPSR(IP3_31_29, DU0_EXODDF_DU0_ODDF_DISP_CDE), 924 PINMUX_IPSR_GPSR(IP3_31_29, QCPV_QDE), 925 PINMUX_IPSR_GPSR(IP3_31_29, CAN1_TX), 926 PINMUX_IPSR_GPSR(IP3_31_29, TX2_C), 927 PINMUX_IPSR_MSEL(IP3_31_29, SCL2_C, SEL_I2C2_2), 928 PINMUX_IPSR_GPSR(IP3_31_29, REMOCON), 929 930 PINMUX_IPSR_GPSR(IP4_1_0, DU0_DISP), 931 PINMUX_IPSR_GPSR(IP4_1_0, QPOLA), 932 PINMUX_IPSR_MSEL(IP4_1_0, CAN_CLK_C, SEL_CANCLK_2), 933 PINMUX_IPSR_MSEL(IP4_1_0, SCK2_C, SEL_SCIF2_2), 934 PINMUX_IPSR_GPSR(IP4_4_2, DU0_CDE), 935 PINMUX_IPSR_GPSR(IP4_4_2, QPOLB), 936 PINMUX_IPSR_GPSR(IP4_4_2, CAN1_RX), 937 PINMUX_IPSR_MSEL(IP4_4_2, RX2_C, SEL_SCIF2_2), 938 PINMUX_IPSR_MSEL(IP4_4_2, DREQ0_B, SEL_EXBUS0_1), 939 PINMUX_IPSR_MSEL(IP4_4_2, SSI_SCK78_B, SEL_SSI7_1), 940 PINMUX_IPSR_MSEL(IP4_4_2, SCK0_B, SEL_SCIF0_1), 941 PINMUX_IPSR_GPSR(IP4_7_5, DU1_DR0), 942 PINMUX_IPSR_GPSR(IP4_7_5, VI2_DATA0_VI2_B0), 943 PINMUX_IPSR_GPSR(IP4_7_5, PWM6), 944 PINMUX_IPSR_GPSR(IP4_7_5, SD3_CLK), 945 PINMUX_IPSR_GPSR(IP4_7_5, TX3_E_IRDA_TX_E), 946 PINMUX_IPSR_GPSR(IP4_7_5, AUDCK), 947 PINMUX_IPSR_MSEL(IP4_7_5, PWMFSW0_B, SEL_PWMFSW_1), 948 PINMUX_IPSR_GPSR(IP4_10_8, DU1_DR1), 949 PINMUX_IPSR_GPSR(IP4_10_8, VI2_DATA1_VI2_B1), 950 PINMUX_IPSR_GPSR(IP4_10_8, PWM0), 951 PINMUX_IPSR_GPSR(IP4_10_8, SD3_CMD), 952 PINMUX_IPSR_MSEL(IP4_10_8, RX3_E_IRDA_RX_E, SEL_SCIF3_4), 953 PINMUX_IPSR_GPSR(IP4_10_8, AUDSYNC), 954 PINMUX_IPSR_MSEL(IP4_10_8, CTS0_D, SEL_SCIF0_3), 955 PINMUX_IPSR_GPSR(IP4_11, DU1_DR2), 956 PINMUX_IPSR_GPSR(IP4_11, VI2_G0), 957 PINMUX_IPSR_GPSR(IP4_12, DU1_DR3), 958 PINMUX_IPSR_GPSR(IP4_12, VI2_G1), 959 PINMUX_IPSR_GPSR(IP4_13, DU1_DR4), 960 PINMUX_IPSR_GPSR(IP4_13, VI2_G2), 961 PINMUX_IPSR_GPSR(IP4_14, DU1_DR5), 962 PINMUX_IPSR_GPSR(IP4_14, VI2_G3), 963 PINMUX_IPSR_GPSR(IP4_15, DU1_DR6), 964 PINMUX_IPSR_GPSR(IP4_15, VI2_G4), 965 PINMUX_IPSR_GPSR(IP4_16, DU1_DR7), 966 PINMUX_IPSR_GPSR(IP4_16, VI2_G5), 967 PINMUX_IPSR_GPSR(IP4_19_17, DU1_DG0), 968 PINMUX_IPSR_GPSR(IP4_19_17, VI2_DATA2_VI2_B2), 969 PINMUX_IPSR_MSEL(IP4_19_17, SCL1_B, SEL_I2C1_1), 970 PINMUX_IPSR_GPSR(IP4_19_17, SD3_DAT2), 971 PINMUX_IPSR_MSEL(IP4_19_17, SCK3_E, SEL_SCIF3_4), 972 PINMUX_IPSR_GPSR(IP4_19_17, AUDATA6), 973 PINMUX_IPSR_GPSR(IP4_19_17, TX0_D), 974 PINMUX_IPSR_GPSR(IP4_22_20, DU1_DG1), 975 PINMUX_IPSR_GPSR(IP4_22_20, VI2_DATA3_VI2_B3), 976 PINMUX_IPSR_MSEL(IP4_22_20, SDA1_B, SEL_I2C1_1), 977 PINMUX_IPSR_GPSR(IP4_22_20, SD3_DAT3), 978 PINMUX_IPSR_MSEL(IP4_22_20, SCK5, SEL_SCIF5_0), 979 PINMUX_IPSR_GPSR(IP4_22_20, AUDATA7), 980 PINMUX_IPSR_MSEL(IP4_22_20, RX0_D, SEL_SCIF0_3), 981 PINMUX_IPSR_GPSR(IP4_23, DU1_DG2), 982 PINMUX_IPSR_GPSR(IP4_23, VI2_G6), 983 PINMUX_IPSR_GPSR(IP4_24, DU1_DG3), 984 PINMUX_IPSR_GPSR(IP4_24, VI2_G7), 985 PINMUX_IPSR_GPSR(IP4_25, DU1_DG4), 986 PINMUX_IPSR_GPSR(IP4_25, VI2_R0), 987 PINMUX_IPSR_GPSR(IP4_26, DU1_DG5), 988 PINMUX_IPSR_GPSR(IP4_26, VI2_R1), 989 PINMUX_IPSR_GPSR(IP4_27, DU1_DG6), 990 PINMUX_IPSR_GPSR(IP4_27, VI2_R2), 991 PINMUX_IPSR_GPSR(IP4_28, DU1_DG7), 992 PINMUX_IPSR_GPSR(IP4_28, VI2_R3), 993 PINMUX_IPSR_GPSR(IP4_31_29, DU1_DB0), 994 PINMUX_IPSR_GPSR(IP4_31_29, VI2_DATA4_VI2_B4), 995 PINMUX_IPSR_MSEL(IP4_31_29, SCL2_B, SEL_I2C2_1), 996 PINMUX_IPSR_GPSR(IP4_31_29, SD3_DAT0), 997 PINMUX_IPSR_GPSR(IP4_31_29, TX5), 998 PINMUX_IPSR_MSEL(IP4_31_29, SCK0_D, SEL_SCIF0_3), 999 1000 PINMUX_IPSR_GPSR(IP5_2_0, DU1_DB1), 1001 PINMUX_IPSR_GPSR(IP5_2_0, VI2_DATA5_VI2_B5), 1002 PINMUX_IPSR_MSEL(IP5_2_0, SDA2_B, SEL_I2C2_1), 1003 PINMUX_IPSR_GPSR(IP5_2_0, SD3_DAT1), 1004 PINMUX_IPSR_MSEL(IP5_2_0, RX5, SEL_SCIF5_0), 1005 PINMUX_IPSR_MSEL(IP5_2_0, RTS0_D_TANS_D, SEL_SCIF0_3), 1006 PINMUX_IPSR_GPSR(IP5_3, DU1_DB2), 1007 PINMUX_IPSR_GPSR(IP5_3, VI2_R4), 1008 PINMUX_IPSR_GPSR(IP5_4, DU1_DB3), 1009 PINMUX_IPSR_GPSR(IP5_4, VI2_R5), 1010 PINMUX_IPSR_GPSR(IP5_5, DU1_DB4), 1011 PINMUX_IPSR_GPSR(IP5_5, VI2_R6), 1012 PINMUX_IPSR_GPSR(IP5_6, DU1_DB5), 1013 PINMUX_IPSR_GPSR(IP5_6, VI2_R7), 1014 PINMUX_IPSR_GPSR(IP5_7, DU1_DB6), 1015 PINMUX_IPSR_MSEL(IP5_7, SCL2_D, SEL_I2C2_3), 1016 PINMUX_IPSR_GPSR(IP5_8, DU1_DB7), 1017 PINMUX_IPSR_MSEL(IP5_8, SDA2_D, SEL_I2C2_3), 1018 PINMUX_IPSR_GPSR(IP5_10_9, DU1_DOTCLKIN), 1019 PINMUX_IPSR_GPSR(IP5_10_9, VI2_CLKENB), 1020 PINMUX_IPSR_MSEL(IP5_10_9, HSPI_CS1, SEL_HSPI1_0), 1021 PINMUX_IPSR_MSEL(IP5_10_9, SCL1_D, SEL_I2C1_3), 1022 PINMUX_IPSR_GPSR(IP5_12_11, DU1_DOTCLKOUT), 1023 PINMUX_IPSR_GPSR(IP5_12_11, VI2_FIELD), 1024 PINMUX_IPSR_MSEL(IP5_12_11, SDA1_D, SEL_I2C1_3), 1025 PINMUX_IPSR_GPSR(IP5_14_13, DU1_EXHSYNC_DU1_HSYNC), 1026 PINMUX_IPSR_GPSR(IP5_14_13, VI2_HSYNC), 1027 PINMUX_IPSR_GPSR(IP5_14_13, VI3_HSYNC), 1028 PINMUX_IPSR_GPSR(IP5_16_15, DU1_EXVSYNC_DU1_VSYNC), 1029 PINMUX_IPSR_GPSR(IP5_16_15, VI2_VSYNC), 1030 PINMUX_IPSR_GPSR(IP5_16_15, VI3_VSYNC), 1031 PINMUX_IPSR_GPSR(IP5_20_17, DU1_EXODDF_DU1_ODDF_DISP_CDE), 1032 PINMUX_IPSR_GPSR(IP5_20_17, VI2_CLK), 1033 PINMUX_IPSR_GPSR(IP5_20_17, TX3_B_IRDA_TX_B), 1034 PINMUX_IPSR_GPSR(IP5_20_17, SD3_CD), 1035 PINMUX_IPSR_GPSR(IP5_20_17, HSPI_TX1), 1036 PINMUX_IPSR_GPSR(IP5_20_17, VI1_CLKENB), 1037 PINMUX_IPSR_GPSR(IP5_20_17, VI3_CLKENB), 1038 PINMUX_IPSR_GPSR(IP5_20_17, AUDIO_CLKC), 1039 PINMUX_IPSR_GPSR(IP5_20_17, TX2_D), 1040 PINMUX_IPSR_GPSR(IP5_20_17, SPEEDIN), 1041 PINMUX_IPSR_MSEL(IP5_20_17, GPS_SIGN_D, SEL_GPS_3), 1042 PINMUX_IPSR_GPSR(IP5_23_21, DU1_DISP), 1043 PINMUX_IPSR_GPSR(IP5_23_21, VI2_DATA6_VI2_B6), 1044 PINMUX_IPSR_MSEL(IP5_23_21, TCLK0, SEL_TMU0_0), 1045 PINMUX_IPSR_GPSR(IP5_23_21, QSTVA_B_QVS_B), 1046 PINMUX_IPSR_MSEL(IP5_23_21, HSPI_CLK1, SEL_HSPI1_0), 1047 PINMUX_IPSR_MSEL(IP5_23_21, SCK2_D, SEL_SCIF2_3), 1048 PINMUX_IPSR_GPSR(IP5_23_21, AUDIO_CLKOUT_B), 1049 PINMUX_IPSR_MSEL(IP5_23_21, GPS_MAG_D, SEL_GPS_3), 1050 PINMUX_IPSR_GPSR(IP5_27_24, DU1_CDE), 1051 PINMUX_IPSR_GPSR(IP5_27_24, VI2_DATA7_VI2_B7), 1052 PINMUX_IPSR_MSEL(IP5_27_24, RX3_B_IRDA_RX_B, SEL_SCIF3_1), 1053 PINMUX_IPSR_GPSR(IP5_27_24, SD3_WP), 1054 PINMUX_IPSR_MSEL(IP5_27_24, HSPI_RX1, SEL_HSPI1_0), 1055 PINMUX_IPSR_GPSR(IP5_27_24, VI1_FIELD), 1056 PINMUX_IPSR_GPSR(IP5_27_24, VI3_FIELD), 1057 PINMUX_IPSR_GPSR(IP5_27_24, AUDIO_CLKOUT), 1058 PINMUX_IPSR_MSEL(IP5_27_24, RX2_D, SEL_SCIF2_3), 1059 PINMUX_IPSR_MSEL(IP5_27_24, GPS_CLK_C, SEL_GPS_2), 1060 PINMUX_IPSR_MSEL(IP5_27_24, GPS_CLK_D, SEL_GPS_3), 1061 PINMUX_IPSR_GPSR(IP5_28, AUDIO_CLKA), 1062 PINMUX_IPSR_GPSR(IP5_28, CAN_TXCLK), 1063 PINMUX_IPSR_GPSR(IP5_30_29, AUDIO_CLKB), 1064 PINMUX_IPSR_GPSR(IP5_30_29, USB_OVC2), 1065 PINMUX_IPSR_GPSR(IP5_30_29, CAN_DEBUGOUT0), 1066 PINMUX_IPSR_GPSR(IP5_30_29, MOUT0), 1067 1068 PINMUX_IPSR_GPSR(IP6_1_0, SSI_SCK0129), 1069 PINMUX_IPSR_GPSR(IP6_1_0, CAN_DEBUGOUT1), 1070 PINMUX_IPSR_GPSR(IP6_1_0, MOUT1), 1071 PINMUX_IPSR_GPSR(IP6_3_2, SSI_WS0129), 1072 PINMUX_IPSR_GPSR(IP6_3_2, CAN_DEBUGOUT2), 1073 PINMUX_IPSR_GPSR(IP6_3_2, MOUT2), 1074 PINMUX_IPSR_GPSR(IP6_5_4, SSI_SDATA0), 1075 PINMUX_IPSR_GPSR(IP6_5_4, CAN_DEBUGOUT3), 1076 PINMUX_IPSR_GPSR(IP6_5_4, MOUT5), 1077 PINMUX_IPSR_GPSR(IP6_7_6, SSI_SDATA1), 1078 PINMUX_IPSR_GPSR(IP6_7_6, CAN_DEBUGOUT4), 1079 PINMUX_IPSR_GPSR(IP6_7_6, MOUT6), 1080 PINMUX_IPSR_GPSR(IP6_8, SSI_SDATA2), 1081 PINMUX_IPSR_GPSR(IP6_8, CAN_DEBUGOUT5), 1082 PINMUX_IPSR_GPSR(IP6_11_9, SSI_SCK34), 1083 PINMUX_IPSR_GPSR(IP6_11_9, CAN_DEBUGOUT6), 1084 PINMUX_IPSR_GPSR(IP6_11_9, CAN0_TX_B), 1085 PINMUX_IPSR_MSEL(IP6_11_9, IERX, SEL_IE_0), 1086 PINMUX_IPSR_MSEL(IP6_11_9, SSI_SCK9_C, SEL_SSI9_2), 1087 PINMUX_IPSR_GPSR(IP6_14_12, SSI_WS34), 1088 PINMUX_IPSR_GPSR(IP6_14_12, CAN_DEBUGOUT7), 1089 PINMUX_IPSR_MSEL(IP6_14_12, CAN0_RX_B, SEL_CAN0_1), 1090 PINMUX_IPSR_GPSR(IP6_14_12, IETX), 1091 PINMUX_IPSR_MSEL(IP6_14_12, SSI_WS9_C, SEL_SSI9_2), 1092 PINMUX_IPSR_GPSR(IP6_17_15, SSI_SDATA3), 1093 PINMUX_IPSR_GPSR(IP6_17_15, PWM0_C), 1094 PINMUX_IPSR_GPSR(IP6_17_15, CAN_DEBUGOUT8), 1095 PINMUX_IPSR_MSEL(IP6_17_15, CAN_CLK_B, SEL_CANCLK_1), 1096 PINMUX_IPSR_MSEL(IP6_17_15, IECLK, SEL_IE_0), 1097 PINMUX_IPSR_MSEL(IP6_17_15, SCIF_CLK_B, SEL_SCIF_1), 1098 PINMUX_IPSR_MSEL(IP6_17_15, TCLK0_B, SEL_TMU0_1), 1099 PINMUX_IPSR_GPSR(IP6_19_18, SSI_SDATA4), 1100 PINMUX_IPSR_GPSR(IP6_19_18, CAN_DEBUGOUT9), 1101 PINMUX_IPSR_MSEL(IP6_19_18, SSI_SDATA9_C, SEL_SSI9_2), 1102 PINMUX_IPSR_GPSR(IP6_22_20, SSI_SCK5), 1103 PINMUX_IPSR_GPSR(IP6_22_20, ADICLK), 1104 PINMUX_IPSR_GPSR(IP6_22_20, CAN_DEBUGOUT10), 1105 PINMUX_IPSR_MSEL(IP6_22_20, SCK3, SEL_SCIF3_0), 1106 PINMUX_IPSR_MSEL(IP6_22_20, TCLK0_D, SEL_TMU0_3), 1107 PINMUX_IPSR_GPSR(IP6_24_23, SSI_WS5), 1108 PINMUX_IPSR_MSEL(IP6_24_23, ADICS_SAMP, SEL_ADI_0), 1109 PINMUX_IPSR_GPSR(IP6_24_23, CAN_DEBUGOUT11), 1110 PINMUX_IPSR_GPSR(IP6_24_23, TX3_IRDA_TX), 1111 PINMUX_IPSR_GPSR(IP6_26_25, SSI_SDATA5), 1112 PINMUX_IPSR_MSEL(IP6_26_25, ADIDATA, SEL_ADI_0), 1113 PINMUX_IPSR_GPSR(IP6_26_25, CAN_DEBUGOUT12), 1114 PINMUX_IPSR_MSEL(IP6_26_25, RX3_IRDA_RX, SEL_SCIF3_0), 1115 PINMUX_IPSR_GPSR(IP6_30_29, SSI_SCK6), 1116 PINMUX_IPSR_GPSR(IP6_30_29, ADICHS0), 1117 PINMUX_IPSR_GPSR(IP6_30_29, CAN0_TX), 1118 PINMUX_IPSR_MSEL(IP6_30_29, IERX_B, SEL_IE_1), 1119 1120 PINMUX_IPSR_GPSR(IP7_1_0, SSI_WS6), 1121 PINMUX_IPSR_GPSR(IP7_1_0, ADICHS1), 1122 PINMUX_IPSR_MSEL(IP7_1_0, CAN0_RX, SEL_CAN0_0), 1123 PINMUX_IPSR_GPSR(IP7_1_0, IETX_B), 1124 PINMUX_IPSR_GPSR(IP7_3_2, SSI_SDATA6), 1125 PINMUX_IPSR_GPSR(IP7_3_2, ADICHS2), 1126 PINMUX_IPSR_MSEL(IP7_3_2, CAN_CLK, SEL_CANCLK_0), 1127 PINMUX_IPSR_MSEL(IP7_3_2, IECLK_B, SEL_IE_1), 1128 PINMUX_IPSR_MSEL(IP7_6_4, SSI_SCK78, SEL_SSI7_0), 1129 PINMUX_IPSR_GPSR(IP7_6_4, CAN_DEBUGOUT13), 1130 PINMUX_IPSR_MSEL(IP7_6_4, IRQ0_B, SEL_INT0_1), 1131 PINMUX_IPSR_MSEL(IP7_6_4, SSI_SCK9_B, SEL_SSI9_1), 1132 PINMUX_IPSR_MSEL(IP7_6_4, HSPI_CLK1_C, SEL_HSPI1_2), 1133 PINMUX_IPSR_MSEL(IP7_9_7, SSI_WS78, SEL_SSI7_0), 1134 PINMUX_IPSR_GPSR(IP7_9_7, CAN_DEBUGOUT14), 1135 PINMUX_IPSR_MSEL(IP7_9_7, IRQ1_B, SEL_INT1_1), 1136 PINMUX_IPSR_MSEL(IP7_9_7, SSI_WS9_B, SEL_SSI9_1), 1137 PINMUX_IPSR_MSEL(IP7_9_7, HSPI_CS1_C, SEL_HSPI1_2), 1138 PINMUX_IPSR_MSEL(IP7_12_10, SSI_SDATA7, SEL_SSI7_0), 1139 PINMUX_IPSR_GPSR(IP7_12_10, CAN_DEBUGOUT15), 1140 PINMUX_IPSR_MSEL(IP7_12_10, IRQ2_B, SEL_INT2_1), 1141 PINMUX_IPSR_MSEL(IP7_12_10, TCLK1_C, SEL_TMU1_2), 1142 PINMUX_IPSR_GPSR(IP7_12_10, HSPI_TX1_C), 1143 PINMUX_IPSR_MSEL(IP7_14_13, SSI_SDATA8, SEL_SSI8_0), 1144 PINMUX_IPSR_GPSR(IP7_14_13, VSP), 1145 PINMUX_IPSR_MSEL(IP7_14_13, IRQ3_B, SEL_INT3_1), 1146 PINMUX_IPSR_MSEL(IP7_14_13, HSPI_RX1_C, SEL_HSPI1_2), 1147 PINMUX_IPSR_GPSR(IP7_16_15, SD0_CLK), 1148 PINMUX_IPSR_GPSR(IP7_16_15, ATACS01), 1149 PINMUX_IPSR_MSEL(IP7_16_15, SCK1_B, SEL_SCIF1_1), 1150 PINMUX_IPSR_GPSR(IP7_18_17, SD0_CMD), 1151 PINMUX_IPSR_GPSR(IP7_18_17, ATACS11), 1152 PINMUX_IPSR_GPSR(IP7_18_17, TX1_B), 1153 PINMUX_IPSR_GPSR(IP7_18_17, CC5_TDO), 1154 PINMUX_IPSR_GPSR(IP7_20_19, SD0_DAT0), 1155 PINMUX_IPSR_GPSR(IP7_20_19, ATADIR1), 1156 PINMUX_IPSR_MSEL(IP7_20_19, RX1_B, SEL_SCIF1_1), 1157 PINMUX_IPSR_GPSR(IP7_20_19, CC5_TRST), 1158 PINMUX_IPSR_GPSR(IP7_22_21, SD0_DAT1), 1159 PINMUX_IPSR_GPSR(IP7_22_21, ATAG1), 1160 PINMUX_IPSR_MSEL(IP7_22_21, SCK2_B, SEL_SCIF2_1), 1161 PINMUX_IPSR_GPSR(IP7_22_21, CC5_TMS), 1162 PINMUX_IPSR_GPSR(IP7_24_23, SD0_DAT2), 1163 PINMUX_IPSR_GPSR(IP7_24_23, ATARD1), 1164 PINMUX_IPSR_GPSR(IP7_24_23, TX2_B), 1165 PINMUX_IPSR_GPSR(IP7_24_23, CC5_TCK), 1166 PINMUX_IPSR_GPSR(IP7_26_25, SD0_DAT3), 1167 PINMUX_IPSR_GPSR(IP7_26_25, ATAWR1), 1168 PINMUX_IPSR_MSEL(IP7_26_25, RX2_B, SEL_SCIF2_1), 1169 PINMUX_IPSR_GPSR(IP7_26_25, CC5_TDI), 1170 PINMUX_IPSR_GPSR(IP7_28_27, SD0_CD), 1171 PINMUX_IPSR_MSEL(IP7_28_27, DREQ2, SEL_EXBUS2_0), 1172 PINMUX_IPSR_MSEL(IP7_28_27, RTS1_B_TANS_B, SEL_SCIF1_1), 1173 PINMUX_IPSR_GPSR(IP7_30_29, SD0_WP), 1174 PINMUX_IPSR_GPSR(IP7_30_29, DACK2), 1175 PINMUX_IPSR_MSEL(IP7_30_29, CTS1_B, SEL_SCIF1_1), 1176 1177 PINMUX_IPSR_GPSR(IP8_3_0, HSPI_CLK0), 1178 PINMUX_IPSR_MSEL(IP8_3_0, CTS0, SEL_SCIF0_0), 1179 PINMUX_IPSR_GPSR(IP8_3_0, USB_OVC0), 1180 PINMUX_IPSR_GPSR(IP8_3_0, AD_CLK), 1181 PINMUX_IPSR_GPSR(IP8_3_0, CC5_STATE4), 1182 PINMUX_IPSR_GPSR(IP8_3_0, CC5_STATE12), 1183 PINMUX_IPSR_GPSR(IP8_3_0, CC5_STATE20), 1184 PINMUX_IPSR_GPSR(IP8_3_0, CC5_STATE28), 1185 PINMUX_IPSR_GPSR(IP8_3_0, CC5_STATE36), 1186 PINMUX_IPSR_GPSR(IP8_7_4, HSPI_CS0), 1187 PINMUX_IPSR_MSEL(IP8_7_4, RTS0_TANS, SEL_SCIF0_0), 1188 PINMUX_IPSR_GPSR(IP8_7_4, USB_OVC1), 1189 PINMUX_IPSR_GPSR(IP8_7_4, AD_DI), 1190 PINMUX_IPSR_GPSR(IP8_7_4, CC5_STATE5), 1191 PINMUX_IPSR_GPSR(IP8_7_4, CC5_STATE13), 1192 PINMUX_IPSR_GPSR(IP8_7_4, CC5_STATE21), 1193 PINMUX_IPSR_GPSR(IP8_7_4, CC5_STATE29), 1194 PINMUX_IPSR_GPSR(IP8_7_4, CC5_STATE37), 1195 PINMUX_IPSR_GPSR(IP8_11_8, HSPI_TX0), 1196 PINMUX_IPSR_GPSR(IP8_11_8, TX0), 1197 PINMUX_IPSR_GPSR(IP8_11_8, CAN_DEBUG_HW_TRIGGER), 1198 PINMUX_IPSR_GPSR(IP8_11_8, AD_DO), 1199 PINMUX_IPSR_GPSR(IP8_11_8, CC5_STATE6), 1200 PINMUX_IPSR_GPSR(IP8_11_8, CC5_STATE14), 1201 PINMUX_IPSR_GPSR(IP8_11_8, CC5_STATE22), 1202 PINMUX_IPSR_GPSR(IP8_11_8, CC5_STATE30), 1203 PINMUX_IPSR_GPSR(IP8_11_8, CC5_STATE38), 1204 PINMUX_IPSR_GPSR(IP8_15_12, HSPI_RX0), 1205 PINMUX_IPSR_MSEL(IP8_15_12, RX0, SEL_SCIF0_0), 1206 PINMUX_IPSR_GPSR(IP8_15_12, CAN_STEP0), 1207 PINMUX_IPSR_GPSR(IP8_15_12, AD_NCS), 1208 PINMUX_IPSR_GPSR(IP8_15_12, CC5_STATE7), 1209 PINMUX_IPSR_GPSR(IP8_15_12, CC5_STATE15), 1210 PINMUX_IPSR_GPSR(IP8_15_12, CC5_STATE23), 1211 PINMUX_IPSR_GPSR(IP8_15_12, CC5_STATE31), 1212 PINMUX_IPSR_GPSR(IP8_15_12, CC5_STATE39), 1213 PINMUX_IPSR_GPSR(IP8_17_16, FMCLK), 1214 PINMUX_IPSR_GPSR(IP8_17_16, RDS_CLK), 1215 PINMUX_IPSR_GPSR(IP8_17_16, PCMOE), 1216 PINMUX_IPSR_GPSR(IP8_18, BPFCLK), 1217 PINMUX_IPSR_GPSR(IP8_18, PCMWE), 1218 PINMUX_IPSR_GPSR(IP8_19, FMIN), 1219 PINMUX_IPSR_GPSR(IP8_19, RDS_DATA), 1220 PINMUX_IPSR_GPSR(IP8_20, VI0_CLK), 1221 PINMUX_IPSR_GPSR(IP8_20, MMC1_CLK), 1222 PINMUX_IPSR_GPSR(IP8_22_21, VI0_CLKENB), 1223 PINMUX_IPSR_GPSR(IP8_22_21, TX1_C), 1224 PINMUX_IPSR_GPSR(IP8_22_21, HTX1_B), 1225 PINMUX_IPSR_GPSR(IP8_22_21, MT1_SYNC), 1226 PINMUX_IPSR_GPSR(IP8_24_23, VI0_FIELD), 1227 PINMUX_IPSR_MSEL(IP8_24_23, RX1_C, SEL_SCIF1_2), 1228 PINMUX_IPSR_MSEL(IP8_24_23, HRX1_B, SEL_HSCIF1_1), 1229 PINMUX_IPSR_GPSR(IP8_27_25, VI0_HSYNC), 1230 PINMUX_IPSR_MSEL(IP8_27_25, VI0_DATA0_B_VI0_B0_B, SEL_VI0_1), 1231 PINMUX_IPSR_MSEL(IP8_27_25, CTS1_C, SEL_SCIF1_2), 1232 PINMUX_IPSR_GPSR(IP8_27_25, TX4_D), 1233 PINMUX_IPSR_GPSR(IP8_27_25, MMC1_CMD), 1234 PINMUX_IPSR_MSEL(IP8_27_25, HSCK1_B, SEL_HSCIF1_1), 1235 PINMUX_IPSR_GPSR(IP8_30_28, VI0_VSYNC), 1236 PINMUX_IPSR_MSEL(IP8_30_28, VI0_DATA1_B_VI0_B1_B, SEL_VI0_1), 1237 PINMUX_IPSR_MSEL(IP8_30_28, RTS1_C_TANS_C, SEL_SCIF1_2), 1238 PINMUX_IPSR_MSEL(IP8_30_28, RX4_D, SEL_SCIF4_3), 1239 PINMUX_IPSR_MSEL(IP8_30_28, PWMFSW0_C, SEL_PWMFSW_2), 1240 1241 PINMUX_IPSR_MSEL(IP9_1_0, VI0_DATA0_VI0_B0, SEL_VI0_0), 1242 PINMUX_IPSR_MSEL(IP9_1_0, HRTS1_B, SEL_HSCIF1_1), 1243 PINMUX_IPSR_GPSR(IP9_1_0, MT1_VCXO), 1244 PINMUX_IPSR_MSEL(IP9_3_2, VI0_DATA1_VI0_B1, SEL_VI0_0), 1245 PINMUX_IPSR_MSEL(IP9_3_2, HCTS1_B, SEL_HSCIF1_1), 1246 PINMUX_IPSR_GPSR(IP9_3_2, MT1_PWM), 1247 PINMUX_IPSR_GPSR(IP9_4, VI0_DATA2_VI0_B2), 1248 PINMUX_IPSR_GPSR(IP9_4, MMC1_D0), 1249 PINMUX_IPSR_GPSR(IP9_5, VI0_DATA3_VI0_B3), 1250 PINMUX_IPSR_GPSR(IP9_5, MMC1_D1), 1251 PINMUX_IPSR_GPSR(IP9_6, VI0_DATA4_VI0_B4), 1252 PINMUX_IPSR_GPSR(IP9_6, MMC1_D2), 1253 PINMUX_IPSR_GPSR(IP9_7, VI0_DATA5_VI0_B5), 1254 PINMUX_IPSR_GPSR(IP9_7, MMC1_D3), 1255 PINMUX_IPSR_GPSR(IP9_9_8, VI0_DATA6_VI0_B6), 1256 PINMUX_IPSR_GPSR(IP9_9_8, MMC1_D4), 1257 PINMUX_IPSR_GPSR(IP9_9_8, ARM_TRACEDATA_0), 1258 PINMUX_IPSR_GPSR(IP9_11_10, VI0_DATA7_VI0_B7), 1259 PINMUX_IPSR_GPSR(IP9_11_10, MMC1_D5), 1260 PINMUX_IPSR_GPSR(IP9_11_10, ARM_TRACEDATA_1), 1261 PINMUX_IPSR_GPSR(IP9_13_12, VI0_G0), 1262 PINMUX_IPSR_MSEL(IP9_13_12, SSI_SCK78_C, SEL_SSI7_2), 1263 PINMUX_IPSR_MSEL(IP9_13_12, IRQ0, SEL_INT0_0), 1264 PINMUX_IPSR_GPSR(IP9_13_12, ARM_TRACEDATA_2), 1265 PINMUX_IPSR_GPSR(IP9_15_14, VI0_G1), 1266 PINMUX_IPSR_MSEL(IP9_15_14, SSI_WS78_C, SEL_SSI7_2), 1267 PINMUX_IPSR_MSEL(IP9_15_14, IRQ1, SEL_INT1_0), 1268 PINMUX_IPSR_GPSR(IP9_15_14, ARM_TRACEDATA_3), 1269 PINMUX_IPSR_GPSR(IP9_18_16, VI0_G2), 1270 PINMUX_IPSR_GPSR(IP9_18_16, ETH_TXD1), 1271 PINMUX_IPSR_GPSR(IP9_18_16, MMC1_D6), 1272 PINMUX_IPSR_GPSR(IP9_18_16, ARM_TRACEDATA_4), 1273 PINMUX_IPSR_GPSR(IP9_18_16, TS_SPSYNC0), 1274 PINMUX_IPSR_GPSR(IP9_21_19, VI0_G3), 1275 PINMUX_IPSR_GPSR(IP9_21_19, ETH_CRS_DV), 1276 PINMUX_IPSR_GPSR(IP9_21_19, MMC1_D7), 1277 PINMUX_IPSR_GPSR(IP9_21_19, ARM_TRACEDATA_5), 1278 PINMUX_IPSR_GPSR(IP9_21_19, TS_SDAT0), 1279 PINMUX_IPSR_GPSR(IP9_23_22, VI0_G4), 1280 PINMUX_IPSR_GPSR(IP9_23_22, ETH_TX_EN), 1281 PINMUX_IPSR_MSEL(IP9_23_22, SD2_DAT0_B, SEL_SD2_1), 1282 PINMUX_IPSR_GPSR(IP9_23_22, ARM_TRACEDATA_6), 1283 PINMUX_IPSR_GPSR(IP9_25_24, VI0_G5), 1284 PINMUX_IPSR_GPSR(IP9_25_24, ETH_RX_ER), 1285 PINMUX_IPSR_MSEL(IP9_25_24, SD2_DAT1_B, SEL_SD2_1), 1286 PINMUX_IPSR_GPSR(IP9_25_24, ARM_TRACEDATA_7), 1287 PINMUX_IPSR_GPSR(IP9_27_26, VI0_G6), 1288 PINMUX_IPSR_GPSR(IP9_27_26, ETH_RXD0), 1289 PINMUX_IPSR_MSEL(IP9_27_26, SD2_DAT2_B, SEL_SD2_1), 1290 PINMUX_IPSR_GPSR(IP9_27_26, ARM_TRACEDATA_8), 1291 PINMUX_IPSR_GPSR(IP9_29_28, VI0_G7), 1292 PINMUX_IPSR_GPSR(IP9_29_28, ETH_RXD1), 1293 PINMUX_IPSR_MSEL(IP9_29_28, SD2_DAT3_B, SEL_SD2_1), 1294 PINMUX_IPSR_GPSR(IP9_29_28, ARM_TRACEDATA_9), 1295 1296 PINMUX_IPSR_GPSR(IP10_2_0, VI0_R0), 1297 PINMUX_IPSR_MSEL(IP10_2_0, SSI_SDATA7_C, SEL_SSI7_2), 1298 PINMUX_IPSR_MSEL(IP10_2_0, SCK1_C, SEL_SCIF1_2), 1299 PINMUX_IPSR_MSEL(IP10_2_0, DREQ1_B, SEL_EXBUS1_0), 1300 PINMUX_IPSR_GPSR(IP10_2_0, ARM_TRACEDATA_10), 1301 PINMUX_IPSR_MSEL(IP10_2_0, DREQ0_C, SEL_EXBUS0_2), 1302 PINMUX_IPSR_GPSR(IP10_5_3, VI0_R1), 1303 PINMUX_IPSR_MSEL(IP10_5_3, SSI_SDATA8_C, SEL_SSI8_2), 1304 PINMUX_IPSR_GPSR(IP10_5_3, DACK1_B), 1305 PINMUX_IPSR_GPSR(IP10_5_3, ARM_TRACEDATA_11), 1306 PINMUX_IPSR_GPSR(IP10_5_3, DACK0_C), 1307 PINMUX_IPSR_GPSR(IP10_5_3, DRACK0_C), 1308 PINMUX_IPSR_GPSR(IP10_8_6, VI0_R2), 1309 PINMUX_IPSR_GPSR(IP10_8_6, ETH_LINK), 1310 PINMUX_IPSR_GPSR(IP10_8_6, SD2_CLK_B), 1311 PINMUX_IPSR_MSEL(IP10_8_6, IRQ2, SEL_INT2_0), 1312 PINMUX_IPSR_GPSR(IP10_8_6, ARM_TRACEDATA_12), 1313 PINMUX_IPSR_GPSR(IP10_11_9, VI0_R3), 1314 PINMUX_IPSR_GPSR(IP10_11_9, ETH_MAGIC), 1315 PINMUX_IPSR_MSEL(IP10_11_9, SD2_CMD_B, SEL_SD2_1), 1316 PINMUX_IPSR_MSEL(IP10_11_9, IRQ3, SEL_INT3_0), 1317 PINMUX_IPSR_GPSR(IP10_11_9, ARM_TRACEDATA_13), 1318 PINMUX_IPSR_GPSR(IP10_14_12, VI0_R4), 1319 PINMUX_IPSR_GPSR(IP10_14_12, ETH_REFCLK), 1320 PINMUX_IPSR_MSEL(IP10_14_12, SD2_CD_B, SEL_SD2_1), 1321 PINMUX_IPSR_MSEL(IP10_14_12, HSPI_CLK1_B, SEL_HSPI1_1), 1322 PINMUX_IPSR_GPSR(IP10_14_12, ARM_TRACEDATA_14), 1323 PINMUX_IPSR_GPSR(IP10_14_12, MT1_CLK), 1324 PINMUX_IPSR_GPSR(IP10_14_12, TS_SCK0), 1325 PINMUX_IPSR_GPSR(IP10_17_15, VI0_R5), 1326 PINMUX_IPSR_GPSR(IP10_17_15, ETH_TXD0), 1327 PINMUX_IPSR_MSEL(IP10_17_15, SD2_WP_B, SEL_SD2_1), 1328 PINMUX_IPSR_MSEL(IP10_17_15, HSPI_CS1_B, SEL_HSPI1_1), 1329 PINMUX_IPSR_GPSR(IP10_17_15, ARM_TRACEDATA_15), 1330 PINMUX_IPSR_GPSR(IP10_17_15, MT1_D), 1331 PINMUX_IPSR_GPSR(IP10_17_15, TS_SDEN0), 1332 PINMUX_IPSR_GPSR(IP10_20_18, VI0_R6), 1333 PINMUX_IPSR_GPSR(IP10_20_18, ETH_MDC), 1334 PINMUX_IPSR_MSEL(IP10_20_18, DREQ2_C, SEL_EXBUS2_2), 1335 PINMUX_IPSR_GPSR(IP10_20_18, HSPI_TX1_B), 1336 PINMUX_IPSR_GPSR(IP10_20_18, TRACECLK), 1337 PINMUX_IPSR_GPSR(IP10_20_18, MT1_BEN), 1338 PINMUX_IPSR_MSEL(IP10_20_18, PWMFSW0_D, SEL_PWMFSW_3), 1339 PINMUX_IPSR_GPSR(IP10_23_21, VI0_R7), 1340 PINMUX_IPSR_GPSR(IP10_23_21, ETH_MDIO), 1341 PINMUX_IPSR_GPSR(IP10_23_21, DACK2_C), 1342 PINMUX_IPSR_MSEL(IP10_23_21, HSPI_RX1_B, SEL_HSPI1_1), 1343 PINMUX_IPSR_MSEL(IP10_23_21, SCIF_CLK_D, SEL_SCIF_3), 1344 PINMUX_IPSR_GPSR(IP10_23_21, TRACECTL), 1345 PINMUX_IPSR_GPSR(IP10_23_21, MT1_PEN), 1346 PINMUX_IPSR_GPSR(IP10_25_24, VI1_CLK), 1347 PINMUX_IPSR_MSEL(IP10_25_24, SIM_D, SEL_SIM_0), 1348 PINMUX_IPSR_MSEL(IP10_25_24, SDA3, SEL_I2C3_0), 1349 PINMUX_IPSR_GPSR(IP10_28_26, VI1_HSYNC), 1350 PINMUX_IPSR_GPSR(IP10_28_26, VI3_CLK), 1351 PINMUX_IPSR_GPSR(IP10_28_26, SSI_SCK4), 1352 PINMUX_IPSR_MSEL(IP10_28_26, GPS_SIGN_C, SEL_GPS_2), 1353 PINMUX_IPSR_MSEL(IP10_28_26, PWMFSW0_E, SEL_PWMFSW_4), 1354 PINMUX_IPSR_GPSR(IP10_31_29, VI1_VSYNC), 1355 PINMUX_IPSR_GPSR(IP10_31_29, AUDIO_CLKOUT_C), 1356 PINMUX_IPSR_GPSR(IP10_31_29, SSI_WS4), 1357 PINMUX_IPSR_GPSR(IP10_31_29, SIM_CLK), 1358 PINMUX_IPSR_MSEL(IP10_31_29, GPS_MAG_C, SEL_GPS_2), 1359 PINMUX_IPSR_GPSR(IP10_31_29, SPV_TRST), 1360 PINMUX_IPSR_MSEL(IP10_31_29, SCL3, SEL_I2C3_0), 1361 1362 PINMUX_IPSR_GPSR(IP11_2_0, VI1_DATA0_VI1_B0), 1363 PINMUX_IPSR_MSEL(IP11_2_0, SD2_DAT0, SEL_SD2_0), 1364 PINMUX_IPSR_GPSR(IP11_2_0, SIM_RST), 1365 PINMUX_IPSR_GPSR(IP11_2_0, SPV_TCK), 1366 PINMUX_IPSR_GPSR(IP11_2_0, ADICLK_B), 1367 PINMUX_IPSR_GPSR(IP11_5_3, VI1_DATA1_VI1_B1), 1368 PINMUX_IPSR_MSEL(IP11_5_3, SD2_DAT1, SEL_SD2_0), 1369 PINMUX_IPSR_GPSR(IP11_5_3, MT0_CLK), 1370 PINMUX_IPSR_GPSR(IP11_5_3, SPV_TMS), 1371 PINMUX_IPSR_MSEL(IP11_5_3, ADICS_B_SAMP_B, SEL_ADI_1), 1372 PINMUX_IPSR_GPSR(IP11_8_6, VI1_DATA2_VI1_B2), 1373 PINMUX_IPSR_MSEL(IP11_8_6, SD2_DAT2, SEL_SD2_0), 1374 PINMUX_IPSR_GPSR(IP11_8_6, MT0_D), 1375 PINMUX_IPSR_GPSR(IP11_8_6, SPVTDI), 1376 PINMUX_IPSR_MSEL(IP11_8_6, ADIDATA_B, SEL_ADI_1), 1377 PINMUX_IPSR_GPSR(IP11_11_9, VI1_DATA3_VI1_B3), 1378 PINMUX_IPSR_MSEL(IP11_11_9, SD2_DAT3, SEL_SD2_0), 1379 PINMUX_IPSR_GPSR(IP11_11_9, MT0_BEN), 1380 PINMUX_IPSR_GPSR(IP11_11_9, SPV_TDO), 1381 PINMUX_IPSR_GPSR(IP11_11_9, ADICHS0_B), 1382 PINMUX_IPSR_GPSR(IP11_14_12, VI1_DATA4_VI1_B4), 1383 PINMUX_IPSR_GPSR(IP11_14_12, SD2_CLK), 1384 PINMUX_IPSR_GPSR(IP11_14_12, MT0_PEN), 1385 PINMUX_IPSR_GPSR(IP11_14_12, SPA_TRST), 1386 PINMUX_IPSR_MSEL(IP11_14_12, HSPI_CLK1_D, SEL_HSPI1_3), 1387 PINMUX_IPSR_GPSR(IP11_14_12, ADICHS1_B), 1388 PINMUX_IPSR_GPSR(IP11_17_15, VI1_DATA5_VI1_B5), 1389 PINMUX_IPSR_MSEL(IP11_17_15, SD2_CMD, SEL_SD2_0), 1390 PINMUX_IPSR_GPSR(IP11_17_15, MT0_SYNC), 1391 PINMUX_IPSR_GPSR(IP11_17_15, SPA_TCK), 1392 PINMUX_IPSR_MSEL(IP11_17_15, HSPI_CS1_D, SEL_HSPI1_3), 1393 PINMUX_IPSR_GPSR(IP11_17_15, ADICHS2_B), 1394 PINMUX_IPSR_GPSR(IP11_20_18, VI1_DATA6_VI1_B6), 1395 PINMUX_IPSR_MSEL(IP11_20_18, SD2_CD, SEL_SD2_0), 1396 PINMUX_IPSR_GPSR(IP11_20_18, MT0_VCXO), 1397 PINMUX_IPSR_GPSR(IP11_20_18, SPA_TMS), 1398 PINMUX_IPSR_GPSR(IP11_20_18, HSPI_TX1_D), 1399 PINMUX_IPSR_GPSR(IP11_23_21, VI1_DATA7_VI1_B7), 1400 PINMUX_IPSR_MSEL(IP11_23_21, SD2_WP, SEL_SD2_0), 1401 PINMUX_IPSR_GPSR(IP11_23_21, MT0_PWM), 1402 PINMUX_IPSR_GPSR(IP11_23_21, SPA_TDI), 1403 PINMUX_IPSR_MSEL(IP11_23_21, HSPI_RX1_D, SEL_HSPI1_3), 1404 PINMUX_IPSR_GPSR(IP11_26_24, VI1_G0), 1405 PINMUX_IPSR_GPSR(IP11_26_24, VI3_DATA0), 1406 PINMUX_IPSR_GPSR(IP11_26_24, TS_SCK1), 1407 PINMUX_IPSR_MSEL(IP11_26_24, DREQ2_B, SEL_EXBUS2_1), 1408 PINMUX_IPSR_GPSR(IP11_26_24, TX2), 1409 PINMUX_IPSR_GPSR(IP11_26_24, SPA_TDO), 1410 PINMUX_IPSR_MSEL(IP11_26_24, HCTS0_B, SEL_HSCIF0_1), 1411 PINMUX_IPSR_GPSR(IP11_29_27, VI1_G1), 1412 PINMUX_IPSR_GPSR(IP11_29_27, VI3_DATA1), 1413 PINMUX_IPSR_GPSR(IP11_29_27, SSI_SCK1), 1414 PINMUX_IPSR_GPSR(IP11_29_27, TS_SDEN1), 1415 PINMUX_IPSR_GPSR(IP11_29_27, DACK2_B), 1416 PINMUX_IPSR_MSEL(IP11_29_27, RX2, SEL_SCIF2_0), 1417 PINMUX_IPSR_MSEL(IP11_29_27, HRTS0_B, SEL_HSCIF0_1), 1418 1419 PINMUX_IPSR_GPSR(IP12_2_0, VI1_G2), 1420 PINMUX_IPSR_GPSR(IP12_2_0, VI3_DATA2), 1421 PINMUX_IPSR_GPSR(IP12_2_0, SSI_WS1), 1422 PINMUX_IPSR_GPSR(IP12_2_0, TS_SPSYNC1), 1423 PINMUX_IPSR_MSEL(IP12_2_0, SCK2, SEL_SCIF2_0), 1424 PINMUX_IPSR_MSEL(IP12_2_0, HSCK0_B, SEL_HSCIF0_1), 1425 PINMUX_IPSR_GPSR(IP12_5_3, VI1_G3), 1426 PINMUX_IPSR_GPSR(IP12_5_3, VI3_DATA3), 1427 PINMUX_IPSR_GPSR(IP12_5_3, SSI_SCK2), 1428 PINMUX_IPSR_GPSR(IP12_5_3, TS_SDAT1), 1429 PINMUX_IPSR_MSEL(IP12_5_3, SCL1_C, SEL_I2C1_2), 1430 PINMUX_IPSR_GPSR(IP12_5_3, HTX0_B), 1431 PINMUX_IPSR_GPSR(IP12_8_6, VI1_G4), 1432 PINMUX_IPSR_GPSR(IP12_8_6, VI3_DATA4), 1433 PINMUX_IPSR_GPSR(IP12_8_6, SSI_WS2), 1434 PINMUX_IPSR_MSEL(IP12_8_6, SDA1_C, SEL_I2C1_2), 1435 PINMUX_IPSR_GPSR(IP12_8_6, SIM_RST_B), 1436 PINMUX_IPSR_MSEL(IP12_8_6, HRX0_B, SEL_HSCIF0_1), 1437 PINMUX_IPSR_GPSR(IP12_11_9, VI1_G5), 1438 PINMUX_IPSR_GPSR(IP12_11_9, VI3_DATA5), 1439 PINMUX_IPSR_MSEL(IP12_11_9, GPS_CLK, SEL_GPS_0), 1440 PINMUX_IPSR_GPSR(IP12_11_9, FSE), 1441 PINMUX_IPSR_GPSR(IP12_11_9, TX4_B), 1442 PINMUX_IPSR_MSEL(IP12_11_9, SIM_D_B, SEL_SIM_1), 1443 PINMUX_IPSR_GPSR(IP12_14_12, VI1_G6), 1444 PINMUX_IPSR_GPSR(IP12_14_12, VI3_DATA6), 1445 PINMUX_IPSR_MSEL(IP12_14_12, GPS_SIGN, SEL_GPS_0), 1446 PINMUX_IPSR_GPSR(IP12_14_12, FRB), 1447 PINMUX_IPSR_MSEL(IP12_14_12, RX4_B, SEL_SCIF4_1), 1448 PINMUX_IPSR_GPSR(IP12_14_12, SIM_CLK_B), 1449 PINMUX_IPSR_GPSR(IP12_17_15, VI1_G7), 1450 PINMUX_IPSR_GPSR(IP12_17_15, VI3_DATA7), 1451 PINMUX_IPSR_MSEL(IP12_17_15, GPS_MAG, SEL_GPS_0), 1452 PINMUX_IPSR_GPSR(IP12_17_15, FCE), 1453 PINMUX_IPSR_MSEL(IP12_17_15, SCK4_B, SEL_SCIF4_1), 1454 }; 1455 1456 /* 1457 * Pins not associated with a GPIO port. 1458 */ 1459 enum { 1460 GP_ASSIGN_LAST(), 1461 NOGP_ALL(), 1462 }; 1463 1464 static const struct sh_pfc_pin pinmux_pins[] = { 1465 PINMUX_GPIO_GP_ALL(), 1466 PINMUX_NOGP_ALL(), 1467 }; 1468 1469 /* - DU0 -------------------------------------------------------------------- */ 1470 static const unsigned int du0_rgb666_pins[] = { 1471 /* R[7:2], G[7:2], B[7:2] */ 1472 RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 27), RCAR_GP_PIN(5, 26), 1473 RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23), 1474 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 0), 1475 RCAR_GP_PIN(5, 31), RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 29), 1476 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6), 1477 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 3), 1478 }; 1479 static const unsigned int du0_rgb666_mux[] = { 1480 DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK, 1481 DU0_DR3_MARK, DU0_DR2_MARK, 1482 DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK, 1483 DU0_DG3_MARK, DU0_DG2_MARK, 1484 DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK, 1485 DU0_DB3_MARK, DU0_DB2_MARK, 1486 }; 1487 static const unsigned int du0_rgb888_pins[] = { 1488 /* R[7:0], G[7:0], B[7:0] */ 1489 RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 27), RCAR_GP_PIN(5, 26), 1490 RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23), 1491 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 23), RCAR_GP_PIN(6, 2), 1492 RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 0), RCAR_GP_PIN(5, 31), 1493 RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 29), RCAR_GP_PIN(0, 26), 1494 RCAR_GP_PIN(0, 25), RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 7), 1495 RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 4), 1496 RCAR_GP_PIN(6, 3), RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 27), 1497 }; 1498 static const unsigned int du0_rgb888_mux[] = { 1499 DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK, 1500 DU0_DR3_MARK, DU0_DR2_MARK, DU0_DR1_MARK, DU0_DR0_MARK, 1501 DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK, 1502 DU0_DG3_MARK, DU0_DG2_MARK, DU0_DG1_MARK, DU0_DG0_MARK, 1503 DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK, 1504 DU0_DB3_MARK, DU0_DB2_MARK, DU0_DB1_MARK, DU0_DB0_MARK, 1505 }; 1506 static const unsigned int du0_clk_in_pins[] = { 1507 /* CLKIN */ 1508 RCAR_GP_PIN(0, 29), 1509 }; 1510 static const unsigned int du0_clk_in_mux[] = { 1511 DU0_DOTCLKIN_MARK, 1512 }; 1513 static const unsigned int du0_clk_out_0_pins[] = { 1514 /* CLKOUT */ 1515 RCAR_GP_PIN(5, 20), 1516 }; 1517 static const unsigned int du0_clk_out_0_mux[] = { 1518 DU0_DOTCLKOUT0_MARK, 1519 }; 1520 static const unsigned int du0_clk_out_1_pins[] = { 1521 /* CLKOUT */ 1522 RCAR_GP_PIN(0, 30), 1523 }; 1524 static const unsigned int du0_clk_out_1_mux[] = { 1525 DU0_DOTCLKOUT1_MARK, 1526 }; 1527 static const unsigned int du0_sync_0_pins[] = { 1528 /* VSYNC, HSYNC, DISP */ 1529 RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 21), RCAR_GP_PIN(0, 31), 1530 }; 1531 static const unsigned int du0_sync_0_mux[] = { 1532 DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK, 1533 DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK 1534 }; 1535 static const unsigned int du0_sync_1_pins[] = { 1536 /* VSYNC, HSYNC, DISP */ 1537 RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 21), RCAR_GP_PIN(1, 0), 1538 }; 1539 static const unsigned int du0_sync_1_mux[] = { 1540 DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK, 1541 DU0_DISP_MARK 1542 }; 1543 static const unsigned int du0_oddf_pins[] = { 1544 /* ODDF */ 1545 RCAR_GP_PIN(0, 31), 1546 }; 1547 static const unsigned int du0_oddf_mux[] = { 1548 DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK 1549 }; 1550 static const unsigned int du0_cde_pins[] = { 1551 /* CDE */ 1552 RCAR_GP_PIN(1, 1), 1553 }; 1554 static const unsigned int du0_cde_mux[] = { 1555 DU0_CDE_MARK 1556 }; 1557 /* - DU1 -------------------------------------------------------------------- */ 1558 static const unsigned int du1_rgb666_pins[] = { 1559 /* R[7:2], G[7:2], B[7:2] */ 1560 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 7), 1561 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 4), 1562 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15), 1563 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12), 1564 RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23), 1565 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 20), 1566 }; 1567 static const unsigned int du1_rgb666_mux[] = { 1568 DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK, 1569 DU1_DR3_MARK, DU1_DR2_MARK, 1570 DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK, 1571 DU1_DG3_MARK, DU1_DG2_MARK, 1572 DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK, 1573 DU1_DB3_MARK, DU1_DB2_MARK, 1574 }; 1575 static const unsigned int du1_rgb888_pins[] = { 1576 /* R[7:0], G[7:0], B[7:0] */ 1577 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 7), 1578 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 4), 1579 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 17), 1580 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), 1581 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 11), 1582 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 24), 1583 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21), 1584 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), 1585 }; 1586 static const unsigned int du1_rgb888_mux[] = { 1587 DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK, 1588 DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK, 1589 DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK, 1590 DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK, 1591 DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK, 1592 DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK, 1593 }; 1594 static const unsigned int du1_clk_in_pins[] = { 1595 /* CLKIN */ 1596 RCAR_GP_PIN(1, 26), 1597 }; 1598 static const unsigned int du1_clk_in_mux[] = { 1599 DU1_DOTCLKIN_MARK, 1600 }; 1601 static const unsigned int du1_clk_out_pins[] = { 1602 /* CLKOUT */ 1603 RCAR_GP_PIN(1, 27), 1604 }; 1605 static const unsigned int du1_clk_out_mux[] = { 1606 DU1_DOTCLKOUT_MARK, 1607 }; 1608 static const unsigned int du1_sync_0_pins[] = { 1609 /* VSYNC, HSYNC, DISP */ 1610 RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 30), 1611 }; 1612 static const unsigned int du1_sync_0_mux[] = { 1613 DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, 1614 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK 1615 }; 1616 static const unsigned int du1_sync_1_pins[] = { 1617 /* VSYNC, HSYNC, DISP */ 1618 RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 31), 1619 }; 1620 static const unsigned int du1_sync_1_mux[] = { 1621 DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, 1622 DU1_DISP_MARK 1623 }; 1624 static const unsigned int du1_oddf_pins[] = { 1625 /* ODDF */ 1626 RCAR_GP_PIN(1, 30), 1627 }; 1628 static const unsigned int du1_oddf_mux[] = { 1629 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK 1630 }; 1631 static const unsigned int du1_cde_pins[] = { 1632 /* CDE */ 1633 RCAR_GP_PIN(2, 0), 1634 }; 1635 static const unsigned int du1_cde_mux[] = { 1636 DU1_CDE_MARK 1637 }; 1638 /* - Ether ------------------------------------------------------------------ */ 1639 static const unsigned int ether_rmii_pins[] = { 1640 /* 1641 * ETH_TXD0, ETH_TXD1, ETH_TX_EN, ETH_REFCLK, 1642 * ETH_RXD0, ETH_RXD1, ETH_CRS_DV, ETH_RX_ER, 1643 * ETH_MDIO, ETH_MDC 1644 */ 1645 RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 18), 1646 RCAR_GP_PIN(2, 26), 1647 RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 17), 1648 RCAR_GP_PIN(2, 19), 1649 RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 28), 1650 }; 1651 static const unsigned int ether_rmii_mux[] = { 1652 ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK, 1653 ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_CRS_DV_MARK, ETH_RX_ER_MARK, 1654 ETH_MDIO_MARK, ETH_MDC_MARK, 1655 }; 1656 static const unsigned int ether_link_pins[] = { 1657 /* ETH_LINK */ 1658 RCAR_GP_PIN(2, 24), 1659 }; 1660 static const unsigned int ether_link_mux[] = { 1661 ETH_LINK_MARK, 1662 }; 1663 static const unsigned int ether_magic_pins[] = { 1664 /* ETH_MAGIC */ 1665 RCAR_GP_PIN(2, 25), 1666 }; 1667 static const unsigned int ether_magic_mux[] = { 1668 ETH_MAGIC_MARK, 1669 }; 1670 /* - HSCIF0 ----------------------------------------------------------------- */ 1671 static const unsigned int hscif0_data_pins[] = { 1672 /* TX, RX */ 1673 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21) 1674 }; 1675 static const unsigned int hscif0_data_mux[] = { 1676 HTX0_MARK, HRX0_MARK 1677 }; 1678 static const unsigned int hscif0_data_b_pins[] = { 1679 /* TX, RX */ 1680 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13) 1681 }; 1682 static const unsigned int hscif0_data_b_mux[] = { 1683 HTX0_B_MARK, HRX0_B_MARK 1684 }; 1685 static const unsigned int hscif0_ctrl_pins[] = { 1686 /* CTS, RTS */ 1687 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 19) 1688 }; 1689 static const unsigned int hscif0_ctrl_mux[] = { 1690 HCTS0_MARK, HRTS0_MARK 1691 }; 1692 static const unsigned int hscif0_ctrl_b_pins[] = { 1693 /* CTS, RTS */ 1694 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10) 1695 }; 1696 static const unsigned int hscif0_ctrl_b_mux[] = { 1697 HCTS0_B_MARK, HRTS0_B_MARK 1698 }; 1699 static const unsigned int hscif0_clk_pins[] = { 1700 /* SCK */ 1701 RCAR_GP_PIN(4, 17) 1702 }; 1703 static const unsigned int hscif0_clk_mux[] = { 1704 HSCK0_MARK 1705 }; 1706 static const unsigned int hscif0_clk_b_pins[] = { 1707 /* SCK */ 1708 RCAR_GP_PIN(3, 11) 1709 }; 1710 static const unsigned int hscif0_clk_b_mux[] = { 1711 HSCK0_B_MARK 1712 }; 1713 /* - HSCIF1 ----------------------------------------------------------------- */ 1714 static const unsigned int hscif1_data_pins[] = { 1715 /* TX, RX */ 1716 RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20) 1717 }; 1718 static const unsigned int hscif1_data_mux[] = { 1719 HTX1_MARK, HRX1_MARK 1720 }; 1721 static const unsigned int hscif1_data_b_pins[] = { 1722 /* TX, RX */ 1723 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3) 1724 }; 1725 static const unsigned int hscif1_data_b_mux[] = { 1726 HTX1_B_MARK, HRX1_B_MARK 1727 }; 1728 static const unsigned int hscif1_ctrl_pins[] = { 1729 /* CTS, RTS */ 1730 RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 22) 1731 }; 1732 static const unsigned int hscif1_ctrl_mux[] = { 1733 HCTS1_MARK, HRTS1_MARK 1734 }; 1735 static const unsigned int hscif1_ctrl_b_pins[] = { 1736 /* CTS, RTS */ 1737 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6) 1738 }; 1739 static const unsigned int hscif1_ctrl_b_mux[] = { 1740 HCTS1_B_MARK, HRTS1_B_MARK 1741 }; 1742 static const unsigned int hscif1_clk_pins[] = { 1743 /* SCK */ 1744 RCAR_GP_PIN(0, 18) 1745 }; 1746 static const unsigned int hscif1_clk_mux[] = { 1747 HSCK1_MARK 1748 }; 1749 static const unsigned int hscif1_clk_b_pins[] = { 1750 /* SCK */ 1751 RCAR_GP_PIN(2, 4) 1752 }; 1753 static const unsigned int hscif1_clk_b_mux[] = { 1754 HSCK1_B_MARK 1755 }; 1756 /* - HSPI0 ------------------------------------------------------------------ */ 1757 static const unsigned int hspi0_pins[] = { 1758 /* CLK, CS, RX, TX */ 1759 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 25), 1760 RCAR_GP_PIN(4, 24), 1761 }; 1762 static const unsigned int hspi0_mux[] = { 1763 HSPI_CLK0_MARK, HSPI_CS0_MARK, HSPI_RX0_MARK, HSPI_TX0_MARK, 1764 }; 1765 /* - HSPI1 ------------------------------------------------------------------ */ 1766 static const unsigned int hspi1_pins[] = { 1767 /* CLK, CS, RX, TX */ 1768 RCAR_GP_PIN(1, 31), RCAR_GP_PIN(1, 26), RCAR_GP_PIN(2, 0), 1769 RCAR_GP_PIN(1, 30), 1770 }; 1771 static const unsigned int hspi1_mux[] = { 1772 HSPI_CLK1_MARK, HSPI_CS1_MARK, HSPI_RX1_MARK, HSPI_TX1_MARK, 1773 }; 1774 static const unsigned int hspi1_b_pins[] = { 1775 /* CLK, CS, RX, TX */ 1776 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 29), 1777 RCAR_GP_PIN(2, 28), 1778 }; 1779 static const unsigned int hspi1_b_mux[] = { 1780 HSPI_CLK1_B_MARK, HSPI_CS1_B_MARK, HSPI_RX1_B_MARK, HSPI_TX1_B_MARK, 1781 }; 1782 static const unsigned int hspi1_c_pins[] = { 1783 /* CLK, CS, RX, TX */ 1784 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 16), 1785 RCAR_GP_PIN(4, 15), 1786 }; 1787 static const unsigned int hspi1_c_mux[] = { 1788 HSPI_CLK1_C_MARK, HSPI_CS1_C_MARK, HSPI_RX1_C_MARK, HSPI_TX1_C_MARK, 1789 }; 1790 static const unsigned int hspi1_d_pins[] = { 1791 /* CLK, CS, RX, TX */ 1792 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 8), 1793 RCAR_GP_PIN(3, 7), 1794 }; 1795 static const unsigned int hspi1_d_mux[] = { 1796 HSPI_CLK1_D_MARK, HSPI_CS1_D_MARK, HSPI_RX1_D_MARK, HSPI_TX1_D_MARK, 1797 }; 1798 /* - HSPI2 ------------------------------------------------------------------ */ 1799 static const unsigned int hspi2_pins[] = { 1800 /* CLK, CS, RX, TX */ 1801 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), 1802 RCAR_GP_PIN(0, 14), 1803 }; 1804 static const unsigned int hspi2_mux[] = { 1805 HSPI_CLK2_MARK, HSPI_CS2_MARK, HSPI_RX2_MARK, HSPI_TX2_MARK, 1806 }; 1807 static const unsigned int hspi2_b_pins[] = { 1808 /* CLK, CS, RX, TX */ 1809 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 8), 1810 RCAR_GP_PIN(0, 6), 1811 }; 1812 static const unsigned int hspi2_b_mux[] = { 1813 HSPI_CLK2_B_MARK, HSPI_CS2_B_MARK, HSPI_RX2_B_MARK, HSPI_TX2_B_MARK, 1814 }; 1815 /* - I2C1 ------------------------------------------------------------------ */ 1816 static const unsigned int i2c1_pins[] = { 1817 /* SCL, SDA, */ 1818 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28), 1819 }; 1820 static const unsigned int i2c1_mux[] = { 1821 SCL1_MARK, SDA1_MARK, 1822 }; 1823 static const unsigned int i2c1_b_pins[] = { 1824 /* SCL, SDA, */ 1825 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11), 1826 }; 1827 static const unsigned int i2c1_b_mux[] = { 1828 SCL1_B_MARK, SDA1_B_MARK, 1829 }; 1830 static const unsigned int i2c1_c_pins[] = { 1831 /* SCL, SDA, */ 1832 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), 1833 }; 1834 static const unsigned int i2c1_c_mux[] = { 1835 SCL1_C_MARK, SDA1_C_MARK, 1836 }; 1837 static const unsigned int i2c1_d_pins[] = { 1838 /* SCL, SDA, */ 1839 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 27), 1840 }; 1841 static const unsigned int i2c1_d_mux[] = { 1842 SCL1_D_MARK, SDA1_D_MARK, 1843 }; 1844 /* - I2C2 ------------------------------------------------------------------ */ 1845 static const unsigned int i2c2_pins[] = { 1846 /* SCL, SDA, */ 1847 RCAR_GP_PIN(0, 25), RCAR_GP_PIN(0, 26), 1848 }; 1849 static const unsigned int i2c2_mux[] = { 1850 SCL2_MARK, SDA2_MARK, 1851 }; 1852 static const unsigned int i2c2_b_pins[] = { 1853 /* SCL, SDA, */ 1854 RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), 1855 }; 1856 static const unsigned int i2c2_b_mux[] = { 1857 SCL2_B_MARK, SDA2_B_MARK, 1858 }; 1859 static const unsigned int i2c2_c_pins[] = { 1860 /* SCL, SDA */ 1861 RCAR_GP_PIN(0, 31), RCAR_GP_PIN(0, 30), 1862 }; 1863 static const unsigned int i2c2_c_mux[] = { 1864 SCL2_C_MARK, SDA2_C_MARK, 1865 }; 1866 static const unsigned int i2c2_d_pins[] = { 1867 /* SCL, SDA */ 1868 RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 25), 1869 }; 1870 static const unsigned int i2c2_d_mux[] = { 1871 SCL2_D_MARK, SDA2_D_MARK, 1872 }; 1873 /* - I2C3 ------------------------------------------------------------------ */ 1874 static const unsigned int i2c3_pins[] = { 1875 /* SCL, SDA, */ 1876 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(2, 30), 1877 }; 1878 static const unsigned int i2c3_mux[] = { 1879 SCL3_MARK, SDA3_MARK, 1880 }; 1881 static const unsigned int i2c3_b_pins[] = { 1882 /* SCL, SDA, */ 1883 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 30), 1884 }; 1885 static const unsigned int i2c3_b_mux[] = { 1886 SCL3_B_MARK, SDA3_B_MARK, 1887 }; 1888 /* - INTC ------------------------------------------------------------------- */ 1889 static const unsigned int intc_irq0_pins[] = { 1890 /* IRQ */ 1891 RCAR_GP_PIN(2, 14), 1892 }; 1893 static const unsigned int intc_irq0_mux[] = { 1894 IRQ0_MARK, 1895 }; 1896 static const unsigned int intc_irq0_b_pins[] = { 1897 /* IRQ */ 1898 RCAR_GP_PIN(4, 13), 1899 }; 1900 static const unsigned int intc_irq0_b_mux[] = { 1901 IRQ0_B_MARK, 1902 }; 1903 static const unsigned int intc_irq1_pins[] = { 1904 /* IRQ */ 1905 RCAR_GP_PIN(2, 15), 1906 }; 1907 static const unsigned int intc_irq1_mux[] = { 1908 IRQ1_MARK, 1909 }; 1910 static const unsigned int intc_irq1_b_pins[] = { 1911 /* IRQ */ 1912 RCAR_GP_PIN(4, 14), 1913 }; 1914 static const unsigned int intc_irq1_b_mux[] = { 1915 IRQ1_B_MARK, 1916 }; 1917 static const unsigned int intc_irq2_pins[] = { 1918 /* IRQ */ 1919 RCAR_GP_PIN(2, 24), 1920 }; 1921 static const unsigned int intc_irq2_mux[] = { 1922 IRQ2_MARK, 1923 }; 1924 static const unsigned int intc_irq2_b_pins[] = { 1925 /* IRQ */ 1926 RCAR_GP_PIN(4, 15), 1927 }; 1928 static const unsigned int intc_irq2_b_mux[] = { 1929 IRQ2_B_MARK, 1930 }; 1931 static const unsigned int intc_irq3_pins[] = { 1932 /* IRQ */ 1933 RCAR_GP_PIN(2, 25), 1934 }; 1935 static const unsigned int intc_irq3_mux[] = { 1936 IRQ3_MARK, 1937 }; 1938 static const unsigned int intc_irq3_b_pins[] = { 1939 /* IRQ */ 1940 RCAR_GP_PIN(4, 16), 1941 }; 1942 static const unsigned int intc_irq3_b_mux[] = { 1943 IRQ3_B_MARK, 1944 }; 1945 /* - LSBC ------------------------------------------------------------------- */ 1946 static const unsigned int lbsc_cs0_pins[] = { 1947 /* CS */ 1948 RCAR_GP_PIN(0, 13), 1949 }; 1950 static const unsigned int lbsc_cs0_mux[] = { 1951 CS0_MARK, 1952 }; 1953 static const unsigned int lbsc_cs1_pins[] = { 1954 /* CS */ 1955 RCAR_GP_PIN(0, 14), 1956 }; 1957 static const unsigned int lbsc_cs1_mux[] = { 1958 CS1_A26_MARK, 1959 }; 1960 static const unsigned int lbsc_ex_cs0_pins[] = { 1961 /* CS */ 1962 RCAR_GP_PIN(0, 15), 1963 }; 1964 static const unsigned int lbsc_ex_cs0_mux[] = { 1965 EX_CS0_MARK, 1966 }; 1967 static const unsigned int lbsc_ex_cs1_pins[] = { 1968 /* CS */ 1969 RCAR_GP_PIN(0, 16), 1970 }; 1971 static const unsigned int lbsc_ex_cs1_mux[] = { 1972 EX_CS1_MARK, 1973 }; 1974 static const unsigned int lbsc_ex_cs2_pins[] = { 1975 /* CS */ 1976 RCAR_GP_PIN(0, 17), 1977 }; 1978 static const unsigned int lbsc_ex_cs2_mux[] = { 1979 EX_CS2_MARK, 1980 }; 1981 static const unsigned int lbsc_ex_cs3_pins[] = { 1982 /* CS */ 1983 RCAR_GP_PIN(0, 18), 1984 }; 1985 static const unsigned int lbsc_ex_cs3_mux[] = { 1986 EX_CS3_MARK, 1987 }; 1988 static const unsigned int lbsc_ex_cs4_pins[] = { 1989 /* CS */ 1990 RCAR_GP_PIN(0, 19), 1991 }; 1992 static const unsigned int lbsc_ex_cs4_mux[] = { 1993 EX_CS4_MARK, 1994 }; 1995 static const unsigned int lbsc_ex_cs5_pins[] = { 1996 /* CS */ 1997 RCAR_GP_PIN(0, 20), 1998 }; 1999 static const unsigned int lbsc_ex_cs5_mux[] = { 2000 EX_CS5_MARK, 2001 }; 2002 /* - MMCIF ------------------------------------------------------------------ */ 2003 static const unsigned int mmc0_data_pins[] = { 2004 /* D[0:7] */ 2005 RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21), 2006 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), 2007 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16), 2008 }; 2009 static const unsigned int mmc0_data_mux[] = { 2010 MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK, 2011 MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK, 2012 }; 2013 static const unsigned int mmc0_ctrl_pins[] = { 2014 /* CMD, CLK */ 2015 RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 17), 2016 }; 2017 static const unsigned int mmc0_ctrl_mux[] = { 2018 MMC0_CMD_MARK, MMC0_CLK_MARK, 2019 }; 2020 static const unsigned int mmc1_data_pins[] = { 2021 /* D[0:7] */ 2022 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10), 2023 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), 2024 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17), 2025 }; 2026 static const unsigned int mmc1_data_mux[] = { 2027 MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK, 2028 MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK, 2029 }; 2030 static const unsigned int mmc1_ctrl_pins[] = { 2031 /* CMD, CLK */ 2032 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 1), 2033 }; 2034 static const unsigned int mmc1_ctrl_mux[] = { 2035 MMC1_CMD_MARK, MMC1_CLK_MARK, 2036 }; 2037 /* - PWM -------------------------------------------------------------------- */ 2038 static const unsigned int pwm0_pins[] = { 2039 RCAR_GP_PIN(1, 3), 2040 }; 2041 static const unsigned int pwm0_mux[] = { 2042 PWM0_MARK, 2043 }; 2044 static const unsigned int pwm0_b_pins[] = { 2045 RCAR_GP_PIN(0, 12), 2046 }; 2047 static const unsigned int pwm0_b_mux[] = { 2048 PWM0_B_MARK, 2049 }; 2050 static const unsigned int pwm0_c_pins[] = { 2051 RCAR_GP_PIN(4, 5), 2052 }; 2053 static const unsigned int pwm0_c_mux[] = { 2054 PWM0_C_MARK, 2055 }; 2056 static const unsigned int pwm0_d_pins[] = { 2057 RCAR_GP_PIN(4, 18), 2058 }; 2059 static const unsigned int pwm0_d_mux[] = { 2060 PWM0_D_MARK, 2061 }; 2062 static const unsigned int pwm1_pins[] = { 2063 RCAR_GP_PIN(4, 28), 2064 }; 2065 static const unsigned int pwm1_mux[] = { 2066 PWM1_MARK, 2067 }; 2068 static const unsigned int pwm2_pins[] = { 2069 RCAR_GP_PIN(3, 25), 2070 }; 2071 static const unsigned int pwm2_mux[] = { 2072 PWM2_MARK, 2073 }; 2074 static const unsigned int pwm3_pins[] = { 2075 RCAR_GP_PIN(3, 26), 2076 }; 2077 static const unsigned int pwm3_mux[] = { 2078 PWM3_MARK, 2079 }; 2080 static const unsigned int pwm4_pins[] = { 2081 RCAR_GP_PIN(3, 27), 2082 }; 2083 static const unsigned int pwm4_mux[] = { 2084 PWM4_MARK, 2085 }; 2086 static const unsigned int pwm5_pins[] = { 2087 RCAR_GP_PIN(4, 17), 2088 }; 2089 static const unsigned int pwm5_mux[] = { 2090 PWM5_MARK, 2091 }; 2092 static const unsigned int pwm6_pins[] = { 2093 RCAR_GP_PIN(1, 2), 2094 }; 2095 static const unsigned int pwm6_mux[] = { 2096 PWM6_MARK, 2097 }; 2098 /* - SCIF0 ------------------------------------------------------------------ */ 2099 static const unsigned int scif0_data_pins[] = { 2100 /* RXD, TXD */ 2101 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24), 2102 }; 2103 static const unsigned int scif0_data_mux[] = { 2104 RX0_MARK, TX0_MARK, 2105 }; 2106 static const unsigned int scif0_clk_pins[] = { 2107 /* SCK */ 2108 RCAR_GP_PIN(4, 28), 2109 }; 2110 static const unsigned int scif0_clk_mux[] = { 2111 SCK0_MARK, 2112 }; 2113 static const unsigned int scif0_ctrl_pins[] = { 2114 /* RTS, CTS */ 2115 RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 22), 2116 }; 2117 static const unsigned int scif0_ctrl_mux[] = { 2118 RTS0_TANS_MARK, CTS0_MARK, 2119 }; 2120 static const unsigned int scif0_data_b_pins[] = { 2121 /* RXD, TXD */ 2122 RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19), 2123 }; 2124 static const unsigned int scif0_data_b_mux[] = { 2125 RX0_B_MARK, TX0_B_MARK, 2126 }; 2127 static const unsigned int scif0_clk_b_pins[] = { 2128 /* SCK */ 2129 RCAR_GP_PIN(1, 1), 2130 }; 2131 static const unsigned int scif0_clk_b_mux[] = { 2132 SCK0_B_MARK, 2133 }; 2134 static const unsigned int scif0_ctrl_b_pins[] = { 2135 /* RTS, CTS */ 2136 RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 11), 2137 }; 2138 static const unsigned int scif0_ctrl_b_mux[] = { 2139 RTS0_B_TANS_B_MARK, CTS0_B_MARK, 2140 }; 2141 static const unsigned int scif0_data_c_pins[] = { 2142 /* RXD, TXD */ 2143 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 19), 2144 }; 2145 static const unsigned int scif0_data_c_mux[] = { 2146 RX0_C_MARK, TX0_C_MARK, 2147 }; 2148 static const unsigned int scif0_clk_c_pins[] = { 2149 /* SCK */ 2150 RCAR_GP_PIN(4, 17), 2151 }; 2152 static const unsigned int scif0_clk_c_mux[] = { 2153 SCK0_C_MARK, 2154 }; 2155 static const unsigned int scif0_ctrl_c_pins[] = { 2156 /* RTS, CTS */ 2157 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), 2158 }; 2159 static const unsigned int scif0_ctrl_c_mux[] = { 2160 RTS0_C_TANS_C_MARK, CTS0_C_MARK, 2161 }; 2162 static const unsigned int scif0_data_d_pins[] = { 2163 /* RXD, TXD */ 2164 RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10), 2165 }; 2166 static const unsigned int scif0_data_d_mux[] = { 2167 RX0_D_MARK, TX0_D_MARK, 2168 }; 2169 static const unsigned int scif0_clk_d_pins[] = { 2170 /* SCK */ 2171 RCAR_GP_PIN(1, 18), 2172 }; 2173 static const unsigned int scif0_clk_d_mux[] = { 2174 SCK0_D_MARK, 2175 }; 2176 static const unsigned int scif0_ctrl_d_pins[] = { 2177 /* RTS, CTS */ 2178 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 3), 2179 }; 2180 static const unsigned int scif0_ctrl_d_mux[] = { 2181 RTS0_D_TANS_D_MARK, CTS0_D_MARK, 2182 }; 2183 /* - SCIF1 ------------------------------------------------------------------ */ 2184 static const unsigned int scif1_data_pins[] = { 2185 /* RXD, TXD */ 2186 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), 2187 }; 2188 static const unsigned int scif1_data_mux[] = { 2189 RX1_MARK, TX1_MARK, 2190 }; 2191 static const unsigned int scif1_clk_pins[] = { 2192 /* SCK */ 2193 RCAR_GP_PIN(4, 17), 2194 }; 2195 static const unsigned int scif1_clk_mux[] = { 2196 SCK1_MARK, 2197 }; 2198 static const unsigned int scif1_ctrl_pins[] = { 2199 /* RTS, CTS */ 2200 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18), 2201 }; 2202 static const unsigned int scif1_ctrl_mux[] = { 2203 RTS1_TANS_MARK, CTS1_MARK, 2204 }; 2205 static const unsigned int scif1_data_b_pins[] = { 2206 /* RXD, TXD */ 2207 RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 18), 2208 }; 2209 static const unsigned int scif1_data_b_mux[] = { 2210 RX1_B_MARK, TX1_B_MARK, 2211 }; 2212 static const unsigned int scif1_clk_b_pins[] = { 2213 /* SCK */ 2214 RCAR_GP_PIN(3, 17), 2215 }; 2216 static const unsigned int scif1_clk_b_mux[] = { 2217 SCK1_B_MARK, 2218 }; 2219 static const unsigned int scif1_ctrl_b_pins[] = { 2220 /* RTS, CTS */ 2221 RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), 2222 }; 2223 static const unsigned int scif1_ctrl_b_mux[] = { 2224 RTS1_B_TANS_B_MARK, CTS1_B_MARK, 2225 }; 2226 static const unsigned int scif1_data_c_pins[] = { 2227 /* RXD, TXD */ 2228 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2), 2229 }; 2230 static const unsigned int scif1_data_c_mux[] = { 2231 RX1_C_MARK, TX1_C_MARK, 2232 }; 2233 static const unsigned int scif1_clk_c_pins[] = { 2234 /* SCK */ 2235 RCAR_GP_PIN(2, 22), 2236 }; 2237 static const unsigned int scif1_clk_c_mux[] = { 2238 SCK1_C_MARK, 2239 }; 2240 static const unsigned int scif1_ctrl_c_pins[] = { 2241 /* RTS, CTS */ 2242 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4), 2243 }; 2244 static const unsigned int scif1_ctrl_c_mux[] = { 2245 RTS1_C_TANS_C_MARK, CTS1_C_MARK, 2246 }; 2247 /* - SCIF2 ------------------------------------------------------------------ */ 2248 static const unsigned int scif2_data_pins[] = { 2249 /* RXD, TXD */ 2250 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 9), 2251 }; 2252 static const unsigned int scif2_data_mux[] = { 2253 RX2_MARK, TX2_MARK, 2254 }; 2255 static const unsigned int scif2_clk_pins[] = { 2256 /* SCK */ 2257 RCAR_GP_PIN(3, 11), 2258 }; 2259 static const unsigned int scif2_clk_mux[] = { 2260 SCK2_MARK, 2261 }; 2262 static const unsigned int scif2_data_b_pins[] = { 2263 /* RXD, TXD */ 2264 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 23), 2265 }; 2266 static const unsigned int scif2_data_b_mux[] = { 2267 RX2_B_MARK, TX2_B_MARK, 2268 }; 2269 static const unsigned int scif2_clk_b_pins[] = { 2270 /* SCK */ 2271 RCAR_GP_PIN(3, 22), 2272 }; 2273 static const unsigned int scif2_clk_b_mux[] = { 2274 SCK2_B_MARK, 2275 }; 2276 static const unsigned int scif2_data_c_pins[] = { 2277 /* RXD, TXD */ 2278 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(0, 31), 2279 }; 2280 static const unsigned int scif2_data_c_mux[] = { 2281 RX2_C_MARK, TX2_C_MARK, 2282 }; 2283 static const unsigned int scif2_clk_c_pins[] = { 2284 /* SCK */ 2285 RCAR_GP_PIN(1, 0), 2286 }; 2287 static const unsigned int scif2_clk_c_mux[] = { 2288 SCK2_C_MARK, 2289 }; 2290 static const unsigned int scif2_data_d_pins[] = { 2291 /* RXD, TXD */ 2292 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(1, 30), 2293 }; 2294 static const unsigned int scif2_data_d_mux[] = { 2295 RX2_D_MARK, TX2_D_MARK, 2296 }; 2297 static const unsigned int scif2_clk_d_pins[] = { 2298 /* SCK */ 2299 RCAR_GP_PIN(1, 31), 2300 }; 2301 static const unsigned int scif2_clk_d_mux[] = { 2302 SCK2_D_MARK, 2303 }; 2304 static const unsigned int scif2_data_e_pins[] = { 2305 /* RXD, TXD */ 2306 RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19), 2307 }; 2308 static const unsigned int scif2_data_e_mux[] = { 2309 RX2_E_MARK, TX2_E_MARK, 2310 }; 2311 /* - SCIF3 ------------------------------------------------------------------ */ 2312 static const unsigned int scif3_data_pins[] = { 2313 /* RXD, TXD */ 2314 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 8), 2315 }; 2316 static const unsigned int scif3_data_mux[] = { 2317 RX3_IRDA_RX_MARK, TX3_IRDA_TX_MARK, 2318 }; 2319 static const unsigned int scif3_clk_pins[] = { 2320 /* SCK */ 2321 RCAR_GP_PIN(4, 7), 2322 }; 2323 static const unsigned int scif3_clk_mux[] = { 2324 SCK3_MARK, 2325 }; 2326 2327 static const unsigned int scif3_data_b_pins[] = { 2328 /* RXD, TXD */ 2329 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(1, 30), 2330 }; 2331 static const unsigned int scif3_data_b_mux[] = { 2332 RX3_B_IRDA_RX_B_MARK, TX3_B_IRDA_TX_B_MARK, 2333 }; 2334 static const unsigned int scif3_data_c_pins[] = { 2335 /* RXD, TXD */ 2336 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 12), 2337 }; 2338 static const unsigned int scif3_data_c_mux[] = { 2339 RX3_C_IRDA_RX_C_MARK, TX3C_IRDA_TX_C_MARK, 2340 }; 2341 static const unsigned int scif3_data_d_pins[] = { 2342 /* RXD, TXD */ 2343 RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 29), 2344 }; 2345 static const unsigned int scif3_data_d_mux[] = { 2346 RX3_D_IRDA_RX_D_MARK, TX3_D_IRDA_TX_D_MARK, 2347 }; 2348 static const unsigned int scif3_data_e_pins[] = { 2349 /* RXD, TXD */ 2350 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), 2351 }; 2352 static const unsigned int scif3_data_e_mux[] = { 2353 RX3_E_IRDA_RX_E_MARK, TX3_E_IRDA_TX_E_MARK, 2354 }; 2355 static const unsigned int scif3_clk_e_pins[] = { 2356 /* SCK */ 2357 RCAR_GP_PIN(1, 10), 2358 }; 2359 static const unsigned int scif3_clk_e_mux[] = { 2360 SCK3_E_MARK, 2361 }; 2362 /* - SCIF4 ------------------------------------------------------------------ */ 2363 static const unsigned int scif4_data_pins[] = { 2364 /* RXD, TXD */ 2365 RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 26), 2366 }; 2367 static const unsigned int scif4_data_mux[] = { 2368 RX4_MARK, TX4_MARK, 2369 }; 2370 static const unsigned int scif4_clk_pins[] = { 2371 /* SCK */ 2372 RCAR_GP_PIN(3, 25), 2373 }; 2374 static const unsigned int scif4_clk_mux[] = { 2375 SCK4_MARK, 2376 }; 2377 static const unsigned int scif4_data_b_pins[] = { 2378 /* RXD, TXD */ 2379 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), 2380 }; 2381 static const unsigned int scif4_data_b_mux[] = { 2382 RX4_B_MARK, TX4_B_MARK, 2383 }; 2384 static const unsigned int scif4_clk_b_pins[] = { 2385 /* SCK */ 2386 RCAR_GP_PIN(3, 16), 2387 }; 2388 static const unsigned int scif4_clk_b_mux[] = { 2389 SCK4_B_MARK, 2390 }; 2391 static const unsigned int scif4_data_c_pins[] = { 2392 /* RXD, TXD */ 2393 RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 21), 2394 }; 2395 static const unsigned int scif4_data_c_mux[] = { 2396 RX4_C_MARK, TX4_C_MARK, 2397 }; 2398 static const unsigned int scif4_data_d_pins[] = { 2399 /* RXD, TXD */ 2400 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4), 2401 }; 2402 static const unsigned int scif4_data_d_mux[] = { 2403 RX4_D_MARK, TX4_D_MARK, 2404 }; 2405 /* - SCIF5 ------------------------------------------------------------------ */ 2406 static const unsigned int scif5_data_pins[] = { 2407 /* RXD, TXD */ 2408 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), 2409 }; 2410 static const unsigned int scif5_data_mux[] = { 2411 RX5_MARK, TX5_MARK, 2412 }; 2413 static const unsigned int scif5_clk_pins[] = { 2414 /* SCK */ 2415 RCAR_GP_PIN(1, 11), 2416 }; 2417 static const unsigned int scif5_clk_mux[] = { 2418 SCK5_MARK, 2419 }; 2420 static const unsigned int scif5_data_b_pins[] = { 2421 /* RXD, TXD */ 2422 RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 11), 2423 }; 2424 static const unsigned int scif5_data_b_mux[] = { 2425 RX5_B_MARK, TX5_B_MARK, 2426 }; 2427 static const unsigned int scif5_clk_b_pins[] = { 2428 /* SCK */ 2429 RCAR_GP_PIN(0, 19), 2430 }; 2431 static const unsigned int scif5_clk_b_mux[] = { 2432 SCK5_B_MARK, 2433 }; 2434 static const unsigned int scif5_data_c_pins[] = { 2435 /* RXD, TXD */ 2436 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 23), 2437 }; 2438 static const unsigned int scif5_data_c_mux[] = { 2439 RX5_C_MARK, TX5_C_MARK, 2440 }; 2441 static const unsigned int scif5_clk_c_pins[] = { 2442 /* SCK */ 2443 RCAR_GP_PIN(0, 28), 2444 }; 2445 static const unsigned int scif5_clk_c_mux[] = { 2446 SCK5_C_MARK, 2447 }; 2448 static const unsigned int scif5_data_d_pins[] = { 2449 /* RXD, TXD */ 2450 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 6), 2451 }; 2452 static const unsigned int scif5_data_d_mux[] = { 2453 RX5_D_MARK, TX5_D_MARK, 2454 }; 2455 static const unsigned int scif5_clk_d_pins[] = { 2456 /* SCK */ 2457 RCAR_GP_PIN(0, 7), 2458 }; 2459 static const unsigned int scif5_clk_d_mux[] = { 2460 SCK5_D_MARK, 2461 }; 2462 /* - SCIF Clock ------------------------------------------------------------- */ 2463 static const unsigned int scif_clk_pins[] = { 2464 /* SCIF_CLK */ 2465 RCAR_GP_PIN(4, 28), 2466 }; 2467 static const unsigned int scif_clk_mux[] = { 2468 SCIF_CLK_MARK, 2469 }; 2470 static const unsigned int scif_clk_b_pins[] = { 2471 /* SCIF_CLK */ 2472 RCAR_GP_PIN(4, 5), 2473 }; 2474 static const unsigned int scif_clk_b_mux[] = { 2475 SCIF_CLK_B_MARK, 2476 }; 2477 static const unsigned int scif_clk_c_pins[] = { 2478 /* SCIF_CLK */ 2479 RCAR_GP_PIN(4, 18), 2480 }; 2481 static const unsigned int scif_clk_c_mux[] = { 2482 SCIF_CLK_C_MARK, 2483 }; 2484 static const unsigned int scif_clk_d_pins[] = { 2485 /* SCIF_CLK */ 2486 RCAR_GP_PIN(2, 29), 2487 }; 2488 static const unsigned int scif_clk_d_mux[] = { 2489 SCIF_CLK_D_MARK, 2490 }; 2491 /* - SDHI0 ------------------------------------------------------------------ */ 2492 static const unsigned int sdhi0_data_pins[] = { 2493 /* D[0:3] */ 2494 RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23), 2495 RCAR_GP_PIN(3, 24), 2496 }; 2497 static const unsigned int sdhi0_data_mux[] = { 2498 SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK, 2499 }; 2500 static const unsigned int sdhi0_ctrl_pins[] = { 2501 /* CMD, CLK */ 2502 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 17), 2503 }; 2504 static const unsigned int sdhi0_ctrl_mux[] = { 2505 SD0_CMD_MARK, SD0_CLK_MARK, 2506 }; 2507 static const unsigned int sdhi0_cd_pins[] = { 2508 /* CD */ 2509 RCAR_GP_PIN(3, 19), 2510 }; 2511 static const unsigned int sdhi0_cd_mux[] = { 2512 SD0_CD_MARK, 2513 }; 2514 static const unsigned int sdhi0_wp_pins[] = { 2515 /* WP */ 2516 RCAR_GP_PIN(3, 20), 2517 }; 2518 static const unsigned int sdhi0_wp_mux[] = { 2519 SD0_WP_MARK, 2520 }; 2521 /* - SDHI1 ------------------------------------------------------------------ */ 2522 static const unsigned int sdhi1_data_pins[] = { 2523 /* D[0:3] */ 2524 RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21), 2525 RCAR_GP_PIN(0, 2), 2526 }; 2527 static const unsigned int sdhi1_data_mux[] = { 2528 SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK, 2529 }; 2530 static const unsigned int sdhi1_ctrl_pins[] = { 2531 /* CMD, CLK */ 2532 RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 17), 2533 }; 2534 static const unsigned int sdhi1_ctrl_mux[] = { 2535 SD1_CMD_MARK, SD1_CLK_MARK, 2536 }; 2537 static const unsigned int sdhi1_cd_pins[] = { 2538 /* CD */ 2539 RCAR_GP_PIN(0, 10), 2540 }; 2541 static const unsigned int sdhi1_cd_mux[] = { 2542 SD1_CD_MARK, 2543 }; 2544 static const unsigned int sdhi1_wp_pins[] = { 2545 /* WP */ 2546 RCAR_GP_PIN(0, 11), 2547 }; 2548 static const unsigned int sdhi1_wp_mux[] = { 2549 SD1_WP_MARK, 2550 }; 2551 /* - SDHI2 ------------------------------------------------------------------ */ 2552 static const unsigned int sdhi2_data_pins[] = { 2553 /* D[0:3] */ 2554 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), 2555 RCAR_GP_PIN(3, 4), 2556 }; 2557 static const unsigned int sdhi2_data_mux[] = { 2558 SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK, 2559 }; 2560 static const unsigned int sdhi2_ctrl_pins[] = { 2561 /* CMD, CLK */ 2562 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 5), 2563 }; 2564 static const unsigned int sdhi2_ctrl_mux[] = { 2565 SD2_CMD_MARK, SD2_CLK_MARK, 2566 }; 2567 static const unsigned int sdhi2_cd_pins[] = { 2568 /* CD */ 2569 RCAR_GP_PIN(3, 7), 2570 }; 2571 static const unsigned int sdhi2_cd_mux[] = { 2572 SD2_CD_MARK, 2573 }; 2574 static const unsigned int sdhi2_wp_pins[] = { 2575 /* WP */ 2576 RCAR_GP_PIN(3, 8), 2577 }; 2578 static const unsigned int sdhi2_wp_mux[] = { 2579 SD2_WP_MARK, 2580 }; 2581 /* - SDHI3 ------------------------------------------------------------------ */ 2582 static const unsigned int sdhi3_data_pins[] = { 2583 /* D[0:3] */ 2584 RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 20), 2585 RCAR_GP_PIN(1, 21), 2586 }; 2587 static const unsigned int sdhi3_data_mux[] = { 2588 SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK, 2589 }; 2590 static const unsigned int sdhi3_ctrl_pins[] = { 2591 /* CMD, CLK */ 2592 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), 2593 }; 2594 static const unsigned int sdhi3_ctrl_mux[] = { 2595 SD3_CMD_MARK, SD3_CLK_MARK, 2596 }; 2597 static const unsigned int sdhi3_cd_pins[] = { 2598 /* CD */ 2599 RCAR_GP_PIN(1, 30), 2600 }; 2601 static const unsigned int sdhi3_cd_mux[] = { 2602 SD3_CD_MARK, 2603 }; 2604 static const unsigned int sdhi3_wp_pins[] = { 2605 /* WP */ 2606 RCAR_GP_PIN(2, 0), 2607 }; 2608 static const unsigned int sdhi3_wp_mux[] = { 2609 SD3_WP_MARK, 2610 }; 2611 /* - USB0 ------------------------------------------------------------------- */ 2612 static const unsigned int usb0_pins[] = { 2613 /* PENC */ 2614 RCAR_GP_PIN(4, 26), 2615 }; 2616 static const unsigned int usb0_mux[] = { 2617 USB_PENC0_MARK, 2618 }; 2619 static const unsigned int usb0_ovc_pins[] = { 2620 /* USB_OVC */ 2621 RCAR_GP_PIN(4, 22), 2622 }; 2623 static const unsigned int usb0_ovc_mux[] = { 2624 USB_OVC0_MARK, 2625 }; 2626 /* - USB1 ------------------------------------------------------------------- */ 2627 static const unsigned int usb1_pins[] = { 2628 /* PENC */ 2629 RCAR_GP_PIN(4, 27), 2630 }; 2631 static const unsigned int usb1_mux[] = { 2632 USB_PENC1_MARK, 2633 }; 2634 static const unsigned int usb1_ovc_pins[] = { 2635 /* USB_OVC */ 2636 RCAR_GP_PIN(4, 24), 2637 }; 2638 static const unsigned int usb1_ovc_mux[] = { 2639 USB_OVC1_MARK, 2640 }; 2641 /* - USB2 ------------------------------------------------------------------- */ 2642 static const unsigned int usb2_pins[] = { 2643 /* PENC */ 2644 RCAR_GP_PIN(4, 28), 2645 }; 2646 static const unsigned int usb2_mux[] = { 2647 USB_PENC2_MARK, 2648 }; 2649 static const unsigned int usb2_ovc_pins[] = { 2650 /* USB_OVC */ 2651 RCAR_GP_PIN(3, 29), 2652 }; 2653 static const unsigned int usb2_ovc_mux[] = { 2654 USB_OVC2_MARK, 2655 }; 2656 /* - VIN0 ------------------------------------------------------------------- */ 2657 static const unsigned int vin0_data8_pins[] = { 2658 /* D[0:7] */ 2659 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), 2660 RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), 2661 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), 2662 }; 2663 static const unsigned int vin0_data8_mux[] = { 2664 VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, VI0_DATA2_VI0_B2_MARK, 2665 VI0_DATA3_VI0_B3_MARK, VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, 2666 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, 2667 }; 2668 static const unsigned int vin0_clk_pins[] = { 2669 /* CLK */ 2670 RCAR_GP_PIN(2, 1), 2671 }; 2672 static const unsigned int vin0_clk_mux[] = { 2673 VI0_CLK_MARK, 2674 }; 2675 static const unsigned int vin0_sync_pins[] = { 2676 /* HSYNC, VSYNC */ 2677 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), 2678 }; 2679 static const unsigned int vin0_sync_mux[] = { 2680 VI0_HSYNC_MARK, VI0_VSYNC_MARK, 2681 }; 2682 /* - VIN1 ------------------------------------------------------------------- */ 2683 static const unsigned int vin1_data8_pins[] = { 2684 /* D[0:7] */ 2685 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), 2686 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), 2687 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8), 2688 }; 2689 static const unsigned int vin1_data8_mux[] = { 2690 VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK, VI1_DATA2_VI1_B2_MARK, 2691 VI1_DATA3_VI1_B3_MARK, VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK, 2692 VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK, 2693 }; 2694 static const unsigned int vin1_clk_pins[] = { 2695 /* CLK */ 2696 RCAR_GP_PIN(2, 30), 2697 }; 2698 static const unsigned int vin1_clk_mux[] = { 2699 VI1_CLK_MARK, 2700 }; 2701 static const unsigned int vin1_sync_pins[] = { 2702 /* HSYNC, VSYNC */ 2703 RCAR_GP_PIN(2, 31), RCAR_GP_PIN(3, 0), 2704 }; 2705 static const unsigned int vin1_sync_mux[] = { 2706 VI1_HSYNC_MARK, VI1_VSYNC_MARK, 2707 }; 2708 /* - VIN2 ------------------------------------------------------------------- */ 2709 static const unsigned int vin2_data8_pins[] = { 2710 /* D[0:7] */ 2711 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10), 2712 RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), 2713 RCAR_GP_PIN(1, 31), RCAR_GP_PIN(2, 0), 2714 }; 2715 static const unsigned int vin2_data8_mux[] = { 2716 VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK, VI2_DATA2_VI2_B2_MARK, 2717 VI2_DATA3_VI2_B3_MARK, VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK, 2718 VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK, 2719 }; 2720 static const unsigned int vin2_clk_pins[] = { 2721 /* CLK */ 2722 RCAR_GP_PIN(1, 30), 2723 }; 2724 static const unsigned int vin2_clk_mux[] = { 2725 VI2_CLK_MARK, 2726 }; 2727 static const unsigned int vin2_sync_pins[] = { 2728 /* HSYNC, VSYNC */ 2729 RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 29), 2730 }; 2731 static const unsigned int vin2_sync_mux[] = { 2732 VI2_HSYNC_MARK, VI2_VSYNC_MARK, 2733 }; 2734 /* - VIN3 ------------------------------------------------------------------- */ 2735 static const unsigned int vin3_data8_pins[] = { 2736 /* D[0:7] */ 2737 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 2738 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14), 2739 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16), 2740 }; 2741 static const unsigned int vin3_data8_mux[] = { 2742 VI3_DATA0_MARK, VI3_DATA1_MARK, VI3_DATA2_MARK, 2743 VI3_DATA3_MARK, VI3_DATA4_MARK, VI3_DATA5_MARK, 2744 VI3_DATA6_MARK, VI3_DATA7_MARK, 2745 }; 2746 static const unsigned int vin3_clk_pins[] = { 2747 /* CLK */ 2748 RCAR_GP_PIN(2, 31), 2749 }; 2750 static const unsigned int vin3_clk_mux[] = { 2751 VI3_CLK_MARK, 2752 }; 2753 static const unsigned int vin3_sync_pins[] = { 2754 /* HSYNC, VSYNC */ 2755 RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 29), 2756 }; 2757 static const unsigned int vin3_sync_mux[] = { 2758 VI3_HSYNC_MARK, VI3_VSYNC_MARK, 2759 }; 2760 2761 static const struct sh_pfc_pin_group pinmux_groups[] = { 2762 SH_PFC_PIN_GROUP(du0_rgb666), 2763 SH_PFC_PIN_GROUP(du0_rgb888), 2764 SH_PFC_PIN_GROUP(du0_clk_in), 2765 SH_PFC_PIN_GROUP(du0_clk_out_0), 2766 SH_PFC_PIN_GROUP(du0_clk_out_1), 2767 SH_PFC_PIN_GROUP(du0_sync_0), 2768 SH_PFC_PIN_GROUP(du0_sync_1), 2769 SH_PFC_PIN_GROUP(du0_oddf), 2770 SH_PFC_PIN_GROUP(du0_cde), 2771 SH_PFC_PIN_GROUP(du1_rgb666), 2772 SH_PFC_PIN_GROUP(du1_rgb888), 2773 SH_PFC_PIN_GROUP(du1_clk_in), 2774 SH_PFC_PIN_GROUP(du1_clk_out), 2775 SH_PFC_PIN_GROUP(du1_sync_0), 2776 SH_PFC_PIN_GROUP(du1_sync_1), 2777 SH_PFC_PIN_GROUP(du1_oddf), 2778 SH_PFC_PIN_GROUP(du1_cde), 2779 SH_PFC_PIN_GROUP(ether_rmii), 2780 SH_PFC_PIN_GROUP(ether_link), 2781 SH_PFC_PIN_GROUP(ether_magic), 2782 SH_PFC_PIN_GROUP(hscif0_data), 2783 SH_PFC_PIN_GROUP(hscif0_data_b), 2784 SH_PFC_PIN_GROUP(hscif0_ctrl), 2785 SH_PFC_PIN_GROUP(hscif0_ctrl_b), 2786 SH_PFC_PIN_GROUP(hscif0_clk), 2787 SH_PFC_PIN_GROUP(hscif0_clk_b), 2788 SH_PFC_PIN_GROUP(hscif1_data), 2789 SH_PFC_PIN_GROUP(hscif1_data_b), 2790 SH_PFC_PIN_GROUP(hscif1_ctrl), 2791 SH_PFC_PIN_GROUP(hscif1_ctrl_b), 2792 SH_PFC_PIN_GROUP(hscif1_clk), 2793 SH_PFC_PIN_GROUP(hscif1_clk_b), 2794 SH_PFC_PIN_GROUP(hspi0), 2795 SH_PFC_PIN_GROUP(hspi1), 2796 SH_PFC_PIN_GROUP(hspi1_b), 2797 SH_PFC_PIN_GROUP(hspi1_c), 2798 SH_PFC_PIN_GROUP(hspi1_d), 2799 SH_PFC_PIN_GROUP(hspi2), 2800 SH_PFC_PIN_GROUP(hspi2_b), 2801 SH_PFC_PIN_GROUP(i2c1), 2802 SH_PFC_PIN_GROUP(i2c1_b), 2803 SH_PFC_PIN_GROUP(i2c1_c), 2804 SH_PFC_PIN_GROUP(i2c1_d), 2805 SH_PFC_PIN_GROUP(i2c2), 2806 SH_PFC_PIN_GROUP(i2c2_b), 2807 SH_PFC_PIN_GROUP(i2c2_c), 2808 SH_PFC_PIN_GROUP(i2c2_d), 2809 SH_PFC_PIN_GROUP(i2c3), 2810 SH_PFC_PIN_GROUP(i2c3_b), 2811 SH_PFC_PIN_GROUP(intc_irq0), 2812 SH_PFC_PIN_GROUP(intc_irq0_b), 2813 SH_PFC_PIN_GROUP(intc_irq1), 2814 SH_PFC_PIN_GROUP(intc_irq1_b), 2815 SH_PFC_PIN_GROUP(intc_irq2), 2816 SH_PFC_PIN_GROUP(intc_irq2_b), 2817 SH_PFC_PIN_GROUP(intc_irq3), 2818 SH_PFC_PIN_GROUP(intc_irq3_b), 2819 SH_PFC_PIN_GROUP(lbsc_cs0), 2820 SH_PFC_PIN_GROUP(lbsc_cs1), 2821 SH_PFC_PIN_GROUP(lbsc_ex_cs0), 2822 SH_PFC_PIN_GROUP(lbsc_ex_cs1), 2823 SH_PFC_PIN_GROUP(lbsc_ex_cs2), 2824 SH_PFC_PIN_GROUP(lbsc_ex_cs3), 2825 SH_PFC_PIN_GROUP(lbsc_ex_cs4), 2826 SH_PFC_PIN_GROUP(lbsc_ex_cs5), 2827 BUS_DATA_PIN_GROUP(mmc0_data, 1), 2828 BUS_DATA_PIN_GROUP(mmc0_data, 4), 2829 BUS_DATA_PIN_GROUP(mmc0_data, 8), 2830 SH_PFC_PIN_GROUP(mmc0_ctrl), 2831 BUS_DATA_PIN_GROUP(mmc1_data, 1), 2832 BUS_DATA_PIN_GROUP(mmc1_data, 4), 2833 BUS_DATA_PIN_GROUP(mmc1_data, 8), 2834 SH_PFC_PIN_GROUP(mmc1_ctrl), 2835 SH_PFC_PIN_GROUP(pwm0), 2836 SH_PFC_PIN_GROUP(pwm0_b), 2837 SH_PFC_PIN_GROUP(pwm0_c), 2838 SH_PFC_PIN_GROUP(pwm0_d), 2839 SH_PFC_PIN_GROUP(pwm1), 2840 SH_PFC_PIN_GROUP(pwm2), 2841 SH_PFC_PIN_GROUP(pwm3), 2842 SH_PFC_PIN_GROUP(pwm4), 2843 SH_PFC_PIN_GROUP(pwm5), 2844 SH_PFC_PIN_GROUP(pwm6), 2845 SH_PFC_PIN_GROUP(scif0_data), 2846 SH_PFC_PIN_GROUP(scif0_clk), 2847 SH_PFC_PIN_GROUP(scif0_ctrl), 2848 SH_PFC_PIN_GROUP(scif0_data_b), 2849 SH_PFC_PIN_GROUP(scif0_clk_b), 2850 SH_PFC_PIN_GROUP(scif0_ctrl_b), 2851 SH_PFC_PIN_GROUP(scif0_data_c), 2852 SH_PFC_PIN_GROUP(scif0_clk_c), 2853 SH_PFC_PIN_GROUP(scif0_ctrl_c), 2854 SH_PFC_PIN_GROUP(scif0_data_d), 2855 SH_PFC_PIN_GROUP(scif0_clk_d), 2856 SH_PFC_PIN_GROUP(scif0_ctrl_d), 2857 SH_PFC_PIN_GROUP(scif1_data), 2858 SH_PFC_PIN_GROUP(scif1_clk), 2859 SH_PFC_PIN_GROUP(scif1_ctrl), 2860 SH_PFC_PIN_GROUP(scif1_data_b), 2861 SH_PFC_PIN_GROUP(scif1_clk_b), 2862 SH_PFC_PIN_GROUP(scif1_ctrl_b), 2863 SH_PFC_PIN_GROUP(scif1_data_c), 2864 SH_PFC_PIN_GROUP(scif1_clk_c), 2865 SH_PFC_PIN_GROUP(scif1_ctrl_c), 2866 SH_PFC_PIN_GROUP(scif2_data), 2867 SH_PFC_PIN_GROUP(scif2_clk), 2868 SH_PFC_PIN_GROUP(scif2_data_b), 2869 SH_PFC_PIN_GROUP(scif2_clk_b), 2870 SH_PFC_PIN_GROUP(scif2_data_c), 2871 SH_PFC_PIN_GROUP(scif2_clk_c), 2872 SH_PFC_PIN_GROUP(scif2_data_d), 2873 SH_PFC_PIN_GROUP(scif2_clk_d), 2874 SH_PFC_PIN_GROUP(scif2_data_e), 2875 SH_PFC_PIN_GROUP(scif3_data), 2876 SH_PFC_PIN_GROUP(scif3_clk), 2877 SH_PFC_PIN_GROUP(scif3_data_b), 2878 SH_PFC_PIN_GROUP(scif3_data_c), 2879 SH_PFC_PIN_GROUP(scif3_data_d), 2880 SH_PFC_PIN_GROUP(scif3_data_e), 2881 SH_PFC_PIN_GROUP(scif3_clk_e), 2882 SH_PFC_PIN_GROUP(scif4_data), 2883 SH_PFC_PIN_GROUP(scif4_clk), 2884 SH_PFC_PIN_GROUP(scif4_data_b), 2885 SH_PFC_PIN_GROUP(scif4_clk_b), 2886 SH_PFC_PIN_GROUP(scif4_data_c), 2887 SH_PFC_PIN_GROUP(scif4_data_d), 2888 SH_PFC_PIN_GROUP(scif5_data), 2889 SH_PFC_PIN_GROUP(scif5_clk), 2890 SH_PFC_PIN_GROUP(scif5_data_b), 2891 SH_PFC_PIN_GROUP(scif5_clk_b), 2892 SH_PFC_PIN_GROUP(scif5_data_c), 2893 SH_PFC_PIN_GROUP(scif5_clk_c), 2894 SH_PFC_PIN_GROUP(scif5_data_d), 2895 SH_PFC_PIN_GROUP(scif5_clk_d), 2896 SH_PFC_PIN_GROUP(scif_clk), 2897 SH_PFC_PIN_GROUP(scif_clk_b), 2898 SH_PFC_PIN_GROUP(scif_clk_c), 2899 SH_PFC_PIN_GROUP(scif_clk_d), 2900 BUS_DATA_PIN_GROUP(sdhi0_data, 1), 2901 BUS_DATA_PIN_GROUP(sdhi0_data, 4), 2902 SH_PFC_PIN_GROUP(sdhi0_ctrl), 2903 SH_PFC_PIN_GROUP(sdhi0_cd), 2904 SH_PFC_PIN_GROUP(sdhi0_wp), 2905 BUS_DATA_PIN_GROUP(sdhi1_data, 1), 2906 BUS_DATA_PIN_GROUP(sdhi1_data, 4), 2907 SH_PFC_PIN_GROUP(sdhi1_ctrl), 2908 SH_PFC_PIN_GROUP(sdhi1_cd), 2909 SH_PFC_PIN_GROUP(sdhi1_wp), 2910 BUS_DATA_PIN_GROUP(sdhi2_data, 1), 2911 BUS_DATA_PIN_GROUP(sdhi2_data, 4), 2912 SH_PFC_PIN_GROUP(sdhi2_ctrl), 2913 SH_PFC_PIN_GROUP(sdhi2_cd), 2914 SH_PFC_PIN_GROUP(sdhi2_wp), 2915 BUS_DATA_PIN_GROUP(sdhi3_data, 1), 2916 BUS_DATA_PIN_GROUP(sdhi3_data, 4), 2917 SH_PFC_PIN_GROUP(sdhi3_ctrl), 2918 SH_PFC_PIN_GROUP(sdhi3_cd), 2919 SH_PFC_PIN_GROUP(sdhi3_wp), 2920 SH_PFC_PIN_GROUP(usb0), 2921 SH_PFC_PIN_GROUP(usb0_ovc), 2922 SH_PFC_PIN_GROUP(usb1), 2923 SH_PFC_PIN_GROUP(usb1_ovc), 2924 SH_PFC_PIN_GROUP(usb2), 2925 SH_PFC_PIN_GROUP(usb2_ovc), 2926 SH_PFC_PIN_GROUP(vin0_data8), 2927 SH_PFC_PIN_GROUP(vin0_clk), 2928 SH_PFC_PIN_GROUP(vin0_sync), 2929 SH_PFC_PIN_GROUP(vin1_data8), 2930 SH_PFC_PIN_GROUP(vin1_clk), 2931 SH_PFC_PIN_GROUP(vin1_sync), 2932 SH_PFC_PIN_GROUP(vin2_data8), 2933 SH_PFC_PIN_GROUP(vin2_clk), 2934 SH_PFC_PIN_GROUP(vin2_sync), 2935 SH_PFC_PIN_GROUP(vin3_data8), 2936 SH_PFC_PIN_GROUP(vin3_clk), 2937 SH_PFC_PIN_GROUP(vin3_sync), 2938 }; 2939 2940 static const char * const du0_groups[] = { 2941 "du0_rgb666", 2942 "du0_rgb888", 2943 "du0_clk_in", 2944 "du0_clk_out_0", 2945 "du0_clk_out_1", 2946 "du0_sync_0", 2947 "du0_sync_1", 2948 "du0_oddf", 2949 "du0_cde", 2950 }; 2951 2952 static const char * const du1_groups[] = { 2953 "du1_rgb666", 2954 "du1_rgb888", 2955 "du1_clk_in", 2956 "du1_clk_out", 2957 "du1_sync_0", 2958 "du1_sync_1", 2959 "du1_oddf", 2960 "du1_cde", 2961 }; 2962 2963 static const char * const ether_groups[] = { 2964 "ether_rmii", 2965 "ether_link", 2966 "ether_magic", 2967 }; 2968 2969 static const char * const hscif0_groups[] = { 2970 "hscif0_data", 2971 "hscif0_data_b", 2972 "hscif0_ctrl", 2973 "hscif0_ctrl_b", 2974 "hscif0_clk", 2975 "hscif0_clk_b", 2976 }; 2977 2978 static const char * const hscif1_groups[] = { 2979 "hscif1_data", 2980 "hscif1_data_b", 2981 "hscif1_ctrl", 2982 "hscif1_ctrl_b", 2983 "hscif1_clk", 2984 "hscif1_clk_b", 2985 }; 2986 2987 static const char * const hspi0_groups[] = { 2988 "hspi0", 2989 }; 2990 2991 static const char * const hspi1_groups[] = { 2992 "hspi1", 2993 "hspi1_b", 2994 "hspi1_c", 2995 "hspi1_d", 2996 }; 2997 2998 static const char * const hspi2_groups[] = { 2999 "hspi2", 3000 "hspi2_b", 3001 }; 3002 3003 static const char * const i2c1_groups[] = { 3004 "i2c1", 3005 "i2c1_b", 3006 "i2c1_c", 3007 "i2c1_d", 3008 }; 3009 3010 static const char * const i2c2_groups[] = { 3011 "i2c2", 3012 "i2c2_b", 3013 "i2c2_c", 3014 "i2c2_d", 3015 }; 3016 3017 static const char * const i2c3_groups[] = { 3018 "i2c3", 3019 "i2c3_b", 3020 }; 3021 3022 static const char * const intc_groups[] = { 3023 "intc_irq0", 3024 "intc_irq0_b", 3025 "intc_irq1", 3026 "intc_irq1_b", 3027 "intc_irq2", 3028 "intc_irq2_b", 3029 "intc_irq3", 3030 "intc_irq3_b", 3031 }; 3032 3033 static const char * const lbsc_groups[] = { 3034 "lbsc_cs0", 3035 "lbsc_cs1", 3036 "lbsc_ex_cs0", 3037 "lbsc_ex_cs1", 3038 "lbsc_ex_cs2", 3039 "lbsc_ex_cs3", 3040 "lbsc_ex_cs4", 3041 "lbsc_ex_cs5", 3042 }; 3043 3044 static const char * const mmc0_groups[] = { 3045 "mmc0_data1", 3046 "mmc0_data4", 3047 "mmc0_data8", 3048 "mmc0_ctrl", 3049 }; 3050 3051 static const char * const mmc1_groups[] = { 3052 "mmc1_data1", 3053 "mmc1_data4", 3054 "mmc1_data8", 3055 "mmc1_ctrl", 3056 }; 3057 3058 static const char * const pwm0_groups[] = { 3059 "pwm0", 3060 "pwm0_b", 3061 "pwm0_c", 3062 "pwm0_d", 3063 }; 3064 3065 static const char * const pwm1_groups[] = { 3066 "pwm1", 3067 }; 3068 3069 static const char * const pwm2_groups[] = { 3070 "pwm2", 3071 }; 3072 3073 static const char * const pwm3_groups[] = { 3074 "pwm3", 3075 }; 3076 3077 static const char * const pwm4_groups[] = { 3078 "pwm4", 3079 }; 3080 3081 static const char * const pwm5_groups[] = { 3082 "pwm5", 3083 }; 3084 3085 static const char * const pwm6_groups[] = { 3086 "pwm6", 3087 }; 3088 3089 static const char * const scif0_groups[] = { 3090 "scif0_data", 3091 "scif0_clk", 3092 "scif0_ctrl", 3093 "scif0_data_b", 3094 "scif0_clk_b", 3095 "scif0_ctrl_b", 3096 "scif0_data_c", 3097 "scif0_clk_c", 3098 "scif0_ctrl_c", 3099 "scif0_data_d", 3100 "scif0_clk_d", 3101 "scif0_ctrl_d", 3102 }; 3103 3104 static const char * const scif1_groups[] = { 3105 "scif1_data", 3106 "scif1_clk", 3107 "scif1_ctrl", 3108 "scif1_data_b", 3109 "scif1_clk_b", 3110 "scif1_ctrl_b", 3111 "scif1_data_c", 3112 "scif1_clk_c", 3113 "scif1_ctrl_c", 3114 }; 3115 3116 static const char * const scif2_groups[] = { 3117 "scif2_data", 3118 "scif2_clk", 3119 "scif2_data_b", 3120 "scif2_clk_b", 3121 "scif2_data_c", 3122 "scif2_clk_c", 3123 "scif2_data_d", 3124 "scif2_clk_d", 3125 "scif2_data_e", 3126 }; 3127 3128 static const char * const scif3_groups[] = { 3129 "scif3_data", 3130 "scif3_clk", 3131 "scif3_data_b", 3132 "scif3_data_c", 3133 "scif3_data_d", 3134 "scif3_data_e", 3135 "scif3_clk_e", 3136 }; 3137 3138 static const char * const scif4_groups[] = { 3139 "scif4_data", 3140 "scif4_clk", 3141 "scif4_data_b", 3142 "scif4_clk_b", 3143 "scif4_data_c", 3144 "scif4_data_d", 3145 }; 3146 3147 static const char * const scif5_groups[] = { 3148 "scif5_data", 3149 "scif5_clk", 3150 "scif5_data_b", 3151 "scif5_clk_b", 3152 "scif5_data_c", 3153 "scif5_clk_c", 3154 "scif5_data_d", 3155 "scif5_clk_d", 3156 }; 3157 3158 static const char * const scif_clk_groups[] = { 3159 "scif_clk", 3160 "scif_clk_b", 3161 "scif_clk_c", 3162 "scif_clk_d", 3163 }; 3164 3165 static const char * const sdhi0_groups[] = { 3166 "sdhi0_data1", 3167 "sdhi0_data4", 3168 "sdhi0_ctrl", 3169 "sdhi0_cd", 3170 "sdhi0_wp", 3171 }; 3172 3173 static const char * const sdhi1_groups[] = { 3174 "sdhi1_data1", 3175 "sdhi1_data4", 3176 "sdhi1_ctrl", 3177 "sdhi1_cd", 3178 "sdhi1_wp", 3179 }; 3180 3181 static const char * const sdhi2_groups[] = { 3182 "sdhi2_data1", 3183 "sdhi2_data4", 3184 "sdhi2_ctrl", 3185 "sdhi2_cd", 3186 "sdhi2_wp", 3187 }; 3188 3189 static const char * const sdhi3_groups[] = { 3190 "sdhi3_data1", 3191 "sdhi3_data4", 3192 "sdhi3_ctrl", 3193 "sdhi3_cd", 3194 "sdhi3_wp", 3195 }; 3196 3197 static const char * const usb0_groups[] = { 3198 "usb0", 3199 "usb0_ovc", 3200 }; 3201 3202 static const char * const usb1_groups[] = { 3203 "usb1", 3204 "usb1_ovc", 3205 }; 3206 3207 static const char * const usb2_groups[] = { 3208 "usb2", 3209 "usb2_ovc", 3210 }; 3211 3212 static const char * const vin0_groups[] = { 3213 "vin0_data8", 3214 "vin0_clk", 3215 "vin0_sync", 3216 }; 3217 3218 static const char * const vin1_groups[] = { 3219 "vin1_data8", 3220 "vin1_clk", 3221 "vin1_sync", 3222 }; 3223 3224 static const char * const vin2_groups[] = { 3225 "vin2_data8", 3226 "vin2_clk", 3227 "vin2_sync", 3228 }; 3229 3230 static const char * const vin3_groups[] = { 3231 "vin3_data8", 3232 "vin3_clk", 3233 "vin3_sync", 3234 }; 3235 3236 static const struct sh_pfc_function pinmux_functions[] = { 3237 SH_PFC_FUNCTION(du0), 3238 SH_PFC_FUNCTION(du1), 3239 SH_PFC_FUNCTION(ether), 3240 SH_PFC_FUNCTION(hscif0), 3241 SH_PFC_FUNCTION(hscif1), 3242 SH_PFC_FUNCTION(hspi0), 3243 SH_PFC_FUNCTION(hspi1), 3244 SH_PFC_FUNCTION(hspi2), 3245 SH_PFC_FUNCTION(i2c1), 3246 SH_PFC_FUNCTION(i2c2), 3247 SH_PFC_FUNCTION(i2c3), 3248 SH_PFC_FUNCTION(intc), 3249 SH_PFC_FUNCTION(lbsc), 3250 SH_PFC_FUNCTION(mmc0), 3251 SH_PFC_FUNCTION(mmc1), 3252 SH_PFC_FUNCTION(pwm0), 3253 SH_PFC_FUNCTION(pwm1), 3254 SH_PFC_FUNCTION(pwm2), 3255 SH_PFC_FUNCTION(pwm3), 3256 SH_PFC_FUNCTION(pwm4), 3257 SH_PFC_FUNCTION(pwm5), 3258 SH_PFC_FUNCTION(pwm6), 3259 SH_PFC_FUNCTION(scif0), 3260 SH_PFC_FUNCTION(scif1), 3261 SH_PFC_FUNCTION(scif2), 3262 SH_PFC_FUNCTION(scif3), 3263 SH_PFC_FUNCTION(scif4), 3264 SH_PFC_FUNCTION(scif5), 3265 SH_PFC_FUNCTION(scif_clk), 3266 SH_PFC_FUNCTION(sdhi0), 3267 SH_PFC_FUNCTION(sdhi1), 3268 SH_PFC_FUNCTION(sdhi2), 3269 SH_PFC_FUNCTION(sdhi3), 3270 SH_PFC_FUNCTION(usb0), 3271 SH_PFC_FUNCTION(usb1), 3272 SH_PFC_FUNCTION(usb2), 3273 SH_PFC_FUNCTION(vin0), 3274 SH_PFC_FUNCTION(vin1), 3275 SH_PFC_FUNCTION(vin2), 3276 SH_PFC_FUNCTION(vin3), 3277 }; 3278 3279 static const struct pinmux_cfg_reg pinmux_config_regs[] = { 3280 { PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1, GROUP( 3281 GP_0_31_FN, FN_IP3_31_29, 3282 GP_0_30_FN, FN_IP3_26_24, 3283 GP_0_29_FN, FN_IP3_22_21, 3284 GP_0_28_FN, FN_IP3_14_12, 3285 GP_0_27_FN, FN_IP3_11_9, 3286 GP_0_26_FN, FN_IP3_2_0, 3287 GP_0_25_FN, FN_IP2_30_28, 3288 GP_0_24_FN, FN_IP2_21_19, 3289 GP_0_23_FN, FN_IP2_18_16, 3290 GP_0_22_FN, FN_IP0_30_28, 3291 GP_0_21_FN, FN_IP0_5_3, 3292 GP_0_20_FN, FN_IP1_18_15, 3293 GP_0_19_FN, FN_IP1_14_11, 3294 GP_0_18_FN, FN_IP1_10_7, 3295 GP_0_17_FN, FN_IP1_6_4, 3296 GP_0_16_FN, FN_IP1_3_2, 3297 GP_0_15_FN, FN_IP1_1_0, 3298 GP_0_14_FN, FN_IP0_27_26, 3299 GP_0_13_FN, FN_IP0_25, 3300 GP_0_12_FN, FN_IP0_24_23, 3301 GP_0_11_FN, FN_IP0_22_19, 3302 GP_0_10_FN, FN_IP0_18_16, 3303 GP_0_9_FN, FN_IP0_15_14, 3304 GP_0_8_FN, FN_IP0_13_12, 3305 GP_0_7_FN, FN_IP0_11_10, 3306 GP_0_6_FN, FN_IP0_9_8, 3307 GP_0_5_FN, FN_A19, 3308 GP_0_4_FN, FN_A18, 3309 GP_0_3_FN, FN_A17, 3310 GP_0_2_FN, FN_IP0_7_6, 3311 GP_0_1_FN, FN_AVS2, 3312 GP_0_0_FN, FN_AVS1 )) 3313 }, 3314 { PINMUX_CFG_REG("GPSR1", 0xfffc0008, 32, 1, GROUP( 3315 GP_1_31_FN, FN_IP5_23_21, 3316 GP_1_30_FN, FN_IP5_20_17, 3317 GP_1_29_FN, FN_IP5_16_15, 3318 GP_1_28_FN, FN_IP5_14_13, 3319 GP_1_27_FN, FN_IP5_12_11, 3320 GP_1_26_FN, FN_IP5_10_9, 3321 GP_1_25_FN, FN_IP5_8, 3322 GP_1_24_FN, FN_IP5_7, 3323 GP_1_23_FN, FN_IP5_6, 3324 GP_1_22_FN, FN_IP5_5, 3325 GP_1_21_FN, FN_IP5_4, 3326 GP_1_20_FN, FN_IP5_3, 3327 GP_1_19_FN, FN_IP5_2_0, 3328 GP_1_18_FN, FN_IP4_31_29, 3329 GP_1_17_FN, FN_IP4_28, 3330 GP_1_16_FN, FN_IP4_27, 3331 GP_1_15_FN, FN_IP4_26, 3332 GP_1_14_FN, FN_IP4_25, 3333 GP_1_13_FN, FN_IP4_24, 3334 GP_1_12_FN, FN_IP4_23, 3335 GP_1_11_FN, FN_IP4_22_20, 3336 GP_1_10_FN, FN_IP4_19_17, 3337 GP_1_9_FN, FN_IP4_16, 3338 GP_1_8_FN, FN_IP4_15, 3339 GP_1_7_FN, FN_IP4_14, 3340 GP_1_6_FN, FN_IP4_13, 3341 GP_1_5_FN, FN_IP4_12, 3342 GP_1_4_FN, FN_IP4_11, 3343 GP_1_3_FN, FN_IP4_10_8, 3344 GP_1_2_FN, FN_IP4_7_5, 3345 GP_1_1_FN, FN_IP4_4_2, 3346 GP_1_0_FN, FN_IP4_1_0 )) 3347 }, 3348 { PINMUX_CFG_REG("GPSR2", 0xfffc000c, 32, 1, GROUP( 3349 GP_2_31_FN, FN_IP10_28_26, 3350 GP_2_30_FN, FN_IP10_25_24, 3351 GP_2_29_FN, FN_IP10_23_21, 3352 GP_2_28_FN, FN_IP10_20_18, 3353 GP_2_27_FN, FN_IP10_17_15, 3354 GP_2_26_FN, FN_IP10_14_12, 3355 GP_2_25_FN, FN_IP10_11_9, 3356 GP_2_24_FN, FN_IP10_8_6, 3357 GP_2_23_FN, FN_IP10_5_3, 3358 GP_2_22_FN, FN_IP10_2_0, 3359 GP_2_21_FN, FN_IP9_29_28, 3360 GP_2_20_FN, FN_IP9_27_26, 3361 GP_2_19_FN, FN_IP9_25_24, 3362 GP_2_18_FN, FN_IP9_23_22, 3363 GP_2_17_FN, FN_IP9_21_19, 3364 GP_2_16_FN, FN_IP9_18_16, 3365 GP_2_15_FN, FN_IP9_15_14, 3366 GP_2_14_FN, FN_IP9_13_12, 3367 GP_2_13_FN, FN_IP9_11_10, 3368 GP_2_12_FN, FN_IP9_9_8, 3369 GP_2_11_FN, FN_IP9_7, 3370 GP_2_10_FN, FN_IP9_6, 3371 GP_2_9_FN, FN_IP9_5, 3372 GP_2_8_FN, FN_IP9_4, 3373 GP_2_7_FN, FN_IP9_3_2, 3374 GP_2_6_FN, FN_IP9_1_0, 3375 GP_2_5_FN, FN_IP8_30_28, 3376 GP_2_4_FN, FN_IP8_27_25, 3377 GP_2_3_FN, FN_IP8_24_23, 3378 GP_2_2_FN, FN_IP8_22_21, 3379 GP_2_1_FN, FN_IP8_20, 3380 GP_2_0_FN, FN_IP5_27_24 )) 3381 }, 3382 { PINMUX_CFG_REG("GPSR3", 0xfffc0010, 32, 1, GROUP( 3383 GP_3_31_FN, FN_IP6_3_2, 3384 GP_3_30_FN, FN_IP6_1_0, 3385 GP_3_29_FN, FN_IP5_30_29, 3386 GP_3_28_FN, FN_IP5_28, 3387 GP_3_27_FN, FN_IP1_24_23, 3388 GP_3_26_FN, FN_IP1_22_21, 3389 GP_3_25_FN, FN_IP1_20_19, 3390 GP_3_24_FN, FN_IP7_26_25, 3391 GP_3_23_FN, FN_IP7_24_23, 3392 GP_3_22_FN, FN_IP7_22_21, 3393 GP_3_21_FN, FN_IP7_20_19, 3394 GP_3_20_FN, FN_IP7_30_29, 3395 GP_3_19_FN, FN_IP7_28_27, 3396 GP_3_18_FN, FN_IP7_18_17, 3397 GP_3_17_FN, FN_IP7_16_15, 3398 GP_3_16_FN, FN_IP12_17_15, 3399 GP_3_15_FN, FN_IP12_14_12, 3400 GP_3_14_FN, FN_IP12_11_9, 3401 GP_3_13_FN, FN_IP12_8_6, 3402 GP_3_12_FN, FN_IP12_5_3, 3403 GP_3_11_FN, FN_IP12_2_0, 3404 GP_3_10_FN, FN_IP11_29_27, 3405 GP_3_9_FN, FN_IP11_26_24, 3406 GP_3_8_FN, FN_IP11_23_21, 3407 GP_3_7_FN, FN_IP11_20_18, 3408 GP_3_6_FN, FN_IP11_17_15, 3409 GP_3_5_FN, FN_IP11_14_12, 3410 GP_3_4_FN, FN_IP11_11_9, 3411 GP_3_3_FN, FN_IP11_8_6, 3412 GP_3_2_FN, FN_IP11_5_3, 3413 GP_3_1_FN, FN_IP11_2_0, 3414 GP_3_0_FN, FN_IP10_31_29 )) 3415 }, 3416 { PINMUX_CFG_REG("GPSR4", 0xfffc0014, 32, 1, GROUP( 3417 GP_4_31_FN, FN_IP8_19, 3418 GP_4_30_FN, FN_IP8_18, 3419 GP_4_29_FN, FN_IP8_17_16, 3420 GP_4_28_FN, FN_IP0_2_0, 3421 GP_4_27_FN, FN_USB_PENC1, 3422 GP_4_26_FN, FN_USB_PENC0, 3423 GP_4_25_FN, FN_IP8_15_12, 3424 GP_4_24_FN, FN_IP8_11_8, 3425 GP_4_23_FN, FN_IP8_7_4, 3426 GP_4_22_FN, FN_IP8_3_0, 3427 GP_4_21_FN, FN_IP2_3_0, 3428 GP_4_20_FN, FN_IP1_28_25, 3429 GP_4_19_FN, FN_IP2_15_12, 3430 GP_4_18_FN, FN_IP2_11_8, 3431 GP_4_17_FN, FN_IP2_7_4, 3432 GP_4_16_FN, FN_IP7_14_13, 3433 GP_4_15_FN, FN_IP7_12_10, 3434 GP_4_14_FN, FN_IP7_9_7, 3435 GP_4_13_FN, FN_IP7_6_4, 3436 GP_4_12_FN, FN_IP7_3_2, 3437 GP_4_11_FN, FN_IP7_1_0, 3438 GP_4_10_FN, FN_IP6_30_29, 3439 GP_4_9_FN, FN_IP6_26_25, 3440 GP_4_8_FN, FN_IP6_24_23, 3441 GP_4_7_FN, FN_IP6_22_20, 3442 GP_4_6_FN, FN_IP6_19_18, 3443 GP_4_5_FN, FN_IP6_17_15, 3444 GP_4_4_FN, FN_IP6_14_12, 3445 GP_4_3_FN, FN_IP6_11_9, 3446 GP_4_2_FN, FN_IP6_8, 3447 GP_4_1_FN, FN_IP6_7_6, 3448 GP_4_0_FN, FN_IP6_5_4 )) 3449 }, 3450 { PINMUX_CFG_REG("GPSR5", 0xfffc0018, 32, 1, GROUP( 3451 GP_5_31_FN, FN_IP3_5, 3452 GP_5_30_FN, FN_IP3_4, 3453 GP_5_29_FN, FN_IP3_3, 3454 GP_5_28_FN, FN_IP2_27, 3455 GP_5_27_FN, FN_IP2_26, 3456 GP_5_26_FN, FN_IP2_25, 3457 GP_5_25_FN, FN_IP2_24, 3458 GP_5_24_FN, FN_IP2_23, 3459 GP_5_23_FN, FN_IP2_22, 3460 GP_5_22_FN, FN_IP3_28, 3461 GP_5_21_FN, FN_IP3_27, 3462 GP_5_20_FN, FN_IP3_23, 3463 GP_5_19_FN, FN_EX_WAIT0, 3464 GP_5_18_FN, FN_WE1, 3465 GP_5_17_FN, FN_WE0, 3466 GP_5_16_FN, FN_RD, 3467 GP_5_15_FN, FN_A16, 3468 GP_5_14_FN, FN_A15, 3469 GP_5_13_FN, FN_A14, 3470 GP_5_12_FN, FN_A13, 3471 GP_5_11_FN, FN_A12, 3472 GP_5_10_FN, FN_A11, 3473 GP_5_9_FN, FN_A10, 3474 GP_5_8_FN, FN_A9, 3475 GP_5_7_FN, FN_A8, 3476 GP_5_6_FN, FN_A7, 3477 GP_5_5_FN, FN_A6, 3478 GP_5_4_FN, FN_A5, 3479 GP_5_3_FN, FN_A4, 3480 GP_5_2_FN, FN_A3, 3481 GP_5_1_FN, FN_A2, 3482 GP_5_0_FN, FN_A1 )) 3483 }, 3484 { PINMUX_CFG_REG_VAR("GPSR6", 0xfffc001c, 32, 3485 GROUP(-23, 1, 1, 1, 1, 1, 1, 1, 1, 1), 3486 GROUP( 3487 /* GP6_31_9 RESERVED */ 3488 GP_6_8_FN, FN_IP3_20, 3489 GP_6_7_FN, FN_IP3_19, 3490 GP_6_6_FN, FN_IP3_18, 3491 GP_6_5_FN, FN_IP3_17, 3492 GP_6_4_FN, FN_IP3_16, 3493 GP_6_3_FN, FN_IP3_15, 3494 GP_6_2_FN, FN_IP3_8, 3495 GP_6_1_FN, FN_IP3_7, 3496 GP_6_0_FN, FN_IP3_6 )) 3497 }, 3498 3499 { PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32, 3500 GROUP(-1, 3, 2, 1, 2, 4, 3, 2, 2, 2, 2, 2, 3, 3), 3501 GROUP( 3502 /* IP0_31 [1] RESERVED */ 3503 /* IP0_30_28 [3] */ 3504 FN_RD_WR, FN_FWE, FN_ATAG0, FN_VI1_R7, 3505 FN_HRTS1, FN_RX4_C, 0, 0, 3506 /* IP0_27_26 [2] */ 3507 FN_CS1_A26, FN_HSPI_TX2, FN_SDSELF_B, 0, 3508 /* IP0_25 [1] */ 3509 FN_CS0, FN_HSPI_CS2_B, 3510 /* IP0_24_23 [2] */ 3511 FN_CLKOUT, FN_TX3C_IRDA_TX_C, FN_PWM0_B, 0, 3512 /* IP0_22_19 [4] */ 3513 FN_A25, FN_SD1_WP, FN_MMC0_D5, FN_FD5, 3514 FN_HSPI_RX2, FN_VI1_R3, FN_TX5_B, FN_SSI_SDATA7_B, 3515 FN_CTS0_B, 0, 0, 0, 3516 0, 0, 0, 0, 3517 /* IP0_18_16 [3] */ 3518 FN_A24, FN_SD1_CD, FN_MMC0_D4, FN_FD4, 3519 FN_HSPI_CS2, FN_VI1_R2, FN_SSI_WS78_B, 0, 3520 /* IP0_15_14 [2] */ 3521 FN_A23, FN_FCLE, FN_HSPI_CLK2, FN_VI1_R1, 3522 /* IP0_13_12 [2] */ 3523 FN_A22, FN_RX5_D, FN_HSPI_RX2_B, FN_VI1_R0, 3524 /* IP0_11_10 [2] */ 3525 FN_A21, FN_SCK5_D, FN_HSPI_CLK2_B, 0, 3526 /* IP0_9_8 [2] */ 3527 FN_A20, FN_TX5_D, FN_HSPI_TX2_B, 0, 3528 /* IP0_7_6 [2] */ 3529 FN_A0, FN_SD1_DAT3, FN_MMC0_D3, FN_FD3, 3530 /* IP0_5_3 [3] */ 3531 FN_BS, FN_SD1_DAT2, FN_MMC0_D2, FN_FD2, 3532 FN_ATADIR0, FN_SDSELF, FN_HCTS1, FN_TX4_C, 3533 /* IP0_2_0 [3] */ 3534 FN_USB_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0, 3535 FN_SCIF_CLK, FN_TCLK0_C, 0, 0 )) 3536 }, 3537 { PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32, 3538 GROUP(-3, 4, 2, 2, 2, 4, 4, 4, 3, 2, 2), 3539 GROUP( 3540 /* IP1_31_29 [3] RESERVED */ 3541 /* IP1_28_25 [4] */ 3542 FN_HTX0, FN_TX1, FN_SDATA, FN_CTS0_C, 3543 FN_SUB_TCK, FN_CC5_STATE2, FN_CC5_STATE10, FN_CC5_STATE18, 3544 FN_CC5_STATE26, FN_CC5_STATE34, 0, 0, 3545 0, 0, 0, 0, 3546 /* IP1_24_23 [2] */ 3547 FN_MLB_DAT, FN_PWM4, FN_RX4, 0, 3548 /* IP1_22_21 [2] */ 3549 FN_MLB_SIG, FN_PWM3, FN_TX4, 0, 3550 /* IP1_20_19 [2] */ 3551 FN_MLB_CLK, FN_PWM2, FN_SCK4, 0, 3552 /* IP1_18_15 [4] */ 3553 FN_EX_CS5, FN_SD1_DAT1, FN_MMC0_D1, FN_FD1, 3554 FN_ATAWR0, FN_VI1_R6, FN_HRX1, FN_RX2_E, 3555 FN_RX0_B, FN_SSI_WS9, 0, 0, 3556 0, 0, 0, 0, 3557 /* IP1_14_11 [4] */ 3558 FN_EX_CS4, FN_SD1_DAT0, FN_MMC0_D0, FN_FD0, 3559 FN_ATARD0, FN_VI1_R5, FN_SCK5_B, FN_HTX1, 3560 FN_TX2_E, FN_TX0_B, FN_SSI_SCK9, 0, 3561 0, 0, 0, 0, 3562 /* IP1_10_7 [4] */ 3563 FN_EX_CS3, FN_SD1_CMD, FN_MMC0_CMD, FN_FRE, 3564 FN_ATACS10, FN_VI1_R4, FN_RX5_B, FN_HSCK1, 3565 FN_SSI_SDATA8_B, FN_RTS0_B_TANS_B, FN_SSI_SDATA9, 0, 3566 0, 0, 0, 0, 3567 /* IP1_6_4 [3] */ 3568 FN_EX_CS2, FN_SD1_CLK, FN_MMC0_CLK, FN_FALE, 3569 FN_ATACS00, 0, 0, 0, 3570 /* IP1_3_2 [2] */ 3571 FN_EX_CS1, FN_MMC0_D7, FN_FD7, 0, 3572 /* IP1_1_0 [2] */ 3573 FN_EX_CS0, FN_RX3_C_IRDA_RX_C, FN_MMC0_D6, FN_FD6 )) 3574 }, 3575 { PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32, 3576 GROUP(-1, 3, 1, 1, 1, 1, 1, 1, 3, 3, 4, 4, 4, 4), 3577 GROUP( 3578 /* IP2_31 [1] RESERVED */ 3579 /* IP2_30_28 [3] */ 3580 FN_DU0_DG0, FN_LCDOUT8, FN_DREQ1, FN_SCL2, 3581 FN_AUDATA2, 0, 0, 0, 3582 /* IP2_27 [1] */ 3583 FN_DU0_DR7, FN_LCDOUT7, 3584 /* IP2_26 [1] */ 3585 FN_DU0_DR6, FN_LCDOUT6, 3586 /* IP2_25 [1] */ 3587 FN_DU0_DR5, FN_LCDOUT5, 3588 /* IP2_24 [1] */ 3589 FN_DU0_DR4, FN_LCDOUT4, 3590 /* IP2_23 [1] */ 3591 FN_DU0_DR3, FN_LCDOUT3, 3592 /* IP2_22 [1] */ 3593 FN_DU0_DR2, FN_LCDOUT2, 3594 /* IP2_21_19 [3] */ 3595 FN_DU0_DR1, FN_LCDOUT1, FN_DACK0, FN_DRACK0, 3596 FN_GPS_SIGN_B, FN_AUDATA1, FN_RX5_C, 0, 3597 /* IP2_18_16 [3] */ 3598 FN_DU0_DR0, FN_LCDOUT0, FN_DREQ0, FN_GPS_CLK_B, 3599 FN_AUDATA0, FN_TX5_C, 0, 0, 3600 /* IP2_15_12 [4] */ 3601 FN_HRTS0, FN_RTS1_TANS, FN_MDATA, FN_TX0_C, 3602 FN_SUB_TMS, FN_CC5_STATE1, FN_CC5_STATE9, FN_CC5_STATE17, 3603 FN_CC5_STATE25, FN_CC5_STATE33, 0, 0, 3604 0, 0, 0, 0, 3605 /* IP2_11_8 [4] */ 3606 FN_HCTS0, FN_CTS1, FN_STM, FN_PWM0_D, 3607 FN_RX0_C, FN_SCIF_CLK_C, FN_SUB_TRST, FN_TCLK1_B, 3608 FN_CC5_OSCOUT, 0, 0, 0, 3609 0, 0, 0, 0, 3610 /* IP2_7_4 [4] */ 3611 FN_HSCK0, FN_SCK1, FN_MTS, FN_PWM5, 3612 FN_SCK0_C, FN_SSI_SDATA9_B, FN_SUB_TDO, FN_CC5_STATE0, 3613 FN_CC5_STATE8, FN_CC5_STATE16, FN_CC5_STATE24, FN_CC5_STATE32, 3614 0, 0, 0, 0, 3615 /* IP2_3_0 [4] */ 3616 FN_HRX0, FN_RX1, FN_SCKZ, FN_RTS0_C_TANS_C, 3617 FN_SUB_TDI, FN_CC5_STATE3, FN_CC5_STATE11, FN_CC5_STATE19, 3618 FN_CC5_STATE27, FN_CC5_STATE35, 0, 0, 3619 0, 0, 0, 0 )) 3620 }, 3621 { PINMUX_CFG_REG_VAR("IPSR3", 0xfffc002c, 32, 3622 GROUP(3, 1, 1, 3, 1, 2, 1, 1, 1, 1, 1, 1, 3623 3, 3, 1, 1, 1, 1, 1, 1, 3), 3624 GROUP( 3625 /* IP3_31_29 [3] */ 3626 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CAN1_TX, FN_TX2_C, 3627 FN_SCL2_C, FN_REMOCON, 0, 0, 3628 /* IP3_28 [1] */ 3629 FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, 3630 /* IP3_27 [1] */ 3631 FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS, 3632 /* IP3_26_24 [3] */ 3633 FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, FN_RX3_D_IRDA_RX_D, FN_SDA3_B, 3634 FN_SDA2_C, FN_DACK0_B, FN_DRACK0_B, 0, 3635 /* IP3_23 [1] */ 3636 FN_DU0_DOTCLKOUT0, FN_QCLK, 3637 /* IP3_22_21 [2] */ 3638 FN_DU0_DOTCLKIN, FN_QSTVA_QVS, FN_TX3_D_IRDA_TX_D, FN_SCL3_B, 3639 /* IP3_20 [1] */ 3640 FN_DU0_DB7, FN_LCDOUT23, 3641 /* IP3_19 [1] */ 3642 FN_DU0_DB6, FN_LCDOUT22, 3643 /* IP3_18 [1] */ 3644 FN_DU0_DB5, FN_LCDOUT21, 3645 /* IP3_17 [1] */ 3646 FN_DU0_DB4, FN_LCDOUT20, 3647 /* IP3_16 [1] */ 3648 FN_DU0_DB3, FN_LCDOUT19, 3649 /* IP3_15 [1] */ 3650 FN_DU0_DB2, FN_LCDOUT18, 3651 /* IP3_14_12 [3] */ 3652 FN_DU0_DB1, FN_LCDOUT17, FN_EX_WAIT2, FN_SDA1, 3653 FN_GPS_MAG_B, FN_AUDATA5, FN_SCK5_C, 0, 3654 /* IP3_11_9 [3] */ 3655 FN_DU0_DB0, FN_LCDOUT16, FN_EX_WAIT1, FN_SCL1, 3656 FN_TCLK1, FN_AUDATA4, 0, 0, 3657 /* IP3_8 [1] */ 3658 FN_DU0_DG7, FN_LCDOUT15, 3659 /* IP3_7 [1] */ 3660 FN_DU0_DG6, FN_LCDOUT14, 3661 /* IP3_6 [1] */ 3662 FN_DU0_DG5, FN_LCDOUT13, 3663 /* IP3_5 [1] */ 3664 FN_DU0_DG4, FN_LCDOUT12, 3665 /* IP3_4 [1] */ 3666 FN_DU0_DG3, FN_LCDOUT11, 3667 /* IP3_3 [1] */ 3668 FN_DU0_DG2, FN_LCDOUT10, 3669 /* IP3_2_0 [3] */ 3670 FN_DU0_DG1, FN_LCDOUT9, FN_DACK1, FN_SDA2, 3671 FN_AUDATA3, 0, 0, 0 )) 3672 }, 3673 { PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32, 3674 GROUP(3, 1, 1, 1, 1, 1, 1, 3, 3, 1, 1, 1, 3675 1, 1, 1, 3, 3, 3, 2), 3676 GROUP( 3677 /* IP4_31_29 [3] */ 3678 FN_DU1_DB0, FN_VI2_DATA4_VI2_B4, FN_SCL2_B, FN_SD3_DAT0, 3679 FN_TX5, FN_SCK0_D, 0, 0, 3680 /* IP4_28 [1] */ 3681 FN_DU1_DG7, FN_VI2_R3, 3682 /* IP4_27 [1] */ 3683 FN_DU1_DG6, FN_VI2_R2, 3684 /* IP4_26 [1] */ 3685 FN_DU1_DG5, FN_VI2_R1, 3686 /* IP4_25 [1] */ 3687 FN_DU1_DG4, FN_VI2_R0, 3688 /* IP4_24 [1] */ 3689 FN_DU1_DG3, FN_VI2_G7, 3690 /* IP4_23 [1] */ 3691 FN_DU1_DG2, FN_VI2_G6, 3692 /* IP4_22_20 [3] */ 3693 FN_DU1_DG1, FN_VI2_DATA3_VI2_B3, FN_SDA1_B, FN_SD3_DAT3, 3694 FN_SCK5, FN_AUDATA7, FN_RX0_D, 0, 3695 /* IP4_19_17 [3] */ 3696 FN_DU1_DG0, FN_VI2_DATA2_VI2_B2, FN_SCL1_B, FN_SD3_DAT2, 3697 FN_SCK3_E, FN_AUDATA6, FN_TX0_D, 0, 3698 /* IP4_16 [1] */ 3699 FN_DU1_DR7, FN_VI2_G5, 3700 /* IP4_15 [1] */ 3701 FN_DU1_DR6, FN_VI2_G4, 3702 /* IP4_14 [1] */ 3703 FN_DU1_DR5, FN_VI2_G3, 3704 /* IP4_13 [1] */ 3705 FN_DU1_DR4, FN_VI2_G2, 3706 /* IP4_12 [1] */ 3707 FN_DU1_DR3, FN_VI2_G1, 3708 /* IP4_11 [1] */ 3709 FN_DU1_DR2, FN_VI2_G0, 3710 /* IP4_10_8 [3] */ 3711 FN_DU1_DR1, FN_VI2_DATA1_VI2_B1, FN_PWM0, FN_SD3_CMD, 3712 FN_RX3_E_IRDA_RX_E, FN_AUDSYNC, FN_CTS0_D, 0, 3713 /* IP4_7_5 [3] */ 3714 FN_DU1_DR0, FN_VI2_DATA0_VI2_B0, FN_PWM6, FN_SD3_CLK, 3715 FN_TX3_E_IRDA_TX_E, FN_AUDCK, FN_PWMFSW0_B, 0, 3716 /* IP4_4_2 [3] */ 3717 FN_DU0_CDE, FN_QPOLB, FN_CAN1_RX, FN_RX2_C, 3718 FN_DREQ0_B, FN_SSI_SCK78_B, FN_SCK0_B, 0, 3719 /* IP4_1_0 [2] */ 3720 FN_DU0_DISP, FN_QPOLA, FN_CAN_CLK_C, FN_SCK2_C )) 3721 }, 3722 { PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32, 3723 GROUP(-1, 2, 1, 4, 3, 4, 2, 2, 2, 2, 1, 1, 3724 1, 1, 1, 1, 3), 3725 GROUP( 3726 /* IP5_31 [1] RESERVED */ 3727 /* IP5_30_29 [2] */ 3728 FN_AUDIO_CLKB, FN_USB_OVC2, FN_CAN_DEBUGOUT0, FN_MOUT0, 3729 /* IP5_28 [1] */ 3730 FN_AUDIO_CLKA, FN_CAN_TXCLK, 3731 /* IP5_27_24 [4] */ 3732 FN_DU1_CDE, FN_VI2_DATA7_VI2_B7, FN_RX3_B_IRDA_RX_B, FN_SD3_WP, 3733 FN_HSPI_RX1, FN_VI1_FIELD, FN_VI3_FIELD, FN_AUDIO_CLKOUT, 3734 FN_RX2_D, FN_GPS_CLK_C, FN_GPS_CLK_D, 0, 3735 0, 0, 0, 0, 3736 /* IP5_23_21 [3] */ 3737 FN_DU1_DISP, FN_VI2_DATA6_VI2_B6, FN_TCLK0, FN_QSTVA_B_QVS_B, 3738 FN_HSPI_CLK1, FN_SCK2_D, FN_AUDIO_CLKOUT_B, FN_GPS_MAG_D, 3739 /* IP5_20_17 [4] */ 3740 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_VI2_CLK, FN_TX3_B_IRDA_TX_B, 3741 FN_SD3_CD, FN_HSPI_TX1, FN_VI1_CLKENB, FN_VI3_CLKENB, 3742 FN_AUDIO_CLKC, FN_TX2_D, FN_SPEEDIN, FN_GPS_SIGN_D, 0, 3743 0, 0, 0, 0, 3744 /* IP5_16_15 [2] */ 3745 FN_DU1_EXVSYNC_DU1_VSYNC, FN_VI2_VSYNC, FN_VI3_VSYNC, 0, 3746 /* IP5_14_13 [2] */ 3747 FN_DU1_EXHSYNC_DU1_HSYNC, FN_VI2_HSYNC, FN_VI3_HSYNC, 0, 3748 /* IP5_12_11 [2] */ 3749 FN_DU1_DOTCLKOUT, FN_VI2_FIELD, FN_SDA1_D, 0, 3750 /* IP5_10_9 [2] */ 3751 FN_DU1_DOTCLKIN, FN_VI2_CLKENB, FN_HSPI_CS1, FN_SCL1_D, 3752 /* IP5_8 [1] */ 3753 FN_DU1_DB7, FN_SDA2_D, 3754 /* IP5_7 [1] */ 3755 FN_DU1_DB6, FN_SCL2_D, 3756 /* IP5_6 [1] */ 3757 FN_DU1_DB5, FN_VI2_R7, 3758 /* IP5_5 [1] */ 3759 FN_DU1_DB4, FN_VI2_R6, 3760 /* IP5_4 [1] */ 3761 FN_DU1_DB3, FN_VI2_R5, 3762 /* IP5_3 [1] */ 3763 FN_DU1_DB2, FN_VI2_R4, 3764 /* IP5_2_0 [3] */ 3765 FN_DU1_DB1, FN_VI2_DATA5_VI2_B5, FN_SDA2_B, FN_SD3_DAT1, 3766 FN_RX5, FN_RTS0_D_TANS_D, 0, 0 )) 3767 }, 3768 { PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32, 3769 GROUP(-1, 2, -2, 2, 2, 3, 2, 3, 3, 3, 1, 2, 3770 2, 2, 2), 3771 GROUP( 3772 /* IP6_31 [1] RESERVED */ 3773 /* IP6_30_29 [2] */ 3774 FN_SSI_SCK6, FN_ADICHS0, FN_CAN0_TX, FN_IERX_B, 3775 /* IP_28_27 [2] RESERVED */ 3776 /* IP6_26_25 [2] */ 3777 FN_SSI_SDATA5, FN_ADIDATA, FN_CAN_DEBUGOUT12, FN_RX3_IRDA_RX, 3778 /* IP6_24_23 [2] */ 3779 FN_SSI_WS5, FN_ADICS_SAMP, FN_CAN_DEBUGOUT11, FN_TX3_IRDA_TX, 3780 /* IP6_22_20 [3] */ 3781 FN_SSI_SCK5, FN_ADICLK, FN_CAN_DEBUGOUT10, FN_SCK3, 3782 FN_TCLK0_D, 0, 0, 0, 3783 /* IP6_19_18 [2] */ 3784 FN_SSI_SDATA4, FN_CAN_DEBUGOUT9, FN_SSI_SDATA9_C, 0, 3785 /* IP6_17_15 [3] */ 3786 FN_SSI_SDATA3, FN_PWM0_C, FN_CAN_DEBUGOUT8, FN_CAN_CLK_B, 3787 FN_IECLK, FN_SCIF_CLK_B, FN_TCLK0_B, 0, 3788 /* IP6_14_12 [3] */ 3789 FN_SSI_WS34, FN_CAN_DEBUGOUT7, FN_CAN0_RX_B, FN_IETX, 3790 FN_SSI_WS9_C, 0, 0, 0, 3791 /* IP6_11_9 [3] */ 3792 FN_SSI_SCK34, FN_CAN_DEBUGOUT6, FN_CAN0_TX_B, FN_IERX, 3793 FN_SSI_SCK9_C, 0, 0, 0, 3794 /* IP6_8 [1] */ 3795 FN_SSI_SDATA2, FN_CAN_DEBUGOUT5, 3796 /* IP6_7_6 [2] */ 3797 FN_SSI_SDATA1, FN_CAN_DEBUGOUT4, FN_MOUT6, 0, 3798 /* IP6_5_4 [2] */ 3799 FN_SSI_SDATA0, FN_CAN_DEBUGOUT3, FN_MOUT5, 0, 3800 /* IP6_3_2 [2] */ 3801 FN_SSI_WS0129, FN_CAN_DEBUGOUT2, FN_MOUT2, 0, 3802 /* IP6_1_0 [2] */ 3803 FN_SSI_SCK0129, FN_CAN_DEBUGOUT1, FN_MOUT1, 0 )) 3804 }, 3805 { PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32, 3806 GROUP(-1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3807 3, 2, 2), 3808 GROUP( 3809 /* IP7_31 [1] RESERVED */ 3810 /* IP7_30_29 [2] */ 3811 FN_SD0_WP, FN_DACK2, FN_CTS1_B, 0, 3812 /* IP7_28_27 [2] */ 3813 FN_SD0_CD, FN_DREQ2, FN_RTS1_B_TANS_B, 0, 3814 /* IP7_26_25 [2] */ 3815 FN_SD0_DAT3, FN_ATAWR1, FN_RX2_B, FN_CC5_TDI, 3816 /* IP7_24_23 [2] */ 3817 FN_SD0_DAT2, FN_ATARD1, FN_TX2_B, FN_CC5_TCK, 3818 /* IP7_22_21 [2] */ 3819 FN_SD0_DAT1, FN_ATAG1, FN_SCK2_B, FN_CC5_TMS, 3820 /* IP7_20_19 [2] */ 3821 FN_SD0_DAT0, FN_ATADIR1, FN_RX1_B, FN_CC5_TRST, 3822 /* IP7_18_17 [2] */ 3823 FN_SD0_CMD, FN_ATACS11, FN_TX1_B, FN_CC5_TDO, 3824 /* IP7_16_15 [2] */ 3825 FN_SD0_CLK, FN_ATACS01, FN_SCK1_B, 0, 3826 /* IP7_14_13 [2] */ 3827 FN_SSI_SDATA8, FN_VSP, FN_IRQ3_B, FN_HSPI_RX1_C, 3828 /* IP7_12_10 [3] */ 3829 FN_SSI_SDATA7, FN_CAN_DEBUGOUT15, FN_IRQ2_B, FN_TCLK1_C, 3830 FN_HSPI_TX1_C, 0, 0, 0, 3831 /* IP7_9_7 [3] */ 3832 FN_SSI_WS78, FN_CAN_DEBUGOUT14, FN_IRQ1_B, FN_SSI_WS9_B, 3833 FN_HSPI_CS1_C, 0, 0, 0, 3834 /* IP7_6_4 [3] */ 3835 FN_SSI_SCK78, FN_CAN_DEBUGOUT13, FN_IRQ0_B, FN_SSI_SCK9_B, 3836 FN_HSPI_CLK1_C, 0, 0, 0, 3837 /* IP7_3_2 [2] */ 3838 FN_SSI_SDATA6, FN_ADICHS2, FN_CAN_CLK, FN_IECLK_B, 3839 /* IP7_1_0 [2] */ 3840 FN_SSI_WS6, FN_ADICHS1, FN_CAN0_RX, FN_IETX_B )) 3841 }, 3842 { PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32, 3843 GROUP(-1, 3, 3, 2, 2, 1, 1, 1, 2, 4, 4, 4, 4), 3844 GROUP( 3845 /* IP8_31 [1] RESERVED */ 3846 /* IP8_30_28 [3] */ 3847 FN_VI0_VSYNC, FN_VI0_DATA1_B_VI0_B1_B, FN_RTS1_C_TANS_C, FN_RX4_D, 3848 FN_PWMFSW0_C, 0, 0, 0, 3849 /* IP8_27_25 [3] */ 3850 FN_VI0_HSYNC, FN_VI0_DATA0_B_VI0_B0_B, FN_CTS1_C, FN_TX4_D, 3851 FN_MMC1_CMD, FN_HSCK1_B, 0, 0, 3852 /* IP8_24_23 [2] */ 3853 FN_VI0_FIELD, FN_RX1_C, FN_HRX1_B, 0, 3854 /* IP8_22_21 [2] */ 3855 FN_VI0_CLKENB, FN_TX1_C, FN_HTX1_B, FN_MT1_SYNC, 3856 /* IP8_20 [1] */ 3857 FN_VI0_CLK, FN_MMC1_CLK, 3858 /* IP8_19 [1] */ 3859 FN_FMIN, FN_RDS_DATA, 3860 /* IP8_18 [1] */ 3861 FN_BPFCLK, FN_PCMWE, 3862 /* IP8_17_16 [2] */ 3863 FN_FMCLK, FN_RDS_CLK, FN_PCMOE, 0, 3864 /* IP8_15_12 [4] */ 3865 FN_HSPI_RX0, FN_RX0, FN_CAN_STEP0, FN_AD_NCS, 3866 FN_CC5_STATE7, FN_CC5_STATE15, FN_CC5_STATE23, FN_CC5_STATE31, 3867 FN_CC5_STATE39, 0, 0, 0, 3868 0, 0, 0, 0, 3869 /* IP8_11_8 [4] */ 3870 FN_HSPI_TX0, FN_TX0, FN_CAN_DEBUG_HW_TRIGGER, FN_AD_DO, 3871 FN_CC5_STATE6, FN_CC5_STATE14, FN_CC5_STATE22, FN_CC5_STATE30, 3872 FN_CC5_STATE38, 0, 0, 0, 3873 0, 0, 0, 0, 3874 /* IP8_7_4 [4] */ 3875 FN_HSPI_CS0, FN_RTS0_TANS, FN_USB_OVC1, FN_AD_DI, 3876 FN_CC5_STATE5, FN_CC5_STATE13, FN_CC5_STATE21, FN_CC5_STATE29, 3877 FN_CC5_STATE37, 0, 0, 0, 3878 0, 0, 0, 0, 3879 /* IP8_3_0 [4] */ 3880 FN_HSPI_CLK0, FN_CTS0, FN_USB_OVC0, FN_AD_CLK, 3881 FN_CC5_STATE4, FN_CC5_STATE12, FN_CC5_STATE20, FN_CC5_STATE28, 3882 FN_CC5_STATE36, 0, 0, 0, 3883 0, 0, 0, 0 )) 3884 }, 3885 { PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32, 3886 GROUP(-2, 2, 2, 2, 2, 3, 3, 2, 2, 2, 2, 1, 3887 1, 1, 1, 2, 2), 3888 GROUP( 3889 /* IP9_31_30 [2] RESERVED */ 3890 /* IP9_29_28 [2] */ 3891 FN_VI0_G7, FN_ETH_RXD1, FN_SD2_DAT3_B, FN_ARM_TRACEDATA_9, 3892 /* IP9_27_26 [2] */ 3893 FN_VI0_G6, FN_ETH_RXD0, FN_SD2_DAT2_B, FN_ARM_TRACEDATA_8, 3894 /* IP9_25_24 [2] */ 3895 FN_VI0_G5, FN_ETH_RX_ER, FN_SD2_DAT1_B, FN_ARM_TRACEDATA_7, 3896 /* IP9_23_22 [2] */ 3897 FN_VI0_G4, FN_ETH_TX_EN, FN_SD2_DAT0_B, FN_ARM_TRACEDATA_6, 3898 /* IP9_21_19 [3] */ 3899 FN_VI0_G3, FN_ETH_CRS_DV, FN_MMC1_D7, FN_ARM_TRACEDATA_5, 3900 FN_TS_SDAT0, 0, 0, 0, 3901 /* IP9_18_16 [3] */ 3902 FN_VI0_G2, FN_ETH_TXD1, FN_MMC1_D6, FN_ARM_TRACEDATA_4, 3903 FN_TS_SPSYNC0, 0, 0, 0, 3904 /* IP9_15_14 [2] */ 3905 FN_VI0_G1, FN_SSI_WS78_C, FN_IRQ1, FN_ARM_TRACEDATA_3, 3906 /* IP9_13_12 [2] */ 3907 FN_VI0_G0, FN_SSI_SCK78_C, FN_IRQ0, FN_ARM_TRACEDATA_2, 3908 /* IP9_11_10 [2] */ 3909 FN_VI0_DATA7_VI0_B7, FN_MMC1_D5, FN_ARM_TRACEDATA_1, 0, 3910 /* IP9_9_8 [2] */ 3911 FN_VI0_DATA6_VI0_B6, FN_MMC1_D4, FN_ARM_TRACEDATA_0, 0, 3912 /* IP9_7 [1] */ 3913 FN_VI0_DATA5_VI0_B5, FN_MMC1_D3, 3914 /* IP9_6 [1] */ 3915 FN_VI0_DATA4_VI0_B4, FN_MMC1_D2, 3916 /* IP9_5 [1] */ 3917 FN_VI0_DATA3_VI0_B3, FN_MMC1_D1, 3918 /* IP9_4 [1] */ 3919 FN_VI0_DATA2_VI0_B2, FN_MMC1_D0, 3920 /* IP9_3_2 [2] */ 3921 FN_VI0_DATA1_VI0_B1, FN_HCTS1_B, FN_MT1_PWM, 0, 3922 /* IP9_1_0 [2] */ 3923 FN_VI0_DATA0_VI0_B0, FN_HRTS1_B, FN_MT1_VCXO, 0 )) 3924 }, 3925 { PINMUX_CFG_REG_VAR("IPSR10", 0xfffc0048, 32, 3926 GROUP(3, 3, 2, 3, 3, 3, 3, 3, 3, 3, 3), 3927 GROUP( 3928 /* IP10_31_29 [3] */ 3929 FN_VI1_VSYNC, FN_AUDIO_CLKOUT_C, FN_SSI_WS4, FN_SIM_CLK, 3930 FN_GPS_MAG_C, FN_SPV_TRST, FN_SCL3, 0, 3931 /* IP10_28_26 [3] */ 3932 FN_VI1_HSYNC, FN_VI3_CLK, FN_SSI_SCK4, FN_GPS_SIGN_C, 3933 FN_PWMFSW0_E, 0, 0, 0, 3934 /* IP10_25_24 [2] */ 3935 FN_VI1_CLK, FN_SIM_D, FN_SDA3, 0, 3936 /* IP10_23_21 [3] */ 3937 FN_VI0_R7, FN_ETH_MDIO, FN_DACK2_C, FN_HSPI_RX1_B, 3938 FN_SCIF_CLK_D, FN_TRACECTL, FN_MT1_PEN, 0, 3939 /* IP10_20_18 [3] */ 3940 FN_VI0_R6, FN_ETH_MDC, FN_DREQ2_C, FN_HSPI_TX1_B, 3941 FN_TRACECLK, FN_MT1_BEN, FN_PWMFSW0_D, 0, 3942 /* IP10_17_15 [3] */ 3943 FN_VI0_R5, FN_ETH_TXD0, FN_SD2_WP_B, FN_HSPI_CS1_B, 3944 FN_ARM_TRACEDATA_15, FN_MT1_D, FN_TS_SDEN0, 0, 3945 /* IP10_14_12 [3] */ 3946 FN_VI0_R4, FN_ETH_REFCLK, FN_SD2_CD_B, FN_HSPI_CLK1_B, 3947 FN_ARM_TRACEDATA_14, FN_MT1_CLK, FN_TS_SCK0, 0, 3948 /* IP10_11_9 [3] */ 3949 FN_VI0_R3, FN_ETH_MAGIC, FN_SD2_CMD_B, FN_IRQ3, 3950 FN_ARM_TRACEDATA_13, 0, 0, 0, 3951 /* IP10_8_6 [3] */ 3952 FN_VI0_R2, FN_ETH_LINK, FN_SD2_CLK_B, FN_IRQ2, 3953 FN_ARM_TRACEDATA_12, 0, 0, 0, 3954 /* IP10_5_3 [3] */ 3955 FN_VI0_R1, FN_SSI_SDATA8_C, FN_DACK1_B, FN_ARM_TRACEDATA_11, 3956 FN_DACK0_C, FN_DRACK0_C, 0, 0, 3957 /* IP10_2_0 [3] */ 3958 FN_VI0_R0, FN_SSI_SDATA7_C, FN_SCK1_C, FN_DREQ1_B, 3959 FN_ARM_TRACEDATA_10, FN_DREQ0_C, 0, 0 )) 3960 }, 3961 { PINMUX_CFG_REG_VAR("IPSR11", 0xfffc004c, 32, 3962 GROUP(-2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3), 3963 GROUP( 3964 /* IP11_31_30 [2] RESERVED */ 3965 /* IP11_29_27 [3] */ 3966 FN_VI1_G1, FN_VI3_DATA1, FN_SSI_SCK1, FN_TS_SDEN1, 3967 FN_DACK2_B, FN_RX2, FN_HRTS0_B, 0, 3968 /* IP11_26_24 [3] */ 3969 FN_VI1_G0, FN_VI3_DATA0, 0, FN_TS_SCK1, 3970 FN_DREQ2_B, FN_TX2, FN_SPA_TDO, FN_HCTS0_B, 3971 /* IP11_23_21 [3] */ 3972 FN_VI1_DATA7_VI1_B7, FN_SD2_WP, FN_MT0_PWM, FN_SPA_TDI, 3973 FN_HSPI_RX1_D, 0, 0, 0, 3974 /* IP11_20_18 [3] */ 3975 FN_VI1_DATA6_VI1_B6, FN_SD2_CD, FN_MT0_VCXO, FN_SPA_TMS, 3976 FN_HSPI_TX1_D, 0, 0, 0, 3977 /* IP11_17_15 [3] */ 3978 FN_VI1_DATA5_VI1_B5, FN_SD2_CMD, FN_MT0_SYNC, FN_SPA_TCK, 3979 FN_HSPI_CS1_D, FN_ADICHS2_B, 0, 0, 3980 /* IP11_14_12 [3] */ 3981 FN_VI1_DATA4_VI1_B4, FN_SD2_CLK, FN_MT0_PEN, FN_SPA_TRST, 3982 FN_HSPI_CLK1_D, FN_ADICHS1_B, 0, 0, 3983 /* IP11_11_9 [3] */ 3984 FN_VI1_DATA3_VI1_B3, FN_SD2_DAT3, FN_MT0_BEN, FN_SPV_TDO, 3985 FN_ADICHS0_B, 0, 0, 0, 3986 /* IP11_8_6 [3] */ 3987 FN_VI1_DATA2_VI1_B2, FN_SD2_DAT2, FN_MT0_D, FN_SPVTDI, 3988 FN_ADIDATA_B, 0, 0, 0, 3989 /* IP11_5_3 [3] */ 3990 FN_VI1_DATA1_VI1_B1, FN_SD2_DAT1, FN_MT0_CLK, FN_SPV_TMS, 3991 FN_ADICS_B_SAMP_B, 0, 0, 0, 3992 /* IP11_2_0 [3] */ 3993 FN_VI1_DATA0_VI1_B0, FN_SD2_DAT0, FN_SIM_RST, FN_SPV_TCK, 3994 FN_ADICLK_B, 0, 0, 0 )) 3995 }, 3996 { PINMUX_CFG_REG_VAR("IPSR12", 0xfffc0050, 32, 3997 GROUP(-14, 3, 3, 3, 3, 3, 3), 3998 GROUP( 3999 /* IP12_31_18 [14] RESERVED */ 4000 /* IP12_17_15 [3] */ 4001 FN_VI1_G7, FN_VI3_DATA7, FN_GPS_MAG, FN_FCE, 4002 FN_SCK4_B, 0, 0, 0, 4003 /* IP12_14_12 [3] */ 4004 FN_VI1_G6, FN_VI3_DATA6, FN_GPS_SIGN, FN_FRB, 4005 FN_RX4_B, FN_SIM_CLK_B, 0, 0, 4006 /* IP12_11_9 [3] */ 4007 FN_VI1_G5, FN_VI3_DATA5, FN_GPS_CLK, FN_FSE, 4008 FN_TX4_B, FN_SIM_D_B, 0, 0, 4009 /* IP12_8_6 [3] */ 4010 FN_VI1_G4, FN_VI3_DATA4, FN_SSI_WS2, FN_SDA1_C, 4011 FN_SIM_RST_B, FN_HRX0_B, 0, 0, 4012 /* IP12_5_3 [3] */ 4013 FN_VI1_G3, FN_VI3_DATA3, FN_SSI_SCK2, FN_TS_SDAT1, 4014 FN_SCL1_C, FN_HTX0_B, 0, 0, 4015 /* IP12_2_0 [3] */ 4016 FN_VI1_G2, FN_VI3_DATA2, FN_SSI_WS1, FN_TS_SPSYNC1, 4017 FN_SCK2, FN_HSCK0_B, 0, 0 )) 4018 }, 4019 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xfffc0090, 32, 4020 GROUP(2, 2, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 4021 1, 1, 1, 1, 2, 1, 2), 4022 GROUP( 4023 /* SEL_SCIF5 [2] */ 4024 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3, 4025 /* SEL_SCIF4 [2] */ 4026 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3, 4027 /* SEL_SCIF3 [3] */ 4028 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3, 4029 FN_SEL_SCIF3_4, 0, 0, 0, 4030 /* SEL_SCIF2 [3] */ 4031 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3, 4032 FN_SEL_SCIF2_4, 0, 0, 0, 4033 /* SEL_SCIF1 [2] */ 4034 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, 0, 4035 /* SEL_SCIF0 [2] */ 4036 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3, 4037 /* SEL_SSI9 [2] */ 4038 FN_SEL_SSI9_0, FN_SEL_SSI9_1, FN_SEL_SSI9_2, 0, 4039 /* SEL_SSI8 [2] */ 4040 FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, 4041 /* SEL_SSI7 [2] */ 4042 FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 0, 4043 /* SEL_VI0 [1] */ 4044 FN_SEL_VI0_0, FN_SEL_VI0_1, 4045 /* SEL_SD2 [1] */ 4046 FN_SEL_SD2_0, FN_SEL_SD2_1, 4047 /* SEL_INT3 [1] */ 4048 FN_SEL_INT3_0, FN_SEL_INT3_1, 4049 /* SEL_INT2 [1] */ 4050 FN_SEL_INT2_0, FN_SEL_INT2_1, 4051 /* SEL_INT1 [1] */ 4052 FN_SEL_INT1_0, FN_SEL_INT1_1, 4053 /* SEL_INT0 [1] */ 4054 FN_SEL_INT0_0, FN_SEL_INT0_1, 4055 /* SEL_IE [1] */ 4056 FN_SEL_IE_0, FN_SEL_IE_1, 4057 /* SEL_EXBUS2 [2] */ 4058 FN_SEL_EXBUS2_0, FN_SEL_EXBUS2_1, FN_SEL_EXBUS2_2, 0, 4059 /* SEL_EXBUS1 [1] */ 4060 FN_SEL_EXBUS1_0, FN_SEL_EXBUS1_1, 4061 /* SEL_EXBUS0 [2] */ 4062 FN_SEL_EXBUS0_0, FN_SEL_EXBUS0_1, FN_SEL_EXBUS0_2, 0 )) 4063 }, 4064 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xfffc0094, 32, 4065 GROUP(2, 2, 2, 2, 1, 1, 1, 3, 1, -6, 4066 2, 1, 1, 2, 1, 2, 2), 4067 GROUP( 4068 /* SEL_TMU1 [2] */ 4069 FN_SEL_TMU1_0, FN_SEL_TMU1_1, FN_SEL_TMU1_2, 0, 4070 /* SEL_TMU0 [2] */ 4071 FN_SEL_TMU0_0, FN_SEL_TMU0_1, FN_SEL_TMU0_2, FN_SEL_TMU0_3, 4072 /* SEL_SCIF [2] */ 4073 FN_SEL_SCIF_0, FN_SEL_SCIF_1, FN_SEL_SCIF_2, FN_SEL_SCIF_3, 4074 /* SEL_CANCLK [2] */ 4075 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, 0, 4076 /* SEL_CAN0 [1] */ 4077 FN_SEL_CAN0_0, FN_SEL_CAN0_1, 4078 /* SEL_HSCIF1 [1] */ 4079 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, 4080 /* SEL_HSCIF0 [1] */ 4081 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, 4082 /* SEL_PWMFSW [3] */ 4083 FN_SEL_PWMFSW_0, FN_SEL_PWMFSW_1, FN_SEL_PWMFSW_2, 4084 FN_SEL_PWMFSW_3, FN_SEL_PWMFSW_4, 0, 0, 0, 4085 /* SEL_ADI [1] */ 4086 FN_SEL_ADI_0, FN_SEL_ADI_1, 4087 /* [6] RESERVED */ 4088 /* SEL_GPS [2] */ 4089 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3, 4090 /* SEL_SIM [1] */ 4091 FN_SEL_SIM_0, FN_SEL_SIM_1, 4092 /* SEL_HSPI2 [1] */ 4093 FN_SEL_HSPI2_0, FN_SEL_HSPI2_1, 4094 /* SEL_HSPI1 [2] */ 4095 FN_SEL_HSPI1_0, FN_SEL_HSPI1_1, FN_SEL_HSPI1_2, FN_SEL_HSPI1_3, 4096 /* SEL_I2C3 [1] */ 4097 FN_SEL_I2C3_0, FN_SEL_I2C3_1, 4098 /* SEL_I2C2 [2] */ 4099 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3, 4100 /* SEL_I2C1 [2] */ 4101 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3 )) 4102 }, 4103 { /* sentinel */ } 4104 }; 4105 4106 static const struct pinmux_bias_reg pinmux_bias_regs[] = { 4107 { PINMUX_BIAS_REG("PUPR0", 0xfffc0100, "N/A", 0) { 4108 [ 0] = RCAR_GP_PIN(0, 2), /* A0 */ 4109 [ 1] = RCAR_GP_PIN(5, 0), /* A1 */ 4110 [ 2] = RCAR_GP_PIN(5, 1), /* A2 */ 4111 [ 3] = RCAR_GP_PIN(5, 2), /* A3 */ 4112 [ 4] = RCAR_GP_PIN(5, 3), /* A4 */ 4113 [ 5] = RCAR_GP_PIN(5, 4), /* A5 */ 4114 [ 6] = RCAR_GP_PIN(5, 5), /* A6 */ 4115 [ 7] = RCAR_GP_PIN(5, 6), /* A7 */ 4116 [ 8] = RCAR_GP_PIN(5, 7), /* A8 */ 4117 [ 9] = RCAR_GP_PIN(5, 8), /* A9 */ 4118 [10] = RCAR_GP_PIN(5, 9), /* A10 */ 4119 [11] = RCAR_GP_PIN(5, 10), /* A11 */ 4120 [12] = RCAR_GP_PIN(5, 11), /* A12 */ 4121 [13] = RCAR_GP_PIN(5, 12), /* A13 */ 4122 [14] = RCAR_GP_PIN(5, 13), /* A14 */ 4123 [15] = RCAR_GP_PIN(5, 14), /* A15 */ 4124 [16] = RCAR_GP_PIN(5, 15), /* A16 */ 4125 [17] = RCAR_GP_PIN(0, 3), /* A17 */ 4126 [18] = RCAR_GP_PIN(0, 4), /* A18 */ 4127 [19] = RCAR_GP_PIN(0, 5), /* A19 */ 4128 [20] = RCAR_GP_PIN(0, 6), /* A20 */ 4129 [21] = RCAR_GP_PIN(0, 7), /* A21 */ 4130 [22] = RCAR_GP_PIN(0, 8), /* A22 */ 4131 [23] = RCAR_GP_PIN(0, 9), /* A23 */ 4132 [24] = RCAR_GP_PIN(0, 10), /* A24 */ 4133 [25] = RCAR_GP_PIN(0, 11), /* A25 */ 4134 [26] = RCAR_GP_PIN(0, 15), /* EX_CS0# */ 4135 [27] = RCAR_GP_PIN(0, 16), /* EX_CS1# */ 4136 [28] = RCAR_GP_PIN(0, 17), /* EX_CS2# */ 4137 [29] = RCAR_GP_PIN(0, 18), /* EX_CS3# */ 4138 [30] = RCAR_GP_PIN(0, 19), /* EX_CS4# */ 4139 [31] = RCAR_GP_PIN(0, 20), /* EX_CS5# */ 4140 } }, 4141 { PINMUX_BIAS_REG("PUPR1", 0xfffc0104, "N/A", 0) { 4142 [ 0] = PIN_PRESETOUT_N, /* PRESETOUT# */ 4143 [ 1] = RCAR_GP_PIN(0, 21), /* BS# */ 4144 [ 2] = RCAR_GP_PIN(0, 22), /* RD/WR# */ 4145 [ 3] = RCAR_GP_PIN(5, 17), /* WE0# */ 4146 [ 4] = RCAR_GP_PIN(5, 18), /* WE1# */ 4147 [ 5] = RCAR_GP_PIN(5, 19), /* EX_WAIT0 */ 4148 [ 6] = RCAR_GP_PIN(0, 0), /* AVS1 */ 4149 [ 7] = RCAR_GP_PIN(0, 1), /* AVS2 */ 4150 [ 8] = SH_PFC_PIN_NONE, 4151 [ 9] = SH_PFC_PIN_NONE, 4152 [10] = PIN_TRST_N, /* TRST# */ 4153 [11] = PIN_TCK, /* TCK */ 4154 [12] = PIN_TMS, /* TMS */ 4155 [13] = PIN_TDI, /* TDI */ 4156 [14] = PIN_TDO, /* TDO */ 4157 [15] = PIN_ASEBRK_N_ACK, /* ASEBRK#/ACK */ 4158 [16] = PIN_D0, /* D0 */ 4159 [17] = PIN_D1, /* D1 */ 4160 [18] = PIN_D2, /* D2 */ 4161 [19] = PIN_D3, /* D3 */ 4162 [20] = PIN_D4, /* D4 */ 4163 [21] = PIN_D5, /* D5 */ 4164 [22] = PIN_D6, /* D6 */ 4165 [23] = PIN_D7, /* D7 */ 4166 [24] = PIN_D8, /* D8 */ 4167 [25] = PIN_D9, /* D9 */ 4168 [26] = PIN_D10, /* D10 */ 4169 [27] = PIN_D11, /* D11 */ 4170 [28] = PIN_D12, /* D12 */ 4171 [29] = PIN_D13, /* D13 */ 4172 [30] = PIN_D14, /* D14 */ 4173 [31] = PIN_D15, /* D15 */ 4174 } }, 4175 { PINMUX_BIAS_REG("PUPR2", 0xfffc0108, "N/A", 0) { 4176 [ 0] = RCAR_GP_PIN(0, 23), /* DU0_DR0 */ 4177 [ 1] = RCAR_GP_PIN(0, 24), /* DU0_DR1 */ 4178 [ 2] = RCAR_GP_PIN(5, 23), /* DU0_DR2 */ 4179 [ 3] = RCAR_GP_PIN(5, 24), /* DU0_DR3 */ 4180 [ 4] = RCAR_GP_PIN(5, 25), /* DU0_DR4 */ 4181 [ 5] = RCAR_GP_PIN(5, 26), /* DU0_DR5 */ 4182 [ 6] = RCAR_GP_PIN(5, 27), /* DU0_DR6 */ 4183 [ 7] = RCAR_GP_PIN(5, 28), /* DU0_DR7 */ 4184 [ 8] = RCAR_GP_PIN(0, 25), /* DU0_DG0 */ 4185 [ 9] = RCAR_GP_PIN(0, 26), /* DU0_DG1 */ 4186 [10] = RCAR_GP_PIN(5, 29), /* DU0_DG2 */ 4187 [11] = RCAR_GP_PIN(5, 30), /* DU0_DG3 */ 4188 [12] = RCAR_GP_PIN(5, 31), /* DU0_DG4 */ 4189 [13] = RCAR_GP_PIN(6, 0), /* DU0_DG5 */ 4190 [14] = RCAR_GP_PIN(6, 1), /* DU0_DG6 */ 4191 [15] = RCAR_GP_PIN(6, 2), /* DU0_DG7 */ 4192 [16] = RCAR_GP_PIN(0, 27), /* DU0_DB0 */ 4193 [17] = RCAR_GP_PIN(0, 28), /* DU0_DB1 */ 4194 [18] = RCAR_GP_PIN(6, 3), /* DU0_DB2 */ 4195 [19] = RCAR_GP_PIN(6, 4), /* DU0_DB3 */ 4196 [20] = RCAR_GP_PIN(6, 5), /* DU0_DB4 */ 4197 [21] = RCAR_GP_PIN(6, 6), /* DU0_DB5 */ 4198 [22] = RCAR_GP_PIN(6, 7), /* DU0_DB6 */ 4199 [23] = RCAR_GP_PIN(6, 8), /* DU0_DB7 */ 4200 [24] = RCAR_GP_PIN(0, 29), /* DU0_DOTCLKIN */ 4201 [25] = RCAR_GP_PIN(5, 20), /* DU0_DOTCLKOUT0 */ 4202 [26] = RCAR_GP_PIN(5, 21), /* DU0_HSYNC */ 4203 [27] = RCAR_GP_PIN(5, 22), /* DU0_VSYNC */ 4204 [28] = RCAR_GP_PIN(0, 31), /* DU0_EXODDF */ 4205 [29] = RCAR_GP_PIN(1, 0), /* DU0_DISP */ 4206 [30] = RCAR_GP_PIN(1, 1), /* DU0_CDE */ 4207 [31] = RCAR_GP_PIN(0, 30), /* DU0_DOTCLKOUT1 */ 4208 } }, 4209 { PINMUX_BIAS_REG("PUPR3", 0xfffc010c, "N/A", 0) { 4210 [ 0] = RCAR_GP_PIN(1, 2), /* DU1_DR0 */ 4211 [ 1] = RCAR_GP_PIN(1, 3), /* DU1_DR1 */ 4212 [ 2] = RCAR_GP_PIN(1, 4), /* DU1_DR2 */ 4213 [ 3] = RCAR_GP_PIN(1, 5), /* DU1_DR3 */ 4214 [ 4] = RCAR_GP_PIN(1, 6), /* DU1_DR4 */ 4215 [ 5] = RCAR_GP_PIN(1, 7), /* DU1_DR5 */ 4216 [ 6] = RCAR_GP_PIN(1, 8), /* DU1_DR6 */ 4217 [ 7] = RCAR_GP_PIN(1, 9), /* DU1_DR7 */ 4218 [ 8] = RCAR_GP_PIN(1, 10), /* DU1_DG0 */ 4219 [ 9] = RCAR_GP_PIN(1, 11), /* DU1_DG1 */ 4220 [10] = RCAR_GP_PIN(1, 12), /* DU1_DG2 */ 4221 [11] = RCAR_GP_PIN(1, 13), /* DU1_DG3 */ 4222 [12] = RCAR_GP_PIN(1, 14), /* DU1_DG4 */ 4223 [13] = RCAR_GP_PIN(1, 15), /* DU1_DG5 */ 4224 [14] = RCAR_GP_PIN(1, 16), /* DU1_DG6 */ 4225 [15] = RCAR_GP_PIN(1, 17), /* DU1_DG7 */ 4226 [16] = RCAR_GP_PIN(1, 18), /* DU1_DB0 */ 4227 [17] = RCAR_GP_PIN(1, 19), /* DU1_DB1 */ 4228 [18] = RCAR_GP_PIN(1, 20), /* DU1_DB2 */ 4229 [19] = RCAR_GP_PIN(1, 21), /* DU1_DB3 */ 4230 [20] = RCAR_GP_PIN(1, 22), /* DU1_DB4 */ 4231 [21] = RCAR_GP_PIN(1, 23), /* DU1_DB5 */ 4232 [22] = RCAR_GP_PIN(1, 24), /* DU1_DB6 */ 4233 [23] = RCAR_GP_PIN(1, 25), /* DU1_DB7 */ 4234 [24] = RCAR_GP_PIN(1, 26), /* DU1_DOTCLKIN */ 4235 [25] = RCAR_GP_PIN(1, 27), /* DU1_DOTCLKOUT */ 4236 [26] = RCAR_GP_PIN(1, 28), /* DU1_HSYNC */ 4237 [27] = RCAR_GP_PIN(1, 29), /* DU1_VSYNC */ 4238 [28] = RCAR_GP_PIN(1, 30), /* DU1_EXODDF */ 4239 [29] = RCAR_GP_PIN(1, 31), /* DU1_DISP */ 4240 [30] = RCAR_GP_PIN(2, 0), /* DU1_CDE */ 4241 [31] = SH_PFC_PIN_NONE, 4242 } }, 4243 { PINMUX_BIAS_REG("PUPR4", 0xfffc0110, "N/A", 0) { 4244 [ 0] = RCAR_GP_PIN(2, 30), /* VI1_CLK */ 4245 [ 1] = SH_PFC_PIN_NONE, 4246 [ 2] = SH_PFC_PIN_NONE, 4247 [ 3] = RCAR_GP_PIN(2, 31), /* VI1_HSYNC# */ 4248 [ 4] = RCAR_GP_PIN(3, 0), /* VI1_VSYNC# */ 4249 [ 5] = RCAR_GP_PIN(3, 1), /* VI1_DATA0 */ 4250 [ 6] = RCAR_GP_PIN(3, 2), /* VI1_DATA1 */ 4251 [ 7] = RCAR_GP_PIN(3, 3), /* VI1_DATA2 */ 4252 [ 8] = RCAR_GP_PIN(3, 4), /* VI1_DATA3 */ 4253 [ 9] = RCAR_GP_PIN(3, 5), /* VI1_DATA4 */ 4254 [10] = RCAR_GP_PIN(3, 6), /* VI1_DATA5 */ 4255 [11] = RCAR_GP_PIN(3, 7), /* VI1_DATA6 */ 4256 [12] = RCAR_GP_PIN(3, 8), /* VI1_DATA7 */ 4257 [13] = RCAR_GP_PIN(3, 9), /* VI1_G0 */ 4258 [14] = RCAR_GP_PIN(3, 10), /* VI1_G1 */ 4259 [15] = RCAR_GP_PIN(3, 11), /* VI1_G2 */ 4260 [16] = RCAR_GP_PIN(3, 12), /* VI1_G3 */ 4261 [17] = RCAR_GP_PIN(3, 13), /* VI1_G4 */ 4262 [18] = RCAR_GP_PIN(3, 14), /* VI1_G5 */ 4263 [19] = RCAR_GP_PIN(3, 15), /* VI1_G6 */ 4264 [20] = RCAR_GP_PIN(3, 16), /* VI1_G7 */ 4265 [21] = SH_PFC_PIN_NONE, 4266 [22] = SH_PFC_PIN_NONE, 4267 [23] = SH_PFC_PIN_NONE, 4268 [24] = SH_PFC_PIN_NONE, 4269 [25] = SH_PFC_PIN_NONE, 4270 [26] = SH_PFC_PIN_NONE, 4271 [27] = SH_PFC_PIN_NONE, 4272 [28] = SH_PFC_PIN_NONE, 4273 [29] = SH_PFC_PIN_NONE, 4274 [30] = SH_PFC_PIN_NONE, 4275 [31] = SH_PFC_PIN_NONE, 4276 } }, 4277 { PINMUX_BIAS_REG("PUPR5", 0xfffc0114, "N/A", 0) { 4278 [ 0] = RCAR_GP_PIN(3, 30), /* SSI_SCK0129 */ 4279 [ 1] = RCAR_GP_PIN(3, 31), /* SSI_WS0129 */ 4280 [ 2] = RCAR_GP_PIN(4, 0), /* SSI_SDATA0 */ 4281 [ 3] = RCAR_GP_PIN(4, 1), /* SSI_SDATA1 */ 4282 [ 4] = RCAR_GP_PIN(4, 2), /* SSI_SDATA2 */ 4283 [ 5] = RCAR_GP_PIN(4, 3), /* SSI_SCK34 */ 4284 [ 6] = RCAR_GP_PIN(4, 4), /* SSI_WS34 */ 4285 [ 7] = RCAR_GP_PIN(4, 5), /* SSI_SDATA3 */ 4286 [ 8] = RCAR_GP_PIN(4, 6), /* SSI_SDATA4 */ 4287 [ 9] = RCAR_GP_PIN(4, 7), /* SSI_SCK5 */ 4288 [10] = RCAR_GP_PIN(4, 8), /* SSI_WS5 */ 4289 [11] = RCAR_GP_PIN(4, 9), /* SSI_SDATA5 */ 4290 [12] = RCAR_GP_PIN(4, 10), /* SSI_SCK6 */ 4291 [13] = RCAR_GP_PIN(4, 11), /* SSI_WS6 */ 4292 [14] = RCAR_GP_PIN(4, 12), /* SSI_SDATA6 */ 4293 [15] = RCAR_GP_PIN(4, 13), /* SSI_SCK78 */ 4294 [16] = RCAR_GP_PIN(4, 14), /* SSI_WS78 */ 4295 [17] = RCAR_GP_PIN(4, 15), /* SSI_SDATA7 */ 4296 [18] = RCAR_GP_PIN(4, 16), /* SSI_SDATA8 */ 4297 [19] = SH_PFC_PIN_NONE, 4298 [20] = RCAR_GP_PIN(3, 17), /* SD0_CLK */ 4299 [21] = RCAR_GP_PIN(3, 18), /* SD0_CMD */ 4300 [22] = RCAR_GP_PIN(3, 21), /* SD0_DAT0 */ 4301 [23] = RCAR_GP_PIN(3, 22), /* SD0_DAT1 */ 4302 [24] = RCAR_GP_PIN(3, 23), /* SD0_DAT2 */ 4303 [25] = RCAR_GP_PIN(3, 24), /* SD0_DAT3 */ 4304 [26] = RCAR_GP_PIN(3, 19), /* SD0_CD */ 4305 [27] = RCAR_GP_PIN(3, 20), /* SD0_WP */ 4306 [28] = RCAR_GP_PIN(3, 28), /* AUDIO_CLKA */ 4307 [29] = RCAR_GP_PIN(3, 29), /* AUDIO_CLKB */ 4308 [30] = SH_PFC_PIN_NONE, 4309 [31] = SH_PFC_PIN_NONE, 4310 } }, 4311 { PINMUX_BIAS_REG("PUPR6", 0xfffc0118, "N/A", 0) { 4312 [ 0] = RCAR_GP_PIN(4, 26), /* PENC0 */ 4313 [ 1] = RCAR_GP_PIN(4, 27), /* PENC1 */ 4314 [ 2] = RCAR_GP_PIN(4, 28), /* PENC2 */ 4315 [ 3] = SH_PFC_PIN_NONE, 4316 [ 4] = SH_PFC_PIN_NONE, 4317 [ 5] = RCAR_GP_PIN(4, 20), /* HTX0 */ 4318 [ 6] = RCAR_GP_PIN(4, 21), /* HRX0 */ 4319 [ 7] = RCAR_GP_PIN(4, 17), /* HSCK0 */ 4320 [ 8] = RCAR_GP_PIN(4, 18), /* HCTS0# */ 4321 [ 9] = RCAR_GP_PIN(4, 19), /* HRTS0# */ 4322 [10] = RCAR_GP_PIN(4, 22), /* HSPI_CLK0 */ 4323 [11] = RCAR_GP_PIN(4, 23), /* HSPI_CS0# */ 4324 [12] = RCAR_GP_PIN(4, 24), /* HSPI_TX0 */ 4325 [13] = RCAR_GP_PIN(4, 25), /* HSPI_RX0 */ 4326 [14] = RCAR_GP_PIN(4, 29), /* FMCLK */ 4327 [15] = RCAR_GP_PIN(4, 30), /* BPFCLK */ 4328 [16] = RCAR_GP_PIN(4, 31), /* FMIN */ 4329 [17] = RCAR_GP_PIN(0, 12), /* CLKOUT */ 4330 [18] = RCAR_GP_PIN(0, 13), /* CS0# */ 4331 [19] = RCAR_GP_PIN(0, 14), /* CS1#/A26 */ 4332 [20] = RCAR_GP_PIN(5, 16), /* RD# */ 4333 [21] = SH_PFC_PIN_NONE, 4334 [22] = SH_PFC_PIN_NONE, 4335 [23] = SH_PFC_PIN_NONE, 4336 [24] = SH_PFC_PIN_NONE, 4337 [25] = SH_PFC_PIN_NONE, 4338 [26] = SH_PFC_PIN_NONE, 4339 [27] = SH_PFC_PIN_NONE, 4340 [28] = SH_PFC_PIN_NONE, 4341 [29] = SH_PFC_PIN_NONE, 4342 [30] = SH_PFC_PIN_NONE, 4343 [31] = SH_PFC_PIN_NONE, 4344 } }, 4345 { /* sentinel */ } 4346 }; 4347 4348 static const struct sh_pfc_soc_operations r8a7779_pfc_ops = { 4349 .get_bias = rcar_pinmux_get_bias, 4350 .set_bias = rcar_pinmux_set_bias, 4351 }; 4352 4353 const struct sh_pfc_soc_info r8a7779_pinmux_info = { 4354 .name = "r8a7779_pfc", 4355 .ops = &r8a7779_pfc_ops, 4356 4357 .unlock_reg = 0xfffc0000, /* PMMR */ 4358 4359 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 4360 4361 .pins = pinmux_pins, 4362 .nr_pins = ARRAY_SIZE(pinmux_pins), 4363 .groups = pinmux_groups, 4364 .nr_groups = ARRAY_SIZE(pinmux_groups), 4365 .functions = pinmux_functions, 4366 .nr_functions = ARRAY_SIZE(pinmux_functions), 4367 4368 .cfg_regs = pinmux_config_regs, 4369 .bias_regs = pinmux_bias_regs, 4370 4371 .pinmux_data = pinmux_data, 4372 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 4373 }; 4374