1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2011-2015 Panasonic Corporation
4 * Copyright (C) 2015-2017 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
6 */
7
8 #include <linux/io.h>
9
10 #include "../init.h"
11 #include "sbc-regs.h"
12
13 #define SBCTRL0_ADMULTIPLX_PERI_VALUE 0x33120000
14 #define SBCTRL1_ADMULTIPLX_PERI_VALUE 0x03005500
15 #define SBCTRL2_ADMULTIPLX_PERI_VALUE 0x14000020
16
17 #define SBCTRL0_ADMULTIPLX_MEM_VALUE 0x33120000
18 #define SBCTRL1_ADMULTIPLX_MEM_VALUE 0x03005500
19 #define SBCTRL2_ADMULTIPLX_MEM_VALUE 0x14000010
20
21 /* slower but LED works */
22 #define SBCTRL0_SAVEPIN_PERI_VALUE 0x55450000
23 #define SBCTRL1_SAVEPIN_PERI_VALUE 0x07168d00
24 #define SBCTRL2_SAVEPIN_PERI_VALUE 0x34000009
25 #define SBCTRL4_SAVEPIN_PERI_VALUE 0x02110110
26
27 /* faster but LED does not work */
28 #define SBCTRL0_SAVEPIN_MEM_VALUE 0x55450000
29 #define SBCTRL1_SAVEPIN_MEM_VALUE 0x06057700
30 /* NOR flash needs more wait counts than SRAM */
31 #define SBCTRL2_SAVEPIN_MEM_VALUE 0x34000009
32 #define SBCTRL4_SAVEPIN_MEM_VALUE 0x02110210
33
__uniphier_sbc_init(int savepin)34 static void __uniphier_sbc_init(int savepin)
35 {
36 /*
37 * Only CS1 is connected to support card.
38 * BKSZ[1:0] should be set to "01".
39 */
40 if (savepin) {
41 writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10);
42 writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11);
43 writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12);
44 writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14);
45 } else {
46 writel(SBCTRL0_ADMULTIPLX_MEM_VALUE, SBCTRL10);
47 writel(SBCTRL1_ADMULTIPLX_MEM_VALUE, SBCTRL11);
48 writel(SBCTRL2_ADMULTIPLX_MEM_VALUE, SBCTRL12);
49 }
50
51 if (boot_is_swapped()) {
52 /*
53 * Boot Swap On: boot from external NOR/SRAM
54 * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff.
55 *
56 * 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank
57 * 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals
58 */
59 writel(0x0000bc01, SBBASE0);
60 } else {
61 /*
62 * Boot Swap Off: boot from mask ROM
63 * 0x40000000-0x41ffffff: mask ROM
64 * 0x42000000-0x43efffff: memory bank (31MB)
65 * 0x43f00000-0x43ffffff: peripherals (1MB)
66 */
67 writel(0x0000be01, SBBASE0); /* dummy */
68 writel(0x0200be01, SBBASE1);
69 }
70 }
71
uniphier_sbc_init_admulti(void)72 void uniphier_sbc_init_admulti(void)
73 {
74 __uniphier_sbc_init(0);
75 }
76
uniphier_sbc_init_savepin(void)77 void uniphier_sbc_init_savepin(void)
78 {
79 __uniphier_sbc_init(1);
80 }
81