xref: /openbmc/qemu/tests/avocado/riscv_opensbi.py (revision 11b937b6)
1# OpenSBI boot test for RISC-V machines
2#
3# Copyright (c) 2022, Ventana Micro
4#
5# This work is licensed under the terms of the GNU GPL, version 2 or
6# later.  See the COPYING file in the top-level directory.
7
8from avocado_qemu import QemuSystemTest
9from avocado_qemu import wait_for_console_pattern
10
11class RiscvOpenSBI(QemuSystemTest):
12    """
13    :avocado: tags=accel:tcg
14    """
15    timeout = 5
16
17    def boot_opensbi(self):
18        self.vm.set_console()
19        self.vm.launch()
20        wait_for_console_pattern(self, 'Platform Name')
21        wait_for_console_pattern(self, 'Boot HART MEDELEG')
22
23    def test_riscv32_spike(self):
24        """
25        :avocado: tags=arch:riscv32
26        :avocado: tags=machine:spike
27        """
28        self.boot_opensbi()
29
30    def test_riscv64_spike(self):
31        """
32        :avocado: tags=arch:riscv64
33        :avocado: tags=machine:spike
34        """
35        self.boot_opensbi()
36
37    def test_riscv32_sifive_u(self):
38        """
39        :avocado: tags=arch:riscv32
40        :avocado: tags=machine:sifive_u
41        """
42        self.boot_opensbi()
43
44    def test_riscv64_sifive_u(self):
45        """
46        :avocado: tags=arch:riscv64
47        :avocado: tags=machine:sifive_u
48        """
49        self.boot_opensbi()
50
51    def test_riscv32_virt(self):
52        """
53        :avocado: tags=arch:riscv32
54        :avocado: tags=machine:virt
55        """
56        self.boot_opensbi()
57
58    def test_riscv64_virt(self):
59        """
60        :avocado: tags=arch:riscv64
61        :avocado: tags=machine:virt
62        """
63        self.boot_opensbi()
64