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Searched defs:Rd (Results 1 – 5 of 5) sorted by relevance

/openbmc/qemu/target/avr/
H A Dtranslate.c296 TCGv Rd = cpu_r[a->rd]; in trans_ADD() local
319 TCGv Rd = cpu_r[a->rd]; in trans_ADC() local
381 TCGv Rd = cpu_r[a->rd]; in trans_SUB() local
406 TCGv Rd = cpu_r[a->rd]; in trans_SUBI() local
429 TCGv Rd = cpu_r[a->rd]; in trans_SBC() local
459 TCGv Rd = cpu_r[a->rd]; in trans_SBCI() local
528 TCGv Rd = cpu_r[a->rd]; in trans_AND() local
550 TCGv Rd = cpu_r[a->rd]; in trans_ANDI() local
568 TCGv Rd = cpu_r[a->rd]; in trans_OR() local
1979 TCGv Rd = cpu_r[0]; in trans_LPM1() local
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/openbmc/linux/arch/arm64/net/
H A Dbpf_jit.h155 #define A64_ADDSUB_IMM(sf, Rd, Rn, imm12, type) \ argument
161 #define A64_ADDS_I(sf, Rd, Rn, imm12) \ argument
163 #define A64_SUBS_I(sf, Rd, Rn, imm12) \ argument
170 #define A64_MOV(sf, Rd, Rn) A64_ADD_I(sf, Rd, Rn, 0) argument
182 #define A64_LSL(sf, Rd, Rn, shift) ({ \ argument
201 #define A64_MOVEW(sf, Rd, imm16, shift, type) \ argument
212 #define A64_ADDSUB_SREG(sf, Rd, Rn, Rm, type) \ argument
253 #define A64_LOGIC_SREG(sf, Rd, Rn, Rm, type) \ argument
264 #define A64_MVN(sf, Rd, Rm) \ argument
268 #define A64_LOGIC_IMM(sf, Rd, Rn, imm, type) ({ \ argument
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/openbmc/qemu/target/hexagon/
H A Darch.c238 int arch_sf_recip_common(float32 *Rs, float32 *Rt, float32 *Rd, int *adjust, in arch_sf_recip_common()
334 int arch_sf_invsqrt_common(float32 *Rs, float32 *Rd, int *adjust, in arch_sf_invsqrt_common()
/openbmc/linux/arch/arm64/lib/
H A Dinsn.c1414 enum aarch64_insn_register Rd, in aarch64_insn_gen_logical_immediate()
1445 enum aarch64_insn_register Rd, in aarch64_insn_gen_extr()
/openbmc/qemu/target/mips/tcg/
H A Dmsa_helper.c5887 #define Rd(pwr, i) (pwr->d[i]) macro