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Searched defs:Rd (Results 1 – 5 of 5) sorted by relevance

/openbmc/qemu/target/avr/
H A Dtranslate.c212 static void gen_add_CHf(TCGv R, TCGv Rd, TCGv Rr) in gen_add_CHf()
229 static void gen_add_Vf(TCGv R, TCGv Rd, TCGv Rr) in gen_add_Vf()
243 static void gen_sub_CHf(TCGv R, TCGv Rd, TCGv Rr) in gen_sub_CHf()
260 static void gen_sub_Vf(TCGv R, TCGv Rd, TCGv Rr) in gen_sub_Vf()
295 TCGv Rd = cpu_r[a->rd]; in trans_ADD() local
318 TCGv Rd = cpu_r[a->rd]; in trans_ADC() local
353 TCGv Rd = tcg_temp_new_i32(); in trans_ADIW() local
380 TCGv Rd = cpu_r[a->rd]; in trans_SUB() local
405 TCGv Rd = cpu_r[a->rd]; in trans_SUBI() local
428 TCGv Rd = cpu_r[a->rd]; in trans_SBC() local
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/openbmc/linux/arch/arm64/net/
H A Dbpf_jit.h155 #define A64_ADDSUB_IMM(sf, Rd, Rn, imm12, type) \ argument
159 #define A64_ADD_I(sf, Rd, Rn, imm12) A64_ADDSUB_IMM(sf, Rd, Rn, imm12, ADD) argument
160 #define A64_SUB_I(sf, Rd, Rn, imm12) A64_ADDSUB_IMM(sf, Rd, Rn, imm12, SUB) argument
161 #define A64_ADDS_I(sf, Rd, Rn, imm12) \ argument
163 #define A64_SUBS_I(sf, Rd, Rn, imm12) \ argument
170 #define A64_MOV(sf, Rd, Rn) A64_ADD_I(sf, Rd, Rn, 0) argument
173 #define A64_BITFIELD(sf, Rd, Rn, immr, imms, type) \ argument
177 #define A64_SBFM(sf, Rd, Rn, ir, is) A64_BITFIELD(sf, Rd, Rn, ir, is, SIGNED) argument
179 #define A64_UBFM(sf, Rd, Rn, ir, is) A64_BITFIELD(sf, Rd, Rn, ir, is, UNSIGNED) argument
182 #define A64_LSL(sf, Rd, Rn, shift) ({ \ argument
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/openbmc/qemu/target/hexagon/
H A Darch.c238 int arch_sf_recip_common(float32 *Rs, float32 *Rt, float32 *Rd, int *adjust, in arch_sf_recip_common()
334 int arch_sf_invsqrt_common(float32 *Rs, float32 *Rd, int *adjust, in arch_sf_invsqrt_common()
/openbmc/linux/arch/arm64/lib/
H A Dinsn.c1414 enum aarch64_insn_register Rd, in aarch64_insn_gen_logical_immediate()
1445 enum aarch64_insn_register Rd, in aarch64_insn_gen_extr()
/openbmc/qemu/target/mips/tcg/
H A Dmsa_helper.c5887 #define Rd(pwr, i) (pwr->d[i]) macro