1 // SPDX-License-Identifier: GPL-2.0
2 // CAN bus driver for Bosch M_CAN controller
3 // Copyright (C) 2014 Freescale Semiconductor, Inc.
4 // Dong Aisheng <b29396@freescale.com>
5 // Copyright (C) 2018-19 Texas Instruments Incorporated - http://www.ti.com/
6
7 /* Bosch M_CAN user manual can be obtained from:
8 * https://github.com/linux-can/can-doc/tree/master/m_can
9 */
10
11 #include <linux/bitfield.h>
12 #include <linux/can/dev.h>
13 #include <linux/ethtool.h>
14 #include <linux/hrtimer.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <linux/iopoll.h>
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/netdevice.h>
21 #include <linux/of.h>
22 #include <linux/phy/phy.h>
23 #include <linux/pinctrl/consumer.h>
24 #include <linux/platform_device.h>
25 #include <linux/pm_runtime.h>
26
27 #include "m_can.h"
28
29 /* registers definition */
30 enum m_can_reg {
31 M_CAN_CREL = 0x0,
32 M_CAN_ENDN = 0x4,
33 M_CAN_CUST = 0x8,
34 M_CAN_DBTP = 0xc,
35 M_CAN_TEST = 0x10,
36 M_CAN_RWD = 0x14,
37 M_CAN_CCCR = 0x18,
38 M_CAN_NBTP = 0x1c,
39 M_CAN_TSCC = 0x20,
40 M_CAN_TSCV = 0x24,
41 M_CAN_TOCC = 0x28,
42 M_CAN_TOCV = 0x2c,
43 M_CAN_ECR = 0x40,
44 M_CAN_PSR = 0x44,
45 /* TDCR Register only available for version >=3.1.x */
46 M_CAN_TDCR = 0x48,
47 M_CAN_IR = 0x50,
48 M_CAN_IE = 0x54,
49 M_CAN_ILS = 0x58,
50 M_CAN_ILE = 0x5c,
51 M_CAN_GFC = 0x80,
52 M_CAN_SIDFC = 0x84,
53 M_CAN_XIDFC = 0x88,
54 M_CAN_XIDAM = 0x90,
55 M_CAN_HPMS = 0x94,
56 M_CAN_NDAT1 = 0x98,
57 M_CAN_NDAT2 = 0x9c,
58 M_CAN_RXF0C = 0xa0,
59 M_CAN_RXF0S = 0xa4,
60 M_CAN_RXF0A = 0xa8,
61 M_CAN_RXBC = 0xac,
62 M_CAN_RXF1C = 0xb0,
63 M_CAN_RXF1S = 0xb4,
64 M_CAN_RXF1A = 0xb8,
65 M_CAN_RXESC = 0xbc,
66 M_CAN_TXBC = 0xc0,
67 M_CAN_TXFQS = 0xc4,
68 M_CAN_TXESC = 0xc8,
69 M_CAN_TXBRP = 0xcc,
70 M_CAN_TXBAR = 0xd0,
71 M_CAN_TXBCR = 0xd4,
72 M_CAN_TXBTO = 0xd8,
73 M_CAN_TXBCF = 0xdc,
74 M_CAN_TXBTIE = 0xe0,
75 M_CAN_TXBCIE = 0xe4,
76 M_CAN_TXEFC = 0xf0,
77 M_CAN_TXEFS = 0xf4,
78 M_CAN_TXEFA = 0xf8,
79 };
80
81 /* message ram configuration data length */
82 #define MRAM_CFG_LEN 8
83
84 /* Core Release Register (CREL) */
85 #define CREL_REL_MASK GENMASK(31, 28)
86 #define CREL_STEP_MASK GENMASK(27, 24)
87 #define CREL_SUBSTEP_MASK GENMASK(23, 20)
88
89 /* Data Bit Timing & Prescaler Register (DBTP) */
90 #define DBTP_TDC BIT(23)
91 #define DBTP_DBRP_MASK GENMASK(20, 16)
92 #define DBTP_DTSEG1_MASK GENMASK(12, 8)
93 #define DBTP_DTSEG2_MASK GENMASK(7, 4)
94 #define DBTP_DSJW_MASK GENMASK(3, 0)
95
96 /* Transmitter Delay Compensation Register (TDCR) */
97 #define TDCR_TDCO_MASK GENMASK(14, 8)
98 #define TDCR_TDCF_MASK GENMASK(6, 0)
99
100 /* Test Register (TEST) */
101 #define TEST_LBCK BIT(4)
102
103 /* CC Control Register (CCCR) */
104 #define CCCR_TXP BIT(14)
105 #define CCCR_TEST BIT(7)
106 #define CCCR_DAR BIT(6)
107 #define CCCR_MON BIT(5)
108 #define CCCR_CSR BIT(4)
109 #define CCCR_CSA BIT(3)
110 #define CCCR_ASM BIT(2)
111 #define CCCR_CCE BIT(1)
112 #define CCCR_INIT BIT(0)
113 /* for version 3.0.x */
114 #define CCCR_CMR_MASK GENMASK(11, 10)
115 #define CCCR_CMR_CANFD 0x1
116 #define CCCR_CMR_CANFD_BRS 0x2
117 #define CCCR_CMR_CAN 0x3
118 #define CCCR_CME_MASK GENMASK(9, 8)
119 #define CCCR_CME_CAN 0
120 #define CCCR_CME_CANFD 0x1
121 #define CCCR_CME_CANFD_BRS 0x2
122 /* for version >=3.1.x */
123 #define CCCR_EFBI BIT(13)
124 #define CCCR_PXHD BIT(12)
125 #define CCCR_BRSE BIT(9)
126 #define CCCR_FDOE BIT(8)
127 /* for version >=3.2.x */
128 #define CCCR_NISO BIT(15)
129 /* for version >=3.3.x */
130 #define CCCR_WMM BIT(11)
131 #define CCCR_UTSU BIT(10)
132
133 /* Nominal Bit Timing & Prescaler Register (NBTP) */
134 #define NBTP_NSJW_MASK GENMASK(31, 25)
135 #define NBTP_NBRP_MASK GENMASK(24, 16)
136 #define NBTP_NTSEG1_MASK GENMASK(15, 8)
137 #define NBTP_NTSEG2_MASK GENMASK(6, 0)
138
139 /* Timestamp Counter Configuration Register (TSCC) */
140 #define TSCC_TCP_MASK GENMASK(19, 16)
141 #define TSCC_TSS_MASK GENMASK(1, 0)
142 #define TSCC_TSS_DISABLE 0x0
143 #define TSCC_TSS_INTERNAL 0x1
144 #define TSCC_TSS_EXTERNAL 0x2
145
146 /* Timestamp Counter Value Register (TSCV) */
147 #define TSCV_TSC_MASK GENMASK(15, 0)
148
149 /* Error Counter Register (ECR) */
150 #define ECR_RP BIT(15)
151 #define ECR_REC_MASK GENMASK(14, 8)
152 #define ECR_TEC_MASK GENMASK(7, 0)
153
154 /* Protocol Status Register (PSR) */
155 #define PSR_BO BIT(7)
156 #define PSR_EW BIT(6)
157 #define PSR_EP BIT(5)
158 #define PSR_LEC_MASK GENMASK(2, 0)
159 #define PSR_DLEC_MASK GENMASK(10, 8)
160
161 /* Interrupt Register (IR) */
162 #define IR_ALL_INT 0xffffffff
163
164 /* Renamed bits for versions > 3.1.x */
165 #define IR_ARA BIT(29)
166 #define IR_PED BIT(28)
167 #define IR_PEA BIT(27)
168
169 /* Bits for version 3.0.x */
170 #define IR_STE BIT(31)
171 #define IR_FOE BIT(30)
172 #define IR_ACKE BIT(29)
173 #define IR_BE BIT(28)
174 #define IR_CRCE BIT(27)
175 #define IR_WDI BIT(26)
176 #define IR_BO BIT(25)
177 #define IR_EW BIT(24)
178 #define IR_EP BIT(23)
179 #define IR_ELO BIT(22)
180 #define IR_BEU BIT(21)
181 #define IR_BEC BIT(20)
182 #define IR_DRX BIT(19)
183 #define IR_TOO BIT(18)
184 #define IR_MRAF BIT(17)
185 #define IR_TSW BIT(16)
186 #define IR_TEFL BIT(15)
187 #define IR_TEFF BIT(14)
188 #define IR_TEFW BIT(13)
189 #define IR_TEFN BIT(12)
190 #define IR_TFE BIT(11)
191 #define IR_TCF BIT(10)
192 #define IR_TC BIT(9)
193 #define IR_HPM BIT(8)
194 #define IR_RF1L BIT(7)
195 #define IR_RF1F BIT(6)
196 #define IR_RF1W BIT(5)
197 #define IR_RF1N BIT(4)
198 #define IR_RF0L BIT(3)
199 #define IR_RF0F BIT(2)
200 #define IR_RF0W BIT(1)
201 #define IR_RF0N BIT(0)
202 #define IR_ERR_STATE (IR_BO | IR_EW | IR_EP)
203
204 /* Interrupts for version 3.0.x */
205 #define IR_ERR_LEC_30X (IR_STE | IR_FOE | IR_ACKE | IR_BE | IR_CRCE)
206 #define IR_ERR_BUS_30X (IR_ERR_LEC_30X | IR_WDI | IR_BEU | IR_BEC | \
207 IR_TOO | IR_MRAF | IR_TSW | IR_TEFL | IR_RF1L | \
208 IR_RF0L)
209 #define IR_ERR_ALL_30X (IR_ERR_STATE | IR_ERR_BUS_30X)
210
211 /* Interrupts for version >= 3.1.x */
212 #define IR_ERR_LEC_31X (IR_PED | IR_PEA)
213 #define IR_ERR_BUS_31X (IR_ERR_LEC_31X | IR_WDI | IR_BEU | IR_BEC | \
214 IR_TOO | IR_MRAF | IR_TSW | IR_TEFL | IR_RF1L | \
215 IR_RF0L)
216 #define IR_ERR_ALL_31X (IR_ERR_STATE | IR_ERR_BUS_31X)
217
218 /* Interrupt Line Select (ILS) */
219 #define ILS_ALL_INT0 0x0
220 #define ILS_ALL_INT1 0xFFFFFFFF
221
222 /* Interrupt Line Enable (ILE) */
223 #define ILE_EINT1 BIT(1)
224 #define ILE_EINT0 BIT(0)
225
226 /* Rx FIFO 0/1 Configuration (RXF0C/RXF1C) */
227 #define RXFC_FWM_MASK GENMASK(30, 24)
228 #define RXFC_FS_MASK GENMASK(22, 16)
229
230 /* Rx FIFO 0/1 Status (RXF0S/RXF1S) */
231 #define RXFS_RFL BIT(25)
232 #define RXFS_FF BIT(24)
233 #define RXFS_FPI_MASK GENMASK(21, 16)
234 #define RXFS_FGI_MASK GENMASK(13, 8)
235 #define RXFS_FFL_MASK GENMASK(6, 0)
236
237 /* Rx Buffer / FIFO Element Size Configuration (RXESC) */
238 #define RXESC_RBDS_MASK GENMASK(10, 8)
239 #define RXESC_F1DS_MASK GENMASK(6, 4)
240 #define RXESC_F0DS_MASK GENMASK(2, 0)
241 #define RXESC_64B 0x7
242
243 /* Tx Buffer Configuration (TXBC) */
244 #define TXBC_TFQS_MASK GENMASK(29, 24)
245 #define TXBC_NDTB_MASK GENMASK(21, 16)
246
247 /* Tx FIFO/Queue Status (TXFQS) */
248 #define TXFQS_TFQF BIT(21)
249 #define TXFQS_TFQPI_MASK GENMASK(20, 16)
250 #define TXFQS_TFGI_MASK GENMASK(12, 8)
251 #define TXFQS_TFFL_MASK GENMASK(5, 0)
252
253 /* Tx Buffer Element Size Configuration (TXESC) */
254 #define TXESC_TBDS_MASK GENMASK(2, 0)
255 #define TXESC_TBDS_64B 0x7
256
257 /* Tx Event FIFO Configuration (TXEFC) */
258 #define TXEFC_EFS_MASK GENMASK(21, 16)
259
260 /* Tx Event FIFO Status (TXEFS) */
261 #define TXEFS_TEFL BIT(25)
262 #define TXEFS_EFF BIT(24)
263 #define TXEFS_EFGI_MASK GENMASK(12, 8)
264 #define TXEFS_EFFL_MASK GENMASK(5, 0)
265
266 /* Tx Event FIFO Acknowledge (TXEFA) */
267 #define TXEFA_EFAI_MASK GENMASK(4, 0)
268
269 /* Message RAM Configuration (in bytes) */
270 #define SIDF_ELEMENT_SIZE 4
271 #define XIDF_ELEMENT_SIZE 8
272 #define RXF0_ELEMENT_SIZE 72
273 #define RXF1_ELEMENT_SIZE 72
274 #define RXB_ELEMENT_SIZE 72
275 #define TXE_ELEMENT_SIZE 8
276 #define TXB_ELEMENT_SIZE 72
277
278 /* Message RAM Elements */
279 #define M_CAN_FIFO_ID 0x0
280 #define M_CAN_FIFO_DLC 0x4
281 #define M_CAN_FIFO_DATA 0x8
282
283 /* Rx Buffer Element */
284 /* R0 */
285 #define RX_BUF_ESI BIT(31)
286 #define RX_BUF_XTD BIT(30)
287 #define RX_BUF_RTR BIT(29)
288 /* R1 */
289 #define RX_BUF_ANMF BIT(31)
290 #define RX_BUF_FDF BIT(21)
291 #define RX_BUF_BRS BIT(20)
292 #define RX_BUF_RXTS_MASK GENMASK(15, 0)
293
294 /* Tx Buffer Element */
295 /* T0 */
296 #define TX_BUF_ESI BIT(31)
297 #define TX_BUF_XTD BIT(30)
298 #define TX_BUF_RTR BIT(29)
299 /* T1 */
300 #define TX_BUF_EFC BIT(23)
301 #define TX_BUF_FDF BIT(21)
302 #define TX_BUF_BRS BIT(20)
303 #define TX_BUF_MM_MASK GENMASK(31, 24)
304 #define TX_BUF_DLC_MASK GENMASK(19, 16)
305
306 /* Tx event FIFO Element */
307 /* E1 */
308 #define TX_EVENT_MM_MASK GENMASK(31, 24)
309 #define TX_EVENT_TXTS_MASK GENMASK(15, 0)
310
311 /* Hrtimer polling interval */
312 #define HRTIMER_POLL_INTERVAL_MS 1
313
314 /* The ID and DLC registers are adjacent in M_CAN FIFO memory,
315 * and we can save a (potentially slow) bus round trip by combining
316 * reads and writes to them.
317 */
318 struct id_and_dlc {
319 u32 id;
320 u32 dlc;
321 };
322
m_can_read(struct m_can_classdev * cdev,enum m_can_reg reg)323 static inline u32 m_can_read(struct m_can_classdev *cdev, enum m_can_reg reg)
324 {
325 return cdev->ops->read_reg(cdev, reg);
326 }
327
m_can_write(struct m_can_classdev * cdev,enum m_can_reg reg,u32 val)328 static inline void m_can_write(struct m_can_classdev *cdev, enum m_can_reg reg,
329 u32 val)
330 {
331 cdev->ops->write_reg(cdev, reg, val);
332 }
333
334 static int
m_can_fifo_read(struct m_can_classdev * cdev,u32 fgi,unsigned int offset,void * val,size_t val_count)335 m_can_fifo_read(struct m_can_classdev *cdev,
336 u32 fgi, unsigned int offset, void *val, size_t val_count)
337 {
338 u32 addr_offset = cdev->mcfg[MRAM_RXF0].off + fgi * RXF0_ELEMENT_SIZE +
339 offset;
340
341 if (val_count == 0)
342 return 0;
343
344 return cdev->ops->read_fifo(cdev, addr_offset, val, val_count);
345 }
346
347 static int
m_can_fifo_write(struct m_can_classdev * cdev,u32 fpi,unsigned int offset,const void * val,size_t val_count)348 m_can_fifo_write(struct m_can_classdev *cdev,
349 u32 fpi, unsigned int offset, const void *val, size_t val_count)
350 {
351 u32 addr_offset = cdev->mcfg[MRAM_TXB].off + fpi * TXB_ELEMENT_SIZE +
352 offset;
353
354 if (val_count == 0)
355 return 0;
356
357 return cdev->ops->write_fifo(cdev, addr_offset, val, val_count);
358 }
359
m_can_fifo_write_no_off(struct m_can_classdev * cdev,u32 fpi,u32 val)360 static inline int m_can_fifo_write_no_off(struct m_can_classdev *cdev,
361 u32 fpi, u32 val)
362 {
363 return cdev->ops->write_fifo(cdev, fpi, &val, 1);
364 }
365
366 static int
m_can_txe_fifo_read(struct m_can_classdev * cdev,u32 fgi,u32 offset,u32 * val)367 m_can_txe_fifo_read(struct m_can_classdev *cdev, u32 fgi, u32 offset, u32 *val)
368 {
369 u32 addr_offset = cdev->mcfg[MRAM_TXE].off + fgi * TXE_ELEMENT_SIZE +
370 offset;
371
372 return cdev->ops->read_fifo(cdev, addr_offset, val, 1);
373 }
374
_m_can_tx_fifo_full(u32 txfqs)375 static inline bool _m_can_tx_fifo_full(u32 txfqs)
376 {
377 return !!(txfqs & TXFQS_TFQF);
378 }
379
m_can_tx_fifo_full(struct m_can_classdev * cdev)380 static inline bool m_can_tx_fifo_full(struct m_can_classdev *cdev)
381 {
382 return _m_can_tx_fifo_full(m_can_read(cdev, M_CAN_TXFQS));
383 }
384
m_can_config_endisable(struct m_can_classdev * cdev,bool enable)385 static void m_can_config_endisable(struct m_can_classdev *cdev, bool enable)
386 {
387 u32 cccr = m_can_read(cdev, M_CAN_CCCR);
388 u32 timeout = 10;
389 u32 val = 0;
390
391 /* Clear the Clock stop request if it was set */
392 if (cccr & CCCR_CSR)
393 cccr &= ~CCCR_CSR;
394
395 if (enable) {
396 /* enable m_can configuration */
397 m_can_write(cdev, M_CAN_CCCR, cccr | CCCR_INIT);
398 udelay(5);
399 /* CCCR.CCE can only be set/reset while CCCR.INIT = '1' */
400 m_can_write(cdev, M_CAN_CCCR, cccr | CCCR_INIT | CCCR_CCE);
401 } else {
402 m_can_write(cdev, M_CAN_CCCR, cccr & ~(CCCR_INIT | CCCR_CCE));
403 }
404
405 /* there's a delay for module initialization */
406 if (enable)
407 val = CCCR_INIT | CCCR_CCE;
408
409 while ((m_can_read(cdev, M_CAN_CCCR) & (CCCR_INIT | CCCR_CCE)) != val) {
410 if (timeout == 0) {
411 netdev_warn(cdev->net, "Failed to init module\n");
412 return;
413 }
414 timeout--;
415 udelay(1);
416 }
417 }
418
m_can_enable_all_interrupts(struct m_can_classdev * cdev)419 static inline void m_can_enable_all_interrupts(struct m_can_classdev *cdev)
420 {
421 if (!cdev->net->irq) {
422 dev_dbg(cdev->dev, "Start hrtimer\n");
423 hrtimer_start(&cdev->hrtimer,
424 ms_to_ktime(HRTIMER_POLL_INTERVAL_MS),
425 HRTIMER_MODE_REL_PINNED);
426 }
427
428 /* Only interrupt line 0 is used in this driver */
429 m_can_write(cdev, M_CAN_ILE, ILE_EINT0);
430 }
431
m_can_disable_all_interrupts(struct m_can_classdev * cdev)432 static inline void m_can_disable_all_interrupts(struct m_can_classdev *cdev)
433 {
434 m_can_write(cdev, M_CAN_ILE, 0x0);
435
436 if (!cdev->net->irq) {
437 dev_dbg(cdev->dev, "Stop hrtimer\n");
438 hrtimer_cancel(&cdev->hrtimer);
439 }
440 }
441
442 /* Retrieve internal timestamp counter from TSCV.TSC, and shift it to 32-bit
443 * width.
444 */
m_can_get_timestamp(struct m_can_classdev * cdev)445 static u32 m_can_get_timestamp(struct m_can_classdev *cdev)
446 {
447 u32 tscv;
448 u32 tsc;
449
450 tscv = m_can_read(cdev, M_CAN_TSCV);
451 tsc = FIELD_GET(TSCV_TSC_MASK, tscv);
452
453 return (tsc << 16);
454 }
455
m_can_clean(struct net_device * net)456 static void m_can_clean(struct net_device *net)
457 {
458 struct m_can_classdev *cdev = netdev_priv(net);
459
460 if (cdev->tx_skb) {
461 int putidx = 0;
462
463 net->stats.tx_errors++;
464 if (cdev->version > 30)
465 putidx = FIELD_GET(TXFQS_TFQPI_MASK,
466 m_can_read(cdev, M_CAN_TXFQS));
467
468 can_free_echo_skb(cdev->net, putidx, NULL);
469 cdev->tx_skb = NULL;
470 }
471 }
472
473 /* For peripherals, pass skb to rx-offload, which will push skb from
474 * napi. For non-peripherals, RX is done in napi already, so push
475 * directly. timestamp is used to ensure good skb ordering in
476 * rx-offload and is ignored for non-peripherals.
477 */
m_can_receive_skb(struct m_can_classdev * cdev,struct sk_buff * skb,u32 timestamp)478 static void m_can_receive_skb(struct m_can_classdev *cdev,
479 struct sk_buff *skb,
480 u32 timestamp)
481 {
482 if (cdev->is_peripheral) {
483 struct net_device_stats *stats = &cdev->net->stats;
484 int err;
485
486 err = can_rx_offload_queue_timestamp(&cdev->offload, skb,
487 timestamp);
488 if (err)
489 stats->rx_fifo_errors++;
490 } else {
491 netif_receive_skb(skb);
492 }
493 }
494
m_can_read_fifo(struct net_device * dev,u32 fgi)495 static int m_can_read_fifo(struct net_device *dev, u32 fgi)
496 {
497 struct net_device_stats *stats = &dev->stats;
498 struct m_can_classdev *cdev = netdev_priv(dev);
499 struct canfd_frame *cf;
500 struct sk_buff *skb;
501 struct id_and_dlc fifo_header;
502 u32 timestamp = 0;
503 int err;
504
505 err = m_can_fifo_read(cdev, fgi, M_CAN_FIFO_ID, &fifo_header, 2);
506 if (err)
507 goto out_fail;
508
509 if (fifo_header.dlc & RX_BUF_FDF)
510 skb = alloc_canfd_skb(dev, &cf);
511 else
512 skb = alloc_can_skb(dev, (struct can_frame **)&cf);
513 if (!skb) {
514 stats->rx_dropped++;
515 return 0;
516 }
517
518 if (fifo_header.dlc & RX_BUF_FDF)
519 cf->len = can_fd_dlc2len((fifo_header.dlc >> 16) & 0x0F);
520 else
521 cf->len = can_cc_dlc2len((fifo_header.dlc >> 16) & 0x0F);
522
523 if (fifo_header.id & RX_BUF_XTD)
524 cf->can_id = (fifo_header.id & CAN_EFF_MASK) | CAN_EFF_FLAG;
525 else
526 cf->can_id = (fifo_header.id >> 18) & CAN_SFF_MASK;
527
528 if (fifo_header.id & RX_BUF_ESI) {
529 cf->flags |= CANFD_ESI;
530 netdev_dbg(dev, "ESI Error\n");
531 }
532
533 if (!(fifo_header.dlc & RX_BUF_FDF) && (fifo_header.id & RX_BUF_RTR)) {
534 cf->can_id |= CAN_RTR_FLAG;
535 } else {
536 if (fifo_header.dlc & RX_BUF_BRS)
537 cf->flags |= CANFD_BRS;
538
539 err = m_can_fifo_read(cdev, fgi, M_CAN_FIFO_DATA,
540 cf->data, DIV_ROUND_UP(cf->len, 4));
541 if (err)
542 goto out_free_skb;
543
544 stats->rx_bytes += cf->len;
545 }
546 stats->rx_packets++;
547
548 timestamp = FIELD_GET(RX_BUF_RXTS_MASK, fifo_header.dlc) << 16;
549
550 m_can_receive_skb(cdev, skb, timestamp);
551
552 return 0;
553
554 out_free_skb:
555 kfree_skb(skb);
556 out_fail:
557 netdev_err(dev, "FIFO read returned %d\n", err);
558 return err;
559 }
560
m_can_do_rx_poll(struct net_device * dev,int quota)561 static int m_can_do_rx_poll(struct net_device *dev, int quota)
562 {
563 struct m_can_classdev *cdev = netdev_priv(dev);
564 u32 pkts = 0;
565 u32 rxfs;
566 u32 rx_count;
567 u32 fgi;
568 int ack_fgi = -1;
569 int i;
570 int err = 0;
571
572 rxfs = m_can_read(cdev, M_CAN_RXF0S);
573 if (!(rxfs & RXFS_FFL_MASK)) {
574 netdev_dbg(dev, "no messages in fifo0\n");
575 return 0;
576 }
577
578 rx_count = FIELD_GET(RXFS_FFL_MASK, rxfs);
579 fgi = FIELD_GET(RXFS_FGI_MASK, rxfs);
580
581 for (i = 0; i < rx_count && quota > 0; ++i) {
582 err = m_can_read_fifo(dev, fgi);
583 if (err)
584 break;
585
586 quota--;
587 pkts++;
588 ack_fgi = fgi;
589 fgi = (++fgi >= cdev->mcfg[MRAM_RXF0].num ? 0 : fgi);
590 }
591
592 if (ack_fgi != -1)
593 m_can_write(cdev, M_CAN_RXF0A, ack_fgi);
594
595 if (err)
596 return err;
597
598 return pkts;
599 }
600
m_can_handle_lost_msg(struct net_device * dev)601 static int m_can_handle_lost_msg(struct net_device *dev)
602 {
603 struct m_can_classdev *cdev = netdev_priv(dev);
604 struct net_device_stats *stats = &dev->stats;
605 struct sk_buff *skb;
606 struct can_frame *frame;
607 u32 timestamp = 0;
608
609 netdev_err(dev, "msg lost in rxf0\n");
610
611 stats->rx_errors++;
612 stats->rx_over_errors++;
613
614 skb = alloc_can_err_skb(dev, &frame);
615 if (unlikely(!skb))
616 return 0;
617
618 frame->can_id |= CAN_ERR_CRTL;
619 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
620
621 if (cdev->is_peripheral)
622 timestamp = m_can_get_timestamp(cdev);
623
624 m_can_receive_skb(cdev, skb, timestamp);
625
626 return 1;
627 }
628
m_can_handle_lec_err(struct net_device * dev,enum m_can_lec_type lec_type)629 static int m_can_handle_lec_err(struct net_device *dev,
630 enum m_can_lec_type lec_type)
631 {
632 struct m_can_classdev *cdev = netdev_priv(dev);
633 struct net_device_stats *stats = &dev->stats;
634 struct can_frame *cf;
635 struct sk_buff *skb;
636 u32 timestamp = 0;
637
638 cdev->can.can_stats.bus_error++;
639
640 /* propagate the error condition to the CAN stack */
641 skb = alloc_can_err_skb(dev, &cf);
642
643 /* check for 'last error code' which tells us the
644 * type of the last error to occur on the CAN bus
645 */
646 if (likely(skb))
647 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
648
649 switch (lec_type) {
650 case LEC_STUFF_ERROR:
651 netdev_dbg(dev, "stuff error\n");
652 stats->rx_errors++;
653 if (likely(skb))
654 cf->data[2] |= CAN_ERR_PROT_STUFF;
655 break;
656 case LEC_FORM_ERROR:
657 netdev_dbg(dev, "form error\n");
658 stats->rx_errors++;
659 if (likely(skb))
660 cf->data[2] |= CAN_ERR_PROT_FORM;
661 break;
662 case LEC_ACK_ERROR:
663 netdev_dbg(dev, "ack error\n");
664 stats->tx_errors++;
665 if (likely(skb))
666 cf->data[3] = CAN_ERR_PROT_LOC_ACK;
667 break;
668 case LEC_BIT1_ERROR:
669 netdev_dbg(dev, "bit1 error\n");
670 stats->tx_errors++;
671 if (likely(skb))
672 cf->data[2] |= CAN_ERR_PROT_BIT1;
673 break;
674 case LEC_BIT0_ERROR:
675 netdev_dbg(dev, "bit0 error\n");
676 stats->tx_errors++;
677 if (likely(skb))
678 cf->data[2] |= CAN_ERR_PROT_BIT0;
679 break;
680 case LEC_CRC_ERROR:
681 netdev_dbg(dev, "CRC error\n");
682 stats->rx_errors++;
683 if (likely(skb))
684 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
685 break;
686 default:
687 break;
688 }
689
690 if (unlikely(!skb))
691 return 0;
692
693 if (cdev->is_peripheral)
694 timestamp = m_can_get_timestamp(cdev);
695
696 m_can_receive_skb(cdev, skb, timestamp);
697
698 return 1;
699 }
700
__m_can_get_berr_counter(const struct net_device * dev,struct can_berr_counter * bec)701 static int __m_can_get_berr_counter(const struct net_device *dev,
702 struct can_berr_counter *bec)
703 {
704 struct m_can_classdev *cdev = netdev_priv(dev);
705 unsigned int ecr;
706
707 ecr = m_can_read(cdev, M_CAN_ECR);
708 bec->rxerr = FIELD_GET(ECR_REC_MASK, ecr);
709 bec->txerr = FIELD_GET(ECR_TEC_MASK, ecr);
710
711 return 0;
712 }
713
m_can_clk_start(struct m_can_classdev * cdev)714 static int m_can_clk_start(struct m_can_classdev *cdev)
715 {
716 if (cdev->pm_clock_support == 0)
717 return 0;
718
719 return pm_runtime_resume_and_get(cdev->dev);
720 }
721
m_can_clk_stop(struct m_can_classdev * cdev)722 static void m_can_clk_stop(struct m_can_classdev *cdev)
723 {
724 if (cdev->pm_clock_support)
725 pm_runtime_put_sync(cdev->dev);
726 }
727
m_can_get_berr_counter(const struct net_device * dev,struct can_berr_counter * bec)728 static int m_can_get_berr_counter(const struct net_device *dev,
729 struct can_berr_counter *bec)
730 {
731 struct m_can_classdev *cdev = netdev_priv(dev);
732 int err;
733
734 err = m_can_clk_start(cdev);
735 if (err)
736 return err;
737
738 __m_can_get_berr_counter(dev, bec);
739
740 m_can_clk_stop(cdev);
741
742 return 0;
743 }
744
m_can_handle_state_change(struct net_device * dev,enum can_state new_state)745 static int m_can_handle_state_change(struct net_device *dev,
746 enum can_state new_state)
747 {
748 struct m_can_classdev *cdev = netdev_priv(dev);
749 struct can_frame *cf;
750 struct sk_buff *skb;
751 struct can_berr_counter bec;
752 unsigned int ecr;
753 u32 timestamp = 0;
754
755 switch (new_state) {
756 case CAN_STATE_ERROR_WARNING:
757 /* error warning state */
758 cdev->can.can_stats.error_warning++;
759 cdev->can.state = CAN_STATE_ERROR_WARNING;
760 break;
761 case CAN_STATE_ERROR_PASSIVE:
762 /* error passive state */
763 cdev->can.can_stats.error_passive++;
764 cdev->can.state = CAN_STATE_ERROR_PASSIVE;
765 break;
766 case CAN_STATE_BUS_OFF:
767 /* bus-off state */
768 cdev->can.state = CAN_STATE_BUS_OFF;
769 m_can_disable_all_interrupts(cdev);
770 cdev->can.can_stats.bus_off++;
771 can_bus_off(dev);
772 break;
773 default:
774 break;
775 }
776
777 /* propagate the error condition to the CAN stack */
778 skb = alloc_can_err_skb(dev, &cf);
779 if (unlikely(!skb))
780 return 0;
781
782 __m_can_get_berr_counter(dev, &bec);
783
784 switch (new_state) {
785 case CAN_STATE_ERROR_WARNING:
786 /* error warning state */
787 cf->can_id |= CAN_ERR_CRTL | CAN_ERR_CNT;
788 cf->data[1] = (bec.txerr > bec.rxerr) ?
789 CAN_ERR_CRTL_TX_WARNING :
790 CAN_ERR_CRTL_RX_WARNING;
791 cf->data[6] = bec.txerr;
792 cf->data[7] = bec.rxerr;
793 break;
794 case CAN_STATE_ERROR_PASSIVE:
795 /* error passive state */
796 cf->can_id |= CAN_ERR_CRTL | CAN_ERR_CNT;
797 ecr = m_can_read(cdev, M_CAN_ECR);
798 if (ecr & ECR_RP)
799 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
800 if (bec.txerr > 127)
801 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
802 cf->data[6] = bec.txerr;
803 cf->data[7] = bec.rxerr;
804 break;
805 case CAN_STATE_BUS_OFF:
806 /* bus-off state */
807 cf->can_id |= CAN_ERR_BUSOFF;
808 break;
809 default:
810 break;
811 }
812
813 if (cdev->is_peripheral)
814 timestamp = m_can_get_timestamp(cdev);
815
816 m_can_receive_skb(cdev, skb, timestamp);
817
818 return 1;
819 }
820
m_can_handle_state_errors(struct net_device * dev,u32 psr)821 static int m_can_handle_state_errors(struct net_device *dev, u32 psr)
822 {
823 struct m_can_classdev *cdev = netdev_priv(dev);
824 int work_done = 0;
825
826 if (psr & PSR_EW && cdev->can.state != CAN_STATE_ERROR_WARNING) {
827 netdev_dbg(dev, "entered error warning state\n");
828 work_done += m_can_handle_state_change(dev,
829 CAN_STATE_ERROR_WARNING);
830 }
831
832 if (psr & PSR_EP && cdev->can.state != CAN_STATE_ERROR_PASSIVE) {
833 netdev_dbg(dev, "entered error passive state\n");
834 work_done += m_can_handle_state_change(dev,
835 CAN_STATE_ERROR_PASSIVE);
836 }
837
838 if (psr & PSR_BO && cdev->can.state != CAN_STATE_BUS_OFF) {
839 netdev_dbg(dev, "entered error bus off state\n");
840 work_done += m_can_handle_state_change(dev,
841 CAN_STATE_BUS_OFF);
842 }
843
844 return work_done;
845 }
846
m_can_handle_other_err(struct net_device * dev,u32 irqstatus)847 static void m_can_handle_other_err(struct net_device *dev, u32 irqstatus)
848 {
849 if (irqstatus & IR_WDI)
850 netdev_err(dev, "Message RAM Watchdog event due to missing READY\n");
851 if (irqstatus & IR_BEU)
852 netdev_err(dev, "Bit Error Uncorrected\n");
853 if (irqstatus & IR_BEC)
854 netdev_err(dev, "Bit Error Corrected\n");
855 if (irqstatus & IR_TOO)
856 netdev_err(dev, "Timeout reached\n");
857 if (irqstatus & IR_MRAF)
858 netdev_err(dev, "Message RAM access failure occurred\n");
859 }
860
is_lec_err(u8 lec)861 static inline bool is_lec_err(u8 lec)
862 {
863 return lec != LEC_NO_ERROR && lec != LEC_NO_CHANGE;
864 }
865
m_can_is_protocol_err(u32 irqstatus)866 static inline bool m_can_is_protocol_err(u32 irqstatus)
867 {
868 return irqstatus & IR_ERR_LEC_31X;
869 }
870
m_can_handle_protocol_error(struct net_device * dev,u32 irqstatus)871 static int m_can_handle_protocol_error(struct net_device *dev, u32 irqstatus)
872 {
873 struct net_device_stats *stats = &dev->stats;
874 struct m_can_classdev *cdev = netdev_priv(dev);
875 struct can_frame *cf;
876 struct sk_buff *skb;
877 u32 timestamp = 0;
878
879 /* propagate the error condition to the CAN stack */
880 skb = alloc_can_err_skb(dev, &cf);
881
882 /* update tx error stats since there is protocol error */
883 stats->tx_errors++;
884
885 /* update arbitration lost status */
886 if (cdev->version >= 31 && (irqstatus & IR_PEA)) {
887 netdev_dbg(dev, "Protocol error in Arbitration fail\n");
888 cdev->can.can_stats.arbitration_lost++;
889 if (skb) {
890 cf->can_id |= CAN_ERR_LOSTARB;
891 cf->data[0] |= CAN_ERR_LOSTARB_UNSPEC;
892 }
893 }
894
895 if (unlikely(!skb)) {
896 netdev_dbg(dev, "allocation of skb failed\n");
897 return 0;
898 }
899
900 if (cdev->is_peripheral)
901 timestamp = m_can_get_timestamp(cdev);
902
903 m_can_receive_skb(cdev, skb, timestamp);
904
905 return 1;
906 }
907
m_can_handle_bus_errors(struct net_device * dev,u32 irqstatus,u32 psr)908 static int m_can_handle_bus_errors(struct net_device *dev, u32 irqstatus,
909 u32 psr)
910 {
911 struct m_can_classdev *cdev = netdev_priv(dev);
912 int work_done = 0;
913
914 if (irqstatus & IR_RF0L)
915 work_done += m_can_handle_lost_msg(dev);
916
917 /* handle lec errors on the bus */
918 if (cdev->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) {
919 u8 lec = FIELD_GET(PSR_LEC_MASK, psr);
920 u8 dlec = FIELD_GET(PSR_DLEC_MASK, psr);
921
922 if (is_lec_err(lec)) {
923 netdev_dbg(dev, "Arbitration phase error detected\n");
924 work_done += m_can_handle_lec_err(dev, lec);
925 }
926
927 if (is_lec_err(dlec)) {
928 netdev_dbg(dev, "Data phase error detected\n");
929 work_done += m_can_handle_lec_err(dev, dlec);
930 }
931 }
932
933 /* handle protocol errors in arbitration phase */
934 if ((cdev->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) &&
935 m_can_is_protocol_err(irqstatus))
936 work_done += m_can_handle_protocol_error(dev, irqstatus);
937
938 /* other unproccessed error interrupts */
939 m_can_handle_other_err(dev, irqstatus);
940
941 return work_done;
942 }
943
m_can_rx_handler(struct net_device * dev,int quota,u32 irqstatus)944 static int m_can_rx_handler(struct net_device *dev, int quota, u32 irqstatus)
945 {
946 struct m_can_classdev *cdev = netdev_priv(dev);
947 int rx_work_or_err;
948 int work_done = 0;
949
950 if (!irqstatus)
951 goto end;
952
953 /* Errata workaround for issue "Needless activation of MRAF irq"
954 * During frame reception while the MCAN is in Error Passive state
955 * and the Receive Error Counter has the value MCAN_ECR.REC = 127,
956 * it may happen that MCAN_IR.MRAF is set although there was no
957 * Message RAM access failure.
958 * If MCAN_IR.MRAF is enabled, an interrupt to the Host CPU is generated
959 * The Message RAM Access Failure interrupt routine needs to check
960 * whether MCAN_ECR.RP = ’1’ and MCAN_ECR.REC = 127.
961 * In this case, reset MCAN_IR.MRAF. No further action is required.
962 */
963 if (cdev->version <= 31 && irqstatus & IR_MRAF &&
964 m_can_read(cdev, M_CAN_ECR) & ECR_RP) {
965 struct can_berr_counter bec;
966
967 __m_can_get_berr_counter(dev, &bec);
968 if (bec.rxerr == 127) {
969 m_can_write(cdev, M_CAN_IR, IR_MRAF);
970 irqstatus &= ~IR_MRAF;
971 }
972 }
973
974 if (irqstatus & IR_ERR_STATE)
975 work_done += m_can_handle_state_errors(dev,
976 m_can_read(cdev, M_CAN_PSR));
977
978 if (irqstatus & IR_ERR_BUS_30X)
979 work_done += m_can_handle_bus_errors(dev, irqstatus,
980 m_can_read(cdev, M_CAN_PSR));
981
982 if (irqstatus & IR_RF0N) {
983 rx_work_or_err = m_can_do_rx_poll(dev, (quota - work_done));
984 if (rx_work_or_err < 0)
985 return rx_work_or_err;
986
987 work_done += rx_work_or_err;
988 }
989 end:
990 return work_done;
991 }
992
m_can_rx_peripheral(struct net_device * dev,u32 irqstatus)993 static int m_can_rx_peripheral(struct net_device *dev, u32 irqstatus)
994 {
995 struct m_can_classdev *cdev = netdev_priv(dev);
996 int work_done;
997
998 work_done = m_can_rx_handler(dev, NAPI_POLL_WEIGHT, irqstatus);
999
1000 /* Don't re-enable interrupts if the driver had a fatal error
1001 * (e.g., FIFO read failure).
1002 */
1003 if (work_done < 0)
1004 m_can_disable_all_interrupts(cdev);
1005
1006 return work_done;
1007 }
1008
m_can_poll(struct napi_struct * napi,int quota)1009 static int m_can_poll(struct napi_struct *napi, int quota)
1010 {
1011 struct net_device *dev = napi->dev;
1012 struct m_can_classdev *cdev = netdev_priv(dev);
1013 int work_done;
1014 u32 irqstatus;
1015
1016 irqstatus = cdev->irqstatus | m_can_read(cdev, M_CAN_IR);
1017
1018 work_done = m_can_rx_handler(dev, quota, irqstatus);
1019
1020 /* Don't re-enable interrupts if the driver had a fatal error
1021 * (e.g., FIFO read failure).
1022 */
1023 if (work_done >= 0 && work_done < quota) {
1024 napi_complete_done(napi, work_done);
1025 m_can_enable_all_interrupts(cdev);
1026 }
1027
1028 return work_done;
1029 }
1030
1031 /* Echo tx skb and update net stats. Peripherals use rx-offload for
1032 * echo. timestamp is used for peripherals to ensure correct ordering
1033 * by rx-offload, and is ignored for non-peripherals.
1034 */
m_can_tx_update_stats(struct m_can_classdev * cdev,unsigned int msg_mark,u32 timestamp)1035 static void m_can_tx_update_stats(struct m_can_classdev *cdev,
1036 unsigned int msg_mark,
1037 u32 timestamp)
1038 {
1039 struct net_device *dev = cdev->net;
1040 struct net_device_stats *stats = &dev->stats;
1041
1042 if (cdev->is_peripheral)
1043 stats->tx_bytes +=
1044 can_rx_offload_get_echo_skb_queue_timestamp(&cdev->offload,
1045 msg_mark,
1046 timestamp,
1047 NULL);
1048 else
1049 stats->tx_bytes += can_get_echo_skb(dev, msg_mark, NULL);
1050
1051 stats->tx_packets++;
1052 }
1053
m_can_echo_tx_event(struct net_device * dev)1054 static int m_can_echo_tx_event(struct net_device *dev)
1055 {
1056 u32 txe_count = 0;
1057 u32 m_can_txefs;
1058 u32 fgi = 0;
1059 int ack_fgi = -1;
1060 int i = 0;
1061 int err = 0;
1062 unsigned int msg_mark;
1063
1064 struct m_can_classdev *cdev = netdev_priv(dev);
1065
1066 /* read tx event fifo status */
1067 m_can_txefs = m_can_read(cdev, M_CAN_TXEFS);
1068
1069 /* Get Tx Event fifo element count */
1070 txe_count = FIELD_GET(TXEFS_EFFL_MASK, m_can_txefs);
1071 fgi = FIELD_GET(TXEFS_EFGI_MASK, m_can_txefs);
1072
1073 /* Get and process all sent elements */
1074 for (i = 0; i < txe_count; i++) {
1075 u32 txe, timestamp = 0;
1076
1077 /* get message marker, timestamp */
1078 err = m_can_txe_fifo_read(cdev, fgi, 4, &txe);
1079 if (err) {
1080 netdev_err(dev, "TXE FIFO read returned %d\n", err);
1081 break;
1082 }
1083
1084 msg_mark = FIELD_GET(TX_EVENT_MM_MASK, txe);
1085 timestamp = FIELD_GET(TX_EVENT_TXTS_MASK, txe) << 16;
1086
1087 ack_fgi = fgi;
1088 fgi = (++fgi >= cdev->mcfg[MRAM_TXE].num ? 0 : fgi);
1089
1090 /* update stats */
1091 m_can_tx_update_stats(cdev, msg_mark, timestamp);
1092 }
1093
1094 if (ack_fgi != -1)
1095 m_can_write(cdev, M_CAN_TXEFA, FIELD_PREP(TXEFA_EFAI_MASK,
1096 ack_fgi));
1097
1098 return err;
1099 }
1100
m_can_isr(int irq,void * dev_id)1101 static irqreturn_t m_can_isr(int irq, void *dev_id)
1102 {
1103 struct net_device *dev = (struct net_device *)dev_id;
1104 struct m_can_classdev *cdev = netdev_priv(dev);
1105 u32 ir;
1106
1107 if (pm_runtime_suspended(cdev->dev))
1108 return IRQ_NONE;
1109 ir = m_can_read(cdev, M_CAN_IR);
1110 if (!ir)
1111 return IRQ_NONE;
1112
1113 /* ACK all irqs */
1114 m_can_write(cdev, M_CAN_IR, ir);
1115
1116 if (cdev->ops->clear_interrupts)
1117 cdev->ops->clear_interrupts(cdev);
1118
1119 /* schedule NAPI in case of
1120 * - rx IRQ
1121 * - state change IRQ
1122 * - bus error IRQ and bus error reporting
1123 */
1124 if ((ir & IR_RF0N) || (ir & IR_ERR_ALL_30X)) {
1125 cdev->irqstatus = ir;
1126 if (!cdev->is_peripheral) {
1127 m_can_disable_all_interrupts(cdev);
1128 napi_schedule(&cdev->napi);
1129 } else if (m_can_rx_peripheral(dev, ir) < 0) {
1130 goto out_fail;
1131 }
1132 }
1133
1134 if (cdev->version == 30) {
1135 if (ir & IR_TC) {
1136 /* Transmission Complete Interrupt*/
1137 u32 timestamp = 0;
1138
1139 if (cdev->is_peripheral)
1140 timestamp = m_can_get_timestamp(cdev);
1141 m_can_tx_update_stats(cdev, 0, timestamp);
1142 netif_wake_queue(dev);
1143 }
1144 } else {
1145 if (ir & IR_TEFN) {
1146 /* New TX FIFO Element arrived */
1147 if (m_can_echo_tx_event(dev) != 0)
1148 goto out_fail;
1149
1150 if (netif_queue_stopped(dev) &&
1151 !m_can_tx_fifo_full(cdev))
1152 netif_wake_queue(dev);
1153 }
1154 }
1155
1156 if (cdev->is_peripheral)
1157 can_rx_offload_threaded_irq_finish(&cdev->offload);
1158
1159 return IRQ_HANDLED;
1160
1161 out_fail:
1162 m_can_disable_all_interrupts(cdev);
1163 return IRQ_HANDLED;
1164 }
1165
1166 static const struct can_bittiming_const m_can_bittiming_const_30X = {
1167 .name = KBUILD_MODNAME,
1168 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */
1169 .tseg1_max = 64,
1170 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */
1171 .tseg2_max = 16,
1172 .sjw_max = 16,
1173 .brp_min = 1,
1174 .brp_max = 1024,
1175 .brp_inc = 1,
1176 };
1177
1178 static const struct can_bittiming_const m_can_data_bittiming_const_30X = {
1179 .name = KBUILD_MODNAME,
1180 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */
1181 .tseg1_max = 16,
1182 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */
1183 .tseg2_max = 8,
1184 .sjw_max = 4,
1185 .brp_min = 1,
1186 .brp_max = 32,
1187 .brp_inc = 1,
1188 };
1189
1190 static const struct can_bittiming_const m_can_bittiming_const_31X = {
1191 .name = KBUILD_MODNAME,
1192 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */
1193 .tseg1_max = 256,
1194 .tseg2_min = 2, /* Time segment 2 = phase_seg2 */
1195 .tseg2_max = 128,
1196 .sjw_max = 128,
1197 .brp_min = 1,
1198 .brp_max = 512,
1199 .brp_inc = 1,
1200 };
1201
1202 static const struct can_bittiming_const m_can_data_bittiming_const_31X = {
1203 .name = KBUILD_MODNAME,
1204 .tseg1_min = 1, /* Time segment 1 = prop_seg + phase_seg1 */
1205 .tseg1_max = 32,
1206 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */
1207 .tseg2_max = 16,
1208 .sjw_max = 16,
1209 .brp_min = 1,
1210 .brp_max = 32,
1211 .brp_inc = 1,
1212 };
1213
m_can_set_bittiming(struct net_device * dev)1214 static int m_can_set_bittiming(struct net_device *dev)
1215 {
1216 struct m_can_classdev *cdev = netdev_priv(dev);
1217 const struct can_bittiming *bt = &cdev->can.bittiming;
1218 const struct can_bittiming *dbt = &cdev->can.data_bittiming;
1219 u16 brp, sjw, tseg1, tseg2;
1220 u32 reg_btp;
1221
1222 brp = bt->brp - 1;
1223 sjw = bt->sjw - 1;
1224 tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
1225 tseg2 = bt->phase_seg2 - 1;
1226 reg_btp = FIELD_PREP(NBTP_NBRP_MASK, brp) |
1227 FIELD_PREP(NBTP_NSJW_MASK, sjw) |
1228 FIELD_PREP(NBTP_NTSEG1_MASK, tseg1) |
1229 FIELD_PREP(NBTP_NTSEG2_MASK, tseg2);
1230 m_can_write(cdev, M_CAN_NBTP, reg_btp);
1231
1232 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) {
1233 reg_btp = 0;
1234 brp = dbt->brp - 1;
1235 sjw = dbt->sjw - 1;
1236 tseg1 = dbt->prop_seg + dbt->phase_seg1 - 1;
1237 tseg2 = dbt->phase_seg2 - 1;
1238
1239 /* TDC is only needed for bitrates beyond 2.5 MBit/s.
1240 * This is mentioned in the "Bit Time Requirements for CAN FD"
1241 * paper presented at the International CAN Conference 2013
1242 */
1243 if (dbt->bitrate > 2500000) {
1244 u32 tdco, ssp;
1245
1246 /* Use the same value of secondary sampling point
1247 * as the data sampling point
1248 */
1249 ssp = dbt->sample_point;
1250
1251 /* Equation based on Bosch's M_CAN User Manual's
1252 * Transmitter Delay Compensation Section
1253 */
1254 tdco = (cdev->can.clock.freq / 1000) *
1255 ssp / dbt->bitrate;
1256
1257 /* Max valid TDCO value is 127 */
1258 if (tdco > 127) {
1259 netdev_warn(dev, "TDCO value of %u is beyond maximum. Using maximum possible value\n",
1260 tdco);
1261 tdco = 127;
1262 }
1263
1264 reg_btp |= DBTP_TDC;
1265 m_can_write(cdev, M_CAN_TDCR,
1266 FIELD_PREP(TDCR_TDCO_MASK, tdco));
1267 }
1268
1269 reg_btp |= FIELD_PREP(DBTP_DBRP_MASK, brp) |
1270 FIELD_PREP(DBTP_DSJW_MASK, sjw) |
1271 FIELD_PREP(DBTP_DTSEG1_MASK, tseg1) |
1272 FIELD_PREP(DBTP_DTSEG2_MASK, tseg2);
1273
1274 m_can_write(cdev, M_CAN_DBTP, reg_btp);
1275 }
1276
1277 return 0;
1278 }
1279
1280 /* Configure M_CAN chip:
1281 * - set rx buffer/fifo element size
1282 * - configure rx fifo
1283 * - accept non-matching frame into fifo 0
1284 * - configure tx buffer
1285 * - >= v3.1.x: TX FIFO is used
1286 * - configure mode
1287 * - setup bittiming
1288 * - configure timestamp generation
1289 */
m_can_chip_config(struct net_device * dev)1290 static int m_can_chip_config(struct net_device *dev)
1291 {
1292 struct m_can_classdev *cdev = netdev_priv(dev);
1293 u32 interrupts = IR_ALL_INT;
1294 u32 cccr, test;
1295 int err;
1296
1297 err = m_can_init_ram(cdev);
1298 if (err) {
1299 dev_err(cdev->dev, "Message RAM configuration failed\n");
1300 return err;
1301 }
1302
1303 /* Disable unused interrupts */
1304 interrupts &= ~(IR_ARA | IR_ELO | IR_DRX | IR_TEFF | IR_TEFW | IR_TFE |
1305 IR_TCF | IR_HPM | IR_RF1F | IR_RF1W | IR_RF1N |
1306 IR_RF0F | IR_RF0W);
1307
1308 m_can_config_endisable(cdev, true);
1309
1310 /* RX Buffer/FIFO Element Size 64 bytes data field */
1311 m_can_write(cdev, M_CAN_RXESC,
1312 FIELD_PREP(RXESC_RBDS_MASK, RXESC_64B) |
1313 FIELD_PREP(RXESC_F1DS_MASK, RXESC_64B) |
1314 FIELD_PREP(RXESC_F0DS_MASK, RXESC_64B));
1315
1316 /* Accept Non-matching Frames Into FIFO 0 */
1317 m_can_write(cdev, M_CAN_GFC, 0x0);
1318
1319 if (cdev->version == 30) {
1320 /* only support one Tx Buffer currently */
1321 m_can_write(cdev, M_CAN_TXBC, FIELD_PREP(TXBC_NDTB_MASK, 1) |
1322 cdev->mcfg[MRAM_TXB].off);
1323 } else {
1324 /* TX FIFO is used for newer IP Core versions */
1325 m_can_write(cdev, M_CAN_TXBC,
1326 FIELD_PREP(TXBC_TFQS_MASK,
1327 cdev->mcfg[MRAM_TXB].num) |
1328 cdev->mcfg[MRAM_TXB].off);
1329 }
1330
1331 /* support 64 bytes payload */
1332 m_can_write(cdev, M_CAN_TXESC,
1333 FIELD_PREP(TXESC_TBDS_MASK, TXESC_TBDS_64B));
1334
1335 /* TX Event FIFO */
1336 if (cdev->version == 30) {
1337 m_can_write(cdev, M_CAN_TXEFC,
1338 FIELD_PREP(TXEFC_EFS_MASK, 1) |
1339 cdev->mcfg[MRAM_TXE].off);
1340 } else {
1341 /* Full TX Event FIFO is used */
1342 m_can_write(cdev, M_CAN_TXEFC,
1343 FIELD_PREP(TXEFC_EFS_MASK,
1344 cdev->mcfg[MRAM_TXE].num) |
1345 cdev->mcfg[MRAM_TXE].off);
1346 }
1347
1348 /* rx fifo configuration, blocking mode, fifo size 1 */
1349 m_can_write(cdev, M_CAN_RXF0C,
1350 FIELD_PREP(RXFC_FS_MASK, cdev->mcfg[MRAM_RXF0].num) |
1351 cdev->mcfg[MRAM_RXF0].off);
1352
1353 m_can_write(cdev, M_CAN_RXF1C,
1354 FIELD_PREP(RXFC_FS_MASK, cdev->mcfg[MRAM_RXF1].num) |
1355 cdev->mcfg[MRAM_RXF1].off);
1356
1357 cccr = m_can_read(cdev, M_CAN_CCCR);
1358 test = m_can_read(cdev, M_CAN_TEST);
1359 test &= ~TEST_LBCK;
1360 if (cdev->version == 30) {
1361 /* Version 3.0.x */
1362
1363 cccr &= ~(CCCR_TEST | CCCR_MON | CCCR_DAR |
1364 FIELD_PREP(CCCR_CMR_MASK, FIELD_MAX(CCCR_CMR_MASK)) |
1365 FIELD_PREP(CCCR_CME_MASK, FIELD_MAX(CCCR_CME_MASK)));
1366
1367 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD)
1368 cccr |= FIELD_PREP(CCCR_CME_MASK, CCCR_CME_CANFD_BRS);
1369
1370 } else {
1371 /* Version 3.1.x or 3.2.x */
1372 cccr &= ~(CCCR_TEST | CCCR_MON | CCCR_BRSE | CCCR_FDOE |
1373 CCCR_NISO | CCCR_DAR);
1374
1375 /* Only 3.2.x has NISO Bit implemented */
1376 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO)
1377 cccr |= CCCR_NISO;
1378
1379 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD)
1380 cccr |= (CCCR_BRSE | CCCR_FDOE);
1381 }
1382
1383 /* Loopback Mode */
1384 if (cdev->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
1385 cccr |= CCCR_TEST | CCCR_MON;
1386 test |= TEST_LBCK;
1387 }
1388
1389 /* Enable Monitoring (all versions) */
1390 if (cdev->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
1391 cccr |= CCCR_MON;
1392
1393 /* Disable Auto Retransmission (all versions) */
1394 if (cdev->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT)
1395 cccr |= CCCR_DAR;
1396
1397 /* Write config */
1398 m_can_write(cdev, M_CAN_CCCR, cccr);
1399 m_can_write(cdev, M_CAN_TEST, test);
1400
1401 /* Enable interrupts */
1402 if (!(cdev->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) {
1403 if (cdev->version == 30)
1404 interrupts &= ~(IR_ERR_LEC_30X);
1405 else
1406 interrupts &= ~(IR_ERR_LEC_31X);
1407 }
1408 m_can_write(cdev, M_CAN_IE, interrupts);
1409
1410 /* route all interrupts to INT0 */
1411 m_can_write(cdev, M_CAN_ILS, ILS_ALL_INT0);
1412
1413 /* set bittiming params */
1414 m_can_set_bittiming(dev);
1415
1416 /* enable internal timestamp generation, with a prescaler of 16. The
1417 * prescaler is applied to the nominal bit timing
1418 */
1419 m_can_write(cdev, M_CAN_TSCC,
1420 FIELD_PREP(TSCC_TCP_MASK, 0xf) |
1421 FIELD_PREP(TSCC_TSS_MASK, TSCC_TSS_INTERNAL));
1422
1423 m_can_config_endisable(cdev, false);
1424
1425 if (cdev->ops->init)
1426 cdev->ops->init(cdev);
1427
1428 return 0;
1429 }
1430
m_can_start(struct net_device * dev)1431 static int m_can_start(struct net_device *dev)
1432 {
1433 struct m_can_classdev *cdev = netdev_priv(dev);
1434 int ret;
1435
1436 /* basic m_can configuration */
1437 ret = m_can_chip_config(dev);
1438 if (ret)
1439 return ret;
1440
1441 cdev->can.state = CAN_STATE_ERROR_ACTIVE;
1442
1443 m_can_enable_all_interrupts(cdev);
1444
1445 return 0;
1446 }
1447
m_can_set_mode(struct net_device * dev,enum can_mode mode)1448 static int m_can_set_mode(struct net_device *dev, enum can_mode mode)
1449 {
1450 switch (mode) {
1451 case CAN_MODE_START:
1452 m_can_clean(dev);
1453 m_can_start(dev);
1454 netif_wake_queue(dev);
1455 break;
1456 default:
1457 return -EOPNOTSUPP;
1458 }
1459
1460 return 0;
1461 }
1462
1463 /* Checks core release number of M_CAN
1464 * returns 0 if an unsupported device is detected
1465 * else it returns the release and step coded as:
1466 * return value = 10 * <release> + 1 * <step>
1467 */
m_can_check_core_release(struct m_can_classdev * cdev)1468 static int m_can_check_core_release(struct m_can_classdev *cdev)
1469 {
1470 u32 crel_reg;
1471 u8 rel;
1472 u8 step;
1473 int res;
1474
1475 /* Read Core Release Version and split into version number
1476 * Example: Version 3.2.1 => rel = 3; step = 2; substep = 1;
1477 */
1478 crel_reg = m_can_read(cdev, M_CAN_CREL);
1479 rel = (u8)FIELD_GET(CREL_REL_MASK, crel_reg);
1480 step = (u8)FIELD_GET(CREL_STEP_MASK, crel_reg);
1481
1482 if (rel == 3) {
1483 /* M_CAN v3.x.y: create return value */
1484 res = 30 + step;
1485 } else {
1486 /* Unsupported M_CAN version */
1487 res = 0;
1488 }
1489
1490 return res;
1491 }
1492
1493 /* Selectable Non ISO support only in version 3.2.x
1494 * This function checks if the bit is writable.
1495 */
m_can_niso_supported(struct m_can_classdev * cdev)1496 static bool m_can_niso_supported(struct m_can_classdev *cdev)
1497 {
1498 u32 cccr_reg, cccr_poll = 0;
1499 int niso_timeout = -ETIMEDOUT;
1500 int i;
1501
1502 m_can_config_endisable(cdev, true);
1503 cccr_reg = m_can_read(cdev, M_CAN_CCCR);
1504 cccr_reg |= CCCR_NISO;
1505 m_can_write(cdev, M_CAN_CCCR, cccr_reg);
1506
1507 for (i = 0; i <= 10; i++) {
1508 cccr_poll = m_can_read(cdev, M_CAN_CCCR);
1509 if (cccr_poll == cccr_reg) {
1510 niso_timeout = 0;
1511 break;
1512 }
1513
1514 usleep_range(1, 5);
1515 }
1516
1517 /* Clear NISO */
1518 cccr_reg &= ~(CCCR_NISO);
1519 m_can_write(cdev, M_CAN_CCCR, cccr_reg);
1520
1521 m_can_config_endisable(cdev, false);
1522
1523 /* return false if time out (-ETIMEDOUT), else return true */
1524 return !niso_timeout;
1525 }
1526
m_can_dev_setup(struct m_can_classdev * cdev)1527 static int m_can_dev_setup(struct m_can_classdev *cdev)
1528 {
1529 struct net_device *dev = cdev->net;
1530 int m_can_version, err;
1531
1532 m_can_version = m_can_check_core_release(cdev);
1533 /* return if unsupported version */
1534 if (!m_can_version) {
1535 dev_err(cdev->dev, "Unsupported version number: %2d",
1536 m_can_version);
1537 return -EINVAL;
1538 }
1539
1540 if (!cdev->is_peripheral)
1541 netif_napi_add(dev, &cdev->napi, m_can_poll);
1542
1543 /* Shared properties of all M_CAN versions */
1544 cdev->version = m_can_version;
1545 cdev->can.do_set_mode = m_can_set_mode;
1546 cdev->can.do_get_berr_counter = m_can_get_berr_counter;
1547
1548 /* Set M_CAN supported operations */
1549 cdev->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1550 CAN_CTRLMODE_LISTENONLY |
1551 CAN_CTRLMODE_BERR_REPORTING |
1552 CAN_CTRLMODE_FD |
1553 CAN_CTRLMODE_ONE_SHOT;
1554
1555 /* Set properties depending on M_CAN version */
1556 switch (cdev->version) {
1557 case 30:
1558 /* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.0.x */
1559 err = can_set_static_ctrlmode(dev, CAN_CTRLMODE_FD_NON_ISO);
1560 if (err)
1561 return err;
1562 cdev->can.bittiming_const = &m_can_bittiming_const_30X;
1563 cdev->can.data_bittiming_const = &m_can_data_bittiming_const_30X;
1564 break;
1565 case 31:
1566 /* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.1.x */
1567 err = can_set_static_ctrlmode(dev, CAN_CTRLMODE_FD_NON_ISO);
1568 if (err)
1569 return err;
1570 cdev->can.bittiming_const = &m_can_bittiming_const_31X;
1571 cdev->can.data_bittiming_const = &m_can_data_bittiming_const_31X;
1572 break;
1573 case 32:
1574 case 33:
1575 /* Support both MCAN version v3.2.x and v3.3.0 */
1576 cdev->can.bittiming_const = &m_can_bittiming_const_31X;
1577 cdev->can.data_bittiming_const = &m_can_data_bittiming_const_31X;
1578
1579 cdev->can.ctrlmode_supported |=
1580 (m_can_niso_supported(cdev) ?
1581 CAN_CTRLMODE_FD_NON_ISO : 0);
1582 break;
1583 default:
1584 dev_err(cdev->dev, "Unsupported version number: %2d",
1585 cdev->version);
1586 return -EINVAL;
1587 }
1588
1589 if (cdev->ops->init)
1590 cdev->ops->init(cdev);
1591
1592 return 0;
1593 }
1594
m_can_stop(struct net_device * dev)1595 static void m_can_stop(struct net_device *dev)
1596 {
1597 struct m_can_classdev *cdev = netdev_priv(dev);
1598
1599 /* disable all interrupts */
1600 m_can_disable_all_interrupts(cdev);
1601
1602 /* Set init mode to disengage from the network */
1603 m_can_config_endisable(cdev, true);
1604
1605 /* set the state as STOPPED */
1606 cdev->can.state = CAN_STATE_STOPPED;
1607 }
1608
m_can_close(struct net_device * dev)1609 static int m_can_close(struct net_device *dev)
1610 {
1611 struct m_can_classdev *cdev = netdev_priv(dev);
1612
1613 netif_stop_queue(dev);
1614
1615 m_can_stop(dev);
1616 if (dev->irq)
1617 free_irq(dev->irq, dev);
1618
1619 if (cdev->is_peripheral) {
1620 cdev->tx_skb = NULL;
1621 destroy_workqueue(cdev->tx_wq);
1622 cdev->tx_wq = NULL;
1623 can_rx_offload_disable(&cdev->offload);
1624 } else {
1625 napi_disable(&cdev->napi);
1626 }
1627
1628 close_candev(dev);
1629
1630 m_can_clk_stop(cdev);
1631 phy_power_off(cdev->transceiver);
1632
1633 return 0;
1634 }
1635
m_can_next_echo_skb_occupied(struct net_device * dev,int putidx)1636 static int m_can_next_echo_skb_occupied(struct net_device *dev, int putidx)
1637 {
1638 struct m_can_classdev *cdev = netdev_priv(dev);
1639 /*get wrap around for loopback skb index */
1640 unsigned int wrap = cdev->can.echo_skb_max;
1641 int next_idx;
1642
1643 /* calculate next index */
1644 next_idx = (++putidx >= wrap ? 0 : putidx);
1645
1646 /* check if occupied */
1647 return !!cdev->can.echo_skb[next_idx];
1648 }
1649
m_can_tx_handler(struct m_can_classdev * cdev)1650 static netdev_tx_t m_can_tx_handler(struct m_can_classdev *cdev)
1651 {
1652 struct canfd_frame *cf = (struct canfd_frame *)cdev->tx_skb->data;
1653 struct net_device *dev = cdev->net;
1654 struct sk_buff *skb = cdev->tx_skb;
1655 struct id_and_dlc fifo_header;
1656 u32 cccr, fdflags;
1657 u32 txfqs;
1658 int err;
1659 int putidx;
1660
1661 cdev->tx_skb = NULL;
1662
1663 /* Generate ID field for TX buffer Element */
1664 /* Common to all supported M_CAN versions */
1665 if (cf->can_id & CAN_EFF_FLAG) {
1666 fifo_header.id = cf->can_id & CAN_EFF_MASK;
1667 fifo_header.id |= TX_BUF_XTD;
1668 } else {
1669 fifo_header.id = ((cf->can_id & CAN_SFF_MASK) << 18);
1670 }
1671
1672 if (cf->can_id & CAN_RTR_FLAG)
1673 fifo_header.id |= TX_BUF_RTR;
1674
1675 if (cdev->version == 30) {
1676 netif_stop_queue(dev);
1677
1678 fifo_header.dlc = can_fd_len2dlc(cf->len) << 16;
1679
1680 /* Write the frame ID, DLC, and payload to the FIFO element. */
1681 err = m_can_fifo_write(cdev, 0, M_CAN_FIFO_ID, &fifo_header, 2);
1682 if (err)
1683 goto out_fail;
1684
1685 err = m_can_fifo_write(cdev, 0, M_CAN_FIFO_DATA,
1686 cf->data, DIV_ROUND_UP(cf->len, 4));
1687 if (err)
1688 goto out_fail;
1689
1690 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) {
1691 cccr = m_can_read(cdev, M_CAN_CCCR);
1692 cccr &= ~CCCR_CMR_MASK;
1693 if (can_is_canfd_skb(skb)) {
1694 if (cf->flags & CANFD_BRS)
1695 cccr |= FIELD_PREP(CCCR_CMR_MASK,
1696 CCCR_CMR_CANFD_BRS);
1697 else
1698 cccr |= FIELD_PREP(CCCR_CMR_MASK,
1699 CCCR_CMR_CANFD);
1700 } else {
1701 cccr |= FIELD_PREP(CCCR_CMR_MASK, CCCR_CMR_CAN);
1702 }
1703 m_can_write(cdev, M_CAN_CCCR, cccr);
1704 }
1705 m_can_write(cdev, M_CAN_TXBTIE, 0x1);
1706
1707 can_put_echo_skb(skb, dev, 0, 0);
1708
1709 m_can_write(cdev, M_CAN_TXBAR, 0x1);
1710 /* End of xmit function for version 3.0.x */
1711 } else {
1712 /* Transmit routine for version >= v3.1.x */
1713
1714 txfqs = m_can_read(cdev, M_CAN_TXFQS);
1715
1716 /* Check if FIFO full */
1717 if (_m_can_tx_fifo_full(txfqs)) {
1718 /* This shouldn't happen */
1719 netif_stop_queue(dev);
1720 netdev_warn(dev,
1721 "TX queue active although FIFO is full.");
1722
1723 if (cdev->is_peripheral) {
1724 kfree_skb(skb);
1725 dev->stats.tx_dropped++;
1726 return NETDEV_TX_OK;
1727 } else {
1728 return NETDEV_TX_BUSY;
1729 }
1730 }
1731
1732 /* get put index for frame */
1733 putidx = FIELD_GET(TXFQS_TFQPI_MASK, txfqs);
1734
1735 /* Construct DLC Field, with CAN-FD configuration.
1736 * Use the put index of the fifo as the message marker,
1737 * used in the TX interrupt for sending the correct echo frame.
1738 */
1739
1740 /* get CAN FD configuration of frame */
1741 fdflags = 0;
1742 if (can_is_canfd_skb(skb)) {
1743 fdflags |= TX_BUF_FDF;
1744 if (cf->flags & CANFD_BRS)
1745 fdflags |= TX_BUF_BRS;
1746 }
1747
1748 fifo_header.dlc = FIELD_PREP(TX_BUF_MM_MASK, putidx) |
1749 FIELD_PREP(TX_BUF_DLC_MASK, can_fd_len2dlc(cf->len)) |
1750 fdflags | TX_BUF_EFC;
1751 err = m_can_fifo_write(cdev, putidx, M_CAN_FIFO_ID, &fifo_header, 2);
1752 if (err)
1753 goto out_fail;
1754
1755 err = m_can_fifo_write(cdev, putidx, M_CAN_FIFO_DATA,
1756 cf->data, DIV_ROUND_UP(cf->len, 4));
1757 if (err)
1758 goto out_fail;
1759
1760 /* Push loopback echo.
1761 * Will be looped back on TX interrupt based on message marker
1762 */
1763 can_put_echo_skb(skb, dev, putidx, 0);
1764
1765 /* Enable TX FIFO element to start transfer */
1766 m_can_write(cdev, M_CAN_TXBAR, (1 << putidx));
1767
1768 /* stop network queue if fifo full */
1769 if (m_can_tx_fifo_full(cdev) ||
1770 m_can_next_echo_skb_occupied(dev, putidx))
1771 netif_stop_queue(dev);
1772 }
1773
1774 return NETDEV_TX_OK;
1775
1776 out_fail:
1777 netdev_err(dev, "FIFO write returned %d\n", err);
1778 m_can_disable_all_interrupts(cdev);
1779 return NETDEV_TX_BUSY;
1780 }
1781
m_can_tx_work_queue(struct work_struct * ws)1782 static void m_can_tx_work_queue(struct work_struct *ws)
1783 {
1784 struct m_can_classdev *cdev = container_of(ws, struct m_can_classdev,
1785 tx_work);
1786
1787 m_can_tx_handler(cdev);
1788 }
1789
m_can_start_xmit(struct sk_buff * skb,struct net_device * dev)1790 static netdev_tx_t m_can_start_xmit(struct sk_buff *skb,
1791 struct net_device *dev)
1792 {
1793 struct m_can_classdev *cdev = netdev_priv(dev);
1794
1795 if (can_dev_dropped_skb(dev, skb))
1796 return NETDEV_TX_OK;
1797
1798 if (cdev->is_peripheral) {
1799 if (cdev->tx_skb) {
1800 netdev_err(dev, "hard_xmit called while tx busy\n");
1801 return NETDEV_TX_BUSY;
1802 }
1803
1804 if (cdev->can.state == CAN_STATE_BUS_OFF) {
1805 m_can_clean(dev);
1806 } else {
1807 /* Need to stop the queue to avoid numerous requests
1808 * from being sent. Suggested improvement is to create
1809 * a queueing mechanism that will queue the skbs and
1810 * process them in order.
1811 */
1812 cdev->tx_skb = skb;
1813 netif_stop_queue(cdev->net);
1814 queue_work(cdev->tx_wq, &cdev->tx_work);
1815 }
1816 } else {
1817 cdev->tx_skb = skb;
1818 return m_can_tx_handler(cdev);
1819 }
1820
1821 return NETDEV_TX_OK;
1822 }
1823
hrtimer_callback(struct hrtimer * timer)1824 static enum hrtimer_restart hrtimer_callback(struct hrtimer *timer)
1825 {
1826 struct m_can_classdev *cdev = container_of(timer, struct
1827 m_can_classdev, hrtimer);
1828
1829 m_can_isr(0, cdev->net);
1830
1831 hrtimer_forward_now(timer, ms_to_ktime(HRTIMER_POLL_INTERVAL_MS));
1832
1833 return HRTIMER_RESTART;
1834 }
1835
m_can_open(struct net_device * dev)1836 static int m_can_open(struct net_device *dev)
1837 {
1838 struct m_can_classdev *cdev = netdev_priv(dev);
1839 int err;
1840
1841 err = phy_power_on(cdev->transceiver);
1842 if (err)
1843 return err;
1844
1845 err = m_can_clk_start(cdev);
1846 if (err)
1847 goto out_phy_power_off;
1848
1849 /* open the can device */
1850 err = open_candev(dev);
1851 if (err) {
1852 netdev_err(dev, "failed to open can device\n");
1853 goto exit_disable_clks;
1854 }
1855
1856 if (cdev->is_peripheral)
1857 can_rx_offload_enable(&cdev->offload);
1858 else
1859 napi_enable(&cdev->napi);
1860
1861 /* register interrupt handler */
1862 if (cdev->is_peripheral) {
1863 cdev->tx_skb = NULL;
1864 cdev->tx_wq = alloc_workqueue("mcan_wq",
1865 WQ_FREEZABLE | WQ_MEM_RECLAIM, 0);
1866 if (!cdev->tx_wq) {
1867 err = -ENOMEM;
1868 goto out_wq_fail;
1869 }
1870
1871 INIT_WORK(&cdev->tx_work, m_can_tx_work_queue);
1872
1873 err = request_threaded_irq(dev->irq, NULL, m_can_isr,
1874 IRQF_ONESHOT,
1875 dev->name, dev);
1876 } else if (dev->irq) {
1877 err = request_irq(dev->irq, m_can_isr, IRQF_SHARED, dev->name,
1878 dev);
1879 }
1880
1881 if (err < 0) {
1882 netdev_err(dev, "failed to request interrupt\n");
1883 goto exit_irq_fail;
1884 }
1885
1886 /* start the m_can controller */
1887 err = m_can_start(dev);
1888 if (err)
1889 goto exit_start_fail;
1890
1891 netif_start_queue(dev);
1892
1893 return 0;
1894
1895 exit_start_fail:
1896 if (cdev->is_peripheral || dev->irq)
1897 free_irq(dev->irq, dev);
1898 exit_irq_fail:
1899 if (cdev->is_peripheral)
1900 destroy_workqueue(cdev->tx_wq);
1901 out_wq_fail:
1902 if (cdev->is_peripheral)
1903 can_rx_offload_disable(&cdev->offload);
1904 else
1905 napi_disable(&cdev->napi);
1906 close_candev(dev);
1907 exit_disable_clks:
1908 m_can_clk_stop(cdev);
1909 out_phy_power_off:
1910 phy_power_off(cdev->transceiver);
1911 return err;
1912 }
1913
1914 static const struct net_device_ops m_can_netdev_ops = {
1915 .ndo_open = m_can_open,
1916 .ndo_stop = m_can_close,
1917 .ndo_start_xmit = m_can_start_xmit,
1918 .ndo_change_mtu = can_change_mtu,
1919 };
1920
1921 static const struct ethtool_ops m_can_ethtool_ops = {
1922 .get_ts_info = ethtool_op_get_ts_info,
1923 };
1924
register_m_can_dev(struct net_device * dev)1925 static int register_m_can_dev(struct net_device *dev)
1926 {
1927 dev->flags |= IFF_ECHO; /* we support local echo */
1928 dev->netdev_ops = &m_can_netdev_ops;
1929 dev->ethtool_ops = &m_can_ethtool_ops;
1930
1931 return register_candev(dev);
1932 }
1933
m_can_check_mram_cfg(struct m_can_classdev * cdev,u32 mram_max_size)1934 int m_can_check_mram_cfg(struct m_can_classdev *cdev, u32 mram_max_size)
1935 {
1936 u32 total_size;
1937
1938 total_size = cdev->mcfg[MRAM_TXB].off - cdev->mcfg[MRAM_SIDF].off +
1939 cdev->mcfg[MRAM_TXB].num * TXB_ELEMENT_SIZE;
1940 if (total_size > mram_max_size) {
1941 dev_err(cdev->dev, "Total size of mram config(%u) exceeds mram(%u)\n",
1942 total_size, mram_max_size);
1943 return -EINVAL;
1944 }
1945
1946 return 0;
1947 }
1948 EXPORT_SYMBOL_GPL(m_can_check_mram_cfg);
1949
m_can_of_parse_mram(struct m_can_classdev * cdev,const u32 * mram_config_vals)1950 static void m_can_of_parse_mram(struct m_can_classdev *cdev,
1951 const u32 *mram_config_vals)
1952 {
1953 cdev->mcfg[MRAM_SIDF].off = mram_config_vals[0];
1954 cdev->mcfg[MRAM_SIDF].num = mram_config_vals[1];
1955 cdev->mcfg[MRAM_XIDF].off = cdev->mcfg[MRAM_SIDF].off +
1956 cdev->mcfg[MRAM_SIDF].num * SIDF_ELEMENT_SIZE;
1957 cdev->mcfg[MRAM_XIDF].num = mram_config_vals[2];
1958 cdev->mcfg[MRAM_RXF0].off = cdev->mcfg[MRAM_XIDF].off +
1959 cdev->mcfg[MRAM_XIDF].num * XIDF_ELEMENT_SIZE;
1960 cdev->mcfg[MRAM_RXF0].num = mram_config_vals[3] &
1961 FIELD_MAX(RXFC_FS_MASK);
1962 cdev->mcfg[MRAM_RXF1].off = cdev->mcfg[MRAM_RXF0].off +
1963 cdev->mcfg[MRAM_RXF0].num * RXF0_ELEMENT_SIZE;
1964 cdev->mcfg[MRAM_RXF1].num = mram_config_vals[4] &
1965 FIELD_MAX(RXFC_FS_MASK);
1966 cdev->mcfg[MRAM_RXB].off = cdev->mcfg[MRAM_RXF1].off +
1967 cdev->mcfg[MRAM_RXF1].num * RXF1_ELEMENT_SIZE;
1968 cdev->mcfg[MRAM_RXB].num = mram_config_vals[5];
1969 cdev->mcfg[MRAM_TXE].off = cdev->mcfg[MRAM_RXB].off +
1970 cdev->mcfg[MRAM_RXB].num * RXB_ELEMENT_SIZE;
1971 cdev->mcfg[MRAM_TXE].num = mram_config_vals[6];
1972 cdev->mcfg[MRAM_TXB].off = cdev->mcfg[MRAM_TXE].off +
1973 cdev->mcfg[MRAM_TXE].num * TXE_ELEMENT_SIZE;
1974 cdev->mcfg[MRAM_TXB].num = mram_config_vals[7] &
1975 FIELD_MAX(TXBC_NDTB_MASK);
1976
1977 dev_dbg(cdev->dev,
1978 "sidf 0x%x %d xidf 0x%x %d rxf0 0x%x %d rxf1 0x%x %d rxb 0x%x %d txe 0x%x %d txb 0x%x %d\n",
1979 cdev->mcfg[MRAM_SIDF].off, cdev->mcfg[MRAM_SIDF].num,
1980 cdev->mcfg[MRAM_XIDF].off, cdev->mcfg[MRAM_XIDF].num,
1981 cdev->mcfg[MRAM_RXF0].off, cdev->mcfg[MRAM_RXF0].num,
1982 cdev->mcfg[MRAM_RXF1].off, cdev->mcfg[MRAM_RXF1].num,
1983 cdev->mcfg[MRAM_RXB].off, cdev->mcfg[MRAM_RXB].num,
1984 cdev->mcfg[MRAM_TXE].off, cdev->mcfg[MRAM_TXE].num,
1985 cdev->mcfg[MRAM_TXB].off, cdev->mcfg[MRAM_TXB].num);
1986 }
1987
m_can_init_ram(struct m_can_classdev * cdev)1988 int m_can_init_ram(struct m_can_classdev *cdev)
1989 {
1990 int end, i, start;
1991 int err = 0;
1992
1993 /* initialize the entire Message RAM in use to avoid possible
1994 * ECC/parity checksum errors when reading an uninitialized buffer
1995 */
1996 start = cdev->mcfg[MRAM_SIDF].off;
1997 end = cdev->mcfg[MRAM_TXB].off +
1998 cdev->mcfg[MRAM_TXB].num * TXB_ELEMENT_SIZE;
1999
2000 for (i = start; i < end; i += 4) {
2001 err = m_can_fifo_write_no_off(cdev, i, 0x0);
2002 if (err)
2003 break;
2004 }
2005
2006 return err;
2007 }
2008 EXPORT_SYMBOL_GPL(m_can_init_ram);
2009
m_can_class_get_clocks(struct m_can_classdev * cdev)2010 int m_can_class_get_clocks(struct m_can_classdev *cdev)
2011 {
2012 int ret = 0;
2013
2014 cdev->hclk = devm_clk_get(cdev->dev, "hclk");
2015 cdev->cclk = devm_clk_get(cdev->dev, "cclk");
2016
2017 if (IS_ERR(cdev->hclk) || IS_ERR(cdev->cclk)) {
2018 dev_err(cdev->dev, "no clock found\n");
2019 ret = -ENODEV;
2020 }
2021
2022 return ret;
2023 }
2024 EXPORT_SYMBOL_GPL(m_can_class_get_clocks);
2025
m_can_class_allocate_dev(struct device * dev,int sizeof_priv)2026 struct m_can_classdev *m_can_class_allocate_dev(struct device *dev,
2027 int sizeof_priv)
2028 {
2029 struct m_can_classdev *class_dev = NULL;
2030 u32 mram_config_vals[MRAM_CFG_LEN];
2031 struct net_device *net_dev;
2032 u32 tx_fifo_size;
2033 int ret;
2034
2035 ret = fwnode_property_read_u32_array(dev_fwnode(dev),
2036 "bosch,mram-cfg",
2037 mram_config_vals,
2038 sizeof(mram_config_vals) / 4);
2039 if (ret) {
2040 dev_err(dev, "Could not get Message RAM configuration.");
2041 goto out;
2042 }
2043
2044 /* Get TX FIFO size
2045 * Defines the total amount of echo buffers for loopback
2046 */
2047 tx_fifo_size = mram_config_vals[7];
2048
2049 /* allocate the m_can device */
2050 net_dev = alloc_candev(sizeof_priv, tx_fifo_size);
2051 if (!net_dev) {
2052 dev_err(dev, "Failed to allocate CAN device");
2053 goto out;
2054 }
2055
2056 class_dev = netdev_priv(net_dev);
2057 class_dev->net = net_dev;
2058 class_dev->dev = dev;
2059 SET_NETDEV_DEV(net_dev, dev);
2060
2061 m_can_of_parse_mram(class_dev, mram_config_vals);
2062 out:
2063 return class_dev;
2064 }
2065 EXPORT_SYMBOL_GPL(m_can_class_allocate_dev);
2066
m_can_class_free_dev(struct net_device * net)2067 void m_can_class_free_dev(struct net_device *net)
2068 {
2069 free_candev(net);
2070 }
2071 EXPORT_SYMBOL_GPL(m_can_class_free_dev);
2072
m_can_class_register(struct m_can_classdev * cdev)2073 int m_can_class_register(struct m_can_classdev *cdev)
2074 {
2075 int ret;
2076
2077 if (cdev->pm_clock_support) {
2078 ret = m_can_clk_start(cdev);
2079 if (ret)
2080 return ret;
2081 }
2082
2083 if (cdev->is_peripheral) {
2084 ret = can_rx_offload_add_manual(cdev->net, &cdev->offload,
2085 NAPI_POLL_WEIGHT);
2086 if (ret)
2087 goto clk_disable;
2088 }
2089
2090 if (!cdev->net->irq)
2091 cdev->hrtimer.function = &hrtimer_callback;
2092
2093 ret = m_can_dev_setup(cdev);
2094 if (ret)
2095 goto rx_offload_del;
2096
2097 ret = register_m_can_dev(cdev->net);
2098 if (ret) {
2099 dev_err(cdev->dev, "registering %s failed (err=%d)\n",
2100 cdev->net->name, ret);
2101 goto rx_offload_del;
2102 }
2103
2104 of_can_transceiver(cdev->net);
2105
2106 dev_info(cdev->dev, "%s device registered (irq=%d, version=%d)\n",
2107 KBUILD_MODNAME, cdev->net->irq, cdev->version);
2108
2109 /* Probe finished
2110 * Stop clocks. They will be reactivated once the M_CAN device is opened
2111 */
2112 m_can_clk_stop(cdev);
2113
2114 return 0;
2115
2116 rx_offload_del:
2117 if (cdev->is_peripheral)
2118 can_rx_offload_del(&cdev->offload);
2119 clk_disable:
2120 m_can_clk_stop(cdev);
2121
2122 return ret;
2123 }
2124 EXPORT_SYMBOL_GPL(m_can_class_register);
2125
m_can_class_unregister(struct m_can_classdev * cdev)2126 void m_can_class_unregister(struct m_can_classdev *cdev)
2127 {
2128 if (cdev->is_peripheral)
2129 can_rx_offload_del(&cdev->offload);
2130 unregister_candev(cdev->net);
2131 }
2132 EXPORT_SYMBOL_GPL(m_can_class_unregister);
2133
m_can_class_suspend(struct device * dev)2134 int m_can_class_suspend(struct device *dev)
2135 {
2136 struct m_can_classdev *cdev = dev_get_drvdata(dev);
2137 struct net_device *ndev = cdev->net;
2138
2139 if (netif_running(ndev)) {
2140 netif_stop_queue(ndev);
2141 netif_device_detach(ndev);
2142 m_can_stop(ndev);
2143 m_can_clk_stop(cdev);
2144 }
2145
2146 pinctrl_pm_select_sleep_state(dev);
2147
2148 cdev->can.state = CAN_STATE_SLEEPING;
2149
2150 return 0;
2151 }
2152 EXPORT_SYMBOL_GPL(m_can_class_suspend);
2153
m_can_class_resume(struct device * dev)2154 int m_can_class_resume(struct device *dev)
2155 {
2156 struct m_can_classdev *cdev = dev_get_drvdata(dev);
2157 struct net_device *ndev = cdev->net;
2158
2159 pinctrl_pm_select_default_state(dev);
2160
2161 cdev->can.state = CAN_STATE_ERROR_ACTIVE;
2162
2163 if (netif_running(ndev)) {
2164 int ret;
2165
2166 ret = m_can_clk_start(cdev);
2167 if (ret)
2168 return ret;
2169 ret = m_can_start(ndev);
2170 if (ret) {
2171 m_can_clk_stop(cdev);
2172
2173 return ret;
2174 }
2175
2176 netif_device_attach(ndev);
2177 netif_start_queue(ndev);
2178 }
2179
2180 return 0;
2181 }
2182 EXPORT_SYMBOL_GPL(m_can_class_resume);
2183
2184 MODULE_AUTHOR("Dong Aisheng <b29396@freescale.com>");
2185 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com>");
2186 MODULE_LICENSE("GPL v2");
2187 MODULE_DESCRIPTION("CAN bus driver for Bosch M_CAN controller");
2188