xref: /openbmc/linux/drivers/net/ethernet/asix/ax88796c_main.h (revision 03ab8e6297acd1bc0eedaa050e2a1635c576fd11)
1  /* SPDX-License-Identifier: GPL-2.0-only */
2  /*
3   * Copyright (c) 2010 ASIX Electronics Corporation
4   * Copyright (c) 2020 Samsung Electronics
5   *
6   * ASIX AX88796C SPI Fast Ethernet Linux driver
7   */
8  
9  #ifndef _AX88796C_MAIN_H
10  #define _AX88796C_MAIN_H
11  
12  #include <linux/netdevice.h>
13  #include <linux/mii.h>
14  
15  #include "ax88796c_spi.h"
16  
17  /* These identify the driver base version and may not be removed. */
18  #define DRV_NAME	"ax88796c"
19  #define ADP_NAME	"ASIX AX88796C SPI Ethernet Adapter"
20  
21  #define TX_QUEUE_HIGH_WATER		45	/* Tx queue high water mark */
22  #define TX_QUEUE_LOW_WATER		20	/* Tx queue low water mark */
23  
24  #define AX88796C_REGDUMP_LEN		256
25  #define AX88796C_PHY_REGDUMP_LEN	14
26  #define AX88796C_PHY_ID			0x10
27  
28  #define TX_OVERHEAD			8
29  #define TX_EOP_SIZE			4
30  
31  #define AX_MCAST_FILTER_SIZE		8
32  #define AX_MAX_MCAST			64
33  #define AX_MAX_CLK                      80000000
34  #define TX_HDR_SOP_DICF			0x8000
35  #define TX_HDR_SOP_CPHI			0x4000
36  #define TX_HDR_SOP_INT			0x2000
37  #define TX_HDR_SOP_MDEQ			0x1000
38  #define TX_HDR_SOP_PKTLEN		0x07FF
39  #define TX_HDR_SOP_SEQNUM		0xF800
40  #define TX_HDR_SOP_PKTLENBAR		0x07FF
41  
42  #define TX_HDR_SEG_FS			0x8000
43  #define TX_HDR_SEG_LS			0x4000
44  #define TX_HDR_SEG_SEGNUM		0x3800
45  #define TX_HDR_SEG_SEGLEN		0x0700
46  #define TX_HDR_SEG_EOFST		0xC000
47  #define TX_HDR_SEG_SOFST		0x3800
48  #define TX_HDR_SEG_SEGLENBAR		0x07FF
49  
50  #define TX_HDR_EOP_SEQNUM		0xF800
51  #define TX_HDR_EOP_PKTLEN		0x07FF
52  #define TX_HDR_EOP_SEQNUMBAR		0xF800
53  #define TX_HDR_EOP_PKTLENBAR		0x07FF
54  
55  /* Rx header fields mask */
56  #define RX_HDR1_MCBC			0x8000
57  #define RX_HDR1_STUFF_PKT		0x4000
58  #define RX_HDR1_MII_ERR			0x2000
59  #define RX_HDR1_CRC_ERR			0x1000
60  #define RX_HDR1_PKT_LEN			0x07FF
61  
62  #define RX_HDR2_SEQ_NUM			0xF800
63  #define RX_HDR2_PKT_LEN_BAR		0x7FFF
64  
65  #define RX_HDR3_PE			0x8000
66  #define RX_HDR3_L3_TYPE_IPV4V6		0x6000
67  #define RX_HDR3_L3_TYPE_IP		0x4000
68  #define RX_HDR3_L3_TYPE_IPV6		0x2000
69  #define RX_HDR3_L4_TYPE_ICMPV6		0x1400
70  #define RX_HDR3_L4_TYPE_TCP		0x1000
71  #define RX_HDR3_L4_TYPE_IGMP		0x0c00
72  #define RX_HDR3_L4_TYPE_ICMP		0x0800
73  #define RX_HDR3_L4_TYPE_UDP		0x0400
74  #define RX_HDR3_L3_ERR			0x0200
75  #define RX_HDR3_L4_ERR			0x0100
76  #define RX_HDR3_PRIORITY(x)		((x) << 4)
77  #define RX_HDR3_STRIP			0x0008
78  #define RX_HDR3_VLAN_ID			0x0007
79  
80  struct ax88796c_pcpu_stats {
81  	u64_stats_t rx_packets;
82  	u64_stats_t rx_bytes;
83  	u64_stats_t tx_packets;
84  	u64_stats_t tx_bytes;
85  	struct u64_stats_sync syncp;
86  	u32 rx_dropped;
87  	u32 tx_dropped;
88  	u32 rx_frame_errors;
89  	u32 rx_crc_errors;
90  };
91  
92  struct ax88796c_device {
93  	struct spi_device	*spi;
94  	struct net_device	*ndev;
95  	struct ax88796c_pcpu_stats __percpu *stats;
96  
97  	struct work_struct	ax_work;
98  
99  	struct mutex		spi_lock; /* device access */
100  
101  	struct sk_buff_head	tx_wait_q;
102  
103  	struct axspi_data	ax_spi;
104  
105  	struct mii_bus		*mdiobus;
106  	struct phy_device	*phydev;
107  
108  	int			msg_enable;
109  
110  	u16			seq_num;
111  
112  	u8			multi_filter[AX_MCAST_FILTER_SIZE];
113  
114  	int			link;
115  	int			speed;
116  	int			duplex;
117  	int			pause;
118  	int			asym_pause;
119  	int			flowctrl;
120  		#define AX_FC_NONE		0
121  		#define AX_FC_RX		BIT(0)
122  		#define AX_FC_TX		BIT(1)
123  		#define AX_FC_ANEG		BIT(2)
124  
125  	u32			priv_flags;
126  		#define AX_CAP_COMP		BIT(0)
127  		#define AX_PRIV_FLAGS_MASK	(AX_CAP_COMP)
128  
129  	unsigned long		flags;
130  		#define EVENT_INTR		0
131  		#define EVENT_TX		1
132  		#define EVENT_SET_MULTI		2
133  
134  };
135  
136  #define to_ax88796c_device(ndev) ((struct ax88796c_device *)netdev_priv(ndev))
137  
138  enum skb_state {
139  	illegal = 0,
140  	tx_done,
141  	rx_done,
142  	rx_err,
143  };
144  
145  struct skb_data {
146  	enum skb_state state;
147  	size_t len;
148  };
149  
150  /* A88796C register definition */
151  	/* Definition of PAGE0 */
152  #define P0_PSR		(0x00)
153  	#define PSR_DEV_READY		BIT(7)
154  	#define PSR_RESET		(0 << 15)
155  	#define PSR_RESET_CLR		BIT(15)
156  #define P0_BOR		(0x02)
157  #define P0_FER		(0x04)
158  	#define FER_IPALM		BIT(0)
159  	#define FER_DCRC		BIT(1)
160  	#define FER_RH3M		BIT(2)
161  	#define FER_HEADERSWAP		BIT(7)
162  	#define FER_WSWAP		BIT(8)
163  	#define FER_BSWAP		BIT(9)
164  	#define FER_INTHI		BIT(10)
165  	#define FER_INTLO		(0 << 10)
166  	#define FER_IRQ_PULL		BIT(11)
167  	#define FER_RXEN		BIT(14)
168  	#define FER_TXEN		BIT(15)
169  #define P0_ISR		(0x06)
170  	#define ISR_RXPKT		BIT(0)
171  	#define ISR_MDQ			BIT(4)
172  	#define ISR_TXT			BIT(5)
173  	#define ISR_TXPAGES		BIT(6)
174  	#define ISR_TXERR		BIT(8)
175  	#define ISR_LINK		BIT(9)
176  #define P0_IMR		(0x08)
177  	#define IMR_RXPKT		BIT(0)
178  	#define IMR_MDQ			BIT(4)
179  	#define IMR_TXT			BIT(5)
180  	#define IMR_TXPAGES		BIT(6)
181  	#define IMR_TXERR		BIT(8)
182  	#define IMR_LINK		BIT(9)
183  	#define IMR_MASKALL		(0xFFFF)
184  	#define IMR_DEFAULT		(IMR_TXERR)
185  #define P0_WFCR		(0x0A)
186  	#define WFCR_PMEIND		BIT(0) /* PME indication */
187  	#define WFCR_PMETYPE		BIT(1) /* PME I/O type */
188  	#define WFCR_PMEPOL		BIT(2) /* PME polarity */
189  	#define WFCR_PMERST		BIT(3) /* Reset PME */
190  	#define WFCR_SLEEP		BIT(4) /* Enable sleep mode */
191  	#define WFCR_WAKEUP		BIT(5) /* Enable wakeup mode */
192  	#define WFCR_WAITEVENT		BIT(6) /* Reserved */
193  	#define WFCR_CLRWAKE		BIT(7) /* Clear wakeup */
194  	#define WFCR_LINKCH		BIT(8) /* Enable link change */
195  	#define WFCR_MAGICP		BIT(9) /* Enable magic packet */
196  	#define WFCR_WAKEF		BIT(10) /* Enable wakeup frame */
197  	#define WFCR_PMEEN		BIT(11) /* Enable PME pin */
198  	#define WFCR_LINKCHS		BIT(12) /* Link change status */
199  	#define WFCR_MAGICPS		BIT(13) /* Magic packet status */
200  	#define WFCR_WAKEFS		BIT(14) /* Wakeup frame status */
201  	#define WFCR_PMES		BIT(15) /* PME pin status */
202  #define P0_PSCR		(0x0C)
203  	#define PSCR_PS_MASK		(0xFFF0)
204  	#define PSCR_PS_D0		(0)
205  	#define PSCR_PS_D1		BIT(0)
206  	#define PSCR_PS_D2		BIT(1)
207  	#define PSCR_FPS		BIT(3) /* Enable fiber mode PS */
208  	#define PSCR_SWPS		BIT(4) /* Enable software */
209  						 /* PS control */
210  	#define PSCR_WOLPS		BIT(5) /* Enable WOL PS */
211  	#define PSCR_SWWOL		BIT(6) /* Enable software select */
212  						 /* WOL PS */
213  	#define PSCR_PHYOSC		BIT(7) /* Internal PHY OSC control */
214  	#define PSCR_FOFEF		BIT(8) /* Force PHY generate FEF */
215  	#define PSCR_FOF		BIT(9) /* Force PHY in fiber mode */
216  	#define PSCR_PHYPD		BIT(10) /* PHY power down. */
217  						  /* Active high */
218  	#define PSCR_PHYRST		BIT(11) /* PHY reset signal. */
219  						  /* Active low */
220  	#define PSCR_PHYCSIL		BIT(12) /* PHY cable energy detect */
221  	#define PSCR_PHYCOFF		BIT(13) /* PHY cable off */
222  	#define PSCR_PHYLINK		BIT(14) /* PHY link status */
223  	#define PSCR_EEPOK		BIT(15) /* EEPROM load complete */
224  #define P0_MACCR	(0x0E)
225  	#define MACCR_RXEN		BIT(0) /* Enable RX */
226  	#define MACCR_DUPLEX_FULL	BIT(1) /* 1: Full, 0: Half */
227  	#define MACCR_SPEED_100		BIT(2) /* 1: 100Mbps, 0: 10Mbps */
228  	#define MACCR_RXFC_ENABLE	BIT(3)
229  	#define MACCR_RXFC_MASK		0xFFF7
230  	#define MACCR_TXFC_ENABLE	BIT(4)
231  	#define MACCR_TXFC_MASK		0xFFEF
232  	#define MACCR_PSI		BIT(6) /* Software Cable-Off */
233  					       /* Power Saving Interrupt */
234  	#define MACCR_PF		BIT(7)
235  	#define MACCR_PMM_BITS		8
236  	#define MACCR_PMM_MASK		(0x1F00)
237  	#define MACCR_PMM_RESET		BIT(8)
238  	#define MACCR_PMM_WAIT		(2 << 8)
239  	#define MACCR_PMM_READY		(3 << 8)
240  	#define MACCR_PMM_D1		(4 << 8)
241  	#define MACCR_PMM_D2		(5 << 8)
242  	#define MACCR_PMM_WAKE		(7 << 8)
243  	#define MACCR_PMM_D1_WAKE	(8 << 8)
244  	#define MACCR_PMM_D2_WAKE	(9 << 8)
245  	#define MACCR_PMM_SLEEP		(10 << 8)
246  	#define MACCR_PMM_PHY_RESET	(11 << 8)
247  	#define MACCR_PMM_SOFT_D1	(16 << 8)
248  	#define MACCR_PMM_SOFT_D2	(17 << 8)
249  #define P0_TFBFCR	(0x10)
250  	#define TFBFCR_SCHE_FREE_PAGE	0xE07F
251  	#define TFBFCR_FREE_PAGE_BITS	0x07
252  	#define TFBFCR_FREE_PAGE_LATCH	BIT(6)
253  	#define TFBFCR_SET_FREE_PAGE(x)	(((x) & 0x3F) << TFBFCR_FREE_PAGE_BITS)
254  	#define TFBFCR_TX_PAGE_SET	BIT(13)
255  	#define TFBFCR_MANU_ENTX	BIT(15)
256  	#define TX_FREEBUF_MASK		0x003F
257  	#define TX_DPTSTART		0x4000
258  
259  #define P0_TSNR		(0x12)
260  	#define TXNR_TXB_ERR		BIT(5)
261  	#define TXNR_TXB_IDLE		BIT(6)
262  	#define TSNR_PKT_CNT(x)		(((x) & 0x3F) << 8)
263  	#define TXNR_TXB_REINIT		BIT(14)
264  	#define TSNR_TXB_START		BIT(15)
265  #define P0_RTDPR	(0x14)
266  #define P0_RXBCR1	(0x16)
267  	#define RXBCR1_RXB_DISCARD	BIT(14)
268  	#define RXBCR1_RXB_START	BIT(15)
269  #define P0_RXBCR2	(0x18)
270  	#define RXBCR2_PKT_MASK		(0xFF)
271  	#define RXBCR2_RXPC_MASK	(0x7F)
272  	#define RXBCR2_RXB_READY	BIT(13)
273  	#define RXBCR2_RXB_IDLE		BIT(14)
274  	#define RXBCR2_RXB_REINIT	BIT(15)
275  #define P0_RTWCR	(0x1A)
276  	#define RTWCR_RXWC_MASK		(0x3FFF)
277  	#define RTWCR_RX_LATCH		BIT(15)
278  #define P0_RCPHR	(0x1C)
279  
280  	/* Definition of PAGE1 */
281  #define P1_RPPER	(0x22)
282  	#define RPPER_RXEN		BIT(0)
283  #define P1_MRCR		(0x28)
284  #define P1_MDR		(0x2A)
285  #define P1_RMPR		(0x2C)
286  #define P1_TMPR		(0x2E)
287  #define P1_RXBSPCR	(0x30)
288  	#define RXBSPCR_STUF_WORD_CNT(x)	(((x) & 0x7000) >> 12)
289  	#define RXBSPCR_STUF_ENABLE		BIT(15)
290  #define P1_MCR		(0x32)
291  	#define MCR_SBP			BIT(8)
292  	#define MCR_SM			BIT(9)
293  	#define MCR_CRCENLAN		BIT(11)
294  	#define MCR_STP			BIT(12)
295  	/* Definition of PAGE2 */
296  #define P2_CIR		(0x42)
297  #define P2_PCR		(0x44)
298  	#define PCR_POLL_EN		BIT(0)
299  	#define PCR_POLL_FLOWCTRL	BIT(1)
300  	#define PCR_POLL_BMCR		BIT(2)
301  	#define PCR_PHYID(x)		((x) << 8)
302  #define P2_PHYSR	(0x46)
303  #define P2_MDIODR	(0x48)
304  #define P2_MDIOCR	(0x4A)
305  	#define MDIOCR_RADDR(x)		((x) & 0x1F)
306  	#define MDIOCR_FADDR(x)		(((x) & 0x1F) << 8)
307  	#define MDIOCR_VALID		BIT(13)
308  	#define MDIOCR_READ		BIT(14)
309  	#define MDIOCR_WRITE		BIT(15)
310  #define P2_LCR0		(0x4C)
311  	#define LCR_LED0_EN		BIT(0)
312  	#define LCR_LED0_100MODE	BIT(1)
313  	#define LCR_LED0_DUPLEX		BIT(2)
314  	#define LCR_LED0_LINK		BIT(3)
315  	#define LCR_LED0_ACT		BIT(4)
316  	#define LCR_LED0_COL		BIT(5)
317  	#define LCR_LED0_10MODE		BIT(6)
318  	#define LCR_LED0_DUPCOL		BIT(7)
319  	#define LCR_LED1_EN		BIT(8)
320  	#define LCR_LED1_100MODE	BIT(9)
321  	#define LCR_LED1_DUPLEX		BIT(10)
322  	#define LCR_LED1_LINK		BIT(11)
323  	#define LCR_LED1_ACT		BIT(12)
324  	#define LCR_LED1_COL		BIT(13)
325  	#define LCR_LED1_10MODE		BIT(14)
326  	#define LCR_LED1_DUPCOL		BIT(15)
327  #define P2_LCR1		(0x4E)
328  	#define LCR_LED2_MASK		(0xFF00)
329  	#define LCR_LED2_EN		BIT(0)
330  	#define LCR_LED2_100MODE	BIT(1)
331  	#define LCR_LED2_DUPLEX		BIT(2)
332  	#define LCR_LED2_LINK		BIT(3)
333  	#define LCR_LED2_ACT		BIT(4)
334  	#define LCR_LED2_COL		BIT(5)
335  	#define LCR_LED2_10MODE		BIT(6)
336  	#define LCR_LED2_DUPCOL		BIT(7)
337  #define P2_IPGCR	(0x50)
338  #define P2_CRIR		(0x52)
339  #define P2_FLHWCR	(0x54)
340  #define P2_RXCR		(0x56)
341  	#define RXCR_PRO		BIT(0)
342  	#define RXCR_AMALL		BIT(1)
343  	#define RXCR_SEP		BIT(2)
344  	#define RXCR_AB			BIT(3)
345  	#define RXCR_AM			BIT(4)
346  	#define RXCR_AP			BIT(5)
347  	#define RXCR_ARP		BIT(6)
348  #define P2_JLCR		(0x58)
349  #define P2_MPLR		(0x5C)
350  
351  	/* Definition of PAGE3 */
352  #define P3_MACASR0	(0x62)
353  	#define P3_MACASR(x)		(P3_MACASR0 + 2 * (x))
354  	#define MACASR_LOWBYTE_MASK	0x00FF
355  	#define MACASR_HIGH_BITS	0x08
356  #define P3_MACASR1	(0x64)
357  #define P3_MACASR2	(0x66)
358  #define P3_MFAR01	(0x68)
359  #define P3_MFAR_BASE	(0x68)
360  	#define P3_MFAR(x)		(P3_MFAR_BASE + 2 * (x))
361  
362  #define P3_MFAR23	(0x6A)
363  #define P3_MFAR45	(0x6C)
364  #define P3_MFAR67	(0x6E)
365  #define P3_VID0FR	(0x70)
366  #define P3_VID1FR	(0x72)
367  #define P3_EECSR	(0x74)
368  #define P3_EEDR		(0x76)
369  #define P3_EECR		(0x78)
370  	#define EECR_ADDR_MASK		(0x00FF)
371  	#define EECR_READ_ACT		BIT(8)
372  	#define EECR_WRITE_ACT		BIT(9)
373  	#define EECR_WRITE_DISABLE	BIT(10)
374  	#define EECR_WRITE_ENABLE	BIT(11)
375  	#define EECR_EE_READY		BIT(13)
376  	#define EECR_RELOAD		BIT(14)
377  	#define EECR_RESET		BIT(15)
378  #define P3_TPCR		(0x7A)
379  	#define TPCR_PATT_MASK		(0xFF)
380  	#define TPCR_RAND_PKT_EN	BIT(14)
381  	#define TPCR_FIXED_PKT_EN	BIT(15)
382  #define P3_TPLR		(0x7C)
383  	/* Definition of PAGE4 */
384  #define P4_SPICR	(0x8A)
385  	#define SPICR_RCEN		BIT(0)
386  	#define SPICR_QCEN		BIT(1)
387  	#define SPICR_RBRE		BIT(3)
388  	#define SPICR_PMM		BIT(4)
389  	#define SPICR_LOOPBACK		BIT(8)
390  	#define SPICR_CORE_RES_CLR	BIT(10)
391  	#define SPICR_SPI_RES_CLR	BIT(11)
392  #define P4_SPIISMR	(0x8C)
393  
394  #define P4_COERCR0	(0x92)
395  	#define COERCR0_RXIPCE		BIT(0)
396  	#define COERCR0_RXIPVE		BIT(1)
397  	#define COERCR0_RXV6PE		BIT(2)
398  	#define COERCR0_RXTCPE		BIT(3)
399  	#define COERCR0_RXUDPE		BIT(4)
400  	#define COERCR0_RXICMP		BIT(5)
401  	#define COERCR0_RXIGMP		BIT(6)
402  	#define COERCR0_RXICV6		BIT(7)
403  
404  	#define COERCR0_RXTCPV6		BIT(8)
405  	#define COERCR0_RXUDPV6		BIT(9)
406  	#define COERCR0_RXICMV6		BIT(10)
407  	#define COERCR0_RXIGMV6		BIT(11)
408  	#define COERCR0_RXICV6V6	BIT(12)
409  
410  	#define COERCR0_DEFAULT		(COERCR0_RXIPCE | COERCR0_RXV6PE | \
411  					 COERCR0_RXTCPE | COERCR0_RXUDPE | \
412  					 COERCR0_RXTCPV6 | COERCR0_RXUDPV6)
413  #define P4_COERCR1	(0x94)
414  	#define COERCR1_IPCEDP		BIT(0)
415  	#define COERCR1_IPVEDP		BIT(1)
416  	#define COERCR1_V6VEDP		BIT(2)
417  	#define COERCR1_TCPEDP		BIT(3)
418  	#define COERCR1_UDPEDP		BIT(4)
419  	#define COERCR1_ICMPDP		BIT(5)
420  	#define COERCR1_IGMPDP		BIT(6)
421  	#define COERCR1_ICV6DP		BIT(7)
422  	#define COERCR1_RX64TE		BIT(8)
423  	#define COERCR1_RXPPPE		BIT(9)
424  	#define COERCR1_TCP6DP		BIT(10)
425  	#define COERCR1_UDP6DP		BIT(11)
426  	#define COERCR1_IC6DP		BIT(12)
427  	#define COERCR1_IG6DP		BIT(13)
428  	#define COERCR1_ICV66DP		BIT(14)
429  	#define COERCR1_RPCE		BIT(15)
430  
431  	#define COERCR1_DEFAULT		(COERCR1_RXPPPE)
432  
433  #define P4_COETCR0	(0x96)
434  	#define COETCR0_TXIP		BIT(0)
435  	#define COETCR0_TXTCP		BIT(1)
436  	#define COETCR0_TXUDP		BIT(2)
437  	#define COETCR0_TXICMP		BIT(3)
438  	#define COETCR0_TXIGMP		BIT(4)
439  	#define COETCR0_TXICV6		BIT(5)
440  	#define COETCR0_TXTCPV6		BIT(8)
441  	#define COETCR0_TXUDPV6		BIT(9)
442  	#define COETCR0_TXICMV6		BIT(10)
443  	#define COETCR0_TXIGMV6		BIT(11)
444  	#define COETCR0_TXICV6V6	BIT(12)
445  
446  	#define COETCR0_DEFAULT		(COETCR0_TXIP | COETCR0_TXTCP | \
447  					 COETCR0_TXUDP | COETCR0_TXTCPV6 | \
448  					 COETCR0_TXUDPV6)
449  #define P4_COETCR1	(0x98)
450  	#define COETCR1_TX64TE		BIT(0)
451  	#define COETCR1_TXPPPE		BIT(1)
452  
453  #define P4_COECEDR	(0x9A)
454  #define P4_L2CECR	(0x9C)
455  
456  	/* Definition of PAGE5 */
457  #define P5_WFTR		(0xA2)
458  	#define WFTR_2MS		(0x01)
459  	#define WFTR_4MS		(0x02)
460  	#define WFTR_8MS		(0x03)
461  	#define WFTR_16MS		(0x04)
462  	#define WFTR_32MS		(0x05)
463  	#define WFTR_64MS		(0x06)
464  	#define WFTR_128MS		(0x07)
465  	#define WFTR_256MS		(0x08)
466  	#define WFTR_512MS		(0x09)
467  	#define WFTR_1024MS		(0x0A)
468  	#define WFTR_2048MS		(0x0B)
469  	#define WFTR_4096MS		(0x0C)
470  	#define WFTR_8192MS		(0x0D)
471  	#define WFTR_16384MS		(0x0E)
472  	#define WFTR_32768MS		(0x0F)
473  #define P5_WFCCR	(0xA4)
474  #define P5_WFCR03	(0xA6)
475  	#define WFCR03_F0_EN		BIT(0)
476  	#define WFCR03_F1_EN		BIT(4)
477  	#define WFCR03_F2_EN		BIT(8)
478  	#define WFCR03_F3_EN		BIT(12)
479  #define P5_WFCR47	(0xA8)
480  	#define WFCR47_F4_EN		BIT(0)
481  	#define WFCR47_F5_EN		BIT(4)
482  	#define WFCR47_F6_EN		BIT(8)
483  	#define WFCR47_F7_EN		BIT(12)
484  #define P5_WF0BMR0	(0xAA)
485  #define P5_WF0BMR1	(0xAC)
486  #define P5_WF0CR	(0xAE)
487  #define P5_WF0OBR	(0xB0)
488  #define P5_WF1BMR0	(0xB2)
489  #define P5_WF1BMR1	(0xB4)
490  #define P5_WF1CR	(0xB6)
491  #define P5_WF1OBR	(0xB8)
492  #define P5_WF2BMR0	(0xBA)
493  #define P5_WF2BMR1	(0xBC)
494  
495  	/* Definition of PAGE6 */
496  #define P6_WF2CR	(0xC2)
497  #define P6_WF2OBR	(0xC4)
498  #define P6_WF3BMR0	(0xC6)
499  #define P6_WF3BMR1	(0xC8)
500  #define P6_WF3CR	(0xCA)
501  #define P6_WF3OBR	(0xCC)
502  #define P6_WF4BMR0	(0xCE)
503  #define P6_WF4BMR1	(0xD0)
504  #define P6_WF4CR	(0xD2)
505  #define P6_WF4OBR	(0xD4)
506  #define P6_WF5BMR0	(0xD6)
507  #define P6_WF5BMR1	(0xD8)
508  #define P6_WF5CR	(0xDA)
509  #define P6_WF5OBR	(0xDC)
510  
511  /* Definition of PAGE7 */
512  #define P7_WF6BMR0	(0xE2)
513  #define P7_WF6BMR1	(0xE4)
514  #define P7_WF6CR	(0xE6)
515  #define P7_WF6OBR	(0xE8)
516  #define P7_WF7BMR0	(0xEA)
517  #define P7_WF7BMR1	(0xEC)
518  #define P7_WF7CR	(0xEE)
519  #define P7_WF7OBR	(0xF0)
520  #define P7_WFR01	(0xF2)
521  #define P7_WFR23	(0xF4)
522  #define P7_WFR45	(0xF6)
523  #define P7_WFR67	(0xF8)
524  #define P7_WFPC0	(0xFA)
525  #define P7_WFPC1	(0xFC)
526  
527  /* Tx headers structure */
528  struct tx_sop_header {
529  	/* bit 15-11: flags, bit 10-0: packet length */
530  	u16 flags_len;
531  	/* bit 15-11: sequence number, bit 11-0: packet length bar */
532  	u16 seq_lenbar;
533  };
534  
535  struct tx_segment_header {
536  	/* bit 15-14: flags, bit 13-11: segment number */
537  	/* bit 10-0: segment length */
538  	u16 flags_seqnum_seglen;
539  	/* bit 15-14: end offset, bit 13-11: start offset */
540  	/* bit 10-0: segment length bar */
541  	u16 eo_so_seglenbar;
542  };
543  
544  struct tx_eop_header {
545  	/* bit 15-11: sequence number, bit 10-0: packet length */
546  	u16 seq_len;
547  	/* bit 15-11: sequence number bar, bit 10-0: packet length bar */
548  	u16 seqbar_lenbar;
549  };
550  
551  struct tx_pkt_info {
552  	struct tx_sop_header sop;
553  	struct tx_segment_header seg;
554  	struct tx_eop_header eop;
555  	u16 pkt_len;
556  	u16 seq_num;
557  };
558  
559  /* Rx headers structure */
560  struct rx_header {
561  	u16 flags_len;
562  	u16 seq_lenbar;
563  	u16 flags;
564  };
565  
566  extern unsigned long ax88796c_no_regs_mask[];
567  
568  #endif /* #ifndef _AX88796C_MAIN_H */
569