xref: /openbmc/linux/sound/soc/codecs/tscs42xx.h (revision 53af408c)
1 // SPDX-License-Identifier: GPL-2.0
2 // tscs42xx.h -- TSCS42xx ALSA SoC Audio driver
3 // Copyright 2017 Tempo Semiconductor, Inc.
4 // Author: Steven Eckhoff <steven.eckhoff.opensource@gmail.com>
5 
6 #ifndef __WOOKIE_H__
7 #define __WOOKIE_H__
8 
9 enum {
10 	TSCS42XX_PLL_SRC_XTAL,
11 	TSCS42XX_PLL_SRC_MCLK1,
12 	TSCS42XX_PLL_SRC_MCLK2,
13 	TSCS42XX_PLL_SRC_CNT,
14 };
15 
16 #define R_HPVOLL        0x0
17 #define R_HPVOLR        0x1
18 #define R_SPKVOLL       0x2
19 #define R_SPKVOLR       0x3
20 #define R_DACVOLL       0x4
21 #define R_DACVOLR       0x5
22 #define R_ADCVOLL       0x6
23 #define R_ADCVOLR       0x7
24 #define R_INVOLL        0x8
25 #define R_INVOLR        0x9
26 #define R_INMODE        0x0B
27 #define R_INSELL        0x0C
28 #define R_INSELR        0x0D
29 #define R_AIC1          0x13
30 #define R_AIC2          0x14
31 #define R_CNVRTR0       0x16
32 #define R_ADCSR         0x17
33 #define R_CNVRTR1       0x18
34 #define R_DACSR         0x19
35 #define R_PWRM1         0x1A
36 #define R_PWRM2         0x1B
37 #define R_CTL		0x1C
38 #define R_CONFIG0       0x1F
39 #define R_CONFIG1       0x20
40 #define R_DMICCTL       0x24
41 #define R_CLECTL        0x25
42 #define R_MUGAIN        0x26
43 #define R_COMPTH        0x27
44 #define R_CMPRAT        0x28
45 #define R_CATKTCL       0x29
46 #define R_CATKTCH       0x2A
47 #define R_CRELTCL       0x2B
48 #define R_CRELTCH       0x2C
49 #define R_LIMTH         0x2D
50 #define R_LIMTGT        0x2E
51 #define R_LATKTCL       0x2F
52 #define R_LATKTCH       0x30
53 #define R_LRELTCL       0x31
54 #define R_LRELTCH       0x32
55 #define R_EXPTH         0x33
56 #define R_EXPRAT        0x34
57 #define R_XATKTCL       0x35
58 #define R_XATKTCH       0x36
59 #define R_XRELTCL       0x37
60 #define R_XRELTCH       0x38
61 #define R_FXCTL         0x39
62 #define R_DACCRWRL      0x3A
63 #define R_DACCRWRM      0x3B
64 #define R_DACCRWRH      0x3C
65 #define R_DACCRRDL      0x3D
66 #define R_DACCRRDM      0x3E
67 #define R_DACCRRDH      0x3F
68 #define R_DACCRADDR     0x40
69 #define R_DCOFSEL       0x41
70 #define R_PLLCTL9       0x4E
71 #define R_PLLCTLA       0x4F
72 #define R_PLLCTLB       0x50
73 #define R_PLLCTLC       0x51
74 #define R_PLLCTLD       0x52
75 #define R_PLLCTLE       0x53
76 #define R_PLLCTLF       0x54
77 #define R_PLLCTL10      0x55
78 #define R_PLLCTL11      0x56
79 #define R_PLLCTL12      0x57
80 #define R_PLLCTL1B      0x60
81 #define R_PLLCTL1C      0x61
82 #define R_TIMEBASE      0x77
83 #define R_DEVIDL        0x7D
84 #define R_DEVIDH        0x7E
85 #define R_RESET         0x80
86 #define R_DACCRSTAT     0x8A
87 #define R_PLLCTL0       0x8E
88 #define R_PLLREFSEL     0x8F
89 #define R_DACMBCEN      0xC7
90 #define R_DACMBCCTL     0xC8
91 #define R_DACMBCMUG1    0xC9
92 #define R_DACMBCTHR1    0xCA
93 #define R_DACMBCRAT1    0xCB
94 #define R_DACMBCATK1L   0xCC
95 #define R_DACMBCATK1H   0xCD
96 #define R_DACMBCREL1L   0xCE
97 #define R_DACMBCREL1H   0xCF
98 #define R_DACMBCMUG2    0xD0
99 #define R_DACMBCTHR2    0xD1
100 #define R_DACMBCRAT2    0xD2
101 #define R_DACMBCATK2L   0xD3
102 #define R_DACMBCATK2H   0xD4
103 #define R_DACMBCREL2L   0xD5
104 #define R_DACMBCREL2H   0xD6
105 #define R_DACMBCMUG3    0xD7
106 #define R_DACMBCTHR3    0xD8
107 #define R_DACMBCRAT3    0xD9
108 #define R_DACMBCATK3L   0xDA
109 #define R_DACMBCATK3H   0xDB
110 #define R_DACMBCREL3L   0xDC
111 #define R_DACMBCREL3H   0xDD
112 
113 /* Helpers */
114 #define RM(m, b) ((m)<<(b))
115 #define RV(v, b) ((v)<<(b))
116 
117 /****************************
118  *      R_HPVOLL (0x0)      *
119  ****************************/
120 
121 /* Field Offsets */
122 #define FB_HPVOLL                            0
123 
124 /* Field Masks */
125 #define FM_HPVOLL                            0X7F
126 
127 /* Field Values */
128 #define FV_HPVOLL_P6DB                       0x7F
129 #define FV_HPVOLL_N88PT5DB                   0x1
130 #define FV_HPVOLL_MUTE                       0x0
131 
132 /* Register Masks */
133 #define RM_HPVOLL                            RM(FM_HPVOLL, FB_HPVOLL)
134 
135 /* Register Values */
136 #define RV_HPVOLL_P6DB                       RV(FV_HPVOLL_P6DB, FB_HPVOLL)
137 #define RV_HPVOLL_N88PT5DB                   RV(FV_HPVOLL_N88PT5DB, FB_HPVOLL)
138 #define RV_HPVOLL_MUTE                       RV(FV_HPVOLL_MUTE, FB_HPVOLL)
139 
140 /****************************
141  *      R_HPVOLR (0x1)      *
142  ****************************/
143 
144 /* Field Offsets */
145 #define FB_HPVOLR                            0
146 
147 /* Field Masks */
148 #define FM_HPVOLR                            0X7F
149 
150 /* Field Values */
151 #define FV_HPVOLR_P6DB                       0x7F
152 #define FV_HPVOLR_N88PT5DB                   0x1
153 #define FV_HPVOLR_MUTE                       0x0
154 
155 /* Register Masks */
156 #define RM_HPVOLR                            RM(FM_HPVOLR, FB_HPVOLR)
157 
158 /* Register Values */
159 #define RV_HPVOLR_P6DB                       RV(FV_HPVOLR_P6DB, FB_HPVOLR)
160 #define RV_HPVOLR_N88PT5DB                   RV(FV_HPVOLR_N88PT5DB, FB_HPVOLR)
161 #define RV_HPVOLR_MUTE                       RV(FV_HPVOLR_MUTE, FB_HPVOLR)
162 
163 /*****************************
164  *      R_SPKVOLL (0x2)      *
165  *****************************/
166 
167 /* Field Offsets */
168 #define FB_SPKVOLL                           0
169 
170 /* Field Masks */
171 #define FM_SPKVOLL                           0X7F
172 
173 /* Field Values */
174 #define FV_SPKVOLL_P12DB                     0x7F
175 #define FV_SPKVOLL_N77PT25DB                 0x8
176 #define FV_SPKVOLL_MUTE                      0x0
177 
178 /* Register Masks */
179 #define RM_SPKVOLL                           RM(FM_SPKVOLL, FB_SPKVOLL)
180 
181 /* Register Values */
182 #define RV_SPKVOLL_P12DB                     RV(FV_SPKVOLL_P12DB, FB_SPKVOLL)
183 #define RV_SPKVOLL_N77PT25DB \
184 	 RV(FV_SPKVOLL_N77PT25DB, FB_SPKVOLL)
185 
186 #define RV_SPKVOLL_MUTE                      RV(FV_SPKVOLL_MUTE, FB_SPKVOLL)
187 
188 /*****************************
189  *      R_SPKVOLR (0x3)      *
190  *****************************/
191 
192 /* Field Offsets */
193 #define FB_SPKVOLR                           0
194 
195 /* Field Masks */
196 #define FM_SPKVOLR                           0X7F
197 
198 /* Field Values */
199 #define FV_SPKVOLR_P12DB                     0x7F
200 #define FV_SPKVOLR_N77PT25DB                 0x8
201 #define FV_SPKVOLR_MUTE                      0x0
202 
203 /* Register Masks */
204 #define RM_SPKVOLR                           RM(FM_SPKVOLR, FB_SPKVOLR)
205 
206 /* Register Values */
207 #define RV_SPKVOLR_P12DB                     RV(FV_SPKVOLR_P12DB, FB_SPKVOLR)
208 #define RV_SPKVOLR_N77PT25DB \
209 	 RV(FV_SPKVOLR_N77PT25DB, FB_SPKVOLR)
210 
211 #define RV_SPKVOLR_MUTE                      RV(FV_SPKVOLR_MUTE, FB_SPKVOLR)
212 
213 /*****************************
214  *      R_DACVOLL (0x4)      *
215  *****************************/
216 
217 /* Field Offsets */
218 #define FB_DACVOLL                           0
219 
220 /* Field Masks */
221 #define FM_DACVOLL                           0XFF
222 
223 /* Field Values */
224 #define FV_DACVOLL_0DB                       0xFF
225 #define FV_DACVOLL_N95PT625DB                0x1
226 #define FV_DACVOLL_MUTE                      0x0
227 
228 /* Register Masks */
229 #define RM_DACVOLL                           RM(FM_DACVOLL, FB_DACVOLL)
230 
231 /* Register Values */
232 #define RV_DACVOLL_0DB                       RV(FV_DACVOLL_0DB, FB_DACVOLL)
233 #define RV_DACVOLL_N95PT625DB \
234 	 RV(FV_DACVOLL_N95PT625DB, FB_DACVOLL)
235 
236 #define RV_DACVOLL_MUTE                      RV(FV_DACVOLL_MUTE, FB_DACVOLL)
237 
238 /*****************************
239  *      R_DACVOLR (0x5)      *
240  *****************************/
241 
242 /* Field Offsets */
243 #define FB_DACVOLR                           0
244 
245 /* Field Masks */
246 #define FM_DACVOLR                           0XFF
247 
248 /* Field Values */
249 #define FV_DACVOLR_0DB                       0xFF
250 #define FV_DACVOLR_N95PT625DB                0x1
251 #define FV_DACVOLR_MUTE                      0x0
252 
253 /* Register Masks */
254 #define RM_DACVOLR                           RM(FM_DACVOLR, FB_DACVOLR)
255 
256 /* Register Values */
257 #define RV_DACVOLR_0DB                       RV(FV_DACVOLR_0DB, FB_DACVOLR)
258 #define RV_DACVOLR_N95PT625DB \
259 	 RV(FV_DACVOLR_N95PT625DB, FB_DACVOLR)
260 
261 #define RV_DACVOLR_MUTE                      RV(FV_DACVOLR_MUTE, FB_DACVOLR)
262 
263 /*****************************
264  *      R_ADCVOLL (0x6)      *
265  *****************************/
266 
267 /* Field Offsets */
268 #define FB_ADCVOLL                           0
269 
270 /* Field Masks */
271 #define FM_ADCVOLL                           0XFF
272 
273 /* Field Values */
274 #define FV_ADCVOLL_P24DB                     0xFF
275 #define FV_ADCVOLL_N71PT25DB                 0x1
276 #define FV_ADCVOLL_MUTE                      0x0
277 
278 /* Register Masks */
279 #define RM_ADCVOLL                           RM(FM_ADCVOLL, FB_ADCVOLL)
280 
281 /* Register Values */
282 #define RV_ADCVOLL_P24DB                     RV(FV_ADCVOLL_P24DB, FB_ADCVOLL)
283 #define RV_ADCVOLL_N71PT25DB \
284 	 RV(FV_ADCVOLL_N71PT25DB, FB_ADCVOLL)
285 
286 #define RV_ADCVOLL_MUTE                      RV(FV_ADCVOLL_MUTE, FB_ADCVOLL)
287 
288 /*****************************
289  *      R_ADCVOLR (0x7)      *
290  *****************************/
291 
292 /* Field Offsets */
293 #define FB_ADCVOLR                           0
294 
295 /* Field Masks */
296 #define FM_ADCVOLR                           0XFF
297 
298 /* Field Values */
299 #define FV_ADCVOLR_P24DB                     0xFF
300 #define FV_ADCVOLR_N71PT25DB                 0x1
301 #define FV_ADCVOLR_MUTE                      0x0
302 
303 /* Register Masks */
304 #define RM_ADCVOLR                           RM(FM_ADCVOLR, FB_ADCVOLR)
305 
306 /* Register Values */
307 #define RV_ADCVOLR_P24DB                     RV(FV_ADCVOLR_P24DB, FB_ADCVOLR)
308 #define RV_ADCVOLR_N71PT25DB \
309 	 RV(FV_ADCVOLR_N71PT25DB, FB_ADCVOLR)
310 
311 #define RV_ADCVOLR_MUTE                      RV(FV_ADCVOLR_MUTE, FB_ADCVOLR)
312 
313 /****************************
314  *      R_INVOLL (0x8)      *
315  ****************************/
316 
317 /* Field Offsets */
318 #define FB_INVOLL_INMUTEL                    7
319 #define FB_INVOLL_IZCL                       6
320 #define FB_INVOLL                            0
321 
322 /* Field Masks */
323 #define FM_INVOLL_INMUTEL                    0X1
324 #define FM_INVOLL_IZCL                       0X1
325 #define FM_INVOLL                            0X3F
326 
327 /* Field Values */
328 #define FV_INVOLL_INMUTEL_ENABLE             0x1
329 #define FV_INVOLL_INMUTEL_DISABLE            0x0
330 #define FV_INVOLL_IZCL_ENABLE                0x1
331 #define FV_INVOLL_IZCL_DISABLE               0x0
332 #define FV_INVOLL_P30DB                      0x3F
333 #define FV_INVOLL_N17PT25DB                  0x0
334 
335 /* Register Masks */
336 #define RM_INVOLL_INMUTEL \
337 	 RM(FM_INVOLL_INMUTEL, FB_INVOLL_INMUTEL)
338 
339 #define RM_INVOLL_IZCL                       RM(FM_INVOLL_IZCL, FB_INVOLL_IZCL)
340 #define RM_INVOLL                            RM(FM_INVOLL, FB_INVOLL)
341 
342 /* Register Values */
343 #define RV_INVOLL_INMUTEL_ENABLE \
344 	 RV(FV_INVOLL_INMUTEL_ENABLE, FB_INVOLL_INMUTEL)
345 
346 #define RV_INVOLL_INMUTEL_DISABLE \
347 	 RV(FV_INVOLL_INMUTEL_DISABLE, FB_INVOLL_INMUTEL)
348 
349 #define RV_INVOLL_IZCL_ENABLE \
350 	 RV(FV_INVOLL_IZCL_ENABLE, FB_INVOLL_IZCL)
351 
352 #define RV_INVOLL_IZCL_DISABLE \
353 	 RV(FV_INVOLL_IZCL_DISABLE, FB_INVOLL_IZCL)
354 
355 #define RV_INVOLL_P30DB                      RV(FV_INVOLL_P30DB, FB_INVOLL)
356 #define RV_INVOLL_N17PT25DB                  RV(FV_INVOLL_N17PT25DB, FB_INVOLL)
357 
358 /****************************
359  *      R_INVOLR (0x9)      *
360  ****************************/
361 
362 /* Field Offsets */
363 #define FB_INVOLR_INMUTER                    7
364 #define FB_INVOLR_IZCR                       6
365 #define FB_INVOLR                            0
366 
367 /* Field Masks */
368 #define FM_INVOLR_INMUTER                    0X1
369 #define FM_INVOLR_IZCR                       0X1
370 #define FM_INVOLR                            0X3F
371 
372 /* Field Values */
373 #define FV_INVOLR_INMUTER_ENABLE             0x1
374 #define FV_INVOLR_INMUTER_DISABLE            0x0
375 #define FV_INVOLR_IZCR_ENABLE                0x1
376 #define FV_INVOLR_IZCR_DISABLE               0x0
377 #define FV_INVOLR_P30DB                      0x3F
378 #define FV_INVOLR_N17PT25DB                  0x0
379 
380 /* Register Masks */
381 #define RM_INVOLR_INMUTER \
382 	 RM(FM_INVOLR_INMUTER, FB_INVOLR_INMUTER)
383 
384 #define RM_INVOLR_IZCR                       RM(FM_INVOLR_IZCR, FB_INVOLR_IZCR)
385 #define RM_INVOLR                            RM(FM_INVOLR, FB_INVOLR)
386 
387 /* Register Values */
388 #define RV_INVOLR_INMUTER_ENABLE \
389 	 RV(FV_INVOLR_INMUTER_ENABLE, FB_INVOLR_INMUTER)
390 
391 #define RV_INVOLR_INMUTER_DISABLE \
392 	 RV(FV_INVOLR_INMUTER_DISABLE, FB_INVOLR_INMUTER)
393 
394 #define RV_INVOLR_IZCR_ENABLE \
395 	 RV(FV_INVOLR_IZCR_ENABLE, FB_INVOLR_IZCR)
396 
397 #define RV_INVOLR_IZCR_DISABLE \
398 	 RV(FV_INVOLR_IZCR_DISABLE, FB_INVOLR_IZCR)
399 
400 #define RV_INVOLR_P30DB                      RV(FV_INVOLR_P30DB, FB_INVOLR)
401 #define RV_INVOLR_N17PT25DB                  RV(FV_INVOLR_N17PT25DB, FB_INVOLR)
402 
403 /*****************************
404  *      R_INMODE (0x0B)      *
405  *****************************/
406 
407 /* Field Offsets */
408 #define FB_INMODE_DS                         0
409 
410 /* Field Masks */
411 #define FM_INMODE_DS                         0X1
412 
413 /* Field Values */
414 #define FV_INMODE_DS_LRIN1                   0x0
415 #define FV_INMODE_DS_LRIN2                   0x1
416 
417 /* Register Masks */
418 #define RM_INMODE_DS                         RM(FM_INMODE_DS, FB_INMODE_DS)
419 
420 /* Register Values */
421 #define RV_INMODE_DS_LRIN1 \
422 	 RV(FV_INMODE_DS_LRIN1, FB_INMODE_DS)
423 
424 #define RV_INMODE_DS_LRIN2 \
425 	 RV(FV_INMODE_DS_LRIN2, FB_INMODE_DS)
426 
427 
428 /*****************************
429  *      R_INSELL (0x0C)      *
430  *****************************/
431 
432 /* Field Offsets */
433 #define FB_INSELL                            6
434 #define FB_INSELL_MICBSTL                    4
435 
436 /* Field Masks */
437 #define FM_INSELL                            0X3
438 #define FM_INSELL_MICBSTL                    0X3
439 
440 /* Field Values */
441 #define FV_INSELL_IN1                        0x0
442 #define FV_INSELL_IN2                        0x1
443 #define FV_INSELL_IN3                        0x2
444 #define FV_INSELL_D2S                        0x3
445 #define FV_INSELL_MICBSTL_OFF                0x0
446 #define FV_INSELL_MICBSTL_10DB               0x1
447 #define FV_INSELL_MICBSTL_20DB               0x2
448 #define FV_INSELL_MICBSTL_30DB               0x3
449 
450 /* Register Masks */
451 #define RM_INSELL                            RM(FM_INSELL, FB_INSELL)
452 #define RM_INSELL_MICBSTL \
453 	 RM(FM_INSELL_MICBSTL, FB_INSELL_MICBSTL)
454 
455 
456 /* Register Values */
457 #define RV_INSELL_IN1                        RV(FV_INSELL_IN1, FB_INSELL)
458 #define RV_INSELL_IN2                        RV(FV_INSELL_IN2, FB_INSELL)
459 #define RV_INSELL_IN3                        RV(FV_INSELL_IN3, FB_INSELL)
460 #define RV_INSELL_D2S                        RV(FV_INSELL_D2S, FB_INSELL)
461 #define RV_INSELL_MICBSTL_OFF \
462 	 RV(FV_INSELL_MICBSTL_OFF, FB_INSELL_MICBSTL)
463 
464 #define RV_INSELL_MICBSTL_10DB \
465 	 RV(FV_INSELL_MICBSTL_10DB, FB_INSELL_MICBSTL)
466 
467 #define RV_INSELL_MICBSTL_20DB \
468 	 RV(FV_INSELL_MICBSTL_20DB, FB_INSELL_MICBSTL)
469 
470 #define RV_INSELL_MICBSTL_30DB \
471 	 RV(FV_INSELL_MICBSTL_30DB, FB_INSELL_MICBSTL)
472 
473 
474 /*****************************
475  *      R_INSELR (0x0D)      *
476  *****************************/
477 
478 /* Field Offsets */
479 #define FB_INSELR                            6
480 #define FB_INSELR_MICBSTR                    4
481 
482 /* Field Masks */
483 #define FM_INSELR                            0X3
484 #define FM_INSELR_MICBSTR                    0X3
485 
486 /* Field Values */
487 #define FV_INSELR_IN1                        0x0
488 #define FV_INSELR_IN2                        0x1
489 #define FV_INSELR_IN3                        0x2
490 #define FV_INSELR_D2S                        0x3
491 #define FV_INSELR_MICBSTR_OFF                0x0
492 #define FV_INSELR_MICBSTR_10DB               0x1
493 #define FV_INSELR_MICBSTR_20DB               0x2
494 #define FV_INSELR_MICBSTR_30DB               0x3
495 
496 /* Register Masks */
497 #define RM_INSELR                            RM(FM_INSELR, FB_INSELR)
498 #define RM_INSELR_MICBSTR \
499 	 RM(FM_INSELR_MICBSTR, FB_INSELR_MICBSTR)
500 
501 
502 /* Register Values */
503 #define RV_INSELR_IN1                        RV(FV_INSELR_IN1, FB_INSELR)
504 #define RV_INSELR_IN2                        RV(FV_INSELR_IN2, FB_INSELR)
505 #define RV_INSELR_IN3                        RV(FV_INSELR_IN3, FB_INSELR)
506 #define RV_INSELR_D2S                        RV(FV_INSELR_D2S, FB_INSELR)
507 #define RV_INSELR_MICBSTR_OFF \
508 	 RV(FV_INSELR_MICBSTR_OFF, FB_INSELR_MICBSTR)
509 
510 #define RV_INSELR_MICBSTR_10DB \
511 	 RV(FV_INSELR_MICBSTR_10DB, FB_INSELR_MICBSTR)
512 
513 #define RV_INSELR_MICBSTR_20DB \
514 	 RV(FV_INSELR_MICBSTR_20DB, FB_INSELR_MICBSTR)
515 
516 #define RV_INSELR_MICBSTR_30DB \
517 	 RV(FV_INSELR_MICBSTR_30DB, FB_INSELR_MICBSTR)
518 
519 
520 /***************************
521  *      R_AIC1 (0x13)      *
522  ***************************/
523 
524 /* Field Offsets */
525 #define FB_AIC1_BCLKINV                      6
526 #define FB_AIC1_MS                           5
527 #define FB_AIC1_LRP                          4
528 #define FB_AIC1_WL                           2
529 #define FB_AIC1_FORMAT                       0
530 
531 /* Field Masks */
532 #define FM_AIC1_BCLKINV                      0X1
533 #define FM_AIC1_MS                           0X1
534 #define FM_AIC1_LRP                          0X1
535 #define FM_AIC1_WL                           0X3
536 #define FM_AIC1_FORMAT                       0X3
537 
538 /* Field Values */
539 #define FV_AIC1_BCLKINV_ENABLE               0x1
540 #define FV_AIC1_BCLKINV_DISABLE              0x0
541 #define FV_AIC1_MS_MASTER                    0x1
542 #define FV_AIC1_MS_SLAVE                     0x0
543 #define FV_AIC1_LRP_INVERT                   0x1
544 #define FV_AIC1_LRP_NORMAL                   0x0
545 #define FV_AIC1_WL_16                        0x0
546 #define FV_AIC1_WL_20                        0x1
547 #define FV_AIC1_WL_24                        0x2
548 #define FV_AIC1_WL_32                        0x3
549 #define FV_AIC1_FORMAT_RIGHT                 0x0
550 #define FV_AIC1_FORMAT_LEFT                  0x1
551 #define FV_AIC1_FORMAT_I2S                   0x2
552 
553 /* Register Masks */
554 #define RM_AIC1_BCLKINV \
555 	 RM(FM_AIC1_BCLKINV, FB_AIC1_BCLKINV)
556 
557 #define RM_AIC1_MS                           RM(FM_AIC1_MS, FB_AIC1_MS)
558 #define RM_AIC1_LRP                          RM(FM_AIC1_LRP, FB_AIC1_LRP)
559 #define RM_AIC1_WL                           RM(FM_AIC1_WL, FB_AIC1_WL)
560 #define RM_AIC1_FORMAT                       RM(FM_AIC1_FORMAT, FB_AIC1_FORMAT)
561 
562 /* Register Values */
563 #define RV_AIC1_BCLKINV_ENABLE \
564 	 RV(FV_AIC1_BCLKINV_ENABLE, FB_AIC1_BCLKINV)
565 
566 #define RV_AIC1_BCLKINV_DISABLE \
567 	 RV(FV_AIC1_BCLKINV_DISABLE, FB_AIC1_BCLKINV)
568 
569 #define RV_AIC1_MS_MASTER                    RV(FV_AIC1_MS_MASTER, FB_AIC1_MS)
570 #define RV_AIC1_MS_SLAVE                     RV(FV_AIC1_MS_SLAVE, FB_AIC1_MS)
571 #define RV_AIC1_LRP_INVERT \
572 	 RV(FV_AIC1_LRP_INVERT, FB_AIC1_LRP)
573 
574 #define RV_AIC1_LRP_NORMAL \
575 	 RV(FV_AIC1_LRP_NORMAL, FB_AIC1_LRP)
576 
577 #define RV_AIC1_WL_16                        RV(FV_AIC1_WL_16, FB_AIC1_WL)
578 #define RV_AIC1_WL_20                        RV(FV_AIC1_WL_20, FB_AIC1_WL)
579 #define RV_AIC1_WL_24                        RV(FV_AIC1_WL_24, FB_AIC1_WL)
580 #define RV_AIC1_WL_32                        RV(FV_AIC1_WL_32, FB_AIC1_WL)
581 #define RV_AIC1_FORMAT_RIGHT \
582 	 RV(FV_AIC1_FORMAT_RIGHT, FB_AIC1_FORMAT)
583 
584 #define RV_AIC1_FORMAT_LEFT \
585 	 RV(FV_AIC1_FORMAT_LEFT, FB_AIC1_FORMAT)
586 
587 #define RV_AIC1_FORMAT_I2S \
588 	 RV(FV_AIC1_FORMAT_I2S, FB_AIC1_FORMAT)
589 
590 
591 /***************************
592  *      R_AIC2 (0x14)      *
593  ***************************/
594 
595 /* Field Offsets */
596 #define FB_AIC2_DACDSEL                      6
597 #define FB_AIC2_ADCDSEL                      4
598 #define FB_AIC2_TRI                          3
599 #define FB_AIC2_BLRCM                        0
600 
601 /* Field Masks */
602 #define FM_AIC2_DACDSEL                      0X3
603 #define FM_AIC2_ADCDSEL                      0X3
604 #define FM_AIC2_TRI                          0X1
605 #define FM_AIC2_BLRCM                        0X7
606 
607 /* Field Values */
608 #define FV_AIC2_BLRCM_DAC_BCLK_LRCLK_SHARED  0x3
609 
610 /* Register Masks */
611 #define RM_AIC2_DACDSEL \
612 	 RM(FM_AIC2_DACDSEL, FB_AIC2_DACDSEL)
613 
614 #define RM_AIC2_ADCDSEL \
615 	 RM(FM_AIC2_ADCDSEL, FB_AIC2_ADCDSEL)
616 
617 #define RM_AIC2_TRI                          RM(FM_AIC2_TRI, FB_AIC2_TRI)
618 #define RM_AIC2_BLRCM                        RM(FM_AIC2_BLRCM, FB_AIC2_BLRCM)
619 
620 /* Register Values */
621 #define RV_AIC2_BLRCM_DAC_BCLK_LRCLK_SHARED \
622 	 RV(FV_AIC2_BLRCM_DAC_BCLK_LRCLK_SHARED, FB_AIC2_BLRCM)
623 
624 
625 /******************************
626  *      R_CNVRTR0 (0x16)      *
627  ******************************/
628 
629 /* Field Offsets */
630 #define FB_CNVRTR0_ADCPOLR                   7
631 #define FB_CNVRTR0_ADCPOLL                   6
632 #define FB_CNVRTR0_AMONOMIX                  4
633 #define FB_CNVRTR0_ADCMU                     3
634 #define FB_CNVRTR0_HPOR                      2
635 #define FB_CNVRTR0_ADCHPDR                   1
636 #define FB_CNVRTR0_ADCHPDL                   0
637 
638 /* Field Masks */
639 #define FM_CNVRTR0_ADCPOLR                   0X1
640 #define FM_CNVRTR0_ADCPOLL                   0X1
641 #define FM_CNVRTR0_AMONOMIX                  0X3
642 #define FM_CNVRTR0_ADCMU                     0X1
643 #define FM_CNVRTR0_HPOR                      0X1
644 #define FM_CNVRTR0_ADCHPDR                   0X1
645 #define FM_CNVRTR0_ADCHPDL                   0X1
646 
647 /* Field Values */
648 #define FV_CNVRTR0_ADCPOLR_INVERT            0x1
649 #define FV_CNVRTR0_ADCPOLR_NORMAL            0x0
650 #define FV_CNVRTR0_ADCPOLL_INVERT            0x1
651 #define FV_CNVRTR0_ADCPOLL_NORMAL            0x0
652 #define FV_CNVRTR0_ADCMU_ENABLE              0x1
653 #define FV_CNVRTR0_ADCMU_DISABLE             0x0
654 #define FV_CNVRTR0_ADCHPDR_ENABLE            0x1
655 #define FV_CNVRTR0_ADCHPDR_DISABLE           0x0
656 #define FV_CNVRTR0_ADCHPDL_ENABLE            0x1
657 #define FV_CNVRTR0_ADCHPDL_DISABLE           0x0
658 
659 /* Register Masks */
660 #define RM_CNVRTR0_ADCPOLR \
661 	 RM(FM_CNVRTR0_ADCPOLR, FB_CNVRTR0_ADCPOLR)
662 
663 #define RM_CNVRTR0_ADCPOLL \
664 	 RM(FM_CNVRTR0_ADCPOLL, FB_CNVRTR0_ADCPOLL)
665 
666 #define RM_CNVRTR0_AMONOMIX \
667 	 RM(FM_CNVRTR0_AMONOMIX, FB_CNVRTR0_AMONOMIX)
668 
669 #define RM_CNVRTR0_ADCMU \
670 	 RM(FM_CNVRTR0_ADCMU, FB_CNVRTR0_ADCMU)
671 
672 #define RM_CNVRTR0_HPOR \
673 	 RM(FM_CNVRTR0_HPOR, FB_CNVRTR0_HPOR)
674 
675 #define RM_CNVRTR0_ADCHPDR \
676 	 RM(FM_CNVRTR0_ADCHPDR, FB_CNVRTR0_ADCHPDR)
677 
678 #define RM_CNVRTR0_ADCHPDL \
679 	 RM(FM_CNVRTR0_ADCHPDL, FB_CNVRTR0_ADCHPDL)
680 
681 
682 /* Register Values */
683 #define RV_CNVRTR0_ADCPOLR_INVERT \
684 	 RV(FV_CNVRTR0_ADCPOLR_INVERT, FB_CNVRTR0_ADCPOLR)
685 
686 #define RV_CNVRTR0_ADCPOLR_NORMAL \
687 	 RV(FV_CNVRTR0_ADCPOLR_NORMAL, FB_CNVRTR0_ADCPOLR)
688 
689 #define RV_CNVRTR0_ADCPOLL_INVERT \
690 	 RV(FV_CNVRTR0_ADCPOLL_INVERT, FB_CNVRTR0_ADCPOLL)
691 
692 #define RV_CNVRTR0_ADCPOLL_NORMAL \
693 	 RV(FV_CNVRTR0_ADCPOLL_NORMAL, FB_CNVRTR0_ADCPOLL)
694 
695 #define RV_CNVRTR0_ADCMU_ENABLE \
696 	 RV(FV_CNVRTR0_ADCMU_ENABLE, FB_CNVRTR0_ADCMU)
697 
698 #define RV_CNVRTR0_ADCMU_DISABLE \
699 	 RV(FV_CNVRTR0_ADCMU_DISABLE, FB_CNVRTR0_ADCMU)
700 
701 #define RV_CNVRTR0_ADCHPDR_ENABLE \
702 	 RV(FV_CNVRTR0_ADCHPDR_ENABLE, FB_CNVRTR0_ADCHPDR)
703 
704 #define RV_CNVRTR0_ADCHPDR_DISABLE \
705 	 RV(FV_CNVRTR0_ADCHPDR_DISABLE, FB_CNVRTR0_ADCHPDR)
706 
707 #define RV_CNVRTR0_ADCHPDL_ENABLE \
708 	 RV(FV_CNVRTR0_ADCHPDL_ENABLE, FB_CNVRTR0_ADCHPDL)
709 
710 #define RV_CNVRTR0_ADCHPDL_DISABLE \
711 	 RV(FV_CNVRTR0_ADCHPDL_DISABLE, FB_CNVRTR0_ADCHPDL)
712 
713 
714 /****************************
715  *      R_ADCSR (0x17)      *
716  ****************************/
717 
718 /* Field Offsets */
719 #define FB_ADCSR_ABCM                        6
720 #define FB_ADCSR_ABR                         3
721 #define FB_ADCSR_ABM                         0
722 
723 /* Field Masks */
724 #define FM_ADCSR_ABCM                        0X3
725 #define FM_ADCSR_ABR                         0X3
726 #define FM_ADCSR_ABM                         0X7
727 
728 /* Field Values */
729 #define FV_ADCSR_ABCM_AUTO                   0x0
730 #define FV_ADCSR_ABCM_32                     0x1
731 #define FV_ADCSR_ABCM_40                     0x2
732 #define FV_ADCSR_ABCM_64                     0x3
733 #define FV_ADCSR_ABR_32                      0x0
734 #define FV_ADCSR_ABR_44_1                    0x1
735 #define FV_ADCSR_ABR_48                      0x2
736 #define FV_ADCSR_ABM_PT25                    0x0
737 #define FV_ADCSR_ABM_PT5                     0x1
738 #define FV_ADCSR_ABM_1                       0x2
739 #define FV_ADCSR_ABM_2                       0x3
740 
741 /* Register Masks */
742 #define RM_ADCSR_ABCM                        RM(FM_ADCSR_ABCM, FB_ADCSR_ABCM)
743 #define RM_ADCSR_ABR                         RM(FM_ADCSR_ABR, FB_ADCSR_ABR)
744 #define RM_ADCSR_ABM                         RM(FM_ADCSR_ABM, FB_ADCSR_ABM)
745 
746 /* Register Values */
747 #define RV_ADCSR_ABCM_AUTO \
748 	 RV(FV_ADCSR_ABCM_AUTO, FB_ADCSR_ABCM)
749 
750 #define RV_ADCSR_ABCM_32 \
751 	 RV(FV_ADCSR_ABCM_32, FB_ADCSR_ABCM)
752 
753 #define RV_ADCSR_ABCM_40 \
754 	 RV(FV_ADCSR_ABCM_40, FB_ADCSR_ABCM)
755 
756 #define RV_ADCSR_ABCM_64 \
757 	 RV(FV_ADCSR_ABCM_64, FB_ADCSR_ABCM)
758 
759 #define RV_ADCSR_ABR_32                      RV(FV_ADCSR_ABR_32, FB_ADCSR_ABR)
760 #define RV_ADCSR_ABR_44_1 \
761 	 RV(FV_ADCSR_ABR_44_1, FB_ADCSR_ABR)
762 
763 #define RV_ADCSR_ABR_48                      RV(FV_ADCSR_ABR_48, FB_ADCSR_ABR)
764 #define RV_ADCSR_ABR_                        RV(FV_ADCSR_ABR_, FB_ADCSR_ABR)
765 #define RV_ADCSR_ABM_PT25 \
766 	 RV(FV_ADCSR_ABM_PT25, FB_ADCSR_ABM)
767 
768 #define RV_ADCSR_ABM_PT5                     RV(FV_ADCSR_ABM_PT5, FB_ADCSR_ABM)
769 #define RV_ADCSR_ABM_1                       RV(FV_ADCSR_ABM_1, FB_ADCSR_ABM)
770 #define RV_ADCSR_ABM_2                       RV(FV_ADCSR_ABM_2, FB_ADCSR_ABM)
771 
772 /******************************
773  *      R_CNVRTR1 (0x18)      *
774  ******************************/
775 
776 /* Field Offsets */
777 #define FB_CNVRTR1_DACPOLR                   7
778 #define FB_CNVRTR1_DACPOLL                   6
779 #define FB_CNVRTR1_DMONOMIX                  4
780 #define FB_CNVRTR1_DACMU                     3
781 #define FB_CNVRTR1_DEEMPH                    2
782 #define FB_CNVRTR1_DACDITH                   0
783 
784 /* Field Masks */
785 #define FM_CNVRTR1_DACPOLR                   0X1
786 #define FM_CNVRTR1_DACPOLL                   0X1
787 #define FM_CNVRTR1_DMONOMIX                  0X3
788 #define FM_CNVRTR1_DACMU                     0X1
789 #define FM_CNVRTR1_DEEMPH                    0X1
790 #define FM_CNVRTR1_DACDITH                   0X3
791 
792 /* Field Values */
793 #define FV_CNVRTR1_DACPOLR_INVERT            0x1
794 #define FV_CNVRTR1_DACPOLR_NORMAL            0x0
795 #define FV_CNVRTR1_DACPOLL_INVERT            0x1
796 #define FV_CNVRTR1_DACPOLL_NORMAL            0x0
797 #define FV_CNVRTR1_DMONOMIX_ENABLE           0x1
798 #define FV_CNVRTR1_DMONOMIX_DISABLE          0x0
799 #define FV_CNVRTR1_DACMU_ENABLE              0x1
800 #define FV_CNVRTR1_DACMU_DISABLE             0x0
801 
802 /* Register Masks */
803 #define RM_CNVRTR1_DACPOLR \
804 	 RM(FM_CNVRTR1_DACPOLR, FB_CNVRTR1_DACPOLR)
805 
806 #define RM_CNVRTR1_DACPOLL \
807 	 RM(FM_CNVRTR1_DACPOLL, FB_CNVRTR1_DACPOLL)
808 
809 #define RM_CNVRTR1_DMONOMIX \
810 	 RM(FM_CNVRTR1_DMONOMIX, FB_CNVRTR1_DMONOMIX)
811 
812 #define RM_CNVRTR1_DACMU \
813 	 RM(FM_CNVRTR1_DACMU, FB_CNVRTR1_DACMU)
814 
815 #define RM_CNVRTR1_DEEMPH \
816 	 RM(FM_CNVRTR1_DEEMPH, FB_CNVRTR1_DEEMPH)
817 
818 #define RM_CNVRTR1_DACDITH \
819 	 RM(FM_CNVRTR1_DACDITH, FB_CNVRTR1_DACDITH)
820 
821 
822 /* Register Values */
823 #define RV_CNVRTR1_DACPOLR_INVERT \
824 	 RV(FV_CNVRTR1_DACPOLR_INVERT, FB_CNVRTR1_DACPOLR)
825 
826 #define RV_CNVRTR1_DACPOLR_NORMAL \
827 	 RV(FV_CNVRTR1_DACPOLR_NORMAL, FB_CNVRTR1_DACPOLR)
828 
829 #define RV_CNVRTR1_DACPOLL_INVERT \
830 	 RV(FV_CNVRTR1_DACPOLL_INVERT, FB_CNVRTR1_DACPOLL)
831 
832 #define RV_CNVRTR1_DACPOLL_NORMAL \
833 	 RV(FV_CNVRTR1_DACPOLL_NORMAL, FB_CNVRTR1_DACPOLL)
834 
835 #define RV_CNVRTR1_DMONOMIX_ENABLE \
836 	 RV(FV_CNVRTR1_DMONOMIX_ENABLE, FB_CNVRTR1_DMONOMIX)
837 
838 #define RV_CNVRTR1_DMONOMIX_DISABLE \
839 	 RV(FV_CNVRTR1_DMONOMIX_DISABLE, FB_CNVRTR1_DMONOMIX)
840 
841 #define RV_CNVRTR1_DACMU_ENABLE \
842 	 RV(FV_CNVRTR1_DACMU_ENABLE, FB_CNVRTR1_DACMU)
843 
844 #define RV_CNVRTR1_DACMU_DISABLE \
845 	 RV(FV_CNVRTR1_DACMU_DISABLE, FB_CNVRTR1_DACMU)
846 
847 
848 /****************************
849  *      R_DACSR (0x19)      *
850  ****************************/
851 
852 /* Field Offsets */
853 #define FB_DACSR_DBCM                        6
854 #define FB_DACSR_DBR                         3
855 #define FB_DACSR_DBM                         0
856 
857 /* Field Masks */
858 #define FM_DACSR_DBCM                        0X3
859 #define FM_DACSR_DBR                         0X3
860 #define FM_DACSR_DBM                         0X7
861 
862 /* Field Values */
863 #define FV_DACSR_DBCM_AUTO                   0x0
864 #define FV_DACSR_DBCM_32                     0x1
865 #define FV_DACSR_DBCM_40                     0x2
866 #define FV_DACSR_DBCM_64                     0x3
867 #define FV_DACSR_DBR_32                      0x0
868 #define FV_DACSR_DBR_44_1                    0x1
869 #define FV_DACSR_DBR_48                      0x2
870 #define FV_DACSR_DBM_PT25                    0x0
871 #define FV_DACSR_DBM_PT5                     0x1
872 #define FV_DACSR_DBM_1                       0x2
873 #define FV_DACSR_DBM_2                       0x3
874 
875 /* Register Masks */
876 #define RM_DACSR_DBCM                        RM(FM_DACSR_DBCM, FB_DACSR_DBCM)
877 #define RM_DACSR_DBR                         RM(FM_DACSR_DBR, FB_DACSR_DBR)
878 #define RM_DACSR_DBM                         RM(FM_DACSR_DBM, FB_DACSR_DBM)
879 
880 /* Register Values */
881 #define RV_DACSR_DBCM_AUTO \
882 	 RV(FV_DACSR_DBCM_AUTO, FB_DACSR_DBCM)
883 
884 #define RV_DACSR_DBCM_32 \
885 	 RV(FV_DACSR_DBCM_32, FB_DACSR_DBCM)
886 
887 #define RV_DACSR_DBCM_40 \
888 	 RV(FV_DACSR_DBCM_40, FB_DACSR_DBCM)
889 
890 #define RV_DACSR_DBCM_64 \
891 	 RV(FV_DACSR_DBCM_64, FB_DACSR_DBCM)
892 
893 #define RV_DACSR_DBR_32                      RV(FV_DACSR_DBR_32, FB_DACSR_DBR)
894 #define RV_DACSR_DBR_44_1 \
895 	 RV(FV_DACSR_DBR_44_1, FB_DACSR_DBR)
896 
897 #define RV_DACSR_DBR_48                      RV(FV_DACSR_DBR_48, FB_DACSR_DBR)
898 #define RV_DACSR_DBM_PT25 \
899 	 RV(FV_DACSR_DBM_PT25, FB_DACSR_DBM)
900 
901 #define RV_DACSR_DBM_PT5                     RV(FV_DACSR_DBM_PT5, FB_DACSR_DBM)
902 #define RV_DACSR_DBM_1                       RV(FV_DACSR_DBM_1, FB_DACSR_DBM)
903 #define RV_DACSR_DBM_2                       RV(FV_DACSR_DBM_2, FB_DACSR_DBM)
904 
905 /****************************
906  *      R_PWRM1 (0x1A)      *
907  ****************************/
908 
909 /* Field Offsets */
910 #define FB_PWRM1_BSTL                        7
911 #define FB_PWRM1_BSTR                        6
912 #define FB_PWRM1_PGAL                        5
913 #define FB_PWRM1_PGAR                        4
914 #define FB_PWRM1_ADCL                        3
915 #define FB_PWRM1_ADCR                        2
916 #define FB_PWRM1_MICB                        1
917 #define FB_PWRM1_DIGENB                      0
918 
919 /* Field Masks */
920 #define FM_PWRM1_BSTL                        0X1
921 #define FM_PWRM1_BSTR                        0X1
922 #define FM_PWRM1_PGAL                        0X1
923 #define FM_PWRM1_PGAR                        0X1
924 #define FM_PWRM1_ADCL                        0X1
925 #define FM_PWRM1_ADCR                        0X1
926 #define FM_PWRM1_MICB                        0X1
927 #define FM_PWRM1_DIGENB                      0X1
928 
929 /* Field Values */
930 #define FV_PWRM1_BSTL_ENABLE                 0x1
931 #define FV_PWRM1_BSTL_DISABLE                0x0
932 #define FV_PWRM1_BSTR_ENABLE                 0x1
933 #define FV_PWRM1_BSTR_DISABLE                0x0
934 #define FV_PWRM1_PGAL_ENABLE                 0x1
935 #define FV_PWRM1_PGAL_DISABLE                0x0
936 #define FV_PWRM1_PGAR_ENABLE                 0x1
937 #define FV_PWRM1_PGAR_DISABLE                0x0
938 #define FV_PWRM1_ADCL_ENABLE                 0x1
939 #define FV_PWRM1_ADCL_DISABLE                0x0
940 #define FV_PWRM1_ADCR_ENABLE                 0x1
941 #define FV_PWRM1_ADCR_DISABLE                0x0
942 #define FV_PWRM1_MICB_ENABLE                 0x1
943 #define FV_PWRM1_MICB_DISABLE                0x0
944 #define FV_PWRM1_DIGENB_DISABLE              0x1
945 #define FV_PWRM1_DIGENB_ENABLE               0x0
946 
947 /* Register Masks */
948 #define RM_PWRM1_BSTL                        RM(FM_PWRM1_BSTL, FB_PWRM1_BSTL)
949 #define RM_PWRM1_BSTR                        RM(FM_PWRM1_BSTR, FB_PWRM1_BSTR)
950 #define RM_PWRM1_PGAL                        RM(FM_PWRM1_PGAL, FB_PWRM1_PGAL)
951 #define RM_PWRM1_PGAR                        RM(FM_PWRM1_PGAR, FB_PWRM1_PGAR)
952 #define RM_PWRM1_ADCL                        RM(FM_PWRM1_ADCL, FB_PWRM1_ADCL)
953 #define RM_PWRM1_ADCR                        RM(FM_PWRM1_ADCR, FB_PWRM1_ADCR)
954 #define RM_PWRM1_MICB                        RM(FM_PWRM1_MICB, FB_PWRM1_MICB)
955 #define RM_PWRM1_DIGENB \
956 	 RM(FM_PWRM1_DIGENB, FB_PWRM1_DIGENB)
957 
958 
959 /* Register Values */
960 #define RV_PWRM1_BSTL_ENABLE \
961 	 RV(FV_PWRM1_BSTL_ENABLE, FB_PWRM1_BSTL)
962 
963 #define RV_PWRM1_BSTL_DISABLE \
964 	 RV(FV_PWRM1_BSTL_DISABLE, FB_PWRM1_BSTL)
965 
966 #define RV_PWRM1_BSTR_ENABLE \
967 	 RV(FV_PWRM1_BSTR_ENABLE, FB_PWRM1_BSTR)
968 
969 #define RV_PWRM1_BSTR_DISABLE \
970 	 RV(FV_PWRM1_BSTR_DISABLE, FB_PWRM1_BSTR)
971 
972 #define RV_PWRM1_PGAL_ENABLE \
973 	 RV(FV_PWRM1_PGAL_ENABLE, FB_PWRM1_PGAL)
974 
975 #define RV_PWRM1_PGAL_DISABLE \
976 	 RV(FV_PWRM1_PGAL_DISABLE, FB_PWRM1_PGAL)
977 
978 #define RV_PWRM1_PGAR_ENABLE \
979 	 RV(FV_PWRM1_PGAR_ENABLE, FB_PWRM1_PGAR)
980 
981 #define RV_PWRM1_PGAR_DISABLE \
982 	 RV(FV_PWRM1_PGAR_DISABLE, FB_PWRM1_PGAR)
983 
984 #define RV_PWRM1_ADCL_ENABLE \
985 	 RV(FV_PWRM1_ADCL_ENABLE, FB_PWRM1_ADCL)
986 
987 #define RV_PWRM1_ADCL_DISABLE \
988 	 RV(FV_PWRM1_ADCL_DISABLE, FB_PWRM1_ADCL)
989 
990 #define RV_PWRM1_ADCR_ENABLE \
991 	 RV(FV_PWRM1_ADCR_ENABLE, FB_PWRM1_ADCR)
992 
993 #define RV_PWRM1_ADCR_DISABLE \
994 	 RV(FV_PWRM1_ADCR_DISABLE, FB_PWRM1_ADCR)
995 
996 #define RV_PWRM1_MICB_ENABLE \
997 	 RV(FV_PWRM1_MICB_ENABLE, FB_PWRM1_MICB)
998 
999 #define RV_PWRM1_MICB_DISABLE \
1000 	 RV(FV_PWRM1_MICB_DISABLE, FB_PWRM1_MICB)
1001 
1002 #define RV_PWRM1_DIGENB_DISABLE \
1003 	 RV(FV_PWRM1_DIGENB_DISABLE, FB_PWRM1_DIGENB)
1004 
1005 #define RV_PWRM1_DIGENB_ENABLE \
1006 	 RV(FV_PWRM1_DIGENB_ENABLE, FB_PWRM1_DIGENB)
1007 
1008 
1009 /****************************
1010  *      R_PWRM2 (0x1B)      *
1011  ****************************/
1012 
1013 /* Field Offsets */
1014 #define FB_PWRM2_D2S                         7
1015 #define FB_PWRM2_HPL                         6
1016 #define FB_PWRM2_HPR                         5
1017 #define FB_PWRM2_SPKL                        4
1018 #define FB_PWRM2_SPKR                        3
1019 #define FB_PWRM2_INSELL                      2
1020 #define FB_PWRM2_INSELR                      1
1021 #define FB_PWRM2_VREF                        0
1022 
1023 /* Field Masks */
1024 #define FM_PWRM2_D2S                         0X1
1025 #define FM_PWRM2_HPL                         0X1
1026 #define FM_PWRM2_HPR                         0X1
1027 #define FM_PWRM2_SPKL                        0X1
1028 #define FM_PWRM2_SPKR                        0X1
1029 #define FM_PWRM2_INSELL                      0X1
1030 #define FM_PWRM2_INSELR                      0X1
1031 #define FM_PWRM2_VREF                        0X1
1032 
1033 /* Field Values */
1034 #define FV_PWRM2_D2S_ENABLE                  0x1
1035 #define FV_PWRM2_D2S_DISABLE                 0x0
1036 #define FV_PWRM2_HPL_ENABLE                  0x1
1037 #define FV_PWRM2_HPL_DISABLE                 0x0
1038 #define FV_PWRM2_HPR_ENABLE                  0x1
1039 #define FV_PWRM2_HPR_DISABLE                 0x0
1040 #define FV_PWRM2_SPKL_ENABLE                 0x1
1041 #define FV_PWRM2_SPKL_DISABLE                0x0
1042 #define FV_PWRM2_SPKR_ENABLE                 0x1
1043 #define FV_PWRM2_SPKR_DISABLE                0x0
1044 #define FV_PWRM2_INSELL_ENABLE               0x1
1045 #define FV_PWRM2_INSELL_DISABLE              0x0
1046 #define FV_PWRM2_INSELR_ENABLE               0x1
1047 #define FV_PWRM2_INSELR_DISABLE              0x0
1048 #define FV_PWRM2_VREF_ENABLE                 0x1
1049 #define FV_PWRM2_VREF_DISABLE                0x0
1050 
1051 /* Register Masks */
1052 #define RM_PWRM2_D2S                         RM(FM_PWRM2_D2S, FB_PWRM2_D2S)
1053 #define RM_PWRM2_HPL                         RM(FM_PWRM2_HPL, FB_PWRM2_HPL)
1054 #define RM_PWRM2_HPR                         RM(FM_PWRM2_HPR, FB_PWRM2_HPR)
1055 #define RM_PWRM2_SPKL                        RM(FM_PWRM2_SPKL, FB_PWRM2_SPKL)
1056 #define RM_PWRM2_SPKR                        RM(FM_PWRM2_SPKR, FB_PWRM2_SPKR)
1057 #define RM_PWRM2_INSELL \
1058 	 RM(FM_PWRM2_INSELL, FB_PWRM2_INSELL)
1059 
1060 #define RM_PWRM2_INSELR \
1061 	 RM(FM_PWRM2_INSELR, FB_PWRM2_INSELR)
1062 
1063 #define RM_PWRM2_VREF                        RM(FM_PWRM2_VREF, FB_PWRM2_VREF)
1064 
1065 /* Register Values */
1066 #define RV_PWRM2_D2S_ENABLE \
1067 	 RV(FV_PWRM2_D2S_ENABLE, FB_PWRM2_D2S)
1068 
1069 #define RV_PWRM2_D2S_DISABLE \
1070 	 RV(FV_PWRM2_D2S_DISABLE, FB_PWRM2_D2S)
1071 
1072 #define RV_PWRM2_HPL_ENABLE \
1073 	 RV(FV_PWRM2_HPL_ENABLE, FB_PWRM2_HPL)
1074 
1075 #define RV_PWRM2_HPL_DISABLE \
1076 	 RV(FV_PWRM2_HPL_DISABLE, FB_PWRM2_HPL)
1077 
1078 #define RV_PWRM2_HPR_ENABLE \
1079 	 RV(FV_PWRM2_HPR_ENABLE, FB_PWRM2_HPR)
1080 
1081 #define RV_PWRM2_HPR_DISABLE \
1082 	 RV(FV_PWRM2_HPR_DISABLE, FB_PWRM2_HPR)
1083 
1084 #define RV_PWRM2_SPKL_ENABLE \
1085 	 RV(FV_PWRM2_SPKL_ENABLE, FB_PWRM2_SPKL)
1086 
1087 #define RV_PWRM2_SPKL_DISABLE \
1088 	 RV(FV_PWRM2_SPKL_DISABLE, FB_PWRM2_SPKL)
1089 
1090 #define RV_PWRM2_SPKR_ENABLE \
1091 	 RV(FV_PWRM2_SPKR_ENABLE, FB_PWRM2_SPKR)
1092 
1093 #define RV_PWRM2_SPKR_DISABLE \
1094 	 RV(FV_PWRM2_SPKR_DISABLE, FB_PWRM2_SPKR)
1095 
1096 #define RV_PWRM2_INSELL_ENABLE \
1097 	 RV(FV_PWRM2_INSELL_ENABLE, FB_PWRM2_INSELL)
1098 
1099 #define RV_PWRM2_INSELL_DISABLE \
1100 	 RV(FV_PWRM2_INSELL_DISABLE, FB_PWRM2_INSELL)
1101 
1102 #define RV_PWRM2_INSELR_ENABLE \
1103 	 RV(FV_PWRM2_INSELR_ENABLE, FB_PWRM2_INSELR)
1104 
1105 #define RV_PWRM2_INSELR_DISABLE \
1106 	 RV(FV_PWRM2_INSELR_DISABLE, FB_PWRM2_INSELR)
1107 
1108 #define RV_PWRM2_VREF_ENABLE \
1109 	 RV(FV_PWRM2_VREF_ENABLE, FB_PWRM2_VREF)
1110 
1111 #define RV_PWRM2_VREF_DISABLE \
1112 	 RV(FV_PWRM2_VREF_DISABLE, FB_PWRM2_VREF)
1113 
1114 /******************************
1115  *      R_CTL (0x1C)          *
1116  ******************************/
1117 
1118 /* Fiel Offsets */
1119 #define FB_CTL_HPSWEN                        7
1120 #define FB_CTL_HPSWPOL                       6
1121 
1122 /******************************
1123  *      R_CONFIG0 (0x1F)      *
1124  ******************************/
1125 
1126 /* Field Offsets */
1127 #define FB_CONFIG0_ASDM                      6
1128 #define FB_CONFIG0_DSDM                      4
1129 #define FB_CONFIG0_DC_BYPASS                 1
1130 #define FB_CONFIG0_SD_FORCE_ON               0
1131 
1132 /* Field Masks */
1133 #define FM_CONFIG0_ASDM                      0X3
1134 #define FM_CONFIG0_DSDM                      0X3
1135 #define FM_CONFIG0_DC_BYPASS                 0X1
1136 #define FM_CONFIG0_SD_FORCE_ON               0X1
1137 
1138 /* Field Values */
1139 #define FV_CONFIG0_ASDM_HALF                 0x1
1140 #define FV_CONFIG0_ASDM_FULL                 0x2
1141 #define FV_CONFIG0_ASDM_AUTO                 0x3
1142 #define FV_CONFIG0_DSDM_HALF                 0x1
1143 #define FV_CONFIG0_DSDM_FULL                 0x2
1144 #define FV_CONFIG0_DSDM_AUTO                 0x3
1145 #define FV_CONFIG0_DC_BYPASS_ENABLE          0x1
1146 #define FV_CONFIG0_DC_BYPASS_DISABLE         0x0
1147 #define FV_CONFIG0_SD_FORCE_ON_ENABLE        0x1
1148 #define FV_CONFIG0_SD_FORCE_ON_DISABLE       0x0
1149 
1150 /* Register Masks */
1151 #define RM_CONFIG0_ASDM \
1152 	 RM(FM_CONFIG0_ASDM, FB_CONFIG0_ASDM)
1153 
1154 #define RM_CONFIG0_DSDM \
1155 	 RM(FM_CONFIG0_DSDM, FB_CONFIG0_DSDM)
1156 
1157 #define RM_CONFIG0_DC_BYPASS \
1158 	 RM(FM_CONFIG0_DC_BYPASS, FB_CONFIG0_DC_BYPASS)
1159 
1160 #define RM_CONFIG0_SD_FORCE_ON \
1161 	 RM(FM_CONFIG0_SD_FORCE_ON, FB_CONFIG0_SD_FORCE_ON)
1162 
1163 
1164 /* Register Values */
1165 #define RV_CONFIG0_ASDM_HALF \
1166 	 RV(FV_CONFIG0_ASDM_HALF, FB_CONFIG0_ASDM)
1167 
1168 #define RV_CONFIG0_ASDM_FULL \
1169 	 RV(FV_CONFIG0_ASDM_FULL, FB_CONFIG0_ASDM)
1170 
1171 #define RV_CONFIG0_ASDM_AUTO \
1172 	 RV(FV_CONFIG0_ASDM_AUTO, FB_CONFIG0_ASDM)
1173 
1174 #define RV_CONFIG0_DSDM_HALF \
1175 	 RV(FV_CONFIG0_DSDM_HALF, FB_CONFIG0_DSDM)
1176 
1177 #define RV_CONFIG0_DSDM_FULL \
1178 	 RV(FV_CONFIG0_DSDM_FULL, FB_CONFIG0_DSDM)
1179 
1180 #define RV_CONFIG0_DSDM_AUTO \
1181 	 RV(FV_CONFIG0_DSDM_AUTO, FB_CONFIG0_DSDM)
1182 
1183 #define RV_CONFIG0_DC_BYPASS_ENABLE \
1184 	 RV(FV_CONFIG0_DC_BYPASS_ENABLE, FB_CONFIG0_DC_BYPASS)
1185 
1186 #define RV_CONFIG0_DC_BYPASS_DISABLE \
1187 	 RV(FV_CONFIG0_DC_BYPASS_DISABLE, FB_CONFIG0_DC_BYPASS)
1188 
1189 #define RV_CONFIG0_SD_FORCE_ON_ENABLE \
1190 	 RV(FV_CONFIG0_SD_FORCE_ON_ENABLE, FB_CONFIG0_SD_FORCE_ON)
1191 
1192 #define RV_CONFIG0_SD_FORCE_ON_DISABLE \
1193 	 RV(FV_CONFIG0_SD_FORCE_ON_DISABLE, FB_CONFIG0_SD_FORCE_ON)
1194 
1195 
1196 /******************************
1197  *      R_CONFIG1 (0x20)      *
1198  ******************************/
1199 
1200 /* Field Offsets */
1201 #define FB_CONFIG1_EQ2_EN                    7
1202 #define FB_CONFIG1_EQ2_BE                    4
1203 #define FB_CONFIG1_EQ1_EN                    3
1204 #define FB_CONFIG1_EQ1_BE                    0
1205 
1206 /* Field Masks */
1207 #define FM_CONFIG1_EQ2_EN                    0X1
1208 #define FM_CONFIG1_EQ2_BE                    0X7
1209 #define FM_CONFIG1_EQ1_EN                    0X1
1210 #define FM_CONFIG1_EQ1_BE                    0X7
1211 
1212 /* Field Values */
1213 #define FV_CONFIG1_EQ2_EN_ENABLE             0x1
1214 #define FV_CONFIG1_EQ2_EN_DISABLE            0x0
1215 #define FV_CONFIG1_EQ2_BE_PRE                0x0
1216 #define FV_CONFIG1_EQ2_BE_PRE_EQ_0           0x1
1217 #define FV_CONFIG1_EQ2_BE_PRE_EQ0_1          0x2
1218 #define FV_CONFIG1_EQ2_BE_PRE_EQ0_2          0x3
1219 #define FV_CONFIG1_EQ2_BE_PRE_EQ0_3          0x4
1220 #define FV_CONFIG1_EQ2_BE_PRE_EQ0_4          0x5
1221 #define FV_CONFIG1_EQ2_BE_PRE_EQ0_5          0x6
1222 #define FV_CONFIG1_EQ1_EN_ENABLE             0x1
1223 #define FV_CONFIG1_EQ1_EN_DISABLE            0x0
1224 #define FV_CONFIG1_EQ1_BE_PRE                0x0
1225 #define FV_CONFIG1_EQ1_BE_PRE_EQ_0           0x1
1226 #define FV_CONFIG1_EQ1_BE_PRE_EQ0_1          0x2
1227 #define FV_CONFIG1_EQ1_BE_PRE_EQ0_2          0x3
1228 #define FV_CONFIG1_EQ1_BE_PRE_EQ0_3          0x4
1229 #define FV_CONFIG1_EQ1_BE_PRE_EQ0_4          0x5
1230 #define FV_CONFIG1_EQ1_BE_PRE_EQ0_5          0x6
1231 
1232 /* Register Masks */
1233 #define RM_CONFIG1_EQ2_EN \
1234 	 RM(FM_CONFIG1_EQ2_EN, FB_CONFIG1_EQ2_EN)
1235 
1236 #define RM_CONFIG1_EQ2_BE \
1237 	 RM(FM_CONFIG1_EQ2_BE, FB_CONFIG1_EQ2_BE)
1238 
1239 #define RM_CONFIG1_EQ1_EN \
1240 	 RM(FM_CONFIG1_EQ1_EN, FB_CONFIG1_EQ1_EN)
1241 
1242 #define RM_CONFIG1_EQ1_BE \
1243 	 RM(FM_CONFIG1_EQ1_BE, FB_CONFIG1_EQ1_BE)
1244 
1245 
1246 /* Register Values */
1247 #define RV_CONFIG1_EQ2_EN_ENABLE \
1248 	 RV(FV_CONFIG1_EQ2_EN_ENABLE, FB_CONFIG1_EQ2_EN)
1249 
1250 #define RV_CONFIG1_EQ2_EN_DISABLE \
1251 	 RV(FV_CONFIG1_EQ2_EN_DISABLE, FB_CONFIG1_EQ2_EN)
1252 
1253 #define RV_CONFIG1_EQ2_BE_PRE \
1254 	 RV(FV_CONFIG1_EQ2_BE_PRE, FB_CONFIG1_EQ2_BE)
1255 
1256 #define RV_CONFIG1_EQ2_BE_PRE_EQ_0 \
1257 	 RV(FV_CONFIG1_EQ2_BE_PRE_EQ_0, FB_CONFIG1_EQ2_BE)
1258 
1259 #define RV_CONFIG1_EQ2_BE_PRE_EQ0_1 \
1260 	 RV(FV_CONFIG1_EQ2_BE_PRE_EQ0_1, FB_CONFIG1_EQ2_BE)
1261 
1262 #define RV_CONFIG1_EQ2_BE_PRE_EQ0_2 \
1263 	 RV(FV_CONFIG1_EQ2_BE_PRE_EQ0_2, FB_CONFIG1_EQ2_BE)
1264 
1265 #define RV_CONFIG1_EQ2_BE_PRE_EQ0_3 \
1266 	 RV(FV_CONFIG1_EQ2_BE_PRE_EQ0_3, FB_CONFIG1_EQ2_BE)
1267 
1268 #define RV_CONFIG1_EQ2_BE_PRE_EQ0_4 \
1269 	 RV(FV_CONFIG1_EQ2_BE_PRE_EQ0_4, FB_CONFIG1_EQ2_BE)
1270 
1271 #define RV_CONFIG1_EQ2_BE_PRE_EQ0_5 \
1272 	 RV(FV_CONFIG1_EQ2_BE_PRE_EQ0_5, FB_CONFIG1_EQ2_BE)
1273 
1274 #define RV_CONFIG1_EQ1_EN_ENABLE \
1275 	 RV(FV_CONFIG1_EQ1_EN_ENABLE, FB_CONFIG1_EQ1_EN)
1276 
1277 #define RV_CONFIG1_EQ1_EN_DISABLE \
1278 	 RV(FV_CONFIG1_EQ1_EN_DISABLE, FB_CONFIG1_EQ1_EN)
1279 
1280 #define RV_CONFIG1_EQ1_BE_PRE \
1281 	 RV(FV_CONFIG1_EQ1_BE_PRE, FB_CONFIG1_EQ1_BE)
1282 
1283 #define RV_CONFIG1_EQ1_BE_PRE_EQ_0 \
1284 	 RV(FV_CONFIG1_EQ1_BE_PRE_EQ_0, FB_CONFIG1_EQ1_BE)
1285 
1286 #define RV_CONFIG1_EQ1_BE_PRE_EQ0_1 \
1287 	 RV(FV_CONFIG1_EQ1_BE_PRE_EQ0_1, FB_CONFIG1_EQ1_BE)
1288 
1289 #define RV_CONFIG1_EQ1_BE_PRE_EQ0_2 \
1290 	 RV(FV_CONFIG1_EQ1_BE_PRE_EQ0_2, FB_CONFIG1_EQ1_BE)
1291 
1292 #define RV_CONFIG1_EQ1_BE_PRE_EQ0_3 \
1293 	 RV(FV_CONFIG1_EQ1_BE_PRE_EQ0_3, FB_CONFIG1_EQ1_BE)
1294 
1295 #define RV_CONFIG1_EQ1_BE_PRE_EQ0_4 \
1296 	 RV(FV_CONFIG1_EQ1_BE_PRE_EQ0_4, FB_CONFIG1_EQ1_BE)
1297 
1298 #define RV_CONFIG1_EQ1_BE_PRE_EQ0_5 \
1299 	 RV(FV_CONFIG1_EQ1_BE_PRE_EQ0_5, FB_CONFIG1_EQ1_BE)
1300 
1301 
1302 /******************************
1303  *      R_DMICCTL (0x24)      *
1304  ******************************/
1305 
1306 /* Field Offsets */
1307 #define FB_DMICCTL_DMICEN                    7
1308 #define FB_DMICCTL_DMONO                     4
1309 #define FB_DMICCTL_DMPHADJ                   2
1310 #define FB_DMICCTL_DMRATE                    0
1311 
1312 /* Field Masks */
1313 #define FM_DMICCTL_DMICEN                    0X1
1314 #define FM_DMICCTL_DMONO                     0X1
1315 #define FM_DMICCTL_DMPHADJ                   0X3
1316 #define FM_DMICCTL_DMRATE                    0X3
1317 
1318 /* Field Values */
1319 #define FV_DMICCTL_DMICEN_ENABLE             0x1
1320 #define FV_DMICCTL_DMICEN_DISABLE            0x0
1321 #define FV_DMICCTL_DMONO_STEREO              0x0
1322 #define FV_DMICCTL_DMONO_MONO                0x1
1323 
1324 /* Register Masks */
1325 #define RM_DMICCTL_DMICEN \
1326 	 RM(FM_DMICCTL_DMICEN, FB_DMICCTL_DMICEN)
1327 
1328 #define RM_DMICCTL_DMONO \
1329 	 RM(FM_DMICCTL_DMONO, FB_DMICCTL_DMONO)
1330 
1331 #define RM_DMICCTL_DMPHADJ \
1332 	 RM(FM_DMICCTL_DMPHADJ, FB_DMICCTL_DMPHADJ)
1333 
1334 #define RM_DMICCTL_DMRATE \
1335 	 RM(FM_DMICCTL_DMRATE, FB_DMICCTL_DMRATE)
1336 
1337 
1338 /* Register Values */
1339 #define RV_DMICCTL_DMICEN_ENABLE \
1340 	 RV(FV_DMICCTL_DMICEN_ENABLE, FB_DMICCTL_DMICEN)
1341 
1342 #define RV_DMICCTL_DMICEN_DISABLE \
1343 	 RV(FV_DMICCTL_DMICEN_DISABLE, FB_DMICCTL_DMICEN)
1344 
1345 #define RV_DMICCTL_DMONO_STEREO \
1346 	 RV(FV_DMICCTL_DMONO_STEREO, FB_DMICCTL_DMONO)
1347 
1348 #define RV_DMICCTL_DMONO_MONO \
1349 	 RV(FV_DMICCTL_DMONO_MONO, FB_DMICCTL_DMONO)
1350 
1351 
1352 /*****************************
1353  *      R_CLECTL (0x25)      *
1354  *****************************/
1355 
1356 /* Field Offsets */
1357 #define FB_CLECTL_LVL_MODE                   4
1358 #define FB_CLECTL_WINDOWSEL                  3
1359 #define FB_CLECTL_EXP_EN                     2
1360 #define FB_CLECTL_LIMIT_EN                   1
1361 #define FB_CLECTL_COMP_EN                    0
1362 
1363 /* Field Masks */
1364 #define FM_CLECTL_LVL_MODE                   0X1
1365 #define FM_CLECTL_WINDOWSEL                  0X1
1366 #define FM_CLECTL_EXP_EN                     0X1
1367 #define FM_CLECTL_LIMIT_EN                   0X1
1368 #define FM_CLECTL_COMP_EN                    0X1
1369 
1370 /* Field Values */
1371 #define FV_CLECTL_LVL_MODE_AVG               0x0
1372 #define FV_CLECTL_LVL_MODE_PEAK              0x1
1373 #define FV_CLECTL_WINDOWSEL_512              0x0
1374 #define FV_CLECTL_WINDOWSEL_64               0x1
1375 #define FV_CLECTL_EXP_EN_ENABLE              0x1
1376 #define FV_CLECTL_EXP_EN_DISABLE             0x0
1377 #define FV_CLECTL_LIMIT_EN_ENABLE            0x1
1378 #define FV_CLECTL_LIMIT_EN_DISABLE           0x0
1379 #define FV_CLECTL_COMP_EN_ENABLE             0x1
1380 #define FV_CLECTL_COMP_EN_DISABLE            0x0
1381 
1382 /* Register Masks */
1383 #define RM_CLECTL_LVL_MODE \
1384 	 RM(FM_CLECTL_LVL_MODE, FB_CLECTL_LVL_MODE)
1385 
1386 #define RM_CLECTL_WINDOWSEL \
1387 	 RM(FM_CLECTL_WINDOWSEL, FB_CLECTL_WINDOWSEL)
1388 
1389 #define RM_CLECTL_EXP_EN \
1390 	 RM(FM_CLECTL_EXP_EN, FB_CLECTL_EXP_EN)
1391 
1392 #define RM_CLECTL_LIMIT_EN \
1393 	 RM(FM_CLECTL_LIMIT_EN, FB_CLECTL_LIMIT_EN)
1394 
1395 #define RM_CLECTL_COMP_EN \
1396 	 RM(FM_CLECTL_COMP_EN, FB_CLECTL_COMP_EN)
1397 
1398 
1399 /* Register Values */
1400 #define RV_CLECTL_LVL_MODE_AVG \
1401 	 RV(FV_CLECTL_LVL_MODE_AVG, FB_CLECTL_LVL_MODE)
1402 
1403 #define RV_CLECTL_LVL_MODE_PEAK \
1404 	 RV(FV_CLECTL_LVL_MODE_PEAK, FB_CLECTL_LVL_MODE)
1405 
1406 #define RV_CLECTL_WINDOWSEL_512 \
1407 	 RV(FV_CLECTL_WINDOWSEL_512, FB_CLECTL_WINDOWSEL)
1408 
1409 #define RV_CLECTL_WINDOWSEL_64 \
1410 	 RV(FV_CLECTL_WINDOWSEL_64, FB_CLECTL_WINDOWSEL)
1411 
1412 #define RV_CLECTL_EXP_EN_ENABLE \
1413 	 RV(FV_CLECTL_EXP_EN_ENABLE, FB_CLECTL_EXP_EN)
1414 
1415 #define RV_CLECTL_EXP_EN_DISABLE \
1416 	 RV(FV_CLECTL_EXP_EN_DISABLE, FB_CLECTL_EXP_EN)
1417 
1418 #define RV_CLECTL_LIMIT_EN_ENABLE \
1419 	 RV(FV_CLECTL_LIMIT_EN_ENABLE, FB_CLECTL_LIMIT_EN)
1420 
1421 #define RV_CLECTL_LIMIT_EN_DISABLE \
1422 	 RV(FV_CLECTL_LIMIT_EN_DISABLE, FB_CLECTL_LIMIT_EN)
1423 
1424 #define RV_CLECTL_COMP_EN_ENABLE \
1425 	 RV(FV_CLECTL_COMP_EN_ENABLE, FB_CLECTL_COMP_EN)
1426 
1427 #define RV_CLECTL_COMP_EN_DISABLE \
1428 	 RV(FV_CLECTL_COMP_EN_DISABLE, FB_CLECTL_COMP_EN)
1429 
1430 
1431 /*****************************
1432  *      R_MUGAIN (0x26)      *
1433  *****************************/
1434 
1435 /* Field Offsets */
1436 #define FB_MUGAIN_CLEMUG                     0
1437 
1438 /* Field Masks */
1439 #define FM_MUGAIN_CLEMUG                     0X1F
1440 
1441 /* Field Values */
1442 #define FV_MUGAIN_CLEMUG_46PT5DB             0x1F
1443 #define FV_MUGAIN_CLEMUG_0DB                 0x0
1444 
1445 /* Register Masks */
1446 #define RM_MUGAIN_CLEMUG \
1447 	 RM(FM_MUGAIN_CLEMUG, FB_MUGAIN_CLEMUG)
1448 
1449 
1450 /* Register Values */
1451 #define RV_MUGAIN_CLEMUG_46PT5DB \
1452 	 RV(FV_MUGAIN_CLEMUG_46PT5DB, FB_MUGAIN_CLEMUG)
1453 
1454 #define RV_MUGAIN_CLEMUG_0DB \
1455 	 RV(FV_MUGAIN_CLEMUG_0DB, FB_MUGAIN_CLEMUG)
1456 
1457 
1458 /*****************************
1459  *      R_COMPTH (0x27)      *
1460  *****************************/
1461 
1462 /* Field Offsets */
1463 #define FB_COMPTH                            0
1464 
1465 /* Field Masks */
1466 #define FM_COMPTH                            0XFF
1467 
1468 /* Field Values */
1469 #define FV_COMPTH_0DB                        0xFF
1470 #define FV_COMPTH_N95PT625DB                 0x0
1471 
1472 /* Register Masks */
1473 #define RM_COMPTH                            RM(FM_COMPTH, FB_COMPTH)
1474 
1475 /* Register Values */
1476 #define RV_COMPTH_0DB                        RV(FV_COMPTH_0DB, FB_COMPTH)
1477 #define RV_COMPTH_N95PT625DB \
1478 	 RV(FV_COMPTH_N95PT625DB, FB_COMPTH)
1479 
1480 
1481 /*****************************
1482  *      R_CMPRAT (0x28)      *
1483  *****************************/
1484 
1485 /* Field Offsets */
1486 #define FB_CMPRAT                            0
1487 
1488 /* Field Masks */
1489 #define FM_CMPRAT                            0X1F
1490 
1491 /* Register Masks */
1492 #define RM_CMPRAT                            RM(FM_CMPRAT, FB_CMPRAT)
1493 
1494 /******************************
1495  *      R_CATKTCL (0x29)      *
1496  ******************************/
1497 
1498 /* Field Offsets */
1499 #define FB_CATKTCL                           0
1500 
1501 /* Field Masks */
1502 #define FM_CATKTCL                           0XFF
1503 
1504 /* Register Masks */
1505 #define RM_CATKTCL                           RM(FM_CATKTCL, FB_CATKTCL)
1506 
1507 /******************************
1508  *      R_CATKTCH (0x2A)      *
1509  ******************************/
1510 
1511 /* Field Offsets */
1512 #define FB_CATKTCH                           0
1513 
1514 /* Field Masks */
1515 #define FM_CATKTCH                           0XFF
1516 
1517 /* Register Masks */
1518 #define RM_CATKTCH                           RM(FM_CATKTCH, FB_CATKTCH)
1519 
1520 /******************************
1521  *      R_CRELTCL (0x2B)      *
1522  ******************************/
1523 
1524 /* Field Offsets */
1525 #define FB_CRELTCL                           0
1526 
1527 /* Field Masks */
1528 #define FM_CRELTCL                           0XFF
1529 
1530 /* Register Masks */
1531 #define RM_CRELTCL                           RM(FM_CRELTCL, FB_CRELTCL)
1532 
1533 /******************************
1534  *      R_CRELTCH (0x2C)      *
1535  ******************************/
1536 
1537 /* Field Offsets */
1538 #define FB_CRELTCH                           0
1539 
1540 /* Field Masks */
1541 #define FM_CRELTCH                           0XFF
1542 
1543 /* Register Masks */
1544 #define RM_CRELTCH                           RM(FM_CRELTCH, FB_CRELTCH)
1545 
1546 /****************************
1547  *      R_LIMTH (0x2D)      *
1548  ****************************/
1549 
1550 /* Field Offsets */
1551 #define FB_LIMTH                             0
1552 
1553 /* Field Masks */
1554 #define FM_LIMTH                             0XFF
1555 
1556 /* Field Values */
1557 #define FV_LIMTH_0DB                         0xFF
1558 #define FV_LIMTH_N95PT625DB                  0x0
1559 
1560 /* Register Masks */
1561 #define RM_LIMTH                             RM(FM_LIMTH, FB_LIMTH)
1562 
1563 /* Register Values */
1564 #define RV_LIMTH_0DB                         RV(FV_LIMTH_0DB, FB_LIMTH)
1565 #define RV_LIMTH_N95PT625DB                  RV(FV_LIMTH_N95PT625DB, FB_LIMTH)
1566 
1567 /*****************************
1568  *      R_LIMTGT (0x2E)      *
1569  *****************************/
1570 
1571 /* Field Offsets */
1572 #define FB_LIMTGT                            0
1573 
1574 /* Field Masks */
1575 #define FM_LIMTGT                            0XFF
1576 
1577 /* Field Values */
1578 #define FV_LIMTGT_0DB                        0xFF
1579 #define FV_LIMTGT_N95PT625DB                 0x0
1580 
1581 /* Register Masks */
1582 #define RM_LIMTGT                            RM(FM_LIMTGT, FB_LIMTGT)
1583 
1584 /* Register Values */
1585 #define RV_LIMTGT_0DB                        RV(FV_LIMTGT_0DB, FB_LIMTGT)
1586 #define RV_LIMTGT_N95PT625DB \
1587 	 RV(FV_LIMTGT_N95PT625DB, FB_LIMTGT)
1588 
1589 
1590 /******************************
1591  *      R_LATKTCL (0x2F)      *
1592  ******************************/
1593 
1594 /* Field Offsets */
1595 #define FB_LATKTCL                           0
1596 
1597 /* Field Masks */
1598 #define FM_LATKTCL                           0XFF
1599 
1600 /* Register Masks */
1601 #define RM_LATKTCL                           RM(FM_LATKTCL, FB_LATKTCL)
1602 
1603 /******************************
1604  *      R_LATKTCH (0x30)      *
1605  ******************************/
1606 
1607 /* Field Offsets */
1608 #define FB_LATKTCH                           0
1609 
1610 /* Field Masks */
1611 #define FM_LATKTCH                           0XFF
1612 
1613 /* Register Masks */
1614 #define RM_LATKTCH                           RM(FM_LATKTCH, FB_LATKTCH)
1615 
1616 /******************************
1617  *      R_LRELTCL (0x31)      *
1618  ******************************/
1619 
1620 /* Field Offsets */
1621 #define FB_LRELTCL                           0
1622 
1623 /* Field Masks */
1624 #define FM_LRELTCL                           0XFF
1625 
1626 /* Register Masks */
1627 #define RM_LRELTCL                           RM(FM_LRELTCL, FB_LRELTCL)
1628 
1629 /******************************
1630  *      R_LRELTCH (0x32)      *
1631  ******************************/
1632 
1633 /* Field Offsets */
1634 #define FB_LRELTCH                           0
1635 
1636 /* Field Masks */
1637 #define FM_LRELTCH                           0XFF
1638 
1639 /* Register Masks */
1640 #define RM_LRELTCH                           RM(FM_LRELTCH, FB_LRELTCH)
1641 
1642 /****************************
1643  *      R_EXPTH (0x33)      *
1644  ****************************/
1645 
1646 /* Field Offsets */
1647 #define FB_EXPTH                             0
1648 
1649 /* Field Masks */
1650 #define FM_EXPTH                             0XFF
1651 
1652 /* Field Values */
1653 #define FV_EXPTH_0DB                         0xFF
1654 #define FV_EXPTH_N95PT625DB                  0x0
1655 
1656 /* Register Masks */
1657 #define RM_EXPTH                             RM(FM_EXPTH, FB_EXPTH)
1658 
1659 /* Register Values */
1660 #define RV_EXPTH_0DB                         RV(FV_EXPTH_0DB, FB_EXPTH)
1661 #define RV_EXPTH_N95PT625DB                  RV(FV_EXPTH_N95PT625DB, FB_EXPTH)
1662 
1663 /*****************************
1664  *      R_EXPRAT (0x34)      *
1665  *****************************/
1666 
1667 /* Field Offsets */
1668 #define FB_EXPRAT                            0
1669 
1670 /* Field Masks */
1671 #define FM_EXPRAT                            0X7
1672 
1673 /* Register Masks */
1674 #define RM_EXPRAT                            RM(FM_EXPRAT, FB_EXPRAT)
1675 
1676 /******************************
1677  *      R_XATKTCL (0x35)      *
1678  ******************************/
1679 
1680 /* Field Offsets */
1681 #define FB_XATKTCL                           0
1682 
1683 /* Field Masks */
1684 #define FM_XATKTCL                           0XFF
1685 
1686 /* Register Masks */
1687 #define RM_XATKTCL                           RM(FM_XATKTCL, FB_XATKTCL)
1688 
1689 /******************************
1690  *      R_XATKTCH (0x36)      *
1691  ******************************/
1692 
1693 /* Field Offsets */
1694 #define FB_XATKTCH                           0
1695 
1696 /* Field Masks */
1697 #define FM_XATKTCH                           0XFF
1698 
1699 /* Register Masks */
1700 #define RM_XATKTCH                           RM(FM_XATKTCH, FB_XATKTCH)
1701 
1702 /******************************
1703  *      R_XRELTCL (0x37)      *
1704  ******************************/
1705 
1706 /* Field Offsets */
1707 #define FB_XRELTCL                           0
1708 
1709 /* Field Masks */
1710 #define FM_XRELTCL                           0XFF
1711 
1712 /* Register Masks */
1713 #define RM_XRELTCL                           RM(FM_XRELTCL, FB_XRELTCL)
1714 
1715 /******************************
1716  *      R_XRELTCH (0x38)      *
1717  ******************************/
1718 
1719 /* Field Offsets */
1720 #define FB_XRELTCH                           0
1721 
1722 /* Field Masks */
1723 #define FM_XRELTCH                           0XFF
1724 
1725 /* Register Masks */
1726 #define RM_XRELTCH                           RM(FM_XRELTCH, FB_XRELTCH)
1727 
1728 /****************************
1729  *      R_FXCTL (0x39)      *
1730  ****************************/
1731 
1732 /* Field Offsets */
1733 #define FB_FXCTL_3DEN                        4
1734 #define FB_FXCTL_TEEN                        3
1735 #define FB_FXCTL_TNLFBYPASS                  2
1736 #define FB_FXCTL_BEEN                        1
1737 #define FB_FXCTL_BNLFBYPASS                  0
1738 
1739 /* Field Masks */
1740 #define FM_FXCTL_3DEN                        0X1
1741 #define FM_FXCTL_TEEN                        0X1
1742 #define FM_FXCTL_TNLFBYPASS                  0X1
1743 #define FM_FXCTL_BEEN                        0X1
1744 #define FM_FXCTL_BNLFBYPASS                  0X1
1745 
1746 /* Field Values */
1747 #define FV_FXCTL_3DEN_ENABLE                 0x1
1748 #define FV_FXCTL_3DEN_DISABLE                0x0
1749 #define FV_FXCTL_TEEN_ENABLE                 0x1
1750 #define FV_FXCTL_TEEN_DISABLE                0x0
1751 #define FV_FXCTL_TNLFBYPASS_ENABLE           0x1
1752 #define FV_FXCTL_TNLFBYPASS_DISABLE          0x0
1753 #define FV_FXCTL_BEEN_ENABLE                 0x1
1754 #define FV_FXCTL_BEEN_DISABLE                0x0
1755 #define FV_FXCTL_BNLFBYPASS_ENABLE           0x1
1756 #define FV_FXCTL_BNLFBYPASS_DISABLE          0x0
1757 
1758 /* Register Masks */
1759 #define RM_FXCTL_3DEN                        RM(FM_FXCTL_3DEN, FB_FXCTL_3DEN)
1760 #define RM_FXCTL_TEEN                        RM(FM_FXCTL_TEEN, FB_FXCTL_TEEN)
1761 #define RM_FXCTL_TNLFBYPASS \
1762 	 RM(FM_FXCTL_TNLFBYPASS, FB_FXCTL_TNLFBYPASS)
1763 
1764 #define RM_FXCTL_BEEN                        RM(FM_FXCTL_BEEN, FB_FXCTL_BEEN)
1765 #define RM_FXCTL_BNLFBYPASS \
1766 	 RM(FM_FXCTL_BNLFBYPASS, FB_FXCTL_BNLFBYPASS)
1767 
1768 
1769 /* Register Values */
1770 #define RV_FXCTL_3DEN_ENABLE \
1771 	 RV(FV_FXCTL_3DEN_ENABLE, FB_FXCTL_3DEN)
1772 
1773 #define RV_FXCTL_3DEN_DISABLE \
1774 	 RV(FV_FXCTL_3DEN_DISABLE, FB_FXCTL_3DEN)
1775 
1776 #define RV_FXCTL_TEEN_ENABLE \
1777 	 RV(FV_FXCTL_TEEN_ENABLE, FB_FXCTL_TEEN)
1778 
1779 #define RV_FXCTL_TEEN_DISABLE \
1780 	 RV(FV_FXCTL_TEEN_DISABLE, FB_FXCTL_TEEN)
1781 
1782 #define RV_FXCTL_TNLFBYPASS_ENABLE \
1783 	 RV(FV_FXCTL_TNLFBYPASS_ENABLE, FB_FXCTL_TNLFBYPASS)
1784 
1785 #define RV_FXCTL_TNLFBYPASS_DISABLE \
1786 	 RV(FV_FXCTL_TNLFBYPASS_DISABLE, FB_FXCTL_TNLFBYPASS)
1787 
1788 #define RV_FXCTL_BEEN_ENABLE \
1789 	 RV(FV_FXCTL_BEEN_ENABLE, FB_FXCTL_BEEN)
1790 
1791 #define RV_FXCTL_BEEN_DISABLE \
1792 	 RV(FV_FXCTL_BEEN_DISABLE, FB_FXCTL_BEEN)
1793 
1794 #define RV_FXCTL_BNLFBYPASS_ENABLE \
1795 	 RV(FV_FXCTL_BNLFBYPASS_ENABLE, FB_FXCTL_BNLFBYPASS)
1796 
1797 #define RV_FXCTL_BNLFBYPASS_DISABLE \
1798 	 RV(FV_FXCTL_BNLFBYPASS_DISABLE, FB_FXCTL_BNLFBYPASS)
1799 
1800 
1801 /*******************************
1802  *      R_DACCRWRL (0x3A)      *
1803  *******************************/
1804 
1805 /* Field Offsets */
1806 #define FB_DACCRWRL_DACCRWDL                 0
1807 
1808 /* Field Masks */
1809 #define FM_DACCRWRL_DACCRWDL                 0XFF
1810 
1811 /* Register Masks */
1812 #define RM_DACCRWRL_DACCRWDL \
1813 	 RM(FM_DACCRWRL_DACCRWDL, FB_DACCRWRL_DACCRWDL)
1814 
1815 
1816 /*******************************
1817  *      R_DACCRWRM (0x3B)      *
1818  *******************************/
1819 
1820 /* Field Offsets */
1821 #define FB_DACCRWRM_DACCRWDM                 0
1822 
1823 /* Field Masks */
1824 #define FM_DACCRWRM_DACCRWDM                 0XFF
1825 
1826 /* Register Masks */
1827 #define RM_DACCRWRM_DACCRWDM \
1828 	 RM(FM_DACCRWRM_DACCRWDM, FB_DACCRWRM_DACCRWDM)
1829 
1830 
1831 /*******************************
1832  *      R_DACCRWRH (0x3C)      *
1833  *******************************/
1834 
1835 /* Field Offsets */
1836 #define FB_DACCRWRH_DACCRWDH                 0
1837 
1838 /* Field Masks */
1839 #define FM_DACCRWRH_DACCRWDH                 0XFF
1840 
1841 /* Register Masks */
1842 #define RM_DACCRWRH_DACCRWDH \
1843 	 RM(FM_DACCRWRH_DACCRWDH, FB_DACCRWRH_DACCRWDH)
1844 
1845 
1846 /*******************************
1847  *      R_DACCRRDL (0x3D)      *
1848  *******************************/
1849 
1850 /* Field Offsets */
1851 #define FB_DACCRRDL                          0
1852 
1853 /* Field Masks */
1854 #define FM_DACCRRDL                          0XFF
1855 
1856 /* Register Masks */
1857 #define RM_DACCRRDL                          RM(FM_DACCRRDL, FB_DACCRRDL)
1858 
1859 /*******************************
1860  *      R_DACCRRDM (0x3E)      *
1861  *******************************/
1862 
1863 /* Field Offsets */
1864 #define FB_DACCRRDM                          0
1865 
1866 /* Field Masks */
1867 #define FM_DACCRRDM                          0XFF
1868 
1869 /* Register Masks */
1870 #define RM_DACCRRDM                          RM(FM_DACCRRDM, FB_DACCRRDM)
1871 
1872 /*******************************
1873  *      R_DACCRRDH (0x3F)      *
1874  *******************************/
1875 
1876 /* Field Offsets */
1877 #define FB_DACCRRDH                          0
1878 
1879 /* Field Masks */
1880 #define FM_DACCRRDH                          0XFF
1881 
1882 /* Register Masks */
1883 #define RM_DACCRRDH                          RM(FM_DACCRRDH, FB_DACCRRDH)
1884 
1885 /********************************
1886  *      R_DACCRADDR (0x40)      *
1887  ********************************/
1888 
1889 /* Field Offsets */
1890 #define FB_DACCRADDR_DACCRADD                0
1891 
1892 /* Field Masks */
1893 #define FM_DACCRADDR_DACCRADD                0XFF
1894 
1895 /* Register Masks */
1896 #define RM_DACCRADDR_DACCRADD \
1897 	 RM(FM_DACCRADDR_DACCRADD, FB_DACCRADDR_DACCRADD)
1898 
1899 
1900 /******************************
1901  *      R_DCOFSEL (0x41)      *
1902  ******************************/
1903 
1904 /* Field Offsets */
1905 #define FB_DCOFSEL_DC_COEF_SEL               0
1906 
1907 /* Field Masks */
1908 #define FM_DCOFSEL_DC_COEF_SEL               0X7
1909 
1910 /* Field Values */
1911 #define FV_DCOFSEL_DC_COEF_SEL_2_N8          0x0
1912 #define FV_DCOFSEL_DC_COEF_SEL_2_N9          0x1
1913 #define FV_DCOFSEL_DC_COEF_SEL_2_N10         0x2
1914 #define FV_DCOFSEL_DC_COEF_SEL_2_N11         0x3
1915 #define FV_DCOFSEL_DC_COEF_SEL_2_N12         0x4
1916 #define FV_DCOFSEL_DC_COEF_SEL_2_N13         0x5
1917 #define FV_DCOFSEL_DC_COEF_SEL_2_N14         0x6
1918 #define FV_DCOFSEL_DC_COEF_SEL_2_N15         0x7
1919 
1920 /* Register Masks */
1921 #define RM_DCOFSEL_DC_COEF_SEL \
1922 	 RM(FM_DCOFSEL_DC_COEF_SEL, FB_DCOFSEL_DC_COEF_SEL)
1923 
1924 
1925 /* Register Values */
1926 #define RV_DCOFSEL_DC_COEF_SEL_2_N8 \
1927 	 RV(FV_DCOFSEL_DC_COEF_SEL_2_N8, FB_DCOFSEL_DC_COEF_SEL)
1928 
1929 #define RV_DCOFSEL_DC_COEF_SEL_2_N9 \
1930 	 RV(FV_DCOFSEL_DC_COEF_SEL_2_N9, FB_DCOFSEL_DC_COEF_SEL)
1931 
1932 #define RV_DCOFSEL_DC_COEF_SEL_2_N10 \
1933 	 RV(FV_DCOFSEL_DC_COEF_SEL_2_N10, FB_DCOFSEL_DC_COEF_SEL)
1934 
1935 #define RV_DCOFSEL_DC_COEF_SEL_2_N11 \
1936 	 RV(FV_DCOFSEL_DC_COEF_SEL_2_N11, FB_DCOFSEL_DC_COEF_SEL)
1937 
1938 #define RV_DCOFSEL_DC_COEF_SEL_2_N12 \
1939 	 RV(FV_DCOFSEL_DC_COEF_SEL_2_N12, FB_DCOFSEL_DC_COEF_SEL)
1940 
1941 #define RV_DCOFSEL_DC_COEF_SEL_2_N13 \
1942 	 RV(FV_DCOFSEL_DC_COEF_SEL_2_N13, FB_DCOFSEL_DC_COEF_SEL)
1943 
1944 #define RV_DCOFSEL_DC_COEF_SEL_2_N14 \
1945 	 RV(FV_DCOFSEL_DC_COEF_SEL_2_N14, FB_DCOFSEL_DC_COEF_SEL)
1946 
1947 #define RV_DCOFSEL_DC_COEF_SEL_2_N15 \
1948 	 RV(FV_DCOFSEL_DC_COEF_SEL_2_N15, FB_DCOFSEL_DC_COEF_SEL)
1949 
1950 
1951 /******************************
1952  *      R_PLLCTL9 (0x4E)      *
1953  ******************************/
1954 
1955 /* Field Offsets */
1956 #define FB_PLLCTL9_REFDIV_PLL1               0
1957 
1958 /* Field Masks */
1959 #define FM_PLLCTL9_REFDIV_PLL1               0XFF
1960 
1961 /* Register Masks */
1962 #define RM_PLLCTL9_REFDIV_PLL1 \
1963 	 RM(FM_PLLCTL9_REFDIV_PLL1, FB_PLLCTL9_REFDIV_PLL1)
1964 
1965 
1966 /******************************
1967  *      R_PLLCTLA (0x4F)      *
1968  ******************************/
1969 
1970 /* Field Offsets */
1971 #define FB_PLLCTLA_OUTDIV_PLL1               0
1972 
1973 /* Field Masks */
1974 #define FM_PLLCTLA_OUTDIV_PLL1               0XFF
1975 
1976 /* Register Masks */
1977 #define RM_PLLCTLA_OUTDIV_PLL1 \
1978 	 RM(FM_PLLCTLA_OUTDIV_PLL1, FB_PLLCTLA_OUTDIV_PLL1)
1979 
1980 
1981 /******************************
1982  *      R_PLLCTLB (0x50)      *
1983  ******************************/
1984 
1985 /* Field Offsets */
1986 #define FB_PLLCTLB_FBDIV_PLL1L               0
1987 
1988 /* Field Masks */
1989 #define FM_PLLCTLB_FBDIV_PLL1L               0XFF
1990 
1991 /* Register Masks */
1992 #define RM_PLLCTLB_FBDIV_PLL1L \
1993 	 RM(FM_PLLCTLB_FBDIV_PLL1L, FB_PLLCTLB_FBDIV_PLL1L)
1994 
1995 
1996 /******************************
1997  *      R_PLLCTLC (0x51)      *
1998  ******************************/
1999 
2000 /* Field Offsets */
2001 #define FB_PLLCTLC_FBDIV_PLL1H               0
2002 
2003 /* Field Masks */
2004 #define FM_PLLCTLC_FBDIV_PLL1H               0X7
2005 
2006 /* Register Masks */
2007 #define RM_PLLCTLC_FBDIV_PLL1H \
2008 	 RM(FM_PLLCTLC_FBDIV_PLL1H, FB_PLLCTLC_FBDIV_PLL1H)
2009 
2010 
2011 /******************************
2012  *      R_PLLCTLD (0x52)      *
2013  ******************************/
2014 
2015 /* Field Offsets */
2016 #define FB_PLLCTLD_RZ_PLL1                   3
2017 #define FB_PLLCTLD_CP_PLL1                   0
2018 
2019 /* Field Masks */
2020 #define FM_PLLCTLD_RZ_PLL1                   0X7
2021 #define FM_PLLCTLD_CP_PLL1                   0X7
2022 
2023 /* Register Masks */
2024 #define RM_PLLCTLD_RZ_PLL1 \
2025 	 RM(FM_PLLCTLD_RZ_PLL1, FB_PLLCTLD_RZ_PLL1)
2026 
2027 #define RM_PLLCTLD_CP_PLL1 \
2028 	 RM(FM_PLLCTLD_CP_PLL1, FB_PLLCTLD_CP_PLL1)
2029 
2030 
2031 /******************************
2032  *      R_PLLCTLE (0x53)      *
2033  ******************************/
2034 
2035 /* Field Offsets */
2036 #define FB_PLLCTLE_REFDIV_PLL2               0
2037 
2038 /* Field Masks */
2039 #define FM_PLLCTLE_REFDIV_PLL2               0XFF
2040 
2041 /* Register Masks */
2042 #define RM_PLLCTLE_REFDIV_PLL2 \
2043 	 RM(FM_PLLCTLE_REFDIV_PLL2, FB_PLLCTLE_REFDIV_PLL2)
2044 
2045 
2046 /******************************
2047  *      R_PLLCTLF (0x54)      *
2048  ******************************/
2049 
2050 /* Field Offsets */
2051 #define FB_PLLCTLF_OUTDIV_PLL2               0
2052 
2053 /* Field Masks */
2054 #define FM_PLLCTLF_OUTDIV_PLL2               0XFF
2055 
2056 /* Register Masks */
2057 #define RM_PLLCTLF_OUTDIV_PLL2 \
2058 	 RM(FM_PLLCTLF_OUTDIV_PLL2, FB_PLLCTLF_OUTDIV_PLL2)
2059 
2060 
2061 /*******************************
2062  *      R_PLLCTL10 (0x55)      *
2063  *******************************/
2064 
2065 /* Field Offsets */
2066 #define FB_PLLCTL10_FBDIV_PLL2L              0
2067 
2068 /* Field Masks */
2069 #define FM_PLLCTL10_FBDIV_PLL2L              0XFF
2070 
2071 /* Register Masks */
2072 #define RM_PLLCTL10_FBDIV_PLL2L \
2073 	 RM(FM_PLLCTL10_FBDIV_PLL2L, FB_PLLCTL10_FBDIV_PLL2L)
2074 
2075 
2076 /*******************************
2077  *      R_PLLCTL11 (0x56)      *
2078  *******************************/
2079 
2080 /* Field Offsets */
2081 #define FB_PLLCTL11_FBDIV_PLL2H              0
2082 
2083 /* Field Masks */
2084 #define FM_PLLCTL11_FBDIV_PLL2H              0X7
2085 
2086 /* Register Masks */
2087 #define RM_PLLCTL11_FBDIV_PLL2H \
2088 	 RM(FM_PLLCTL11_FBDIV_PLL2H, FB_PLLCTL11_FBDIV_PLL2H)
2089 
2090 
2091 /*******************************
2092  *      R_PLLCTL12 (0x57)      *
2093  *******************************/
2094 
2095 /* Field Offsets */
2096 #define FB_PLLCTL12_RZ_PLL2                  3
2097 #define FB_PLLCTL12_CP_PLL2                  0
2098 
2099 /* Field Masks */
2100 #define FM_PLLCTL12_RZ_PLL2                  0X7
2101 #define FM_PLLCTL12_CP_PLL2                  0X7
2102 
2103 /* Register Masks */
2104 #define RM_PLLCTL12_RZ_PLL2 \
2105 	 RM(FM_PLLCTL12_RZ_PLL2, FB_PLLCTL12_RZ_PLL2)
2106 
2107 #define RM_PLLCTL12_CP_PLL2 \
2108 	 RM(FM_PLLCTL12_CP_PLL2, FB_PLLCTL12_CP_PLL2)
2109 
2110 
2111 /*******************************
2112  *      R_PLLCTL1B (0x60)      *
2113  *******************************/
2114 
2115 /* Field Offsets */
2116 #define FB_PLLCTL1B_VCOI_PLL2                4
2117 #define FB_PLLCTL1B_VCOI_PLL1                2
2118 
2119 /* Field Masks */
2120 #define FM_PLLCTL1B_VCOI_PLL2                0X3
2121 #define FM_PLLCTL1B_VCOI_PLL1                0X3
2122 
2123 /* Register Masks */
2124 #define RM_PLLCTL1B_VCOI_PLL2 \
2125 	 RM(FM_PLLCTL1B_VCOI_PLL2, FB_PLLCTL1B_VCOI_PLL2)
2126 
2127 #define RM_PLLCTL1B_VCOI_PLL1 \
2128 	 RM(FM_PLLCTL1B_VCOI_PLL1, FB_PLLCTL1B_VCOI_PLL1)
2129 
2130 
2131 /*******************************
2132  *      R_PLLCTL1C (0x61)      *
2133  *******************************/
2134 
2135 /* Field Offsets */
2136 #define FB_PLLCTL1C_PDB_PLL2                 2
2137 #define FB_PLLCTL1C_PDB_PLL1                 1
2138 
2139 /* Field Masks */
2140 #define FM_PLLCTL1C_PDB_PLL2                 0X1
2141 #define FM_PLLCTL1C_PDB_PLL1                 0X1
2142 
2143 /* Field Values */
2144 #define FV_PLLCTL1C_PDB_PLL2_ENABLE          0x1
2145 #define FV_PLLCTL1C_PDB_PLL2_DISABLE         0x0
2146 #define FV_PLLCTL1C_PDB_PLL1_ENABLE          0x1
2147 #define FV_PLLCTL1C_PDB_PLL1_DISABLE         0x0
2148 
2149 /* Register Masks */
2150 #define RM_PLLCTL1C_PDB_PLL2 \
2151 	 RM(FM_PLLCTL1C_PDB_PLL2, FB_PLLCTL1C_PDB_PLL2)
2152 
2153 #define RM_PLLCTL1C_PDB_PLL1 \
2154 	 RM(FM_PLLCTL1C_PDB_PLL1, FB_PLLCTL1C_PDB_PLL1)
2155 
2156 
2157 /* Register Values */
2158 #define RV_PLLCTL1C_PDB_PLL2_ENABLE \
2159 	 RV(FV_PLLCTL1C_PDB_PLL2_ENABLE, FB_PLLCTL1C_PDB_PLL2)
2160 
2161 #define RV_PLLCTL1C_PDB_PLL2_DISABLE \
2162 	 RV(FV_PLLCTL1C_PDB_PLL2_DISABLE, FB_PLLCTL1C_PDB_PLL2)
2163 
2164 #define RV_PLLCTL1C_PDB_PLL1_ENABLE \
2165 	 RV(FV_PLLCTL1C_PDB_PLL1_ENABLE, FB_PLLCTL1C_PDB_PLL1)
2166 
2167 #define RV_PLLCTL1C_PDB_PLL1_DISABLE \
2168 	 RV(FV_PLLCTL1C_PDB_PLL1_DISABLE, FB_PLLCTL1C_PDB_PLL1)
2169 
2170 
2171 /*******************************
2172  *      R_TIMEBASE (0x77)      *
2173  *******************************/
2174 
2175 /* Field Offsets */
2176 #define FB_TIMEBASE_DIVIDER                  0
2177 
2178 /* Field Masks */
2179 #define FM_TIMEBASE_DIVIDER                  0XFF
2180 
2181 /* Register Masks */
2182 #define RM_TIMEBASE_DIVIDER \
2183 	 RM(FM_TIMEBASE_DIVIDER, FB_TIMEBASE_DIVIDER)
2184 
2185 
2186 /*****************************
2187  *      R_DEVIDL (0x7D)      *
2188  *****************************/
2189 
2190 /* Field Offsets */
2191 #define FB_DEVIDL_DIDL                       0
2192 
2193 /* Field Masks */
2194 #define FM_DEVIDL_DIDL                       0XFF
2195 
2196 /* Register Masks */
2197 #define RM_DEVIDL_DIDL                       RM(FM_DEVIDL_DIDL, FB_DEVIDL_DIDL)
2198 
2199 /*****************************
2200  *      R_DEVIDH (0x7E)      *
2201  *****************************/
2202 
2203 /* Field Offsets */
2204 #define FB_DEVIDH_DIDH                       0
2205 
2206 /* Field Masks */
2207 #define FM_DEVIDH_DIDH                       0XFF
2208 
2209 /* Register Masks */
2210 #define RM_DEVIDH_DIDH                       RM(FM_DEVIDH_DIDH, FB_DEVIDH_DIDH)
2211 
2212 /****************************
2213  *      R_RESET (0x80)      *
2214  ****************************/
2215 
2216 /* Field Offsets */
2217 #define FB_RESET                             0
2218 
2219 /* Field Masks */
2220 #define FM_RESET                             0XFF
2221 
2222 /* Field Values */
2223 #define FV_RESET_ENABLE                      0x85
2224 
2225 /* Register Masks */
2226 #define RM_RESET                             RM(FM_RESET, FB_RESET)
2227 
2228 /* Register Values */
2229 #define RV_RESET_ENABLE                      RV(FV_RESET_ENABLE, FB_RESET)
2230 
2231 /********************************
2232  *      R_DACCRSTAT (0x8A)      *
2233  ********************************/
2234 
2235 /* Field Offsets */
2236 #define FB_DACCRSTAT_DACCR_BUSY              7
2237 
2238 /* Field Masks */
2239 #define FM_DACCRSTAT_DACCR_BUSY              0X1
2240 
2241 /* Register Masks */
2242 #define RM_DACCRSTAT_DACCR_BUSY \
2243 	 RM(FM_DACCRSTAT_DACCR_BUSY, FB_DACCRSTAT_DACCR_BUSY)
2244 
2245 
2246 /******************************
2247  *      R_PLLCTL0 (0x8E)      *
2248  ******************************/
2249 
2250 /* Field Offsets */
2251 #define FB_PLLCTL0_PLL2_LOCK                 1
2252 #define FB_PLLCTL0_PLL1_LOCK                 0
2253 
2254 /* Field Masks */
2255 #define FM_PLLCTL0_PLL2_LOCK                 0X1
2256 #define FM_PLLCTL0_PLL1_LOCK                 0X1
2257 
2258 /* Register Masks */
2259 #define RM_PLLCTL0_PLL2_LOCK \
2260 	 RM(FM_PLLCTL0_PLL2_LOCK, FB_PLLCTL0_PLL2_LOCK)
2261 
2262 #define RM_PLLCTL0_PLL1_LOCK \
2263 	 RM(FM_PLLCTL0_PLL1_LOCK, FB_PLLCTL0_PLL1_LOCK)
2264 
2265 
2266 /********************************
2267  *      R_PLLREFSEL (0x8F)      *
2268  ********************************/
2269 
2270 /* Field Offsets */
2271 #define FB_PLLREFSEL_PLL2_REF_SEL            4
2272 #define FB_PLLREFSEL_PLL1_REF_SEL            0
2273 
2274 /* Field Masks */
2275 #define FM_PLLREFSEL_PLL2_REF_SEL            0X7
2276 #define FM_PLLREFSEL_PLL1_REF_SEL            0X7
2277 
2278 /* Field Values */
2279 #define FV_PLLREFSEL_PLL2_REF_SEL_XTAL_MCLK1 0x0
2280 #define FV_PLLREFSEL_PLL2_REF_SEL_MCLK2      0x1
2281 #define FV_PLLREFSEL_PLL1_REF_SEL_XTAL_MCLK1 0x0
2282 #define FV_PLLREFSEL_PLL1_REF_SEL_MCLK2      0x1
2283 
2284 /* Register Masks */
2285 #define RM_PLLREFSEL_PLL2_REF_SEL \
2286 	 RM(FM_PLLREFSEL_PLL2_REF_SEL, FB_PLLREFSEL_PLL2_REF_SEL)
2287 
2288 #define RM_PLLREFSEL_PLL1_REF_SEL \
2289 	 RM(FM_PLLREFSEL_PLL1_REF_SEL, FB_PLLREFSEL_PLL1_REF_SEL)
2290 
2291 
2292 /* Register Values */
2293 #define RV_PLLREFSEL_PLL2_REF_SEL_XTAL_MCLK1 \
2294 	 RV(FV_PLLREFSEL_PLL2_REF_SEL_XTAL_MCLK1, FB_PLLREFSEL_PLL2_REF_SEL)
2295 
2296 #define RV_PLLREFSEL_PLL2_REF_SEL_MCLK2 \
2297 	 RV(FV_PLLREFSEL_PLL2_REF_SEL_MCLK2, FB_PLLREFSEL_PLL2_REF_SEL)
2298 
2299 #define RV_PLLREFSEL_PLL1_REF_SEL_XTAL_MCLK1 \
2300 	 RV(FV_PLLREFSEL_PLL1_REF_SEL_XTAL_MCLK1, FB_PLLREFSEL_PLL1_REF_SEL)
2301 
2302 #define RV_PLLREFSEL_PLL1_REF_SEL_MCLK2 \
2303 	 RV(FV_PLLREFSEL_PLL1_REF_SEL_MCLK2, FB_PLLREFSEL_PLL1_REF_SEL)
2304 
2305 
2306 /*******************************
2307  *      R_DACMBCEN (0xC7)      *
2308  *******************************/
2309 
2310 /* Field Offsets */
2311 #define FB_DACMBCEN_MBCEN3                   2
2312 #define FB_DACMBCEN_MBCEN2                   1
2313 #define FB_DACMBCEN_MBCEN1                   0
2314 
2315 /* Field Masks */
2316 #define FM_DACMBCEN_MBCEN3                   0X1
2317 #define FM_DACMBCEN_MBCEN2                   0X1
2318 #define FM_DACMBCEN_MBCEN1                   0X1
2319 
2320 /* Register Masks */
2321 #define RM_DACMBCEN_MBCEN3 \
2322 	 RM(FM_DACMBCEN_MBCEN3, FB_DACMBCEN_MBCEN3)
2323 
2324 #define RM_DACMBCEN_MBCEN2 \
2325 	 RM(FM_DACMBCEN_MBCEN2, FB_DACMBCEN_MBCEN2)
2326 
2327 #define RM_DACMBCEN_MBCEN1 \
2328 	 RM(FM_DACMBCEN_MBCEN1, FB_DACMBCEN_MBCEN1)
2329 
2330 
2331 /********************************
2332  *      R_DACMBCCTL (0xC8)      *
2333  ********************************/
2334 
2335 /* Field Offsets */
2336 #define FB_DACMBCCTL_LVLMODE3                5
2337 #define FB_DACMBCCTL_WINSEL3                 4
2338 #define FB_DACMBCCTL_LVLMODE2                3
2339 #define FB_DACMBCCTL_WINSEL2                 2
2340 #define FB_DACMBCCTL_LVLMODE1                1
2341 #define FB_DACMBCCTL_WINSEL1                 0
2342 
2343 /* Field Masks */
2344 #define FM_DACMBCCTL_LVLMODE3                0X1
2345 #define FM_DACMBCCTL_WINSEL3                 0X1
2346 #define FM_DACMBCCTL_LVLMODE2                0X1
2347 #define FM_DACMBCCTL_WINSEL2                 0X1
2348 #define FM_DACMBCCTL_LVLMODE1                0X1
2349 #define FM_DACMBCCTL_WINSEL1                 0X1
2350 
2351 /* Register Masks */
2352 #define RM_DACMBCCTL_LVLMODE3 \
2353 	 RM(FM_DACMBCCTL_LVLMODE3, FB_DACMBCCTL_LVLMODE3)
2354 
2355 #define RM_DACMBCCTL_WINSEL3 \
2356 	 RM(FM_DACMBCCTL_WINSEL3, FB_DACMBCCTL_WINSEL3)
2357 
2358 #define RM_DACMBCCTL_LVLMODE2 \
2359 	 RM(FM_DACMBCCTL_LVLMODE2, FB_DACMBCCTL_LVLMODE2)
2360 
2361 #define RM_DACMBCCTL_WINSEL2 \
2362 	 RM(FM_DACMBCCTL_WINSEL2, FB_DACMBCCTL_WINSEL2)
2363 
2364 #define RM_DACMBCCTL_LVLMODE1 \
2365 	 RM(FM_DACMBCCTL_LVLMODE1, FB_DACMBCCTL_LVLMODE1)
2366 
2367 #define RM_DACMBCCTL_WINSEL1 \
2368 	 RM(FM_DACMBCCTL_WINSEL1, FB_DACMBCCTL_WINSEL1)
2369 
2370 
2371 /*********************************
2372  *      R_DACMBCMUG1 (0xC9)      *
2373  *********************************/
2374 
2375 /* Field Offsets */
2376 #define FB_DACMBCMUG1_PHASE                  5
2377 #define FB_DACMBCMUG1_MUGAIN                 0
2378 
2379 /* Field Masks */
2380 #define FM_DACMBCMUG1_PHASE                  0X1
2381 #define FM_DACMBCMUG1_MUGAIN                 0X1F
2382 
2383 /* Register Masks */
2384 #define RM_DACMBCMUG1_PHASE \
2385 	 RM(FM_DACMBCMUG1_PHASE, FB_DACMBCMUG1_PHASE)
2386 
2387 #define RM_DACMBCMUG1_MUGAIN \
2388 	 RM(FM_DACMBCMUG1_MUGAIN, FB_DACMBCMUG1_MUGAIN)
2389 
2390 
2391 /*********************************
2392  *      R_DACMBCTHR1 (0xCA)      *
2393  *********************************/
2394 
2395 /* Field Offsets */
2396 #define FB_DACMBCTHR1_THRESH                 0
2397 
2398 /* Field Masks */
2399 #define FM_DACMBCTHR1_THRESH                 0XFF
2400 
2401 /* Register Masks */
2402 #define RM_DACMBCTHR1_THRESH \
2403 	 RM(FM_DACMBCTHR1_THRESH, FB_DACMBCTHR1_THRESH)
2404 
2405 
2406 /*********************************
2407  *      R_DACMBCRAT1 (0xCB)      *
2408  *********************************/
2409 
2410 /* Field Offsets */
2411 #define FB_DACMBCRAT1_RATIO                  0
2412 
2413 /* Field Masks */
2414 #define FM_DACMBCRAT1_RATIO                  0X1F
2415 
2416 /* Register Masks */
2417 #define RM_DACMBCRAT1_RATIO \
2418 	 RM(FM_DACMBCRAT1_RATIO, FB_DACMBCRAT1_RATIO)
2419 
2420 
2421 /**********************************
2422  *      R_DACMBCATK1L (0xCC)      *
2423  **********************************/
2424 
2425 /* Field Offsets */
2426 #define FB_DACMBCATK1L_TCATKL                0
2427 
2428 /* Field Masks */
2429 #define FM_DACMBCATK1L_TCATKL                0XFF
2430 
2431 /* Register Masks */
2432 #define RM_DACMBCATK1L_TCATKL \
2433 	 RM(FM_DACMBCATK1L_TCATKL, FB_DACMBCATK1L_TCATKL)
2434 
2435 
2436 /**********************************
2437  *      R_DACMBCATK1H (0xCD)      *
2438  **********************************/
2439 
2440 /* Field Offsets */
2441 #define FB_DACMBCATK1H_TCATKH                0
2442 
2443 /* Field Masks */
2444 #define FM_DACMBCATK1H_TCATKH                0XFF
2445 
2446 /* Register Masks */
2447 #define RM_DACMBCATK1H_TCATKH \
2448 	 RM(FM_DACMBCATK1H_TCATKH, FB_DACMBCATK1H_TCATKH)
2449 
2450 
2451 /**********************************
2452  *      R_DACMBCREL1L (0xCE)      *
2453  **********************************/
2454 
2455 /* Field Offsets */
2456 #define FB_DACMBCREL1L_TCRELL                0
2457 
2458 /* Field Masks */
2459 #define FM_DACMBCREL1L_TCRELL                0XFF
2460 
2461 /* Register Masks */
2462 #define RM_DACMBCREL1L_TCRELL \
2463 	 RM(FM_DACMBCREL1L_TCRELL, FB_DACMBCREL1L_TCRELL)
2464 
2465 
2466 /**********************************
2467  *      R_DACMBCREL1H (0xCF)      *
2468  **********************************/
2469 
2470 /* Field Offsets */
2471 #define FB_DACMBCREL1H_TCRELH                0
2472 
2473 /* Field Masks */
2474 #define FM_DACMBCREL1H_TCRELH                0XFF
2475 
2476 /* Register Masks */
2477 #define RM_DACMBCREL1H_TCRELH \
2478 	 RM(FM_DACMBCREL1H_TCRELH, FB_DACMBCREL1H_TCRELH)
2479 
2480 
2481 /*********************************
2482  *      R_DACMBCMUG2 (0xD0)      *
2483  *********************************/
2484 
2485 /* Field Offsets */
2486 #define FB_DACMBCMUG2_PHASE                  5
2487 #define FB_DACMBCMUG2_MUGAIN                 0
2488 
2489 /* Field Masks */
2490 #define FM_DACMBCMUG2_PHASE                  0X1
2491 #define FM_DACMBCMUG2_MUGAIN                 0X1F
2492 
2493 /* Register Masks */
2494 #define RM_DACMBCMUG2_PHASE \
2495 	 RM(FM_DACMBCMUG2_PHASE, FB_DACMBCMUG2_PHASE)
2496 
2497 #define RM_DACMBCMUG2_MUGAIN \
2498 	 RM(FM_DACMBCMUG2_MUGAIN, FB_DACMBCMUG2_MUGAIN)
2499 
2500 
2501 /*********************************
2502  *      R_DACMBCTHR2 (0xD1)      *
2503  *********************************/
2504 
2505 /* Field Offsets */
2506 #define FB_DACMBCTHR2_THRESH                 0
2507 
2508 /* Field Masks */
2509 #define FM_DACMBCTHR2_THRESH                 0XFF
2510 
2511 /* Register Masks */
2512 #define RM_DACMBCTHR2_THRESH \
2513 	 RM(FM_DACMBCTHR2_THRESH, FB_DACMBCTHR2_THRESH)
2514 
2515 
2516 /*********************************
2517  *      R_DACMBCRAT2 (0xD2)      *
2518  *********************************/
2519 
2520 /* Field Offsets */
2521 #define FB_DACMBCRAT2_RATIO                  0
2522 
2523 /* Field Masks */
2524 #define FM_DACMBCRAT2_RATIO                  0X1F
2525 
2526 /* Register Masks */
2527 #define RM_DACMBCRAT2_RATIO \
2528 	 RM(FM_DACMBCRAT2_RATIO, FB_DACMBCRAT2_RATIO)
2529 
2530 
2531 /**********************************
2532  *      R_DACMBCATK2L (0xD3)      *
2533  **********************************/
2534 
2535 /* Field Offsets */
2536 #define FB_DACMBCATK2L_TCATKL                0
2537 
2538 /* Field Masks */
2539 #define FM_DACMBCATK2L_TCATKL                0XFF
2540 
2541 /* Register Masks */
2542 #define RM_DACMBCATK2L_TCATKL \
2543 	 RM(FM_DACMBCATK2L_TCATKL, FB_DACMBCATK2L_TCATKL)
2544 
2545 
2546 /**********************************
2547  *      R_DACMBCATK2H (0xD4)      *
2548  **********************************/
2549 
2550 /* Field Offsets */
2551 #define FB_DACMBCATK2H_TCATKH                0
2552 
2553 /* Field Masks */
2554 #define FM_DACMBCATK2H_TCATKH                0XFF
2555 
2556 /* Register Masks */
2557 #define RM_DACMBCATK2H_TCATKH \
2558 	 RM(FM_DACMBCATK2H_TCATKH, FB_DACMBCATK2H_TCATKH)
2559 
2560 
2561 /**********************************
2562  *      R_DACMBCREL2L (0xD5)      *
2563  **********************************/
2564 
2565 /* Field Offsets */
2566 #define FB_DACMBCREL2L_TCRELL                0
2567 
2568 /* Field Masks */
2569 #define FM_DACMBCREL2L_TCRELL                0XFF
2570 
2571 /* Register Masks */
2572 #define RM_DACMBCREL2L_TCRELL \
2573 	 RM(FM_DACMBCREL2L_TCRELL, FB_DACMBCREL2L_TCRELL)
2574 
2575 
2576 /**********************************
2577  *      R_DACMBCREL2H (0xD6)      *
2578  **********************************/
2579 
2580 /* Field Offsets */
2581 #define FB_DACMBCREL2H_TCRELH                0
2582 
2583 /* Field Masks */
2584 #define FM_DACMBCREL2H_TCRELH                0XFF
2585 
2586 /* Register Masks */
2587 #define RM_DACMBCREL2H_TCRELH \
2588 	 RM(FM_DACMBCREL2H_TCRELH, FB_DACMBCREL2H_TCRELH)
2589 
2590 
2591 /*********************************
2592  *      R_DACMBCMUG3 (0xD7)      *
2593  *********************************/
2594 
2595 /* Field Offsets */
2596 #define FB_DACMBCMUG3_PHASE                  5
2597 #define FB_DACMBCMUG3_MUGAIN                 0
2598 
2599 /* Field Masks */
2600 #define FM_DACMBCMUG3_PHASE                  0X1
2601 #define FM_DACMBCMUG3_MUGAIN                 0X1F
2602 
2603 /* Register Masks */
2604 #define RM_DACMBCMUG3_PHASE \
2605 	 RM(FM_DACMBCMUG3_PHASE, FB_DACMBCMUG3_PHASE)
2606 
2607 #define RM_DACMBCMUG3_MUGAIN \
2608 	 RM(FM_DACMBCMUG3_MUGAIN, FB_DACMBCMUG3_MUGAIN)
2609 
2610 
2611 /*********************************
2612  *      R_DACMBCTHR3 (0xD8)      *
2613  *********************************/
2614 
2615 /* Field Offsets */
2616 #define FB_DACMBCTHR3_THRESH                 0
2617 
2618 /* Field Masks */
2619 #define FM_DACMBCTHR3_THRESH                 0XFF
2620 
2621 /* Register Masks */
2622 #define RM_DACMBCTHR3_THRESH \
2623 	 RM(FM_DACMBCTHR3_THRESH, FB_DACMBCTHR3_THRESH)
2624 
2625 
2626 /*********************************
2627  *      R_DACMBCRAT3 (0xD9)      *
2628  *********************************/
2629 
2630 /* Field Offsets */
2631 #define FB_DACMBCRAT3_RATIO                  0
2632 
2633 /* Field Masks */
2634 #define FM_DACMBCRAT3_RATIO                  0X1F
2635 
2636 /* Register Masks */
2637 #define RM_DACMBCRAT3_RATIO \
2638 	 RM(FM_DACMBCRAT3_RATIO, FB_DACMBCRAT3_RATIO)
2639 
2640 
2641 /**********************************
2642  *      R_DACMBCATK3L (0xDA)      *
2643  **********************************/
2644 
2645 /* Field Offsets */
2646 #define FB_DACMBCATK3L_TCATKL                0
2647 
2648 /* Field Masks */
2649 #define FM_DACMBCATK3L_TCATKL                0XFF
2650 
2651 /* Register Masks */
2652 #define RM_DACMBCATK3L_TCATKL \
2653 	 RM(FM_DACMBCATK3L_TCATKL, FB_DACMBCATK3L_TCATKL)
2654 
2655 
2656 /**********************************
2657  *      R_DACMBCATK3H (0xDB)      *
2658  **********************************/
2659 
2660 /* Field Offsets */
2661 #define FB_DACMBCATK3H_TCATKH                0
2662 
2663 /* Field Masks */
2664 #define FM_DACMBCATK3H_TCATKH                0XFF
2665 
2666 /* Register Masks */
2667 #define RM_DACMBCATK3H_TCATKH \
2668 	 RM(FM_DACMBCATK3H_TCATKH, FB_DACMBCATK3H_TCATKH)
2669 
2670 
2671 /**********************************
2672  *      R_DACMBCREL3L (0xDC)      *
2673  **********************************/
2674 
2675 /* Field Offsets */
2676 #define FB_DACMBCREL3L_TCRELL                0
2677 
2678 /* Field Masks */
2679 #define FM_DACMBCREL3L_TCRELL                0XFF
2680 
2681 /* Register Masks */
2682 #define RM_DACMBCREL3L_TCRELL \
2683 	 RM(FM_DACMBCREL3L_TCRELL, FB_DACMBCREL3L_TCRELL)
2684 
2685 
2686 /**********************************
2687  *      R_DACMBCREL3H (0xDD)      *
2688  **********************************/
2689 
2690 /* Field Offsets */
2691 #define FB_DACMBCREL3H_TCRELH                0
2692 
2693 /* Field Masks */
2694 #define FM_DACMBCREL3H_TCRELH                0XFF
2695 
2696 /* Register Masks */
2697 #define RM_DACMBCREL3H_TCRELH \
2698 	 RM(FM_DACMBCREL3H_TCRELH, FB_DACMBCREL3H_TCRELH)
2699 
2700 
2701 #endif /* __WOOKIE_H__ */
2702